<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S12 / MagniV MicrocontrollersのトピックRe: Memory mapping of XGATE</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935954#M16589</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;XGATE sees memory little different than S12X. Up to 32kB of RAM is available at 0x8000..0xFFFF (from XGATE point of view), peripherals registers the same like S12X 0x0..0x7FF, flash page 0xE0 at 0x800..0x3FFF, flash page 0xE1 at 0x4000..0x7FFF. XGATE memory is not paged, RPAGE, PPAGE don't affect in any way what XGATE sees at given address. XGATE RAM addresses 0x8000..0xFFFF correspond to global address 0xF_8000..0xF_FFFF. XGATE RAM addresses 0x8000..0x8FFF corresponds&amp;nbsp;to S12X RPAGE=0xF8, 0x9000..0x9FFF - RPAGE=0xF9, 0xA000..0xAFFF - RPAGE=0xFA and so on.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 04 Jul 2019 06:29:37 GMT</pubDate>
    <dc:creator>kef2</dc:creator>
    <dc:date>2019-07-04T06:29:37Z</dc:date>
    <item>
      <title>Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935951#M16586</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;My MCU is S12XEQ.&lt;/P&gt;&lt;P&gt;In the official project "Simple SCI" from AN3144,i get functions address in the map file:&lt;/P&gt;&lt;P&gt;main : 0xFE8016&lt;/P&gt;&lt;P&gt;SCI_Thread : 0xFB12C4&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Accordding to the datasheet,Flash paged window range from 0x8000~0xBFFF,so the paged address should look like 0xXX8000~0xXXBFFF,just like the address of function main().&lt;/P&gt;&lt;P&gt;why does&amp;nbsp;the address of function SCI_Thread() get be 0xFB12C4,although it's a XGATE Thread.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 03 Jul 2019 08:15:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935951#M16586</guid>
      <dc:creator>everkimage</dc:creator>
      <dc:date>2019-07-03T08:15:09Z</dc:date>
    </item>
    <item>
      <title>Re: Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935952#M16587</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The vector value is 0xB2C4 and the actuall execution address is 0xB2C4 too.&lt;/P&gt;&lt;P&gt;But why does it get be&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;0xFB12C4 in the map file.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 03 Jul 2019 08:24:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935952#M16587</guid>
      <dc:creator>everkimage</dc:creator>
      <dc:date>2019-07-03T08:24:33Z</dc:date>
    </item>
    <item>
      <title>Re: Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935953#M16588</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;ok~,XGATE_CODE segment is putted into RAM page FB,FC,and RAM window ranges from 0x1000~0x1FFF(4KB),so 0xFB12C4 is right.&lt;/P&gt;&lt;P&gt;But in the simulator,PC value of XGATE is 0xB2C4(so with vector value) while execute the &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;function SCI_Thread() &lt;/SPAN&gt;,why?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 03 Jul 2019 08:59:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935953#M16588</guid>
      <dc:creator>everkimage</dc:creator>
      <dc:date>2019-07-03T08:59:41Z</dc:date>
    </item>
    <item>
      <title>Re: Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935954#M16589</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;XGATE sees memory little different than S12X. Up to 32kB of RAM is available at 0x8000..0xFFFF (from XGATE point of view), peripherals registers the same like S12X 0x0..0x7FF, flash page 0xE0 at 0x800..0x3FFF, flash page 0xE1 at 0x4000..0x7FFF. XGATE memory is not paged, RPAGE, PPAGE don't affect in any way what XGATE sees at given address. XGATE RAM addresses 0x8000..0xFFFF correspond to global address 0xF_8000..0xF_FFFF. XGATE RAM addresses 0x8000..0x8FFF corresponds&amp;nbsp;to S12X RPAGE=0xF8, 0x9000..0x9FFF - RPAGE=0xF9, 0xA000..0xAFFF - RPAGE=0xFA and so on.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jul 2019 06:29:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935954#M16589</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2019-07-04T06:29:37Z</dc:date>
    </item>
    <item>
      <title>Re: Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935955#M16590</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you very much.&lt;/P&gt;&lt;P&gt;As you said,0xFB12C4 means RPAGE = 0xFB,and the offset is 0x12C4,minus the RAM window range start address 0x1000,the offset is 0x02C4.So in the XGATE,the address of SCI_Thread is 0xB2C4.Is it right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If XGETE thread is put into a paged flash,whileit is executed,there is no affect to PPAGE.Is it right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And which pdf file can i find the knowledge about XGATE memory map?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jul 2019 07:06:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935955#M16590</guid>
      <dc:creator>everkimage</dc:creator>
      <dc:date>2019-07-04T07:06:53Z</dc:date>
    </item>
    <item>
      <title>Re: Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935956#M16591</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;right.&lt;/P&gt;&lt;P&gt;right.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;See S12XE RM Figure 1-3. XGATE Global Address Mapping&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jul 2019 12:09:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935956#M16591</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2019-07-04T12:09:35Z</dc:date>
    </item>
    <item>
      <title>Re: Memory mapping of XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935957#M16592</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Everk,&lt;/P&gt;&lt;P&gt;you may also use the attached S12XE memory map in excel file for your reference.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope it helps you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Radek&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 13 Aug 2019 14:55:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Memory-mapping-of-XGATE/m-p/935957#M16592</guid>
      <dc:creator>RadekS</dc:creator>
      <dc:date>2019-08-13T14:55:39Z</dc:date>
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  </channel>
</rss>

