S12 / MagniV MicrocontrollersのトピックPLL Question

PLL Question

lssuer — Tue, 11 Apr 2006 11:36:45 GMT

I am using the MC9S12DP256B microcontroller and I have written a routine to utilize the phase loop lock feature. Every time I run the debugger in codewarrior my program goes into the clock monitor fail reset.

The code that I have written is as follows:

void SetClkSpeed20(void)
{
//multiply 4MHz by 2 by 5/1 to get 40MHz for the PLL
//or a bus clk of 20 MHz
SYNR=4;//+1
REFDV=0;//+1
while (!(CRGFLG_LOCK)) ;//wait for PLL lock
CLKSEL_PLLSEL=1; //engage PLL
}

I am also using SPI in this program, is there an issue with using both SPI and PLL that would cause the clock monitor fail reset or could I be missing something in my PLL routine that is causing the clock monitor fail reset. Any advice or insight into this interrupt or problem would be appreciated.

Thanks,
Lssuer

Re: PLL Question

gautier — Tue, 11 Apr 2006 14:35:16 GMT

hello,

I have the same problembut with SCI port.

After some research I have found the EB614/D

it's detail that some componant have a problem.

look at this bulletin, perhaps it can help you.

it's in attachement part.

excuse me for spelling mistake I'm French.

good luck!

ErrataSCIinterrupt.pdf

Message Edited by t.dowe on 2009-10-21 12:20 AM

Re: PLL Question

domi2c — Fri, 14 Apr 2006 04:03:53 GMT

Hello,

I'm also using a MC9S12DP256B on Dragon12 and MiniDragon. The two have a bus speed of 8MHz with a cristal at 16 MHz. And I've had to create a little function to run my boards at 24MHz when not using D-Bug12.

I'm not using codewarrior but the ICC12 compiler, and here is my function and it works fine :

void set_pll(void)

{

ClearBit(CLKSEL,0x80);

SetBit(PLLCTL,0x40);

SYNR = 0x05;

REFDV = 0x03;

{

;

} while (TestBit(CRGFLG,0x08) == 0);

SetBit(CLKSEL,0x80);

}

I think the 2 first and bold lines are missing in your code.

hope this helps

Jean Claude

Re: PLL Question

pittbull — Sat, 15 Apr 2006 04:42:39 GMT

Hi Issuer,
I'm not sure if this happens if your SYNR or REFDV values are wrong but I had a similar problem when the oscillator was down. If the osc. is not running, the MCU uses 'self-clocking' and thus you can't activate the PLL.

Re: PLL Question

MO_84 — Thu, 13 Jan 2011 04:41:09 GMT

I had a similar problem with the Dragon 12 Plus board.

When you switch from LOAD mode to RUN mode, the clock frequency changes from 24MHz to 4MHz. This was messing up a lot of my Calculations. I used the PLL and it works fine now.

PLLCLK = 8*2*6/2 = 48MHz
The bus speed = PLLCLK / 2 = 24 MHz

Here is code. Its very similar to the ones above:

void Set_Clock(void)
{
    CLKSEL &= 0x7F;
    PLLCTL |= 0x40;
    SYNR = 0x05;
    REFDV = 0x01;
    while(!(0x08 & CRGFLG));
    CLKSEL |= 0x80;
}

You can also find a description of what all the above registers do at the link beow under the Clock and Reset Generator section.

http://cache.freescale.com/files/microcontrollers/doc/data_sheet/MC9S12DP256.pdf?fsrch=1&WT_TYPE=Data%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=1

Hope this helps someone.