topic Re: RSIs1() in Processor Expert in S12 / MagniV Microcontrollers

RSIs1() in Processor Expert

aaronlee — Thu, 11 Apr 2019 09:58:51 GMT

Hi,

We are using S12ZVCA & Processor Expert(CodeWarrior 11.0.1). And we are setting RSIs1 to trigger a ISR per 1ms.

How to increase variable "i" per 1ms in main()?

main()
{
uint16_t i;
i++; // when ISR(RTIs1_Interrupt) is trigger
}

RSIs1.c (Manage by Processor Expert)

/*
** ===================================================================
** Method : RTIs1_Interrupt (component RTIshared)
**
** Description :
** The method services the interrupt of the selected peripheral(s)
** and eventually invokes the components event(s).
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
#pragma CODE_SEG __NEAR_SEG NON_BANKED
ISR(RTIs1_Interrupt)
{
TIM1TFLG1 = 0x01U; /* Reset interrupt request flag */
TIM1TC0 += 0xFA00U; /* Add value corresponding with period */
/* Warning: This component is not used by any other component! */
}
#pragma CODE_SEG RTIs1_CODE
/* END RTIs1. */

I have been add code "i++;" to ISR(RTIs1_Interrupt). But "i++;" disappear when i regenerate the PROCESSOR EXPERT CODE.

Do you have any recommend?

Best Regards,

Aaron

Re: RSIs1() in Processor Expert

dianabatrlova — Tue, 16 Apr 2019 11:04:02 GMT

Hi Aaron,

I would like to apologize for the delay.

I assume you are using RTIshared component.

Can you share your settings of this component?

When I generate code with default settings I can see that there is a counter

RTIs1_Cnt++; in the interrupt routine. I assume you can use it instead of your own variable "i".

#pragma CODE_SEG __NEAR_SEG NON_BANKED
ISR(RTIs1_Interrupt)
{
TIM0TFLG1 = 0x02U; /* Reset interrupt request flag */
RTIs1_Cnt++; /* Increment SW counter RTIs1_Cnt */
if (RTIs1_Cnt == 0xFAU) { /* Is it now the period time? */
RTIs1_Cnt = 0x00U; /* Reset SW counter RTIs1_Cnt */
/* * */
/* Warning: This component is not used by any other component! */
/* * */
}
}
#pragma CODE_SEG RTIs1_CODE

I hope it helps.

Best Regards,

Diana

Re: RSIs1() in Processor Expert

aaronlee — Fri, 19 Apr 2019 16:08:17 GMT

Hi Diana,

We are using RTIshared component. But I don't know why our ISR(RTIs1_Interrupt) is different from yours.

Best Regards,

Aaron

Re: RSIs1() in Processor Expert

dianabatrlova — Tue, 23 Apr 2019 07:54:13 GMT

Hello Aaron,

I attached my project with the same settings as yours in CW 11.1. Could you please check it?

I hope it helps.

Best Regards,

Diana