S12 / MagniV MicrocontrollersのトピックS12ZVM_CAN ISR(Cpu_Interrupt)

S12ZVM_CAN ISR(Cpu_Interrupt)

18647340486 — Fri, 15 Feb 2019 09:05:38 GMT

Dear all,

There was a problem when I implemented an interrupt handler. As shown below.

__interrupt void INT_STATUS(void){
byte Status = CAN0RFLG; /* Read the status register */

if((Status & CAN_STATUS_BOFF_MASK) == CAN_STATUS_BOFF_MASK) { /* Bus-Off state */
   ErrFlag |= CAN_STATUS_BOFF_EXT_MASK;
   ErrFlag |= (Status & 0x83U);       /* Add error flags */
}
else {
   ErrFlag |= (Status & 0xBFU);       /* Add error flags */
}
CAN0RFLG = 0xFEU;                    /* Reset error flags */
if ((Status & CAN_STATUS_BOFF_MASK) == CAN_STATUS_BOFF_MASK) { /* Is busoff error detected? */
   CAN1_OnBusOff();                   /* If yes then invoke user method */
}
CAN0RFLG = CAN0RFLG_CSCIF_MASK;

}

The CPU generated an error interrupt while implementing the above interrupt function.As shown below.

ISR(Cpu_Interrupt)
{
/*lint -save -e950 Disable MISRA rule (1.1) checking. */
asm(BGND);
/*lint -restore Enable MISRA rule (1.1) checking. */
}

I didn't find the problem point.

I need your help.

Thanks.

Re: S12ZVM_CAN ISR(Cpu_Interrupt)

dianabatrlova — Mon, 18 Feb 2019 10:12:32 GMT

Hi,

The Processor expert function ISR(Cpu_Interrupt) is called from each unimplemented interrupt to catch the unexpected
event. The example below can be useful to identify the unimplemented interrupt.

S12Z Interrupt catcher for unexpected interrupts

Could you please check the "3.3.2.2 Error Code Register (MMCECH, MMCECL)"?

Also, in the RM rev. 2.11 in the section "13.3.2.5 MSCAN Receiver Flag Register (CANRFLG)" we can see that RSTAT[1:0] and TSTAT[1:0] flags are read-only.

I hope it helps you.

Best Regards,

Diana

Re: S12ZVM_CAN ISR(Cpu_Interrupt)

18647340486 — Mon, 18 Feb 2019 10:43:17 GMT

Hi,

This problem has been solved . The reason is that one of interrupts was not complete.Thank you for you help.

Best Regards,

Katherine