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    <title>S12 / MagniV Microcontrollers中的主题 Re: S12ZVML gate drive ability</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVML-gate-drive-ability/m-p/809753#M15806</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;The RM specifies only the typical total gate charge, depending on device 75nC (GDU v4 and v6) and 50nC (GDU v5).&amp;nbsp;&lt;/P&gt;&lt;P&gt;As the Table E-1 footnote 5 states,&amp;nbsp;the total gate charge spec is only a recommendation. FETs with higher gate charge can be used when resulting slew rates are&amp;nbsp;tolerable by the application and resulting power dissipation does not lead to thermal overload.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 23 Oct 2018 19:39:39 GMT</pubDate>
    <dc:creator>danielmartynek</dc:creator>
    <dc:date>2018-10-23T19:39:39Z</dc:date>
    <item>
      <title>S12ZVML gate drive ability</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVML-gate-drive-ability/m-p/809752#M15805</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear&amp;nbsp;matej:&lt;/P&gt;&lt;P&gt;I want to ask a question, how much s12zvml&amp;nbsp;MCU gate drive ability is ? for example,&lt;/P&gt;&lt;P&gt;I choose a mosfet , from the datasheet , I know the total gate charge is 93nc.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can s12zvml&amp;nbsp;MCU drive this mosfet very well ? or how should I choose the mosfet according&amp;nbsp;&lt;/P&gt;&lt;P&gt;to the s12zvm max gate drive ability?&amp;nbsp;&lt;/P&gt;&lt;P&gt;best regards.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 19 Oct 2018 06:55:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVML-gate-drive-ability/m-p/809752#M15805</guid>
      <dc:creator>dmeng1</dc:creator>
      <dc:date>2018-10-19T06:55:13Z</dc:date>
    </item>
    <item>
      <title>Re: S12ZVML gate drive ability</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVML-gate-drive-ability/m-p/809753#M15806</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;The RM specifies only the typical total gate charge, depending on device 75nC (GDU v4 and v6) and 50nC (GDU v5).&amp;nbsp;&lt;/P&gt;&lt;P&gt;As the Table E-1 footnote 5 states,&amp;nbsp;the total gate charge spec is only a recommendation. FETs with higher gate charge can be used when resulting slew rates are&amp;nbsp;tolerable by the application and resulting power dissipation does not lead to thermal overload.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Oct 2018 19:39:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVML-gate-drive-ability/m-p/809753#M15806</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2018-10-23T19:39:39Z</dc:date>
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