SWI AND SYS TEST

rajesh057 — Thu, 26 Jul 2018 05:26:33 GMT

I am using s12zvc controller I would like to check interrupt like SWI AND SYS .is their any way to test this two .I would like to test this 2 interrupts at starting stage middle and end of my code .any already existing package avail to check.

thanks for helping

Rajesh kota

Re: SWI AND SYS TEST

dianabatrlova — Tue, 31 Jul 2018 13:07:07 GMT

Hi Rajesh,

As I know we have no a package for the check SWI and SYS interrupts.

Let me introduce you to the SWI and SYS interrupts.

For related information see page 293 and 294

https://www.nxp.com/docs/en/reference-manual/S12ZCPU_RM_V1.pdf

The opcode of SWI instruction is 0xFF whereas SYS instruction is 0x1B07 (this is the machine code).
So, whenever the CPU is trying to execute code from an erased memory location (0xFF), SWI instruction will be called.
The SYS instruction is similar to the SWI instruction (It clears U bit, the return address is the subsequent instruction after SWI/SYS…) except for different opcode (it will be called when the CPU executes 0x1B07) and it fetches a different vector – SYS vector, not SWI vector.

I hope the information is helpful.

Best regards,

Diana

S12 / MagniV MicrocontrollersのトピックSWI AND SYS TEST

SWI AND SYS TEST

Re: SWI AND SYS TEST