topic Re: Forceful commutation hampering ADC0 Conversion done(50 usec) ISR. in S12 / MagniV Microcontrollers

Forceful commutation hampering ADC0 Conversion done(50 usec) ISR.

pratibhasurabhi — Tue, 27 Feb 2018 06:33:37 GMT

Hi all,

I was performing a PoC on the NXP MTRCKTSBNZVM128 Kit for motor rotation using Hall sensor 120 commutation algorithm.

During the course of PoC i found out that the whenever forceful commutation(TIM0CFORC_FOC0 = 1 ) is performed( say in APP_STOP) when motor is idle,it affects the ADC0 conversion done ISR (50 usec ISR).

Can someone please explain as to why this occurs.

Thank you.

Re: Forceful commutation hampering ADC0 Conversion done(50 usec) ISR.

pachamatej — Wed, 28 Feb 2018 16:52:26 GMT

Hello,

could you please be more specific on what does the PoC mean? And also what means that "it affects the ADC0 conversion done ISR"?

Thank you,

Matej

Re: Forceful commutation hampering ADC0 Conversion done(50 usec) ISR.

pratibhasurabhi — Thu, 01 Mar 2018 06:04:23 GMT

Hi Matej,

PoC- Proof of Concept..i was trying with the Hall sensor 120 degree sample code to understand the sample codes' functionality on the starter kit

When i say it affects the ADC0 conversion ISR i mean the ISR is skipped.It does not come at a regular interval of 50 usec(as expected),but after every 100 or say 115 usec.

In the sample code the following chunk of code is present in the AppInit function :

// Load 0% duty cycle
dutyCycle = 0;
// Select commutation sector (all transistors OFF)
cmtSector = 6;

// Select pattern
PMFCFG2 = 0x40 + MaskVal[cmtSector];
PMFOUTC_OUTCTL = OutCtl[cmtSector];
// TIM ch0 output toggle on compare to force commutation
TIM0TCTL2_OL0 = 1;
TIM0TCTL2_OM0 = 0;
// Force commutation (apply PMF MASK/Control configuration)
TIM0CFORC_FOC0 = 1;
// Disable TIM ch0 output compare action to do not generate
// force commutation (async_event), when TIM counter TCNT reaches value 0
TIM0TCTL2_OL0 = 0;
TIM0TCTL2_OM0 = 0;

//Load duty cycle
PMFVAL0 = dutyCycle;
// Switch list when next reload event (apply PWM duty cycle)
PTUC_PTULDOK = 1;

If the same chunk is added to AppStop ,then the ADC0done_ISR interrupt interval which is of 50usec is affected.(it is skipped).Comes after 100usec.

So what I cannot understand is how adding this particular chunk of code in which forceful commutation is performed( TIM0CFORC_FOC0 = 1; ) affects the above said ISR.

Thank you!

Re: Forceful commutation hampering ADC0 Conversion done(50 usec) ISR.

pachamatej — Mon, 05 Mar 2018 07:55:10 GMT

Hi,

The reason would be the timing of the application.

If the code is presented in the AppInit function, it is probably called just once. Actually, if I download the Hall-sensor-based application from the NXP web, I can see the "TIM0CFORC_FOC0 = 1;" only in the transition functions, thus also called once between two states (e.g. in "void AppStopToAlignment(void)" ). The only exception is forcing the commutation in the timer event "TIMchan1_ISR".

In contrast to that, you have placed the code in the AppStop state, which is a function called within the main "while" loop, thus called over and over, with no time span in between. Since there is also the PTUC_PTULDOK = 1 command, I can imagine the ADC is being restarted so many times that it can skip some conversions.

Actually, with the lates package available at the NXP web, I can place your code in the AppStop and I still see the ADC interrupt being called every 50 us. However, the motor will not run since your code makes changes not compatible with the rest of the code.

Personally, I can see no benefit in placing the whole code into the AppStop state. If you are about to implement the in-speed start-up, the Hall sensors interface should be used to detect the speed.

I hope I have explained it at least a bit.

Best regards,

Matej

Re: Forceful commutation hampering ADC0 Conversion done(50 usec) ISR.

pratibhasurabhi — Mon, 05 Mar 2018 13:05:47 GMT

Hi Matej,

Thank you for the explanation provided.

So do you mean to say the combination of forceful commutation occurring over and over again (while loop ) and the bit PTULDOK being set might be the reason behind the ADC ISR being skipped.Is my undersatnding correct.

Also in your reply you have mention in the Hall Sensor based application from the NXP web,you found the FOC0 set only in transition function (AppStopToAlignment)

The sample code which is present with me does not have any transition function.

As per my knowledge the BEMF sample code has the AppStopToAlignment.

Is it correct? If not can you please share the Hall sample code which is present with you?

Thank you.

Re: Forceful commutation hampering ADC0 Conversion done(50 usec) ISR.

pachamatej — Wed, 07 Mar 2018 13:54:49 GMT

Hello,

Yes, you understand it correctly. The mechanism for the BLDC case is, the ADC will skip the conversion if the on-going conversion is interrupted. This situation occurs when an asynchronous commutation is forced (thus in every BLDC commutation).

The NXP provides demo codes for the devKits - available for you to download at 3-phase Sensorless BLDC Development Kit|NXP . Please go to the Download section and use https://www.nxp.com/downloads/en/board-support-packages/MTRCKTSBNZVM128_SW.exe to download the package (of both sensorless and hall sensor based applications).

Best regards,

Matej