S12 / MagniV Microcontrollers中的主题 LIN FSL_LIN_2.x_STACK_Package_4.5.9 : SCI Receive Data Register Full Interrupt set while transmitting

LIN FSL_LIN_2.x_STACK_Package_4.5.9 : SCI Receive Data Register Full Interrupt set while transmitting

salmanshaikh — Thu, 07 Jun 2018 11:01:07 GMT

Hello,

I am using LIN FSL_LIN_2.x_STACK_Package_4.5.9 package to implement a master LIN node. The communication is working fine but I am intrigued to know how is RDRF bit in SCISR1 set while transmitting data.

Re: LIN FSL_LIN_2.x_STACK_Package_4.5.9 : SCI Receive Data Register Full Interrupt set while transmitting

dianabatrlova — Tue, 12 Jun 2018 06:45:19 GMT

Hi Salman,

I assume, you already read the reference manual

Receive Data Register Full Flag:

RDRF is set when the data in the receive shift register transfers to the SCI
data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data
register low (SCIDRL).
0 Data not available in SCI data register
1 Received data available in SCI data register

In case of master, the SCI TX and RX lines are connected to the LIN PHY.

When master sends data through TX wire, it will receive this data in RX wire and RDRF will be set. In another case when slave sends data in Lin Bus, RX wire of master will receive this data too and RDRF will be set.

I hope it helps you.

Best regards,

Diana

Re: LIN FSL_LIN_2.x_STACK_Package_4.5.9 : SCI Receive Data Register Full Interrupt set while transmitting

salmanshaikh — Tue, 12 Jun 2018 07:07:17 GMT

Thanks. I missed the readback part which caused the misunderstanding.