S12XEP100 RTI ISR Problems

alfredkronwinkl — Thu, 12 Apr 2018 06:34:07 GMT

Hello community,

i am trying to get the RTI to work on my S12XEP100. I am getting the clock from a 8 MHz crystal and i want to run the INT every 1ms. I am Using CodeWarrior IDE 5.9.0.

I read Datasheet and configured the RTI as followed:

void RTI_init(void)

{
RTICTL_RTDEC = 1; // Decimal or Binary Divider Select Bit (decimal based divider value)

//Divider = 8000 (RTI Time = 1ms)
RTICTL_RTR0 = 1;                      // Real Time Interrupt Modulus Counter Select Bit 0
RTICTL_RTR1 = 1;                      // Real Time Interrupt Modulus Counter Select Bit 1
RTICTL_RTR2 = 0;                      // Real Time Interrupt Modulus Counter Select Bit 2
RTICTL_RTR3 = 0;                      // Real Time Interrupt Modulus Counter Select Bit 3
RTICTL_RTR4 = 1;                      // Real Time Interrupt Prescale Rate Select Bit 4
RTICTL_RTR5 = 0;                      // Real Time Interrupt Prescale Rate Select Bit 5
RTICTL_RTR6 = 0;                      // Real Time Interrupt Prescale Rate Select Bit 6

CRGINT_RTIE = 1; // Real Time Interrupt Enable Bit

EnableInterrupts;

}

so far so good... now i am trying to create an ISR for the RTI but this where problems begin....

I have searched in S12x examples pack on NXP page how to create an ISR and found an example for creating an ISR for ADT0. Here is what i found:

//==============================================================================
// ATD0_ISR
//==============================================================================
#pragma CODE_SEG NON_BANKED
interrupt 22 void ATD0_ISR(void)
{
//code
}
#pragma CODE_SEG DEFAULT

Now the question:

Where can i find the information how i have to change the ATD0_ISR code to get an RTI ISR?

Where can i find the information whitch Nuber i need? (for ADT0 this is 22 but what for RTI?)

Where can i find the information for the ISR Name i need? (for ADT0 this is ATD0_ISR but what for RTI?)

Thanx!

Re: S12XEP100 RTI ISR Problems

lama — Mon, 16 Apr 2018 07:36:49 GMT

Please look into https://community.nxp.com/docs/DOC-329209

There is many examples to easy understand how it works:

Also I have attached a few I use in explanation....

For example:

#pragma CODE_SEG NON_BANKED

interrupt 7 void RTI_ISR(void)

{

ARMCOP=0x55; // kick the dog

ARMCOP=0xAA;

CRGFLG = 0x80; // Clear the flag

PORTB=~PORTB;

}

#pragma CODE_SEG DEFAULT

If you go into Table 1-14. Interrupt Vector Locations then you can also use following approach which explains how to get interrupt number.

//====================================

#pragma CODE_SEG NON_BANKED

interrupt ((0xFE-0xD2)/2) void ATD0_ISR(void) // 0xD2 is an offset presented in the table for given interrupt

{

}

#pragma CODE_SEG DEFAULT

//====================================

#pragma CODE_SEG NON_BANKED

interrupt ((0xFE-0xF0)/2) void RTI_ISR(void) // interrupt ((0xFE-0xF0)/2) the same as interrupt 7

{

}

#pragma CODE_SEG DEFAULT

//====================================

#pragma CODE_SEG NON_BANKED

interrupt ((0xFE-0xA2)/2) void can2Rx_ISR(void)

{

}

#pragma CODE_SEG DEFAULT

//====================================

I would like also to direct you to an example XEP100-INT-INTERRUPTNUMBER-CW51

#define SET_CPU_PRIORITY(vec_adr, priority) \

INT_CFADDR= (vec_adr) & 0xF0; \

INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (priority)

#define PIT0 0x7A // vector address

Code:

…

SET_CPU_PRIORITY(PIT0, 1); // set to HW priority and the lowest level

…

SET_CPU_PRIORITY(PIT0, 4); // change HW priority level

…

Note, another example usinf TRAPPROC as definition of the interrupt together with interrupt function vector defined in the prm file (at the bottom of the file) can be seen in XEP100-INT-TRAPPROC-CW51

Which presents how to set interrupt priority level from 0 to 7. Let’s mention that level 0 disables interrupt even it is enabled in the control register of given peripheral.

The easiest way is to use vector table from the reference manual and use following principle:

If this does not answer your question(s), or I have forgotten something, or if you need more assistance, please contact me again.

This issue will auto close in 7 days upon no reply.

Best Regards, Ladislav

topic Re: S12XEP100 RTI ISR Problems in S12 / MagniV Microcontrollers

S12XEP100 RTI ISR Problems

Re: S12XEP100 RTI ISR Problems