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    <title>topic Re: Interfacing 8-bit parallel memory with MC9S12XEP100 in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interfacing-8-bit-parallel-memory-with-MC9S12XEP100/m-p/701235#M14543</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I created a document "a few" days ago which answer your question and probably provides something more.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93594"&gt;https://community.nxp.com/docs/DOC-93594&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Search for Chapter 6 in the document attached to previous link .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ladislav&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 10 Oct 2017 11:04:32 GMT</pubDate>
    <dc:creator>lama</dc:creator>
    <dc:date>2017-10-10T11:04:32Z</dc:date>
    <item>
      <title>Interfacing 8-bit parallel memory with MC9S12XEP100</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interfacing-8-bit-parallel-memory-with-MC9S12XEP100/m-p/701234#M14542</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Hello,&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I have interfaced&amp;nbsp;MC9S12XEP100 with 8-bit (16 address lines) parallel EEPROM where the A0 line of&amp;nbsp;MC9S12XEP100 is connected to A0 line of EEPROM, A1 line of&amp;nbsp;MC9S12XEP100 is connected to A1 line of EEPROM and so on till A15. While accessing the memory HDBE bit in EBICTL0 register is set to zero which implies&amp;nbsp;DATA[15:8], UDS, and LDS disabled and ASIZ is set to 16. However, it is observed that only odd addresses of memory is accessed by the&amp;nbsp;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;MC9S12XEP100. The A0 line of controller remains at logic HIGH level.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Is there any way to access the whole 8-bit memory using&amp;nbsp;MC9S12XEP100 for above mentioned hardware configuration?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Oct 2017 03:32:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interfacing-8-bit-parallel-memory-with-MC9S12XEP100/m-p/701234#M14542</guid>
      <dc:creator>shraddhanagle</dc:creator>
      <dc:date>2017-10-09T03:32:27Z</dc:date>
    </item>
    <item>
      <title>Re: Interfacing 8-bit parallel memory with MC9S12XEP100</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interfacing-8-bit-parallel-memory-with-MC9S12XEP100/m-p/701235#M14543</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I created a document "a few" days ago which answer your question and probably provides something more.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93594"&gt;https://community.nxp.com/docs/DOC-93594&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Search for Chapter 6 in the document attached to previous link .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Ladislav&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Oct 2017 11:04:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interfacing-8-bit-parallel-memory-with-MC9S12XEP100/m-p/701235#M14543</guid>
      <dc:creator>lama</dc:creator>
      <dc:date>2017-10-10T11:04:32Z</dc:date>
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