xcc

tommy_duan — Tue, 12 Sep 2017 00:42:41 GMT

Hi Sir :

Our customer need the function of the ROM and RAM check, this function will be used in the product Initial stage. At first, we will check the RAM areas from 0x2000 to 0x3FFE . then check the ROM page, page A , B, C, D, E, F from the address of 0x8000 to the 0xC000. here we have some confusion about this ROM and RAM check.

(1) For the RAM check, if I check the RAM areas and find RAM error, if I reset the MCU, the error is whether will be disapper. and what does I want to know is that the reset action is necessary or not.

(2) for the ROM check , we use the System register FERSTAT_SFDIF and FERSTAT_DFDIF, to check if whether those register have a error flag have been set. then if we detect this is on error, we think we have finished the check aciton. so could you please illustrate this two system regiseter how to work and the principle. so we can analysis the algorithm and the logical that we use in ROM check is right.

I am looking forward to your reply! BR. /Tommy

Re: xcc

danielmartynek — Wed, 13 Sep 2017 11:18:04 GMT

Hi,

Regarding SRAM, if I understand, you initialize the memory with some data during startup, so after reset it will be initialized again. But the SRAM is powered during reset so without the initialization the SRAM content is preserved. Only after POR the content is unknown.

Regarding Flash, each phrase includes two sets of aligned double words (half-phrase). For each of these double words 7 ECC bits are calculated and stored for single bit fault correction and double bit fault detection. During a read (always read by half-phrase), the data are being compared with the ECC bits. In case of a single-bit error, the result of the read is corrected and FERSTAT_SFDIF is set. But the data stored at the fault address are not corrected. In case of a double-bit error, the data are not corrected, the error is only detected and FERSTAT_DFDIF is set.

NOTE: There is one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of ECC errors. (Table 24-16, footnote 2).

Regards,

Daniel

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Re: xcc