S12 / MagniV Microcontrollers中的主题 Re: S12ZVC EVALUATION BOARD Schematic question

S12ZVC EVALUATION BOARD Schematic question

mars_huang — Mon, 19 Jun 2017 05:54:29 GMT

Hi All,

For S12ZVC evaluation board there are some questions , thank you
1.VDDA & VDDX & VDDC by external VSUP direct input 12V to internal conversion to 5V?
2.GPIO & TXD & RXD voltage level is 5V or software can be set to 3.3v? If you need to connect with other ic communication voltage level of 3.3V, how to deal with?

Re: S12ZVC EVALUATION BOARD Schematic question

RadekS — Mon, 19 Jun 2017 11:51:24 GMT

Hi Mars,

The S12ZVC contains VDDX, VDDC regulators. So, we may power MCU directly from 12V.
The VDDX regulator may be configured as internal (P=(12V-5V)*IDDX must be dissipated by MCU package) or external (P=(12V-5V)*IDDX will be dissipated by external PNP transistor).
The VDDC regulator does not have the internal option as VDDX (external PNP transistor is needed).

The output voltage from VDDX and VDDC regulators is 5V.
The selectable output voltage is a feature available only at S12ZVLA128 or S12ZVLA64 MCUs.

The optimal solution for 5V / 3V3 interconnection is using voltage translators. For example 74LVC1T45.
For specific buses might be used dedicated circuits like a PCA9517for I2C bus.

I would like to recommend our application note AN2433 5V to 3V Design Considerations
http://www.nxp.com/files/microcontrollers/doc/app_note/AN2433.pdf
with general information about this topic.
Please be aware, that this AN is already 15 years old and the voltage translation portfolio is now much wider.
https://www.nexperia.com/products/logic/logic-voltage-translators
http://www.nxp.com/products/interfaces/voltage-level-translators:VOLTAGE-LEVEL-TRANSLATORS

I hope it helps you.

Have a great day,
Radek

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Re: S12ZVC EVALUATION BOARD Schematic question

mars_huang — Tue, 20 Jun 2017 02:55:46 GMT

Hi Radek,

Thank you for your reply, there is a problem, VDDX and VDDC is the internal conversion 5V voltage, then how to provide 5V voltage level to the voltage converter? Thank you.

Re: S12ZVC EVALUATION BOARD Schematic question

RadekS — Tue, 20 Jun 2017 09:10:52 GMT

Hi Mars,

I cannot see any problem.

The VDDC is typically used for CAN PHY only.

The VDDX pin behaves as output voltage pin when regulator is configured as internal. When regulator is configured as external, the VDDX pin behaves as input voltage pin.

The VDDX is power supply rail for most of the GPIO pins (port AD is powered from VDDA).

So, the 5V for voltage translator should be connected to the VDDX pin.

Let’s assume that VDDX is configured as internal and MCU consumption itself is 25mA.

The RM specifies that internal regulator may provide up to 70mA (for VSUP>6V, TJ < +175°C).

So, there remains up to 45mA for VDDX and pin loads.

Please take these numbers with reserve. The available output current should be evaluated per target application and thermal analysis.

I hope it helps you.

Have a great day,
Radek

Re: S12ZVC EVALUATION BOARD Schematic question

mars_huang — Tue, 20 Jun 2017 10:56:36 GMT

Hi Radek,

I see your reply to other questions (link below) and I always think that the external PNP is the switch, but now it's clear that thanks.

Https://community.nxp.com/thread/437034

Re: S12ZVC EVALUATION BOARD Schematic question

RadekS — Tue, 20 Jun 2017 12:12:11 GMT

Hi Mars,

Thank you for your note. Your previous questions are now clear also for me.

I am glad that this small misunderstanding was explained.

Best regards

Radek