S12 / MagniV Microcontrollers中的主题 Re: S12ZVC interrupt priority

S12ZVC interrupt priority

xiaohui200808 — Mon, 16 Jan 2017 07:21:37 GMT

Hello

I see the S12ZVC datasheet:two registers INT_CFADDR and INT_CFDATA0-7.There is something I donot understand.

Is it means S12ZVC can deal at most 8 interrupts at a point. By configure the INT_CFDATA0-7 ,am I able to deal an interrupt at first ,whose interrupt priority is lower. when two interrupts occuered. IS there any demo code to describe it .Thank you!

Re: S12ZVC interrupt priority

martynek — Mon, 16 Jan 2017 12:16:17 GMT

Hi,

There is the paging mechanism. You can configure all 128 interrupts priority with only 9 registers.

For instance, if you want to have two interrupts with different priority, let’s say:

CAN receive (Vector base + 0x154) and Port L (Vector base + 0x0C0)

Then for CAN receive interrupt:

Vector address/vector size = 0x154 / 4 = 0x55. We use only bit [7..4] for INT_CFADDR configuration. In this case, it is 0x50.

INT_CFADDR = 0x50;

The 3 LSB of 0x55 are 0b101 = 5, therefore for priority configuration of this interrupt use data register 5 and load it with priority you need.

INT_CFDATA5_PRIOLVL = 0x01; /*Priority level of CAN receive */

Similarly for Port L

INT_CFADDR = 0x30;

INT_CFDATA0_PRIOLVL = 0x02; /* Priority level of Port L */

The higher PRIOLVL number means the higher interrupt priority. With PRIOLVL = 0 the corresponding interrupt is disabled.

If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins.

You may look at S12Z CPU RM for more details about interrupt event principles:

http://www.nxp.com/assets/documents/data/en/reference-manuals/S12ZCPU_RM_V1.pdf

I hope it helps you.

Have a great day,

Daniel

Re: S12ZVC interrupt priority

simonliu — Mon, 08 Oct 2018 09:58:39 GMT

Hi Daniel，

As mentioned above,If I need set the CAN and Port L priority at same time.How do I set INT_CFADDR？The CAN is 0x50，Port L is 0x30. I need set INT_CFADDR = （0x50 & 0x30 ）？

Re: S12ZVC interrupt priority

danielmartynek — Mon, 08 Oct 2018 19:07:48 GMT

Hi,

The INT_CFADDR registers selects 8 vectors out of 128 that are accessible in the 8-byte register window INT_CFDATA0–7. And thus you can't configure CAN and Port L interrupts with just one write to the INT_CFADDR register. You have to configure the interrupts one by one.

Regards,

Daniel

Re: S12ZVC interrupt priority

simonliu — Wed, 10 Oct 2018 03:37:04 GMT

Hi Daniel,

I have set the reg for this,but it still doesn't work.

Is there an example of this part of the project?Tks!

Re: S12ZVC interrupt priority

danielmartynek — Thu, 11 Oct 2018 07:45:18 GMT

Hi,

For example, S12ZVML12_Hall_BLDC demo uses the below function:

/*****************************************************************************
*
* Function: void InitINT(void)
*
* Description: Interrupt priorities configuration
*
*****************************************************************************/
void InitINT(void)
{
 // set ADC 0 done ISR (0x184) priority to 6
 // 0x184 / 4 = 0x61 => reg. 0x60, offset 1
 INT_CFADDR = 0x60;
 INT_CFDATA1 = 6;
 
 // set ADC 0 error ISR (0x18C) priority to 2
 // 0x18C / 4 = 0x63 => reg. 0x60, offset 3
 INT_CFADDR = 0x60;
 INT_CFDATA3 = 2;
 
 // TIM ch1 input capture ISR (0x1C8) priority set to 5
 // 0x1C8 / 4 = 0x72 => reg. value = 0x70 + offset 2
 INT_CFADDR = 0x70;
 INT_CFDATA2 = 5;
 
 // TIM ch3 output compare ISR (0x1C0) priority set to 4
 // 0x1C0 / 4 = 0x70 => reg. value = 0x70 + offset 0
 INT_CFADDR = 0x70;
 INT_CFDATA0 = 4;
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Regards,

Daniel