topic I-bit feature implementation on S12Z magniV in S12 / MagniV Microcontrollers

I-bit feature implementation on S12Z magniV

ikkishingu — Tue, 28 Jun 2016 08:46:39 GMT

Hello,

I have a question about S12Z MagniV(e.g.S12ZVM).

About interrupt, where I-bit mask/unmask feature is implemented?

On S12Z CPU? Or INT module?

I cannot find I-bit signal path on device RM and S12Z core manual.

Best Regards,

Ikki

Re: I-bit feature implementation on S12Z magniV

lama — Thu, 30 Jun 2016 10:22:41 GMT

Hi Ikki,

The I-bit is a part of CPU register CCR. The value of bit is connected to an interrupt module S12ZINTV0.

The picture is similar to previous MCUs, Figure 1-1 in http://www.nxp.com/files/microcontrollers/doc/ref_manual/S12INTV1.pdf

Best regards,

Ladislav

Re: I-bit feature implementation on S12Z magniV

ikkishingu — Mon, 04 Jul 2016 05:33:22 GMT

Hi lama,

From your commnent, I imagine the following signal path/connection.

My understanding summary:
1. SEI/CLI instructions act for CCR I-bit
2. I-bit set/clear status signal is connected to INT modules
3. I-bit set/clear status signal and each peripheral interrupt signal are muxed in INT modules
INT module judges Interrupt release or pending based on these signals and register settings

(e.g. PRIOLVL[2:0] in S12Z INT module)
4. Output signals are connected to CPU

Is my understanding correct?
If not, could you point out the wrong point/description?

Best Regards,

Ikki

Re: I-bit feature implementation on S12Z magniV

lama — Mon, 11 Jul 2016 09:25:30 GMT

Hi Ikki,

First of all I am sorry for delay because of vacation.

If I have not missed anything then your description is OK.

I have also asked Radek for double check.

BTW; I really do not understand why you need such an info. From user point of view it is enough to see it as a black box and just understand interrupt selection, nesting possibilities and setup.

Best regards,

Ladislav