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    <title>S12 / MagniV MicrocontrollersのトピックRe: Interrupt priority in MC9S12DJ128</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interrupt-priority-in-MC9S12DJ128/m-p/580754#M12901</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;An Interrupt priority is given by order in the vector table. There is no possibility to chang interrupt priority with exeption than there is one interrupt from I bit maskable interrupt which priority can be put higher from other I-bit maskable interrupts by means of register HPRIO.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are two application notes which ususally solves issue with interrupts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Issues with interrupt priority and nesting interrupts solves.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;UL style="list-style-type: disc;"&gt;&lt;LI&gt;A Software Interrupt Priority Scheme for HCS12 Microcontrollers&lt;BR /&gt; &lt;A href="http://www.nxp.com/files/microcontrollers/doc/app_note/AN2617.pdf"&gt;http://www.nxp.com/files/microcontrollers/doc/app_note/AN2617.pdf&lt;/A&gt;&lt;BR /&gt;&amp;nbsp; &lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Issues with clearing flags when they all are in the same register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL style="list-style-type: disc;"&gt;&lt;LI&gt;Clearing and Disabling Interrupt Flags &lt;BR /&gt;&lt;A href="http://www.nxp.com/files/microcontrollers/doc/app_note/AN2554.pdf"&gt;http://www.nxp.com/files/microcontrollers/doc/app_note/AN2554.pdf&lt;/A&gt;&lt;BR /&gt;&amp;nbsp; &lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;So it looks like you are still going in the loop into CAN0 and all other higher interrupts which avoid you to serve CAN1 interrupts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards, Ladislav&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 08 Aug 2016 09:45:28 GMT</pubDate>
    <dc:creator>lama</dc:creator>
    <dc:date>2016-08-08T09:45:28Z</dc:date>
    <item>
      <title>Interrupt priority in MC9S12DJ128</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interrupt-priority-in-MC9S12DJ128/m-p/580753#M12900</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am using a MC9S12DJ128&amp;nbsp; for BCM.&lt;/P&gt;&lt;P&gt;Some problem occurred during CAN interface.&lt;/P&gt;&lt;P&gt;When I tried interrupt in "CAN0 errors", "CAN1 Transmit" didn't work.&lt;/P&gt;&lt;P&gt;Other interrupt was working well.(Timer, etc.)&lt;/P&gt;&lt;P&gt;Where can I check the interrupt priority?&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Aug 2016 09:28:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interrupt-priority-in-MC9S12DJ128/m-p/580753#M12900</guid>
      <dc:creator>jtpark</dc:creator>
      <dc:date>2016-08-08T09:28:49Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt priority in MC9S12DJ128</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interrupt-priority-in-MC9S12DJ128/m-p/580754#M12901</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;An Interrupt priority is given by order in the vector table. There is no possibility to chang interrupt priority with exeption than there is one interrupt from I bit maskable interrupt which priority can be put higher from other I-bit maskable interrupts by means of register HPRIO.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are two application notes which ususally solves issue with interrupts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Issues with interrupt priority and nesting interrupts solves.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;UL style="list-style-type: disc;"&gt;&lt;LI&gt;A Software Interrupt Priority Scheme for HCS12 Microcontrollers&lt;BR /&gt; &lt;A href="http://www.nxp.com/files/microcontrollers/doc/app_note/AN2617.pdf"&gt;http://www.nxp.com/files/microcontrollers/doc/app_note/AN2617.pdf&lt;/A&gt;&lt;BR /&gt;&amp;nbsp; &lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Issues with clearing flags when they all are in the same register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;UL style="list-style-type: disc;"&gt;&lt;LI&gt;Clearing and Disabling Interrupt Flags &lt;BR /&gt;&lt;A href="http://www.nxp.com/files/microcontrollers/doc/app_note/AN2554.pdf"&gt;http://www.nxp.com/files/microcontrollers/doc/app_note/AN2554.pdf&lt;/A&gt;&lt;BR /&gt;&amp;nbsp; &lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;So it looks like you are still going in the loop into CAN0 and all other higher interrupts which avoid you to serve CAN1 interrupts.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards, Ladislav&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Aug 2016 09:45:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Interrupt-priority-in-MC9S12DJ128/m-p/580754#M12901</guid>
      <dc:creator>lama</dc:creator>
      <dc:date>2016-08-08T09:45:28Z</dc:date>
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