S12 / MagniV MicrocontrollersのトピックRe: Simulating the data corruption between s12x and xgate https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484865#M12065 <HTML><HEAD></HEAD><BODY><P>S12X devices have a build-in trace buffer, which may help you debug your problem. You can set up a breakpoint, which is triggered whenever a zero is read from a specific address and the trace buffer can record either the execution flows or the memory accesses of CPU and XGATE leading up to the breakpoint.</P></BODY></HTML> Wed, 03 Feb 2016 13:44:54 GMT HSW 2016-02-03T13:44:54Z Simulating the data corruption between s12x and xgate https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484864#M12064 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>I am facing an issue&nbsp; where the data received over CAN by Xgate and processed by the s12x. I am sending a proper value on CAN message on xgate but some how the s12x is reading as 0 or some invalid values. I am guessing some type of corruption of data between s12x and xgate and i am not sure as well. The problem is it happens once several hours or it may not happen so i cannot reproduce it easily. Just wanted to know if i can simulate the data corruption between s12x and xgate by sending huge number of can messages or some other way. Please advice.</P></BODY></HTML> Wed, 03 Feb 2016 02:47:37 GMT https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484864#M12064 rahulkrishna 2016-02-03T02:47:37Z Re: Simulating the data corruption between s12x and xgate https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484865#M12065 <HTML><HEAD></HEAD><BODY><P>S12X devices have a build-in trace buffer, which may help you debug your problem. You can set up a breakpoint, which is triggered whenever a zero is read from a specific address and the trace buffer can record either the execution flows or the memory accesses of CPU and XGATE leading up to the breakpoint.</P></BODY></HTML> Wed, 03 Feb 2016 13:44:54 GMT https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484865#M12065 HSW 2016-02-03T13:44:54Z Re: Simulating the data corruption between s12x and xgate https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484866#M12066 <HTML><HEAD></HEAD><BODY><P>Hi rahul,</P><P>How you share data between CPU and XGATE cores?</P><P>I suppose for now that you use shared RAM. Correct?</P><P></P><P>In that case you should use synchronization tools to drive access to these data – for example hardware semaphores.</P><P>Since CAN message typically contains more than one byte, there is high chance that simultaneous XGATE write and CPU read could cause data corruption.</P><P>Semaphores could be used for driving access to peripheral, variables in RAM,…</P><P></P><P>In attachment is example how to use semaphores.</P><P>BTW: which MCU you use?</P><P><BR />I hope it helps you.</P><P></P><P>Have a great day,<BR />RadekS</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Wed, 03 Feb 2016 14:51:43 GMT https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simulating-the-data-corruption-between-s12x-and-xgate/m-p/484866#M12066 RadekS 2016-02-03T14:51:43Z