<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic S12ZVL Watchdog (cop) in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVL-Watchdog-cop/m-p/417702#M11237</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I want to know the default value of ACLK clock in S12zvl controller .I need to calculate value of cop time out period.while selecting cop clock source is ACLK.&lt;/P&gt;&lt;P&gt;its good to have if i get example of same .&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Jul 2015 05:54:28 GMT</pubDate>
    <dc:creator>charudattaingal</dc:creator>
    <dc:date>2015-07-16T05:54:28Z</dc:date>
    <item>
      <title>S12ZVL Watchdog (cop)</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVL-Watchdog-cop/m-p/417702#M11237</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I want to know the default value of ACLK clock in S12zvl controller .I need to calculate value of cop time out period.while selecting cop clock source is ACLK.&lt;/P&gt;&lt;P&gt;its good to have if i get example of same .&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Jul 2015 05:54:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVL-Watchdog-cop/m-p/417702#M11237</guid>
      <dc:creator>charudattaingal</dc:creator>
      <dc:date>2015-07-16T05:54:28Z</dc:date>
    </item>
    <item>
      <title>Re: S12ZVL Watchdog (cop)</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVL-Watchdog-cop/m-p/417703#M11238</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Nominal value of ACLK is 20kHz.&lt;/P&gt;&lt;P&gt;ACLK frequency is divided by 2 when ACLK is selected as clock source for watchdog:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="ACLK.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/56580i0918A1C649904AB0/image-size/large?v=v2&amp;amp;px=999" role="button" title="ACLK.png" alt="ACLK.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;So, 10kHz is source clock frequency for COP watchdog.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Minimum timeout (CPMUCOP_CR=0x01, CPMUCLKS _COPOSCSEL1=1) is 2^7*(1/10kHz)=12,8ms&lt;/P&gt;&lt;P&gt;Maximum timeout (CPMUCOP_CR=0x07, CPMUCLKS _COPOSCSEL1=1) is 2^17*(1/10kHz)= 13,1072s&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Note: ACLK frequency could be trimmed by modifying CPMUACLKTR register value. Note: After reset a value is automatically loaded again from the Flash memory.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I hope it helps you.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;RadekS&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Jul 2015 13:03:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVL-Watchdog-cop/m-p/417703#M11238</guid>
      <dc:creator>RadekS</dc:creator>
      <dc:date>2015-07-17T13:03:21Z</dc:date>
    </item>
  </channel>
</rss>

