External Bus Interface on MC9S12XDP512

manuelschmidber — Wed, 05 Nov 2014 08:12:16 GMT

Hallo,

I use the external bus interface of the MC9S12XDP512 Microcontroller to connect an external Flash. The flash is a 32Mbit, organized as 2Mx16, memory (SST39VF3201B). The following pins are connected with the controller pins (Show attachment).

Following settings are made in software:

MMCCTL0 = 0x02; // Enable \CS1

MMCCTL1 = 0x01 // Enable the Flash or ROM in the memory map

MODE = 0xA0; // Normal expanded mode - bus enabled

EBICTL0 = 0x36; // High byte enable and ADDR21:1

EBICTL1 = 0x02; // Stretch = 3cycles

When I read from memory, following happens:

Unsigned int data = *((unsigned int *far)0x200001);

-> ADDR1 is set to 1 -> OK

Unsigned int data = *((unsigned int *far)0x200002);

-> ADDR1 is set to 0 -> OK

-> ADDR2 is set to 0 -> Why not 1?

Unsigned int data = *((unsigned int *far)0x200003);

-> ADDR1 is set to 0 -> Why not 1?

-> ADDR2 is set to 1 -> OK

Is there something wrong?

Re: External Bus Interface on MC9S12XDP512

lama — Wed, 05 Nov 2014 19:21:35 GMT

Hi,

I am not sure you have read AN2708 http://www.freescale.com/files/microcontrollers/doc/app_note/AN2708.pdf and real examples https://community.freescale.com/docs/DOC-93594 but it could help you to better understand.

Especially page 11, you will see word read and write from even and odd addresses with 3 stretch cycles.

In reality the MCU is 8bit. The memory you have connected to the MCU is not able to be addresed by bytes so I do not know application reason of your flash - code or data. If it is code then I see issue because you are not able to access bytes of the external memory. For this purpose memory with UDS and LDS pins should be used.

So:

*((unsigned int *far) 0x200001) reads word from bytes 0x200001,0x200002

*((unsigned int *far) 0x200002) reads word from bytes 0x200002,0x200003

*((unsigned int *far) 0x200003) reads word from bytes 0x200003,0x200004

The result is that if you read word from odd address (misaligned access) then the access is split into two phases. One reads upper byte of the result word from lower address of aligned word and the second reads lower byte of the result word from upper address of aligned word at higher address. Probably complicated explanation, so=>

address 0 1 2 3 4 5

aligned words address W0H W0L W1H W1L W2H W2L

misaligned words address x W0H W0L W1H W1L W2H W2L

The word access to the bus is always aligned so reading of the word from misaligned address is split into two phases.

Best Regards, Ladislav

topic Re: External Bus Interface on MC9S12XDP512 in S12 / MagniV Microcontrollers

External Bus Interface on MC9S12XDP512

Re: External Bus Interface on MC9S12XDP512