topic S12G SPI polarity control in S12 / MagniV Microcontrollers

S12G SPI polarity control

DustyStew — Mon, 22 Dec 2014 19:14:01 GMT

The SPI MOSI pin defaults to high. So when no data is being sent, it goes high. I would like it to be low.

So I had a look at the Port Integration section of the Reference Manual, and it seemed this should be possible. The settings would be: wire-or mode, pull enabled, pulldown i.e. for MOSI on port 0:

WOMS &= ~0b00100000; // set PS5 to wire-or mode

PERS |= 0b00100000; // enable pull resistor on PS5

PPSS |= 0b0010000; // pull down

I'm afraid this doesn't work. I assume that is because these configuration bits do not apply when using the pins as SPI.

Or have I made an error?

Any other way to make the default state of MOSI low?

TIA

Re: S12G SPI polarity control

steph — Thu, 08 Jan 2015 15:01:26 GMT

hello,

how have you configure the SPI module (SPICR1, SPICR2, SPIBR...) ?

your problem must be in the configuration of the module.

Re: S12G SPI polarity control

davezawislak — Thu, 08 Jan 2015 17:30:20 GMT

In SPICR1 after your SPI session is complete, set SPE to 0. This will take SPI off the buss and allow IO control over the pin.

Re: S12G SPI polarity control

iggi — Fri, 09 Jan 2015 14:35:14 GMT

Hi,

David is right. You must disable the SPI. Also you should set the Port Data Direction Register (DDRS for example) as output. I've tested this on DEMOAX9S12XEP100 board. See screenshots below (click on them to enlarge):

1. Initial state. SPI module initialized, but not enabled yet. The yellow marked address in memory window shows Port S Data Register (PTS) at 0x0248, Port S Input Register (PTIS) at 0x0249 and Port S Data Direction Register (DDRS) at 0x024A address.

As you can see Port S is set as input and PTIS reflects the buffered state on the pin which is 0xFC (taken from the PTS register). The MOSI pin (PS5) is logic 1.

2. SPI enabled. Port S dedicated to SPI module.

3. Port S set as output. SPI still enabled. the PTIS reflect the 4 SPI pin status: MOSI and MISO are high.

4. SPI disabled. Finally, PS5 (MOSI) pin is low as well as other Port S pins.

5. SPI enabled again. Doublecheck the Port S status. MOSI/MISO pins are high again.

Regards,

iggi