topic Re: Missed TIMER input capture edge interrupt mc9s12xs in S12 / MagniV Microcontrollers

Missed TIMER input capture edge interrupt mc9s12xs

Florijan — Fri, 21 Nov 2014 09:59:22 GMT

Hello,

i have an application in which i have to count 3000 pulses of 120khz input square signal. I am using input capture on timer module to trigger interrupt on positive edge of 120khz input signal. Sometimes one interrupt is not generated and one pulse is not counted. So 3000 pulses lasts for 3001 pulse long. this happens rarely (once per 20s) but it happens. Does anyone have any idea why this is happening. In my application it is critical that interrupts are not missed. The mcu is working on 32Mhz bus clock. Can anyone say what should be the slew rate of measured square signal? Right now it is 50 ns. I am convinced that the there is a hardware problem inside mcu.

Best regards,

Florijan

Re: Missed TIMER input capture edge interrupt mc9s12xs

kef2 — Fri, 21 Nov 2014 14:11:53 GMT

Rise time of 50ns is OK. The more important is minimum pulse width, which must be longer than ECLK period.

Aren't you are late servicing all interrupts in time? For robust ISR handling the sum of all your ISR execution times should be less then 1/120kHz. 32M / 120k = 266 bus cycles - not a lot.

Are you using several timer channel interrupts? If so, then this thread applies to you to

Why clearing RTIF bit will cause PORF, LVRF bit cleared also for S12 MCU?

Re: Missed TIMER input capture edge interrupt mc9s12xs

Florijan — Mon, 24 Nov 2014 08:29:34 GMT

Hi Edward,

Thank you for fast reply.

I am using only one interrupt (mentioned). The pulse duty cycle is around 50%. I am using only one timer channel so clearing channel flag is not an issue.

The init code is:

void MCU_init(void)

{

/* ### MC9S12XS256_112 "Cpu" init code ... */

/* PE initialization code after reset */

/* System clock initialization */

/* CLKSEL: PLLSEL=0,PSTP=0,XCLKS=0,PLLWAI=0,RTIWAI=0,COPWAI=0 */

CLKSEL = 0x00U; /* Select clock source from XTAL and set bits in CLKSEL reg. */

/* PLLCTL: CME=1,PLLON=0,FM1=0,FM0=0,FSTWKP=0,PRE=0,PCE=0,SCME=0 */

PLLCTL = 0x80U; /* Disable the PLL */

/* SYNR: VCOFRQ1=0,VCOFRQ0=1,SYNDIV5=0,SYNDIV4=0,SYNDIV3=0,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */

SYNR = 0x47U; /* Set the multiplier register */

/* REFDV: REFFRQ1=0,REFFRQ0=1,REFDIV5=0,REFDIV4=0,REFDIV3=0,REFDIV2=0,REFDIV1=0,REFDIV0=0 */

REFDV = 0x40U; /* Set the divider register */

/* POSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */

POSTDIV = 0x00U; /* Set the post divider register */

/* PLLCTL: CME=1,PLLON=1,FM1=0,FM0=0,FSTWKP=0,PRE=0,PCE=0,SCME=0 */

PLLCTL = 0xC0U;

while(CRGFLG_LOCK == 0U) { /* Wait until the PLL is within the desired tolerance of the target frequency */

}

/* CLKSEL: PLLSEL=1 */

CLKSEL |= (unsigned char)0x80U; /* Select clock source from PLL */

/* VREGHTCL: VSEL=0,VAE=1,HTEN=0,HTDS=0,HTIE=0,HTIF=0 */

VREGHTCL = 0x10U;

/* Int. priority initialization */

/* No. Address Pri XGATE Name Description */

INT_CFADDR = 0x10U;

INT_CFDATA2 = 0x01U; /* 0x0A 0xFF14 1 no ivVReserved118 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x0B 0xFF16 1 no ivVReserved117 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x0C 0xFF18 1 no ivVReserved116 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x0D 0xFF1A 1 no ivVReserved115 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x0E 0xFF1C 1 no ivVReserved114 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x0F 0xFF1E 1 no ivVReserved113 unused by PE */

INT_CFADDR = 0x20U;

INT_CFDATA0 = 0x01U; /* 0x10 0xFF20 1 no ivVReserved112 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x11 0xFF22 1 no ivVReserved111 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x12 0xFF24 1 no ivVReserved110 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x13 0xFF26 1 no ivVReserved109 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x14 0xFF28 1 no ivVReserved108 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x15 0xFF2A 1 no ivVReserved107 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x16 0xFF2C 1 no ivVReserved106 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x17 0xFF2E 1 no ivVReserved105 unused by PE */

INT_CFADDR = 0x30U;

INT_CFDATA0 = 0x01U; /* 0x18 0xFF30 1 no ivVReserved104 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x19 0xFF32 1 no ivVReserved103 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x1A 0xFF34 1 no ivVReserved102 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x1B 0xFF36 1 no ivVReserved101 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x1C 0xFF38 1 no ivVReserved100 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x1D 0xFF3A 1 no ivVReserved99 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x1E 0xFF3C 1 no ivVReserved98 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x1F 0xFF3E 1 no ivVatd0compare unused by PE */

INT_CFADDR = 0x40U;

INT_CFDATA0 = 0x01U; /* 0x20 0xFF40 1 no ivVReserved96 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x21 0xFF42 1 no ivVReserved95 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x22 0xFF44 1 no ivVReserved94 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x23 0xFF46 1 no ivVReserved93 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x24 0xFF48 1 no ivVReserved92 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x25 0xFF4A 1 no ivVReserved91 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x26 0xFF4C 1 no ivVReserved90 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x27 0xFF4E 1 no ivVReserved89 unused by PE */

INT_CFADDR = 0x50U;

INT_CFDATA0 = 0x01U; /* 0x28 0xFF50 1 no ivVReserved88 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x29 0xFF52 1 no ivVReserved87 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x2A 0xFF54 1 no ivVReserved86 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x2B 0xFF56 1 no ivVReserved85 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x2C 0xFF58 1 no ivVReserved84 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x2D 0xFF5A 1 no ivVReserved83 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x2E 0xFF5C 1 no ivVReserved82 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x2F 0xFF5E 1 no ivVReserved81 unused by PE */

INT_CFADDR = 0x60U;

INT_CFDATA0 = 0x01U; /* 0x30 0xFF60 1 no ivVReserved79 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x31 0xFF62 1 no ivVReserved78 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x32 0xFF64 1 no ivVReserved77 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x33 0xFF66 1 no ivVReserved76 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x34 0xFF68 1 no ivVReserved75 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x35 0xFF6A 1 no ivVReserved74 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x36 0xFF6C 1 no ivVReserved73 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x37 0xFF6E 1 no ivVReserved72 unused by PE */

INT_CFADDR = 0x70U;

INT_CFDATA0 = 0x01U; /* 0x38 0xFF70 1 no ivVReserved71 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x39 0xFF72 1 no ivVReserved70 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x3A 0xFF74 1 no ivVpit3 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x3B 0xFF76 1 no ivVpit2 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x3C 0xFF78 1 no ivVpit1 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x3D 0xFF7A 1 no ivVpit0 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x3E 0xFF7C 1 - ivVhti unused by PE */

INT_CFDATA7 = 0x01U; /* 0x3F 0xFF7E 1 no ivVapi unused by PE */

INT_CFADDR = 0x80U;

INT_CFDATA0 = 0x01U; /* 0x40 0xFF80 1 no ivVlvi unused by PE */

INT_CFDATA1 = 0x01U; /* 0x41 0xFF82 1 no ivVReserved62 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x42 0xFF84 1 no ivVReserved61 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x43 0xFF86 1 no ivVReserved60 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x44 0xFF88 1 no ivVReserved59 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x45 0xFF8A 1 no ivVReserved58 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x46 0xFF8C 1 no ivVpwmesdn used by PE */

INT_CFDATA7 = 0x01U; /* 0x47 0xFF8E 1 no ivVportp used by PE */

INT_CFADDR = 0x90U;

INT_CFDATA0 = 0x01U; /* 0x48 0xFF90 1 no ivVReserved55 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x49 0xFF92 1 no ivVReserved54 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x4A 0xFF94 1 no ivVReserved53 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x4B 0xFF96 1 no ivVReserved52 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x4C 0xFF98 1 no ivVReserved51 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x4D 0xFF9A 1 no ivVReserved50 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x4E 0xFF9C 1 no ivVReserved49 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x4F 0xFF9E 1 no ivVReserved48 unused by PE */

INT_CFADDR = 0xA0U;

INT_CFDATA0 = 0x01U; /* 0x50 0xFFA0 1 no ivVReserved47 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x51 0xFFA2 1 no ivVReserved46 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x52 0xFFA4 1 no ivVReserved45 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x53 0xFFA6 1 no ivVReserved44 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x54 0xFFA8 1 no ivVReserved43 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x55 0xFFAA 1 no ivVReserved42 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x56 0xFFAC 1 no ivVReserved41 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x57 0xFFAE 1 no ivVReserved40 unused by PE */

INT_CFADDR = 0xB0U;

INT_CFDATA0 = 0x01U; /* 0x58 0xFFB0 1 no ivVcan0tx unused by PE */

INT_CFDATA1 = 0x01U; /* 0x59 0xFFB2 1 no ivVcan0rx unused by PE */

INT_CFDATA2 = 0x01U; /* 0x5A 0xFFB4 1 no ivVcan0err unused by PE */

INT_CFDATA3 = 0x01U; /* 0x5B 0xFFB6 1 no ivVcan0wkup unused by PE */

INT_CFDATA4 = 0x01U; /* 0x5C 0xFFB8 1 no ivVflash used by PE */

INT_CFDATA5 = 0x01U; /* 0x5D 0xFFBA 1 no ivVflashfd used by PE */

INT_CFDATA6 = 0x01U; /* 0x5E 0xFFBC 1 no ivVReserved33 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x5F 0xFFBE 1 no ivVReserved32 unused by PE */

INT_CFADDR = 0xC0U;

INT_CFDATA0 = 0x01U; /* 0x60 0xFFC0 1 no ivVReserved31 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x61 0xFFC2 1 no ivVReserved30 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x62 0xFFC4 1 no ivVcrgscm unused by PE */

INT_CFDATA3 = 0x01U; /* 0x63 0xFFC6 1 no ivVcrgplllck unused by PE */

INT_CFDATA4 = 0x01U; /* 0x64 0xFFC8 1 no ivVReserved27 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x65 0xFFCA 1 no ivVReserved26 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x66 0xFFCC 1 no ivVporth unused by PE */

INT_CFDATA7 = 0x01U; /* 0x67 0xFFCE 1 no ivVportj unused by PE */

INT_CFADDR = 0xD0U;

INT_CFDATA0 = 0x01U; /* 0x68 0xFFD0 1 no ivVReserved23 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x69 0xFFD2 1 no ivVatd0 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x6A 0xFFD4 1 no ivVsci1 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x6B 0xFFD6 1 no ivVsci0 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x6C 0xFFD8 1 no ivVspi0 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x6D 0xFFDA 1 no ivVtimpaie used by PE */

INT_CFDATA6 = 0x01U; /* 0x6E 0xFFDC 1 no ivVtimpaaovf used by PE */

INT_CFDATA7 = 0x01U; /* 0x6F 0xFFDE 1 no ivVtimovf used by PE */

INT_CFADDR = 0xE0U;

INT_CFDATA0 = 0x01U; /* 0x70 0xFFE0 1 no ivVtimch7 unused by PE */

INT_CFDATA1 = 0x01U; /* 0x71 0xFFE2 1 no ivVtimch6 unused by PE */

INT_CFDATA2 = 0x01U; /* 0x72 0xFFE4 1 no ivVtimch5 unused by PE */

INT_CFDATA3 = 0x01U; /* 0x73 0xFFE6 1 no ivVtimch4 unused by PE */

INT_CFDATA4 = 0x01U; /* 0x74 0xFFE8 1 no ivVtimch3 unused by PE */

INT_CFDATA5 = 0x01U; /* 0x75 0xFFEA 1 no ivVtimch2 unused by PE */

INT_CFDATA6 = 0x01U; /* 0x76 0xFFEC 1 no ivVtimch1 unused by PE */

INT_CFDATA7 = 0x01U; /* 0x77 0xFFEE 1 no ivVtimch0 used by PE */

INT_CFADDR = 0xF0U;

INT_CFDATA0 = 0x01U; /* 0x78 0xFFF0 1 no ivVrti unused by PE */

INT_CFDATA1 = 0x01U; /* 0x79 0xFFF2 1 no ivVirq unused by PE */

/* Common initialization of the CPU registers */

/* RDRP: RDRP7=0,RDRP6=0,RDRP5=1,RDRP4=0,RDRP3=0,RDRP2=0,RDRP1=0,RDRP0=1 */

RDRP = 0x21U;

/* PTTRR: PTTRR5=0 */

PTTRR &= (unsigned char)~(unsigned char)0x20U;

/* PPSP: PPSP0=0 */

PPSP &= (unsigned char)~(unsigned char)0x01U;

/* PERP: PERP0=1 */

PERP |= (unsigned char)0x01U;

/* COPCTL: WCOP=0,RSBCK=1,CR2=0,CR1=1,CR0=1 */

COPCTL = (COPCTL & (unsigned char)~(unsigned char)0x84U) | (unsigned char)0x43U;

/* CRGINT: LOCKIE=0,SCMIE=0 */

CRGINT &= (unsigned char)~(unsigned char)0x12U;

/* VREGCTRL: LVIE=0 */

VREGCTRL &= (unsigned char)~(unsigned char)0x02U;

/* RDRIV: RDPK=0,RDPE=0,RDPB=0,RDPA=0 */

RDRIV &= (unsigned char)~(unsigned char)0x93U;

/* RDRH: RDRH7=0,RDRH6=0,RDRH5=0,RDRH4=0,RDRH3=0,RDRH2=0,RDRH1=0,RDRH0=0 */

RDRH = 0x00U;

/* RDRJ: RDRJ7=0,RDRJ6=0,RDRJ1=0,RDRJ0=0 */

RDRJ &= (unsigned char)~(unsigned char)0xC3U;

/* RDRM: RDRM7=0,RDRM6=0,RDRM5=0,RDRM4=0,RDRM3=0,RDRM2=0,RDRM1=0,RDRM0=0 */

RDRM = 0x00U;

/* RDRS: RDRS7=0,RDRS6=0,RDRS5=0,RDRS4=0,RDRS3=0,RDRS2=0,RDRS1=0,RDRS0=0 */

RDRS = 0x00U;

/* RDRT: RDRT7=0,RDRT6=0,RDRT5=1,RDRT4=0,RDRT3=0,RDRT2=0,RDRT1=0,RDRT0=0 */

RDRT = 0x20U;

/* RDR0AD0: RDR0AD07=0,RDR0AD06=0,RDR0AD05=0,RDR0AD04=0,RDR0AD03=0,RDR0AD02=0,RDR0AD01=0,RDR0AD00=0 */

RDR0AD0 = 0x00U;

/* RDR1AD0: RDR1AD07=0,RDR1AD06=0,RDR1AD05=0,RDR1AD04=0,RDR1AD03=0,RDR1AD02=0,RDR1AD01=0,RDR1AD00=0 */

RDR1AD0 = 0x00U;

/* IRQCR: IRQEN=0 */

IRQCR &= (unsigned char)~(unsigned char)0x40U;

/* ### Init_PWM init code */

/* PWME: PWME7=0,PWME6=0,PWME5=0,PWME4=0,PWME3=0,PWME2=0,PWME1=0,PWME0=0 */

PWME = 0x00U; /* Disable all PWM channels */

/* PWMPOL: PPOL7=0,PPOL6=0,PPOL5=1,PPOL4=0,PPOL3=0,PPOL2=0,PPOL1=1,PPOL0=0 */

PWMPOL = 0x22U;

/* PWMCLK: PCLK7=0,PCLK6=0,PCLK5=0,PCLK4=0,PCLK3=0,PCLK2=0,PCLK1=1,PCLK0=0 */

PWMCLK = 0x02U;

/* PWMCAE: CAE7=0,CAE6=0,CAE5=0,CAE4=0,CAE3=0,CAE2=0,CAE1=0,CAE0=0 */

PWMCAE = 0x00U;

/* PWMCTL: CON67=0,CON45=1,CON23=0,CON01=1,PSWAI=1,PFRZ=0 */

PWMCTL = 0x58U;

/* PWMDTY01: PWMDTY01=0 */

PWMDTY01 = 0x00U;

/* PWMPER01: PWMPER01=0xFFFF */

PWMPER01 = 0xFFFFU;

/* PWMDTY45: PWMDTY45=0x8000 */

PWMDTY45 = 0x8000U;

/* PWMPER45: PWMPER45=0xFFFF */

PWMPER45 = 0xFFFFU;

/* PWMSCLA: BIT7=0,BIT6=0,BIT5=0,BIT4=1,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */

PWMSCLA = 0x10U;

/* PWMSCLB: BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=1,BIT1=1,BIT0=0 */

PWMSCLB = 0x06U;

/* PWMPRCLK: PCKB2=0,PCKB1=0,PCKB0=0,PCKA2=0,PCKA1=0,PCKA0=0 */

PWMPRCLK = 0x00U;

/* PWMSDN: PWMIF=1,PWMIE=0,PWMRSTRT=1,PWMLVL=0,PWM7IN=0,PWM7INL=0,PWM7ENA=0 */

PWMSDN = 0xA0U;

/* PWME: PWME7=0,PWME6=0,PWME5=1,PWME4=0,PWME3=0,PWME2=0,PWME1=1,PWME0=0 */

PWME = 0x22U; /* Enable only configured PWM channels */

/* ### Init_TIM init code */

/* TSCR1: TEN=0 */

TSCR1 &= (unsigned char)~(unsigned char)0x80U;

/* TIE: C7I=0,C6I=0,C5I=0,C4I=0,C3I=0,C2I=0,C1I=0,C0I=0 */

TIE = 0x00U;

/* PACTL: PAEN=0,PAI=0 */

PACTL &= (unsigned char)~(unsigned char)0x41U;

/* PTTRR: PTTRR7=0,PTTRR6=0,PTTRR5=0,PTTRR4=0,PTTRR2=0,PTTRR1=0,PTTRR0=1 */

PTTRR = 0x01U;

/* TIOS: IOS7=0,IOS6=0,IOS5=0,IOS4=0,IOS3=0,IOS2=0,IOS1=0,IOS0=0 */

TIOS = 0x00U;

/* TC0: BIT15=0,BIT14=0,BIT13=0,BIT12=0,BIT11=0,BIT10=0,BIT9=0,BIT8=0,BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */

TC0 = 0x00U;

/* OCPD: OCPD7=0,OCPD6=0,OCPD5=0,OCPD4=0,OCPD3=0,OCPD2=0,OCPD1=0,OCPD0=1 */

OCPD = 0x01U;

/* OC7M: OC7M7=0,OC7M6=0,OC7M5=0,OC7M4=0,OC7M3=0,OC7M2=0,OC7M1=0,OC7M0=0 */

OC7M = 0x00U;

/* OC7D: OC7D7=0,OC7D6=0,OC7D5=0,OC7D4=0,OC7D3=0,OC7D2=0,OC7D1=0,OC7D0=0 */

OC7D = 0x00U;

/* TTOV: TOV7=0,TOV6=0,TOV5=0,TOV4=0,TOV3=0,TOV2=0,TOV1=0,TOV0=0 */

TTOV = 0x00U;

/* TCTL1: OM7=0,OL7=0,OM6=0,OL6=0,OM5=0,OL5=0,OM4=0,OL4=0 */

TCTL1 = 0x00U;

/* TCTL2: OM3=0,OL3=0,OM2=0,OL2=0,OM1=0,OL1=0,OM0=0,OL0=0 */

TCTL2 = 0x00U;

/* TCTL3: EDG7B=0,EDG7A=0,EDG6B=0,EDG6A=0,EDG5B=0,EDG5A=0,EDG4B=0,EDG4A=0 */

TCTL3 = 0x00U;

/* TCTL4: EDG3B=0,EDG3A=0,EDG2B=0,EDG2A=0,EDG1B=0,EDG1A=0,EDG0B=0,EDG0A=1 */

TCTL4 = 0x01U;

/* TFLG1: C7F=1,C6F=1,C5F=1,C4F=1,C3F=1,C2F=1,C1F=1,C0F=1 */

TFLG1 = 0xFFU;

/* TFLG2: TOF=1 */

TFLG2 = 0x80U;

/* TIE: C7I=0,C6I=0,C5I=0,C4I=0,C3I=0,C2I=0,C1I=0,C0I=1 */

TIE = 0x01U;

/* TSCR2: TOI=0,TCRE=0,PR2=0,PR1=0,PR0=0 */

TSCR2 = 0x00U;

/* PACNT: BIT15=0,BIT14=0,BIT13=0,BIT12=0,BIT11=0,BIT10=0,BIT9=0,BIT8=0,BIT7=0,BIT6=0,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */

PACNT = 0x00U;

/* PTPSR: PTPS7=0,PTPS6=0,PTPS5=0,PTPS4=0,PTPS3=0,PTPS2=0,PTPS1=0,PTPS0=0 */

PTPSR = 0x00U;

/* TSCR1: TEN=1,TSWAI=1,TSFRZ=1,TFFCA=1,PRNT=0 */

TSCR1 = 0xF0U;

/* PAFLG: PAOVF=1,PAIF=1 */

PAFLG = 0x03U;

/* PACTL: PAEN=0,PAMOD=0,PEDGE=0,CLK1=0,CLK0=0,PAOVI=0,PAI=0 */

PACTL = 0x00U;

/* ### Init_FLASH init code */

/* FERSTAT: DFDIF=1,SFDIF=1 */

FERSTAT = 0x03U;

/* FSTAT: CCIF=0,ACCERR=1,FPVIOL=1,MGBUSY=0,MGSTAT1=0,MGSTAT0=0 */

FSTAT = 0x30U; /* Clear error flags ACCERR and FPVIOL */

/* FPROT: FPOPEN=1,RNV6=1,FPHDIS=1,FPHS1=1,FPHS0=1,FPLDIS=1,FPLS1=1,FPLS0=1 */

FPROT = 0xFFU;

/* DFPROT: DPOPEN=1,DPS4=0,DPS3=0,DPS2=0,DPS1=0,DPS0=0 */

DFPROT = 0x80U;

/* FERCNFG: DFDIE=0,SFDIE=0 */

FERCNFG = 0x00U;

/* FCNFG: CCIE=0,IGNSF=0,FDFD=0,FSFD=0 */

FCNFG = 0x00U;

/* FCLKDIV: FDIVLD=0,FDIV6=0,FDIV5=0,FDIV4=0,FDIV3=0,FDIV2=1,FDIV1=0,FDIV0=0 */

FCLKDIV = 0x04U;

/* ### Init_COP init code */

/* CLKSEL: COPWAI=1 */

CLKSEL |= (unsigned char)0x01U;

/* PLLCTL: PCE=1 */

PLLCTL |= (unsigned char)0x02U;

/* ### Init_GPIO init code */

/* Disable interrupts */

/* PIEP: PIEP7=0,PIEP6=0,PIEP5=0,PIEP4=0,PIEP3=0,PIEP2=0,PIEP1=0,PIEP0=0 */

PIEP = 0x00U;

/* Clear interrupt flags */

/* PIFP: PIFP7=1,PIFP6=1,PIFP5=1,PIFP4=1,PIFP3=1,PIFP2=1,PIFP1=1,PIFP0=1 */

PIFP = 0xFFU;

/* DDRP: DDRP3=1 */

DDRP |= (unsigned char)0x08U;

/* ### Init_GPIO init code */

/* PORTA: PA0=0 */

PORTA &= (unsigned char)~(unsigned char)0x01U;

/* DDRA: DDRA0=1 */

DDRA |= (unsigned char)0x01U;

/* ### */

/* Initial interrupt priority */

/*lint -save -e950 Disable MISRA rule (1.1) checking. */

asm CLI; /* Enable interrupts */

/*lint -restore Enable MISRA rule (1.1) checking. */

} /*MCU_init*/

The ISR code is:

unsigned char measurementCH0_finished=0;

unsigned int NumberOfPulsesToCountCH0=3000;

unsigned int ValueCH0atStart;

unsigned int ValueCH0End;

unsigned int ValueCH0Temp;

unsigned int NumberOfOverflowsCH0;

unsigned char FirstTimeCH0;

unsigned int TC0_temp;

void InterruptCH0(void){

TFLG1_C0F=1; //flag

// PORTA_PA0=1;

TC0_temp= TC0;

if(FirstTimeCH0) {

ValueCH0atStart=TC0_temp;

ValueCH0Temp=ValueCH0atStart;

FirstTimeCH0=0;

} else{

if(ValueCH0Temp>TC0_temp){

NumberOfOverflowsCH0+=1;

}

ValueCH0Temp= TC0_temp;

}

if(NumberOfPulsesToCountCH0==0){

ValueCH0End=TC0_temp;

TIE_C0I=0; // interrupt

// PORTA_PA0=0;

measurementCH0_finished=1;

} else{

NumberOfPulsesToCountCH0-=1;

}

Best regards,

Florijan

Re: Missed TIMER input capture edge interrupt mc9s12xs

kef2 — Mon, 24 Nov 2014 09:12:02 GMT

With TFFC==1, sequence to clear timer flags is different. Writes to TFLG1 are ignored. For input capture channel you need to read TCx to clear timer flag. Try replacing your TFFC1 = 0xFF; with read from TC0 and check if it helps.

Re: Missed TIMER input capture edge interrupt mc9s12xs

Florijan — Mon, 24 Nov 2014 09:24:01 GMT

I do have read from TC0 already.

The ISR code is:

unsigned char measurementCH0_finished=0;

unsigned int NumberOfPulsesToCountCH0=3000;

unsigned int ValueCH0atStart;

unsigned int ValueCH0End;

unsigned int ValueCH0Temp;

unsigned int NumberOfOverflowsCH0;

unsigned char FirstTimeCH0;

unsigned int TC0_temp;

void InterruptCH0(void){

TFLG1_C0F=1; //flag

// PORTA_PA0=1;

TC0_temp= TC0; <---------------------------------------------------------------

if(FirstTimeCH0) {

ValueCH0atStart=TC0_temp;

ValueCH0Temp=ValueCH0atStart;

FirstTimeCH0=0;

} else{

if(ValueCH0Temp>TC0_temp){

NumberOfOverflowsCH0+=1;

}

ValueCH0Temp= TC0_temp;

}

if(NumberOfPulsesToCountCH0==0){

ValueCH0End=TC0_temp;

TIE_C0I=0; // interrupt

// PORTA_PA0=0;

measurementCH0_finished=1;

} else{

NumberOfPulsesToCountCH0-=1;

}

Best regards,

Florijan

Re: Missed TIMER input capture edge interrupt mc9s12xs

Florijan — Mon, 24 Nov 2014 09:53:04 GMT

Finally I found the solution. I forgot to clear TFLG1_C0F interrupt flag before a whole measurement. Now everything works ok.

Thank you Edward for useful comments.

Best regards,

Floriijan