topic Re: Re: 9S12XDP512 PLL set up in S12 / MagniV Microcontrollers

9S12XDP512 PLL set up

roberthiebert — Sat, 19 Apr 2014 20:47:21 GMT

I'm having difficulty setting up the PLL. The lock bit doesn't apper to be getting set and I dont know what I'm doing wrong.

Here's my code.

;***********************************************************************
;
; - Set the Phase Lock Loop for 80MHz and enable the PLL.
; Crystal frequency is 16MHz
; PLL frequency is (2*(crystal frequency/(REFDV+1))*(SYNR+1))
;
;***********************************************************************

            bclr CLKSEL,CLKSEL_PLLSEL ; Clear "PLL Select" bit of
                                       ;"CLKSEL" to derive system
                                       ; clocks from "OSCCLK"
            bclr PLLCTL,PLLCTL_PLLON ; Clear "Phase Lock Loop On" bit
                                       ; of "PLLCTL" to turn PLL off
            movb #$03,REFDV           ; Load "REFDV" with 3d
                                       ;(16MHz/(3+1)=4MHz Bus freq.)
            movb #$09,SYNR            ; Load "SYNR" with 9d
                                       ;( 4MHz*(9+1)=40MHz Bus freq.)
            bset PLLCTL,PLLCTL_AUTO   ; Set "Automatic Bandwidth
                                       ; Control bit" of "PLLCTL"

            bset PLLCTL,PLLCTL_PLLON ; Set "Phase Lock Loop On" bit
                                       ; of "PLLCTL" to turn PLL on at
                                       ; 80MHz)

;***********************************************************************
;
; - Switch to using PLL for clock (40MHz Bus frequency)
;   Bus frequency is half PLL frequency:
;   ((crystal frequency/(RFDV+1))*(SYNR+1))
;
;***********************************************************************

            nop                          ; Wait 1 bus clock cycle
            nop                          ; Wait 1 bus clock cycle
            nop                          ; Wait 1 bus clock cycle
            nop                          ; Wait 1 bus clock cycle
            brclr CRGFLG,CRGFLG_LOCK,*+0 ; Loop until "Lock Status" bit
                                         ; of "CRFLG" is cleared
            bset CLKSEL,CLKSEL_PLLSEL   ; Set "PLL Select bit" to
                                         ; derive system clocks from
                                         ; "PLLCLK"

;======================================================================
;--------------------------- DEBUG INDICATOR --------------------------
;======================================================================
            LDAA #$80   ; Load accumulator with %1000000
            STAA PORTA ; Copy to PORTA (Fuel Pump LED on)
;=====================================================================

Re: 9S12XDP512 PLL set up

kef2 — Tue, 22 Apr 2014 08:50:06 GMT

Is PLL filter circuit provided by your design? Try checking with scope how stable is voltage at XFC pin.

Re: 9S12XDP512 PLL set up

roberthiebert — Wed, 23 Apr 2014 00:47:37 GMT

The filter circuit is as per the 112 pin recommended PCB layout. Q1 is a 16 MHz crystal, C7 and C8 are 20pf. C5 is 0.22uf, C9 is 6.8nf, C10 is 680pf and R1 is 3.3k. Voltage to ground at XFC is steady at ~1.27 volts

Re: 9S12XDP512 PLL set up

lama — Wed, 23 Apr 2014 04:40:31 GMT

Check the MCU is correct and running without PLL. Start the MCU in the special single chip mode. There are pin MODC, MODB and MODA. If you want to start MCU in special mode (the MCU will stop and the ECLK ( PE4) pin will show busclock OSCCLK/2 [MHz]. This approach will help you to check whether oscillator is running correctly and what is his frequency.
- It is enough to load the code with BDM and do not press run/execute. However, check MODB=0, MODA =0 during reset.
Your description of osc and PLL circuitry looks to be correct, however, double check cold be good. (experience) May I see the schematic - all necessary MCU connections to be MCU running?
Check the test pin is grounded directly.
You use loop controlled Pierce oscillator. So, check pin PE7 = 1
//==============================================================================

void SetupPLL(char synr, char refdv)

{

CLKSEL &= 0x7F;

REFDV = refdv;

SYNR = synr;

while(!(CRGFLG&0x08))

{

// insert any condition to be able to exit in the case of failure

};

CLKSEL |= 0x80;

}

//==============================================================================

Disassembled:

113: CLKSEL &= 0x7F;

0000 4d0080 [4] BCLR _CLKSEL,#128

114: REFDV = refdv;

0003 5b00 [2] STAB _REFDV

115: SYNR = synr;

0005 e683 [3] LDAB 3,SP

0007 5b00 [2] STAB _SYNR

116: while(!(CRGFLG&0x08));

0009 4f0008fc [4] BRCLR _CRGFLG,#8,*+0 ;abs = 0009

117: CLKSEL |= 0x80;

000d 4c0080 [4] BSET _CLKSEL,#128

6. I use PLL filter calculator and it has provided a little bit different values. However, I believe it could not be the issue.

7. Do not step the code to see the PLL is locked. Set breakpoint after PLL is locked.

8. Use command line ECLKCTL_NECLK = 0 to see BUSCLK at PE4.

Best regard,

Ladislav

Re: 9S12XDP512 PLL set up

roberthiebert — Wed, 23 Apr 2014 16:12:36 GMT

Hi Ladislav,

Thanks for your response. First let me say that I am very new to the 9S12XDP512 and CW Special Edition. I am coding in assembler and have very limited knowledge about "C" so the learning curves are steep.

I will make up a schematic for you with the connections to the CPU. Once done, how do I attach the file or send it to you?

PE4 is not brought out on my board, but I may be able to. If I can do this how do I use the command line to read the state?

Regards,

Robert

Re: 9S12XDP512 PLL set up

roberthiebert — Sat, 03 May 2014 14:29:26 GMT

Hi All,

I'm still completely stalled with this. Any assistance would be greatly appreciated.

Robert

Re: Re: 9S12XDP512 PLL set up

lama — Wed, 14 May 2014 13:46:49 GMT

Hi,

here is the code you should compare with yours.

; Include derivative-specific definitions

INCLUDE 'derivative.inc'

; export symbols

XDEF Entry, _Startup, main

; we use export 'Entry' as symbol. This allows us to

; reference 'Entry' either in the linker .prm file

; or from C/C++ later on

XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack

; variable/data section

MY_EXTENDED_RAM: SECTION

; Insert here your data definition.

Counter ds.w 1

FiboRes ds.w 1

;/===================================================================

; code section

;/===================================================================

MyCode: SECTION

main:

_Startup:

Entry:

LDS #__SEG_END_SSTACK ; initialize the stack pointer

;--- init PLL start ---

MOVB #$1,PLLCTL ; PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1

MOVB #$3,CLKSEL ; CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1

MOVB #$9,SYNR ;

MOVB #$3,REFDV ;

BSET PLLCTL,#$40 ; PLLCTL_PLLON = 1;

BRCLR CRGFLG,#$8,*+0 ; while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance

BSET CLKSEL,#$80 ; CLKSEL_PLLSEL = 1; // Select clock source from PLLCLK

BCLR ECLKCTL,#$80 ; ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin to see busclk if necessary

;--- init PLL end ---

BSET DDRB,#$0F

EndlessLoop:

BSET PORTB,#$0F

BCLR PORTB,#$0F

BRA EndlessLoop ; restart.

;/===================================================================

I believe there will be some difference.

Entire project is attached.

Best regards,

Ladislav

Re: Re: 9S12XDP512 PLL set up

roberthiebert — Wed, 14 May 2014 14:10:48 GMT

My error turned out to be the line:

BRCLR CRGFLG,CRGFLG_LOCK,*+1

In the definitions CRGFLG_LOCK equ 3, which does not work, however, mCRGFLG_LOCK equ %00001000 does work. %00001000 is the same as $8.

Thanks so much for your input Ladislav.

Regards,

Robert