/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-vf610.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb_mass_storage.h>
#include <usb/arcotg_udc.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)

#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)

#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)

#define USB_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED| \
			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)

void setup_iomux_ddr(void)
{
#define DDR_IOMUX       0x000001C0
#define DDR_IOMUX1      0x000101C0

	static const iomux_v3_cfg_t ddr_pads[] = {
		NEW_PAD_CTRL(VF610_PAD_DDR_A15__DDR_A_15, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A14__DDR_A_14, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A13__DDR_A_13, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A12__DDR_A_12, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A11__DDR_A_11, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A10__DDR_A_10, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A9__DDR_A_9, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A8__DDR_A_8, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A7__DDR_A_7, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A6__DDR_A_6, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A5__DDR_A_5, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A4__DDR_A_4, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A3__DDR_A_3, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A2__DDR_A_2, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A1__DDR_A_1, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_A0__DDR_A_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_BA2__DDR_BA_2, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_BA1__DDR_BA_1, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_BA0__DDR_BA_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_CAS__DDR_CAS_B, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_CKE__DDR_CKE_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_CLK__DDR_CLK_0, DDR_IOMUX1),
		NEW_PAD_CTRL(VF610_PAD_DDR_CS__DDR_CS_B_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D15__DDR_D_15, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D14__DDR_D_14, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D13__DDR_D_13, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D12__DDR_D_12, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D11__DDR_D_11, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D10__DDR_D_10, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D9__DDR_D_9, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D8__DDR_D_8, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D7__DDR_D_7, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D6__DDR_D_6, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D5__DDR_D_5, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D4__DDR_D_4, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D3__DDR_D_3, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D2__DDR_D_2, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D1__DDR_D_1, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_D0__DDR_D_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_DQM1__DDR_DQM_1, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_DQM0__DDR_DQM_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_DQS1__DDR_DQS_1, DDR_IOMUX1),
		NEW_PAD_CTRL(VF610_PAD_DDR_DQS0__DDR_DQS_0, DDR_IOMUX1),
		NEW_PAD_CTRL(VF610_PAD_DDR_RAS__DDR_RAS_B, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_WE__DDR_WE_B, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_ODT1__DDR_ODT_1, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_ODT0__DDR_ODT_0, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_DDRBYTE1__DDRBYTE1, DDR_IOMUX),
		NEW_PAD_CTRL(VF610_PAD_DDR_DDRBYTE0__DDRBYTE0, DDR_IOMUX),
	};

	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
}

void ddr_phy_init(void)
{
	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;

	#define PHY_DQ_TIMING           0x00002213
	#define PHY_DQS_TIMING          0x00002615
	#define PHY_CTRL                0x00290000
	#define PHY_MASTER_CTRL         0x0001012a
	#define PHY_SLAVE_CTRL          0x00002c00
	#define PHY_SLAVE_CTRL2         0x00010020

	/* phy_dq_timing_reg freq set 0 */
	writel(PHY_DQ_TIMING, &ddrmr->phy[0]);
	writel(PHY_DQ_TIMING, &ddrmr->phy[16]);
	writel(PHY_DQ_TIMING, &ddrmr->phy[32]);
	writel(PHY_DQ_TIMING, &ddrmr->phy[48]);

	writel(PHY_DQS_TIMING, &ddrmr->phy[1]);
	writel(PHY_DQS_TIMING, &ddrmr->phy[17]);
	writel(PHY_DQS_TIMING, &ddrmr->phy[33]);
	writel(PHY_DQS_TIMING, &ddrmr->phy[49]);

	/* phy_gate_lpbk_ctrl_reg freq set 0 */
	writel(PHY_CTRL, &ddrmr->phy[2]);	/* read delay bit21:19 */
	writel(PHY_CTRL, &ddrmr->phy[18]);	/* phase_detect_sel bit18:16 */
	writel(PHY_CTRL, &ddrmr->phy[34]);	/* bit lpbk_ctrl bit12 */

	/* phy_dll_master_ctrl_reg freq set 0 */
	writel(PHY_MASTER_CTRL, &ddrmr->phy[3]);
	writel(PHY_MASTER_CTRL, &ddrmr->phy[19]);
	writel(PHY_MASTER_CTRL, &ddrmr->phy[35]);

	/* phy_dll_slave_ctrl_reg freq set 0 */
	writel(PHY_SLAVE_CTRL, &ddrmr->phy[4]);
	writel(PHY_SLAVE_CTRL, &ddrmr->phy[20]);
	writel(PHY_SLAVE_CTRL, &ddrmr->phy[36]);

	writel(PHY_SLAVE_CTRL2, &ddrmr->phy[52]);

	writel(0x00001100, &ddrmr->phy[50]);
}

void ddr_ctrl_init(void)
{
	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
	int dram_size, rows, cols, banks, port;

	writel(0x00000600, &ddrmr->cr[0]);	/* LPDDR2 or DDR3 */
	writel(0x00000005, &ddrmr->cr[2]);	/* TINIT */
	writel(0x00013880, &ddrmr->cr[10]);	/* reset during power on */
						/* warm boot - 200us */
	writel(0x00030D40, &ddrmr->cr[11]);	/* 500us - 10ns */
	writel(0x0000050c, &ddrmr->cr[12]);	/* CASLAT_LIN, WRLAT */
	writel(0x06040404, &ddrmr->cr[13]);	/* trc, trrd, tccd
						   tbst_int_interval */
	writel(0x1206040F, &ddrmr->cr[14]);	/* tfaw, trp, twtr, tras_min */
	writel(0x04040000, &ddrmr->cr[16]);	/* tmrd, trtp */
	writel(0x0036D80C, &ddrmr->cr[17]);	/* tras_max, tmod */
	writel(0x00000403, &ddrmr->cr[18]);	/* tckesr, tcke */

	writel(0x01000403, &ddrmr->cr[20]);	/* ap, writrp */
	writel(0x00060101, &ddrmr->cr[21]);	/* trcd_int, tras_lockout
						   ccAP */
	writel(0x000A0000, &ddrmr->cr[22]);	/* tdal */
	writel(0x03000200, &ddrmr->cr[23]);	/* bstlen, tmrr, tdll */
	writel(0x00000006, &ddrmr->cr[24]);	/* addr_mirror, reg_dimm
						   trp_ab */
	writel(0x00010000, &ddrmr->cr[25]);	/* tref_enable, auto_refresh
						   arefresh */
	writel(0x06060040, &ddrmr->cr[26]);	/* tref, trfc */
	writel(0x00000005, &ddrmr->cr[28]);	/* tref_interval fixed at 5 */
	writel(0x00000003, &ddrmr->cr[29]);	/* tpdex */

	writel(0x0000000A, &ddrmr->cr[30]);	/* txpdll */
	writel(0x004401FA, &ddrmr->cr[31]);	/* txsnr, txsr */
	writel(0x00010000, &ddrmr->cr[33]);	/* cke_dly, en_quick_srefresh
						 * srefresh_exit_no_refresh,
						 * pwr, srefresh_exit
						 */
	writel(0x00050500, &ddrmr->cr[34]);	/* cksrx, */
						/* cksre, lowpwr_ref_en */

	/* Frequency change */
	writel(0x00000100, &ddrmr->cr[38]);	/* freq change... */
	writel(0x04001002, &ddrmr->cr[39]);

	writel(0x00000001, &ddrmr->cr[41]);	/* dfi_init_start */
	writel(0x00000000, &ddrmr->cr[45]);	/* wrmd */
	writel(0x00000000, &ddrmr->cr[46]);	/* rdmd */
	writel(0x00000000, &ddrmr->cr[47]);	/* REF_PER_AUTO_TEMPCHK:
						 *   LPDDR2 set to 2, else 0
						 */

	/* DRAM device Mode registers */
	writel(0x00460420, &ddrmr->cr[48]);	/* mr0, ddr3 burst of 8 only
						 * mr1, if freq < 125
						 * dll_dis = 1, rtt = 0
						 * if freq > 125, dll_dis = 0
						 * rtt = 3
						 */
	writel(0x00000000, &ddrmr->cr[49]);	/* mr2 */
	writel(0x00000000, &ddrmr->cr[51]);	/* mr3 & mrsingle_data_0 */
	writel(0x00000000, &ddrmr->cr[52]);	/* mr17 & mr16 */

	writel(0x00000000, &ddrmr->cr[57]);	/* ctrl_raw */
	writel(0x00000000, &ddrmr->cr[58]);

	/* ECC */

	/* ZQ stuff */
	writel(0x01000200, &ddrmr->cr[66]);	/* zqcl, zqinit */
	writel(0x00000040, &ddrmr->cr[67]);	/* zqcs */
	writel(0x00000200, &ddrmr->cr[69]);	/* zq_on_sref_exit, qz_req */

	writel(0x00000040, &ddrmr->cr[70]);	/* ref_per_zq */
	writel(0x00000000, &ddrmr->cr[71]);	/* zqreset, ddr3 set to 0 */
	writel(0x01000000, &ddrmr->cr[72]);	/* zqcs_rotate, no_zq_init */

	/* DRAM controller misc */
	writel(0x0a010200, &ddrmr->cr[73]);	/* arebit, col_diff, row_diff
						   bank_diff */
	writel(0x0101ffff, &ddrmr->cr[74]);	/* bank_split, addr_cmp_en
						   cmd/age cnt */
	writel(0x01010101, &ddrmr->cr[75]);	/* rw same pg, rw same en
						   pri en, plen */
	writel(0x03030101, &ddrmr->cr[76]);	/* #q_entries_act_dis
						 * (#cmdqueues
						 * dis_rw_grp_w_bnk_conflict
						 * w2r_split_en, cs_same_en */
	writel(0x01000101, &ddrmr->cr[77]);	/* cs_map, inhibit_dram_cmd
						 * dis_interleave, swen */
	writel(0x0000000C, &ddrmr->cr[78]);	/* qfull, lpddr2_s4, reduc
						   burst_on_fly */
	writel(0x01000000, &ddrmr->cr[79]);	/* ctrlupd_req_per aref en
						 * ctrlupd_req
						 * ctrller busy
						 * in_ord_accept */

	/* ODT */
	writel(0x01010000, &ddrmr->cr[87]);	/* odt: wr_map_cs0
						 * rd_map_cs0
						 * port_data_err_id */
	writel(0x00040000, &ddrmr->cr[88]);	/* todtl_2cmd */
	writel(0x00000002, &ddrmr->cr[89]);	/* add_odt stuff */

	writel(0x00020000, &ddrmr->cr[91]);
	writel(0x00000000, &ddrmr->cr[92]);	/* tdqsck _min, max */

	writel(0x00002819, &ddrmr->cr[96]);	/* wlmrd, wldqsen */


	/* AXI ports */
	writel(0x00202000, &ddrmr->cr[105]);
	writel(0x20200000, &ddrmr->cr[106]);
	writel(0x00002020, &ddrmr->cr[110]);
	writel(0x00202000, &ddrmr->cr[114]);
	writel(0x20200000, &ddrmr->cr[115]);

	writel(0x00000101, &ddrmr->cr[117]);	/* FIFO type (0-async, 1-2:1
						 *	2-1:2, 3- sync, w_pri
						 * r_pri
						 */
	writel(0x01010000, &ddrmr->cr[118]);	/* w_pri, rpri, en */
	writel(0x00000000, &ddrmr->cr[119]);	/* fifo_type */

	writel(0x02020000, &ddrmr->cr[120]);
	writel(0x00000202, &ddrmr->cr[121]);
	writel(0x01010064, &ddrmr->cr[122]);
	writel(0x00010101, &ddrmr->cr[123]);
	writel(0x00000064, &ddrmr->cr[124]);

	/* TDFI */
	writel(0x00000000, &ddrmr->cr[125]);
	writel(0x00000B00, &ddrmr->cr[126]);	/* PHY rdlat */
	writel(0x00000000, &ddrmr->cr[127]);	/* dram ck dis */

	writel(0x00000000, &ddrmr->cr[131]);
	writel(0x00000506, &ddrmr->cr[132]);	/* wrlat, rdlat */
	writel(0x00020000, &ddrmr->cr[137]);
	writel(0x04070303, &ddrmr->cr[139]);

	writel(0x00000000, &ddrmr->cr[136]);
#if 0
	writel(0x80000301, &ddrmr->cr[138]);
	writel(0x0000000A, &ddrmr->cr[140]);
	writel(0x00000000, &ddrmr->cr[141]);
	writel(0x0010ffff, &ddrmr->cr[143]);
	writel(0x16070303, &ddrmr->cr[144]);
	writel(0x0000000f, &ddrmr->cr[145]);
	writel(0x00000000, &ddrmr->cr[146]);
	writel(0x00000000, &ddrmr->cr[147]);
	writel(0x00000000, &ddrmr->cr[148]);
	writel(0x00000000, &ddrmr->cr[149]);
	writel(0x00000000, &ddrmr->cr[150]);
	writel(0x00000204, &ddrmr->cr[151]);
	writel(0x00000000, &ddrmr->cr[152]);
	writel(0x00000000, &ddrmr->cr[153]);
#endif
	writel(0x682C0000, &ddrmr->cr[154]);
	writel(0x0000002d, &ddrmr->cr[155]);	/* pad_ibe, _sel */
	writel(0x00000006, &ddrmr->cr[158]);	/* twr */
	writel(0x00000006, &ddrmr->cr[161]);	/* todth */ // Freescale writes to CR159? Not sure why.

	ddr_phy_init();
	writel(0x1FFFFFFF, &ddrmr->cr[82]);
	writel(0x00000601, &ddrmr->cr[0]);	/* LPDDR2 or DDR3, start */

	udelay(200);

	rows = (readl(&ddrmr->cr[1]) & 0x1F) -
	       ((readl(&ddrmr->cr[73]) >> 8) & 3);
	cols = ((readl(&ddrmr->cr[1]) >> 8) & 0xF) -
	       ((readl(&ddrmr->cr[73]) >> 16) & 7);
	banks = 1 << (3 - (readl(&ddrmr->cr[73]) & 3));
	port = ((readl(&ddrmr->cr[78]) >> 8) & 1) ? 1 : 2;

	dram_size = (1 << (rows + cols)) * banks * port;
}

int dram_init(void)
{
	setup_iomux_ddr();

	ddr_ctrl_init();
	gd->ram_size = PHYS_SDRAM_SIZE;


	return 0;
}

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTB6__UART2_TX, UART_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTB7__UART2_RX, UART_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

static void setup_iomux_enet(void)
{
	static const iomux_v3_cfg_t enet0_pads[] = {
		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
	{ESDHC1_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	/* eSDHC1 is always present */
	return 1;
}

int board_mmc_init(bd_t *bis)
{
	static const iomux_v3_cfg_t esdhc1_pads[] = {
		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
	};

	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	imx_iomux_v3_setup_multiple_pads(
		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));

	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
#endif

static void clock_init(void)
{
	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;

	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr8, CCM_REG_CTRL_MASK,
                CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
                CCM_CCGRX_ENABLE_ALL_CTRL_MASK);

	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);

	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
		CCM_CACRR_ARM_CLK_DIV(0));
	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
		CCM_CSCDR1_RMII_CLK_EN);
	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
		CCM_CSCMR2_RMII_CLK_SEL(0));
}

static void mscm_init(void)
{
	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
	int i;

	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
}

int board_phy_config(struct phy_device *phydev)
{
	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

int board_early_init_f(void)
{
	clock_init();
	mscm_init();

	setup_iomux_uart();
	setup_iomux_enet();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	return 0;
}

int checkboard(void)
{
	puts("Board: phyCORE-Vybrid\n");

	return 0;
}

#ifdef CONFIG_USB_GADGET_ARCOTG_UDC

void udc_pins_setting(void)
{
    u32 reg;
    void *gpio_reg = (void *)GPIO2_PSOR;
	static const iomux_v3_cfg_t usb0_pads[] = {
		NEW_PAD_CTRL(VF610_PAD_PTD6__GPIO85, USB_PAD_CTRL),
		NEW_PAD_CTRL(VF610_PAD_PTD13__GPIO92, USB_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(usb0_pads, ARRAY_SIZE(usb0_pads));
    /*set PTD6 and PTD13*/
    reg = readl(GPIO2_PSOR);
    reg |= (1<<21);
    reg |= (1<<28);
    writel(0x10200000, &gpio_reg);
}
#endif

#ifdef CONFIG_USB_GADGET
void board_usb_init(void)
{
	struct fsl_usb2_platform_data *pdata;
	pdata = calloc(sizeof(*pdata), 1);
	fsl_udc_probe(pdata);
}
#endif

#ifdef CONFIG_USB_GADGET_MASS_STORAGE
static int ums_read_sector(struct ums_device *ums_dev,
                           ulong start, lbaint_t blkcnt, void *buf)
{
        if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num,
                        start + ums_dev->offset, blkcnt, buf) != blkcnt)
                return -1;

        return 0;
}

static int ums_write_sector(struct ums_device *ums_dev,
                            ulong start, lbaint_t blkcnt, const void *buf)
{
        if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num,
                        start + ums_dev->offset, blkcnt, buf) != blkcnt)
                return -1;

        return 0;
}

static void ums_get_capacity(struct ums_device *ums_dev,
                             long long int *capacity)
{
        long long int tmp_capacity;

        tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size)
                                        * SECTOR_SIZE);
        *capacity = ums_dev->mmc->capacity - tmp_capacity;
}

static struct ums_board_info ums_board = {
        .read_sector = ums_read_sector,
        .write_sector = ums_write_sector,
        .get_capacity = ums_get_capacity,
        .name = "Vybrid UMS disk",
        .ums_dev = {
                .mmc = NULL,
                .dev_num = 0,
                .offset = 0,
                .part_size = 0.
        },
};

struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset,
                                      unsigned int part_size)
{
        struct mmc *mmc;

        mmc = find_mmc_device(dev_num);
        if (!mmc)
                return NULL;

        ums_board.ums_dev.mmc = mmc;
        ums_board.ums_dev.dev_num = dev_num;
        ums_board.ums_dev.offset = offset;
        ums_board.ums_dev.part_size = part_size;

        return &ums_board;
}
#endif

