; generated by ARM C/C++ Compiler, 5.03 [Build 102]
; commandline armcc [--c90 --arm --forceinline --no_conditionalize --bss_threshold=0 --debug -c --asm --interleave --no_lower_rwpi --library_interface=aeabi_clib90 -ommu.o --asm_dir=asm --depend_dir=dep --depend=mmu.d --retain=fns,paths,calls,data --cpu=Cortex-A5.vfp --fpu=VFPv4_D16 --fpmode=ieee_full --no_wchar -O0 --data_reorder --licretry --diag_warning=optimizations -I../src/A5 -DTOWER -DARMCC_A5 --no_alternative_tokens --no_trigraphs --remarks --phony_targets ../src/A5/mmu.c]
                          ARM

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  MMUInit PROC
;;;72      **/
;;;73     void MMUInit(unsigned int *masterPt)
000000  e92d4070          PUSH     {r4-r6,lr}
;;;74     {
000004  e1a04000          MOV      r4,r0
;;;75         unsigned int idx;
;;;76     
;;;77        /* Invalidate the TLB entries */
;;;78         CP15TlbInvalidate();
000008  ebfffffe          BL       CP15TlbInvalidate
;;;79     
;;;80         /* Set domain access rights */
;;;81          CP15DomainAccessClientSet();
00000c  ebfffffe          BL       CP15DomainAccessClientSet
;;;82     
;;;83     	
;;;84         /* Disable TEX remapping, Access Flag usage and alignment check */
;;;85        // CP15ControlFeatureDisable( CP15_CONTROL_TEXREMAP
;;;86        //                            | CP15_CONTROL_ACCESSFLAG
;;;87         //                           | CP15_CONTROL_ALIGN_CHCK
;;;88          //                          | CP15_CONTROL_MMU);
;;;89     
;;;90         /* Configure the TTB Control register to use only TTB0 */
;;;91        // CP15TtbCtlTtb0Config();
;;;92     
;;;93         /* Se the master page table with fault entries */
;;;94         for(idx = MMU_PAGETABLE_NUM_ENTRY; idx !=0; idx--)
000010  e3015000          MOVW     r5,#0x1000
000014  ea000002          B        |L1.36|
                  |L1.24|
;;;95         {
;;;96             *masterPt++ = MMU_PAGETABLE_ENTRY_FAULT;
000018  e3a00000          MOV      r0,#0
00001c  e4840004          STR      r0,[r4],#4
000020  e2455001          SUB      r5,r5,#1              ;94
                  |L1.36|
000024  e3550000          CMP      r5,#0                 ;94
000028  1afffffa          BNE      |L1.24|
;;;97         }
;;;98     }
00002c  e8bd8070          POP      {r4-r6,pc}
;;;99     
                          ENDP

                  MMUMemRegionMap PROC
;;;132     **/
;;;133    void MMUMemRegionMap(REGION *region)
000030  e92d4030          PUSH     {r4,r5,lr}
;;;134    {
;;;135        unsigned int *ptEntryPtr;
;;;136        unsigned int ptEntry;
;;;137        int idx;
;;;138    
;;;139        /* Get the first entry in the page table to set */
;;;140        ptEntryPtr = region->masterPtPtr + 
000034  e5905004          LDR      r5,[r0,#4]
000038  e1a05a25          LSR      r5,r5,#20
00003c  e5904018          LDR      r4,[r0,#0x18]
000040  e0841105          ADD      r1,r4,r5,LSL #2
;;;141                     (region->startAddr >> MMU_PAGEBOUND_SHIFT);
;;;142    
;;;143        /* Set the pointer to the last entry */
;;;144        ptEntryPtr += (region->numPages - 1); 
000044  e5904008          LDR      r4,[r0,#8]
000048  e2444001          SUB      r4,r4,#1
00004c  e0811104          ADD      r1,r1,r4,LSL #2
;;;145    
;;;146        /* Get the start Address MSB 3 nibbles. Ignore extended address */
;;;147        ptEntry = (region->startAddr & region->pgType) & MMU_PGADDR_MASK;
000050  e5904004          LDR      r4,[r0,#4]
000054  e5905000          LDR      r5,[r0,#0]
000058  e0044005          AND      r4,r4,r5
00005c  e7d3401f          BFC      r4,#0,#20
000060  e1a03004          MOV      r3,r4
;;;148    
;;;149        /*
;;;150        ** Update the page table entry with memory attributes and
;;;151        ** Access Permissions and Security.
;;;152        ** All the regions will be marked as global.
;;;153        */
;;;154        ptEntry |= ((MMU_PGTYPE_MASK & region->pgType) 
000064  e5904000          LDR      r4,[r0,#0]
000068  e59f5058          LDR      r5,|L1.200|
00006c  e0044005          AND      r4,r4,r5
000070  e5905014          LDR      r5,[r0,#0x14]
000074  e1844005          ORR      r4,r4,r5
000078  e590500c          LDR      r5,[r0,#0xc]
00007c  e1844005          ORR      r4,r4,r5
000080  e5905010          LDR      r5,[r0,#0x10]
000084  e1844005          ORR      r4,r4,r5
000088  e1833004          ORR      r3,r3,r4
;;;155                    | region->accsCtrl | region->memAttrib
;;;156                    | region->secureType);
;;;157    
;;;158        /* Set the entries in the page table for the region attributes */
;;;159        for(idx = (region->numPages - 1); idx >= 0; idx--)
00008c  e5904008          LDR      r4,[r0,#8]
000090  e2442001          SUB      r2,r4,#1
000094  ea000002          B        |L1.164|
                  |L1.152|
;;;160        {
;;;161           *ptEntryPtr-- = ptEntry + (idx << MMU_PAGEBOUND_SHIFT) ;
000098  e0834a02          ADD      r4,r3,r2,LSL #20
00009c  e4014004          STR      r4,[r1],#-4
0000a0  e2422001          SUB      r2,r2,#1              ;159
                  |L1.164|
0000a4  e3520000          CMP      r2,#0                 ;159
0000a8  aafffffa          BGE      |L1.152|
;;;162        }
;;;163    }
0000ac  e8bd8030          POP      {r4,r5,pc}
;;;164    
                          ENDP

                  MMUEnable PROC
;;;174     **/
;;;175    void MMUEnable(unsigned int *masterPt)
0000b0  e92d4010          PUSH     {r4,lr}
;;;176    {
0000b4  e1a04000          MOV      r4,r0
;;;177        /* Set TTB0 register */
;;;178        CP15Ttb0Set((unsigned int)masterPt);
0000b8  e1a00004          MOV      r0,r4
0000bc  ebfffffe          BL       CP15Ttb0Set
;;;179    
;;;180        /* Enable MMU */
;;;181        CP15MMUEnable();
0000c0  ebfffffe          BL       CP15MMUEnable
;;;182    }
0000c4  e8bd8010          POP      {r4,pc}
;;;183    
                          ENDP

                  |L1.200|
                          DCD      0x00040002
