   
Read_DDR_Base_ADDR 	EQU 	0x80000000
Read_DDR_Limit 	EQU	0X81000000


Read_OCRAM1_Base_ADDR 	EQU 	0x3F040000
Read_OCRAM1_Limit 	EQU	0X3f080000

Pattern_init	EQU	0xAA55AA55

ReadBase_ADDR 	EQU 	0x80000000
ReadLimit 	EQU	0X80080000
;ReadBase_ADDR 	EQU 	0x3F040000
;ReadLimit 	EQU	0X3f080000
ReadLimit256 	EQU	0X80000400
   
   
    PRESERVE8
    AREA   Benchmark, CODE, READONLY      ; name this block of code	; Use to match original sample code.  This section is in vectors_armcc.s (entry point) then that calls crt0_armcc.s

	
    ENTRY
;   THUMB	
	
	EXPORT ca5_bench_flowprediction
	EXPORT init_DDR3_ECC
	EXPORT init_DDR3_ECC_32
	EXPORT init_DDR3_ECC_64
	EXPORT init_OCRAM1_ECC
	EXPORT ca5_bench_ecc_test


ca5_bench_flowprediction

   	push {r2-r12}
; disable flow prediction bit Z
	MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR
; set bit Z -> 0 
	mov r3,#0xF7FF	
	movt r3,#0xFFFF
	AND r2,r3
	MCR p15, 0, r2, c1, c0, 0 ; Write SCTLR

;disable BTAC
	MRC p15, 0, r2, c1, c0, 1 ; Read ACTLR
	ORR r2,#0x40000
	MCR p15, 0, r2, c1, c0, 1 ; Write ACTLR
	
;disable RSDIS
	MRC p15, 0, r2, c1, c0, 1 ; Read ACTLR
	ORR r2,#0x20000
	MCR p15, 0, r2, c1, c0, 1 ; Write ACTLR
;modify branch prediction 
	MRC p15, 0, r2, c1, c0, 1 ; Read ACTLR
	ORR r2,#0x10000
	MCR p15, 0, r2, c1, c0, 1 ; Write ACTLR
;disable Branch issue 
	MRC p15, 0, r2, c1, c0, 1 ; Read ACTLR
	ORR r2,#0x10000000
	MCR p15, 0, r2, c1, c0, 1 ; Write ACTLR
; init counter 
	sub r11,r11,r11
	
	;bl ca5_bench_write256
	;bl ca5_bench_ecc_test
	;bl ca5_fecth_inst_bench
	bl ca5_bench_read32
	bl ca5_bench_write32
	bl ca5_bench_read64
	bl ca5_bench_read256
	bl ca5_bench_readOffset
	bl ca5_bench_readfpu
	
	bl ca5_bench_write32
	bl ca5_bench_write64
	bl ca5_bench_write256
	bl ca5_bench_read32
	bl ca5_bench_write32
	bl ca5_bench_writefpu

test
	
	b test
	

	
;THUMB
ca5_fecth_inst_bench
	
	push {r2-r7}
	sub r8,r8,r8
	;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit	
ca5_loop1
	LDR r1,[r0]
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7
	subs r4,r4,r4
	subs r5,r5,r5
	subs r6,r6,r6
	subs r7,r7,r7															
	add r8,#0x1
	cmp r8,#0xF
		
	;bne ca5_loop1
	b ca5_loop1
	
	pop {r2-r7}
	bx lr

ARM

ca5_bench_ecc_test
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit	
		
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r6}
		LDR r0,=ReadBase_ADDR
		STMIA r0!,{r3-r4}
		LDR r0,=ReadBase_ADDR
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}
		LDMIA r0!,{r3}				
		LDR r0,=ReadBase_ADDR
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}
		STMIA r0!,{r3}		
		pop {r3-r12,r14}		 
		bx 	lr	
	
ca5_bench_read32
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_read32_loop		
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}
		LDMIA r0!,{r3}
		LDMIA r0!,{r5}
		LDMIA r0!,{r7}
		LDMIA r0!,{r9}							
		cmp   r0,r2
		
		bne   ca5_bench_read32_loop

		pop {r3-r12,r14}		 
		bx 	lr			


ca5_bench_readOffset
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_readOffset_loop		
		LDR r1,[r0]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x40]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4							
		LDR r1,[r0,#0x80]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0xC0]		
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x100]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x140]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x180]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x1C0]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x200]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x240]								
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x280]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x2C0]		
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x300]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x340]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x380]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x3C0]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x400]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x440]								
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x480]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x4C0]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x500]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x540]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4		
		LDR r1,[r0,#0x580]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x5C0]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x600]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x640]								
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x680]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x6C0]		
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x700]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x740]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		LDR r1,[r0,#0x780]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		;LDR r1,[r0,#0x7C0]
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		subs r4,r4,r4
		add   r0,#0x800													
		cmp   r0,r2
		bne   ca5_bench_readOffset_loop

		pop {r3-r12,r14}		 
		bx 	lr		

ca5_bench_read64
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_read64_loop		
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}
		LDMIA r0!,{r3-r4}							
		cmp   r0,r2
		bne   ca5_bench_read64_loop

		pop {r3-r12,r14}		 
		bx 	lr
				
ca5_bench_read256
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_read256_loop		
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}
		LDMIA r0!,{r3-r10}						
		cmp   r0,r2
		bne   ca5_bench_read256_loop

		pop {r3-r12,r14}		 
		bx 	lr		

ca5_bench_readfpu
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_readfpu_loop		
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}
		VLDMIA.64 r0!,{d2-d5}					
		cmp   r0,r2
		bne   ca5_bench_readfpu_loop

		pop {r3-r12,r14}		 
		bx 	lr		


ca5_bench_write32
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_write32_loop		
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}
		STMIA r0!,{r3}
		STMIA r0!,{r5}
		STMIA r0!,{r7}
		STMIA r0!,{r9}						
		cmp   r0,r2
		bne   ca5_bench_write32_loop

		pop {r3-r12,r14}		 
		bx 	lr		

ca5_bench_write32Bis
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_write32Bis_loop		
		str   r3,[r0]	
		str   r3,[r0,#0x4]
		str   r3,[r0,#0x4]	
		str   r3,[r0,#0x8]	
		str   r3,[r0,#0xC]	
		str   r3,[r0,#0x10]
		str   r3,[r0,#0x14]	
		str   r3,[r0,#0x18]
		str   r3,[r0,#0x1C]	
		str   r3,[r0,#0x20]
		str   r3,[r0,#0x24]	
		str   r3,[r0,#0x28]	
		str   r3,[r0,#0x2C]	
		str   r3,[r0,#0x30]
		str   r3,[r0,#0x34]	
		str   r3,[r0,#0x3C]
		add   r0,#0x40											
		cmp   r0,r2
		bne   ca5_bench_write32Bis_loop

		pop {r3-r12,r14}		 
		bx 	lr		


ca5_bench_write64
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_write64_loop		
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}						
		cmp   r0,r2
		bne   ca5_bench_write64_loop

		pop {r3-r12,r14}		 
		bx 	lr		

ca5_bench_write256
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_write256_loop		
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}						
		cmp   r0,r2
		bne   ca5_bench_write256_loop

		pop {r3-r12,r14}		 
		bx 	lr	
		
ca5_bench_writefpu
		push {r3-r12,r14}
;init parameter
		LDR r0,=ReadBase_ADDR
;init limit 
		LDR r2,=ReadLimit		

ca5_bench_writefpu_loop		
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}
		VSTMIA.64 r0!,{d2-d5}					
		cmp   r0,r2
		bne   ca5_bench_writefpu_loop

		pop {r3-r12,r14}		 
		bx 	lr		
			
init_DDR3_ECC
		push {r3-r12,r14}
;init parameter
		LDR r0,=Read_DDR_Base_ADDR
;init limit 
		LDR r2,=Read_DDR_Limit
		LDR r3,=Pattern_init
		LDR r4,=Pattern_init
		LDR r5,=Pattern_init
		LDR r6,=Pattern_init
		LDR r7,=Pattern_init
		LDR r8,=Pattern_init
		LDR r9,=Pattern_init
		LDR r10,=Pattern_init

				
loop_ddr_init		
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}						
		cmp   r0,r2
		bne   loop_ddr_init

		pop {r3-r12,r14}		 
		bx 	lr	

init_DDR3_ECC_32
		push {r3-r12,r14}
;init parameter
		LDR r0,=Read_DDR_Base_ADDR
;init limit 
		LDR r2,=Read_DDR_Limit
		LDR r3,=Pattern_init
		LDR r4,=Pattern_init
		LDR r5,=Pattern_init
		LDR r6,=Pattern_init
		LDR r7,=Pattern_init
		LDR r8,=Pattern_init
		LDR r9,=Pattern_init
		LDR r10,=Pattern_init

				
loop_ddr_init_32		
		str   r3,[r0]	
		str   r3,[r0,#0x4]
		str   r3,[r0,#0x4]	
		str   r3,[r0,#0x8]	
		str   r3,[r0,#0xC]	
		str   r3,[r0,#0x10]
		str   r3,[r0,#0x14]	
		str   r3,[r0,#0x18]
		str   r3,[r0,#0x1C]	
		str   r3,[r0,#0x20]
		str   r3,[r0,#0x24]	
		str   r3,[r0,#0x28]	
		str   r3,[r0,#0x2C]	
		str   r3,[r0,#0x30]
		str   r3,[r0,#0x34]	
		str   r3,[r0,#0x3C]
		add   r0,#0x40											
		cmp   r0,r2
		bne   loop_ddr_init_32

		pop {r3-r12,r14}		 
		bx 	lr

init_DDR3_ECC_64
		push {r3-r12,r14}
;init parameter
		LDR r0,=Read_DDR_Base_ADDR
;init limit 
		LDR r2,=Read_DDR_Limit
		LDR r3,=Pattern_init
		LDR r4,=Pattern_init
		LDR r5,=Pattern_init
		LDR r6,=Pattern_init
		LDR r7,=Pattern_init
		LDR r8,=Pattern_init
		LDR r9,=Pattern_init
		LDR r10,=Pattern_init

				
loop_ddr_init_64		
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}
		STMIA r0!,{r3-r4}						
		cmp   r0,r2
		bne   loop_ddr_init_64

		pop {r3-r12,r14}		 
		bx 	lr

init_OCRAM1_ECC
		push {r3-r12,r14}
;init parameter
		LDR r0,=Read_OCRAM1_Base_ADDR
;init limit 
		LDR r2,=Read_OCRAM1_Limit
		LDR r3,=Pattern_init
		LDR r4,=Pattern_init
		LDR r5,=Pattern_init
		LDR r6,=Pattern_init
		LDR r7,=Pattern_init
		LDR r8,=Pattern_init
		LDR r9,=Pattern_init
		LDR r10,=Pattern_init

				
loop_ocram1_init		
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}
		STMIA r0!,{r3-r10}						
		cmp   r0,r2
		bne   loop_ddr_init

		pop {r3-r12,r14}		 
		bx 	lr	
	

	END
