; generated by ARM C/C++ Compiler, 5.03 [Build 102]
; commandline armcc [--c90 --arm --forceinline --no_conditionalize --bss_threshold=0 --debug -c --asm --interleave --no_lower_rwpi --library_interface=aeabi_clib90 -obenchinit.o --asm_dir=asm --depend_dir=dep --depend=benchinit.d --retain=fns,paths,calls,data --cpu=Cortex-A5.vfp --fpu=VFPv4_D16 --fpmode=ieee_full --no_wchar -O0 --data_reorder --licretry --diag_warning=optimizations -I../src/A5 -DTOWER -DARMCC_A5 --no_alternative_tokens --no_trigraphs --remarks --phony_targets ../src/A5/benchinit.c]
                          ARM

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  perf_init PROC
;;;147    
;;;148    void perf_init(unsigned long PerfMonEventSelect[])
000000  e92d4010          PUSH     {r4,lr}
;;;149    {
000004  e1a04000          MOV      r4,r0
;;;150    	/* Initialize Performance Monitor, allow control from user mode */
;;;151       	 _pmuInit_();
000008  ebfffffe          BL       _pmuInit_
;;;152       	/* _pmuUserEnable_();*/
;;;153        	_pmuStartCounters_(pmuCOUNTER0 | pmuCOUNTER1 | pmuCYCLE_COUNTER);
00000c  e3a0010e          MOV      r0,#0x80000003
000010  ebfffffe          BL       _pmuStartCounters_
;;;154          	/* Select event counters */
;;;155      
;;;156      	_pmuSetCountEvent_(0, PerfMonEventSelect[0]); 
000014  e3a00000          MOV      r0,#0
000018  e5941000          LDR      r1,[r4,#0]
00001c  ebfffffe          BL       _pmuSetCountEvent_
;;;157      	_pmuSetCountEvent_(1, PerfMonEventSelect[1]);  
000020  e3a00001          MOV      r0,#1
000024  e5941004          LDR      r1,[r4,#4]
000028  ebfffffe          BL       _pmuSetCountEvent_
;;;158    
;;;159    
;;;160    }
00002c  e8bd8010          POP      {r4,pc}
;;;161    
                          ENDP

                  MMUConfigAndEnable PROC
;;;62     
;;;63     void MMUConfigAndEnable(void)
000030  e52de004          PUSH     {lr}
;;;64     {
000034  e24dd08c          SUB      sp,sp,#0x8c
;;;65         /*
;;;66         ** Define DDR memory region of AM335x. DDR can be configured as Normal
;;;67         ** memory with R/W access in user/privileged modes. The cache attributes
;;;68         ** specified here are,
;;;69         ** Inner - Write through, No Write Allocate
;;;70         ** Outer - Write Back, Write Allocate
;;;71         */
;;;72     
;;;73     
;;;74      
;;;75         REGION region_Code_Ddr = {
000038  e3a0201c          MOV      r2,#0x1c
00003c  e59f1148          LDR      r1,|L1.396|
000040  e28d0070          ADD      r0,sp,#0x70
000044  ebfffffe          BL       __aeabi_memcpy4
;;;76                             MMU_PGTYPE_SECTION, START_ADDR_CODE_DDR, NUM_SECTIONS_CODE_DDR,
;;;77                            MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WB_WA,
;;;78                                                              MMU_NON_CACHEABLE),
;;;79     			/*MMU_MEMTYPE_DEVICE_SHAREABLE,*/
;;;80                             MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
;;;81                             (unsigned int*)pageTable
;;;82                            };
;;;83     
;;;84          REGION region_Const_Ddr = {
000048  e3a0201c          MOV      r2,#0x1c
00004c  e59f113c          LDR      r1,|L1.400|
000050  e28d0054          ADD      r0,sp,#0x54
000054  ebfffffe          BL       __aeabi_memcpy4
;;;85                             MMU_PGTYPE_SECTION, START_ADDR_CONST_DDR, NUM_SECTIONS_CONST_DDR,
;;;86                            MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WB_WA,
;;;87                                                              MMU_NON_CACHEABLE),
;;;88     			/*MMU_MEMTYPE_DEVICE_SHAREABLE,*/
;;;89                             MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
;;;90                             (unsigned int*)pageTable
;;;91                            }	;       
;;;92     
;;;93         REGION region_Data_Ddr = {
000058  e3a0201c          MOV      r2,#0x1c
00005c  e59f1130          LDR      r1,|L1.404|
000060  e28d0038          ADD      r0,sp,#0x38
000064  ebfffffe          BL       __aeabi_memcpy4
;;;94                             MMU_PGTYPE_SECTION, START_ADDR_DATA_DDR, NUM_SECTIONS_DATA_DDR,
;;;95                            	MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_NON_CACHEABLE,
;;;96                                                              MMU_NON_CACHEABLE),
;;;97     			//MMU_MEMTYPE_STRONG_ORD_SHAREABLE,
;;;98     			//MMU_MEMTYPE_DEVICE_NON_SHAREABLE,
;;;99     			
;;;100                            MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
;;;101                            (unsigned int*)pageTable
;;;102                           };
;;;103       
;;;104    
;;;105        /*
;;;106        ** Define Device Memory Region. The region between OCMC and DDR is
;;;107        ** configed as device memory, with R/W access in user/privileged modes.
;;;108        ** Also, the region is marked 'Execute Never'.
;;;109        */
;;;110        REGION regionDev = {
000068  e3a0201c          MOV      r2,#0x1c
00006c  e59f1124          LDR      r1,|L1.408|
000070  e28d001c          ADD      r0,sp,#0x1c
000074  ebfffffe          BL       __aeabi_memcpy4
;;;111                            MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV,
;;;112                            MMU_MEMTYPE_DEVICE_NON_SHAREABLE,
;;;113                            MMU_REGION_SECURE,
;;;114                            MMU_AP_PRV_RW_USR_RW ,
;;;115    			/* | MMU_SECTION_EXEC_NEVER*/
;;;116                            (unsigned int*)pageTable
;;;117                           };
;;;118    		       
;;;119    /*
;;;120        ** Define OCMC RAM region of AM335x. Same Attributes of DDR region given.
;;;121        */
;;;122        REGION regionOcmc = {
000078  e3a0201c          MOV      r2,#0x1c
00007c  e59f1118          LDR      r1,|L1.412|
000080  e1a0000d          MOV      r0,sp
000084  ebfffffe          BL       __aeabi_memcpy4
;;;123                             MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC,
;;;124    			 MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WB_WA,
;;;125                                                             MMU_NON_CACHEABLE),
;;;126    			 //MMU_MEMTYPE_STRONG_ORD_SHAREABLE,
;;;127    			 //MMU_MEMTYPE_DEVICE_NON_SHAREABLE,
;;;128                             MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
;;;129                             (unsigned int*)pageTable
;;;130                            };
;;;131    
;;;132    
;;;133        /* Initialize the page table and MMU */
;;;134        MMUInit((unsigned int*)pageTable);
000088  e59f0110          LDR      r0,|L1.416|
00008c  ebfffffe          BL       MMUInit
;;;135    
;;;136        /* Map the defined regions */
;;;137        MMUMemRegionMap(&region_Code_Ddr);
000090  e28d0070          ADD      r0,sp,#0x70
000094  ebfffffe          BL       MMUMemRegionMap
;;;138        MMUMemRegionMap(&region_Const_Ddr);    
000098  e28d0054          ADD      r0,sp,#0x54
00009c  ebfffffe          BL       MMUMemRegionMap
;;;139        MMUMemRegionMap(&region_Data_Ddr);
0000a0  e28d0038          ADD      r0,sp,#0x38
0000a4  ebfffffe          BL       MMUMemRegionMap
;;;140        MMUMemRegionMap(&regionDev);
0000a8  e28d001c          ADD      r0,sp,#0x1c
0000ac  ebfffffe          BL       MMUMemRegionMap
;;;141        MMUMemRegionMap(&regionOcmc);
0000b0  e1a0000d          MOV      r0,sp
0000b4  ebfffffe          BL       MMUMemRegionMap
;;;142    
;;;143        /* Now Safe to enable MMU */
;;;144        MMUEnable((unsigned int*)pageTable);
0000b8  e59f00e0          LDR      r0,|L1.416|
0000bc  ebfffffe          BL       MMUEnable
;;;145    }
0000c0  e28dd08c          ADD      sp,sp,#0x8c
0000c4  e49df004          POP      {pc}
;;;146    
                          ENDP

                  benchinit PROC
;;;46     
;;;47     void benchinit(void)
0000c8  e92d401c          PUSH     {r2-r4,lr}
;;;48     {
;;;49     	unsigned long PerfMonEventSelect[2] = {	DATA_READ,
0000cc  e3a02008          MOV      r2,#8
0000d0  e59f10cc          LDR      r1,|L1.420|
0000d4  e1a0000d          MOV      r0,sp
0000d8  ebfffffe          BL       __aeabi_memcpy4
;;;50     					DATA_WRITES
;;;51     					} ;
;;;52     					
;;;53     	MMUConfigAndEnable();
0000dc  ebfffffe          BL       MMUConfigAndEnable
;;;54     	
;;;55     	perf_init(PerfMonEventSelect);
0000e0  e1a0000d          MOV      r0,sp
0000e4  ebfffffe          BL       perf_init
;;;56     	
;;;57     	CP15IcacheEnable();
0000e8  ebfffffe          BL       CP15IcacheEnable
;;;58     	CP15DcacheFlush();
0000ec  ebfffffe          BL       CP15DcacheFlush
;;;59     	CP15DcacheEnable();	
0000f0  ebfffffe          BL       CP15DcacheEnable
;;;60     }
0000f4  e8bd801c          POP      {r2-r4,pc}
;;;61     
                          ENDP

                  perf_set PROC
;;;162    
;;;163    void perf_set(long evt0,long evt1  )
0000f8  e92d4070          PUSH     {r4-r6,lr}
;;;164    {
0000fc  e1a04000          MOV      r4,r0
000100  e1a05001          MOV      r5,r1
;;;165    	if (evt0 )
000104  e3540000          CMP      r4,#0
000108  0a000002          BEQ      |L1.280|
;;;166    	_pmuSetCountEvent_(0, evt0); 
00010c  e1a01004          MOV      r1,r4
000110  e3a00000          MOV      r0,#0
000114  ebfffffe          BL       _pmuSetCountEvent_
                  |L1.280|
;;;167    	if (evt1)
000118  e3550000          CMP      r5,#0
00011c  0a000002          BEQ      |L1.300|
;;;168      	_pmuSetCountEvent_(1, evt1);  
000120  e1a01005          MOV      r1,r5
000124  e3a00001          MOV      r0,#1
000128  ebfffffe          BL       _pmuSetCountEvent_
                  |L1.300|
;;;169    	
;;;170    	
;;;171    	
;;;172    }
00012c  e8bd8070          POP      {r4-r6,pc}
;;;173    
                          ENDP

                  perf_start PROC
;;;174    void perf_start(void)
000130  e92d4010          PUSH     {r4,lr}
;;;175    {
;;;176    _pmuEnableCountersGlobal_();
000134  ebfffffe          BL       _pmuEnableCountersGlobal_
;;;177    
;;;178    }
000138  e8bd8010          POP      {r4,pc}
;;;179    
                          ENDP

                  perf_stop PROC
;;;180    void perf_stop(long TestNumberX )
00013c  e92d4010          PUSH     {r4,lr}
;;;181    {
000140  e1a04000          MOV      r4,r0
;;;182    	
;;;183    	_pmuDisableCountersGlobal_();
000144  ebfffffe          BL       _pmuDisableCountersGlobal_
;;;184    #if 1
;;;185    	PerfMonReg[TestNumberX][0]= TestNumberX; 
000148  e59f0058          LDR      r0,|L1.424|
00014c  e7804204          STR      r4,[r0,r4,LSL #4]
;;;186    	PerfMonReg[TestNumberX][1]= _pmuGetCycleCount_(); 	
000150  ebfffffe          BL       _pmuGetCycleCount_
000154  e59f104c          LDR      r1,|L1.424|
000158  e0811204          ADD      r1,r1,r4,LSL #4
00015c  e5810004          STR      r0,[r1,#4]
;;;187    	PerfMonReg[TestNumberX][2]= _pmuGetEventCount_(0);	
000160  e3a00000          MOV      r0,#0
000164  ebfffffe          BL       _pmuGetEventCount_
000168  e59f1038          LDR      r1,|L1.424|
00016c  e0811204          ADD      r1,r1,r4,LSL #4
000170  e5810008          STR      r0,[r1,#8]
;;;188    	PerfMonReg[TestNumberX][3]= _pmuGetEventCount_(1);	
000174  e3a00001          MOV      r0,#1
000178  ebfffffe          BL       _pmuGetEventCount_
00017c  e59f1024          LDR      r1,|L1.424|
000180  e0811204          ADD      r1,r1,r4,LSL #4
000184  e581000c          STR      r0,[r1,#0xc]
;;;189    #endif
;;;190    }
000188  e8bd8010          POP      {r4,pc}
                          ENDP

                  |L1.396|
                          DCD      ||.constdata||+0x8
                  |L1.400|
                          DCD      ||.constdata||+0x24
                  |L1.404|
                          DCD      ||.constdata||+0x40
                  |L1.408|
                          DCD      ||.constdata||+0x5c
                  |L1.412|
                          DCD      ||.constdata||+0x78
                  |L1.416|
                          DCD      pageTable
                  |L1.420|
                          DCD      ||.constdata||
                  |L1.424|
                          DCD      PerfMonReg

                          AREA ||.bss||, DATA, NOINIT, ALIGN=14

                  Slice_Period
                          %        4
                  next_state
                          %        16380
                  pageTable
                          %        16384
                  PerfMonReg
                          %        3840

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00000006
                          DCD      0x00000007
                          DCD      0xfff04002
                          DCD      0x80000000
                          DCD      0x00000002
                          DCD      0x00004004
                          DCD      0x00080000
                          DCD      0x00000c00
                          DCD      pageTable
                          DCD      0xfff04002
                          DCD      0x80300000
                          DCD      0x00000001
                          DCD      0x00004004
                          DCD      0x00080000
                          DCD      0x00000c00
                          DCD      pageTable
                          DCD      0xfff04002
                          DCD      0x80400000
                          DCD      0x00000001
                          DCD      0x00004000
                          DCD      0x00080000
                          DCD      0x00000c00
                          DCD      pageTable
                          DCD      0xfff04002
                          DCD      0x40000000
                          DCD      0x00000001
                          DCD      0x00002000
                          DCD      0x00000000
                          DCD      0x00000c00
                          DCD      pageTable
                          DCD      0xfff04002
                          DCD      0x3f000000
                          DCD      0x00000001
                          DCD      0x00004004
                          DCD      0x00080000
                          DCD      0x00000c00
                          DCD      pageTable
