/*
** ###################################################################
**     Processor:           MVF50GS10MK50
**     Compilers:           ARM Compiler
**                          Freescale C/C++ for Embedded ARM
**                          GNU C Compiler
**                          IAR ANSI C/C++ Compiler for ARM
**
**     Reference manual:    Faraday RM Rev. 1, Draft B Feb 2012
**     Version:             rev. 0.1, 2012-05-30
**
**     Abstract:
**         CMSIS Peripheral Access Layer for MVF50GS10MK50
**
**     Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
**
**     http:                 www.freescale.com
**     mail:                 support@freescale.com
**
**     Revisions:
**     - rev. 0.1 (2012-05-30)
**         Initial version
**
** ###################################################################
*/

/**
 * @file MVF50GS10MK50.h
 * @version 0.1
 * @date 2012-05-30
 * @brief CMSIS Peripheral Access Layer for MVF50GS10MK50
 *
 * CMSIS Peripheral Access Layer for MVF50GS10MK50
 */

#if !defined(MVF50GS10MK50_H_)
#define MVF50GS10MK50_H_                         /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0000u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0001u


/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
typedef enum IRQn {
  /* Core interrupts */
  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */

  /* Device specific interrupts */
  SGI0_IRQn                    = 0,                /**< Software Generated Interrupt */
  SGI1_IRQn                    = 1,                /**< Software Generated Interrupt */
  SGI2_IRQn                    = 2,                /**< Software Generated Interrupt */
  SGI3_IRQn                    = 3,                /**< Software Generated Interrupt */
  SGI4_IRQn                    = 4,                /**< Software Generated Interrupt */
  SGI5_IRQn                    = 5,                /**< Software Generated Interrupt */
  SGI6_IRQn                    = 6,                /**< Software Generated Interrupt */
  SGI7_IRQn                    = 7,                /**< Software Generated Interrupt */
  SGI8_IRQn                    = 8,                /**< Software Generated Interrupt */
  SGI9_IRQn                    = 9,                /**< Software Generated Interrupt */
  SGI10_IRQn                   = 10,               /**< Software Generated Interrupt */
  SGI11_IRQn                   = 11,               /**< Software Generated Interrupt */
  SGI12_IRQn                   = 12,               /**< Software Generated Interrupt */
  SGI13_IRQn                   = 13,               /**< Software Generated Interrupt */
  SGI14_IRQn                   = 14,               /**< Software Generated Interrupt */
  SGI15_IRQn                   = 15,               /**< Software Generated Interrupt */
  PPI0_IRQn                    = 16,               /**< Private Peripheral Interrupt */
  PPI1_IRQn                    = 17,               /**< Private Peripheral Interrupt */
  PPI2_IRQn                    = 18,               /**< Private Peripheral Interrupt */
  PPI3_IRQn                    = 19,               /**< Private Peripheral Interrupt */
  PPI4_IRQn                    = 20,               /**< Private Peripheral Interrupt */
  PPI5_IRQn                    = 21,               /**< Private Peripheral Interrupt */
  PPI6_IRQn                    = 22,               /**< Private Peripheral Interrupt */
  PPI7_IRQn                    = 23,               /**< Private Peripheral Interrupt */
  PPI8_IRQn                    = 24,               /**< Private Peripheral Interrupt */
  PPI9_IRQn                    = 25,               /**< Private Peripheral Interrupt */
  PPI10_IRQn                   = 26,               /**< Private Peripheral Interrupt */
  GlobalTimer_IRQn             = 27,               /**< Private Peripheral Interrupt */
  PPI12_IRQn                   = 28,               /**< Private Peripheral Interrupt */
  CoreTimer_IRQn               = 29,               /**< Private Peripheral Interrupt */
  CoreWatchdog_IRQn            = 30,               /**< Private Peripheral Interrupt */
  PPI15_IRQn                   = 31,               /**< Private Peripheral Interrupt */
  CPU_to_CPU_int0_IRQn         = 32,               /**< Shared Peripheral Interrupt */
  CPU_to_CPU_int1_IRQn         = 33,               /**< Shared Peripheral Interrupt */
  CPU_to_CPU_int2_IRQn         = 34,               /**< Shared Peripheral Interrupt */
  CPU_to_CPU_int3_IRQn         = 35,               /**< Shared Peripheral Interrupt */
  Directed_CM4_int0_IRQn       = 36,               /**< Shared Peripheral Interrupt */
  Directed_CM4_int1_IRQn       = 37,               /**< Shared Peripheral Interrupt */
  Directed_CM4_int2_IRQn       = 38,               /**< Shared Peripheral Interrupt */
  Directed_CM4_int3_IRQn       = 39,               /**< Shared Peripheral Interrupt */
  DMA0_Transfer_Complete_IRQn  = 40,               /**< Shared Peripheral Interrupt */
  DMA0_Error_IRQn              = 41,               /**< Shared Peripheral Interrupt */
  DMA1_Transfer_Complete_IRQn  = 42,               /**< Shared Peripheral Interrupt */
  DMA1_Error_IRQn              = 43,               /**< Shared Peripheral Interrupt */
  Reserved44_IRQn              = 44,               /**< Shared Peripheral Interrupt */
  Reserved45_IRQn              = 45,               /**< Shared Peripheral Interrupt */
  MSCM_ECC0_IRQn               = 46,               /**< Shared Peripheral Interrupt */
  MSCM_ECC1_IRQn               = 47,               /**< Shared Peripheral Interrupt */
  CSU_Alarm_IRQn               = 48,               /**< Shared Peripheral Interrupt */
  Reserved49_IRQn              = 49,               /**< Shared Peripheral Interrupt */
  MSCM_ACTZS_IRQn              = 50,               /**< Shared Peripheral Interrupt */
  Reserved51_IRQn              = 51,               /**< Shared Peripheral Interrupt */
  WDOG_A5_IRQn                 = 52,               /**< Shared Peripheral Interrupt */
  WDOG_M4_IRQn                 = 53,               /**< Shared Peripheral Interrupt */
  WDOG_SNVS_IRQn               = 54,               /**< Shared Peripheral Interrupt */
  CP1_Boot_Fail_IRQn           = 55,               /**< Shared Peripheral Interrupt */
  QuadSPI0_IRQn                = 56,               /**< Shared Peripheral Interrupt */
  QuadSPI1_IRQn                = 57,               /**< Shared Peripheral Interrupt */
  DRAM_IRQn                    = 58,               /**< Shared Peripheral Interrupt */
  SDHC0_IRQn                   = 59,               /**< Shared Peripheral Interrupt */
  SDHC1_IRQn                   = 60,               /**< Shared Peripheral Interrupt */
  Reserved61_IRQn              = 61,               /**< Shared Peripheral Interrupt */
  DCU0_IRQn                    = 62,               /**< Shared Peripheral Interrupt */
  DCU1_IRQn                    = 63,               /**< Shared Peripheral Interrupt */
  VIU_IRQn                     = 64,               /**< Shared Peripheral Interrupt */
  Reserved65_IRQn              = 65,               /**< Shared Peripheral Interrupt */
  GC355_IRQn                   = 66,               /**< Shared Peripheral Interrupt */
  RLE_IRQn                     = 67,               /**< Shared Peripheral Interrupt */
  LCD_IRQn                     = 68,               /**< Shared Peripheral Interrupt */
  Reserved69_IRQn              = 69,               /**< Shared Peripheral Interrupt */
  Reserved70_IRQn              = 70,               /**< Shared Peripheral Interrupt */
  PIT_IRQn                     = 71,               /**< PIT timer interrupt (Shared Peripheral Interrupt) */
  LPTimer0_IRQn                = 72,               /**< LPTimer interrupt (Shared Peripheral Interrupt) */
  Reserved73_IRQn              = 73,               /**< Shared Peripheral Interrupt */
  FlexTimer0_IRQn              = 74,               /**< FTM0 fault, overflow and channels interrupt (Shared Peripheral Interrupt) */
  FlexTimer1_IRQn              = 75,               /**< FTM1 fault, overflow and channels interrupt (Shared Peripheral Interrupt) */
  FlexTimer2_IRQn              = 76,               /**< FTM2 fault, overflow and channels interrupt (Shared Peripheral Interrupt) */
  FlexTimer3_IRQn              = 77,               /**< FTM3 fault, overflow and channels interrupt (Shared Peripheral Interrupt) */
  Reserved78_IRQn              = 78,               /**< Shared Peripheral Interrupt */
  Reserved79_IRQn              = 79,               /**< Shared Peripheral Interrupt */
  Reserved80_IRQn              = 80,               /**< Shared Peripheral Interrupt */
  Reserved81_IRQn              = 81,               /**< Shared Peripheral Interrupt */
  USBPHY0_IRQn                 = 82,               /**< Shared Peripheral Interrupt */
  USBPHY1_IRQn                 = 83,               /**< Shared Peripheral Interrupt */
  Reserved84_IRQn              = 84,               /**< Shared Peripheral Interrupt */
  ADC0_IRQn                    = 85,               /**< Shared Peripheral Interrupt */
  ADC1_IRQn                    = 86,               /**< Shared Peripheral Interrupt */
  DAC0_IRQn                    = 87,               /**< Shared Peripheral Interrupt */
  DAC1_IRQn                    = 88,               /**< Shared Peripheral Interrupt */
  Reserved89_IRQn              = 89,               /**< Shared Peripheral Interrupt */
  FlexCAN0_IRQn                = 90,               /**< Shared Peripheral Interrupt */
  FlexCAN1_IRQn                = 91,               /**< Shared Peripheral Interrupt */
  MLB_IRQn                     = 92,               /**< Shared Peripheral Interrupt */
  UART0_IRQn                   = 93,               /**< Shared Peripheral Interrupt */
  UART1_IRQn                   = 94,               /**< Shared Peripheral Interrupt */
  UART2_IRQn                   = 95,               /**< Shared Peripheral Interrupt */
  UART3_IRQn                   = 96,               /**< Shared Peripheral Interrupt */
  UART4_IRQn                   = 97,               /**< Shared Peripheral Interrupt */
  UART5_IRQn                   = 98,               /**< Shared Peripheral Interrupt */
  DSPI0_IRQn                   = 99,               /**< Shared Peripheral Interrupt */
  DSPI1_IRQn                   = 100,              /**< Shared Peripheral Interrupt */
  DSPI2_IRQn                   = 101,              /**< Shared Peripheral Interrupt */
  DSPI3_IRQn                   = 102,              /**< Shared Peripheral Interrupt */
  I2C0_IRQn                    = 103,              /**< Shared Peripheral Interrupt */
  I2C1_IRQn                    = 104,              /**< Shared Peripheral Interrupt */
  I2C2_IRQn                    = 105,              /**< Shared Peripheral Interrupt */
  I2C3_IRQn                    = 106,              /**< Shared Peripheral Interrupt */
  USB0_IRQn                    = 107,              /**< Shared Peripheral Interrupt */
  USB1_IRQn                    = 108,              /**< Shared Peripheral Interrupt */
  Reserved109_IRQn             = 109,              /**< Shared Peripheral Interrupt */
  ENET_MAC0_IRQn               = 110,              /**< Shared Peripheral Interrupt */
  ENET_MAC1_IRQn               = 111,              /**< Shared Peripheral Interrupt */
  ENET_1588_Timer0_IRQn        = 112,              /**< Shared Peripheral Interrupt */
  ENET_1588_Timer1_IRQn        = 113,              /**< Shared Peripheral Interrupt */
  ENET_Switch_IRQn             = 114,              /**< Shared Peripheral Interrupt */
  NFC_IRQn                     = 115,              /**< Shared Peripheral Interrupt */
  SAI0_IRQn                    = 116,              /**< Shared Peripheral Interrupt */
  SAI1_IRQn                    = 117,              /**< Shared Peripheral Interrupt */
  SAI2_IRQn                    = 118,              /**< Shared Peripheral Interrupt */
  SAI3_IRQn                    = 119,              /**< Shared Peripheral Interrupt */
  ESAI_BIFIFO_IRQn             = 120,              /**< Shared Peripheral Interrupt */
  SPDIF_IRQn                   = 121,              /**< Shared Peripheral Interrupt */
  ASRC_IRQn                    = 122,              /**< Shared Peripheral Interrupt */
  CMU_IRQn                     = 123,              /**< Shared Peripheral Interrupt */
  WKPU0_IRQn                   = 124,              /**< Shared Peripheral Interrupt */
  WKPU1_IRQn                   = 125,              /**< Shared Peripheral Interrupt */
  CCM0_IRQn                    = 126,              /**< Shared Peripheral Interrupt */
  CCM1_IRQn                    = 127,              /**< Shared Peripheral Interrupt */
  SRC_IRQn                     = 128,              /**< Shared Peripheral Interrupt */
  PDB_IRQn                     = 129,              /**< Shared Peripheral Interrupt */
  EWM_IRQn                     = 130,              /**< Shared Peripheral Interrupt */
  Reserved131_IRQn             = 131,              /**< Shared Peripheral Interrupt */
  SNVS_Consolidated_IRQn       = 132,              /**< Shared Peripheral Interrupt */
  SNVS_Security_IRQn           = 133,              /**< Shared Peripheral Interrupt */
  CAAM_IRQn                    = 134,              /**< Shared Peripheral Interrupt */
  Reserved135_IRQn             = 135,              /**< Shared Peripheral Interrupt */
  Reserved136_IRQn             = 136,              /**< Shared Peripheral Interrupt */
  Reserved137_IRQn             = 137,              /**< Shared Peripheral Interrupt */
  Reserved138_IRQn             = 138,              /**< Shared Peripheral Interrupt */
  PORT0_IRQn                   = 139,              /**< Shared Peripheral Interrupt */
  PORT1_IRQn                   = 140,              /**< Shared Peripheral Interrupt */
  PORT2_IRQn                   = 141,              /**< Shared Peripheral Interrupt */
  PORT3_IRQn                   = 142,              /**< Shared Peripheral Interrupt */
  PORT4_IRQn                   = 143,              /**< Shared Peripheral Interrupt */
  Reserved160_IRQn             = 144,              /**< Reserved interrupt 160 */
  Reserved161_IRQn             = 145,              /**< Reserved interrupt 161 */
  Reserved162_IRQn             = 146,              /**< Reserved interrupt 162 */
  Reserved163_IRQn             = 147,              /**< Reserved interrupt 163 */
  Reserved164_IRQn             = 148,              /**< Reserved interrupt 164 */
  Reserved165_IRQn             = 149,              /**< Reserved interrupt 165 */
  Reserved166_IRQn             = 150,              /**< Reserved interrupt 166 */
  Reserved167_IRQn             = 151,              /**< Reserved interrupt 167 */
  Reserved168_IRQn             = 152,              /**< Reserved interrupt 168 */
  Reserved169_IRQn             = 153,              /**< Reserved interrupt 169 */
  Reserved170_IRQn             = 154,              /**< Reserved interrupt 170 */
  Reserved171_IRQn             = 155,              /**< Reserved interrupt 171 */
  Reserved172_IRQn             = 156,              /**< Reserved interrupt 172 */
  Reserved173_IRQn             = 157,              /**< Reserved interrupt 173 */
  Reserved174_IRQn             = 158,              /**< Reserved interrupt 174 */
  Reserved175_IRQn             = 159,              /**< Reserved interrupt 175 */
  Reserved176_IRQn             = 160,              /**< Reserved interrupt 176 */
  Reserved177_IRQn             = 161,              /**< Reserved interrupt 177 */
  Reserved178_IRQn             = 162,              /**< Reserved interrupt 178 */
  Reserved179_IRQn             = 163,              /**< Reserved interrupt 179 */
  Reserved180_IRQn             = 164,              /**< Reserved interrupt 180 */
  Reserved181_IRQn             = 165,              /**< Reserved interrupt 181 */
  Reserved182_IRQn             = 166,              /**< Reserved interrupt 182 */
  Reserved183_IRQn             = 167,              /**< Reserved interrupt 183 */
  Reserved184_IRQn             = 168,              /**< Reserved interrupt 184 */
  Reserved185_IRQn             = 169,              /**< Reserved interrupt 185 */
  Reserved186_IRQn             = 170,              /**< Reserved interrupt 186 */
  Reserved187_IRQn             = 171,              /**< Reserved interrupt 187 */
  Reserved188_IRQn             = 172,              /**< Reserved interrupt 188 */
  Reserved189_IRQn             = 173,              /**< Reserved interrupt 189 */
  Reserved190_IRQn             = 174,              /**< Reserved interrupt 190 */
  Reserved191_IRQn             = 175,              /**< Reserved interrupt 191 */
  Reserved192_IRQn             = 176,              /**< Reserved interrupt 192 */
  Reserved193_IRQn             = 177,              /**< Reserved interrupt 193 */
  Reserved194_IRQn             = 178,              /**< Reserved interrupt 194 */
  Reserved195_IRQn             = 179,              /**< Reserved interrupt 195 */
  Reserved196_IRQn             = 180,              /**< Reserved interrupt 196 */
  Reserved197_IRQn             = 181,              /**< Reserved interrupt 197 */
  Reserved198_IRQn             = 182,              /**< Reserved interrupt 198 */
  Reserved199_IRQn             = 183,              /**< Reserved interrupt 199 */
  Reserved200_IRQn             = 184,              /**< Reserved interrupt 200 */
  Reserved201_IRQn             = 185,              /**< Reserved interrupt 201 */
  Reserved202_IRQn             = 186,              /**< Reserved interrupt 202 */
  Reserved203_IRQn             = 187,              /**< Reserved interrupt 203 */
  Reserved204_IRQn             = 188,              /**< Reserved interrupt 204 */
  Reserved205_IRQn             = 189,              /**< Reserved interrupt 205 */
  Reserved206_IRQn             = 190,              /**< Reserved interrupt 206 */
  Reserved207_IRQn             = 191,              /**< Reserved interrupt 207 */
  Reserved208_IRQn             = 192,              /**< Reserved interrupt 208 */
  Reserved209_IRQn             = 193,              /**< Reserved interrupt 209 */
  Reserved210_IRQn             = 194,              /**< Reserved interrupt 210 */
  Reserved211_IRQn             = 195,              /**< Reserved interrupt 211 */
  Reserved212_IRQn             = 196,              /**< Reserved interrupt 212 */
  Reserved213_IRQn             = 197,              /**< Reserved interrupt 213 */
  Reserved214_IRQn             = 198,              /**< Reserved interrupt 214 */
  Reserved215_IRQn             = 199,              /**< Reserved interrupt 215 */
  Reserved216_IRQn             = 200,              /**< Reserved interrupt 216 */
  Reserved217_IRQn             = 201,              /**< Reserved interrupt 217 */
  Reserved218_IRQn             = 202,              /**< Reserved interrupt 218 */
  Reserved219_IRQn             = 203,              /**< Reserved interrupt 219 */
  Reserved220_IRQn             = 204,              /**< Reserved interrupt 220 */
  Reserved221_IRQn             = 205,              /**< Reserved interrupt 221 */
  Reserved222_IRQn             = 206,              /**< Reserved interrupt 222 */
  Reserved223_IRQn             = 207,              /**< Reserved interrupt 223 */
  Reserved224_IRQn             = 208,              /**< Reserved interrupt 224 */
  Reserved225_IRQn             = 209,              /**< Reserved interrupt 225 */
  Reserved226_IRQn             = 210,              /**< Reserved interrupt 226 */
  Reserved227_IRQn             = 211,              /**< Reserved interrupt 227 */
  Reserved228_IRQn             = 212,              /**< Reserved interrupt 228 */
  Reserved229_IRQn             = 213,              /**< Reserved interrupt 229 */
  Reserved230_IRQn             = 214,              /**< Reserved interrupt 230 */
  Reserved231_IRQn             = 215,              /**< Reserved interrupt 231 */
  Reserved232_IRQn             = 216,              /**< Reserved interrupt 232 */
  Reserved233_IRQn             = 217,              /**< Reserved interrupt 233 */
  Reserved234_IRQn             = 218,              /**< Reserved interrupt 234 */
  Reserved235_IRQn             = 219,              /**< Reserved interrupt 235 */
  Reserved236_IRQn             = 220,              /**< Reserved interrupt 236 */
  Reserved237_IRQn             = 221,              /**< Reserved interrupt 237 */
  Reserved238_IRQn             = 222,              /**< Reserved interrupt 238 */
  Reserved239_IRQn             = 223,              /**< Reserved interrupt 239 */
  Reserved240_IRQn             = 224,              /**< Reserved interrupt 240 */
  Reserved241_IRQn             = 225,              /**< Reserved interrupt 241 */
  Reserved242_IRQn             = 226,              /**< Reserved interrupt 242 */
  Reserved243_IRQn             = 227,              /**< Reserved interrupt 243 */
  Reserved244_IRQn             = 228,              /**< Reserved interrupt 244 */
  Reserved245_IRQn             = 229,              /**< Reserved interrupt 245 */
  Reserved246_IRQn             = 230,              /**< Reserved interrupt 246 */
  Reserved247_IRQn             = 231,              /**< Reserved interrupt 247 */
  Reserved248_IRQn             = 232,              /**< Reserved interrupt 248 */
  Reserved249_IRQn             = 233,              /**< Reserved interrupt 249 */
  Reserved250_IRQn             = 234,              /**< Reserved interrupt 250 */
  Reserved251_IRQn             = 235,              /**< Reserved interrupt 251 */
  Reserved252_IRQn             = 236,              /**< Reserved interrupt 252 */
  Reserved253_IRQn             = 237,              /**< Reserved interrupt 253 */
  Reserved254_IRQn             = 238,              /**< Reserved interrupt 254 */
  Reserved255_IRQn             = 239,              /**< Reserved interrupt 255 */
  Reserved256_IRQn             = 240,              /**< Reserved interrupt 256 */
  Reserved257_IRQn             = 241,              /**< Reserved interrupt 257 */
  Reserved258_IRQn             = 242,              /**< Reserved interrupt 258 */
  Reserved259_IRQn             = 243,              /**< Reserved interrupt 259 */
  Reserved260_IRQn             = 244,              /**< Reserved interrupt 260 */
  Reserved261_IRQn             = 245,              /**< Reserved interrupt 261 */
  Reserved262_IRQn             = 246,              /**< Reserved interrupt 262 */
  Reserved263_IRQn             = 247,              /**< Reserved interrupt 263 */
  Reserved264_IRQn             = 248,              /**< Reserved interrupt 264 */
  Reserved265_IRQn             = 249,              /**< Reserved interrupt 265 */
  Reserved266_IRQn             = 250,              /**< Reserved interrupt 266 */
  Reserved267_IRQn             = 251,              /**< Reserved interrupt 267 */
  Reserved268_IRQn             = 252,              /**< Reserved interrupt 268 */
  Reserved269_IRQn             = 253,              /**< Reserved interrupt 269 */
  Reserved270_IRQn             = 254,              /**< Reserved interrupt 270 */
  Reserved271_IRQn             = 255,              /**< Reserved interrupt 271 */
  Reserved272_IRQn             = 256,              /**< Reserved interrupt 272 */
  Reserved273_IRQn             = 257,              /**< Reserved interrupt 273 */
  Reserved274_IRQn             = 258,              /**< Reserved interrupt 274 */
  Reserved275_IRQn             = 259,              /**< Reserved interrupt 275 */
  Reserved276_IRQn             = 260,              /**< Reserved interrupt 276 */
  Reserved277_IRQn             = 261,              /**< Reserved interrupt 277 */
  Reserved278_IRQn             = 262,              /**< Reserved interrupt 278 */
  Reserved279_IRQn             = 263,              /**< Reserved interrupt 279 */
  Reserved280_IRQn             = 264,              /**< Reserved interrupt 280 */
  Reserved281_IRQn             = 265,              /**< Reserved interrupt 281 */
  Reserved282_IRQn             = 266,              /**< Reserved interrupt 282 */
  Reserved283_IRQn             = 267,              /**< Reserved interrupt 283 */
  Reserved284_IRQn             = 268,              /**< Reserved interrupt 284 */
  Reserved285_IRQn             = 269,              /**< Reserved interrupt 285 */
  Reserved286_IRQn             = 270,              /**< Reserved interrupt 286 */
  Reserved287_IRQn             = 271,              /**< Reserved interrupt 287 */
  Reserved288_IRQn             = 272,              /**< Reserved interrupt 288 */
  Reserved289_IRQn             = 273,              /**< Reserved interrupt 289 */
  Reserved290_IRQn             = 274,              /**< Reserved interrupt 290 */
  Reserved291_IRQn             = 275,              /**< Reserved interrupt 291 */
  Reserved292_IRQn             = 276,              /**< Reserved interrupt 292 */
  Reserved293_IRQn             = 277,              /**< Reserved interrupt 293 */
  Reserved294_IRQn             = 278,              /**< Reserved interrupt 294 */
  Reserved295_IRQn             = 279,              /**< Reserved interrupt 295 */
  Reserved296_IRQn             = 280,              /**< Reserved interrupt 296 */
  Reserved297_IRQn             = 281,              /**< Reserved interrupt 297 */
  Reserved298_IRQn             = 282,              /**< Reserved interrupt 298 */
  Reserved299_IRQn             = 283,              /**< Reserved interrupt 299 */
  Reserved300_IRQn             = 284,              /**< Reserved interrupt 300 */
  Reserved301_IRQn             = 285,              /**< Reserved interrupt 301 */
  Reserved302_IRQn             = 286,              /**< Reserved interrupt 302 */
  Reserved303_IRQn             = 287,              /**< Reserved interrupt 303 */
  Reserved304_IRQn             = 288,              /**< Reserved interrupt 304 */
  Reserved305_IRQn             = 289,              /**< Reserved interrupt 305 */
  Reserved306_IRQn             = 290,              /**< Reserved interrupt 306 */
  Reserved307_IRQn             = 291,              /**< Reserved interrupt 307 */
  Reserved308_IRQn             = 292,              /**< Reserved interrupt 308 */
  Reserved309_IRQn             = 293,              /**< Reserved interrupt 309 */
  Reserved310_IRQn             = 294,              /**< Reserved interrupt 310 */
  Reserved311_IRQn             = 295,              /**< Reserved interrupt 311 */
  Reserved312_IRQn             = 296,              /**< Reserved interrupt 312 */
  Reserved313_IRQn             = 297,              /**< Reserved interrupt 313 */
  Reserved314_IRQn             = 298,              /**< Reserved interrupt 314 */
  Reserved315_IRQn             = 299,              /**< Reserved interrupt 315 */
  Reserved316_IRQn             = 300,              /**< Reserved interrupt 316 */
  Reserved317_IRQn             = 301,              /**< Reserved interrupt 317 */
  Reserved318_IRQn             = 302,              /**< Reserved interrupt 318 */
  Reserved319_IRQn             = 303,              /**< Reserved interrupt 319 */
  Reserved320_IRQn             = 304,              /**< Reserved interrupt 320 */
  Reserved321_IRQn             = 305,              /**< Reserved interrupt 321 */
  Reserved322_IRQn             = 306,              /**< Reserved interrupt 322 */
  Reserved323_IRQn             = 307,              /**< Reserved interrupt 323 */
  Reserved324_IRQn             = 308,              /**< Reserved interrupt 324 */
  Reserved325_IRQn             = 309,              /**< Reserved interrupt 325 */
  Reserved326_IRQn             = 310,              /**< Reserved interrupt 326 */
  Reserved327_IRQn             = 311,              /**< Reserved interrupt 327 */
  Reserved328_IRQn             = 312,              /**< Reserved interrupt 328 */
  Reserved329_IRQn             = 313,              /**< Reserved interrupt 329 */
  Reserved330_IRQn             = 314,              /**< Reserved interrupt 330 */
  Reserved331_IRQn             = 315,              /**< Reserved interrupt 331 */
  Reserved332_IRQn             = 316,              /**< Reserved interrupt 332 */
  Reserved333_IRQn             = 317,              /**< Reserved interrupt 333 */
  Reserved334_IRQn             = 318,              /**< Reserved interrupt 334 */
  Reserved335_IRQn             = 319,              /**< Reserved interrupt 335 */
  Reserved336_IRQn             = 320,              /**< Reserved interrupt 336 */
  Reserved337_IRQn             = 321,              /**< Reserved interrupt 337 */
  Reserved338_IRQn             = 322,              /**< Reserved interrupt 338 */
  Reserved339_IRQn             = 323,              /**< Reserved interrupt 339 */
  Reserved340_IRQn             = 324,              /**< Reserved interrupt 340 */
  Reserved341_IRQn             = 325,              /**< Reserved interrupt 341 */
  Reserved342_IRQn             = 326,              /**< Reserved interrupt 342 */
  Reserved343_IRQn             = 327,              /**< Reserved interrupt 343 */
  Reserved344_IRQn             = 328,              /**< Reserved interrupt 344 */
  Reserved345_IRQn             = 329,              /**< Reserved interrupt 345 */
  Reserved346_IRQn             = 330,              /**< Reserved interrupt 346 */
  Reserved347_IRQn             = 331,              /**< Reserved interrupt 347 */
  Reserved348_IRQn             = 332,              /**< Reserved interrupt 348 */
  Reserved349_IRQn             = 333,              /**< Reserved interrupt 349 */
  Reserved350_IRQn             = 334,              /**< Reserved interrupt 350 */
  Reserved351_IRQn             = 335,              /**< Reserved interrupt 351 */
  Reserved352_IRQn             = 336,              /**< Reserved interrupt 352 */
  Reserved353_IRQn             = 337,              /**< Reserved interrupt 353 */
  Reserved354_IRQn             = 338,              /**< Reserved interrupt 354 */
  Reserved355_IRQn             = 339,              /**< Reserved interrupt 355 */
  Reserved356_IRQn             = 340,              /**< Reserved interrupt 356 */
  Reserved357_IRQn             = 341,              /**< Reserved interrupt 357 */
  Reserved358_IRQn             = 342,              /**< Reserved interrupt 358 */
  Reserved359_IRQn             = 343,              /**< Reserved interrupt 359 */
  Reserved360_IRQn             = 344,              /**< Reserved interrupt 360 */
  Reserved361_IRQn             = 345,              /**< Reserved interrupt 361 */
  Reserved362_IRQn             = 346,              /**< Reserved interrupt 362 */
  Reserved363_IRQn             = 347,              /**< Reserved interrupt 363 */
  Reserved364_IRQn             = 348,              /**< Reserved interrupt 364 */
  Reserved365_IRQn             = 349,              /**< Reserved interrupt 365 */
  Reserved366_IRQn             = 350,              /**< Reserved interrupt 366 */
  Reserved367_IRQn             = 351,              /**< Reserved interrupt 367 */
  Reserved368_IRQn             = 352,              /**< Reserved interrupt 368 */
  Reserved369_IRQn             = 353,              /**< Reserved interrupt 369 */
  Reserved370_IRQn             = 354,              /**< Reserved interrupt 370 */
  Reserved371_IRQn             = 355,              /**< Reserved interrupt 371 */
  Reserved372_IRQn             = 356,              /**< Reserved interrupt 372 */
  Reserved373_IRQn             = 357,              /**< Reserved interrupt 373 */
  Reserved374_IRQn             = 358,              /**< Reserved interrupt 374 */
  Reserved375_IRQn             = 359,              /**< Reserved interrupt 375 */
  Reserved376_IRQn             = 360,              /**< Reserved interrupt 376 */
  Reserved377_IRQn             = 361,              /**< Reserved interrupt 377 */
  Reserved378_IRQn             = 362,              /**< Reserved interrupt 378 */
  Reserved379_IRQn             = 363,              /**< Reserved interrupt 379 */
  Reserved380_IRQn             = 364,              /**< Reserved interrupt 380 */
  Reserved381_IRQn             = 365,              /**< Reserved interrupt 381 */
  Reserved382_IRQn             = 366,              /**< Reserved interrupt 382 */
  Reserved383_IRQn             = 367,              /**< Reserved interrupt 383 */
  Reserved384_IRQn             = 368,              /**< Reserved interrupt 384 */
  Reserved385_IRQn             = 369,              /**< Reserved interrupt 385 */
  Reserved386_IRQn             = 370,              /**< Reserved interrupt 386 */
  Reserved387_IRQn             = 371,              /**< Reserved interrupt 387 */
  Reserved388_IRQn             = 372,              /**< Reserved interrupt 388 */
  Reserved389_IRQn             = 373,              /**< Reserved interrupt 389 */
  Reserved390_IRQn             = 374,              /**< Reserved interrupt 390 */
  Reserved391_IRQn             = 375,              /**< Reserved interrupt 391 */
  Reserved392_IRQn             = 376,              /**< Reserved interrupt 392 */
  Reserved393_IRQn             = 377,              /**< Reserved interrupt 393 */
  Reserved394_IRQn             = 378,              /**< Reserved interrupt 394 */
  Reserved395_IRQn             = 379,              /**< Reserved interrupt 395 */
  Reserved396_IRQn             = 380,              /**< Reserved interrupt 396 */
  Reserved397_IRQn             = 381,              /**< Reserved interrupt 397 */
  Reserved398_IRQn             = 382,              /**< Reserved interrupt 398 */
  Reserved399_IRQn             = 383,              /**< Reserved interrupt 399 */
  Reserved400_IRQn             = 384,              /**< Reserved interrupt 400 */
  Reserved401_IRQn             = 385,              /**< Reserved interrupt 401 */
  Reserved402_IRQn             = 386,              /**< Reserved interrupt 402 */
  Reserved403_IRQn             = 387,              /**< Reserved interrupt 403 */
  Reserved404_IRQn             = 388,              /**< Reserved interrupt 404 */
  Reserved405_IRQn             = 389,              /**< Reserved interrupt 405 */
  Reserved406_IRQn             = 390,              /**< Reserved interrupt 406 */
  Reserved407_IRQn             = 391,              /**< Reserved interrupt 407 */
  Reserved408_IRQn             = 392,              /**< Reserved interrupt 408 */
  Reserved409_IRQn             = 393,              /**< Reserved interrupt 409 */
  Reserved410_IRQn             = 394,              /**< Reserved interrupt 410 */
  Reserved411_IRQn             = 395,              /**< Reserved interrupt 411 */
  Reserved412_IRQn             = 396,              /**< Reserved interrupt 412 */
  Reserved413_IRQn             = 397,              /**< Reserved interrupt 413 */
  Reserved414_IRQn             = 398,              /**< Reserved interrupt 414 */
  Reserved415_IRQn             = 399,              /**< Reserved interrupt 415 */
  Reserved416_IRQn             = 400,              /**< Reserved interrupt 416 */
  Reserved417_IRQn             = 401,              /**< Reserved interrupt 417 */
  Reserved418_IRQn             = 402,              /**< Reserved interrupt 418 */
  Reserved419_IRQn             = 403,              /**< Reserved interrupt 419 */
  Reserved420_IRQn             = 404,              /**< Reserved interrupt 420 */
  Reserved421_IRQn             = 405,              /**< Reserved interrupt 421 */
  Reserved422_IRQn             = 406,              /**< Reserved interrupt 422 */
  Reserved423_IRQn             = 407,              /**< Reserved interrupt 423 */
  Reserved424_IRQn             = 408,              /**< Reserved interrupt 424 */
  Reserved425_IRQn             = 409,              /**< Reserved interrupt 425 */
  Reserved426_IRQn             = 410,              /**< Reserved interrupt 426 */
  Reserved427_IRQn             = 411,              /**< Reserved interrupt 427 */
  Reserved428_IRQn             = 412,              /**< Reserved interrupt 428 */
  Reserved429_IRQn             = 413,              /**< Reserved interrupt 429 */
  Reserved430_IRQn             = 414,              /**< Reserved interrupt 430 */
  Reserved431_IRQn             = 415,              /**< Reserved interrupt 431 */
  Reserved432_IRQn             = 416,              /**< Reserved interrupt 432 */
  Reserved433_IRQn             = 417,              /**< Reserved interrupt 433 */
  Reserved434_IRQn             = 418,              /**< Reserved interrupt 434 */
  Reserved435_IRQn             = 419,              /**< Reserved interrupt 435 */
  Reserved436_IRQn             = 420,              /**< Reserved interrupt 436 */
  Reserved437_IRQn             = 421,              /**< Reserved interrupt 437 */
  Reserved438_IRQn             = 422,              /**< Reserved interrupt 438 */
  Reserved439_IRQn             = 423,              /**< Reserved interrupt 439 */
  Reserved440_IRQn             = 424,              /**< Reserved interrupt 440 */
  Reserved441_IRQn             = 425,              /**< Reserved interrupt 441 */
  Reserved442_IRQn             = 426,              /**< Reserved interrupt 442 */
  Reserved443_IRQn             = 427,              /**< Reserved interrupt 443 */
  Reserved444_IRQn             = 428,              /**< Reserved interrupt 444 */
  Reserved445_IRQn             = 429,              /**< Reserved interrupt 445 */
  Reserved446_IRQn             = 430,              /**< Reserved interrupt 446 */
  Reserved447_IRQn             = 431,              /**< Reserved interrupt 447 */
  Reserved448_IRQn             = 432,              /**< Reserved interrupt 448 */
  Reserved449_IRQn             = 433,              /**< Reserved interrupt 449 */
  Reserved450_IRQn             = 434,              /**< Reserved interrupt 450 */
  Reserved451_IRQn             = 435,              /**< Reserved interrupt 451 */
  Reserved452_IRQn             = 436,              /**< Reserved interrupt 452 */
  Reserved453_IRQn             = 437,              /**< Reserved interrupt 453 */
  Reserved454_IRQn             = 438,              /**< Reserved interrupt 454 */
  Reserved455_IRQn             = 439,              /**< Reserved interrupt 455 */
  Reserved456_IRQn             = 440,              /**< Reserved interrupt 456 */
  Reserved457_IRQn             = 441,              /**< Reserved interrupt 457 */
  Reserved458_IRQn             = 442,              /**< Reserved interrupt 458 */
  Reserved459_IRQn             = 443,              /**< Reserved interrupt 459 */
  Reserved460_IRQn             = 444,              /**< Reserved interrupt 460 */
  Reserved461_IRQn             = 445,              /**< Reserved interrupt 461 */
  Reserved462_IRQn             = 446,              /**< Reserved interrupt 462 */
  Reserved463_IRQn             = 447,              /**< Reserved interrupt 463 */
  Reserved464_IRQn             = 448,              /**< Reserved interrupt 464 */
  Reserved465_IRQn             = 449,              /**< Reserved interrupt 465 */
  Reserved466_IRQn             = 450,              /**< Reserved interrupt 466 */
  Reserved467_IRQn             = 451,              /**< Reserved interrupt 467 */
  Reserved468_IRQn             = 452,              /**< Reserved interrupt 468 */
  Reserved469_IRQn             = 453,              /**< Reserved interrupt 469 */
  Reserved470_IRQn             = 454,              /**< Reserved interrupt 470 */
  Reserved471_IRQn             = 455,              /**< Reserved interrupt 471 */
  Reserved472_IRQn             = 456,              /**< Reserved interrupt 472 */
  Reserved473_IRQn             = 457,              /**< Reserved interrupt 473 */
  Reserved474_IRQn             = 458,              /**< Reserved interrupt 474 */
  Reserved475_IRQn             = 459,              /**< Reserved interrupt 475 */
  Reserved476_IRQn             = 460,              /**< Reserved interrupt 476 */
  Reserved477_IRQn             = 461,              /**< Reserved interrupt 477 */
  Reserved478_IRQn             = 462,              /**< Reserved interrupt 478 */
  Reserved479_IRQn             = 463,              /**< Reserved interrupt 479 */
  Reserved480_IRQn             = 464,              /**< Reserved interrupt 480 */
  Reserved481_IRQn             = 465,              /**< Reserved interrupt 481 */
  Reserved482_IRQn             = 466,              /**< Reserved interrupt 482 */
  Reserved483_IRQn             = 467,              /**< Reserved interrupt 483 */
  Reserved484_IRQn             = 468,              /**< Reserved interrupt 484 */
  Reserved485_IRQn             = 469,              /**< Reserved interrupt 485 */
  Reserved486_IRQn             = 470,              /**< Reserved interrupt 486 */
  Reserved487_IRQn             = 471,              /**< Reserved interrupt 487 */
  Reserved488_IRQn             = 472,              /**< Reserved interrupt 488 */
  Reserved489_IRQn             = 473,              /**< Reserved interrupt 489 */
  Reserved490_IRQn             = 474,              /**< Reserved interrupt 490 */
  Reserved491_IRQn             = 475,              /**< Reserved interrupt 491 */
  Reserved492_IRQn             = 476,              /**< Reserved interrupt 492 */
  Reserved493_IRQn             = 477,              /**< Reserved interrupt 493 */
  Reserved494_IRQn             = 478,              /**< Reserved interrupt 494 */
  Reserved495_IRQn             = 479,              /**< Reserved interrupt 495 */
  Reserved496_IRQn             = 480,              /**< Reserved interrupt 496 */
  Reserved497_IRQn             = 481,              /**< Reserved interrupt 497 */
  Reserved498_IRQn             = 482,              /**< Reserved interrupt 498 */
  Reserved499_IRQn             = 483,              /**< Reserved interrupt 499 */
  Reserved500_IRQn             = 484,              /**< Reserved interrupt 500 */
  Reserved501_IRQn             = 485,              /**< Reserved interrupt 501 */
  Reserved502_IRQn             = 486,              /**< Reserved interrupt 502 */
  Reserved503_IRQn             = 487,              /**< Reserved interrupt 503 */
  Reserved504_IRQn             = 488,              /**< Reserved interrupt 504 */
  Reserved505_IRQn             = 489,              /**< Reserved interrupt 505 */
  Reserved506_IRQn             = 490,              /**< Reserved interrupt 506 */
  Reserved507_IRQn             = 491,              /**< Reserved interrupt 507 */
  Reserved508_IRQn             = 492,              /**< Reserved interrupt 508 */
  Reserved509_IRQn             = 493,              /**< Reserved interrupt 509 */
  Reserved510_IRQn             = 494,              /**< Reserved interrupt 510 */
  Reserved511_IRQn             = 495,              /**< Reserved interrupt 511 */
  Reserved512_IRQn             = 496,              /**< Reserved interrupt 512 */
  Reserved513_IRQn             = 497,              /**< Reserved interrupt 513 */
  Reserved514_IRQn             = 498,              /**< Reserved interrupt 514 */
  Reserved515_IRQn             = 499,              /**< Reserved interrupt 515 */
  Reserved516_IRQn             = 500,              /**< Reserved interrupt 516 */
  Reserved517_IRQn             = 501,              /**< Reserved interrupt 517 */
  Reserved518_IRQn             = 502,              /**< Reserved interrupt 518 */
  Reserved519_IRQn             = 503,              /**< Reserved interrupt 519 */
  Reserved520_IRQn             = 504,              /**< Reserved interrupt 520 */
  Reserved521_IRQn             = 505,              /**< Reserved interrupt 521 */
  Reserved522_IRQn             = 506,              /**< Reserved interrupt 522 */
  Reserved523_IRQn             = 507,              /**< Reserved interrupt 523 */
  Reserved524_IRQn             = 508,              /**< Reserved interrupt 524 */
  Reserved525_IRQn             = 509,              /**< Reserved interrupt 525 */
  Reserved526_IRQn             = 510,              /**< Reserved interrupt 526 */
  Reserved527_IRQn             = 511,              /**< Reserved interrupt 527 */
  Reserved528_IRQn             = 512,              /**< Reserved interrupt 528 */
  Reserved529_IRQn             = 513,              /**< Reserved interrupt 529 */
  Reserved530_IRQn             = 514,              /**< Reserved interrupt 530 */
  Reserved531_IRQn             = 515,              /**< Reserved interrupt 531 */
  Reserved532_IRQn             = 516,              /**< Reserved interrupt 532 */
  Reserved533_IRQn             = 517,              /**< Reserved interrupt 533 */
  Reserved534_IRQn             = 518,              /**< Reserved interrupt 534 */
  Reserved535_IRQn             = 519,              /**< Reserved interrupt 535 */
  Reserved536_IRQn             = 520,              /**< Reserved interrupt 536 */
  Reserved537_IRQn             = 521,              /**< Reserved interrupt 537 */
  Reserved538_IRQn             = 522,              /**< Reserved interrupt 538 */
  Reserved539_IRQn             = 523,              /**< Reserved interrupt 539 */
  Reserved540_IRQn             = 524,              /**< Reserved interrupt 540 */
  Reserved541_IRQn             = 525,              /**< Reserved interrupt 541 */
  Reserved542_IRQn             = 526,              /**< Reserved interrupt 542 */
  Reserved543_IRQn             = 527,              /**< Reserved interrupt 543 */
  Reserved544_IRQn             = 528,              /**< Reserved interrupt 544 */
  Reserved545_IRQn             = 529,              /**< Reserved interrupt 545 */
  Reserved546_IRQn             = 530,              /**< Reserved interrupt 546 */
  Reserved547_IRQn             = 531,              /**< Reserved interrupt 547 */
  Reserved548_IRQn             = 532,              /**< Reserved interrupt 548 */
  Reserved549_IRQn             = 533,              /**< Reserved interrupt 549 */
  Reserved550_IRQn             = 534,              /**< Reserved interrupt 550 */
  Reserved551_IRQn             = 535,              /**< Reserved interrupt 551 */
  Reserved552_IRQn             = 536,              /**< Reserved interrupt 552 */
  Reserved553_IRQn             = 537,              /**< Reserved interrupt 553 */
  Reserved554_IRQn             = 538,              /**< Reserved interrupt 554 */
  Reserved555_IRQn             = 539,              /**< Reserved interrupt 555 */
  Reserved556_IRQn             = 540,              /**< Reserved interrupt 556 */
  Reserved557_IRQn             = 541,              /**< Reserved interrupt 557 */
  Reserved558_IRQn             = 542,              /**< Reserved interrupt 558 */
  Reserved559_IRQn             = 543,              /**< Reserved interrupt 559 */
  Reserved560_IRQn             = 544,              /**< Reserved interrupt 560 */
  Reserved561_IRQn             = 545,              /**< Reserved interrupt 561 */
  Reserved562_IRQn             = 546,              /**< Reserved interrupt 562 */
  Reserved563_IRQn             = 547,              /**< Reserved interrupt 563 */
  Reserved564_IRQn             = 548,              /**< Reserved interrupt 564 */
  Reserved565_IRQn             = 549,              /**< Reserved interrupt 565 */
  Reserved566_IRQn             = 550,              /**< Reserved interrupt 566 */
  Reserved567_IRQn             = 551,              /**< Reserved interrupt 567 */
  Reserved568_IRQn             = 552,              /**< Reserved interrupt 568 */
  Reserved569_IRQn             = 553,              /**< Reserved interrupt 569 */
  Reserved570_IRQn             = 554,              /**< Reserved interrupt 570 */
  Reserved571_IRQn             = 555,              /**< Reserved interrupt 571 */
  Reserved572_IRQn             = 556,              /**< Reserved interrupt 572 */
  Reserved573_IRQn             = 557,              /**< Reserved interrupt 573 */
  Reserved574_IRQn             = 558,              /**< Reserved interrupt 574 */
  Reserved575_IRQn             = 559,              /**< Reserved interrupt 575 */
  Reserved576_IRQn             = 560,              /**< Reserved interrupt 576 */
  Reserved577_IRQn             = 561,              /**< Reserved interrupt 577 */
  Reserved578_IRQn             = 562,              /**< Reserved interrupt 578 */
  Reserved579_IRQn             = 563,              /**< Reserved interrupt 579 */
  Reserved580_IRQn             = 564,              /**< Reserved interrupt 580 */
  Reserved581_IRQn             = 565,              /**< Reserved interrupt 581 */
  Reserved582_IRQn             = 566,              /**< Reserved interrupt 582 */
  Reserved583_IRQn             = 567,              /**< Reserved interrupt 583 */
  Reserved584_IRQn             = 568,              /**< Reserved interrupt 584 */
  Reserved585_IRQn             = 569,              /**< Reserved interrupt 585 */
  Reserved586_IRQn             = 570,              /**< Reserved interrupt 586 */
  Reserved587_IRQn             = 571,              /**< Reserved interrupt 587 */
  Reserved588_IRQn             = 572,              /**< Reserved interrupt 588 */
  Reserved589_IRQn             = 573,              /**< Reserved interrupt 589 */
  Reserved590_IRQn             = 574,              /**< Reserved interrupt 590 */
  Reserved591_IRQn             = 575,              /**< Reserved interrupt 591 */
  Reserved592_IRQn             = 576,              /**< Reserved interrupt 592 */
  Reserved593_IRQn             = 577,              /**< Reserved interrupt 593 */
  Reserved594_IRQn             = 578,              /**< Reserved interrupt 594 */
  Reserved595_IRQn             = 579,              /**< Reserved interrupt 595 */
  Reserved596_IRQn             = 580,              /**< Reserved interrupt 596 */
  Reserved597_IRQn             = 581,              /**< Reserved interrupt 597 */
  Reserved598_IRQn             = 582,              /**< Reserved interrupt 598 */
  Reserved599_IRQn             = 583,              /**< Reserved interrupt 599 */
  Reserved600_IRQn             = 584,              /**< Reserved interrupt 600 */
  Reserved601_IRQn             = 585,              /**< Reserved interrupt 601 */
  Reserved602_IRQn             = 586,              /**< Reserved interrupt 602 */
  Reserved603_IRQn             = 587,              /**< Reserved interrupt 603 */
  Reserved604_IRQn             = 588,              /**< Reserved interrupt 604 */
  Reserved605_IRQn             = 589,              /**< Reserved interrupt 605 */
  Reserved606_IRQn             = 590,              /**< Reserved interrupt 606 */
  Reserved607_IRQn             = 591,              /**< Reserved interrupt 607 */
  Reserved608_IRQn             = 592,              /**< Reserved interrupt 608 */
  Reserved609_IRQn             = 593,              /**< Reserved interrupt 609 */
  Reserved610_IRQn             = 594,              /**< Reserved interrupt 610 */
  Reserved611_IRQn             = 595,              /**< Reserved interrupt 611 */
  Reserved612_IRQn             = 596,              /**< Reserved interrupt 612 */
  Reserved613_IRQn             = 597,              /**< Reserved interrupt 613 */
  Reserved614_IRQn             = 598,              /**< Reserved interrupt 614 */
  Reserved615_IRQn             = 599,              /**< Reserved interrupt 615 */
  Reserved616_IRQn             = 600,              /**< Reserved interrupt 616 */
  Reserved617_IRQn             = 601,              /**< Reserved interrupt 617 */
  Reserved618_IRQn             = 602,              /**< Reserved interrupt 618 */
  Reserved619_IRQn             = 603,              /**< Reserved interrupt 619 */
  Reserved620_IRQn             = 604,              /**< Reserved interrupt 620 */
  Reserved621_IRQn             = 605,              /**< Reserved interrupt 621 */
  Reserved622_IRQn             = 606,              /**< Reserved interrupt 622 */
  Reserved623_IRQn             = 607,              /**< Reserved interrupt 623 */
  Reserved624_IRQn             = 608,              /**< Reserved interrupt 624 */
  Reserved625_IRQn             = 609,              /**< Reserved interrupt 625 */
  Reserved626_IRQn             = 610,              /**< Reserved interrupt 626 */
  Reserved627_IRQn             = 611,              /**< Reserved interrupt 627 */
  Reserved628_IRQn             = 612,              /**< Reserved interrupt 628 */
  Reserved629_IRQn             = 613,              /**< Reserved interrupt 629 */
  Reserved630_IRQn             = 614,              /**< Reserved interrupt 630 */
  Reserved631_IRQn             = 615,              /**< Reserved interrupt 631 */
  Reserved632_IRQn             = 616,              /**< Reserved interrupt 632 */
  Reserved633_IRQn             = 617,              /**< Reserved interrupt 633 */
  Reserved634_IRQn             = 618,              /**< Reserved interrupt 634 */
  Reserved635_IRQn             = 619,              /**< Reserved interrupt 635 */
  Reserved636_IRQn             = 620,              /**< Reserved interrupt 636 */
  Reserved637_IRQn             = 621,              /**< Reserved interrupt 637 */
  Reserved638_IRQn             = 622,              /**< Reserved interrupt 638 */
  Reserved639_IRQn             = 623,              /**< Reserved interrupt 639 */
  Reserved640_IRQn             = 624,              /**< Reserved interrupt 640 */
  Reserved641_IRQn             = 625,              /**< Reserved interrupt 641 */
  Reserved642_IRQn             = 626,              /**< Reserved interrupt 642 */
  Reserved643_IRQn             = 627,              /**< Reserved interrupt 643 */
  Reserved644_IRQn             = 628,              /**< Reserved interrupt 644 */
  Reserved645_IRQn             = 629,              /**< Reserved interrupt 645 */
  Reserved646_IRQn             = 630,              /**< Reserved interrupt 646 */
  Reserved647_IRQn             = 631,              /**< Reserved interrupt 647 */
  Reserved648_IRQn             = 632,              /**< Reserved interrupt 648 */
  Reserved649_IRQn             = 633,              /**< Reserved interrupt 649 */
  Reserved650_IRQn             = 634,              /**< Reserved interrupt 650 */
  Reserved651_IRQn             = 635,              /**< Reserved interrupt 651 */
  Reserved652_IRQn             = 636,              /**< Reserved interrupt 652 */
  Reserved653_IRQn             = 637,              /**< Reserved interrupt 653 */
  Reserved654_IRQn             = 638,              /**< Reserved interrupt 654 */
  Reserved655_IRQn             = 639,              /**< Reserved interrupt 655 */
  Reserved656_IRQn             = 640,              /**< Reserved interrupt 656 */
  Reserved657_IRQn             = 641,              /**< Reserved interrupt 657 */
  Reserved658_IRQn             = 642,              /**< Reserved interrupt 658 */
  Reserved659_IRQn             = 643,              /**< Reserved interrupt 659 */
  Reserved660_IRQn             = 644,              /**< Reserved interrupt 660 */
  Reserved661_IRQn             = 645,              /**< Reserved interrupt 661 */
  Reserved662_IRQn             = 646,              /**< Reserved interrupt 662 */
  Reserved663_IRQn             = 647,              /**< Reserved interrupt 663 */
  Reserved664_IRQn             = 648,              /**< Reserved interrupt 664 */
  Reserved665_IRQn             = 649,              /**< Reserved interrupt 665 */
  Reserved666_IRQn             = 650,              /**< Reserved interrupt 666 */
  Reserved667_IRQn             = 651,              /**< Reserved interrupt 667 */
  Reserved668_IRQn             = 652,              /**< Reserved interrupt 668 */
  Reserved669_IRQn             = 653,              /**< Reserved interrupt 669 */
  Reserved670_IRQn             = 654,              /**< Reserved interrupt 670 */
  Reserved671_IRQn             = 655,              /**< Reserved interrupt 671 */
  Reserved672_IRQn             = 656,              /**< Reserved interrupt 672 */
  Reserved673_IRQn             = 657,              /**< Reserved interrupt 673 */
  Reserved674_IRQn             = 658,              /**< Reserved interrupt 674 */
  Reserved675_IRQn             = 659,              /**< Reserved interrupt 675 */
  Reserved676_IRQn             = 660,              /**< Reserved interrupt 676 */
  Reserved677_IRQn             = 661,              /**< Reserved interrupt 677 */
  Reserved678_IRQn             = 662,              /**< Reserved interrupt 678 */
  Reserved679_IRQn             = 663,              /**< Reserved interrupt 679 */
  Reserved680_IRQn             = 664,              /**< Reserved interrupt 680 */
  Reserved681_IRQn             = 665,              /**< Reserved interrupt 681 */
  Reserved682_IRQn             = 666,              /**< Reserved interrupt 682 */
  Reserved683_IRQn             = 667,              /**< Reserved interrupt 683 */
  Reserved684_IRQn             = 668,              /**< Reserved interrupt 684 */
  Reserved685_IRQn             = 669,              /**< Reserved interrupt 685 */
  Reserved686_IRQn             = 670,              /**< Reserved interrupt 686 */
  Reserved687_IRQn             = 671,              /**< Reserved interrupt 687 */
  Reserved688_IRQn             = 672,              /**< Reserved interrupt 688 */
  Reserved689_IRQn             = 673,              /**< Reserved interrupt 689 */
  Reserved690_IRQn             = 674,              /**< Reserved interrupt 690 */
  Reserved691_IRQn             = 675,              /**< Reserved interrupt 691 */
  Reserved692_IRQn             = 676,              /**< Reserved interrupt 692 */
  Reserved693_IRQn             = 677,              /**< Reserved interrupt 693 */
  Reserved694_IRQn             = 678,              /**< Reserved interrupt 694 */
  Reserved695_IRQn             = 679,              /**< Reserved interrupt 695 */
  Reserved696_IRQn             = 680,              /**< Reserved interrupt 696 */
  Reserved697_IRQn             = 681,              /**< Reserved interrupt 697 */
  Reserved698_IRQn             = 682,              /**< Reserved interrupt 698 */
  Reserved699_IRQn             = 683,              /**< Reserved interrupt 699 */
  Reserved700_IRQn             = 684,              /**< Reserved interrupt 700 */
  Reserved701_IRQn             = 685,              /**< Reserved interrupt 701 */
  Reserved702_IRQn             = 686,              /**< Reserved interrupt 702 */
  Reserved703_IRQn             = 687,              /**< Reserved interrupt 703 */
  Reserved704_IRQn             = 688,              /**< Reserved interrupt 704 */
  Reserved705_IRQn             = 689,              /**< Reserved interrupt 705 */
  Reserved706_IRQn             = 690,              /**< Reserved interrupt 706 */
  Reserved707_IRQn             = 691,              /**< Reserved interrupt 707 */
  Reserved708_IRQn             = 692,              /**< Reserved interrupt 708 */
  Reserved709_IRQn             = 693,              /**< Reserved interrupt 709 */
  Reserved710_IRQn             = 694,              /**< Reserved interrupt 710 */
  Reserved711_IRQn             = 695,              /**< Reserved interrupt 711 */
  Reserved712_IRQn             = 696,              /**< Reserved interrupt 712 */
  Reserved713_IRQn             = 697,              /**< Reserved interrupt 713 */
  Reserved714_IRQn             = 698,              /**< Reserved interrupt 714 */
  Reserved715_IRQn             = 699,              /**< Reserved interrupt 715 */
  Reserved716_IRQn             = 700,              /**< Reserved interrupt 716 */
  Reserved717_IRQn             = 701,              /**< Reserved interrupt 717 */
  Reserved718_IRQn             = 702,              /**< Reserved interrupt 718 */
  Reserved719_IRQn             = 703,              /**< Reserved interrupt 719 */
  Reserved720_IRQn             = 704,              /**< Reserved interrupt 720 */
  Reserved721_IRQn             = 705,              /**< Reserved interrupt 721 */
  Reserved722_IRQn             = 706,              /**< Reserved interrupt 722 */
  Reserved723_IRQn             = 707,              /**< Reserved interrupt 723 */
  Reserved724_IRQn             = 708,              /**< Reserved interrupt 724 */
  Reserved725_IRQn             = 709,              /**< Reserved interrupt 725 */
  Reserved726_IRQn             = 710,              /**< Reserved interrupt 726 */
  Reserved727_IRQn             = 711,              /**< Reserved interrupt 727 */
  Reserved728_IRQn             = 712,              /**< Reserved interrupt 728 */
  Reserved729_IRQn             = 713,              /**< Reserved interrupt 729 */
  Reserved730_IRQn             = 714,              /**< Reserved interrupt 730 */
  Reserved731_IRQn             = 715,              /**< Reserved interrupt 731 */
  Reserved732_IRQn             = 716,              /**< Reserved interrupt 732 */
  Reserved733_IRQn             = 717,              /**< Reserved interrupt 733 */
  Reserved734_IRQn             = 718,              /**< Reserved interrupt 734 */
  Reserved735_IRQn             = 719,              /**< Reserved interrupt 735 */
  Reserved736_IRQn             = 720,              /**< Reserved interrupt 736 */
  Reserved737_IRQn             = 721,              /**< Reserved interrupt 737 */
  Reserved738_IRQn             = 722,              /**< Reserved interrupt 738 */
  Reserved739_IRQn             = 723,              /**< Reserved interrupt 739 */
  Reserved740_IRQn             = 724,              /**< Reserved interrupt 740 */
  Reserved741_IRQn             = 725,              /**< Reserved interrupt 741 */
  Reserved742_IRQn             = 726,              /**< Reserved interrupt 742 */
  Reserved743_IRQn             = 727,              /**< Reserved interrupt 743 */
  Reserved744_IRQn             = 728,              /**< Reserved interrupt 744 */
  Reserved745_IRQn             = 729,              /**< Reserved interrupt 745 */
  Reserved746_IRQn             = 730,              /**< Reserved interrupt 746 */
  Reserved747_IRQn             = 731,              /**< Reserved interrupt 747 */
  Reserved748_IRQn             = 732,              /**< Reserved interrupt 748 */
  Reserved749_IRQn             = 733,              /**< Reserved interrupt 749 */
  Reserved750_IRQn             = 734,              /**< Reserved interrupt 750 */
  Reserved751_IRQn             = 735,              /**< Reserved interrupt 751 */
  Reserved752_IRQn             = 736,              /**< Reserved interrupt 752 */
  Reserved753_IRQn             = 737,              /**< Reserved interrupt 753 */
  Reserved754_IRQn             = 738,              /**< Reserved interrupt 754 */
  Reserved755_IRQn             = 739,              /**< Reserved interrupt 755 */
  Reserved756_IRQn             = 740,              /**< Reserved interrupt 756 */
  Reserved757_IRQn             = 741,              /**< Reserved interrupt 757 */
  Reserved758_IRQn             = 742,              /**< Reserved interrupt 758 */
  Reserved759_IRQn             = 743,              /**< Reserved interrupt 759 */
  Reserved760_IRQn             = 744,              /**< Reserved interrupt 760 */
  Reserved761_IRQn             = 745,              /**< Reserved interrupt 761 */
  Reserved762_IRQn             = 746,              /**< Reserved interrupt 762 */
  Reserved763_IRQn             = 747,              /**< Reserved interrupt 763 */
  Reserved764_IRQn             = 748,              /**< Reserved interrupt 764 */
  Reserved765_IRQn             = 749,              /**< Reserved interrupt 765 */
  Reserved766_IRQn             = 750,              /**< Reserved interrupt 766 */
  Reserved767_IRQn             = 751,              /**< Reserved interrupt 767 */
  Reserved768_IRQn             = 752,              /**< Reserved interrupt 768 */
  Reserved769_IRQn             = 753,              /**< Reserved interrupt 769 */
  Reserved770_IRQn             = 754,              /**< Reserved interrupt 770 */
  Reserved771_IRQn             = 755,              /**< Reserved interrupt 771 */
  Reserved772_IRQn             = 756,              /**< Reserved interrupt 772 */
  Reserved773_IRQn             = 757,              /**< Reserved interrupt 773 */
  Reserved774_IRQn             = 758,              /**< Reserved interrupt 774 */
  Reserved775_IRQn             = 759,              /**< Reserved interrupt 775 */
  Reserved776_IRQn             = 760,              /**< Reserved interrupt 776 */
  Reserved777_IRQn             = 761,              /**< Reserved interrupt 777 */
  Reserved778_IRQn             = 762,              /**< Reserved interrupt 778 */
  Reserved779_IRQn             = 763,              /**< Reserved interrupt 779 */
  Reserved780_IRQn             = 764,              /**< Reserved interrupt 780 */
  Reserved781_IRQn             = 765,              /**< Reserved interrupt 781 */
  Reserved782_IRQn             = 766,              /**< Reserved interrupt 782 */
  Reserved783_IRQn             = 767,              /**< Reserved interrupt 783 */
  Reserved784_IRQn             = 768,              /**< Reserved interrupt 784 */
  Reserved785_IRQn             = 769,              /**< Reserved interrupt 785 */
  Reserved786_IRQn             = 770,              /**< Reserved interrupt 786 */
  Reserved787_IRQn             = 771,              /**< Reserved interrupt 787 */
  Reserved788_IRQn             = 772,              /**< Reserved interrupt 788 */
  Reserved789_IRQn             = 773,              /**< Reserved interrupt 789 */
  Reserved790_IRQn             = 774,              /**< Reserved interrupt 790 */
  Reserved791_IRQn             = 775,              /**< Reserved interrupt 791 */
  Reserved792_IRQn             = 776,              /**< Reserved interrupt 792 */
  Reserved793_IRQn             = 777,              /**< Reserved interrupt 793 */
  Reserved794_IRQn             = 778,              /**< Reserved interrupt 794 */
  Reserved795_IRQn             = 779,              /**< Reserved interrupt 795 */
  Reserved796_IRQn             = 780,              /**< Reserved interrupt 796 */
  Reserved797_IRQn             = 781,              /**< Reserved interrupt 797 */
  Reserved798_IRQn             = 782,              /**< Reserved interrupt 798 */
  Reserved799_IRQn             = 783,              /**< Reserved interrupt 799 */
  Reserved800_IRQn             = 784,              /**< Reserved interrupt 800 */
  Reserved801_IRQn             = 785,              /**< Reserved interrupt 801 */
  Reserved802_IRQn             = 786,              /**< Reserved interrupt 802 */
  Reserved803_IRQn             = 787,              /**< Reserved interrupt 803 */
  Reserved804_IRQn             = 788,              /**< Reserved interrupt 804 */
  Reserved805_IRQn             = 789,              /**< Reserved interrupt 805 */
  Reserved806_IRQn             = 790,              /**< Reserved interrupt 806 */
  Reserved807_IRQn             = 791,              /**< Reserved interrupt 807 */
  Reserved808_IRQn             = 792,              /**< Reserved interrupt 808 */
  Reserved809_IRQn             = 793,              /**< Reserved interrupt 809 */
  Reserved810_IRQn             = 794,              /**< Reserved interrupt 810 */
  Reserved811_IRQn             = 795,              /**< Reserved interrupt 811 */
  Reserved812_IRQn             = 796,              /**< Reserved interrupt 812 */
  Reserved813_IRQn             = 797,              /**< Reserved interrupt 813 */
  Reserved814_IRQn             = 798,              /**< Reserved interrupt 814 */
  Reserved815_IRQn             = 799,              /**< Reserved interrupt 815 */
  Reserved816_IRQn             = 800,              /**< Reserved interrupt 816 */
  Reserved817_IRQn             = 801,              /**< Reserved interrupt 817 */
  Reserved818_IRQn             = 802,              /**< Reserved interrupt 818 */
  Reserved819_IRQn             = 803,              /**< Reserved interrupt 819 */
  Reserved820_IRQn             = 804,              /**< Reserved interrupt 820 */
  Reserved821_IRQn             = 805,              /**< Reserved interrupt 821 */
  Reserved822_IRQn             = 806,              /**< Reserved interrupt 822 */
  Reserved823_IRQn             = 807,              /**< Reserved interrupt 823 */
  Reserved824_IRQn             = 808,              /**< Reserved interrupt 824 */
  Reserved825_IRQn             = 809,              /**< Reserved interrupt 825 */
  Reserved826_IRQn             = 810,              /**< Reserved interrupt 826 */
  Reserved827_IRQn             = 811,              /**< Reserved interrupt 827 */
  Reserved828_IRQn             = 812,              /**< Reserved interrupt 828 */
  Reserved829_IRQn             = 813,              /**< Reserved interrupt 829 */
  Reserved830_IRQn             = 814,              /**< Reserved interrupt 830 */
  Reserved831_IRQn             = 815,              /**< Reserved interrupt 831 */
  Reserved832_IRQn             = 816,              /**< Reserved interrupt 832 */
  Reserved833_IRQn             = 817,              /**< Reserved interrupt 833 */
  Reserved834_IRQn             = 818,              /**< Reserved interrupt 834 */
  Reserved835_IRQn             = 819,              /**< Reserved interrupt 835 */
  Reserved836_IRQn             = 820,              /**< Reserved interrupt 836 */
  Reserved837_IRQn             = 821,              /**< Reserved interrupt 837 */
  Reserved838_IRQn             = 822,              /**< Reserved interrupt 838 */
  Reserved839_IRQn             = 823,              /**< Reserved interrupt 839 */
  Reserved840_IRQn             = 824,              /**< Reserved interrupt 840 */
  Reserved841_IRQn             = 825,              /**< Reserved interrupt 841 */
  Reserved842_IRQn             = 826,              /**< Reserved interrupt 842 */
  Reserved843_IRQn             = 827,              /**< Reserved interrupt 843 */
  Reserved844_IRQn             = 828,              /**< Reserved interrupt 844 */
  Reserved845_IRQn             = 829,              /**< Reserved interrupt 845 */
  Reserved846_IRQn             = 830,              /**< Reserved interrupt 846 */
  Reserved847_IRQn             = 831,              /**< Reserved interrupt 847 */
  Reserved848_IRQn             = 832,              /**< Reserved interrupt 848 */
  Reserved849_IRQn             = 833,              /**< Reserved interrupt 849 */
  Reserved850_IRQn             = 834,              /**< Reserved interrupt 850 */
  Reserved851_IRQn             = 835,              /**< Reserved interrupt 851 */
  Reserved852_IRQn             = 836,              /**< Reserved interrupt 852 */
  Reserved853_IRQn             = 837,              /**< Reserved interrupt 853 */
  Reserved854_IRQn             = 838,              /**< Reserved interrupt 854 */
  Reserved855_IRQn             = 839,              /**< Reserved interrupt 855 */
  Reserved856_IRQn             = 840,              /**< Reserved interrupt 856 */
  Reserved857_IRQn             = 841,              /**< Reserved interrupt 857 */
  Reserved858_IRQn             = 842,              /**< Reserved interrupt 858 */
  Reserved859_IRQn             = 843,              /**< Reserved interrupt 859 */
  Reserved860_IRQn             = 844,              /**< Reserved interrupt 860 */
  Reserved861_IRQn             = 845,              /**< Reserved interrupt 861 */
  Reserved862_IRQn             = 846,              /**< Reserved interrupt 862 */
  Reserved863_IRQn             = 847,              /**< Reserved interrupt 863 */
  Reserved864_IRQn             = 848,              /**< Reserved interrupt 864 */
  Reserved865_IRQn             = 849,              /**< Reserved interrupt 865 */
  Reserved866_IRQn             = 850,              /**< Reserved interrupt 866 */
  Reserved867_IRQn             = 851,              /**< Reserved interrupt 867 */
  Reserved868_IRQn             = 852,              /**< Reserved interrupt 868 */
  Reserved869_IRQn             = 853,              /**< Reserved interrupt 869 */
  Reserved870_IRQn             = 854,              /**< Reserved interrupt 870 */
  Reserved871_IRQn             = 855,              /**< Reserved interrupt 871 */
  Reserved872_IRQn             = 856,              /**< Reserved interrupt 872 */
  Reserved873_IRQn             = 857,              /**< Reserved interrupt 873 */
  Reserved874_IRQn             = 858,              /**< Reserved interrupt 874 */
  Reserved875_IRQn             = 859,              /**< Reserved interrupt 875 */
  Reserved876_IRQn             = 860,              /**< Reserved interrupt 876 */
  Reserved877_IRQn             = 861,              /**< Reserved interrupt 877 */
  Reserved878_IRQn             = 862,              /**< Reserved interrupt 878 */
  Reserved879_IRQn             = 863,              /**< Reserved interrupt 879 */
  Reserved880_IRQn             = 864,              /**< Reserved interrupt 880 */
  Reserved881_IRQn             = 865,              /**< Reserved interrupt 881 */
  Reserved882_IRQn             = 866,              /**< Reserved interrupt 882 */
  Reserved883_IRQn             = 867,              /**< Reserved interrupt 883 */
  Reserved884_IRQn             = 868,              /**< Reserved interrupt 884 */
  Reserved885_IRQn             = 869,              /**< Reserved interrupt 885 */
  Reserved886_IRQn             = 870,              /**< Reserved interrupt 886 */
  Reserved887_IRQn             = 871,              /**< Reserved interrupt 887 */
  Reserved888_IRQn             = 872,              /**< Reserved interrupt 888 */
  Reserved889_IRQn             = 873,              /**< Reserved interrupt 889 */
  Reserved890_IRQn             = 874,              /**< Reserved interrupt 890 */
  Reserved891_IRQn             = 875,              /**< Reserved interrupt 891 */
  Reserved892_IRQn             = 876,              /**< Reserved interrupt 892 */
  Reserved893_IRQn             = 877,              /**< Reserved interrupt 893 */
  Reserved894_IRQn             = 878,              /**< Reserved interrupt 894 */
  Reserved895_IRQn             = 879,              /**< Reserved interrupt 895 */
  Reserved896_IRQn             = 880,              /**< Reserved interrupt 896 */
  Reserved897_IRQn             = 881,              /**< Reserved interrupt 897 */
  Reserved898_IRQn             = 882,              /**< Reserved interrupt 898 */
  Reserved899_IRQn             = 883,              /**< Reserved interrupt 899 */
  Reserved900_IRQn             = 884,              /**< Reserved interrupt 900 */
  Reserved901_IRQn             = 885,              /**< Reserved interrupt 901 */
  Reserved902_IRQn             = 886,              /**< Reserved interrupt 902 */
  Reserved903_IRQn             = 887,              /**< Reserved interrupt 903 */
  Reserved904_IRQn             = 888,              /**< Reserved interrupt 904 */
  Reserved905_IRQn             = 889,              /**< Reserved interrupt 905 */
  Reserved906_IRQn             = 890,              /**< Reserved interrupt 906 */
  Reserved907_IRQn             = 891,              /**< Reserved interrupt 907 */
  Reserved908_IRQn             = 892,              /**< Reserved interrupt 908 */
  Reserved909_IRQn             = 893,              /**< Reserved interrupt 909 */
  Reserved910_IRQn             = 894,              /**< Reserved interrupt 910 */
  Reserved911_IRQn             = 895,              /**< Reserved interrupt 911 */
  Reserved912_IRQn             = 896,              /**< Reserved interrupt 912 */
  Reserved913_IRQn             = 897,              /**< Reserved interrupt 913 */
  Reserved914_IRQn             = 898,              /**< Reserved interrupt 914 */
  Reserved915_IRQn             = 899,              /**< Reserved interrupt 915 */
  Reserved916_IRQn             = 900,              /**< Reserved interrupt 916 */
  Reserved917_IRQn             = 901,              /**< Reserved interrupt 917 */
  Reserved918_IRQn             = 902,              /**< Reserved interrupt 918 */
  Reserved919_IRQn             = 903,              /**< Reserved interrupt 919 */
  Reserved920_IRQn             = 904,              /**< Reserved interrupt 920 */
  Reserved921_IRQn             = 905,              /**< Reserved interrupt 921 */
  Reserved922_IRQn             = 906,              /**< Reserved interrupt 922 */
  Reserved923_IRQn             = 907,              /**< Reserved interrupt 923 */
  Reserved924_IRQn             = 908,              /**< Reserved interrupt 924 */
  Reserved925_IRQn             = 909,              /**< Reserved interrupt 925 */
  Reserved926_IRQn             = 910,              /**< Reserved interrupt 926 */
  Reserved927_IRQn             = 911,              /**< Reserved interrupt 927 */
  Reserved928_IRQn             = 912,              /**< Reserved interrupt 928 */
  Reserved929_IRQn             = 913,              /**< Reserved interrupt 929 */
  Reserved930_IRQn             = 914,              /**< Reserved interrupt 930 */
  Reserved931_IRQn             = 915,              /**< Reserved interrupt 931 */
  Reserved932_IRQn             = 916,              /**< Reserved interrupt 932 */
  Reserved933_IRQn             = 917,              /**< Reserved interrupt 933 */
  Reserved934_IRQn             = 918,              /**< Reserved interrupt 934 */
  Reserved935_IRQn             = 919,              /**< Reserved interrupt 935 */
  Reserved936_IRQn             = 920,              /**< Reserved interrupt 936 */
  Reserved937_IRQn             = 921,              /**< Reserved interrupt 937 */
  Reserved938_IRQn             = 922,              /**< Reserved interrupt 938 */
  Reserved939_IRQn             = 923,              /**< Reserved interrupt 939 */
  Reserved940_IRQn             = 924,              /**< Reserved interrupt 940 */
  Reserved941_IRQn             = 925,              /**< Reserved interrupt 941 */
  Reserved942_IRQn             = 926,              /**< Reserved interrupt 942 */
  Reserved943_IRQn             = 927,              /**< Reserved interrupt 943 */
  Reserved944_IRQn             = 928,              /**< Reserved interrupt 944 */
  Reserved945_IRQn             = 929,              /**< Reserved interrupt 945 */
  Reserved946_IRQn             = 930,              /**< Reserved interrupt 946 */
  Reserved947_IRQn             = 931,              /**< Reserved interrupt 947 */
  Reserved948_IRQn             = 932,              /**< Reserved interrupt 948 */
  Reserved949_IRQn             = 933,              /**< Reserved interrupt 949 */
  Reserved950_IRQn             = 934,              /**< Reserved interrupt 950 */
  Reserved951_IRQn             = 935,              /**< Reserved interrupt 951 */
  Reserved952_IRQn             = 936,              /**< Reserved interrupt 952 */
  Reserved953_IRQn             = 937,              /**< Reserved interrupt 953 */
  Reserved954_IRQn             = 938,              /**< Reserved interrupt 954 */
  Reserved955_IRQn             = 939,              /**< Reserved interrupt 955 */
  Reserved956_IRQn             = 940,              /**< Reserved interrupt 956 */
  Reserved957_IRQn             = 941,              /**< Reserved interrupt 957 */
  Reserved958_IRQn             = 942,              /**< Reserved interrupt 958 */
  Reserved959_IRQn             = 943,              /**< Reserved interrupt 959 */
  Reserved960_IRQn             = 944,              /**< Reserved interrupt 960 */
  Reserved961_IRQn             = 945,              /**< Reserved interrupt 961 */
  Reserved962_IRQn             = 946,              /**< Reserved interrupt 962 */
  Reserved963_IRQn             = 947,              /**< Reserved interrupt 963 */
  Reserved964_IRQn             = 948,              /**< Reserved interrupt 964 */
  Reserved965_IRQn             = 949,              /**< Reserved interrupt 965 */
  Reserved966_IRQn             = 950,              /**< Reserved interrupt 966 */
  Reserved967_IRQn             = 951,              /**< Reserved interrupt 967 */
  Reserved968_IRQn             = 952,              /**< Reserved interrupt 968 */
  Reserved969_IRQn             = 953,              /**< Reserved interrupt 969 */
  Reserved970_IRQn             = 954,              /**< Reserved interrupt 970 */
  Reserved971_IRQn             = 955,              /**< Reserved interrupt 971 */
  Reserved972_IRQn             = 956,              /**< Reserved interrupt 972 */
  Reserved973_IRQn             = 957,              /**< Reserved interrupt 973 */
  Reserved974_IRQn             = 958,              /**< Reserved interrupt 974 */
  Reserved975_IRQn             = 959,              /**< Reserved interrupt 975 */
  Reserved976_IRQn             = 960,              /**< Reserved interrupt 976 */
  Reserved977_IRQn             = 961,              /**< Reserved interrupt 977 */
  Reserved978_IRQn             = 962,              /**< Reserved interrupt 978 */
  Reserved979_IRQn             = 963,              /**< Reserved interrupt 979 */
  Reserved980_IRQn             = 964,              /**< Reserved interrupt 980 */
  Reserved981_IRQn             = 965,              /**< Reserved interrupt 981 */
  Reserved982_IRQn             = 966,              /**< Reserved interrupt 982 */
  Reserved983_IRQn             = 967,              /**< Reserved interrupt 983 */
  Reserved984_IRQn             = 968,              /**< Reserved interrupt 984 */
  Reserved985_IRQn             = 969,              /**< Reserved interrupt 985 */
  Reserved986_IRQn             = 970,              /**< Reserved interrupt 986 */
  Reserved987_IRQn             = 971,              /**< Reserved interrupt 987 */
  Reserved988_IRQn             = 972,              /**< Reserved interrupt 988 */
  Reserved989_IRQn             = 973,              /**< Reserved interrupt 989 */
  Reserved990_IRQn             = 974,              /**< Reserved interrupt 990 */
  Reserved991_IRQn             = 975,              /**< Reserved interrupt 991 */
  Reserved992_IRQn             = 976,              /**< Reserved interrupt 992 */
  Reserved993_IRQn             = 977,              /**< Reserved interrupt 993 */
  Reserved994_IRQn             = 978,              /**< Reserved interrupt 994 */
  Reserved995_IRQn             = 979,              /**< Reserved interrupt 995 */
  Reserved996_IRQn             = 980,              /**< Reserved interrupt 996 */
  Reserved997_IRQn             = 981,              /**< Reserved interrupt 997 */
  Reserved998_IRQn             = 982,              /**< Reserved interrupt 998 */
  Reserved999_IRQn             = 983,              /**< Reserved interrupt 999 */
  Reserved1000_IRQn            = 984,              /**< Reserved interrupt 1000 */
  Reserved1001_IRQn            = 985,              /**< Reserved interrupt 1001 */
  Reserved1002_IRQn            = 986,              /**< Reserved interrupt 1002 */
  Reserved1003_IRQn            = 987,              /**< Reserved interrupt 1003 */
  Reserved1004_IRQn            = 988,              /**< Reserved interrupt 1004 */
  Reserved1005_IRQn            = 989,              /**< Reserved interrupt 1005 */
  Reserved1006_IRQn            = 990,              /**< Reserved interrupt 1006 */
  Reserved1007_IRQn            = 991,              /**< Reserved interrupt 1007 */
  Reserved1008_IRQn            = 992,              /**< Reserved interrupt 1008 */
  Reserved1009_IRQn            = 993,              /**< Reserved interrupt 1009 */
  Reserved1010_IRQn            = 994,              /**< Reserved interrupt 1010 */
  Reserved1011_IRQn            = 995,              /**< Reserved interrupt 1011 */
  Reserved1012_IRQn            = 996,              /**< Reserved interrupt 1012 */
  Reserved1013_IRQn            = 997,              /**< Reserved interrupt 1013 */
  Reserved1014_IRQn            = 998,              /**< Reserved interrupt 1014 */
  Reserved1015_IRQn            = 999,              /**< Reserved interrupt 1015 */
  Reserved1016_IRQn            = 1000,             /**< Reserved interrupt 1016 */
  Reserved1017_IRQn            = 1001,             /**< Reserved interrupt 1017 */
  Reserved1018_IRQn            = 1002,             /**< Reserved interrupt 1018 */
  Reserved1019_IRQn            = 1003,             /**< Reserved interrupt 1019 */
  Reserved1020_IRQn            = 1004,             /**< Reserved interrupt 1020 */
  Reserved1021_IRQn            = 1005,             /**< Reserved interrupt 1021 */
  Spurious1022_IRQn            = 1006,             /**< Special Interrupt */
  Spurious1023_IRQn            = 1007              /**< Special Interrupt */
} IRQn_Type;

/**
 * @}
 */ /* end of group Interrupt_vector_numbers */


/* ----------------------------------------------------------------------------
   -- Cortex A5 Core Configuration
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup Cortex_Core_Configuration Cortex A5 Core Configuration
 * @{
 */

#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS               5         /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */

//armcc complains when compiling m4 specific features for A5
#if defined(ARMCC_A5)

	/* IO definitions (access restrictions to peripheral registers) */
	/**
		\defgroup CMSIS_glob_defs CMSIS Global Defines

		<strong>IO Type Qualifiers</strong> are used
		\li to specify the access to peripheral variables.
		\li for automatic generation of peripheral register debug information.
	*/
	#ifdef __cplusplus
	  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
	#else
	  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
	#endif
	#define     __O     volatile             /*!< Defines 'write only' permissions                */
	#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

#else
	#include "core_cm4.h"                  /* Core Peripheral Access Layer */
#endif
#include "system_MVF50GS10MK50.h"      /* Device specific configuration file */

/**
 * @}
 */ /* end of group Cortex_Core_Configuration */


/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #pragma push
  #pragma anon_unions
#elif defined(__CWCC__)
  #pragma push
  #pragma cpp_extensions on
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __IO uint32_t HC[2];                             /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
  __I  uint32_t HS;                                /**< Status register for HW triggers, offset: 0x8 */
  __I  uint32_t R[2];                              /**< Data result register for HW triggers, array offset: 0xC, array step: 0x4 */
  __IO uint32_t CFG;                               /**< Configuration register, offset: 0x14 */
  __IO uint32_t GC;                                /**< General control register, offset: 0x18 */
  __IO uint32_t GS;                                /**< General status register, offset: 0x1C */
  __IO uint32_t CV;                                /**< Compare value register, offset: 0x20 */
  __IO uint32_t OFS;                               /**< Offset correction value register, offset: 0x24 */
  __IO uint32_t CAL;                               /**< Calibration value register, offset: 0x28 */
       uint8_t RESERVED_0[4];
  __IO uint32_t PCTL;                              /**< Pin control register, offset: 0x30 */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/* HC Bit Fields */
#define ADC_HC_ADCH_MASK                         0x1Fu
#define ADC_HC_ADCH_SHIFT                        0
#define ADC_HC_ADCH(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_HC_ADCH_SHIFT))&ADC_HC_ADCH_MASK)
#define ADC_HC_AIEN_MASK                         0x80u
#define ADC_HC_AIEN_SHIFT                        7
/* HS Bit Fields */
#define ADC_HS_COCO0_MASK                        0x1u
#define ADC_HS_COCO0_SHIFT                       0
#define ADC_HS_COCO1_MASK                        0x2u
#define ADC_HS_COCO1_SHIFT                       1
/* R Bit Fields */
#define ADC_R_D_MASK                             0xFFFu
#define ADC_R_D_SHIFT                            0
#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CFG Bit Fields */
#define ADC_CFG_ADICLK_MASK                      0x3u
#define ADC_CFG_ADICLK_SHIFT                     0
#define ADC_CFG_ADICLK(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADICLK_SHIFT))&ADC_CFG_ADICLK_MASK)
#define ADC_CFG_MODE_MASK                        0xCu
#define ADC_CFG_MODE_SHIFT                       2
#define ADC_CFG_MODE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_CFG_MODE_SHIFT))&ADC_CFG_MODE_MASK)
#define ADC_CFG_ADLSMP_MASK                      0x10u
#define ADC_CFG_ADLSMP_SHIFT                     4
#define ADC_CFG_ADIV_MASK                        0x60u
#define ADC_CFG_ADIV_SHIFT                       5
#define ADC_CFG_ADIV(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADIV_SHIFT))&ADC_CFG_ADIV_MASK)
#define ADC_CFG_ADLPC_MASK                       0x80u
#define ADC_CFG_ADLPC_SHIFT                      7
#define ADC_CFG_ADSTS_MASK                       0x300u
#define ADC_CFG_ADSTS_SHIFT                      8
#define ADC_CFG_ADSTS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADSTS_SHIFT))&ADC_CFG_ADSTS_MASK)
#define ADC_CFG_ADHSC_MASK                       0x400u
#define ADC_CFG_ADHSC_SHIFT                      10
#define ADC_CFG_REFSEL_MASK                      0x1800u
#define ADC_CFG_REFSEL_SHIFT                     11
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG_REFSEL_SHIFT))&ADC_CFG_REFSEL_MASK)
#define ADC_CFG_ADTRG_MASK                       0x2000u
#define ADC_CFG_ADTRG_SHIFT                      13
#define ADC_CFG_AVGS_MASK                        0xC000u
#define ADC_CFG_AVGS_SHIFT                       14
#define ADC_CFG_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_CFG_AVGS_SHIFT))&ADC_CFG_AVGS_MASK)
#define ADC_CFG_OVWREN_MASK                      0x10000u
#define ADC_CFG_OVWREN_SHIFT                     16
/* GC Bit Fields */
#define ADC_GC_ADACKEN_MASK                      0x1u
#define ADC_GC_ADACKEN_SHIFT                     0
#define ADC_GC_DMAEN_MASK                        0x2u
#define ADC_GC_DMAEN_SHIFT                       1
#define ADC_GC_ACREN_MASK                        0x4u
#define ADC_GC_ACREN_SHIFT                       2
#define ADC_GC_ACFGT_MASK                        0x8u
#define ADC_GC_ACFGT_SHIFT                       3
#define ADC_GC_ACFE_MASK                         0x10u
#define ADC_GC_ACFE_SHIFT                        4
#define ADC_GC_AVGE_MASK                         0x20u
#define ADC_GC_AVGE_SHIFT                        5
#define ADC_GC_ADCO_MASK                         0x40u
#define ADC_GC_ADCO_SHIFT                        6
#define ADC_GC_CAL_MASK                          0x80u
#define ADC_GC_CAL_SHIFT                         7
/* GS Bit Fields */
#define ADC_GS_ADACT_MASK                        0x1u
#define ADC_GS_ADACT_SHIFT                       0
#define ADC_GS_CALF_MASK                         0x2u
#define ADC_GS_CALF_SHIFT                        1
#define ADC_GS_AWKST_MASK                        0x4u
#define ADC_GS_AWKST_SHIFT                       2
/* CV Bit Fields */
#define ADC_CV_CV1_MASK                          0xFFFu
#define ADC_CV_CV1_SHIFT                         0
#define ADC_CV_CV1(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV1_SHIFT))&ADC_CV_CV1_MASK)
#define ADC_CV_CV2_MASK                          0xFFF0000u
#define ADC_CV_CV2_SHIFT                         16
#define ADC_CV_CV2(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV2_SHIFT))&ADC_CV_CV2_MASK)
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK                         0xFFFu
#define ADC_OFS_OFS_SHIFT                        0
#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
#define ADC_OFS_SIGN_MASK                        0x1000u
#define ADC_OFS_SIGN_SHIFT                       12
/* CAL Bit Fields */
#define ADC_CAL_CAL_CODE_MASK                    0xFu
#define ADC_CAL_CAL_CODE_SHIFT                   0
#define ADC_CAL_CAL_CODE(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CAL_CAL_CODE_SHIFT))&ADC_CAL_CAL_CODE_MASK)
/* PCTL Bit Fields */
#define ADC_PCTL_ADPC0_MASK                      0x1u
#define ADC_PCTL_ADPC0_SHIFT                     0
#define ADC_PCTL_ADPC1_MASK                      0x2u
#define ADC_PCTL_ADPC1_SHIFT                     1
#define ADC_PCTL_ADPC2_MASK                      0x4u
#define ADC_PCTL_ADPC2_SHIFT                     2
#define ADC_PCTL_ADPC3_MASK                      0x8u
#define ADC_PCTL_ADPC3_SHIFT                     3
#define ADC_PCTL_ADPC4_MASK                      0x10u
#define ADC_PCTL_ADPC4_SHIFT                     4
#define ADC_PCTL_ADPC5_MASK                      0x20u
#define ADC_PCTL_ADPC5_SHIFT                     5
#define ADC_PCTL_ADPC6_MASK                      0x40u
#define ADC_PCTL_ADPC6_SHIFT                     6
#define ADC_PCTL_ADPC7_MASK                      0x80u
#define ADC_PCTL_ADPC7_SHIFT                     7
#define ADC_PCTL_ADPC8_MASK                      0x100u
#define ADC_PCTL_ADPC8_SHIFT                     8
#define ADC_PCTL_ADPC9_MASK                      0x200u
#define ADC_PCTL_ADPC9_SHIFT                     9
#define ADC_PCTL_ADPC10_MASK                     0x400u
#define ADC_PCTL_ADPC10_SHIFT                    10
#define ADC_PCTL_ADPC11_MASK                     0x800u
#define ADC_PCTL_ADPC11_SHIFT                    11
#define ADC_PCTL_ADPC12_MASK                     0x1000u
#define ADC_PCTL_ADPC12_SHIFT                    12
#define ADC_PCTL_ADPC13_MASK                     0x2000u
#define ADC_PCTL_ADPC13_SHIFT                    13
#define ADC_PCTL_ADPC14_MASK                     0x4000u
#define ADC_PCTL_ADPC14_SHIFT                    14
#define ADC_PCTL_ADPC15_MASK                     0x8000u
#define ADC_PCTL_ADPC15_SHIFT                    15
#define ADC_PCTL_ADPC16_MASK                     0x10000u
#define ADC_PCTL_ADPC16_SHIFT                    16
#define ADC_PCTL_ADPC17_MASK                     0x20000u
#define ADC_PCTL_ADPC17_SHIFT                    17
#define ADC_PCTL_ADPC18_MASK                     0x40000u
#define ADC_PCTL_ADPC18_SHIFT                    18
#define ADC_PCTL_ADPC19_MASK                     0x80000u
#define ADC_PCTL_ADPC19_SHIFT                    19
#define ADC_PCTL_ADPC20_MASK                     0x100000u
#define ADC_PCTL_ADPC20_SHIFT                    20
#define ADC_PCTL_ADPC21_MASK                     0x200000u
#define ADC_PCTL_ADPC21_SHIFT                    21
#define ADC_PCTL_ADPC22_MASK                     0x400000u
#define ADC_PCTL_ADPC22_SHIFT                    22
#define ADC_PCTL_ADPC23_MASK                     0x800000u
#define ADC_PCTL_ADPC23_SHIFT                    23

/**
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE                                (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0                                     ((ADC_Type *)ADC0_BASE)
/** Peripheral ADC1 base address */
#define ADC1_BASE                                (0x400BB000u)
/** Peripheral ADC1 base pointer */
#define ADC1                                     ((ADC_Type *)ADC1_BASE)
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASES                                { ADC0, ADC1 }

/**
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AFE Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup AFE_Peripheral_Access_Layer AFE Peripheral Access Layer
 * @{
 */

/** AFE - Register Layout Typedef */
typedef struct {
  __I  uint32_t MISC_ID;                           /**< Misc. ID, offset: 0x0 */
  __IO uint32_t PDBUF;                             /**< Power Down Buffers, offset: 0x4 */
  __IO uint32_t SWRST;                             /**< Software Reset, offset: 0x8 */
       uint8_t RESERVED_0[12];
  __IO uint32_t BGREG;                             /**< Band Gap, offset: 0x18 */
       uint8_t RESERVED_1[996];
  __I  uint32_t ACCESSAR_ID;                       /**< Accessar ID, offset: 0x400 */
  __IO uint32_t PDADC;                             /**< Power Down ADC, offset: 0x404 */
  __IO uint32_t PDSARH;                            /**< Power Down SAR High, offset: 0x408 */
  __IO uint32_t PDSARL;                            /**< Power Down SAR Low, offset: 0x40C */
  __IO uint32_t PDADCRFH;                          /**< Power Down ADC Ref. High, offset: 0x410 */
  __IO uint32_t PDADCRFL;                          /**< Power Down ADC Ref. Low, offset: 0x414 */
       uint8_t RESERVED_2[4];
  __IO uint32_t ADCGN;                             /**< ADC Gain, offset: 0x41C */
       uint8_t RESERVED_3[20];
  __IO uint32_t REFTRIML;                          /**< ADC Ref Trim Low, offset: 0x434 */
  __IO uint32_t REFTRIMH;                          /**< ADC Ref Trim High, offset: 0x438 */
       uint8_t RESERVED_4[12];
  __I  uint32_t DLYALG;                            /**< Delay Loop Calculated Data, offset: 0x448 */
  __IO uint32_t DACAMP;                            /**< Clamp DAC Trim, offset: 0x44C */
       uint8_t RESERVED_5[4];
  __IO uint32_t CLMPDAT;                           /**< Clamp DAC Data, offset: 0x454 */
  __IO uint32_t CLMPAMP;                           /**< Clamp DAC Control, offset: 0x458 */
  __IO uint32_t CLAMP;                             /**< Clamp Control, offset: 0x45C */
  __IO uint32_t INPBUF;                            /**< Input Buffer, offset: 0x460 */
  __IO uint32_t INPFLT;                            /**< Analog Input Filter, offset: 0x464 */
  __IO uint32_t ADCDGN;                            /**< ADC Digital Gain, offset: 0x468 */
  __IO uint32_t OFFDRV;                            /**< Off-Chip Drive, offset: 0x46C */
       uint8_t RESERVED_6[912];
  __I  uint32_t ACC_ID;                            /**< Acc ID, offset: 0x800 */
       uint8_t RESERVED_7[4];
  __IO uint32_t ASAREG;                            /**< ADC Sample Acquisition, offset: 0x808 */
       uint8_t RESERVED_8[4];
  __IO uint32_t ASCREG;                            /**< ADC Sample Compensation, offset: 0x810 */
  __IO uint32_t BLCREG;                            /**< Block Level Control Register, offset: 0x814 */
       uint8_t RESERVED_9[12];
  __IO uint32_t AOCREG0;                           /**< ADC Operation Controller 0, offset: 0x824 */
} AFE_Type;

/* ----------------------------------------------------------------------------
   -- AFE Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup AFE_Register_Masks AFE Register Masks
 * @{
 */

/* MISC_ID Bit Fields */
#define AFE_MISC_ID_misc_id_MASK                 0xFFu
#define AFE_MISC_ID_misc_id_SHIFT                0
#define AFE_MISC_ID_misc_id(x)                   (((uint32_t)(((uint32_t)(x))<<AFE_MISC_ID_misc_id_SHIFT))&AFE_MISC_ID_misc_id_MASK)
/* PDBUF Bit Fields */
#define AFE_PDBUF_acafe_pd_n_MASK                0x1u
#define AFE_PDBUF_acafe_pd_n_SHIFT               0
#define AFE_PDBUF_bgr_bgr_pd_n_MASK              0x2u
#define AFE_PDBUF_bgr_bgr_pd_n_SHIFT             1
#define AFE_PDBUF_bgr_pd_n_MASK                  0x4u
#define AFE_PDBUF_bgr_pd_n_SHIFT                 2
/* SWRST Bit Fields */
#define AFE_SWRST_sysclk_sw_rst_n_MASK           0x1u
#define AFE_SWRST_sysclk_sw_rst_n_SHIFT          0
#define AFE_SWRST_adc_proc_clk_sw_rst_n_MASK     0x4u
#define AFE_SWRST_adc_proc_clk_sw_rst_n_SHIFT    2
#define AFE_SWRST_acafe_sw_rst_n_MASK            0x8u
#define AFE_SWRST_acafe_sw_rst_n_SHIFT           3
/* BGREG Bit Fields */
#define AFE_BGREG_bgr_trimlevel_MASK             0xFu
#define AFE_BGREG_bgr_trimlevel_SHIFT            0
#define AFE_BGREG_bgr_trimlevel(x)               (((uint32_t)(((uint32_t)(x))<<AFE_BGREG_bgr_trimlevel_SHIFT))&AFE_BGREG_bgr_trimlevel_MASK)
/* ACCESSAR_ID Bit Fields */
#define AFE_ACCESSAR_ID_accessar_id_MASK         0xFFu
#define AFE_ACCESSAR_ID_accessar_id_SHIFT        0
#define AFE_ACCESSAR_ID_accessar_id(x)           (((uint32_t)(((uint32_t)(x))<<AFE_ACCESSAR_ID_accessar_id_SHIFT))&AFE_ACCESSAR_ID_accessar_id_MASK)
/* PDADC Bit Fields */
#define AFE_PDADC_dlyloop_pd_n_MASK              0x2u
#define AFE_PDADC_dlyloop_pd_n_SHIFT             1
#define AFE_PDADC_adc_dlyloop_dac_pd_n_MASK      0x4u
#define AFE_PDADC_adc_dlyloop_dac_pd_n_SHIFT     2
#define AFE_PDADC_adc_iref_pd_n_MASK             0x8u
#define AFE_PDADC_adc_iref_pd_n_SHIFT            3
#define AFE_PDADC_clamp_pd_n_MASK                0x10u
#define AFE_PDADC_clamp_pd_n_SHIFT               4
/* PDSARH Bit Fields */
#define AFE_PDSARH_adc_pd_n_MASK                 0x1u
#define AFE_PDSARH_adc_pd_n_SHIFT                0
/* PDSARL Bit Fields */
#define AFE_PDSARL_adc_pd_n_MASK                 0xFFu
#define AFE_PDSARL_adc_pd_n_SHIFT                0
#define AFE_PDSARL_adc_pd_n(x)                   (((uint32_t)(((uint32_t)(x))<<AFE_PDSARL_adc_pd_n_SHIFT))&AFE_PDSARL_adc_pd_n_MASK)
/* PDADCRFH Bit Fields */
#define AFE_PDADCRFH_adcref_refbufslice_pd_n_MASK 0x1u
#define AFE_PDADCRFH_adcref_refbufslice_pd_n_SHIFT 0
/* PDADCRFL Bit Fields */
#define AFE_PDADCRFL_adcref_refbufslice_pd_n_MASK 0xFFu
#define AFE_PDADCRFL_adcref_refbufslice_pd_n_SHIFT 0
#define AFE_PDADCRFL_adcref_refbufslice_pd_n(x)  (((uint32_t)(((uint32_t)(x))<<AFE_PDADCRFL_adcref_refbufslice_pd_n_SHIFT))&AFE_PDADCRFL_adcref_refbufslice_pd_n_MASK)
/* ADCGN Bit Fields */
#define AFE_ADCGN_adc_gain_MASK                  0xFu
#define AFE_ADCGN_adc_gain_SHIFT                 0
#define AFE_ADCGN_adc_gain(x)                    (((uint32_t)(((uint32_t)(x))<<AFE_ADCGN_adc_gain_SHIFT))&AFE_ADCGN_adc_gain_MASK)
/* REFTRIML Bit Fields */
#define AFE_REFTRIML_adcref_reftrim08_MASK       0x3u
#define AFE_REFTRIML_adcref_reftrim08_SHIFT      0
#define AFE_REFTRIML_adcref_reftrim08(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_adcref_reftrim08_SHIFT))&AFE_REFTRIML_adcref_reftrim08_MASK)
#define AFE_REFTRIML_adcref_reftrim04_MASK       0xCu
#define AFE_REFTRIML_adcref_reftrim04_SHIFT      2
#define AFE_REFTRIML_adcref_reftrim04(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_adcref_reftrim04_SHIFT))&AFE_REFTRIML_adcref_reftrim04_MASK)
#define AFE_REFTRIML_adcref_reftrim02_MASK       0x30u
#define AFE_REFTRIML_adcref_reftrim02_SHIFT      4
#define AFE_REFTRIML_adcref_reftrim02(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_adcref_reftrim02_SHIFT))&AFE_REFTRIML_adcref_reftrim02_MASK)
#define AFE_REFTRIML_adcref_reftrimop_MASK       0xC0u
#define AFE_REFTRIML_adcref_reftrimop_SHIFT      6
#define AFE_REFTRIML_adcref_reftrimop(x)         (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_adcref_reftrimop_SHIFT))&AFE_REFTRIML_adcref_reftrimop_MASK)
/* REFTRIMH Bit Fields */
#define AFE_REFTRIMH_adcref_reftrim_MASK         0xFu
#define AFE_REFTRIMH_adcref_reftrim_SHIFT        0
#define AFE_REFTRIMH_adcref_reftrim(x)           (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIMH_adcref_reftrim_SHIFT))&AFE_REFTRIMH_adcref_reftrim_MASK)
/* DLYALG Bit Fields */
#define AFE_DLYALG_dlyloop_calculateddata_MASK   0x7Fu
#define AFE_DLYALG_dlyloop_calculateddata_SHIFT  0
#define AFE_DLYALG_dlyloop_calculateddata(x)     (((uint32_t)(((uint32_t)(x))<<AFE_DLYALG_dlyloop_calculateddata_SHIFT))&AFE_DLYALG_dlyloop_calculateddata_MASK)
/* DACAMP Bit Fields */
#define AFE_DACAMP_clampdac_trim_MASK            0xFu
#define AFE_DACAMP_clampdac_trim_SHIFT           0
#define AFE_DACAMP_clampdac_trim(x)              (((uint32_t)(((uint32_t)(x))<<AFE_DACAMP_clampdac_trim_SHIFT))&AFE_DACAMP_clampdac_trim_MASK)
/* CLMPDAT Bit Fields */
#define AFE_CLMPDAT_clampdac_data_MASK           0xFFu
#define AFE_CLMPDAT_clampdac_data_SHIFT          0
#define AFE_CLMPDAT_clampdac_data(x)             (((uint32_t)(((uint32_t)(x))<<AFE_CLMPDAT_clampdac_data_SHIFT))&AFE_CLMPDAT_clampdac_data_MASK)
/* CLMPAMP Bit Fields */
#define AFE_CLMPAMP_clamp_dacdata_extra_MASK     0x7u
#define AFE_CLMPAMP_clamp_dacdata_extra_SHIFT    0
#define AFE_CLMPAMP_clamp_dacdata_extra(x)       (((uint32_t)(((uint32_t)(x))<<AFE_CLMPAMP_clamp_dacdata_extra_SHIFT))&AFE_CLMPAMP_clamp_dacdata_extra_MASK)
#define AFE_CLMPAMP_clamp_dacdata_weight_MASK    0x18u
#define AFE_CLMPAMP_clamp_dacdata_weight_SHIFT   3
#define AFE_CLMPAMP_clamp_dacdata_weight(x)      (((uint32_t)(((uint32_t)(x))<<AFE_CLMPAMP_clamp_dacdata_weight_SHIFT))&AFE_CLMPAMP_clamp_dacdata_weight_MASK)
#define AFE_CLMPAMP_clamp_updn_reg_override_MASK 0x20u
#define AFE_CLMPAMP_clamp_updn_reg_override_SHIFT 5
#define AFE_CLMPAMP_clamp_current_reg_override_MASK 0x40u
#define AFE_CLMPAMP_clamp_current_reg_override_SHIFT 6
/* CLAMP Bit Fields */
#define AFE_CLAMP_nclamp_powersave_MASK          0x1u
#define AFE_CLAMP_nclamp_powersave_SHIFT         0
#define AFE_CLAMP_clamp_ipen_reg_MASK            0x4u
#define AFE_CLAMP_clamp_ipen_reg_SHIFT           2
#define AFE_CLAMP_clamp_inen_reg_MASK            0x8u
#define AFE_CLAMP_clamp_inen_reg_SHIFT           3
#define AFE_CLAMP_clamp_lowcurrmode_MASK         0x10u
#define AFE_CLAMP_clamp_lowcurrmode_SHIFT        4
#define AFE_CLAMP_clamp_irefselect_MASK          0x20u
#define AFE_CLAMP_clamp_irefselect_SHIFT         5
#define AFE_CLAMP_clamp_up_down_polarity_MASK    0x40u
#define AFE_CLAMP_clamp_up_down_polarity_SHIFT   6
#define AFE_CLAMP_clamp_pwm_mode_MASK            0x80u
#define AFE_CLAMP_clamp_pwm_mode_SHIFT           7
/* INPBUF Bit Fields */
#define AFE_INPBUF_buff_en_ri_MASK               0x1u
#define AFE_INPBUF_buff_en_ri_SHIFT              0
#define AFE_INPBUF_buff_en_cm_MASK               0x4u
#define AFE_INPBUF_buff_en_cm_SHIFT              2
#define AFE_INPBUF_mux_buffer_bp_en_MASK         0x8u
#define AFE_INPBUF_mux_buffer_bp_en_SHIFT        3
#define AFE_INPBUF_mux_buffer_15m_en_MASK        0x10u
#define AFE_INPBUF_mux_buffer_15m_en_SHIFT       4
#define AFE_INPBUF_mux_clampen_MASK              0x20u
#define AFE_INPBUF_mux_clampen_SHIFT             5
/* INPFLT Bit Fields */
#define AFE_INPFLT_mux_pdcurrentmirror_MASK      0x1u
#define AFE_INPFLT_mux_pdcurrentmirror_SHIFT     0
#define AFE_INPFLT_mux_filter_15m_en_MASK        0x2u
#define AFE_INPFLT_mux_filter_15m_en_SHIFT       1
#define AFE_INPFLT_mux_filterbypass_MASK         0x4u
#define AFE_INPFLT_mux_filterbypass_SHIFT        2
#define AFE_INPFLT_mux_enlf_MASK                 0x78u
#define AFE_INPFLT_mux_enlf_SHIFT                3
#define AFE_INPFLT_mux_enlf(x)                   (((uint32_t)(((uint32_t)(x))<<AFE_INPFLT_mux_enlf_SHIFT))&AFE_INPFLT_mux_enlf_MASK)
/* ADCDGN Bit Fields */
#define AFE_ADCDGN_adc_digital_gain_MASK         0x3Fu
#define AFE_ADCDGN_adc_digital_gain_SHIFT        0
#define AFE_ADCDGN_adc_digital_gain(x)           (((uint32_t)(((uint32_t)(x))<<AFE_ADCDGN_adc_digital_gain_SHIFT))&AFE_ADCDGN_adc_digital_gain_MASK)
#define AFE_ADCDGN_adc_digital_gain_bypass_MASK  0x40u
#define AFE_ADCDGN_adc_digital_gain_bypass_SHIFT 6
/* OFFDRV Bit Fields */
#define AFE_OFFDRV_input_pulldown_en_MASK        0xF0u
#define AFE_OFFDRV_input_pulldown_en_SHIFT       4
#define AFE_OFFDRV_input_pulldown_en(x)          (((uint32_t)(((uint32_t)(x))<<AFE_OFFDRV_input_pulldown_en_SHIFT))&AFE_OFFDRV_input_pulldown_en_MASK)
/* ACC_ID Bit Fields */
#define AFE_ACC_ID_acc_id_MASK                   0xFFu
#define AFE_ACC_ID_acc_id_SHIFT                  0
#define AFE_ACC_ID_acc_id(x)                     (((uint32_t)(((uint32_t)(x))<<AFE_ACC_ID_acc_id_SHIFT))&AFE_ACC_ID_acc_id_MASK)
/* ASAREG Bit Fields */
#define AFE_ASAREG_asa_reg3_MASK                 0x2u
#define AFE_ASAREG_asa_reg3_SHIFT                1
#define AFE_ASAREG_asa_reg5_MASK                 0x4u
#define AFE_ASAREG_asa_reg5_SHIFT                2
#define AFE_ASAREG_asa_reg9_MASK                 0x8u
#define AFE_ASAREG_asa_reg9_SHIFT                3
#define AFE_ASAREG_asa_reg_MASK                  0xE0u
#define AFE_ASAREG_asa_reg_SHIFT                 5
#define AFE_ASAREG_asa_reg(x)                    (((uint32_t)(((uint32_t)(x))<<AFE_ASAREG_asa_reg_SHIFT))&AFE_ASAREG_asa_reg_MASK)
/* ASCREG Bit Fields */
#define AFE_ASCREG_asc_reg_MASK                  0x1u
#define AFE_ASCREG_asc_reg_SHIFT                 0
/* BLCREG Bit Fields */
#define AFE_BLCREG_en_bypass_MASK                0x1u
#define AFE_BLCREG_en_bypass_SHIFT               0
#define AFE_BLCREG_start_cal_MASK                0x2u
#define AFE_BLCREG_start_cal_SHIFT               1
/* AOCREG0 Bit Fields */
#define AFE_AOCREG0_start_cal_MASK               0x1u
#define AFE_AOCREG0_start_cal_SHIFT              0

/**
 * @}
 */ /* end of group AFE_Register_Masks */


/* AFE - Peripheral instance base addresses */
/** Peripheral AFE base address */
#define AFE_BASE                                 (0x400C7000u)
/** Peripheral AFE base pointer */
#define AFE                                      ((AFE_Type *)AFE_BASE)
/** Array initializer of AFE peripheral base pointers */
#define AFE_BASES                                { AFE }

/**
 * @}
 */ /* end of group AFE_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ANADIG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ANADIG_Peripheral_Access_Layer ANADIG Peripheral Access Layer
 * @{
 */

/** ANADIG - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PLL3_CTRL;                         /**< PLL3 Control register, offset: 0x10 */
       uint8_t RESERVED_1[12];
  __IO uint32_t PLL7_CTRL;                         /**< PLL7 Control register, offset: 0x20 */
       uint8_t RESERVED_2[12];
  __IO uint32_t PLL2_CTRL;                         /**< PLL2 Control register, offset: 0x30 */
       uint8_t RESERVED_3[12];
  __IO uint32_t PLL2_SS;                           /**< PLL2 Spread Spectrum definition register, offset: 0x40 */
       uint8_t RESERVED_4[12];
  __IO uint32_t PLL2_NUM;                          /**< PLL2 Numerator definition register, offset: 0x50 */
       uint8_t RESERVED_5[12];
  __IO uint32_t PLL2_DENOM;                        /**< PLL2 Denominator definition register, offset: 0x60 */
       uint8_t RESERVED_6[12];
  __IO uint32_t PLL4_CTRL;                         /**< PLL4 Control register, offset: 0x70 */
       uint8_t RESERVED_7[12];
  __IO uint32_t PLL4_NUM;                          /**< PLL4 Numerator register, offset: 0x80 */
       uint8_t RESERVED_8[12];
  __IO uint32_t PLL4_DENOM;                        /**< PLL4 Denominator register, offset: 0x90 */
       uint8_t RESERVED_9[12];
  __IO uint32_t PLL6_CTRL;                         /**< PLL6 Control register, offset: 0xA0 */
       uint8_t RESERVED_10[12];
  __IO uint32_t PLL6_NUM;                          /**< PLL6 Numerator register, offset: 0xB0 */
       uint8_t RESERVED_11[12];
  __IO uint32_t PLL6_DENOM;                        /**< PLL6 Denominator register, offset: 0xC0 */
       uint8_t RESERVED_12[28];
  __IO uint32_t PLL5_CTRL;                         /**< PLL5 Control register, offset: 0xE0 */
       uint8_t RESERVED_13[12];
  __IO uint32_t PLL3_PFD;                          /**< ANADIG PLL3 PFD definition register, offset: 0xF0 */
       uint8_t RESERVED_14[12];
  __IO uint32_t PLL2_PFD;                          /**< ANADIG PLL2 PFD definition register, offset: 0x100 */
       uint8_t RESERVED_15[12];
  __IO uint32_t REG_1P1;                           /**< ANADIG Regulator 1P1 definition register, offset: 0x110 */
       uint8_t RESERVED_16[12];
  __IO uint32_t REG_3P0;                           /**< ANADIG Regulator 3P0 definition register, offset: 0x120 */
       uint8_t RESERVED_17[12];
  __IO uint32_t REG_2P5;                           /**< ANADIG Regulator 2P5 definition register, offset: 0x130 */
       uint8_t RESERVED_18[28];
  __IO uint32_t ANA_MISC0;                         /**< ANADIG Analog Miscellaneous definition register, offset: 0x150 */
       uint8_t RESERVED_19[12];
  __IO uint32_t ANA_MISC1;                         /**< ANADIG Analog Miscellaneous definition register, offset: 0x160 */
       uint8_t RESERVED_20[252];
  __I  uint32_t DIGPROG;                           /**< ANADIG Digital Program register, offset: 0x260 */
       uint8_t RESERVED_21[12];
  __IO uint32_t PLL1_CTRL;                         /**< PLL1 Control register, offset: 0x270 */
       uint8_t RESERVED_22[12];
  __IO uint32_t PLL1_SS;                           /**< PLL1 Spread Spectrum register, offset: 0x280 */
       uint8_t RESERVED_23[12];
  __IO uint32_t PLL1_NUM;                          /**< PLL1 Numerator register, offset: 0x290 */
       uint8_t RESERVED_24[12];
  __IO uint32_t PLL1_DENOM;                        /**< PLL1 Denominator register, offset: 0x2A0 */
       uint8_t RESERVED_25[12];
  __IO uint32_t PLL1_PFD;                          /**< ANADIG PLL1_PFD definition register, offset: 0x2B0 */
       uint8_t RESERVED_26[12];
  __I  uint32_t PLL_LOCK;                          /**< ANADIG PLL Lock register, offset: 0x2C0 */
} ANADIG_Type;

/* ----------------------------------------------------------------------------
   -- ANADIG Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ANADIG_Register_Masks ANADIG Register Masks
 * @{
 */

/* PLL3_CTRL Bit Fields */
#define ANADIG_PLL3_CTRL_DIV_SELECT_MASK         0x1u
#define ANADIG_PLL3_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL3_CTRL_EN_USB_CLKS_MASK        0x40u
#define ANADIG_PLL3_CTRL_EN_USB_CLKS_SHIFT       6
#define ANADIG_PLL3_CTRL_POWER_MASK              0x1000u
#define ANADIG_PLL3_CTRL_POWER_SHIFT             12
#define ANADIG_PLL3_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL3_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL3_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL3_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL3_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL3_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL3_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL3_CTRL_LOCK_SHIFT              31
/* PLL7_CTRL Bit Fields */
#define ANADIG_PLL7_CTRL_DIV_SELECT_MASK         0x1u
#define ANADIG_PLL7_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL7_CTRL_EN_USB_CLKS_MASK        0x40u
#define ANADIG_PLL7_CTRL_EN_USB_CLKS_SHIFT       6
#define ANADIG_PLL7_CTRL_POWER_MASK              0x1000u
#define ANADIG_PLL7_CTRL_POWER_SHIFT             12
#define ANADIG_PLL7_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL7_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL7_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL7_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL7_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL7_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL7_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL7_CTRL_LOCK_SHIFT              31
/* PLL2_CTRL Bit Fields */
#define ANADIG_PLL2_CTRL_DIV_SELECT_MASK         0x1u
#define ANADIG_PLL2_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL2_CTRL_POWERDOWN_MASK          0x1000u
#define ANADIG_PLL2_CTRL_POWERDOWN_SHIFT         12
#define ANADIG_PLL2_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL2_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL2_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL2_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL2_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL2_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL2_CTRL_DITHER_ENABLE_MASK      0x20000u
#define ANADIG_PLL2_CTRL_DITHER_ENABLE_SHIFT     17
#define ANADIG_PLL2_CTRL_PFD_OFFSET_EN_MASK      0x40000u
#define ANADIG_PLL2_CTRL_PFD_OFFSET_EN_SHIFT     18
#define ANADIG_PLL2_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL2_CTRL_LOCK_SHIFT              31
/* PLL2_SS Bit Fields */
#define ANADIG_PLL2_SS_STEP_MASK                 0x7FFFu
#define ANADIG_PLL2_SS_STEP_SHIFT                0
#define ANADIG_PLL2_SS_STEP(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_SS_STEP_SHIFT))&ANADIG_PLL2_SS_STEP_MASK)
#define ANADIG_PLL2_SS_ENABLE_MASK               0x8000u
#define ANADIG_PLL2_SS_ENABLE_SHIFT              15
#define ANADIG_PLL2_SS_STOP_MASK                 0xFFFF0000u
#define ANADIG_PLL2_SS_STOP_SHIFT                16
#define ANADIG_PLL2_SS_STOP(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_SS_STOP_SHIFT))&ANADIG_PLL2_SS_STOP_MASK)
/* PLL2_NUM Bit Fields */
#define ANADIG_PLL2_NUM_A_MASK                   0x3FFFFFFFu
#define ANADIG_PLL2_NUM_A_SHIFT                  0
#define ANADIG_PLL2_NUM_A(x)                     (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_NUM_A_SHIFT))&ANADIG_PLL2_NUM_A_MASK)
/* PLL2_DENOM Bit Fields */
#define ANADIG_PLL2_DENOM_B_MASK                 0x3FFFFFFFu
#define ANADIG_PLL2_DENOM_B_SHIFT                0
#define ANADIG_PLL2_DENOM_B(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_DENOM_B_SHIFT))&ANADIG_PLL2_DENOM_B_MASK)
/* PLL4_CTRL Bit Fields */
#define ANADIG_PLL4_CTRL_DIV_SELECT_MASK         0x7Fu
#define ANADIG_PLL4_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL4_CTRL_DIV_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL4_CTRL_DIV_SELECT_SHIFT))&ANADIG_PLL4_CTRL_DIV_SELECT_MASK)
#define ANADIG_PLL4_CTRL_POWERDOWN_MASK          0x1000u
#define ANADIG_PLL4_CTRL_POWERDOWN_SHIFT         12
#define ANADIG_PLL4_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL4_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL4_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL4_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL4_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL4_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL4_CTRL_DITHER_ENABLE_MASK      0x20000u
#define ANADIG_PLL4_CTRL_DITHER_ENABLE_SHIFT     17
#define ANADIG_PLL4_CTRL_PFD_OFFSET_EN_MASK      0x40000u
#define ANADIG_PLL4_CTRL_PFD_OFFSET_EN_SHIFT     18
#define ANADIG_PLL4_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL4_CTRL_LOCK_SHIFT              31
/* PLL4_NUM Bit Fields */
#define ANADIG_PLL4_NUM_A_MASK                   0x3FFFFFFFu
#define ANADIG_PLL4_NUM_A_SHIFT                  0
#define ANADIG_PLL4_NUM_A(x)                     (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL4_NUM_A_SHIFT))&ANADIG_PLL4_NUM_A_MASK)
/* PLL4_DENOM Bit Fields */
#define ANADIG_PLL4_DENOM_B_MASK                 0x3FFFFFFFu
#define ANADIG_PLL4_DENOM_B_SHIFT                0
#define ANADIG_PLL4_DENOM_B(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL4_DENOM_B_SHIFT))&ANADIG_PLL4_DENOM_B_MASK)
/* PLL6_CTRL Bit Fields */
#define ANADIG_PLL6_CTRL_DIV_SELECT_MASK         0x7Fu
#define ANADIG_PLL6_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL6_CTRL_DIV_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL6_CTRL_DIV_SELECT_SHIFT))&ANADIG_PLL6_CTRL_DIV_SELECT_MASK)
#define ANADIG_PLL6_CTRL_POWERDOWN_MASK          0x1000u
#define ANADIG_PLL6_CTRL_POWERDOWN_SHIFT         12
#define ANADIG_PLL6_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL6_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL6_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL6_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL6_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL6_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL6_CTRL_DITHER_ENABLE_MASK      0x20000u
#define ANADIG_PLL6_CTRL_DITHER_ENABLE_SHIFT     17
#define ANADIG_PLL6_CTRL_PFD_OFFSET_EN_MASK      0x40000u
#define ANADIG_PLL6_CTRL_PFD_OFFSET_EN_SHIFT     18
#define ANADIG_PLL6_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL6_CTRL_LOCK_SHIFT              31
/* PLL6_NUM Bit Fields */
#define ANADIG_PLL6_NUM_A_MASK                   0x3FFFFFFFu
#define ANADIG_PLL6_NUM_A_SHIFT                  0
#define ANADIG_PLL6_NUM_A(x)                     (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL6_NUM_A_SHIFT))&ANADIG_PLL6_NUM_A_MASK)
/* PLL6_DENOM Bit Fields */
#define ANADIG_PLL6_DENOM_B_MASK                 0x3FFFFFFFu
#define ANADIG_PLL6_DENOM_B_SHIFT                0
#define ANADIG_PLL6_DENOM_B(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL6_DENOM_B_SHIFT))&ANADIG_PLL6_DENOM_B_MASK)
/* PLL5_CTRL Bit Fields */
#define ANADIG_PLL5_CTRL_DIV_SELECT_MASK         0x3u
#define ANADIG_PLL5_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL5_CTRL_DIV_SELECT(x)           (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL5_CTRL_DIV_SELECT_SHIFT))&ANADIG_PLL5_CTRL_DIV_SELECT_MASK)
#define ANADIG_PLL5_CTRL_POWERDOWN_MASK          0x1000u
#define ANADIG_PLL5_CTRL_POWERDOWN_SHIFT         12
#define ANADIG_PLL5_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL5_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL5_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL5_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL5_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL5_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL5_CTRL_DITHER_ENABLE_MASK      0x20000u
#define ANADIG_PLL5_CTRL_DITHER_ENABLE_SHIFT     17
#define ANADIG_PLL5_CTRL_PFD_OFFSET_EN_MASK      0x40000u
#define ANADIG_PLL5_CTRL_PFD_OFFSET_EN_SHIFT     18
#define ANADIG_PLL5_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL5_CTRL_LOCK_SHIFT              31
/* PLL3_PFD Bit Fields */
#define ANADIG_PLL3_PFD_PFD1_FRAC_MASK           0x3Fu
#define ANADIG_PLL3_PFD_PFD1_FRAC_SHIFT          0
#define ANADIG_PLL3_PFD_PFD1_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL3_PFD_PFD1_FRAC_SHIFT))&ANADIG_PLL3_PFD_PFD1_FRAC_MASK)
#define ANADIG_PLL3_PFD_PFD1_STABLE_MASK         0x40u
#define ANADIG_PLL3_PFD_PFD1_STABLE_SHIFT        6
#define ANADIG_PLL3_PFD_PFD1_CLKGATE_MASK        0x80u
#define ANADIG_PLL3_PFD_PFD1_CLKGATE_SHIFT       7
#define ANADIG_PLL3_PFD_PFD2_FRAC_MASK           0x3F00u
#define ANADIG_PLL3_PFD_PFD2_FRAC_SHIFT          8
#define ANADIG_PLL3_PFD_PFD2_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL3_PFD_PFD2_FRAC_SHIFT))&ANADIG_PLL3_PFD_PFD2_FRAC_MASK)
#define ANADIG_PLL3_PFD_PFD2_STABLE_MASK         0x4000u
#define ANADIG_PLL3_PFD_PFD2_STABLE_SHIFT        14
#define ANADIG_PLL3_PFD_PFD2_CLKGATE_MASK        0x8000u
#define ANADIG_PLL3_PFD_PFD2_CLKGATE_SHIFT       15
#define ANADIG_PLL3_PFD_PFD3_FRAC_MASK           0x3F0000u
#define ANADIG_PLL3_PFD_PFD3_FRAC_SHIFT          16
#define ANADIG_PLL3_PFD_PFD3_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL3_PFD_PFD3_FRAC_SHIFT))&ANADIG_PLL3_PFD_PFD3_FRAC_MASK)
#define ANADIG_PLL3_PFD_PFD3_STABLE_MASK         0x400000u
#define ANADIG_PLL3_PFD_PFD3_STABLE_SHIFT        22
#define ANADIG_PLL3_PFD_PFD3_CLKGATE_MASK        0x800000u
#define ANADIG_PLL3_PFD_PFD3_CLKGATE_SHIFT       23
#define ANADIG_PLL3_PFD_PFD4_FRAC_MASK           0x3F000000u
#define ANADIG_PLL3_PFD_PFD4_FRAC_SHIFT          24
#define ANADIG_PLL3_PFD_PFD4_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL3_PFD_PFD4_FRAC_SHIFT))&ANADIG_PLL3_PFD_PFD4_FRAC_MASK)
#define ANADIG_PLL3_PFD_PFD4_STABLE_MASK         0x40000000u
#define ANADIG_PLL3_PFD_PFD4_STABLE_SHIFT        30
#define ANADIG_PLL3_PFD_PFD4_CLKGATE_MASK        0x80000000u
#define ANADIG_PLL3_PFD_PFD4_CLKGATE_SHIFT       31
/* PLL2_PFD Bit Fields */
#define ANADIG_PLL2_PFD_PFD1_FRAC_MASK           0x3Fu
#define ANADIG_PLL2_PFD_PFD1_FRAC_SHIFT          0
#define ANADIG_PLL2_PFD_PFD1_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_PFD_PFD1_FRAC_SHIFT))&ANADIG_PLL2_PFD_PFD1_FRAC_MASK)
#define ANADIG_PLL2_PFD_PFD1_STABLE_MASK         0x40u
#define ANADIG_PLL2_PFD_PFD1_STABLE_SHIFT        6
#define ANADIG_PLL2_PFD_PFD1_CLKGATE_MASK        0x80u
#define ANADIG_PLL2_PFD_PFD1_CLKGATE_SHIFT       7
#define ANADIG_PLL2_PFD_PFD2_FRAC_MASK           0x3F00u
#define ANADIG_PLL2_PFD_PFD2_FRAC_SHIFT          8
#define ANADIG_PLL2_PFD_PFD2_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_PFD_PFD2_FRAC_SHIFT))&ANADIG_PLL2_PFD_PFD2_FRAC_MASK)
#define ANADIG_PLL2_PFD_PFD2_STABLE_MASK         0x4000u
#define ANADIG_PLL2_PFD_PFD2_STABLE_SHIFT        14
#define ANADIG_PLL2_PFD_PFD2_CLKGATE_MASK        0x8000u
#define ANADIG_PLL2_PFD_PFD2_CLKGATE_SHIFT       15
#define ANADIG_PLL2_PFD_PFD3_FRAC_MASK           0x3F0000u
#define ANADIG_PLL2_PFD_PFD3_FRAC_SHIFT          16
#define ANADIG_PLL2_PFD_PFD3_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_PFD_PFD3_FRAC_SHIFT))&ANADIG_PLL2_PFD_PFD3_FRAC_MASK)
#define ANADIG_PLL2_PFD_PFD3_STABLE_MASK         0x400000u
#define ANADIG_PLL2_PFD_PFD3_STABLE_SHIFT        22
#define ANADIG_PLL2_PFD_PFD3_CLKGATE_MASK        0x800000u
#define ANADIG_PLL2_PFD_PFD3_CLKGATE_SHIFT       23
#define ANADIG_PLL2_PFD_PFD4_FRAC_MASK           0x3F000000u
#define ANADIG_PLL2_PFD_PFD4_FRAC_SHIFT          24
#define ANADIG_PLL2_PFD_PFD4_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL2_PFD_PFD4_FRAC_SHIFT))&ANADIG_PLL2_PFD_PFD4_FRAC_MASK)
#define ANADIG_PLL2_PFD_PFD4_STABLE_MASK         0x40000000u
#define ANADIG_PLL2_PFD_PFD4_STABLE_SHIFT        30
#define ANADIG_PLL2_PFD_PFD4_CLKGATE_MASK        0x80000000u
#define ANADIG_PLL2_PFD_PFD4_CLKGATE_SHIFT       31
/* REG_1P1 Bit Fields */
#define ANADIG_REG_1P1_ENABLE_LINREG_MASK        0x1u
#define ANADIG_REG_1P1_ENABLE_LINREG_SHIFT       0
#define ANADIG_REG_1P1_ENABLE_BO_MASK            0x2u
#define ANADIG_REG_1P1_ENABLE_BO_SHIFT           1
#define ANADIG_REG_1P1_ENABLE_ILIMIT_MASK        0x4u
#define ANADIG_REG_1P1_ENABLE_ILIMIT_SHIFT       2
#define ANADIG_REG_1P1_ENABLE_PULLDOWN_MASK      0x8u
#define ANADIG_REG_1P1_ENABLE_PULLDOWN_SHIFT     3
#define ANADIG_REG_1P1_BO_VDD1P1_MASK            0x10000u
#define ANADIG_REG_1P1_BO_VDD1P1_SHIFT           16
#define ANADIG_REG_1P1_OK_VDD1P1_MASK            0x20000u
#define ANADIG_REG_1P1_OK_VDD1P1_SHIFT           17
/* REG_3P0 Bit Fields */
#define ANADIG_REG_3P0_ENABLE_LINREG_MASK        0x1u
#define ANADIG_REG_3P0_ENABLE_LINREG_SHIFT       0
#define ANADIG_REG_3P0_ENABLE_BO_MASK            0x2u
#define ANADIG_REG_3P0_ENABLE_BO_SHIFT           1
#define ANADIG_REG_3P0_ENABLE_ILIMIT_MASK        0x4u
#define ANADIG_REG_3P0_ENABLE_ILIMIT_SHIFT       2
#define ANADIG_REG_3P0_REG_3P0_VBUS_SEL_MASK     0x80u
#define ANADIG_REG_3P0_REG_3P0_VBUS_SEL_SHIFT    7
#define ANADIG_REG_3P0_BO_VDD3P0_MASK            0x10000u
#define ANADIG_REG_3P0_BO_VDD3P0_SHIFT           16
#define ANADIG_REG_3P0_OK_VDD3P0_MASK            0x20000u
#define ANADIG_REG_3P0_OK_VDD3P0_SHIFT           17
/* REG_2P5 Bit Fields */
#define ANADIG_REG_2P5_ENABLE_LINREG_MASK        0x1u
#define ANADIG_REG_2P5_ENABLE_LINREG_SHIFT       0
#define ANADIG_REG_2P5_ENABLE_BO_MASK            0x2u
#define ANADIG_REG_2P5_ENABLE_BO_SHIFT           1
#define ANADIG_REG_2P5_ENABLE_ILIMIT_MASK        0x4u
#define ANADIG_REG_2P5_ENABLE_ILIMIT_SHIFT       2
#define ANADIG_REG_2P5_ENABLE_PULLDOWN_MASK      0x8u
#define ANADIG_REG_2P5_ENABLE_PULLDOWN_SHIFT     3
#define ANADIG_REG_2P5_BO_VDD2P5_MASK            0x10000u
#define ANADIG_REG_2P5_BO_VDD2P5_SHIFT           16
#define ANADIG_REG_2P5_OK_VDD2P5_MASK            0x20000u
#define ANADIG_REG_2P5_OK_VDD2P5_SHIFT           17
#define ANADIG_REG_2P5_ENABLE_WEAK_LINREG_MASK   0x40000u
#define ANADIG_REG_2P5_ENABLE_WEAK_LINREG_SHIFT  18
/* ANA_MISC0 Bit Fields */
#define ANADIG_ANA_MISC0_REFTOP_PWD_MASK         0x1u
#define ANADIG_ANA_MISC0_REFTOP_PWD_SHIFT        0
#define ANADIG_ANA_MISC0_REFTOP_PWDVBGUP_MASK    0x2u
#define ANADIG_ANA_MISC0_REFTOP_PWDVBGUP_SHIFT   1
#define ANADIG_ANA_MISC0_REFTOP_LOWPOWER_MASK    0x4u
#define ANADIG_ANA_MISC0_REFTOP_LOWPOWER_SHIFT   2
#define ANADIG_ANA_MISC0_REFTOP_SELBIASOFF_MASK  0x8u
#define ANADIG_ANA_MISC0_REFTOP_SELBIASOFF_SHIFT 3
#define ANADIG_ANA_MISC0_REFTOP_VBGUP_MASK       0x80u
#define ANADIG_ANA_MISC0_REFTOP_VBGUP_SHIFT      7
#define ANADIG_ANA_MISC0_STOP_MODE_CONFIG_MASK   0x1000u
#define ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SHIFT  12
#define ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL_MASK 0x2000u
#define ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL_SHIFT 13
#define ANADIG_ANA_MISC0_OSC_XTALOK_MASK         0x10000u
#define ANADIG_ANA_MISC0_OSC_XTALOK_SHIFT        16
#define ANADIG_ANA_MISC0_OSC_XTALOK_EN_MASK      0x20000u
#define ANADIG_ANA_MISC0_OSC_XTALOK_EN_SHIFT     17
/* ANA_MISC1 Bit Fields */
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN_MASK      0x400u
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN_SHIFT     10
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN_MASK      0x1000u
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN_SHIFT     12
#define ANADIG_ANA_MISC1_IRQ_TEMPSENSE_MASK      0x20000000u
#define ANADIG_ANA_MISC1_IRQ_TEMPSENSE_SHIFT     29
#define ANADIG_ANA_MISC1_IRQ_ANA_BO_MASK         0x40000000u
#define ANADIG_ANA_MISC1_IRQ_ANA_BO_SHIFT        30
/* DIGPROG Bit Fields */
#define ANADIG_DIGPROG_MINOR_MASK                0xFFu
#define ANADIG_DIGPROG_MINOR_SHIFT               0
#define ANADIG_DIGPROG_MINOR(x)                  (((uint32_t)(((uint32_t)(x))<<ANADIG_DIGPROG_MINOR_SHIFT))&ANADIG_DIGPROG_MINOR_MASK)
#define ANADIG_DIGPROG_MAJOR_MASK                0xFFFF00u
#define ANADIG_DIGPROG_MAJOR_SHIFT               8
#define ANADIG_DIGPROG_MAJOR(x)                  (((uint32_t)(((uint32_t)(x))<<ANADIG_DIGPROG_MAJOR_SHIFT))&ANADIG_DIGPROG_MAJOR_MASK)
/* PLL1_CTRL Bit Fields */
#define ANADIG_PLL1_CTRL_DIV_SELECT_MASK         0x1u
#define ANADIG_PLL1_CTRL_DIV_SELECT_SHIFT        0
#define ANADIG_PLL1_CTRL_POWERDOWN_MASK          0x1000u
#define ANADIG_PLL1_CTRL_POWERDOWN_SHIFT         12
#define ANADIG_PLL1_CTRL_ENABLE_MASK             0x2000u
#define ANADIG_PLL1_CTRL_ENABLE_SHIFT            13
#define ANADIG_PLL1_CTRL_BYPASS_CLK_SRC_MASK     0x4000u
#define ANADIG_PLL1_CTRL_BYPASS_CLK_SRC_SHIFT    14
#define ANADIG_PLL1_CTRL_BYPASS_MASK             0x10000u
#define ANADIG_PLL1_CTRL_BYPASS_SHIFT            16
#define ANADIG_PLL1_CTRL_DITHER_ENABLE_MASK      0x20000u
#define ANADIG_PLL1_CTRL_DITHER_ENABLE_SHIFT     17
#define ANADIG_PLL1_CTRL_PFD_OFFSET_EN_MASK      0x40000u
#define ANADIG_PLL1_CTRL_PFD_OFFSET_EN_SHIFT     18
#define ANADIG_PLL1_CTRL_LOCK_MASK               0x80000000u
#define ANADIG_PLL1_CTRL_LOCK_SHIFT              31
/* PLL1_SS Bit Fields */
#define ANADIG_PLL1_SS_STEP_MASK                 0x7FFFu
#define ANADIG_PLL1_SS_STEP_SHIFT                0
#define ANADIG_PLL1_SS_STEP(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_SS_STEP_SHIFT))&ANADIG_PLL1_SS_STEP_MASK)
#define ANADIG_PLL1_SS_ENABLE_MASK               0x8000u
#define ANADIG_PLL1_SS_ENABLE_SHIFT              15
#define ANADIG_PLL1_SS_STOP_MASK                 0xFFFF0000u
#define ANADIG_PLL1_SS_STOP_SHIFT                16
#define ANADIG_PLL1_SS_STOP(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_SS_STOP_SHIFT))&ANADIG_PLL1_SS_STOP_MASK)
/* PLL1_NUM Bit Fields */
#define ANADIG_PLL1_NUM_A_MASK                   0x3FFFFFFFu
#define ANADIG_PLL1_NUM_A_SHIFT                  0
#define ANADIG_PLL1_NUM_A(x)                     (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_NUM_A_SHIFT))&ANADIG_PLL1_NUM_A_MASK)
/* PLL1_DENOM Bit Fields */
#define ANADIG_PLL1_DENOM_B_MASK                 0x3FFFFFFFu
#define ANADIG_PLL1_DENOM_B_SHIFT                0
#define ANADIG_PLL1_DENOM_B(x)                   (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_DENOM_B_SHIFT))&ANADIG_PLL1_DENOM_B_MASK)
/* PLL1_PFD Bit Fields */
#define ANADIG_PLL1_PFD_PFD1_FRAC_MASK           0x3Fu
#define ANADIG_PLL1_PFD_PFD1_FRAC_SHIFT          0
#define ANADIG_PLL1_PFD_PFD1_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_PFD_PFD1_FRAC_SHIFT))&ANADIG_PLL1_PFD_PFD1_FRAC_MASK)
#define ANADIG_PLL1_PFD_D1_STABLE_MASK           0x40u
#define ANADIG_PLL1_PFD_D1_STABLE_SHIFT          6
#define ANADIG_PLL1_PFD_PFD1_CLKGATE_MASK        0x80u
#define ANADIG_PLL1_PFD_PFD1_CLKGATE_SHIFT       7
#define ANADIG_PLL1_PFD_PFD2_FRAC_MASK           0x3F00u
#define ANADIG_PLL1_PFD_PFD2_FRAC_SHIFT          8
#define ANADIG_PLL1_PFD_PFD2_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_PFD_PFD2_FRAC_SHIFT))&ANADIG_PLL1_PFD_PFD2_FRAC_MASK)
#define ANADIG_PLL1_PFD_PFD2_STABLE_MASK         0x4000u
#define ANADIG_PLL1_PFD_PFD2_STABLE_SHIFT        14
#define ANADIG_PLL1_PFD_PFD2_CLKGATE_MASK        0x8000u
#define ANADIG_PLL1_PFD_PFD2_CLKGATE_SHIFT       15
#define ANADIG_PLL1_PFD_PFD3_FRAC_MASK           0x3F0000u
#define ANADIG_PLL1_PFD_PFD3_FRAC_SHIFT          16
#define ANADIG_PLL1_PFD_PFD3_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_PFD_PFD3_FRAC_SHIFT))&ANADIG_PLL1_PFD_PFD3_FRAC_MASK)
#define ANADIG_PLL1_PFD_PFD3_STABLE_MASK         0x400000u
#define ANADIG_PLL1_PFD_PFD3_STABLE_SHIFT        22
#define ANADIG_PLL1_PFD_PFD3_CLKGATE_MASK        0x800000u
#define ANADIG_PLL1_PFD_PFD3_CLKGATE_SHIFT       23
#define ANADIG_PLL1_PFD_PFD4_FRAC_MASK           0x3F000000u
#define ANADIG_PLL1_PFD_PFD4_FRAC_SHIFT          24
#define ANADIG_PLL1_PFD_PFD4_FRAC(x)             (((uint32_t)(((uint32_t)(x))<<ANADIG_PLL1_PFD_PFD4_FRAC_SHIFT))&ANADIG_PLL1_PFD_PFD4_FRAC_MASK)
#define ANADIG_PLL1_PFD_PFD4_STABLE_MASK         0x40000000u
#define ANADIG_PLL1_PFD_PFD4_STABLE_SHIFT        30
#define ANADIG_PLL1_PFD_PFD4_CLKGATE_MASK        0x80000000u
#define ANADIG_PLL1_PFD_PFD4_CLKGATE_SHIFT       31
/* PLL_LOCK Bit Fields */
#define ANADIG_PLL_LOCK_PLL7_MASK                0x1u
#define ANADIG_PLL_LOCK_PLL7_SHIFT               0
#define ANADIG_PLL_LOCK_PLL3_MASK                0x2u
#define ANADIG_PLL_LOCK_PLL3_SHIFT               1
#define ANADIG_PLL_LOCK_PLL5_MASK                0x4u
#define ANADIG_PLL_LOCK_PLL5_SHIFT               2
#define ANADIG_PLL_LOCK_PLL6_MASK                0x8u
#define ANADIG_PLL_LOCK_PLL6_SHIFT               3
#define ANADIG_PLL_LOCK_PLL4_MASK                0x10u
#define ANADIG_PLL_LOCK_PLL4_SHIFT               4
#define ANADIG_PLL_LOCK_PLL2_MASK                0x20u
#define ANADIG_PLL_LOCK_PLL2_SHIFT               5
#define ANADIG_PLL_LOCK_PLL1_MASK                0x40u
#define ANADIG_PLL_LOCK_PLL1_SHIFT               6

/**
 * @}
 */ /* end of group ANADIG_Register_Masks */


/* ANADIG - Peripheral instance base addresses */
/** Peripheral ANADIG base address */
#define ANADIG_BASE                              (0x40050000u)
/** Peripheral ANADIG base pointer */
#define ANADIG                                   ((ANADIG_Type *)ANADIG_BASE)
/** Array initializer of ANADIG peripheral base pointers */
#define ANADIG_BASES                             { ANADIG }

/**
 * @}
 */ /* end of group ANADIG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ASRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
 * @{
 */

/** ASRC - Register Layout Typedef */
typedef struct {
  __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
  __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
  __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
  __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
  __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
  __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
  __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
       uint8_t RESERVED_1[28];
  __IO uint32_t ASRPMn[5];                         /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
  __IO uint32_t ASRTFR1;                           /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
       uint8_t RESERVED_2[4];
  __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
  struct {                                         /* offset: 0x60, array step: 0x8 */
    __IO uint32_t ASRDI;                             /**< ASRC Data Input Register for Pair x, array offset: 0x60, array step: 0x8 */
    __I  uint32_t ASRDO;                             /**< ASRC Data Output Register for Pair x, array offset: 0x64, array step: 0x8 */
  } ASRD[3];
       uint8_t RESERVED_3[8];
  __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
  __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
  __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
  __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
  __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
  __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
  __IO uint32_t ASR76K;                            /**< ASRC 76kHz Period in terms of ASRC processing clock, offset: 0x98 */
  __IO uint32_t ASR56K;                            /**< ASRC 56kHz Period in terms of ASRC processing clock, offset: 0x9C */
  __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
  __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
  __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
  __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
  __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
  __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
       uint8_t RESERVED_4[8];
  __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
} ASRC_Type;

/* ----------------------------------------------------------------------------
   -- ASRC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ASRC_Register_Masks ASRC Register Masks
 * @{
 */

/* ASRCTR Bit Fields */
#define ASRC_ASRCTR_ASRCEN_MASK                  0x1u
#define ASRC_ASRCTR_ASRCEN_SHIFT                 0
#define ASRC_ASRCTR_ASREA_MASK                   0x2u
#define ASRC_ASRCTR_ASREA_SHIFT                  1
#define ASRC_ASRCTR_ASREB_MASK                   0x4u
#define ASRC_ASRCTR_ASREB_SHIFT                  2
#define ASRC_ASRCTR_ASREC_MASK                   0x8u
#define ASRC_ASRCTR_ASREC_SHIFT                  3
#define ASRC_ASRCTR_SRST_MASK                    0x10u
#define ASRC_ASRCTR_SRST_SHIFT                   4
#define ASRC_ASRCTR_IDRA_MASK                    0x2000u
#define ASRC_ASRCTR_IDRA_SHIFT                   13
#define ASRC_ASRCTR_USRA_MASK                    0x4000u
#define ASRC_ASRCTR_USRA_SHIFT                   14
#define ASRC_ASRCTR_IDRB_MASK                    0x8000u
#define ASRC_ASRCTR_IDRB_SHIFT                   15
#define ASRC_ASRCTR_USRB_MASK                    0x10000u
#define ASRC_ASRCTR_USRB_SHIFT                   16
#define ASRC_ASRCTR_IDRC_MASK                    0x20000u
#define ASRC_ASRCTR_IDRC_SHIFT                   17
#define ASRC_ASRCTR_USRC_MASK                    0x40000u
#define ASRC_ASRCTR_USRC_SHIFT                   18
#define ASRC_ASRCTR_ATSA_MASK                    0x100000u
#define ASRC_ASRCTR_ATSA_SHIFT                   20
#define ASRC_ASRCTR_ATSB_MASK                    0x200000u
#define ASRC_ASRCTR_ATSB_SHIFT                   21
#define ASRC_ASRCTR_ATSC_MASK                    0x400000u
#define ASRC_ASRCTR_ATSC_SHIFT                   22
/* ASRIER Bit Fields */
#define ASRC_ASRIER_ADIEA_MASK                   0x1u
#define ASRC_ASRIER_ADIEA_SHIFT                  0
#define ASRC_ASRIER_ADIEB_MASK                   0x2u
#define ASRC_ASRIER_ADIEB_SHIFT                  1
#define ASRC_ASRIER_ADIEC_MASK                   0x4u
#define ASRC_ASRIER_ADIEC_SHIFT                  2
#define ASRC_ASRIER_ADOEA_MASK                   0x8u
#define ASRC_ASRIER_ADOEA_SHIFT                  3
#define ASRC_ASRIER_ADOEB_MASK                   0x10u
#define ASRC_ASRIER_ADOEB_SHIFT                  4
#define ASRC_ASRIER_ADOEC_MASK                   0x20u
#define ASRC_ASRIER_ADOEC_SHIFT                  5
#define ASRC_ASRIER_AOLIE_MASK                   0x40u
#define ASRC_ASRIER_AOLIE_SHIFT                  6
#define ASRC_ASRIER_AFPWE_MASK                   0x80u
#define ASRC_ASRIER_AFPWE_SHIFT                  7
/* ASRCNCR Bit Fields */
#define ASRC_ASRCNCR_ANCA_MASK                   0xFu
#define ASRC_ASRCNCR_ANCA_SHIFT                  0
#define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCA_SHIFT))&ASRC_ASRCNCR_ANCA_MASK)
#define ASRC_ASRCNCR_ANCB_MASK                   0xF0u
#define ASRC_ASRCNCR_ANCB_SHIFT                  4
#define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCB_SHIFT))&ASRC_ASRCNCR_ANCB_MASK)
#define ASRC_ASRCNCR_ANCC_MASK                   0xF00u
#define ASRC_ASRCNCR_ANCC_SHIFT                  8
#define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCC_SHIFT))&ASRC_ASRCNCR_ANCC_MASK)
/* ASRCFG Bit Fields */
#define ASRC_ASRCFG_PREMODA_MASK                 0xC0u
#define ASRC_ASRCFG_PREMODA_SHIFT                6
#define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODA_SHIFT))&ASRC_ASRCFG_PREMODA_MASK)
#define ASRC_ASRCFG_POSTMODA_MASK                0x300u
#define ASRC_ASRCFG_POSTMODA_SHIFT               8
#define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODA_SHIFT))&ASRC_ASRCFG_POSTMODA_MASK)
#define ASRC_ASRCFG_PREMODB_MASK                 0xC00u
#define ASRC_ASRCFG_PREMODB_SHIFT                10
#define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODB_SHIFT))&ASRC_ASRCFG_PREMODB_MASK)
#define ASRC_ASRCFG_POSTMODB_MASK                0x3000u
#define ASRC_ASRCFG_POSTMODB_SHIFT               12
#define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODB_SHIFT))&ASRC_ASRCFG_POSTMODB_MASK)
#define ASRC_ASRCFG_PREMODC_MASK                 0xC000u
#define ASRC_ASRCFG_PREMODC_SHIFT                14
#define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODC_SHIFT))&ASRC_ASRCFG_PREMODC_MASK)
#define ASRC_ASRCFG_POSTMODC_MASK                0x30000u
#define ASRC_ASRCFG_POSTMODC_SHIFT               16
#define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODC_SHIFT))&ASRC_ASRCFG_POSTMODC_MASK)
#define ASRC_ASRCFG_NDPRA_MASK                   0x40000u
#define ASRC_ASRCFG_NDPRA_SHIFT                  18
#define ASRC_ASRCFG_NDPRB_MASK                   0x80000u
#define ASRC_ASRCFG_NDPRB_SHIFT                  19
#define ASRC_ASRCFG_NDPRC_MASK                   0x100000u
#define ASRC_ASRCFG_NDPRC_SHIFT                  20
#define ASRC_ASRCFG_INIRQA_MASK                  0x200000u
#define ASRC_ASRCFG_INIRQA_SHIFT                 21
#define ASRC_ASRCFG_INIRQB_MASK                  0x400000u
#define ASRC_ASRCFG_INIRQB_SHIFT                 22
#define ASRC_ASRCFG_INIRQC_MASK                  0x800000u
#define ASRC_ASRCFG_INIRQC_SHIFT                 23
/* ASRCSR Bit Fields */
#define ASRC_ASRCSR_AICSA_MASK                   0xFu
#define ASRC_ASRCSR_AICSA_SHIFT                  0
#define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSA_SHIFT))&ASRC_ASRCSR_AICSA_MASK)
#define ASRC_ASRCSR_AICSB_MASK                   0xF0u
#define ASRC_ASRCSR_AICSB_SHIFT                  4
#define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSB_SHIFT))&ASRC_ASRCSR_AICSB_MASK)
#define ASRC_ASRCSR_AICSC_MASK                   0xF00u
#define ASRC_ASRCSR_AICSC_SHIFT                  8
#define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSC_SHIFT))&ASRC_ASRCSR_AICSC_MASK)
#define ASRC_ASRCSR_AOCSA_MASK                   0xF000u
#define ASRC_ASRCSR_AOCSA_SHIFT                  12
#define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSA_SHIFT))&ASRC_ASRCSR_AOCSA_MASK)
#define ASRC_ASRCSR_AOCSB_MASK                   0xF0000u
#define ASRC_ASRCSR_AOCSB_SHIFT                  16
#define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSB_SHIFT))&ASRC_ASRCSR_AOCSB_MASK)
#define ASRC_ASRCSR_AOCSC_MASK                   0xF00000u
#define ASRC_ASRCSR_AOCSC_SHIFT                  20
#define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSC_SHIFT))&ASRC_ASRCSR_AOCSC_MASK)
/* ASRCDR1 Bit Fields */
#define ASRC_ASRCDR1_AICPA_MASK                  0x7u
#define ASRC_ASRCDR1_AICPA_SHIFT                 0
#define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICPA_SHIFT))&ASRC_ASRCDR1_AICPA_MASK)
#define ASRC_ASRCDR1_AICDA_MASK                  0x38u
#define ASRC_ASRCDR1_AICDA_SHIFT                 3
#define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICDA_SHIFT))&ASRC_ASRCDR1_AICDA_MASK)
#define ASRC_ASRCDR1_AICPB_MASK                  0x1C0u
#define ASRC_ASRCDR1_AICPB_SHIFT                 6
#define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICPB_SHIFT))&ASRC_ASRCDR1_AICPB_MASK)
#define ASRC_ASRCDR1_AICDB_MASK                  0xE00u
#define ASRC_ASRCDR1_AICDB_SHIFT                 9
#define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICDB_SHIFT))&ASRC_ASRCDR1_AICDB_MASK)
#define ASRC_ASRCDR1_AOCPA_MASK                  0x7000u
#define ASRC_ASRCDR1_AOCPA_SHIFT                 12
#define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCPA_SHIFT))&ASRC_ASRCDR1_AOCPA_MASK)
#define ASRC_ASRCDR1_AOCDA_MASK                  0x38000u
#define ASRC_ASRCDR1_AOCDA_SHIFT                 15
#define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCDA_SHIFT))&ASRC_ASRCDR1_AOCDA_MASK)
#define ASRC_ASRCDR1_AOCPB_MASK                  0x1C0000u
#define ASRC_ASRCDR1_AOCPB_SHIFT                 18
#define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCPB_SHIFT))&ASRC_ASRCDR1_AOCPB_MASK)
#define ASRC_ASRCDR1_AOCDB_MASK                  0xE00000u
#define ASRC_ASRCDR1_AOCDB_SHIFT                 21
#define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCDB_SHIFT))&ASRC_ASRCDR1_AOCDB_MASK)
/* ASRCDR2 Bit Fields */
#define ASRC_ASRCDR2_AICPC_MASK                  0x7u
#define ASRC_ASRCDR2_AICPC_SHIFT                 0
#define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AICPC_SHIFT))&ASRC_ASRCDR2_AICPC_MASK)
#define ASRC_ASRCDR2_AICDC_MASK                  0x38u
#define ASRC_ASRCDR2_AICDC_SHIFT                 3
#define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AICDC_SHIFT))&ASRC_ASRCDR2_AICDC_MASK)
#define ASRC_ASRCDR2_AOCPC_MASK                  0x1C0u
#define ASRC_ASRCDR2_AOCPC_SHIFT                 6
#define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AOCPC_SHIFT))&ASRC_ASRCDR2_AOCPC_MASK)
#define ASRC_ASRCDR2_AOCDC_MASK                  0xE00u
#define ASRC_ASRCDR2_AOCDC_SHIFT                 9
#define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AOCDC_SHIFT))&ASRC_ASRCDR2_AOCDC_MASK)
/* ASRSTR Bit Fields */
#define ASRC_ASRSTR_AIDEA_MASK                   0x1u
#define ASRC_ASRSTR_AIDEA_SHIFT                  0
#define ASRC_ASRSTR_AIDEB_MASK                   0x2u
#define ASRC_ASRSTR_AIDEB_SHIFT                  1
#define ASRC_ASRSTR_AIDEC_MASK                   0x4u
#define ASRC_ASRSTR_AIDEC_SHIFT                  2
#define ASRC_ASRSTR_AODFA_MASK                   0x8u
#define ASRC_ASRSTR_AODFA_SHIFT                  3
#define ASRC_ASRSTR_AODFB_MASK                   0x10u
#define ASRC_ASRSTR_AODFB_SHIFT                  4
#define ASRC_ASRSTR_AODFC_MASK                   0x20u
#define ASRC_ASRSTR_AODFC_SHIFT                  5
#define ASRC_ASRSTR_AOLE_MASK                    0x40u
#define ASRC_ASRSTR_AOLE_SHIFT                   6
#define ASRC_ASRSTR_FPWT_MASK                    0x80u
#define ASRC_ASRSTR_FPWT_SHIFT                   7
#define ASRC_ASRSTR_AIDUA_MASK                   0x100u
#define ASRC_ASRSTR_AIDUA_SHIFT                  8
#define ASRC_ASRSTR_AIDUB_MASK                   0x200u
#define ASRC_ASRSTR_AIDUB_SHIFT                  9
#define ASRC_ASRSTR_AIDUC_MASK                   0x400u
#define ASRC_ASRSTR_AIDUC_SHIFT                  10
#define ASRC_ASRSTR_AODOA_MASK                   0x800u
#define ASRC_ASRSTR_AODOA_SHIFT                  11
#define ASRC_ASRSTR_AODOB_MASK                   0x1000u
#define ASRC_ASRSTR_AODOB_SHIFT                  12
#define ASRC_ASRSTR_AODOC_MASK                   0x2000u
#define ASRC_ASRSTR_AODOC_SHIFT                  13
#define ASRC_ASRSTR_AIOLA_MASK                   0x4000u
#define ASRC_ASRSTR_AIOLA_SHIFT                  14
#define ASRC_ASRSTR_AIOLB_MASK                   0x8000u
#define ASRC_ASRSTR_AIOLB_SHIFT                  15
#define ASRC_ASRSTR_AIOLC_MASK                   0x10000u
#define ASRC_ASRSTR_AIOLC_SHIFT                  16
#define ASRC_ASRSTR_AOOLA_MASK                   0x20000u
#define ASRC_ASRSTR_AOOLA_SHIFT                  17
#define ASRC_ASRSTR_AOOLB_MASK                   0x40000u
#define ASRC_ASRSTR_AOOLB_SHIFT                  18
#define ASRC_ASRSTR_AOOLC_MASK                   0x80000u
#define ASRC_ASRSTR_AOOLC_SHIFT                  19
#define ASRC_ASRSTR_ATQOL_MASK                   0x100000u
#define ASRC_ASRSTR_ATQOL_SHIFT                  20
#define ASRC_ASRSTR_DSLCNT_MASK                  0x200000u
#define ASRC_ASRSTR_DSLCNT_SHIFT                 21
/* ASRPMn Bit Fields */
#define ASRC_ASRPMn_PARAMETER_VALUE_MASK         0xFFFFFFu
#define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT        0
#define ASRC_ASRPMn_PARAMETER_VALUE(x)           (((uint32_t)(((uint32_t)(x))<<ASRC_ASRPMn_PARAMETER_VALUE_SHIFT))&ASRC_ASRPMn_PARAMETER_VALUE_MASK)
/* ASRTFR1 Bit Fields */
#define ASRC_ASRTFR1_TF_BASE_MASK                0x1FC0u
#define ASRC_ASRTFR1_TF_BASE_SHIFT               6
#define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRTFR1_TF_BASE_SHIFT))&ASRC_ASRTFR1_TF_BASE_MASK)
#define ASRC_ASRTFR1_TF_FILL_MASK                0xFE000u
#define ASRC_ASRTFR1_TF_FILL_SHIFT               13
#define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x))<<ASRC_ASRTFR1_TF_FILL_SHIFT))&ASRC_ASRTFR1_TF_FILL_MASK)
/* ASRCCR Bit Fields */
#define ASRC_ASRCCR_ACIA_MASK                    0xFu
#define ASRC_ASRCCR_ACIA_SHIFT                   0
#define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIA_SHIFT))&ASRC_ASRCCR_ACIA_MASK)
#define ASRC_ASRCCR_ACIB_MASK                    0xF0u
#define ASRC_ASRCCR_ACIB_SHIFT                   4
#define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIB_SHIFT))&ASRC_ASRCCR_ACIB_MASK)
#define ASRC_ASRCCR_ACIC_MASK                    0xF00u
#define ASRC_ASRCCR_ACIC_SHIFT                   8
#define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIC_SHIFT))&ASRC_ASRCCR_ACIC_MASK)
#define ASRC_ASRCCR_ACOA_MASK                    0xF000u
#define ASRC_ASRCCR_ACOA_SHIFT                   12
#define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOA_SHIFT))&ASRC_ASRCCR_ACOA_MASK)
#define ASRC_ASRCCR_ACOB_MASK                    0xF0000u
#define ASRC_ASRCCR_ACOB_SHIFT                   16
#define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOB_SHIFT))&ASRC_ASRCCR_ACOB_MASK)
#define ASRC_ASRCCR_ACOC_MASK                    0xF00000u
#define ASRC_ASRCCR_ACOC_SHIFT                   20
#define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOC_SHIFT))&ASRC_ASRCCR_ACOC_MASK)
/* ASRDI Bit Fields */
#define ASRC_ASRDI_DATA_MASK                     0xFFFFFFu
#define ASRC_ASRDI_DATA_SHIFT                    0
#define ASRC_ASRDI_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRDI_DATA_SHIFT))&ASRC_ASRDI_DATA_MASK)
/* ASRDO Bit Fields */
#define ASRC_ASRDO_DATA_MASK                     0xFFFFFFu
#define ASRC_ASRDO_DATA_SHIFT                    0
#define ASRC_ASRDO_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRDO_DATA_SHIFT))&ASRC_ASRDO_DATA_MASK)
/* ASRIDRHA Bit Fields */
#define ASRC_ASRIDRHA_IDRATIOA_MASK              0xFFu
#define ASRC_ASRIDRHA_IDRATIOA_SHIFT             0
#define ASRC_ASRIDRHA_IDRATIOA(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHA_IDRATIOA_SHIFT))&ASRC_ASRIDRHA_IDRATIOA_MASK)
/* ASRIDRLA Bit Fields */
#define ASRC_ASRIDRLA_IDRATIOA_MASK              0xFFFFFFu
#define ASRC_ASRIDRLA_IDRATIOA_SHIFT             0
#define ASRC_ASRIDRLA_IDRATIOA(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLA_IDRATIOA_SHIFT))&ASRC_ASRIDRLA_IDRATIOA_MASK)
/* ASRIDRHB Bit Fields */
#define ASRC_ASRIDRHB_IDRATIOB_MASK              0xFFu
#define ASRC_ASRIDRHB_IDRATIOB_SHIFT             0
#define ASRC_ASRIDRHB_IDRATIOB(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHB_IDRATIOB_SHIFT))&ASRC_ASRIDRHB_IDRATIOB_MASK)
/* ASRIDRLB Bit Fields */
#define ASRC_ASRIDRLB_IDRATIOB_MASK              0xFFFFFFu
#define ASRC_ASRIDRLB_IDRATIOB_SHIFT             0
#define ASRC_ASRIDRLB_IDRATIOB(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLB_IDRATIOB_SHIFT))&ASRC_ASRIDRLB_IDRATIOB_MASK)
/* ASRIDRHC Bit Fields */
#define ASRC_ASRIDRHC_IDRATIOC_MASK              0xFFu
#define ASRC_ASRIDRHC_IDRATIOC_SHIFT             0
#define ASRC_ASRIDRHC_IDRATIOC(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHC_IDRATIOC_SHIFT))&ASRC_ASRIDRHC_IDRATIOC_MASK)
/* ASRIDRLC Bit Fields */
#define ASRC_ASRIDRLC_IDRATIOC_MASK              0xFFFFFFu
#define ASRC_ASRIDRLC_IDRATIOC_SHIFT             0
#define ASRC_ASRIDRLC_IDRATIOC(x)                (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLC_IDRATIOC_SHIFT))&ASRC_ASRIDRLC_IDRATIOC_MASK)
/* ASR76K Bit Fields */
#define ASRC_ASR76K_ASR76K_MASK                  0x1FFFFu
#define ASRC_ASR76K_ASR76K_SHIFT                 0
#define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASR76K_ASR76K_SHIFT))&ASRC_ASR76K_ASR76K_MASK)
/* ASR56K Bit Fields */
#define ASRC_ASR56K_ASR56K_MASK                  0x1FFFFu
#define ASRC_ASR56K_ASR56K_SHIFT                 0
#define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x))<<ASRC_ASR56K_ASR56K_SHIFT))&ASRC_ASR56K_ASR56K_MASK)
/* ASRMCRA Bit Fields */
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      0x3Fu
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     0
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT))&ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
#define ASRC_ASRMCRA_RSYNOFA_MASK                0x400u
#define ASRC_ASRMCRA_RSYNOFA_SHIFT               10
#define ASRC_ASRMCRA_RSYNIFA_MASK                0x800u
#define ASRC_ASRMCRA_RSYNIFA_SHIFT               11
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     0x3F000u
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    12
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT))&ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
#define ASRC_ASRMCRA_BYPASSPOLYA_MASK            0x100000u
#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           20
#define ASRC_ASRMCRA_BUFSTALLA_MASK              0x200000u
#define ASRC_ASRMCRA_BUFSTALLA_SHIFT             21
#define ASRC_ASRMCRA_EXTTHRSHA_MASK              0x400000u
#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             22
#define ASRC_ASRMCRA_ZEROBUFA_MASK               0x800000u
#define ASRC_ASRMCRA_ZEROBUFA_SHIFT              23
/* ASRFSTA Bit Fields */
#define ASRC_ASRFSTA_INFIFO_FILLA_MASK           0x7Fu
#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          0
#define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTA_INFIFO_FILLA_SHIFT))&ASRC_ASRFSTA_INFIFO_FILLA_MASK)
#define ASRC_ASRFSTA_IAEA_MASK                   0x800u
#define ASRC_ASRFSTA_IAEA_SHIFT                  11
#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          0x7F000u
#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         12
#define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT))&ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
#define ASRC_ASRFSTA_OAFA_MASK                   0x800000u
#define ASRC_ASRFSTA_OAFA_SHIFT                  23
/* ASRMCRB Bit Fields */
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      0x3Fu
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     0
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT))&ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
#define ASRC_ASRMCRB_RSYNOFB_MASK                0x400u
#define ASRC_ASRMCRB_RSYNOFB_SHIFT               10
#define ASRC_ASRMCRB_RSYNIFB_MASK                0x800u
#define ASRC_ASRMCRB_RSYNIFB_SHIFT               11
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     0x3F000u
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    12
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT))&ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
#define ASRC_ASRMCRB_BYPASSPOLYB_MASK            0x100000u
#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           20
#define ASRC_ASRMCRB_BUFSTALLB_MASK              0x200000u
#define ASRC_ASRMCRB_BUFSTALLB_SHIFT             21
#define ASRC_ASRMCRB_EXTTHRSHB_MASK              0x400000u
#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             22
#define ASRC_ASRMCRB_ZEROBUFB_MASK               0x800000u
#define ASRC_ASRMCRB_ZEROBUFB_SHIFT              23
/* ASRFSTB Bit Fields */
#define ASRC_ASRFSTB_INFIFO_FILLB_MASK           0x7Fu
#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          0
#define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTB_INFIFO_FILLB_SHIFT))&ASRC_ASRFSTB_INFIFO_FILLB_MASK)
#define ASRC_ASRFSTB_IAEB_MASK                   0x800u
#define ASRC_ASRFSTB_IAEB_SHIFT                  11
#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          0x7F000u
#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         12
#define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT))&ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
#define ASRC_ASRFSTB_OAFB_MASK                   0x800000u
#define ASRC_ASRFSTB_OAFB_SHIFT                  23
/* ASRMCRC Bit Fields */
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      0x3Fu
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     0
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT))&ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
#define ASRC_ASRMCRC_RSYNOFC_MASK                0x400u
#define ASRC_ASRMCRC_RSYNOFC_SHIFT               10
#define ASRC_ASRMCRC_RSYNIFC_MASK                0x800u
#define ASRC_ASRMCRC_RSYNIFC_SHIFT               11
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     0x3F000u
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    12
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT))&ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
#define ASRC_ASRMCRC_BYPASSPOLYC_MASK            0x100000u
#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           20
#define ASRC_ASRMCRC_BUFSTALLC_MASK              0x200000u
#define ASRC_ASRMCRC_BUFSTALLC_SHIFT             21
#define ASRC_ASRMCRC_EXTTHRSHC_MASK              0x400000u
#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             22
#define ASRC_ASRMCRC_ZEROBUFC_MASK               0x800000u
#define ASRC_ASRMCRC_ZEROBUFC_SHIFT              23
/* ASRFSTC Bit Fields */
#define ASRC_ASRFSTC_INFIFO_FILLC_MASK           0x7Fu
#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          0
#define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTC_INFIFO_FILLC_SHIFT))&ASRC_ASRFSTC_INFIFO_FILLC_MASK)
#define ASRC_ASRFSTC_IAEC_MASK                   0x800u
#define ASRC_ASRFSTC_IAEC_SHIFT                  11
#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          0x7F000u
#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         12
#define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT))&ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
#define ASRC_ASRFSTC_OAFC_MASK                   0x800000u
#define ASRC_ASRFSTC_OAFC_SHIFT                  23
/* ASRMCR1 Bit Fields */
#define ASRC_ASRMCR1_OW16_MASK                   0x1u
#define ASRC_ASRMCR1_OW16_SHIFT                  0
#define ASRC_ASRMCR1_OSGN_MASK                   0x2u
#define ASRC_ASRMCR1_OSGN_SHIFT                  1
#define ASRC_ASRMCR1_OMSB_MASK                   0x4u
#define ASRC_ASRMCR1_OMSB_SHIFT                  2
#define ASRC_ASRMCR1_IMSB_MASK                   0x100u
#define ASRC_ASRMCR1_IMSB_SHIFT                  8
#define ASRC_ASRMCR1_IWD_MASK                    0xE00u
#define ASRC_ASRMCR1_IWD_SHIFT                   9
#define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCR1_IWD_SHIFT))&ASRC_ASRMCR1_IWD_MASK)

/**
 * @}
 */ /* end of group ASRC_Register_Masks */


/* ASRC - Peripheral instance base addresses */
/** Peripheral ASRC base address */
#define ASRC_BASE                                (0x40060000u)
/** Peripheral ASRC base pointer */
#define ASRC                                     ((ASRC_Type *)ASRC_BASE)
/** Array initializer of ASRC peripheral base pointers */
#define ASRC_BASES                               { ASRC }

/**
 * @}
 */ /* end of group ASRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CAN Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
 * @{
 */

/** CAN - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
  __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
  __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
       uint8_t RESERVED_1[8];
  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
       uint8_t RESERVED_2[48];
  struct {                                         /* offset: 0x80, array step: 0x10 */
    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
  } MB[64];
       uint8_t RESERVED_3[1024];
  __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
       uint8_t RESERVED_4[352];
  __IO uint32_t MECR;                              /**< Memory Error Control Register, offset: 0xAE0 */
  __IO uint32_t ERRIAR;                            /**< Error Injection Address Register, offset: 0xAE4 */
  __IO uint32_t ERRIDPR;                           /**< Error Injection Data Pattern Register, offset: 0xAE8 */
  __IO uint32_t ERRIPPR;                           /**< Error Injection Parity Pattern Register, offset: 0xAEC */
  __I  uint32_t RERRAR;                            /**< Error Report Address Register, offset: 0xAF0 */
  __IO uint32_t RERRDR;                            /**< Error Report Data Register, offset: 0xAF4 */
  __IO uint32_t RERRSYNR;                          /**< Error Report Syndrome Register, offset: 0xAF8 */
  __IO uint32_t ERRSR;                             /**< Error Status Register, offset: 0xAFC */
} CAN_Type;

/* ----------------------------------------------------------------------------
   -- CAN Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CAN_Register_Masks CAN Register Masks
 * @{
 */

/* MCR Bit Fields */
#define CAN_MCR_MAXMB_MASK                       0x7Fu
#define CAN_MCR_MAXMB_SHIFT                      0
#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK                        0x300u
#define CAN_MCR_IDAM_SHIFT                       8
#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK                         0x1000u
#define CAN_MCR_AEN_SHIFT                        12
#define CAN_MCR_LPRIOEN_MASK                     0x2000u
#define CAN_MCR_LPRIOEN_SHIFT                    13
#define CAN_MCR_IRMQ_MASK                        0x10000u
#define CAN_MCR_IRMQ_SHIFT                       16
#define CAN_MCR_SRXDIS_MASK                      0x20000u
#define CAN_MCR_SRXDIS_SHIFT                     17
#define CAN_MCR_LPMACK_MASK                      0x100000u
#define CAN_MCR_LPMACK_SHIFT                     20
#define CAN_MCR_WRNEN_MASK                       0x200000u
#define CAN_MCR_WRNEN_SHIFT                      21
#define CAN_MCR_SUPV_MASK                        0x800000u
#define CAN_MCR_SUPV_SHIFT                       23
#define CAN_MCR_FRZACK_MASK                      0x1000000u
#define CAN_MCR_FRZACK_SHIFT                     24
#define CAN_MCR_SOFTRST_MASK                     0x2000000u
#define CAN_MCR_SOFTRST_SHIFT                    25
#define CAN_MCR_NOTRDY_MASK                      0x8000000u
#define CAN_MCR_NOTRDY_SHIFT                     27
#define CAN_MCR_HALT_MASK                        0x10000000u
#define CAN_MCR_HALT_SHIFT                       28
#define CAN_MCR_RFEN_MASK                        0x20000000u
#define CAN_MCR_RFEN_SHIFT                       29
#define CAN_MCR_FRZ_MASK                         0x40000000u
#define CAN_MCR_FRZ_SHIFT                        30
#define CAN_MCR_MDIS_MASK                        0x80000000u
#define CAN_MCR_MDIS_SHIFT                       31
/* CTRL1 Bit Fields */
#define CAN_CTRL1_PROPSEG_MASK                   0x7u
#define CAN_CTRL1_PROPSEG_SHIFT                  0
#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK                       0x8u
#define CAN_CTRL1_LOM_SHIFT                      3
#define CAN_CTRL1_LBUF_MASK                      0x10u
#define CAN_CTRL1_LBUF_SHIFT                     4
#define CAN_CTRL1_TSYN_MASK                      0x20u
#define CAN_CTRL1_TSYN_SHIFT                     5
#define CAN_CTRL1_BOFFREC_MASK                   0x40u
#define CAN_CTRL1_BOFFREC_SHIFT                  6
#define CAN_CTRL1_SMP_MASK                       0x80u
#define CAN_CTRL1_SMP_SHIFT                      7
#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
#define CAN_CTRL1_RWRNMSK_SHIFT                  10
#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
#define CAN_CTRL1_TWRNMSK_SHIFT                  11
#define CAN_CTRL1_LPB_MASK                       0x1000u
#define CAN_CTRL1_LPB_SHIFT                      12
#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
#define CAN_CTRL1_CLKSRC_SHIFT                   13
#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
#define CAN_CTRL1_ERRMSK_SHIFT                   14
#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
#define CAN_CTRL1_BOFFMSK_SHIFT                  15
#define CAN_CTRL1_PSEG2_MASK                     0x70000u
#define CAN_CTRL1_PSEG2_SHIFT                    16
#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK                     0x380000u
#define CAN_CTRL1_PSEG1_SHIFT                    19
#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK                       0xC00000u
#define CAN_CTRL1_RJW_SHIFT                      22
#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
#define CAN_CTRL1_PRESDIV_SHIFT                  24
#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
/* TIMER Bit Fields */
#define CAN_TIMER_TIMER_MASK                     0xFFFFu
#define CAN_TIMER_TIMER_SHIFT                    0
#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
/* RXMGMASK Bit Fields */
#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
#define CAN_RXMGMASK_MG_SHIFT                    0
#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
/* RX14MASK Bit Fields */
#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
#define CAN_RX14MASK_RX14M_SHIFT                 0
#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
/* RX15MASK Bit Fields */
#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
#define CAN_RX15MASK_RX15M_SHIFT                 0
#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
/* ECR Bit Fields */
#define CAN_ECR_TXERRCNT_MASK                    0xFFu
#define CAN_ECR_TXERRCNT_SHIFT                   0
#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
#define CAN_ECR_RXERRCNT_SHIFT                   8
#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
/* ESR1 Bit Fields */
#define CAN_ESR1_ERRINT_MASK                     0x2u
#define CAN_ESR1_ERRINT_SHIFT                    1
#define CAN_ESR1_BOFFINT_MASK                    0x4u
#define CAN_ESR1_BOFFINT_SHIFT                   2
#define CAN_ESR1_RX_MASK                         0x8u
#define CAN_ESR1_RX_SHIFT                        3
#define CAN_ESR1_FLTCONF_MASK                    0x30u
#define CAN_ESR1_FLTCONF_SHIFT                   4
#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK                         0x40u
#define CAN_ESR1_TX_SHIFT                        6
#define CAN_ESR1_IDLE_MASK                       0x80u
#define CAN_ESR1_IDLE_SHIFT                      7
#define CAN_ESR1_RXWRN_MASK                      0x100u
#define CAN_ESR1_RXWRN_SHIFT                     8
#define CAN_ESR1_TXWRN_MASK                      0x200u
#define CAN_ESR1_TXWRN_SHIFT                     9
#define CAN_ESR1_STFERR_MASK                     0x400u
#define CAN_ESR1_STFERR_SHIFT                    10
#define CAN_ESR1_FRMERR_MASK                     0x800u
#define CAN_ESR1_FRMERR_SHIFT                    11
#define CAN_ESR1_CRCERR_MASK                     0x1000u
#define CAN_ESR1_CRCERR_SHIFT                    12
#define CAN_ESR1_ACKERR_MASK                     0x2000u
#define CAN_ESR1_ACKERR_SHIFT                    13
#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
#define CAN_ESR1_BIT0ERR_SHIFT                   14
#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
#define CAN_ESR1_BIT1ERR_SHIFT                   15
#define CAN_ESR1_RWRNINT_MASK                    0x10000u
#define CAN_ESR1_RWRNINT_SHIFT                   16
#define CAN_ESR1_TWRNINT_MASK                    0x20000u
#define CAN_ESR1_TWRNINT_SHIFT                   17
#define CAN_ESR1_SYNCH_MASK                      0x40000u
#define CAN_ESR1_SYNCH_SHIFT                     18
/* IMASK2 Bit Fields */
#define CAN_IMASK2_BUFHM_MASK                    0xFFFFFFFFu
#define CAN_IMASK2_BUFHM_SHIFT                   0
#define CAN_IMASK2_BUFHM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
/* IMASK1 Bit Fields */
#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
#define CAN_IMASK1_BUFLM_SHIFT                   0
#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
/* IFLAG2 Bit Fields */
#define CAN_IFLAG2_BUFHI_MASK                    0xFFFFFFFFu
#define CAN_IFLAG2_BUFHI_SHIFT                   0
#define CAN_IFLAG2_BUFHI(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
/* IFLAG1 Bit Fields */
#define CAN_IFLAG1_BUF4TO0I_MASK                 0x1Fu
#define CAN_IFLAG1_BUF4TO0I_SHIFT                0
#define CAN_IFLAG1_BUF4TO0I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
#define CAN_IFLAG1_BUF5I_MASK                    0x20u
#define CAN_IFLAG1_BUF5I_SHIFT                   5
#define CAN_IFLAG1_BUF6I_MASK                    0x40u
#define CAN_IFLAG1_BUF6I_SHIFT                   6
#define CAN_IFLAG1_BUF7I_MASK                    0x80u
#define CAN_IFLAG1_BUF7I_SHIFT                   7
#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
/* CTRL2 Bit Fields */
#define CAN_CTRL2_EACEN_MASK                     0x10000u
#define CAN_CTRL2_EACEN_SHIFT                    16
#define CAN_CTRL2_RRS_MASK                       0x20000u
#define CAN_CTRL2_RRS_SHIFT                      17
#define CAN_CTRL2_MRP_MASK                       0x40000u
#define CAN_CTRL2_MRP_SHIFT                      18
#define CAN_CTRL2_TASD_MASK                      0xF80000u
#define CAN_CTRL2_TASD_SHIFT                     19
#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK                      0xF000000u
#define CAN_CTRL2_RFFN_SHIFT                     24
#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
#define CAN_CTRL2_WRMFRZ_SHIFT                   28
#define CAN_CTRL2_ECRWRE_MASK                    0x20000000u
#define CAN_CTRL2_ECRWRE_SHIFT                   29
/* ESR2 Bit Fields */
#define CAN_ESR2_IMB_MASK                        0x2000u
#define CAN_ESR2_IMB_SHIFT                       13
#define CAN_ESR2_VPS_MASK                        0x4000u
#define CAN_ESR2_VPS_SHIFT                       14
#define CAN_ESR2_LPTM_MASK                       0x7F0000u
#define CAN_ESR2_LPTM_SHIFT                      16
#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
/* CRCR Bit Fields */
#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
#define CAN_CRCR_TXCRC_SHIFT                     0
#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
#define CAN_CRCR_MBCRC_SHIFT                     16
#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
/* RXFGMASK Bit Fields */
#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
#define CAN_RXFGMASK_FGM_SHIFT                   0
#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
/* RXFIR Bit Fields */
#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
#define CAN_RXFIR_IDHIT_SHIFT                    0
#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT                  0
#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK                          0xF0000u
#define CAN_CS_DLC_SHIFT                         16
#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK                          0x100000u
#define CAN_CS_RTR_SHIFT                         20
#define CAN_CS_IDE_MASK                          0x200000u
#define CAN_CS_IDE_SHIFT                         21
#define CAN_CS_SRR_MASK                          0x400000u
#define CAN_CS_SRR_SHIFT                         22
#define CAN_CS_CODE_MASK                         0xF000000u
#define CAN_CS_CODE_SHIFT                        24
#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
/* ID Bit Fields */
#define CAN_ID_EXT_MASK                          0x3FFFFu
#define CAN_ID_EXT_SHIFT                         0
#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK                          0x1FFC0000u
#define CAN_ID_STD_SHIFT                         18
#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK                         0xE0000000u
#define CAN_ID_PRIO_SHIFT                        29
#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
/* WORD0 Bit Fields */
#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
/* WORD1 Bit Fields */
#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
/* RXIMR Bit Fields */
#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
#define CAN_RXIMR_MI_SHIFT                       0
#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
/* MECR Bit Fields */
#define CAN_MECR_NCEFAFRZ_MASK                   0x80u
#define CAN_MECR_NCEFAFRZ_SHIFT                  7
#define CAN_MECR_ECCDIS_MASK                     0x100u
#define CAN_MECR_ECCDIS_SHIFT                    8
#define CAN_MECR_RERRDIS_MASK                    0x200u
#define CAN_MECR_RERRDIS_SHIFT                   9
#define CAN_MECR_EXTERRIE_MASK                   0x2000u
#define CAN_MECR_EXTERRIE_SHIFT                  13
#define CAN_MECR_FAERRIE_MASK                    0x4000u
#define CAN_MECR_FAERRIE_SHIFT                   14
#define CAN_MECR_HAERRIE_MASK                    0x8000u
#define CAN_MECR_HAERRIE_SHIFT                   15
#define CAN_MECR_CEI_MSK_MASK                    0x10000u
#define CAN_MECR_CEI_MSK_SHIFT                   16
#define CAN_MECR_FANCEI_MSK_MASK                 0x40000u
#define CAN_MECR_FANCEI_MSK_SHIFT                18
#define CAN_MECR_HANCEI_MSK_MASK                 0x80000u
#define CAN_MECR_HANCEI_MSK_SHIFT                19
#define CAN_MECR_ECRWRDIS_MASK                   0x80000000u
#define CAN_MECR_ECRWRDIS_SHIFT                  31
/* ERRIAR Bit Fields */
#define CAN_ERRIAR_INJADDR_MASK                  0x3FFFu
#define CAN_ERRIAR_INJADDR_SHIFT                 0
#define CAN_ERRIAR_INJADDR(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_ERRIAR_INJADDR_SHIFT))&CAN_ERRIAR_INJADDR_MASK)
/* ERRIDPR Bit Fields */
#define CAN_ERRIDPR_DFLIP_MASK                   0xFFFFFFFFu
#define CAN_ERRIDPR_DFLIP_SHIFT                  0
#define CAN_ERRIDPR_DFLIP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_ERRIDPR_DFLIP_SHIFT))&CAN_ERRIDPR_DFLIP_MASK)
/* ERRIPPR Bit Fields */
#define CAN_ERRIPPR_PFLIP0_MASK                  0x1Fu
#define CAN_ERRIPPR_PFLIP0_SHIFT                 0
#define CAN_ERRIPPR_PFLIP0(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_ERRIPPR_PFLIP0_SHIFT))&CAN_ERRIPPR_PFLIP0_MASK)
#define CAN_ERRIPPR_PFLIP1_MASK                  0x1F00u
#define CAN_ERRIPPR_PFLIP1_SHIFT                 8
#define CAN_ERRIPPR_PFLIP1(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_ERRIPPR_PFLIP1_SHIFT))&CAN_ERRIPPR_PFLIP1_MASK)
#define CAN_ERRIPPR_PFLIP2_MASK                  0x1F0000u
#define CAN_ERRIPPR_PFLIP2_SHIFT                 16
#define CAN_ERRIPPR_PFLIP2(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_ERRIPPR_PFLIP2_SHIFT))&CAN_ERRIPPR_PFLIP2_MASK)
#define CAN_ERRIPPR_PFLIP3_MASK                  0x1F000000u
#define CAN_ERRIPPR_PFLIP3_SHIFT                 24
#define CAN_ERRIPPR_PFLIP3(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_ERRIPPR_PFLIP3_SHIFT))&CAN_ERRIPPR_PFLIP3_MASK)
/* RERRAR Bit Fields */
#define CAN_RERRAR_ERRADDR_MASK                  0x3FFFu
#define CAN_RERRAR_ERRADDR_SHIFT                 0
#define CAN_RERRAR_ERRADDR(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RERRAR_ERRADDR_SHIFT))&CAN_RERRAR_ERRADDR_MASK)
#define CAN_RERRAR_SAID_MASK                     0x70000u
#define CAN_RERRAR_SAID_SHIFT                    16
#define CAN_RERRAR_SAID(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RERRAR_SAID_SHIFT))&CAN_RERRAR_SAID_MASK)
#define CAN_RERRAR_NCE_MASK                      0x1000000u
#define CAN_RERRAR_NCE_SHIFT                     24
/* RERRDR Bit Fields */
#define CAN_RERRDR_RDATA_MASK                    0xFFFFFFFFu
#define CAN_RERRDR_RDATA_SHIFT                   0
#define CAN_RERRDR_RDATA(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RERRDR_RDATA_SHIFT))&CAN_RERRDR_RDATA_MASK)
/* RERRSYNR Bit Fields */
#define CAN_RERRSYNR_SYND0_MASK                  0x1Fu
#define CAN_RERRSYNR_SYND0_SHIFT                 0
#define CAN_RERRSYNR_SYND0(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RERRSYNR_SYND0_SHIFT))&CAN_RERRSYNR_SYND0_MASK)
#define CAN_RERRSYNR_BE0_MASK                    0x80u
#define CAN_RERRSYNR_BE0_SHIFT                   7
#define CAN_RERRSYNR_SYND1_MASK                  0x1F00u
#define CAN_RERRSYNR_SYND1_SHIFT                 8
#define CAN_RERRSYNR_SYND1(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RERRSYNR_SYND1_SHIFT))&CAN_RERRSYNR_SYND1_MASK)
#define CAN_RERRSYNR_BE1_MASK                    0x8000u
#define CAN_RERRSYNR_BE1_SHIFT                   15
#define CAN_RERRSYNR_SYND2_MASK                  0x1F0000u
#define CAN_RERRSYNR_SYND2_SHIFT                 16
#define CAN_RERRSYNR_SYND2(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RERRSYNR_SYND2_SHIFT))&CAN_RERRSYNR_SYND2_MASK)
#define CAN_RERRSYNR_BE2_MASK                    0x800000u
#define CAN_RERRSYNR_BE2_SHIFT                   23
#define CAN_RERRSYNR_SYND3_MASK                  0x1F000000u
#define CAN_RERRSYNR_SYND3_SHIFT                 24
#define CAN_RERRSYNR_SYND3(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RERRSYNR_SYND3_SHIFT))&CAN_RERRSYNR_SYND3_MASK)
#define CAN_RERRSYNR_BE3_MASK                    0x80000000u
#define CAN_RERRSYNR_BE3_SHIFT                   31
/* ERRSR Bit Fields */
#define CAN_ERRSR_CEIOF_MASK                     0x1u
#define CAN_ERRSR_CEIOF_SHIFT                    0
#define CAN_ERRSR_FANCEIOF_MASK                  0x4u
#define CAN_ERRSR_FANCEIOF_SHIFT                 2
#define CAN_ERRSR_HANCEIOF_MASK                  0x8u
#define CAN_ERRSR_HANCEIOF_SHIFT                 3
#define CAN_ERRSR_CEIF_MASK                      0x10000u
#define CAN_ERRSR_CEIF_SHIFT                     16
#define CAN_ERRSR_FANCEIF_MASK                   0x40000u
#define CAN_ERRSR_FANCEIF_SHIFT                  18
#define CAN_ERRSR_HANCEIF_MASK                   0x80000u
#define CAN_ERRSR_HANCEIF_SHIFT                  19

/**
 * @}
 */ /* end of group CAN_Register_Masks */


/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base address */
#define CAN0_BASE                                (0x40020000u)
/** Peripheral CAN0 base pointer */
#define CAN0                                     ((CAN_Type *)CAN0_BASE)
/** Peripheral CAN1 base address */
#define CAN1_BASE                                (0x400D4000u)
/** Peripheral CAN1 base pointer */
#define CAN1                                     ((CAN_Type *)CAN1_BASE)
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASES                                { CAN0, CAN1 }

/**
 * @}
 */ /* end of group CAN_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
 * @{
 */

/** CCM - Register Layout Typedef */
typedef struct {
  __IO uint32_t CCR;                               /**< CCM Control Register, offset: 0x0 */
  __IO uint32_t CSR;                               /**< CCM Status Register, offset: 0x4 */
  __IO uint32_t CCSR;                              /**< CCM Clock Switcher Register, offset: 0x8 */
  __IO uint32_t CACRR;                             /**< CCM ARM Clock Root Register, offset: 0xC */
  __IO uint32_t CSCMR1;                            /**< CCM Serial Clock Multiplexer Register 1, offset: 0x10 */
  __IO uint32_t CSCDR1;                            /**< CCM Serial Clock Divider Register 1, offset: 0x14 */
  __IO uint32_t CSCDR2;                            /**< CCM Serial Clock Divider Register 2, offset: 0x18 */
  __IO uint32_t CSCDR3;                            /**< CCM Serial Clock Divider Register 3, offset: 0x1C */
  __IO uint32_t CSCMR2;                            /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
  __IO uint32_t CSCDR4;                            /**< CCM Serial Clock Divider Register 4, offset: 0x24 */
  __IO uint32_t CTOR;                              /**< CCM Testing Observability Register, offset: 0x28 */
  __IO uint32_t CLPCR;                             /**< CCM Low Power Control Register, offset: 0x2C */
  __IO uint32_t CISR;                              /**< CCM Interrupt Status Register, offset: 0x30 */
  __IO uint32_t CIMR;                              /**< CCM Interrupt Mask Register, offset: 0x34 */
  __IO uint32_t CCOSR;                             /**< CCM Clock Output Source Register, offset: 0x38 */
       uint8_t RESERVED_0[4];
  __IO uint32_t CCGR0;                             /**< CCM Clock Gating Register, offset: 0x40 */
  __IO uint32_t CCGR1;                             /**< CCM Clock Gating Register, offset: 0x44 */
  __IO uint32_t CCGR2;                             /**< CCM Clock Gating Register, offset: 0x48 */
  __IO uint32_t CCGR3;                             /**< CCM Clock Gating Register, offset: 0x4C */
  __IO uint32_t CCGR4;                             /**< CCM Clock Gating Register, offset: 0x50 */
  __IO uint32_t CCGR5;                             /**< CCM Clock Gating Register, offset: 0x54 */
  __IO uint32_t CCGR6;                             /**< CCM Clock Gating Register, offset: 0x58 */
  __IO uint32_t CCGR7;                             /**< CCM Clock Gating Register, offset: 0x5C */
  __IO uint32_t CCGR8;                             /**< CCM Clock Gating Register, offset: 0x60 */
  __IO uint32_t CCGR9;                             /**< CCM Clock Gating Register, offset: 0x64 */
  __IO uint32_t CCGR10;                            /**< CCM Clock Gating Register, offset: 0x68 */
  __IO uint32_t CCGR11;                            /**< CCM Clock Gating Register, offset: 0x6C */
  __IO uint32_t CMEOR0;                            /**< CCM Module Enable Override Register, offset: 0x70 */
  __IO uint32_t CMEOR1;                            /**< CCM Module Enable Override Register, offset: 0x74 */
  __IO uint32_t CMEOR2;                            /**< CCM Module Enable Override Register, offset: 0x78 */
  __IO uint32_t CMEOR3;                            /**< CCM Module Enable Override Register, offset: 0x7C */
  __IO uint32_t CMEOR4;                            /**< CCM Module Enable Override Register, offset: 0x80 */
  __IO uint32_t CMEOR5;                            /**< CCM Module Enable Override Register, offset: 0x84 */
  __I  uint32_t CPPDSR;                            /**< CCM PLL PFD Disable Status Register, offset: 0x88 */
  __IO uint32_t CCOWR;                             /**< CCM CORE Wakeup Register, offset: 0x8C */
  __IO uint32_t CCPGR0;                            /**< CCM Platform Clock Gating Register, offset: 0x90 */
  __IO uint32_t CCPGR1;                            /**< CCM Platform Clock Gating Register, offset: 0x94 */
  __IO uint32_t CCPGR2;                            /**< CCM Platform Clock Gating Register, offset: 0x98 */
  __IO uint32_t CCPGR3;                            /**< CCM Platform Clock Gating Register, offset: 0x9C */
} CCM_Type;

/* ----------------------------------------------------------------------------
   -- CCM Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CCM_Register_Masks CCM Register Masks
 * @{
 */

/* CCR Bit Fields */
#define CCM_CCR_OSCNT_MASK                       0xFFu
#define CCM_CCR_OSCNT_SHIFT                      0
#define CCM_CCR_OSCNT(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCR_OSCNT_SHIFT))&CCM_CCR_OSCNT_MASK)
#define CCM_CCR_FXOSC_EN_MASK                    0x1000u
#define CCM_CCR_FXOSC_EN_SHIFT                   12
#define CCM_CCR_FIRC_EN_MASK                     0x10000u
#define CCM_CCR_FIRC_EN_SHIFT                    16
/* CSR Bit Fields */
#define CCM_CSR_FXOSC_RDY_MASK                   0x20u
#define CCM_CSR_FXOSC_RDY_SHIFT                  5
/* CCSR Bit Fields */
#define CCM_CCSR_SYS_CLK_SEL_MASK                0x7u
#define CCM_CCSR_SYS_CLK_SEL_SHIFT               0
#define CCM_CCSR_SYS_CLK_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CCSR_SYS_CLK_SEL_SHIFT))&CCM_CCSR_SYS_CLK_SEL_MASK)
#define CCM_CCSR_SLOW_CLK_SEL_MASK               0x10u
#define CCM_CCSR_SLOW_CLK_SEL_SHIFT              4
#define CCM_CCSR_FAST_CLK_SEL_MASK               0x20u
#define CCM_CCSR_FAST_CLK_SEL_SHIFT              5
#define CCM_CCSR_DDRC_CLK_SEL_MASK               0x40u
#define CCM_CCSR_DDRC_CLK_SEL_SHIFT              6
#define CCM_CCSR_PLL1_PFD1_EN_MASK               0x100u
#define CCM_CCSR_PLL1_PFD1_EN_SHIFT              8
#define CCM_CCSR_PLL1_PFD2_EN_MASK               0x200u
#define CCM_CCSR_PLL1_PFD2_EN_SHIFT              9
#define CCM_CCSR_PLL1_PFD3_EN_MASK               0x400u
#define CCM_CCSR_PLL1_PFD3_EN_SHIFT              10
#define CCM_CCSR_PLL1_PFD4_EN_MASK               0x800u
#define CCM_CCSR_PLL1_PFD4_EN_SHIFT              11
#define CCM_CCSR_PLL2_PFD1_EN_MASK               0x1000u
#define CCM_CCSR_PLL2_PFD1_EN_SHIFT              12
#define CCM_CCSR_PLL2_PFD2_EN_MASK               0x2000u
#define CCM_CCSR_PLL2_PFD2_EN_SHIFT              13
#define CCM_CCSR_PLL2_PFD3_EN_MASK               0x4000u
#define CCM_CCSR_PLL2_PFD3_EN_SHIFT              14
#define CCM_CCSR_PLL2_PFD4_EN_MASK               0x8000u
#define CCM_CCSR_PLL2_PFD4_EN_SHIFT              15
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK           0x70000u
#define CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT          16
#define CCM_CCSR_PLL1_PFD_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT))&CCM_CCSR_PLL1_PFD_CLK_SEL_MASK)
#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK           0x380000u
#define CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT          19
#define CCM_CCSR_PLL2_PFD_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT))&CCM_CCSR_PLL2_PFD_CLK_SEL_MASK)
#define CCM_CCSR_DAP_EN_MASK                     0x1000000u
#define CCM_CCSR_DAP_EN_SHIFT                    24
#define CCM_CCSR_PLL3_PFD1_EN_MASK               0x10000000u
#define CCM_CCSR_PLL3_PFD1_EN_SHIFT              28
#define CCM_CCSR_PLL3_PFD2_EN_MASK               0x20000000u
#define CCM_CCSR_PLL3_PFD2_EN_SHIFT              29
#define CCM_CCSR_PLL3_PFD3_EN_MASK               0x40000000u
#define CCM_CCSR_PLL3_PFD3_EN_SHIFT              30
#define CCM_CCSR_PLL3_PFD4_EN_MASK               0x80000000u
#define CCM_CCSR_PLL3_PFD4_EN_SHIFT              31
/* CACRR Bit Fields */
#define CCM_CACRR_ARM_CLK_DIV_MASK               0x7u
#define CCM_CACRR_ARM_CLK_DIV_SHIFT              0
#define CCM_CACRR_ARM_CLK_DIV(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_ARM_CLK_DIV_SHIFT))&CCM_CACRR_ARM_CLK_DIV_MASK)
#define CCM_CACRR_BUS_CLK_DIV_MASK               0x38u
#define CCM_CACRR_BUS_CLK_DIV_SHIFT              3
#define CCM_CACRR_BUS_CLK_DIV(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_BUS_CLK_DIV_SHIFT))&CCM_CACRR_BUS_CLK_DIV_MASK)
#define CCM_CACRR_PLL4_CLK_DIV_MASK              0x1C0u
#define CCM_CACRR_PLL4_CLK_DIV_SHIFT             6
#define CCM_CACRR_PLL4_CLK_DIV(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_PLL4_CLK_DIV_SHIFT))&CCM_CACRR_PLL4_CLK_DIV_MASK)
#define CCM_CACRR_IPG_CLK_DIV_MASK               0x1800u
#define CCM_CACRR_IPG_CLK_DIV_SHIFT              11
#define CCM_CACRR_IPG_CLK_DIV(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_IPG_CLK_DIV_SHIFT))&CCM_CACRR_IPG_CLK_DIV_MASK)
#define CCM_CACRR_PLL1_PFD_CLK_DIV_MASK          0x30000u
#define CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT         16
#define CCM_CACRR_PLL1_PFD_CLK_DIV(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT))&CCM_CACRR_PLL1_PFD_CLK_DIV_MASK)
#define CCM_CACRR_PLL3_CLK_DIV_MASK              0x100000u
#define CCM_CACRR_PLL3_CLK_DIV_SHIFT             20
#define CCM_CACRR_PLL6_CLK_DIV_MASK              0x200000u
#define CCM_CACRR_PLL6_CLK_DIV_SHIFT             21
#define CCM_CACRR_FLEX_CLK_DIV_MASK              0x1C00000u
#define CCM_CACRR_FLEX_CLK_DIV_SHIFT             22
#define CCM_CACRR_FLEX_CLK_DIV(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_FLEX_CLK_DIV_SHIFT))&CCM_CACRR_FLEX_CLK_DIV_MASK)
/* CSCMR1 Bit Fields */
#define CCM_CSCMR1_SAI0_CLK_SEL_MASK             0x3u
#define CCM_CSCMR1_SAI0_CLK_SEL_SHIFT            0
#define CCM_CSCMR1_SAI0_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_SAI0_CLK_SEL_SHIFT))&CCM_CSCMR1_SAI0_CLK_SEL_MASK)
#define CCM_CSCMR1_SAI1_CLK_SEL_MASK             0xCu
#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT            2
#define CCM_CSCMR1_SAI1_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_SAI1_CLK_SEL_SHIFT))&CCM_CSCMR1_SAI1_CLK_SEL_MASK)
#define CCM_CSCMR1_SAI2_CLK_SEL_MASK             0x30u
#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT            4
#define CCM_CSCMR1_SAI2_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_SAI2_CLK_SEL_SHIFT))&CCM_CSCMR1_SAI2_CLK_SEL_MASK)
#define CCM_CSCMR1_SAI3_CLK_SEL_MASK             0xC0u
#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT            6
#define CCM_CSCMR1_SAI3_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_SAI3_CLK_SEL_SHIFT))&CCM_CSCMR1_SAI3_CLK_SEL_MASK)
#define CCM_CSCMR1_VADC_CLK_SEL_MASK             0x300u
#define CCM_CSCMR1_VADC_CLK_SEL_SHIFT            8
#define CCM_CSCMR1_VADC_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_VADC_CLK_SEL_SHIFT))&CCM_CSCMR1_VADC_CLK_SEL_MASK)
#define CCM_CSCMR1_SPDIF_CLK_SEL_MASK            0xC00u
#define CCM_CSCMR1_SPDIF_CLK_SEL_SHIFT           10
#define CCM_CSCMR1_SPDIF_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_SPDIF_CLK_SEL_SHIFT))&CCM_CSCMR1_SPDIF_CLK_SEL_MASK)
#define CCM_CSCMR1_NFC_CLK_SEL_MASK              0x3000u
#define CCM_CSCMR1_NFC_CLK_SEL_SHIFT             12
#define CCM_CSCMR1_NFC_CLK_SEL(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_NFC_CLK_SEL_SHIFT))&CCM_CSCMR1_NFC_CLK_SEL_MASK)
#define CCM_CSCMR1_GPU_CLK_SEL_MASK              0x4000u
#define CCM_CSCMR1_GPU_CLK_SEL_SHIFT             14
#define CCM_CSCMR1_ESDHC0_CLK_SEL_MASK           0x30000u
#define CCM_CSCMR1_ESDHC0_CLK_SEL_SHIFT          16
#define CCM_CSCMR1_ESDHC0_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ESDHC0_CLK_SEL_SHIFT))&CCM_CSCMR1_ESDHC0_CLK_SEL_MASK)
#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK           0xC0000u
#define CCM_CSCMR1_ESDHC1_CLK_SEL_SHIFT          18
#define CCM_CSCMR1_ESDHC1_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ESDHC1_CLK_SEL_SHIFT))&CCM_CSCMR1_ESDHC1_CLK_SEL_MASK)
#define CCM_CSCMR1_ESAI_CLK_SEL_MASK             0x300000u
#define CCM_CSCMR1_ESAI_CLK_SEL_SHIFT            20
#define CCM_CSCMR1_ESAI_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ESAI_CLK_SEL_SHIFT))&CCM_CSCMR1_ESAI_CLK_SEL_MASK)
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK            0xC00000u
#define CCM_CSCMR1_QSPI0_CLK_SEL_SHIFT           22
#define CCM_CSCMR1_QSPI0_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_QSPI0_CLK_SEL_SHIFT))&CCM_CSCMR1_QSPI0_CLK_SEL_MASK)
#define CCM_CSCMR1_QSPI1_CLK_SEL_MASK            0x3000000u
#define CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT           24
#define CCM_CSCMR1_QSPI1_CLK_SEL(x)              (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT))&CCM_CSCMR1_QSPI1_CLK_SEL_MASK)
#define CCM_CSCMR1_DCU0_CLK_SEL_MASK             0x10000000u
#define CCM_CSCMR1_DCU0_CLK_SEL_SHIFT            28
#define CCM_CSCMR1_DCU1_CLK_SEL_MASK             0x20000000u
#define CCM_CSCMR1_DCU1_CLK_SEL_SHIFT            29
/* CSCDR1 Bit Fields */
#define CCM_CSCDR1_SAI0_DIV_MASK                 0xFu
#define CCM_CSCDR1_SAI0_DIV_SHIFT                0
#define CCM_CSCDR1_SAI0_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_SAI0_DIV_SHIFT))&CCM_CSCDR1_SAI0_DIV_MASK)
#define CCM_CSCDR1_SAI1_DIV_MASK                 0xF0u
#define CCM_CSCDR1_SAI1_DIV_SHIFT                4
#define CCM_CSCDR1_SAI1_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_SAI1_DIV_SHIFT))&CCM_CSCDR1_SAI1_DIV_MASK)
#define CCM_CSCDR1_SAI2_DIV_MASK                 0xF00u
#define CCM_CSCDR1_SAI2_DIV_SHIFT                8
#define CCM_CSCDR1_SAI2_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_SAI2_DIV_SHIFT))&CCM_CSCDR1_SAI2_DIV_MASK)
#define CCM_CSCDR1_SAI3_DIV_MASK                 0xF000u
#define CCM_CSCDR1_SAI3_DIV_SHIFT                12
#define CCM_CSCDR1_SAI3_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_SAI3_DIV_SHIFT))&CCM_CSCDR1_SAI3_DIV_MASK)
#define CCM_CSCDR1_SAI0_EN_MASK                  0x10000u
#define CCM_CSCDR1_SAI0_EN_SHIFT                 16
#define CCM_CSCDR1_SAI1_EN_MASK                  0x20000u
#define CCM_CSCDR1_SAI1_EN_SHIFT                 17
#define CCM_CSCDR1_SAI2_EN_MASK                  0x40000u
#define CCM_CSCDR1_SAI2_EN_SHIFT                 18
#define CCM_CSCDR1_SAI3_EN_MASK                  0x80000u
#define CCM_CSCDR1_SAI3_EN_SHIFT                 19
#define CCM_CSCDR1_VADC_DIV_MASK                 0x300000u
#define CCM_CSCDR1_VADC_DIV_SHIFT                20
#define CCM_CSCDR1_VADC_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_VADC_DIV_SHIFT))&CCM_CSCDR1_VADC_DIV_MASK)
#define CCM_CSCDR1_VADC_EN_MASK                  0x400000u
#define CCM_CSCDR1_VADC_EN_SHIFT                 22
#define CCM_CSCDR1_ENET_TS_EN_MASK               0x800000u
#define CCM_CSCDR1_ENET_TS_EN_SHIFT              23
#define CCM_CSCDR1_RMII_CLK_EN_MASK              0x1000000u
#define CCM_CSCDR1_RMII_CLK_EN_SHIFT             24
#define CCM_CSCDR1_FTM0_CLK_EN_MASK              0x2000000u
#define CCM_CSCDR1_FTM0_CLK_EN_SHIFT             25
#define CCM_CSCDR1_FTM1_CLK_EN_MASK              0x4000000u
#define CCM_CSCDR1_FTM1_CLK_EN_SHIFT             26
#define CCM_CSCDR1_FTM2_CLK_EN_MASK              0x8000000u
#define CCM_CSCDR1_FTM2_CLK_EN_SHIFT             27
#define CCM_CSCDR1_FTM3_CLK_EN_MASK              0x10000000u
#define CCM_CSCDR1_FTM3_CLK_EN_SHIFT             28
/* CSCDR2 Bit Fields */
#define CCM_CSCDR2_SPDIF_DIV_MASK                0xFu
#define CCM_CSCDR2_SPDIF_DIV_SHIFT               0
#define CCM_CSCDR2_SPDIF_DIV(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_SPDIF_DIV_SHIFT))&CCM_CSCDR2_SPDIF_DIV_MASK)
#define CCM_CSCDR2_NFC_FRAC_DIV_MASK             0xF0u
#define CCM_CSCDR2_NFC_FRAC_DIV_SHIFT            4
#define CCM_CSCDR2_NFC_FRAC_DIV(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_NFC_FRAC_DIV_SHIFT))&CCM_CSCDR2_NFC_FRAC_DIV_MASK)
#define CCM_CSCDR2_SPDIF_EN_MASK                 0x100u
#define CCM_CSCDR2_SPDIF_EN_SHIFT                8
#define CCM_CSCDR2_NFC_EN_MASK                   0x200u
#define CCM_CSCDR2_NFC_EN_SHIFT                  9
#define CCM_CSCDR2_GPU_EN_MASK                   0x400u
#define CCM_CSCDR2_GPU_EN_SHIFT                  10
#define CCM_CSCDR2_CAN0_EN_MASK                  0x800u
#define CCM_CSCDR2_CAN0_EN_SHIFT                 11
#define CCM_CSCDR2_CAN1_EN_MASK                  0x1000u
#define CCM_CSCDR2_CAN1_EN_SHIFT                 12
#define CCM_CSCDR2_NFC_FRAC_DIV_EN_MASK          0x2000u
#define CCM_CSCDR2_NFC_FRAC_DIV_EN_SHIFT         13
#define CCM_CSCDR2_NFC_CLK_INV_MASK              0x4000u
#define CCM_CSCDR2_NFC_CLK_INV_SHIFT             14
#define CCM_CSCDR2_ESDHC0_DIV_MASK               0xF0000u
#define CCM_CSCDR2_ESDHC0_DIV_SHIFT              16
#define CCM_CSCDR2_ESDHC0_DIV(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_ESDHC0_DIV_SHIFT))&CCM_CSCDR2_ESDHC0_DIV_MASK)
#define CCM_CSCDR2_ESDHC1_DIV_MASK               0xF00000u
#define CCM_CSCDR2_ESDHC1_DIV_SHIFT              20
#define CCM_CSCDR2_ESDHC1_DIV(x)                 (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_ESDHC1_DIV_SHIFT))&CCM_CSCDR2_ESDHC1_DIV_MASK)
#define CCM_CSCDR2_ESAI_DIV_MASK                 0xF000000u
#define CCM_CSCDR2_ESAI_DIV_SHIFT                24
#define CCM_CSCDR2_ESAI_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_ESAI_DIV_SHIFT))&CCM_CSCDR2_ESAI_DIV_MASK)
#define CCM_CSCDR2_ESDHC0_EN_MASK                0x10000000u
#define CCM_CSCDR2_ESDHC0_EN_SHIFT               28
#define CCM_CSCDR2_ESDHC1_EN_MASK                0x20000000u
#define CCM_CSCDR2_ESDHC1_EN_SHIFT               29
#define CCM_CSCDR2_ESAI_EN_MASK                  0x40000000u
#define CCM_CSCDR2_ESAI_EN_SHIFT                 30
/* CSCDR3 Bit Fields */
#define CCM_CSCDR3_QSPI0_X4_DIV_MASK             0x3u
#define CCM_CSCDR3_QSPI0_X4_DIV_SHIFT            0
#define CCM_CSCDR3_QSPI0_X4_DIV(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_QSPI0_X4_DIV_SHIFT))&CCM_CSCDR3_QSPI0_X4_DIV_MASK)
#define CCM_CSCDR3_QSPI0_X2_DIV_MASK             0x4u
#define CCM_CSCDR3_QSPI0_X2_DIV_SHIFT            2
#define CCM_CSCDR3_QSPI0_DIV_MASK                0x8u
#define CCM_CSCDR3_QSPI0_DIV_SHIFT               3
#define CCM_CSCDR3_QSPI0_EN_MASK                 0x10u
#define CCM_CSCDR3_QSPI0_EN_SHIFT                4
#define CCM_CSCDR3_QSPI1_X4_DIV_MASK             0x300u
#define CCM_CSCDR3_QSPI1_X4_DIV_SHIFT            8
#define CCM_CSCDR3_QSPI1_X4_DIV(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_QSPI1_X4_DIV_SHIFT))&CCM_CSCDR3_QSPI1_X4_DIV_MASK)
#define CCM_CSCDR3_QSPI1_X2_DIV_MASK             0x400u
#define CCM_CSCDR3_QSPI1_X2_DIV_SHIFT            10
#define CCM_CSCDR3_QSPI1_DIV_MASK                0x800u
#define CCM_CSCDR3_QSPI1_DIV_SHIFT               11
#define CCM_CSCDR3_QSPI1_EN_MASK                 0x1000u
#define CCM_CSCDR3_QSPI1_EN_SHIFT                12
#define CCM_CSCDR3_NFC_PRE_DIV_MASK              0xE000u
#define CCM_CSCDR3_NFC_PRE_DIV_SHIFT             13
#define CCM_CSCDR3_NFC_PRE_DIV(x)                (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_NFC_PRE_DIV_SHIFT))&CCM_CSCDR3_NFC_PRE_DIV_MASK)
#define CCM_CSCDR3_DCU0_DIV_MASK                 0x70000u
#define CCM_CSCDR3_DCU0_DIV_SHIFT                16
#define CCM_CSCDR3_DCU0_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_DCU0_DIV_SHIFT))&CCM_CSCDR3_DCU0_DIV_MASK)
#define CCM_CSCDR3_DCU0_EN_MASK                  0x80000u
#define CCM_CSCDR3_DCU0_EN_SHIFT                 19
#define CCM_CSCDR3_DCU1_DIV_MASK                 0x700000u
#define CCM_CSCDR3_DCU1_DIV_SHIFT                20
#define CCM_CSCDR3_DCU1_DIV(x)                   (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_DCU1_DIV_SHIFT))&CCM_CSCDR3_DCU1_DIV_MASK)
#define CCM_CSCDR3_DCU1_EN_MASK                  0x800000u
#define CCM_CSCDR3_DCU1_EN_SHIFT                 23
#define CCM_CSCDR3_TRACE_DIV_MASK                0x3000000u
#define CCM_CSCDR3_TRACE_DIV_SHIFT               24
#define CCM_CSCDR3_TRACE_DIV(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_TRACE_DIV_SHIFT))&CCM_CSCDR3_TRACE_DIV_MASK)
#define CCM_CSCDR3_TRACE_EN_MASK                 0x4000000u
#define CCM_CSCDR3_TRACE_EN_SHIFT                26
#define CCM_CSCDR3_SWO_DIV_MASK                  0x8000000u
#define CCM_CSCDR3_SWO_DIV_SHIFT                 27
#define CCM_CSCDR3_SWO_EN_MASK                   0x10000000u
#define CCM_CSCDR3_SWO_EN_SHIFT                  28
/* CSCMR2 Bit Fields */
#define CCM_CSCMR2_ENET_TS_CLK_SEL_MASK          0x7u
#define CCM_CSCMR2_ENET_TS_CLK_SEL_SHIFT         0
#define CCM_CSCMR2_ENET_TS_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_ENET_TS_CLK_SEL_SHIFT))&CCM_CSCMR2_ENET_TS_CLK_SEL_MASK)
#define CCM_CSCMR2_RMII_CLK_SEL_MASK             0x30u
#define CCM_CSCMR2_RMII_CLK_SEL_SHIFT            4
#define CCM_CSCMR2_RMII_CLK_SEL(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_RMII_CLK_SEL_SHIFT))&CCM_CSCMR2_RMII_CLK_SEL_MASK)
#define CCM_CSCMR2_FTM0_EXT_CLK_SEL_MASK         0xC0u
#define CCM_CSCMR2_FTM0_EXT_CLK_SEL_SHIFT        6
#define CCM_CSCMR2_FTM0_EXT_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_FTM0_EXT_CLK_SEL_SHIFT))&CCM_CSCMR2_FTM0_EXT_CLK_SEL_MASK)
#define CCM_CSCMR2_FTM1_EXT_CLK_SEL_MASK         0x300u
#define CCM_CSCMR2_FTM1_EXT_CLK_SEL_SHIFT        8
#define CCM_CSCMR2_FTM1_EXT_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_FTM1_EXT_CLK_SEL_SHIFT))&CCM_CSCMR2_FTM1_EXT_CLK_SEL_MASK)
#define CCM_CSCMR2_FTM2_EXT_CLK_SEL_MASK         0xC00u
#define CCM_CSCMR2_FTM2_EXT_CLK_SEL_SHIFT        10
#define CCM_CSCMR2_FTM2_EXT_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_FTM2_EXT_CLK_SEL_SHIFT))&CCM_CSCMR2_FTM2_EXT_CLK_SEL_MASK)
#define CCM_CSCMR2_FTM3_EXT_CLK_SEL_MASK         0x3000u
#define CCM_CSCMR2_FTM3_EXT_CLK_SEL_SHIFT        12
#define CCM_CSCMR2_FTM3_EXT_CLK_SEL(x)           (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_FTM3_EXT_CLK_SEL_SHIFT))&CCM_CSCMR2_FTM3_EXT_CLK_SEL_MASK)
#define CCM_CSCMR2_FTM0_FIX_CLK_SEL_MASK         0x4000u
#define CCM_CSCMR2_FTM0_FIX_CLK_SEL_SHIFT        14
#define CCM_CSCMR2_FTM1_FIX_CLK_SEL_MASK         0x8000u
#define CCM_CSCMR2_FTM1_FIX_CLK_SEL_SHIFT        15
#define CCM_CSCMR2_FTM2_FIX_CLK_SEL_MASK         0x10000u
#define CCM_CSCMR2_FTM2_FIX_CLK_SEL_SHIFT        16
#define CCM_CSCMR2_FTM3_FIX_CLK_SEL_MASK         0x20000u
#define CCM_CSCMR2_FTM3_FIX_CLK_SEL_SHIFT        17
#define CCM_CSCMR2_TRACE_CLK_SEL_MASK            0x40000u
#define CCM_CSCMR2_TRACE_CLK_SEL_SHIFT           18
#define CCM_CSCMR2_SWO_CLK_SEL_MASK              0x80000u
#define CCM_CSCMR2_SWO_CLK_SEL_SHIFT             19
/* CSCDR4 Bit Fields */
#define CCM_CSCDR4_SNVS_CLK_DIV_MASK             0x7Fu
#define CCM_CSCDR4_SNVS_CLK_DIV_SHIFT            0
#define CCM_CSCDR4_SNVS_CLK_DIV(x)               (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR4_SNVS_CLK_DIV_SHIFT))&CCM_CSCDR4_SNVS_CLK_DIV_MASK)
/* CTOR Bit Fields */
#define CCM_CTOR_OBS_OUTPUT_0_SEL_MASK           0x1Fu
#define CCM_CTOR_OBS_OUTPUT_0_SEL_SHIFT          0
#define CCM_CTOR_OBS_OUTPUT_0_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CTOR_OBS_OUTPUT_0_SEL_SHIFT))&CCM_CTOR_OBS_OUTPUT_0_SEL_MASK)
#define CCM_CTOR_OBS_OUTPUT_1_SEL_MASK           0x3E0u
#define CCM_CTOR_OBS_OUTPUT_1_SEL_SHIFT          5
#define CCM_CTOR_OBS_OUTPUT_1_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CTOR_OBS_OUTPUT_1_SEL_SHIFT))&CCM_CTOR_OBS_OUTPUT_1_SEL_MASK)
#define CCM_CTOR_OBS_OUTPUT_2_SEL_MASK           0x7C00u
#define CCM_CTOR_OBS_OUTPUT_2_SEL_SHIFT          10
#define CCM_CTOR_OBS_OUTPUT_2_SEL(x)             (((uint32_t)(((uint32_t)(x))<<CCM_CTOR_OBS_OUTPUT_2_SEL_SHIFT))&CCM_CTOR_OBS_OUTPUT_2_SEL_MASK)
#define CCM_CTOR_OBS_EN_MASK                     0x8000u
#define CCM_CTOR_OBS_EN_SHIFT                    15
/* CLPCR Bit Fields */
#define CCM_CLPCR_ARM_CLK_LPM_MASK               0x20u
#define CCM_CLPCR_ARM_CLK_LPM_SHIFT              5
#define CCM_CLPCR_SBYOS_MASK                     0x40u
#define CCM_CLPCR_SBYOS_SHIFT                    6
#define CCM_CLPCR_DIS_REF_OSC_MASK               0x80u
#define CCM_CLPCR_DIS_REF_OSC_SHIFT              7
#define CCM_CLPCR_ANATOP_STOP_MODE_MASK          0x100u
#define CCM_CLPCR_ANATOP_STOP_MODE_SHIFT         8
#define CCM_CLPCR_FXOSC_PWRDWN_MASK              0x800u
#define CCM_CLPCR_FXOSC_PWRDWN_SHIFT             11
#define CCM_CLPCR_M_CORE0_WFI_MASK               0x400000u
#define CCM_CLPCR_M_CORE0_WFI_SHIFT              22
#define CCM_CLPCR_M_CORE1_WFI_MASK               0x800000u
#define CCM_CLPCR_M_CORE1_WFI_SHIFT              23
#define CCM_CLPCR_M_SCU_IDLE_MASK                0x1000000u
#define CCM_CLPCR_M_SCU_IDLE_SHIFT               24
#define CCM_CLPCR_M_L2CC_IDLE_MASK               0x2000000u
#define CCM_CLPCR_M_L2CC_IDLE_SHIFT              25
/* CISR Bit Fields */
#define CCM_CISR_LRF_PLL1_MASK                   0x1u
#define CCM_CISR_LRF_PLL1_SHIFT                  0
#define CCM_CISR_LRF_PLL2_MASK                   0x2u
#define CCM_CISR_LRF_PLL2_SHIFT                  1
#define CCM_CISR_LRF_PLL3_MASK                   0x4u
#define CCM_CISR_LRF_PLL3_SHIFT                  2
#define CCM_CISR_LRF_PLL4_MASK                   0x8u
#define CCM_CISR_LRF_PLL4_SHIFT                  3
#define CCM_CISR_FXOSC_RDY_MASK                  0x40u
#define CCM_CISR_FXOSC_RDY_SHIFT                 6
/* CIMR Bit Fields */
#define CCM_CIMR_M_LRF_PLL1_MASK                 0x1u
#define CCM_CIMR_M_LRF_PLL1_SHIFT                0
#define CCM_CIMR_M_LRF_PLL2_MASK                 0x2u
#define CCM_CIMR_M_LRF_PLL2_SHIFT                1
#define CCM_CIMR_M_LRF_PLL3_MASK                 0x4u
#define CCM_CIMR_M_LRF_PLL3_SHIFT                2
#define CCM_CIMR_M_LRF_PLL4_MASK                 0x8u
#define CCM_CIMR_M_LRF_PLL4_SHIFT                3
#define CCM_CIMR_M_FXOSC_READY_MASK              0x40u
#define CCM_CIMR_M_FXOSC_READY_SHIFT             6
/* CCOSR Bit Fields */
#define CCM_CCOSR_CKO1_SEL_MASK                  0x3Fu
#define CCM_CCOSR_CKO1_SEL_SHIFT                 0
#define CCM_CCOSR_CKO1_SEL(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CKO1_SEL_SHIFT))&CCM_CCOSR_CKO1_SEL_MASK)
#define CCM_CCOSR_CKO1_DIV_MASK                  0x3C0u
#define CCM_CCOSR_CKO1_DIV_SHIFT                 6
#define CCM_CCOSR_CKO1_DIV(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CKO1_DIV_SHIFT))&CCM_CCOSR_CKO1_DIV_MASK)
#define CCM_CCOSR_CKO1_EN_MASK                   0x400u
#define CCM_CCOSR_CKO1_EN_SHIFT                  10
#define CCM_CCOSR_CKO2_SEL_MASK                  0x3F0000u
#define CCM_CCOSR_CKO2_SEL_SHIFT                 16
#define CCM_CCOSR_CKO2_SEL(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CKO2_SEL_SHIFT))&CCM_CCOSR_CKO2_SEL_MASK)
#define CCM_CCOSR_CKO2_DIV_MASK                  0x3C00000u
#define CCM_CCOSR_CKO2_DIV_SHIFT                 22
#define CCM_CCOSR_CKO2_DIV(x)                    (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CKO2_DIV_SHIFT))&CCM_CCOSR_CKO2_DIV_MASK)
#define CCM_CCOSR_CKO2_EN_MASK                   0x4000000u
#define CCM_CCOSR_CKO2_EN_SHIFT                  26
/* CCGR0 Bit Fields */
#define CCM_CCGR0_CG0_MASK                       0x3u
#define CCM_CCGR0_CG0_SHIFT                      0
#define CCM_CCGR0_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG0_SHIFT))&CCM_CCGR0_CG0_MASK)
#define CCM_CCGR0_CG1_MASK                       0xCu
#define CCM_CCGR0_CG1_SHIFT                      2
#define CCM_CCGR0_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG1_SHIFT))&CCM_CCGR0_CG1_MASK)
#define CCM_CCGR0_CG2_MASK                       0x30u
#define CCM_CCGR0_CG2_SHIFT                      4
#define CCM_CCGR0_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG2_SHIFT))&CCM_CCGR0_CG2_MASK)
#define CCM_CCGR0_CG3_MASK                       0xC0u
#define CCM_CCGR0_CG3_SHIFT                      6
#define CCM_CCGR0_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG3_SHIFT))&CCM_CCGR0_CG3_MASK)
#define CCM_CCGR0_CG4_MASK                       0x300u
#define CCM_CCGR0_CG4_SHIFT                      8
#define CCM_CCGR0_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG4_SHIFT))&CCM_CCGR0_CG4_MASK)
#define CCM_CCGR0_CG5_MASK                       0xC00u
#define CCM_CCGR0_CG5_SHIFT                      10
#define CCM_CCGR0_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG5_SHIFT))&CCM_CCGR0_CG5_MASK)
#define CCM_CCGR0_CG6_MASK                       0x3000u
#define CCM_CCGR0_CG6_SHIFT                      12
#define CCM_CCGR0_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG6_SHIFT))&CCM_CCGR0_CG6_MASK)
#define CCM_CCGR0_CG7_MASK                       0xC000u
#define CCM_CCGR0_CG7_SHIFT                      14
#define CCM_CCGR0_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG7_SHIFT))&CCM_CCGR0_CG7_MASK)
#define CCM_CCGR0_CG8_MASK                       0x30000u
#define CCM_CCGR0_CG8_SHIFT                      16
#define CCM_CCGR0_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG8_SHIFT))&CCM_CCGR0_CG8_MASK)
#define CCM_CCGR0_CG9_MASK                       0xC0000u
#define CCM_CCGR0_CG9_SHIFT                      18
#define CCM_CCGR0_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG9_SHIFT))&CCM_CCGR0_CG9_MASK)
#define CCM_CCGR0_CG10_MASK                      0x300000u
#define CCM_CCGR0_CG10_SHIFT                     20
#define CCM_CCGR0_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG10_SHIFT))&CCM_CCGR0_CG10_MASK)
#define CCM_CCGR0_CG11_MASK                      0xC00000u
#define CCM_CCGR0_CG11_SHIFT                     22
#define CCM_CCGR0_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG11_SHIFT))&CCM_CCGR0_CG11_MASK)
#define CCM_CCGR0_CG12_MASK                      0x3000000u
#define CCM_CCGR0_CG12_SHIFT                     24
#define CCM_CCGR0_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG12_SHIFT))&CCM_CCGR0_CG12_MASK)
#define CCM_CCGR0_CG13_MASK                      0xC000000u
#define CCM_CCGR0_CG13_SHIFT                     26
#define CCM_CCGR0_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG13_SHIFT))&CCM_CCGR0_CG13_MASK)
#define CCM_CCGR0_CG14_MASK                      0x30000000u
#define CCM_CCGR0_CG14_SHIFT                     28
#define CCM_CCGR0_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG14_SHIFT))&CCM_CCGR0_CG14_MASK)
#define CCM_CCGR0_CG15_MASK                      0xC0000000u
#define CCM_CCGR0_CG15_SHIFT                     30
#define CCM_CCGR0_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG15_SHIFT))&CCM_CCGR0_CG15_MASK)
/* CCGR1 Bit Fields */
#define CCM_CCGR1_CG0_MASK                       0x3u
#define CCM_CCGR1_CG0_SHIFT                      0
#define CCM_CCGR1_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG0_SHIFT))&CCM_CCGR1_CG0_MASK)
#define CCM_CCGR1_CG1_MASK                       0xCu
#define CCM_CCGR1_CG1_SHIFT                      2
#define CCM_CCGR1_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG1_SHIFT))&CCM_CCGR1_CG1_MASK)
#define CCM_CCGR1_CG2_MASK                       0x30u
#define CCM_CCGR1_CG2_SHIFT                      4
#define CCM_CCGR1_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG2_SHIFT))&CCM_CCGR1_CG2_MASK)
#define CCM_CCGR1_CG3_MASK                       0xC0u
#define CCM_CCGR1_CG3_SHIFT                      6
#define CCM_CCGR1_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG3_SHIFT))&CCM_CCGR1_CG3_MASK)
#define CCM_CCGR1_CG4_MASK                       0x300u
#define CCM_CCGR1_CG4_SHIFT                      8
#define CCM_CCGR1_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG4_SHIFT))&CCM_CCGR1_CG4_MASK)
#define CCM_CCGR1_CG5_MASK                       0xC00u
#define CCM_CCGR1_CG5_SHIFT                      10
#define CCM_CCGR1_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG5_SHIFT))&CCM_CCGR1_CG5_MASK)
#define CCM_CCGR1_CG6_MASK                       0x3000u
#define CCM_CCGR1_CG6_SHIFT                      12
#define CCM_CCGR1_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG6_SHIFT))&CCM_CCGR1_CG6_MASK)
#define CCM_CCGR1_CG7_MASK                       0xC000u
#define CCM_CCGR1_CG7_SHIFT                      14
#define CCM_CCGR1_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG7_SHIFT))&CCM_CCGR1_CG7_MASK)
#define CCM_CCGR1_CG8_MASK                       0x30000u
#define CCM_CCGR1_CG8_SHIFT                      16
#define CCM_CCGR1_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG8_SHIFT))&CCM_CCGR1_CG8_MASK)
#define CCM_CCGR1_CG9_MASK                       0xC0000u
#define CCM_CCGR1_CG9_SHIFT                      18
#define CCM_CCGR1_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG9_SHIFT))&CCM_CCGR1_CG9_MASK)
#define CCM_CCGR1_CG10_MASK                      0x300000u
#define CCM_CCGR1_CG10_SHIFT                     20
#define CCM_CCGR1_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG10_SHIFT))&CCM_CCGR1_CG10_MASK)
#define CCM_CCGR1_CG11_MASK                      0xC00000u
#define CCM_CCGR1_CG11_SHIFT                     22
#define CCM_CCGR1_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG11_SHIFT))&CCM_CCGR1_CG11_MASK)
#define CCM_CCGR1_CG12_MASK                      0x3000000u
#define CCM_CCGR1_CG12_SHIFT                     24
#define CCM_CCGR1_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG12_SHIFT))&CCM_CCGR1_CG12_MASK)
#define CCM_CCGR1_CG13_MASK                      0xC000000u
#define CCM_CCGR1_CG13_SHIFT                     26
#define CCM_CCGR1_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG13_SHIFT))&CCM_CCGR1_CG13_MASK)
#define CCM_CCGR1_CG14_MASK                      0x30000000u
#define CCM_CCGR1_CG14_SHIFT                     28
#define CCM_CCGR1_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG14_SHIFT))&CCM_CCGR1_CG14_MASK)
#define CCM_CCGR1_CG15_MASK                      0xC0000000u
#define CCM_CCGR1_CG15_SHIFT                     30
#define CCM_CCGR1_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG15_SHIFT))&CCM_CCGR1_CG15_MASK)
/* CCGR2 Bit Fields */
#define CCM_CCGR2_CG0_MASK                       0x3u
#define CCM_CCGR2_CG0_SHIFT                      0
#define CCM_CCGR2_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG0_SHIFT))&CCM_CCGR2_CG0_MASK)
#define CCM_CCGR2_CG1_MASK                       0xCu
#define CCM_CCGR2_CG1_SHIFT                      2
#define CCM_CCGR2_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG1_SHIFT))&CCM_CCGR2_CG1_MASK)
#define CCM_CCGR2_CG2_MASK                       0x30u
#define CCM_CCGR2_CG2_SHIFT                      4
#define CCM_CCGR2_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG2_SHIFT))&CCM_CCGR2_CG2_MASK)
#define CCM_CCGR2_CG3_MASK                       0xC0u
#define CCM_CCGR2_CG3_SHIFT                      6
#define CCM_CCGR2_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG3_SHIFT))&CCM_CCGR2_CG3_MASK)
#define CCM_CCGR2_CG4_MASK                       0x300u
#define CCM_CCGR2_CG4_SHIFT                      8
#define CCM_CCGR2_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG4_SHIFT))&CCM_CCGR2_CG4_MASK)
#define CCM_CCGR2_CG5_MASK                       0xC00u
#define CCM_CCGR2_CG5_SHIFT                      10
#define CCM_CCGR2_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG5_SHIFT))&CCM_CCGR2_CG5_MASK)
#define CCM_CCGR2_CG6_MASK                       0x3000u
#define CCM_CCGR2_CG6_SHIFT                      12
#define CCM_CCGR2_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG6_SHIFT))&CCM_CCGR2_CG6_MASK)
#define CCM_CCGR2_CG7_MASK                       0xC000u
#define CCM_CCGR2_CG7_SHIFT                      14
#define CCM_CCGR2_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG7_SHIFT))&CCM_CCGR2_CG7_MASK)
#define CCM_CCGR2_CG8_MASK                       0x30000u
#define CCM_CCGR2_CG8_SHIFT                      16
#define CCM_CCGR2_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG8_SHIFT))&CCM_CCGR2_CG8_MASK)
#define CCM_CCGR2_CG9_MASK                       0xC0000u
#define CCM_CCGR2_CG9_SHIFT                      18
#define CCM_CCGR2_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG9_SHIFT))&CCM_CCGR2_CG9_MASK)
#define CCM_CCGR2_CG10_MASK                      0x300000u
#define CCM_CCGR2_CG10_SHIFT                     20
#define CCM_CCGR2_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG10_SHIFT))&CCM_CCGR2_CG10_MASK)
#define CCM_CCGR2_CG11_MASK                      0xC00000u
#define CCM_CCGR2_CG11_SHIFT                     22
#define CCM_CCGR2_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG11_SHIFT))&CCM_CCGR2_CG11_MASK)
#define CCM_CCGR2_CG12_MASK                      0x3000000u
#define CCM_CCGR2_CG12_SHIFT                     24
#define CCM_CCGR2_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG12_SHIFT))&CCM_CCGR2_CG12_MASK)
#define CCM_CCGR2_CG13_MASK                      0xC000000u
#define CCM_CCGR2_CG13_SHIFT                     26
#define CCM_CCGR2_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG13_SHIFT))&CCM_CCGR2_CG13_MASK)
#define CCM_CCGR2_CG14_MASK                      0x30000000u
#define CCM_CCGR2_CG14_SHIFT                     28
#define CCM_CCGR2_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG14_SHIFT))&CCM_CCGR2_CG14_MASK)
#define CCM_CCGR2_CG15_MASK                      0xC0000000u
#define CCM_CCGR2_CG15_SHIFT                     30
#define CCM_CCGR2_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG15_SHIFT))&CCM_CCGR2_CG15_MASK)
/* CCGR3 Bit Fields */
#define CCM_CCGR3_CG0_MASK                       0x3u
#define CCM_CCGR3_CG0_SHIFT                      0
#define CCM_CCGR3_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG0_SHIFT))&CCM_CCGR3_CG0_MASK)
#define CCM_CCGR3_CG1_MASK                       0xCu
#define CCM_CCGR3_CG1_SHIFT                      2
#define CCM_CCGR3_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG1_SHIFT))&CCM_CCGR3_CG1_MASK)
#define CCM_CCGR3_CG2_MASK                       0x30u
#define CCM_CCGR3_CG2_SHIFT                      4
#define CCM_CCGR3_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG2_SHIFT))&CCM_CCGR3_CG2_MASK)
#define CCM_CCGR3_CG3_MASK                       0xC0u
#define CCM_CCGR3_CG3_SHIFT                      6
#define CCM_CCGR3_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG3_SHIFT))&CCM_CCGR3_CG3_MASK)
#define CCM_CCGR3_CG4_MASK                       0x300u
#define CCM_CCGR3_CG4_SHIFT                      8
#define CCM_CCGR3_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG4_SHIFT))&CCM_CCGR3_CG4_MASK)
#define CCM_CCGR3_CG5_MASK                       0xC00u
#define CCM_CCGR3_CG5_SHIFT                      10
#define CCM_CCGR3_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG5_SHIFT))&CCM_CCGR3_CG5_MASK)
#define CCM_CCGR3_CG6_MASK                       0x3000u
#define CCM_CCGR3_CG6_SHIFT                      12
#define CCM_CCGR3_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG6_SHIFT))&CCM_CCGR3_CG6_MASK)
#define CCM_CCGR3_CG7_MASK                       0xC000u
#define CCM_CCGR3_CG7_SHIFT                      14
#define CCM_CCGR3_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG7_SHIFT))&CCM_CCGR3_CG7_MASK)
#define CCM_CCGR3_CG8_MASK                       0x30000u
#define CCM_CCGR3_CG8_SHIFT                      16
#define CCM_CCGR3_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG8_SHIFT))&CCM_CCGR3_CG8_MASK)
#define CCM_CCGR3_CG9_MASK                       0xC0000u
#define CCM_CCGR3_CG9_SHIFT                      18
#define CCM_CCGR3_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG9_SHIFT))&CCM_CCGR3_CG9_MASK)
#define CCM_CCGR3_CG10_MASK                      0x300000u
#define CCM_CCGR3_CG10_SHIFT                     20
#define CCM_CCGR3_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG10_SHIFT))&CCM_CCGR3_CG10_MASK)
#define CCM_CCGR3_CG11_MASK                      0xC00000u
#define CCM_CCGR3_CG11_SHIFT                     22
#define CCM_CCGR3_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG11_SHIFT))&CCM_CCGR3_CG11_MASK)
#define CCM_CCGR3_CG12_MASK                      0x3000000u
#define CCM_CCGR3_CG12_SHIFT                     24
#define CCM_CCGR3_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG12_SHIFT))&CCM_CCGR3_CG12_MASK)
#define CCM_CCGR3_CG13_MASK                      0xC000000u
#define CCM_CCGR3_CG13_SHIFT                     26
#define CCM_CCGR3_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG13_SHIFT))&CCM_CCGR3_CG13_MASK)
#define CCM_CCGR3_CG14_MASK                      0x30000000u
#define CCM_CCGR3_CG14_SHIFT                     28
#define CCM_CCGR3_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG14_SHIFT))&CCM_CCGR3_CG14_MASK)
#define CCM_CCGR3_CG15_MASK                      0xC0000000u
#define CCM_CCGR3_CG15_SHIFT                     30
#define CCM_CCGR3_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG15_SHIFT))&CCM_CCGR3_CG15_MASK)
/* CCGR4 Bit Fields */
#define CCM_CCGR4_CG0_MASK                       0x3u
#define CCM_CCGR4_CG0_SHIFT                      0
#define CCM_CCGR4_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG0_SHIFT))&CCM_CCGR4_CG0_MASK)
#define CCM_CCGR4_CG1_MASK                       0xCu
#define CCM_CCGR4_CG1_SHIFT                      2
#define CCM_CCGR4_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG1_SHIFT))&CCM_CCGR4_CG1_MASK)
#define CCM_CCGR4_CG2_MASK                       0x30u
#define CCM_CCGR4_CG2_SHIFT                      4
#define CCM_CCGR4_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG2_SHIFT))&CCM_CCGR4_CG2_MASK)
#define CCM_CCGR4_CG3_MASK                       0xC0u
#define CCM_CCGR4_CG3_SHIFT                      6
#define CCM_CCGR4_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG3_SHIFT))&CCM_CCGR4_CG3_MASK)
#define CCM_CCGR4_CG4_MASK                       0x300u
#define CCM_CCGR4_CG4_SHIFT                      8
#define CCM_CCGR4_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG4_SHIFT))&CCM_CCGR4_CG4_MASK)
#define CCM_CCGR4_CG5_MASK                       0xC00u
#define CCM_CCGR4_CG5_SHIFT                      10
#define CCM_CCGR4_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG5_SHIFT))&CCM_CCGR4_CG5_MASK)
#define CCM_CCGR4_CG6_MASK                       0x3000u
#define CCM_CCGR4_CG6_SHIFT                      12
#define CCM_CCGR4_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG6_SHIFT))&CCM_CCGR4_CG6_MASK)
#define CCM_CCGR4_CG7_MASK                       0xC000u
#define CCM_CCGR4_CG7_SHIFT                      14
#define CCM_CCGR4_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG7_SHIFT))&CCM_CCGR4_CG7_MASK)
#define CCM_CCGR4_CG8_MASK                       0x30000u
#define CCM_CCGR4_CG8_SHIFT                      16
#define CCM_CCGR4_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG8_SHIFT))&CCM_CCGR4_CG8_MASK)
#define CCM_CCGR4_CG9_MASK                       0xC0000u
#define CCM_CCGR4_CG9_SHIFT                      18
#define CCM_CCGR4_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG9_SHIFT))&CCM_CCGR4_CG9_MASK)
#define CCM_CCGR4_CG10_MASK                      0x300000u
#define CCM_CCGR4_CG10_SHIFT                     20
#define CCM_CCGR4_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG10_SHIFT))&CCM_CCGR4_CG10_MASK)
#define CCM_CCGR4_CG11_MASK                      0xC00000u
#define CCM_CCGR4_CG11_SHIFT                     22
#define CCM_CCGR4_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG11_SHIFT))&CCM_CCGR4_CG11_MASK)
#define CCM_CCGR4_CG12_MASK                      0x3000000u
#define CCM_CCGR4_CG12_SHIFT                     24
#define CCM_CCGR4_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG12_SHIFT))&CCM_CCGR4_CG12_MASK)
#define CCM_CCGR4_CG13_MASK                      0xC000000u
#define CCM_CCGR4_CG13_SHIFT                     26
#define CCM_CCGR4_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG13_SHIFT))&CCM_CCGR4_CG13_MASK)
#define CCM_CCGR4_CG14_MASK                      0x30000000u
#define CCM_CCGR4_CG14_SHIFT                     28
#define CCM_CCGR4_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG14_SHIFT))&CCM_CCGR4_CG14_MASK)
#define CCM_CCGR4_CG15_MASK                      0xC0000000u
#define CCM_CCGR4_CG15_SHIFT                     30
#define CCM_CCGR4_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG15_SHIFT))&CCM_CCGR4_CG15_MASK)
/* CCGR5 Bit Fields */
#define CCM_CCGR5_CG0_MASK                       0x3u
#define CCM_CCGR5_CG0_SHIFT                      0
#define CCM_CCGR5_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG0_SHIFT))&CCM_CCGR5_CG0_MASK)
#define CCM_CCGR5_CG1_MASK                       0xCu
#define CCM_CCGR5_CG1_SHIFT                      2
#define CCM_CCGR5_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG1_SHIFT))&CCM_CCGR5_CG1_MASK)
#define CCM_CCGR5_CG2_MASK                       0x30u
#define CCM_CCGR5_CG2_SHIFT                      4
#define CCM_CCGR5_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG2_SHIFT))&CCM_CCGR5_CG2_MASK)
#define CCM_CCGR5_CG3_MASK                       0xC0u
#define CCM_CCGR5_CG3_SHIFT                      6
#define CCM_CCGR5_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG3_SHIFT))&CCM_CCGR5_CG3_MASK)
#define CCM_CCGR5_CG4_MASK                       0x300u
#define CCM_CCGR5_CG4_SHIFT                      8
#define CCM_CCGR5_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG4_SHIFT))&CCM_CCGR5_CG4_MASK)
#define CCM_CCGR5_CG5_MASK                       0xC00u
#define CCM_CCGR5_CG5_SHIFT                      10
#define CCM_CCGR5_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG5_SHIFT))&CCM_CCGR5_CG5_MASK)
#define CCM_CCGR5_CG6_MASK                       0x3000u
#define CCM_CCGR5_CG6_SHIFT                      12
#define CCM_CCGR5_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG6_SHIFT))&CCM_CCGR5_CG6_MASK)
#define CCM_CCGR5_CG7_MASK                       0xC000u
#define CCM_CCGR5_CG7_SHIFT                      14
#define CCM_CCGR5_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG7_SHIFT))&CCM_CCGR5_CG7_MASK)
#define CCM_CCGR5_CG8_MASK                       0x30000u
#define CCM_CCGR5_CG8_SHIFT                      16
#define CCM_CCGR5_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG8_SHIFT))&CCM_CCGR5_CG8_MASK)
#define CCM_CCGR5_CG9_MASK                       0xC0000u
#define CCM_CCGR5_CG9_SHIFT                      18
#define CCM_CCGR5_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG9_SHIFT))&CCM_CCGR5_CG9_MASK)
#define CCM_CCGR5_CG10_MASK                      0x300000u
#define CCM_CCGR5_CG10_SHIFT                     20
#define CCM_CCGR5_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG10_SHIFT))&CCM_CCGR5_CG10_MASK)
#define CCM_CCGR5_CG11_MASK                      0xC00000u
#define CCM_CCGR5_CG11_SHIFT                     22
#define CCM_CCGR5_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG11_SHIFT))&CCM_CCGR5_CG11_MASK)
#define CCM_CCGR5_CG12_MASK                      0x3000000u
#define CCM_CCGR5_CG12_SHIFT                     24
#define CCM_CCGR5_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG12_SHIFT))&CCM_CCGR5_CG12_MASK)
#define CCM_CCGR5_CG13_MASK                      0xC000000u
#define CCM_CCGR5_CG13_SHIFT                     26
#define CCM_CCGR5_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG13_SHIFT))&CCM_CCGR5_CG13_MASK)
#define CCM_CCGR5_CG14_MASK                      0x30000000u
#define CCM_CCGR5_CG14_SHIFT                     28
#define CCM_CCGR5_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG14_SHIFT))&CCM_CCGR5_CG14_MASK)
#define CCM_CCGR5_CG15_MASK                      0xC0000000u
#define CCM_CCGR5_CG15_SHIFT                     30
#define CCM_CCGR5_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG15_SHIFT))&CCM_CCGR5_CG15_MASK)
/* CCGR6 Bit Fields */
#define CCM_CCGR6_CG0_MASK                       0x3u
#define CCM_CCGR6_CG0_SHIFT                      0
#define CCM_CCGR6_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG0_SHIFT))&CCM_CCGR6_CG0_MASK)
#define CCM_CCGR6_CG1_MASK                       0xCu
#define CCM_CCGR6_CG1_SHIFT                      2
#define CCM_CCGR6_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG1_SHIFT))&CCM_CCGR6_CG1_MASK)
#define CCM_CCGR6_CG2_MASK                       0x30u
#define CCM_CCGR6_CG2_SHIFT                      4
#define CCM_CCGR6_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG2_SHIFT))&CCM_CCGR6_CG2_MASK)
#define CCM_CCGR6_CG3_MASK                       0xC0u
#define CCM_CCGR6_CG3_SHIFT                      6
#define CCM_CCGR6_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG3_SHIFT))&CCM_CCGR6_CG3_MASK)
#define CCM_CCGR6_CG4_MASK                       0x300u
#define CCM_CCGR6_CG4_SHIFT                      8
#define CCM_CCGR6_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG4_SHIFT))&CCM_CCGR6_CG4_MASK)
#define CCM_CCGR6_CG5_MASK                       0xC00u
#define CCM_CCGR6_CG5_SHIFT                      10
#define CCM_CCGR6_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG5_SHIFT))&CCM_CCGR6_CG5_MASK)
#define CCM_CCGR6_CG6_MASK                       0x3000u
#define CCM_CCGR6_CG6_SHIFT                      12
#define CCM_CCGR6_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG6_SHIFT))&CCM_CCGR6_CG6_MASK)
#define CCM_CCGR6_CG7_MASK                       0xC000u
#define CCM_CCGR6_CG7_SHIFT                      14
#define CCM_CCGR6_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG7_SHIFT))&CCM_CCGR6_CG7_MASK)
#define CCM_CCGR6_CG8_MASK                       0x30000u
#define CCM_CCGR6_CG8_SHIFT                      16
#define CCM_CCGR6_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG8_SHIFT))&CCM_CCGR6_CG8_MASK)
#define CCM_CCGR6_CG9_MASK                       0xC0000u
#define CCM_CCGR6_CG9_SHIFT                      18
#define CCM_CCGR6_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG9_SHIFT))&CCM_CCGR6_CG9_MASK)
#define CCM_CCGR6_CG10_MASK                      0x300000u
#define CCM_CCGR6_CG10_SHIFT                     20
#define CCM_CCGR6_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG10_SHIFT))&CCM_CCGR6_CG10_MASK)
#define CCM_CCGR6_CG11_MASK                      0xC00000u
#define CCM_CCGR6_CG11_SHIFT                     22
#define CCM_CCGR6_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG11_SHIFT))&CCM_CCGR6_CG11_MASK)
#define CCM_CCGR6_CG12_MASK                      0x3000000u
#define CCM_CCGR6_CG12_SHIFT                     24
#define CCM_CCGR6_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG12_SHIFT))&CCM_CCGR6_CG12_MASK)
#define CCM_CCGR6_CG13_MASK                      0xC000000u
#define CCM_CCGR6_CG13_SHIFT                     26
#define CCM_CCGR6_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG13_SHIFT))&CCM_CCGR6_CG13_MASK)
#define CCM_CCGR6_CG14_MASK                      0x30000000u
#define CCM_CCGR6_CG14_SHIFT                     28
#define CCM_CCGR6_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG14_SHIFT))&CCM_CCGR6_CG14_MASK)
#define CCM_CCGR6_CG15_MASK                      0xC0000000u
#define CCM_CCGR6_CG15_SHIFT                     30
#define CCM_CCGR6_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG15_SHIFT))&CCM_CCGR6_CG15_MASK)
/* CCGR7 Bit Fields */
#define CCM_CCGR7_CG0_MASK                       0x3u
#define CCM_CCGR7_CG0_SHIFT                      0
#define CCM_CCGR7_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG0_SHIFT))&CCM_CCGR7_CG0_MASK)
#define CCM_CCGR7_CG1_MASK                       0xCu
#define CCM_CCGR7_CG1_SHIFT                      2
#define CCM_CCGR7_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG1_SHIFT))&CCM_CCGR7_CG1_MASK)
#define CCM_CCGR7_CG2_MASK                       0x30u
#define CCM_CCGR7_CG2_SHIFT                      4
#define CCM_CCGR7_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG2_SHIFT))&CCM_CCGR7_CG2_MASK)
#define CCM_CCGR7_CG3_MASK                       0xC0u
#define CCM_CCGR7_CG3_SHIFT                      6
#define CCM_CCGR7_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG3_SHIFT))&CCM_CCGR7_CG3_MASK)
#define CCM_CCGR7_CG4_MASK                       0x300u
#define CCM_CCGR7_CG4_SHIFT                      8
#define CCM_CCGR7_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG4_SHIFT))&CCM_CCGR7_CG4_MASK)
#define CCM_CCGR7_CG5_MASK                       0xC00u
#define CCM_CCGR7_CG5_SHIFT                      10
#define CCM_CCGR7_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG5_SHIFT))&CCM_CCGR7_CG5_MASK)
#define CCM_CCGR7_CG6_MASK                       0x3000u
#define CCM_CCGR7_CG6_SHIFT                      12
#define CCM_CCGR7_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG6_SHIFT))&CCM_CCGR7_CG6_MASK)
#define CCM_CCGR7_CG7_MASK                       0xC000u
#define CCM_CCGR7_CG7_SHIFT                      14
#define CCM_CCGR7_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG7_SHIFT))&CCM_CCGR7_CG7_MASK)
#define CCM_CCGR7_CG8_MASK                       0x30000u
#define CCM_CCGR7_CG8_SHIFT                      16
#define CCM_CCGR7_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG8_SHIFT))&CCM_CCGR7_CG8_MASK)
#define CCM_CCGR7_CG9_MASK                       0xC0000u
#define CCM_CCGR7_CG9_SHIFT                      18
#define CCM_CCGR7_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG9_SHIFT))&CCM_CCGR7_CG9_MASK)
#define CCM_CCGR7_CG10_MASK                      0x300000u
#define CCM_CCGR7_CG10_SHIFT                     20
#define CCM_CCGR7_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG10_SHIFT))&CCM_CCGR7_CG10_MASK)
#define CCM_CCGR7_CG11_MASK                      0xC00000u
#define CCM_CCGR7_CG11_SHIFT                     22
#define CCM_CCGR7_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG11_SHIFT))&CCM_CCGR7_CG11_MASK)
#define CCM_CCGR7_CG12_MASK                      0x3000000u
#define CCM_CCGR7_CG12_SHIFT                     24
#define CCM_CCGR7_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG12_SHIFT))&CCM_CCGR7_CG12_MASK)
#define CCM_CCGR7_CG13_MASK                      0xC000000u
#define CCM_CCGR7_CG13_SHIFT                     26
#define CCM_CCGR7_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG13_SHIFT))&CCM_CCGR7_CG13_MASK)
#define CCM_CCGR7_CG14_MASK                      0x30000000u
#define CCM_CCGR7_CG14_SHIFT                     28
#define CCM_CCGR7_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG14_SHIFT))&CCM_CCGR7_CG14_MASK)
#define CCM_CCGR7_CG15_MASK                      0xC0000000u
#define CCM_CCGR7_CG15_SHIFT                     30
#define CCM_CCGR7_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG15_SHIFT))&CCM_CCGR7_CG15_MASK)
/* CCGR8 Bit Fields */
#define CCM_CCGR8_CG0_MASK                       0x3u
#define CCM_CCGR8_CG0_SHIFT                      0
#define CCM_CCGR8_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG0_SHIFT))&CCM_CCGR8_CG0_MASK)
#define CCM_CCGR8_CG1_MASK                       0xCu
#define CCM_CCGR8_CG1_SHIFT                      2
#define CCM_CCGR8_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG1_SHIFT))&CCM_CCGR8_CG1_MASK)
#define CCM_CCGR8_CG2_MASK                       0x30u
#define CCM_CCGR8_CG2_SHIFT                      4
#define CCM_CCGR8_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG2_SHIFT))&CCM_CCGR8_CG2_MASK)
#define CCM_CCGR8_CG3_MASK                       0xC0u
#define CCM_CCGR8_CG3_SHIFT                      6
#define CCM_CCGR8_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG3_SHIFT))&CCM_CCGR8_CG3_MASK)
#define CCM_CCGR8_CG4_MASK                       0x300u
#define CCM_CCGR8_CG4_SHIFT                      8
#define CCM_CCGR8_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG4_SHIFT))&CCM_CCGR8_CG4_MASK)
#define CCM_CCGR8_CG5_MASK                       0xC00u
#define CCM_CCGR8_CG5_SHIFT                      10
#define CCM_CCGR8_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG5_SHIFT))&CCM_CCGR8_CG5_MASK)
#define CCM_CCGR8_CG6_MASK                       0x3000u
#define CCM_CCGR8_CG6_SHIFT                      12
#define CCM_CCGR8_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG6_SHIFT))&CCM_CCGR8_CG6_MASK)
#define CCM_CCGR8_CG7_MASK                       0xC000u
#define CCM_CCGR8_CG7_SHIFT                      14
#define CCM_CCGR8_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG7_SHIFT))&CCM_CCGR8_CG7_MASK)
#define CCM_CCGR8_CG8_MASK                       0x30000u
#define CCM_CCGR8_CG8_SHIFT                      16
#define CCM_CCGR8_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG8_SHIFT))&CCM_CCGR8_CG8_MASK)
#define CCM_CCGR8_CG9_MASK                       0xC0000u
#define CCM_CCGR8_CG9_SHIFT                      18
#define CCM_CCGR8_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG9_SHIFT))&CCM_CCGR8_CG9_MASK)
#define CCM_CCGR8_CG10_MASK                      0x300000u
#define CCM_CCGR8_CG10_SHIFT                     20
#define CCM_CCGR8_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG10_SHIFT))&CCM_CCGR8_CG10_MASK)
#define CCM_CCGR8_CG11_MASK                      0xC00000u
#define CCM_CCGR8_CG11_SHIFT                     22
#define CCM_CCGR8_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG11_SHIFT))&CCM_CCGR8_CG11_MASK)
#define CCM_CCGR8_CG12_MASK                      0x3000000u
#define CCM_CCGR8_CG12_SHIFT                     24
#define CCM_CCGR8_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG12_SHIFT))&CCM_CCGR8_CG12_MASK)
#define CCM_CCGR8_CG13_MASK                      0xC000000u
#define CCM_CCGR8_CG13_SHIFT                     26
#define CCM_CCGR8_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG13_SHIFT))&CCM_CCGR8_CG13_MASK)
#define CCM_CCGR8_CG14_MASK                      0x30000000u
#define CCM_CCGR8_CG14_SHIFT                     28
#define CCM_CCGR8_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG14_SHIFT))&CCM_CCGR8_CG14_MASK)
#define CCM_CCGR8_CG15_MASK                      0xC0000000u
#define CCM_CCGR8_CG15_SHIFT                     30
#define CCM_CCGR8_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG15_SHIFT))&CCM_CCGR8_CG15_MASK)
/* CCGR9 Bit Fields */
#define CCM_CCGR9_CG0_MASK                       0x3u
#define CCM_CCGR9_CG0_SHIFT                      0
#define CCM_CCGR9_CG0(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG0_SHIFT))&CCM_CCGR9_CG0_MASK)
#define CCM_CCGR9_CG1_MASK                       0xCu
#define CCM_CCGR9_CG1_SHIFT                      2
#define CCM_CCGR9_CG1(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG1_SHIFT))&CCM_CCGR9_CG1_MASK)
#define CCM_CCGR9_CG2_MASK                       0x30u
#define CCM_CCGR9_CG2_SHIFT                      4
#define CCM_CCGR9_CG2(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG2_SHIFT))&CCM_CCGR9_CG2_MASK)
#define CCM_CCGR9_CG3_MASK                       0xC0u
#define CCM_CCGR9_CG3_SHIFT                      6
#define CCM_CCGR9_CG3(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG3_SHIFT))&CCM_CCGR9_CG3_MASK)
#define CCM_CCGR9_CG4_MASK                       0x300u
#define CCM_CCGR9_CG4_SHIFT                      8
#define CCM_CCGR9_CG4(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG4_SHIFT))&CCM_CCGR9_CG4_MASK)
#define CCM_CCGR9_CG5_MASK                       0xC00u
#define CCM_CCGR9_CG5_SHIFT                      10
#define CCM_CCGR9_CG5(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG5_SHIFT))&CCM_CCGR9_CG5_MASK)
#define CCM_CCGR9_CG6_MASK                       0x3000u
#define CCM_CCGR9_CG6_SHIFT                      12
#define CCM_CCGR9_CG6(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG6_SHIFT))&CCM_CCGR9_CG6_MASK)
#define CCM_CCGR9_CG7_MASK                       0xC000u
#define CCM_CCGR9_CG7_SHIFT                      14
#define CCM_CCGR9_CG7(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG7_SHIFT))&CCM_CCGR9_CG7_MASK)
#define CCM_CCGR9_CG8_MASK                       0x30000u
#define CCM_CCGR9_CG8_SHIFT                      16
#define CCM_CCGR9_CG8(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG8_SHIFT))&CCM_CCGR9_CG8_MASK)
#define CCM_CCGR9_CG9_MASK                       0xC0000u
#define CCM_CCGR9_CG9_SHIFT                      18
#define CCM_CCGR9_CG9(x)                         (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG9_SHIFT))&CCM_CCGR9_CG9_MASK)
#define CCM_CCGR9_CG10_MASK                      0x300000u
#define CCM_CCGR9_CG10_SHIFT                     20
#define CCM_CCGR9_CG10(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG10_SHIFT))&CCM_CCGR9_CG10_MASK)
#define CCM_CCGR9_CG11_MASK                      0xC00000u
#define CCM_CCGR9_CG11_SHIFT                     22
#define CCM_CCGR9_CG11(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG11_SHIFT))&CCM_CCGR9_CG11_MASK)
#define CCM_CCGR9_CG12_MASK                      0x3000000u
#define CCM_CCGR9_CG12_SHIFT                     24
#define CCM_CCGR9_CG12(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG12_SHIFT))&CCM_CCGR9_CG12_MASK)
#define CCM_CCGR9_CG13_MASK                      0xC000000u
#define CCM_CCGR9_CG13_SHIFT                     26
#define CCM_CCGR9_CG13(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG13_SHIFT))&CCM_CCGR9_CG13_MASK)
#define CCM_CCGR9_CG14_MASK                      0x30000000u
#define CCM_CCGR9_CG14_SHIFT                     28
#define CCM_CCGR9_CG14(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG14_SHIFT))&CCM_CCGR9_CG14_MASK)
#define CCM_CCGR9_CG15_MASK                      0xC0000000u
#define CCM_CCGR9_CG15_SHIFT                     30
#define CCM_CCGR9_CG15(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG15_SHIFT))&CCM_CCGR9_CG15_MASK)
/* CCGR10 Bit Fields */
#define CCM_CCGR10_CG0_MASK                      0x3u
#define CCM_CCGR10_CG0_SHIFT                     0
#define CCM_CCGR10_CG0(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG0_SHIFT))&CCM_CCGR10_CG0_MASK)
#define CCM_CCGR10_CG1_MASK                      0xCu
#define CCM_CCGR10_CG1_SHIFT                     2
#define CCM_CCGR10_CG1(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG1_SHIFT))&CCM_CCGR10_CG1_MASK)
#define CCM_CCGR10_CG2_MASK                      0x30u
#define CCM_CCGR10_CG2_SHIFT                     4
#define CCM_CCGR10_CG2(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG2_SHIFT))&CCM_CCGR10_CG2_MASK)
#define CCM_CCGR10_CG3_MASK                      0xC0u
#define CCM_CCGR10_CG3_SHIFT                     6
#define CCM_CCGR10_CG3(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG3_SHIFT))&CCM_CCGR10_CG3_MASK)
#define CCM_CCGR10_CG4_MASK                      0x300u
#define CCM_CCGR10_CG4_SHIFT                     8
#define CCM_CCGR10_CG4(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG4_SHIFT))&CCM_CCGR10_CG4_MASK)
#define CCM_CCGR10_CG5_MASK                      0xC00u
#define CCM_CCGR10_CG5_SHIFT                     10
#define CCM_CCGR10_CG5(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG5_SHIFT))&CCM_CCGR10_CG5_MASK)
#define CCM_CCGR10_CG6_MASK                      0x3000u
#define CCM_CCGR10_CG6_SHIFT                     12
#define CCM_CCGR10_CG6(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG6_SHIFT))&CCM_CCGR10_CG6_MASK)
#define CCM_CCGR10_CG7_MASK                      0xC000u
#define CCM_CCGR10_CG7_SHIFT                     14
#define CCM_CCGR10_CG7(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG7_SHIFT))&CCM_CCGR10_CG7_MASK)
#define CCM_CCGR10_CG8_MASK                      0x30000u
#define CCM_CCGR10_CG8_SHIFT                     16
#define CCM_CCGR10_CG8(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG8_SHIFT))&CCM_CCGR10_CG8_MASK)
#define CCM_CCGR10_CG9_MASK                      0xC0000u
#define CCM_CCGR10_CG9_SHIFT                     18
#define CCM_CCGR10_CG9(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG9_SHIFT))&CCM_CCGR10_CG9_MASK)
#define CCM_CCGR10_CG10_MASK                     0x300000u
#define CCM_CCGR10_CG10_SHIFT                    20
#define CCM_CCGR10_CG10(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG10_SHIFT))&CCM_CCGR10_CG10_MASK)
#define CCM_CCGR10_CG11_MASK                     0xC00000u
#define CCM_CCGR10_CG11_SHIFT                    22
#define CCM_CCGR10_CG11(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG11_SHIFT))&CCM_CCGR10_CG11_MASK)
#define CCM_CCGR10_CG12_MASK                     0x3000000u
#define CCM_CCGR10_CG12_SHIFT                    24
#define CCM_CCGR10_CG12(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG12_SHIFT))&CCM_CCGR10_CG12_MASK)
#define CCM_CCGR10_CG13_MASK                     0xC000000u
#define CCM_CCGR10_CG13_SHIFT                    26
#define CCM_CCGR10_CG13(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG13_SHIFT))&CCM_CCGR10_CG13_MASK)
#define CCM_CCGR10_CG14_MASK                     0x30000000u
#define CCM_CCGR10_CG14_SHIFT                    28
#define CCM_CCGR10_CG14(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG14_SHIFT))&CCM_CCGR10_CG14_MASK)
#define CCM_CCGR10_CG15_MASK                     0xC0000000u
#define CCM_CCGR10_CG15_SHIFT                    30
#define CCM_CCGR10_CG15(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG15_SHIFT))&CCM_CCGR10_CG15_MASK)
/* CCGR11 Bit Fields */
#define CCM_CCGR11_CG0_MASK                      0x3u
#define CCM_CCGR11_CG0_SHIFT                     0
#define CCM_CCGR11_CG0(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG0_SHIFT))&CCM_CCGR11_CG0_MASK)
#define CCM_CCGR11_CG1_MASK                      0xCu
#define CCM_CCGR11_CG1_SHIFT                     2
#define CCM_CCGR11_CG1(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG1_SHIFT))&CCM_CCGR11_CG1_MASK)
#define CCM_CCGR11_CG2_MASK                      0x30u
#define CCM_CCGR11_CG2_SHIFT                     4
#define CCM_CCGR11_CG2(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG2_SHIFT))&CCM_CCGR11_CG2_MASK)
#define CCM_CCGR11_CG3_MASK                      0xC0u
#define CCM_CCGR11_CG3_SHIFT                     6
#define CCM_CCGR11_CG3(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG3_SHIFT))&CCM_CCGR11_CG3_MASK)
#define CCM_CCGR11_CG4_MASK                      0x300u
#define CCM_CCGR11_CG4_SHIFT                     8
#define CCM_CCGR11_CG4(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG4_SHIFT))&CCM_CCGR11_CG4_MASK)
#define CCM_CCGR11_CG5_MASK                      0xC00u
#define CCM_CCGR11_CG5_SHIFT                     10
#define CCM_CCGR11_CG5(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG5_SHIFT))&CCM_CCGR11_CG5_MASK)
#define CCM_CCGR11_CG6_MASK                      0x3000u
#define CCM_CCGR11_CG6_SHIFT                     12
#define CCM_CCGR11_CG6(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG6_SHIFT))&CCM_CCGR11_CG6_MASK)
#define CCM_CCGR11_CG7_MASK                      0xC000u
#define CCM_CCGR11_CG7_SHIFT                     14
#define CCM_CCGR11_CG7(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG7_SHIFT))&CCM_CCGR11_CG7_MASK)
#define CCM_CCGR11_CG8_MASK                      0x30000u
#define CCM_CCGR11_CG8_SHIFT                     16
#define CCM_CCGR11_CG8(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG8_SHIFT))&CCM_CCGR11_CG8_MASK)
#define CCM_CCGR11_CG9_MASK                      0xC0000u
#define CCM_CCGR11_CG9_SHIFT                     18
#define CCM_CCGR11_CG9(x)                        (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG9_SHIFT))&CCM_CCGR11_CG9_MASK)
#define CCM_CCGR11_CG10_MASK                     0x300000u
#define CCM_CCGR11_CG10_SHIFT                    20
#define CCM_CCGR11_CG10(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG10_SHIFT))&CCM_CCGR11_CG10_MASK)
#define CCM_CCGR11_CG11_MASK                     0xC00000u
#define CCM_CCGR11_CG11_SHIFT                    22
#define CCM_CCGR11_CG11(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG11_SHIFT))&CCM_CCGR11_CG11_MASK)
#define CCM_CCGR11_CG12_MASK                     0x3000000u
#define CCM_CCGR11_CG12_SHIFT                    24
#define CCM_CCGR11_CG12(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG12_SHIFT))&CCM_CCGR11_CG12_MASK)
#define CCM_CCGR11_CG13_MASK                     0xC000000u
#define CCM_CCGR11_CG13_SHIFT                    26
#define CCM_CCGR11_CG13(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG13_SHIFT))&CCM_CCGR11_CG13_MASK)
#define CCM_CCGR11_CG14_MASK                     0x30000000u
#define CCM_CCGR11_CG14_SHIFT                    28
#define CCM_CCGR11_CG14(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG14_SHIFT))&CCM_CCGR11_CG14_MASK)
#define CCM_CCGR11_CG15_MASK                     0xC0000000u
#define CCM_CCGR11_CG15_SHIFT                    30
#define CCM_CCGR11_CG15(x)                       (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG15_SHIFT))&CCM_CCGR11_CG15_MASK)
/* CMEOR0 Bit Fields */
#define CCM_CMEOR0_MO0_MASK                      0x1u
#define CCM_CMEOR0_MO0_SHIFT                     0
#define CCM_CMEOR0_MO1_MASK                      0x2u
#define CCM_CMEOR0_MO1_SHIFT                     1
#define CCM_CMEOR0_MO2_MASK                      0x4u
#define CCM_CMEOR0_MO2_SHIFT                     2
#define CCM_CMEOR0_MO3_MASK                      0x8u
#define CCM_CMEOR0_MO3_SHIFT                     3
#define CCM_CMEOR0_MO4_MASK                      0x10u
#define CCM_CMEOR0_MO4_SHIFT                     4
#define CCM_CMEOR0_MO5_MASK                      0x20u
#define CCM_CMEOR0_MO5_SHIFT                     5
#define CCM_CMEOR0_MO6_MASK                      0x40u
#define CCM_CMEOR0_MO6_SHIFT                     6
#define CCM_CMEOR0_MO7_MASK                      0x80u
#define CCM_CMEOR0_MO7_SHIFT                     7
#define CCM_CMEOR0_MO8_MASK                      0x100u
#define CCM_CMEOR0_MO8_SHIFT                     8
#define CCM_CMEOR0_MO9_MASK                      0x200u
#define CCM_CMEOR0_MO9_SHIFT                     9
#define CCM_CMEOR0_MO10_MASK                     0x400u
#define CCM_CMEOR0_MO10_SHIFT                    10
#define CCM_CMEOR0_MO11_MASK                     0x800u
#define CCM_CMEOR0_MO11_SHIFT                    11
#define CCM_CMEOR0_MO12_MASK                     0x1000u
#define CCM_CMEOR0_MO12_SHIFT                    12
#define CCM_CMEOR0_MO13_MASK                     0x2000u
#define CCM_CMEOR0_MO13_SHIFT                    13
#define CCM_CMEOR0_MO14_MASK                     0x4000u
#define CCM_CMEOR0_MO14_SHIFT                    14
#define CCM_CMEOR0_MO15_MASK                     0x8000u
#define CCM_CMEOR0_MO15_SHIFT                    15
#define CCM_CMEOR0_MO16_MASK                     0x10000u
#define CCM_CMEOR0_MO16_SHIFT                    16
#define CCM_CMEOR0_MO17_MASK                     0x20000u
#define CCM_CMEOR0_MO17_SHIFT                    17
#define CCM_CMEOR0_MO18_MASK                     0x40000u
#define CCM_CMEOR0_MO18_SHIFT                    18
#define CCM_CMEOR0_MO19_MASK                     0x80000u
#define CCM_CMEOR0_MO19_SHIFT                    19
#define CCM_CMEOR0_MO20_MASK                     0x100000u
#define CCM_CMEOR0_MO20_SHIFT                    20
#define CCM_CMEOR0_MO21_MASK                     0x200000u
#define CCM_CMEOR0_MO21_SHIFT                    21
#define CCM_CMEOR0_MO22_MASK                     0x400000u
#define CCM_CMEOR0_MO22_SHIFT                    22
#define CCM_CMEOR0_MO23_MASK                     0x800000u
#define CCM_CMEOR0_MO23_SHIFT                    23
#define CCM_CMEOR0_MO24_MASK                     0x1000000u
#define CCM_CMEOR0_MO24_SHIFT                    24
#define CCM_CMEOR0_MO25_MASK                     0x2000000u
#define CCM_CMEOR0_MO25_SHIFT                    25
#define CCM_CMEOR0_MO26_MASK                     0x4000000u
#define CCM_CMEOR0_MO26_SHIFT                    26
#define CCM_CMEOR0_MO27_MASK                     0x8000000u
#define CCM_CMEOR0_MO27_SHIFT                    27
#define CCM_CMEOR0_MO28_MASK                     0x10000000u
#define CCM_CMEOR0_MO28_SHIFT                    28
#define CCM_CMEOR0_MO29_MASK                     0x20000000u
#define CCM_CMEOR0_MO29_SHIFT                    29
#define CCM_CMEOR0_MO30_MASK                     0x40000000u
#define CCM_CMEOR0_MO30_SHIFT                    30
#define CCM_CMEOR0_MO31_MASK                     0x80000000u
#define CCM_CMEOR0_MO31_SHIFT                    31
/* CMEOR1 Bit Fields */
#define CCM_CMEOR1_MO0_MASK                      0x1u
#define CCM_CMEOR1_MO0_SHIFT                     0
#define CCM_CMEOR1_MO1_MASK                      0x2u
#define CCM_CMEOR1_MO1_SHIFT                     1
#define CCM_CMEOR1_MO2_MASK                      0x4u
#define CCM_CMEOR1_MO2_SHIFT                     2
#define CCM_CMEOR1_MO3_MASK                      0x8u
#define CCM_CMEOR1_MO3_SHIFT                     3
#define CCM_CMEOR1_MO4_MASK                      0x10u
#define CCM_CMEOR1_MO4_SHIFT                     4
#define CCM_CMEOR1_MO5_MASK                      0x20u
#define CCM_CMEOR1_MO5_SHIFT                     5
#define CCM_CMEOR1_MO6_MASK                      0x40u
#define CCM_CMEOR1_MO6_SHIFT                     6
#define CCM_CMEOR1_MO7_MASK                      0x80u
#define CCM_CMEOR1_MO7_SHIFT                     7
#define CCM_CMEOR1_MO8_MASK                      0x100u
#define CCM_CMEOR1_MO8_SHIFT                     8
#define CCM_CMEOR1_MO9_MASK                      0x200u
#define CCM_CMEOR1_MO9_SHIFT                     9
#define CCM_CMEOR1_MO10_MASK                     0x400u
#define CCM_CMEOR1_MO10_SHIFT                    10
#define CCM_CMEOR1_MO11_MASK                     0x800u
#define CCM_CMEOR1_MO11_SHIFT                    11
#define CCM_CMEOR1_MO12_MASK                     0x1000u
#define CCM_CMEOR1_MO12_SHIFT                    12
#define CCM_CMEOR1_MO13_MASK                     0x2000u
#define CCM_CMEOR1_MO13_SHIFT                    13
#define CCM_CMEOR1_MO14_MASK                     0x4000u
#define CCM_CMEOR1_MO14_SHIFT                    14
#define CCM_CMEOR1_MO15_MASK                     0x8000u
#define CCM_CMEOR1_MO15_SHIFT                    15
#define CCM_CMEOR1_MO16_MASK                     0x10000u
#define CCM_CMEOR1_MO16_SHIFT                    16
#define CCM_CMEOR1_MO17_MASK                     0x20000u
#define CCM_CMEOR1_MO17_SHIFT                    17
#define CCM_CMEOR1_MO18_MASK                     0x40000u
#define CCM_CMEOR1_MO18_SHIFT                    18
#define CCM_CMEOR1_MO19_MASK                     0x80000u
#define CCM_CMEOR1_MO19_SHIFT                    19
#define CCM_CMEOR1_MO20_MASK                     0x100000u
#define CCM_CMEOR1_MO20_SHIFT                    20
#define CCM_CMEOR1_MO21_MASK                     0x200000u
#define CCM_CMEOR1_MO21_SHIFT                    21
#define CCM_CMEOR1_MO22_MASK                     0x400000u
#define CCM_CMEOR1_MO22_SHIFT                    22
#define CCM_CMEOR1_MO23_MASK                     0x800000u
#define CCM_CMEOR1_MO23_SHIFT                    23
#define CCM_CMEOR1_MO24_MASK                     0x1000000u
#define CCM_CMEOR1_MO24_SHIFT                    24
#define CCM_CMEOR1_MO25_MASK                     0x2000000u
#define CCM_CMEOR1_MO25_SHIFT                    25
#define CCM_CMEOR1_MO26_MASK                     0x4000000u
#define CCM_CMEOR1_MO26_SHIFT                    26
#define CCM_CMEOR1_MO27_MASK                     0x8000000u
#define CCM_CMEOR1_MO27_SHIFT                    27
#define CCM_CMEOR1_MO28_MASK                     0x10000000u
#define CCM_CMEOR1_MO28_SHIFT                    28
#define CCM_CMEOR1_MO29_MASK                     0x20000000u
#define CCM_CMEOR1_MO29_SHIFT                    29
#define CCM_CMEOR1_MO30_MASK                     0x40000000u
#define CCM_CMEOR1_MO30_SHIFT                    30
#define CCM_CMEOR1_MO31_MASK                     0x80000000u
#define CCM_CMEOR1_MO31_SHIFT                    31
/* CMEOR2 Bit Fields */
#define CCM_CMEOR2_MO0_MASK                      0x1u
#define CCM_CMEOR2_MO0_SHIFT                     0
#define CCM_CMEOR2_MO1_MASK                      0x2u
#define CCM_CMEOR2_MO1_SHIFT                     1
#define CCM_CMEOR2_MO2_MASK                      0x4u
#define CCM_CMEOR2_MO2_SHIFT                     2
#define CCM_CMEOR2_MO3_MASK                      0x8u
#define CCM_CMEOR2_MO3_SHIFT                     3
#define CCM_CMEOR2_MO4_MASK                      0x10u
#define CCM_CMEOR2_MO4_SHIFT                     4
#define CCM_CMEOR2_MO5_MASK                      0x20u
#define CCM_CMEOR2_MO5_SHIFT                     5
#define CCM_CMEOR2_MO6_MASK                      0x40u
#define CCM_CMEOR2_MO6_SHIFT                     6
#define CCM_CMEOR2_MO7_MASK                      0x80u
#define CCM_CMEOR2_MO7_SHIFT                     7
#define CCM_CMEOR2_MO8_MASK                      0x100u
#define CCM_CMEOR2_MO8_SHIFT                     8
#define CCM_CMEOR2_MO9_MASK                      0x200u
#define CCM_CMEOR2_MO9_SHIFT                     9
#define CCM_CMEOR2_MO10_MASK                     0x400u
#define CCM_CMEOR2_MO10_SHIFT                    10
#define CCM_CMEOR2_MO11_MASK                     0x800u
#define CCM_CMEOR2_MO11_SHIFT                    11
#define CCM_CMEOR2_MO12_MASK                     0x1000u
#define CCM_CMEOR2_MO12_SHIFT                    12
#define CCM_CMEOR2_MO13_MASK                     0x2000u
#define CCM_CMEOR2_MO13_SHIFT                    13
#define CCM_CMEOR2_MO14_MASK                     0x4000u
#define CCM_CMEOR2_MO14_SHIFT                    14
#define CCM_CMEOR2_MO15_MASK                     0x8000u
#define CCM_CMEOR2_MO15_SHIFT                    15
#define CCM_CMEOR2_MO16_MASK                     0x10000u
#define CCM_CMEOR2_MO16_SHIFT                    16
#define CCM_CMEOR2_MO17_MASK                     0x20000u
#define CCM_CMEOR2_MO17_SHIFT                    17
#define CCM_CMEOR2_MO18_MASK                     0x40000u
#define CCM_CMEOR2_MO18_SHIFT                    18
#define CCM_CMEOR2_MO19_MASK                     0x80000u
#define CCM_CMEOR2_MO19_SHIFT                    19
#define CCM_CMEOR2_MO20_MASK                     0x100000u
#define CCM_CMEOR2_MO20_SHIFT                    20
#define CCM_CMEOR2_MO21_MASK                     0x200000u
#define CCM_CMEOR2_MO21_SHIFT                    21
#define CCM_CMEOR2_MO22_MASK                     0x400000u
#define CCM_CMEOR2_MO22_SHIFT                    22
#define CCM_CMEOR2_MO23_MASK                     0x800000u
#define CCM_CMEOR2_MO23_SHIFT                    23
#define CCM_CMEOR2_MO24_MASK                     0x1000000u
#define CCM_CMEOR2_MO24_SHIFT                    24
#define CCM_CMEOR2_MO25_MASK                     0x2000000u
#define CCM_CMEOR2_MO25_SHIFT                    25
#define CCM_CMEOR2_MO26_MASK                     0x4000000u
#define CCM_CMEOR2_MO26_SHIFT                    26
#define CCM_CMEOR2_MO27_MASK                     0x8000000u
#define CCM_CMEOR2_MO27_SHIFT                    27
#define CCM_CMEOR2_MO28_MASK                     0x10000000u
#define CCM_CMEOR2_MO28_SHIFT                    28
#define CCM_CMEOR2_MO29_MASK                     0x20000000u
#define CCM_CMEOR2_MO29_SHIFT                    29
#define CCM_CMEOR2_MO30_MASK                     0x40000000u
#define CCM_CMEOR2_MO30_SHIFT                    30
#define CCM_CMEOR2_MO31_MASK                     0x80000000u
#define CCM_CMEOR2_MO31_SHIFT                    31
/* CMEOR3 Bit Fields */
#define CCM_CMEOR3_MO0_MASK                      0x1u
#define CCM_CMEOR3_MO0_SHIFT                     0
#define CCM_CMEOR3_MO1_MASK                      0x2u
#define CCM_CMEOR3_MO1_SHIFT                     1
#define CCM_CMEOR3_MO2_MASK                      0x4u
#define CCM_CMEOR3_MO2_SHIFT                     2
#define CCM_CMEOR3_MO3_MASK                      0x8u
#define CCM_CMEOR3_MO3_SHIFT                     3
#define CCM_CMEOR3_MO4_MASK                      0x10u
#define CCM_CMEOR3_MO4_SHIFT                     4
#define CCM_CMEOR3_MO5_MASK                      0x20u
#define CCM_CMEOR3_MO5_SHIFT                     5
#define CCM_CMEOR3_MO6_MASK                      0x40u
#define CCM_CMEOR3_MO6_SHIFT                     6
#define CCM_CMEOR3_MO7_MASK                      0x80u
#define CCM_CMEOR3_MO7_SHIFT                     7
#define CCM_CMEOR3_MO8_MASK                      0x100u
#define CCM_CMEOR3_MO8_SHIFT                     8
#define CCM_CMEOR3_MO9_MASK                      0x200u
#define CCM_CMEOR3_MO9_SHIFT                     9
#define CCM_CMEOR3_MO10_MASK                     0x400u
#define CCM_CMEOR3_MO10_SHIFT                    10
#define CCM_CMEOR3_MO11_MASK                     0x800u
#define CCM_CMEOR3_MO11_SHIFT                    11
#define CCM_CMEOR3_MO12_MASK                     0x1000u
#define CCM_CMEOR3_MO12_SHIFT                    12
#define CCM_CMEOR3_MO13_MASK                     0x2000u
#define CCM_CMEOR3_MO13_SHIFT                    13
#define CCM_CMEOR3_MO14_MASK                     0x4000u
#define CCM_CMEOR3_MO14_SHIFT                    14
#define CCM_CMEOR3_MO15_MASK                     0x8000u
#define CCM_CMEOR3_MO15_SHIFT                    15
#define CCM_CMEOR3_MO16_MASK                     0x10000u
#define CCM_CMEOR3_MO16_SHIFT                    16
#define CCM_CMEOR3_MO17_MASK                     0x20000u
#define CCM_CMEOR3_MO17_SHIFT                    17
#define CCM_CMEOR3_MO18_MASK                     0x40000u
#define CCM_CMEOR3_MO18_SHIFT                    18
#define CCM_CMEOR3_MO19_MASK                     0x80000u
#define CCM_CMEOR3_MO19_SHIFT                    19
#define CCM_CMEOR3_MO20_MASK                     0x100000u
#define CCM_CMEOR3_MO20_SHIFT                    20
#define CCM_CMEOR3_MO21_MASK                     0x200000u
#define CCM_CMEOR3_MO21_SHIFT                    21
#define CCM_CMEOR3_MO22_MASK                     0x400000u
#define CCM_CMEOR3_MO22_SHIFT                    22
#define CCM_CMEOR3_MO23_MASK                     0x800000u
#define CCM_CMEOR3_MO23_SHIFT                    23
#define CCM_CMEOR3_MO24_MASK                     0x1000000u
#define CCM_CMEOR3_MO24_SHIFT                    24
#define CCM_CMEOR3_MO25_MASK                     0x2000000u
#define CCM_CMEOR3_MO25_SHIFT                    25
#define CCM_CMEOR3_MO26_MASK                     0x4000000u
#define CCM_CMEOR3_MO26_SHIFT                    26
#define CCM_CMEOR3_MO27_MASK                     0x8000000u
#define CCM_CMEOR3_MO27_SHIFT                    27
#define CCM_CMEOR3_MO28_MASK                     0x10000000u
#define CCM_CMEOR3_MO28_SHIFT                    28
#define CCM_CMEOR3_MO29_MASK                     0x20000000u
#define CCM_CMEOR3_MO29_SHIFT                    29
#define CCM_CMEOR3_MO30_MASK                     0x40000000u
#define CCM_CMEOR3_MO30_SHIFT                    30
#define CCM_CMEOR3_MO31_MASK                     0x80000000u
#define CCM_CMEOR3_MO31_SHIFT                    31
/* CMEOR4 Bit Fields */
#define CCM_CMEOR4_MO0_MASK                      0x1u
#define CCM_CMEOR4_MO0_SHIFT                     0
#define CCM_CMEOR4_MO1_MASK                      0x2u
#define CCM_CMEOR4_MO1_SHIFT                     1
#define CCM_CMEOR4_MO2_MASK                      0x4u
#define CCM_CMEOR4_MO2_SHIFT                     2
#define CCM_CMEOR4_MO3_MASK                      0x8u
#define CCM_CMEOR4_MO3_SHIFT                     3
#define CCM_CMEOR4_MO4_MASK                      0x10u
#define CCM_CMEOR4_MO4_SHIFT                     4
#define CCM_CMEOR4_MO5_MASK                      0x20u
#define CCM_CMEOR4_MO5_SHIFT                     5
#define CCM_CMEOR4_MO6_MASK                      0x40u
#define CCM_CMEOR4_MO6_SHIFT                     6
#define CCM_CMEOR4_MO7_MASK                      0x80u
#define CCM_CMEOR4_MO7_SHIFT                     7
#define CCM_CMEOR4_MO8_MASK                      0x100u
#define CCM_CMEOR4_MO8_SHIFT                     8
#define CCM_CMEOR4_MO9_MASK                      0x200u
#define CCM_CMEOR4_MO9_SHIFT                     9
#define CCM_CMEOR4_MO10_MASK                     0x400u
#define CCM_CMEOR4_MO10_SHIFT                    10
#define CCM_CMEOR4_MO11_MASK                     0x800u
#define CCM_CMEOR4_MO11_SHIFT                    11
#define CCM_CMEOR4_MO12_MASK                     0x1000u
#define CCM_CMEOR4_MO12_SHIFT                    12
#define CCM_CMEOR4_MO13_MASK                     0x2000u
#define CCM_CMEOR4_MO13_SHIFT                    13
#define CCM_CMEOR4_MO14_MASK                     0x4000u
#define CCM_CMEOR4_MO14_SHIFT                    14
#define CCM_CMEOR4_MO15_MASK                     0x8000u
#define CCM_CMEOR4_MO15_SHIFT                    15
#define CCM_CMEOR4_MO16_MASK                     0x10000u
#define CCM_CMEOR4_MO16_SHIFT                    16
#define CCM_CMEOR4_MO17_MASK                     0x20000u
#define CCM_CMEOR4_MO17_SHIFT                    17
#define CCM_CMEOR4_MO18_MASK                     0x40000u
#define CCM_CMEOR4_MO18_SHIFT                    18
#define CCM_CMEOR4_MO19_MASK                     0x80000u
#define CCM_CMEOR4_MO19_SHIFT                    19
#define CCM_CMEOR4_MO20_MASK                     0x100000u
#define CCM_CMEOR4_MO20_SHIFT                    20
#define CCM_CMEOR4_MO21_MASK                     0x200000u
#define CCM_CMEOR4_MO21_SHIFT                    21
#define CCM_CMEOR4_MO22_MASK                     0x400000u
#define CCM_CMEOR4_MO22_SHIFT                    22
#define CCM_CMEOR4_MO23_MASK                     0x800000u
#define CCM_CMEOR4_MO23_SHIFT                    23
#define CCM_CMEOR4_MO24_MASK                     0x1000000u
#define CCM_CMEOR4_MO24_SHIFT                    24
#define CCM_CMEOR4_MO25_MASK                     0x2000000u
#define CCM_CMEOR4_MO25_SHIFT                    25
#define CCM_CMEOR4_MO26_MASK                     0x4000000u
#define CCM_CMEOR4_MO26_SHIFT                    26
#define CCM_CMEOR4_MO27_MASK                     0x8000000u
#define CCM_CMEOR4_MO27_SHIFT                    27
#define CCM_CMEOR4_MO28_MASK                     0x10000000u
#define CCM_CMEOR4_MO28_SHIFT                    28
#define CCM_CMEOR4_MO29_MASK                     0x20000000u
#define CCM_CMEOR4_MO29_SHIFT                    29
#define CCM_CMEOR4_MO30_MASK                     0x40000000u
#define CCM_CMEOR4_MO30_SHIFT                    30
#define CCM_CMEOR4_MO31_MASK                     0x80000000u
#define CCM_CMEOR4_MO31_SHIFT                    31
/* CMEOR5 Bit Fields */
#define CCM_CMEOR5_MO0_MASK                      0x1u
#define CCM_CMEOR5_MO0_SHIFT                     0
#define CCM_CMEOR5_MO1_MASK                      0x2u
#define CCM_CMEOR5_MO1_SHIFT                     1
#define CCM_CMEOR5_MO2_MASK                      0x4u
#define CCM_CMEOR5_MO2_SHIFT                     2
#define CCM_CMEOR5_MO3_MASK                      0x8u
#define CCM_CMEOR5_MO3_SHIFT                     3
#define CCM_CMEOR5_MO4_MASK                      0x10u
#define CCM_CMEOR5_MO4_SHIFT                     4
#define CCM_CMEOR5_MO5_MASK                      0x20u
#define CCM_CMEOR5_MO5_SHIFT                     5
#define CCM_CMEOR5_MO6_MASK                      0x40u
#define CCM_CMEOR5_MO6_SHIFT                     6
#define CCM_CMEOR5_MO7_MASK                      0x80u
#define CCM_CMEOR5_MO7_SHIFT                     7
#define CCM_CMEOR5_MO8_MASK                      0x100u
#define CCM_CMEOR5_MO8_SHIFT                     8
#define CCM_CMEOR5_MO9_MASK                      0x200u
#define CCM_CMEOR5_MO9_SHIFT                     9
#define CCM_CMEOR5_MO10_MASK                     0x400u
#define CCM_CMEOR5_MO10_SHIFT                    10
#define CCM_CMEOR5_MO11_MASK                     0x800u
#define CCM_CMEOR5_MO11_SHIFT                    11
#define CCM_CMEOR5_MO12_MASK                     0x1000u
#define CCM_CMEOR5_MO12_SHIFT                    12
#define CCM_CMEOR5_MO13_MASK                     0x2000u
#define CCM_CMEOR5_MO13_SHIFT                    13
#define CCM_CMEOR5_MO14_MASK                     0x4000u
#define CCM_CMEOR5_MO14_SHIFT                    14
#define CCM_CMEOR5_MO15_MASK                     0x8000u
#define CCM_CMEOR5_MO15_SHIFT                    15
#define CCM_CMEOR5_MO16_MASK                     0x10000u
#define CCM_CMEOR5_MO16_SHIFT                    16
#define CCM_CMEOR5_MO17_MASK                     0x20000u
#define CCM_CMEOR5_MO17_SHIFT                    17
#define CCM_CMEOR5_MO18_MASK                     0x40000u
#define CCM_CMEOR5_MO18_SHIFT                    18
#define CCM_CMEOR5_MO19_MASK                     0x80000u
#define CCM_CMEOR5_MO19_SHIFT                    19
#define CCM_CMEOR5_MO20_MASK                     0x100000u
#define CCM_CMEOR5_MO20_SHIFT                    20
#define CCM_CMEOR5_MO21_MASK                     0x200000u
#define CCM_CMEOR5_MO21_SHIFT                    21
#define CCM_CMEOR5_MO22_MASK                     0x400000u
#define CCM_CMEOR5_MO22_SHIFT                    22
#define CCM_CMEOR5_MO23_MASK                     0x800000u
#define CCM_CMEOR5_MO23_SHIFT                    23
#define CCM_CMEOR5_MO24_MASK                     0x1000000u
#define CCM_CMEOR5_MO24_SHIFT                    24
#define CCM_CMEOR5_MO25_MASK                     0x2000000u
#define CCM_CMEOR5_MO25_SHIFT                    25
#define CCM_CMEOR5_MO26_MASK                     0x4000000u
#define CCM_CMEOR5_MO26_SHIFT                    26
#define CCM_CMEOR5_MO27_MASK                     0x8000000u
#define CCM_CMEOR5_MO27_SHIFT                    27
#define CCM_CMEOR5_MO28_MASK                     0x10000000u
#define CCM_CMEOR5_MO28_SHIFT                    28
#define CCM_CMEOR5_MO29_MASK                     0x20000000u
#define CCM_CMEOR5_MO29_SHIFT                    29
#define CCM_CMEOR5_MO30_MASK                     0x40000000u
#define CCM_CMEOR5_MO30_SHIFT                    30
#define CCM_CMEOR5_MO31_MASK                     0x80000000u
#define CCM_CMEOR5_MO31_SHIFT                    31
/* CPPDSR Bit Fields */
#define CCM_CPPDSR_PLL1_PFD1_MASK                0x1u
#define CCM_CPPDSR_PLL1_PFD1_SHIFT               0
#define CCM_CPPDSR_PLL1_PFD2_MASK                0x2u
#define CCM_CPPDSR_PLL1_PFD2_SHIFT               1
#define CCM_CPPDSR_PLL1_PFD3_MASK                0x4u
#define CCM_CPPDSR_PLL1_PFD3_SHIFT               2
#define CCM_CPPDSR_PLL1_PFD4_MASK                0x8u
#define CCM_CPPDSR_PLL1_PFD4_SHIFT               3
#define CCM_CPPDSR_PLL2_PFD1_MASK                0x10u
#define CCM_CPPDSR_PLL2_PFD1_SHIFT               4
#define CCM_CPPDSR_PLL2_PFD2_MASK                0x20u
#define CCM_CPPDSR_PLL2_PFD2_SHIFT               5
#define CCM_CPPDSR_PLL2_PFD3_MASK                0x40u
#define CCM_CPPDSR_PLL2_PFD3_SHIFT               6
#define CCM_CPPDSR_PLL2_PFD4_MASK                0x80u
#define CCM_CPPDSR_PLL2_PFD4_SHIFT               7
#define CCM_CPPDSR_PLL3_PFD1_MASK                0x100u
#define CCM_CPPDSR_PLL3_PFD1_SHIFT               8
#define CCM_CPPDSR_PLL3_PFD2_MASK                0x200u
#define CCM_CPPDSR_PLL3_PFD2_SHIFT               9
#define CCM_CPPDSR_PLL3_PFD3_MASK                0x400u
#define CCM_CPPDSR_PLL3_PFD3_SHIFT               10
#define CCM_CPPDSR_PLL3_PFD4_MASK                0x800u
#define CCM_CPPDSR_PLL3_PFD4_SHIFT               11
/* CCOWR Bit Fields */
#define CCM_CCOWR_WAKEUP_KEY_MASK                0xFFFFu
#define CCM_CCOWR_WAKEUP_KEY_SHIFT               0
#define CCM_CCOWR_WAKEUP_KEY(x)                  (((uint32_t)(((uint32_t)(x))<<CCM_CCOWR_WAKEUP_KEY_SHIFT))&CCM_CCOWR_WAKEUP_KEY_MASK)
#define CCM_CCOWR_AUX_CORE_WKUP_MASK             0x10000u
#define CCM_CCOWR_AUX_CORE_WKUP_SHIFT            16
/* CCPGR0 Bit Fields */
#define CCM_CCPGR0_PPCG0_MASK                    0x3u
#define CCM_CCPGR0_PPCG0_SHIFT                   0
#define CCM_CCPGR0_PPCG0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG0_SHIFT))&CCM_CCPGR0_PPCG0_MASK)
#define CCM_CCPGR0_PPCG1_MASK                    0xCu
#define CCM_CCPGR0_PPCG1_SHIFT                   2
#define CCM_CCPGR0_PPCG1(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG1_SHIFT))&CCM_CCPGR0_PPCG1_MASK)
#define CCM_CCPGR0_PPCG2_MASK                    0x30u
#define CCM_CCPGR0_PPCG2_SHIFT                   4
#define CCM_CCPGR0_PPCG2(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG2_SHIFT))&CCM_CCPGR0_PPCG2_MASK)
#define CCM_CCPGR0_PPCG3_MASK                    0xC0u
#define CCM_CCPGR0_PPCG3_SHIFT                   6
#define CCM_CCPGR0_PPCG3(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG3_SHIFT))&CCM_CCPGR0_PPCG3_MASK)
#define CCM_CCPGR0_PPCG4_MASK                    0x300u
#define CCM_CCPGR0_PPCG4_SHIFT                   8
#define CCM_CCPGR0_PPCG4(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG4_SHIFT))&CCM_CCPGR0_PPCG4_MASK)
#define CCM_CCPGR0_PPCG5_MASK                    0xC00u
#define CCM_CCPGR0_PPCG5_SHIFT                   10
#define CCM_CCPGR0_PPCG5(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG5_SHIFT))&CCM_CCPGR0_PPCG5_MASK)
#define CCM_CCPGR0_PPCG6_MASK                    0x3000u
#define CCM_CCPGR0_PPCG6_SHIFT                   12
#define CCM_CCPGR0_PPCG6(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG6_SHIFT))&CCM_CCPGR0_PPCG6_MASK)
#define CCM_CCPGR0_PPCG7_MASK                    0xC000u
#define CCM_CCPGR0_PPCG7_SHIFT                   14
#define CCM_CCPGR0_PPCG7(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG7_SHIFT))&CCM_CCPGR0_PPCG7_MASK)
#define CCM_CCPGR0_PPCG8_MASK                    0x30000u
#define CCM_CCPGR0_PPCG8_SHIFT                   16
#define CCM_CCPGR0_PPCG8(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG8_SHIFT))&CCM_CCPGR0_PPCG8_MASK)
#define CCM_CCPGR0_PPCG9_MASK                    0xC0000u
#define CCM_CCPGR0_PPCG9_SHIFT                   18
#define CCM_CCPGR0_PPCG9(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG9_SHIFT))&CCM_CCPGR0_PPCG9_MASK)
#define CCM_CCPGR0_PPCG10_MASK                   0x300000u
#define CCM_CCPGR0_PPCG10_SHIFT                  20
#define CCM_CCPGR0_PPCG10(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG10_SHIFT))&CCM_CCPGR0_PPCG10_MASK)
#define CCM_CCPGR0_PPCG11_MASK                   0xC00000u
#define CCM_CCPGR0_PPCG11_SHIFT                  22
#define CCM_CCPGR0_PPCG11(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG11_SHIFT))&CCM_CCPGR0_PPCG11_MASK)
#define CCM_CCPGR0_PPCG12_MASK                   0x3000000u
#define CCM_CCPGR0_PPCG12_SHIFT                  24
#define CCM_CCPGR0_PPCG12(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG12_SHIFT))&CCM_CCPGR0_PPCG12_MASK)
#define CCM_CCPGR0_PPCG13_MASK                   0xC000000u
#define CCM_CCPGR0_PPCG13_SHIFT                  26
#define CCM_CCPGR0_PPCG13(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG13_SHIFT))&CCM_CCPGR0_PPCG13_MASK)
#define CCM_CCPGR0_PPCG14_MASK                   0x30000000u
#define CCM_CCPGR0_PPCG14_SHIFT                  28
#define CCM_CCPGR0_PPCG14(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG14_SHIFT))&CCM_CCPGR0_PPCG14_MASK)
#define CCM_CCPGR0_PPCG15_MASK                   0xC0000000u
#define CCM_CCPGR0_PPCG15_SHIFT                  30
#define CCM_CCPGR0_PPCG15(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR0_PPCG15_SHIFT))&CCM_CCPGR0_PPCG15_MASK)
/* CCPGR1 Bit Fields */
#define CCM_CCPGR1_PPCG0_MASK                    0x3u
#define CCM_CCPGR1_PPCG0_SHIFT                   0
#define CCM_CCPGR1_PPCG0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG0_SHIFT))&CCM_CCPGR1_PPCG0_MASK)
#define CCM_CCPGR1_PPCG1_MASK                    0xCu
#define CCM_CCPGR1_PPCG1_SHIFT                   2
#define CCM_CCPGR1_PPCG1(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG1_SHIFT))&CCM_CCPGR1_PPCG1_MASK)
#define CCM_CCPGR1_PPCG2_MASK                    0x30u
#define CCM_CCPGR1_PPCG2_SHIFT                   4
#define CCM_CCPGR1_PPCG2(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG2_SHIFT))&CCM_CCPGR1_PPCG2_MASK)
#define CCM_CCPGR1_PPCG3_MASK                    0xC0u
#define CCM_CCPGR1_PPCG3_SHIFT                   6
#define CCM_CCPGR1_PPCG3(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG3_SHIFT))&CCM_CCPGR1_PPCG3_MASK)
#define CCM_CCPGR1_PPCG4_MASK                    0x300u
#define CCM_CCPGR1_PPCG4_SHIFT                   8
#define CCM_CCPGR1_PPCG4(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG4_SHIFT))&CCM_CCPGR1_PPCG4_MASK)
#define CCM_CCPGR1_PPCG5_MASK                    0xC00u
#define CCM_CCPGR1_PPCG5_SHIFT                   10
#define CCM_CCPGR1_PPCG5(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG5_SHIFT))&CCM_CCPGR1_PPCG5_MASK)
#define CCM_CCPGR1_PPCG6_MASK                    0x3000u
#define CCM_CCPGR1_PPCG6_SHIFT                   12
#define CCM_CCPGR1_PPCG6(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG6_SHIFT))&CCM_CCPGR1_PPCG6_MASK)
#define CCM_CCPGR1_PPCG7_MASK                    0xC000u
#define CCM_CCPGR1_PPCG7_SHIFT                   14
#define CCM_CCPGR1_PPCG7(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG7_SHIFT))&CCM_CCPGR1_PPCG7_MASK)
#define CCM_CCPGR1_PPCG8_MASK                    0x30000u
#define CCM_CCPGR1_PPCG8_SHIFT                   16
#define CCM_CCPGR1_PPCG8(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG8_SHIFT))&CCM_CCPGR1_PPCG8_MASK)
#define CCM_CCPGR1_PPCG9_MASK                    0xC0000u
#define CCM_CCPGR1_PPCG9_SHIFT                   18
#define CCM_CCPGR1_PPCG9(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG9_SHIFT))&CCM_CCPGR1_PPCG9_MASK)
#define CCM_CCPGR1_PPCG10_MASK                   0x300000u
#define CCM_CCPGR1_PPCG10_SHIFT                  20
#define CCM_CCPGR1_PPCG10(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG10_SHIFT))&CCM_CCPGR1_PPCG10_MASK)
#define CCM_CCPGR1_PPCG11_MASK                   0xC00000u
#define CCM_CCPGR1_PPCG11_SHIFT                  22
#define CCM_CCPGR1_PPCG11(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG11_SHIFT))&CCM_CCPGR1_PPCG11_MASK)
#define CCM_CCPGR1_PPCG12_MASK                   0x3000000u
#define CCM_CCPGR1_PPCG12_SHIFT                  24
#define CCM_CCPGR1_PPCG12(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG12_SHIFT))&CCM_CCPGR1_PPCG12_MASK)
#define CCM_CCPGR1_PPCG13_MASK                   0xC000000u
#define CCM_CCPGR1_PPCG13_SHIFT                  26
#define CCM_CCPGR1_PPCG13(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG13_SHIFT))&CCM_CCPGR1_PPCG13_MASK)
#define CCM_CCPGR1_PPCG14_MASK                   0x30000000u
#define CCM_CCPGR1_PPCG14_SHIFT                  28
#define CCM_CCPGR1_PPCG14(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG14_SHIFT))&CCM_CCPGR1_PPCG14_MASK)
#define CCM_CCPGR1_PPCG15_MASK                   0xC0000000u
#define CCM_CCPGR1_PPCG15_SHIFT                  30
#define CCM_CCPGR1_PPCG15(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR1_PPCG15_SHIFT))&CCM_CCPGR1_PPCG15_MASK)
/* CCPGR2 Bit Fields */
#define CCM_CCPGR2_PPCG0_MASK                    0x3u
#define CCM_CCPGR2_PPCG0_SHIFT                   0
#define CCM_CCPGR2_PPCG0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG0_SHIFT))&CCM_CCPGR2_PPCG0_MASK)
#define CCM_CCPGR2_PPCG1_MASK                    0xCu
#define CCM_CCPGR2_PPCG1_SHIFT                   2
#define CCM_CCPGR2_PPCG1(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG1_SHIFT))&CCM_CCPGR2_PPCG1_MASK)
#define CCM_CCPGR2_PPCG2_MASK                    0x30u
#define CCM_CCPGR2_PPCG2_SHIFT                   4
#define CCM_CCPGR2_PPCG2(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG2_SHIFT))&CCM_CCPGR2_PPCG2_MASK)
#define CCM_CCPGR2_PPCG3_MASK                    0xC0u
#define CCM_CCPGR2_PPCG3_SHIFT                   6
#define CCM_CCPGR2_PPCG3(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG3_SHIFT))&CCM_CCPGR2_PPCG3_MASK)
#define CCM_CCPGR2_PPCG4_MASK                    0x300u
#define CCM_CCPGR2_PPCG4_SHIFT                   8
#define CCM_CCPGR2_PPCG4(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG4_SHIFT))&CCM_CCPGR2_PPCG4_MASK)
#define CCM_CCPGR2_PPCG5_MASK                    0xC00u
#define CCM_CCPGR2_PPCG5_SHIFT                   10
#define CCM_CCPGR2_PPCG5(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG5_SHIFT))&CCM_CCPGR2_PPCG5_MASK)
#define CCM_CCPGR2_PPCG6_MASK                    0x3000u
#define CCM_CCPGR2_PPCG6_SHIFT                   12
#define CCM_CCPGR2_PPCG6(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG6_SHIFT))&CCM_CCPGR2_PPCG6_MASK)
#define CCM_CCPGR2_PPCG7_MASK                    0xC000u
#define CCM_CCPGR2_PPCG7_SHIFT                   14
#define CCM_CCPGR2_PPCG7(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG7_SHIFT))&CCM_CCPGR2_PPCG7_MASK)
#define CCM_CCPGR2_PPCG8_MASK                    0x30000u
#define CCM_CCPGR2_PPCG8_SHIFT                   16
#define CCM_CCPGR2_PPCG8(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG8_SHIFT))&CCM_CCPGR2_PPCG8_MASK)
#define CCM_CCPGR2_PPCG9_MASK                    0xC0000u
#define CCM_CCPGR2_PPCG9_SHIFT                   18
#define CCM_CCPGR2_PPCG9(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG9_SHIFT))&CCM_CCPGR2_PPCG9_MASK)
#define CCM_CCPGR2_PPCG10_MASK                   0x300000u
#define CCM_CCPGR2_PPCG10_SHIFT                  20
#define CCM_CCPGR2_PPCG10(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG10_SHIFT))&CCM_CCPGR2_PPCG10_MASK)
#define CCM_CCPGR2_PPCG11_MASK                   0xC00000u
#define CCM_CCPGR2_PPCG11_SHIFT                  22
#define CCM_CCPGR2_PPCG11(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG11_SHIFT))&CCM_CCPGR2_PPCG11_MASK)
#define CCM_CCPGR2_PPCG12_MASK                   0x3000000u
#define CCM_CCPGR2_PPCG12_SHIFT                  24
#define CCM_CCPGR2_PPCG12(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG12_SHIFT))&CCM_CCPGR2_PPCG12_MASK)
#define CCM_CCPGR2_PPCG13_MASK                   0xC000000u
#define CCM_CCPGR2_PPCG13_SHIFT                  26
#define CCM_CCPGR2_PPCG13(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG13_SHIFT))&CCM_CCPGR2_PPCG13_MASK)
#define CCM_CCPGR2_PPCG14_MASK                   0x30000000u
#define CCM_CCPGR2_PPCG14_SHIFT                  28
#define CCM_CCPGR2_PPCG14(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG14_SHIFT))&CCM_CCPGR2_PPCG14_MASK)
#define CCM_CCPGR2_PPCG15_MASK                   0xC0000000u
#define CCM_CCPGR2_PPCG15_SHIFT                  30
#define CCM_CCPGR2_PPCG15(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR2_PPCG15_SHIFT))&CCM_CCPGR2_PPCG15_MASK)
/* CCPGR3 Bit Fields */
#define CCM_CCPGR3_PPCG0_MASK                    0x3u
#define CCM_CCPGR3_PPCG0_SHIFT                   0
#define CCM_CCPGR3_PPCG0(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG0_SHIFT))&CCM_CCPGR3_PPCG0_MASK)
#define CCM_CCPGR3_PPCG1_MASK                    0xCu
#define CCM_CCPGR3_PPCG1_SHIFT                   2
#define CCM_CCPGR3_PPCG1(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG1_SHIFT))&CCM_CCPGR3_PPCG1_MASK)
#define CCM_CCPGR3_PPCG2_MASK                    0x30u
#define CCM_CCPGR3_PPCG2_SHIFT                   4
#define CCM_CCPGR3_PPCG2(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG2_SHIFT))&CCM_CCPGR3_PPCG2_MASK)
#define CCM_CCPGR3_PPCG3_MASK                    0xC0u
#define CCM_CCPGR3_PPCG3_SHIFT                   6
#define CCM_CCPGR3_PPCG3(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG3_SHIFT))&CCM_CCPGR3_PPCG3_MASK)
#define CCM_CCPGR3_PPCG4_MASK                    0x300u
#define CCM_CCPGR3_PPCG4_SHIFT                   8
#define CCM_CCPGR3_PPCG4(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG4_SHIFT))&CCM_CCPGR3_PPCG4_MASK)
#define CCM_CCPGR3_PPCG5_MASK                    0xC00u
#define CCM_CCPGR3_PPCG5_SHIFT                   10
#define CCM_CCPGR3_PPCG5(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG5_SHIFT))&CCM_CCPGR3_PPCG5_MASK)
#define CCM_CCPGR3_PPCG6_MASK                    0x3000u
#define CCM_CCPGR3_PPCG6_SHIFT                   12
#define CCM_CCPGR3_PPCG6(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG6_SHIFT))&CCM_CCPGR3_PPCG6_MASK)
#define CCM_CCPGR3_PPCG7_MASK                    0xC000u
#define CCM_CCPGR3_PPCG7_SHIFT                   14
#define CCM_CCPGR3_PPCG7(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG7_SHIFT))&CCM_CCPGR3_PPCG7_MASK)
#define CCM_CCPGR3_PPCG8_MASK                    0x30000u
#define CCM_CCPGR3_PPCG8_SHIFT                   16
#define CCM_CCPGR3_PPCG8(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG8_SHIFT))&CCM_CCPGR3_PPCG8_MASK)
#define CCM_CCPGR3_PPCG9_MASK                    0xC0000u
#define CCM_CCPGR3_PPCG9_SHIFT                   18
#define CCM_CCPGR3_PPCG9(x)                      (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG9_SHIFT))&CCM_CCPGR3_PPCG9_MASK)
#define CCM_CCPGR3_PPCG10_MASK                   0x300000u
#define CCM_CCPGR3_PPCG10_SHIFT                  20
#define CCM_CCPGR3_PPCG10(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG10_SHIFT))&CCM_CCPGR3_PPCG10_MASK)
#define CCM_CCPGR3_PPCG11_MASK                   0xC00000u
#define CCM_CCPGR3_PPCG11_SHIFT                  22
#define CCM_CCPGR3_PPCG11(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG11_SHIFT))&CCM_CCPGR3_PPCG11_MASK)
#define CCM_CCPGR3_PPCG12_MASK                   0x3000000u
#define CCM_CCPGR3_PPCG12_SHIFT                  24
#define CCM_CCPGR3_PPCG12(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG12_SHIFT))&CCM_CCPGR3_PPCG12_MASK)
#define CCM_CCPGR3_PPCG13_MASK                   0xC000000u
#define CCM_CCPGR3_PPCG13_SHIFT                  26
#define CCM_CCPGR3_PPCG13(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG13_SHIFT))&CCM_CCPGR3_PPCG13_MASK)
#define CCM_CCPGR3_PPCG14_MASK                   0x30000000u
#define CCM_CCPGR3_PPCG14_SHIFT                  28
#define CCM_CCPGR3_PPCG14(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG14_SHIFT))&CCM_CCPGR3_PPCG14_MASK)
#define CCM_CCPGR3_PPCG15_MASK                   0xC0000000u
#define CCM_CCPGR3_PPCG15_SHIFT                  30
#define CCM_CCPGR3_PPCG15(x)                     (((uint32_t)(((uint32_t)(x))<<CCM_CCPGR3_PPCG15_SHIFT))&CCM_CCPGR3_PPCG15_MASK)

/**
 * @}
 */ /* end of group CCM_Register_Masks */


/* CCM - Peripheral instance base addresses */
/** Peripheral CCM base address */
#define CCM_BASE                                 (0x4006B000u)
/** Peripheral CCM base pointer */
#define CCM                                      ((CCM_Type *)CCM_BASE)
/** Array initializer of CCM peripheral base pointers */
#define CCM_BASES                                { CCM }

/**
 * @}
 */ /* end of group CCM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CMU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CMU_Peripheral_Access_Layer CMU Peripheral Access Layer
 * @{
 */

/** CMU - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSR;                               /**< CMU Control Status Register, offset: 0x0 */
  __I  uint32_t FDR;                               /**< CMU Frequency Display Register, offset: 0x4 */
  __IO uint32_t HFREFR;                            /**< CMU High Frequency Reference Register CLKMN1, offset: 0x8 */
  __IO uint32_t LFREFR;                            /**< CMU Low Frequency Reference Register CLKMN1, offset: 0xC */
  __IO uint32_t ISR;                               /**< CMU Interrupt Status Register, offset: 0x10 */
       uint8_t RESERVED_0[4];
  __IO uint32_t MDR;                               /**< CMU Measurement Duration Register, offset: 0x18 */
} CMU_Type;

/* ----------------------------------------------------------------------------
   -- CMU Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CMU_Register_Masks CMU Register Masks
 * @{
 */

/* CSR Bit Fields */
#define CMU_CSR_CME_MASK                         0x1u
#define CMU_CSR_CME_SHIFT                        0
#define CMU_CSR_RCDIV_MASK                       0x6u
#define CMU_CSR_RCDIV_SHIFT                      1
#define CMU_CSR_RCDIV(x)                         (((uint32_t)(((uint32_t)(x))<<CMU_CSR_RCDIV_SHIFT))&CMU_CSR_RCDIV_MASK)
#define CMU_CSR_CKSEL1_MASK                      0x300u
#define CMU_CSR_CKSEL1_SHIFT                     8
#define CMU_CSR_CKSEL1(x)                        (((uint32_t)(((uint32_t)(x))<<CMU_CSR_CKSEL1_SHIFT))&CMU_CSR_CKSEL1_MASK)
#define CMU_CSR_SFM_MASK                         0x800000u
#define CMU_CSR_SFM_SHIFT                        23
/* FDR Bit Fields */
#define CMU_FDR_FD_MASK                          0xFFFFFu
#define CMU_FDR_FD_SHIFT                         0
#define CMU_FDR_FD(x)                            (((uint32_t)(((uint32_t)(x))<<CMU_FDR_FD_SHIFT))&CMU_FDR_FD_MASK)
/* HFREFR Bit Fields */
#define CMU_HFREFR_HFREF_MASK                    0xFFFu
#define CMU_HFREFR_HFREF_SHIFT                   0
#define CMU_HFREFR_HFREF(x)                      (((uint32_t)(((uint32_t)(x))<<CMU_HFREFR_HFREF_SHIFT))&CMU_HFREFR_HFREF_MASK)
/* LFREFR Bit Fields */
#define CMU_LFREFR_LFREF_MASK                    0xFFFu
#define CMU_LFREFR_LFREF_SHIFT                   0
#define CMU_LFREFR_LFREF(x)                      (((uint32_t)(((uint32_t)(x))<<CMU_LFREFR_LFREF_SHIFT))&CMU_LFREFR_LFREF_MASK)
/* ISR Bit Fields */
#define CMU_ISR_OLRI_MASK                        0x1u
#define CMU_ISR_OLRI_SHIFT                       0
#define CMU_ISR_FLLI_MASK                        0x2u
#define CMU_ISR_FLLI_SHIFT                       1
#define CMU_ISR_FHHI_MASK                        0x4u
#define CMU_ISR_FHHI_SHIFT                       2
#define CMU_ISR_FLCI_MASK                        0x8u
#define CMU_ISR_FLCI_SHIFT                       3
/* MDR Bit Fields */
#define CMU_MDR_MD_MASK                          0xFFFFFu
#define CMU_MDR_MD_SHIFT                         0
#define CMU_MDR_MD(x)                            (((uint32_t)(((uint32_t)(x))<<CMU_MDR_MD_SHIFT))&CMU_MDR_MD_MASK)

/**
 * @}
 */ /* end of group CMU_Register_Masks */


/* CMU - Peripheral instance base addresses */
/** Peripheral CMU base address */
#define CMU_BASE                                 (0x4006F000u)
/** Peripheral CMU base pointer */
#define CMU                                      ((CMU_Type *)CMU_BASE)
/** Array initializer of CMU peripheral base pointers */
#define CMU_BASES                                { CMU }

/**
 * @}
 */ /* end of group CMU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
 * @{
 */

/** CRC - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    struct {                                         /* offset: 0x0 */
      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
    } ACCESS16BIT;
    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
    struct {                                         /* offset: 0x0 */
      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
    } ACCESS8BIT;
  };
  union {                                          /* offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
    } GPOLY_ACCESS16BIT;
    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
    struct {                                         /* offset: 0x4 */
      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
    } GPOLY_ACCESS8BIT;
  };
  union {                                          /* offset: 0x8 */
    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
    struct {                                         /* offset: 0x8 */
           uint8_t RESERVED_0[3];
      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
    } CTRL_ACCESS8BIT;
  };
} CRC_Type;

/* ----------------------------------------------------------------------------
   -- CRC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CRC_Register_Masks CRC Register Masks
 * @{
 */

/* DATAL Bit Fields */
#define CRC_DATAL_CRCL_MASK                      0xFFFFu
#define CRC_DATAL_CRCL_SHIFT                     0
#define CRC_DATAL_CRCL(x)                        (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_CRCL_SHIFT))&CRC_DATAL_CRCL_MASK)
/* DATAH Bit Fields */
#define CRC_DATAH_CRCH_MASK                      0xFFFFu
#define CRC_DATAH_CRCH_SHIFT                     0
#define CRC_DATAH_CRCH(x)                        (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_CRCH_SHIFT))&CRC_DATAH_CRCH_MASK)
/* DATA Bit Fields */
#define CRC_DATA_LL_MASK                         0xFFu
#define CRC_DATA_LL_SHIFT                        0
#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
#define CRC_DATA_LU_MASK                         0xFF00u
#define CRC_DATA_LU_SHIFT                        8
#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
#define CRC_DATA_HL_MASK                         0xFF0000u
#define CRC_DATA_HL_SHIFT                        16
#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
#define CRC_DATA_HU_MASK                         0xFF000000u
#define CRC_DATA_HU_SHIFT                        24
#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
/* DATALL Bit Fields */
#define CRC_DATALL_CRCLL_MASK                    0xFFu
#define CRC_DATALL_CRCLL_SHIFT                   0
#define CRC_DATALL_CRCLL(x)                      (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_CRCLL_SHIFT))&CRC_DATALL_CRCLL_MASK)
/* DATALU Bit Fields */
#define CRC_DATALU_CRCLU_MASK                    0xFFu
#define CRC_DATALU_CRCLU_SHIFT                   0
#define CRC_DATALU_CRCLU(x)                      (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_CRCLU_SHIFT))&CRC_DATALU_CRCLU_MASK)
/* DATAHL Bit Fields */
#define CRC_DATAHL_CRCHL_MASK                    0xFFu
#define CRC_DATAHL_CRCHL_SHIFT                   0
#define CRC_DATAHL_CRCHL(x)                      (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_CRCHL_SHIFT))&CRC_DATAHL_CRCHL_MASK)
/* DATAHU Bit Fields */
#define CRC_DATAHU_CRCHU_MASK                    0xFFu
#define CRC_DATAHU_CRCHU_SHIFT                   0
#define CRC_DATAHU_CRCHU(x)                      (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_CRCHU_SHIFT))&CRC_DATAHU_CRCHU_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT                  0
#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT                  0
#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK                       0xFFFFu
#define CRC_GPOLY_LOW_SHIFT                      0
#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT                     16
#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK                       0x1000000u
#define CRC_CTRL_TCRC_SHIFT                      24
#define CRC_CTRL_WAS_MASK                        0x2000000u
#define CRC_CTRL_WAS_SHIFT                       25
#define CRC_CTRL_FXOR_MASK                       0x4000000u
#define CRC_CTRL_FXOR_SHIFT                      26
#define CRC_CTRL_TOTR_MASK                       0x30000000u
#define CRC_CTRL_TOTR_SHIFT                      28
#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK                        0xC0000000u
#define CRC_CTRL_TOT_SHIFT                       30
#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK                     0x1u
#define CRC_CTRLHU_TCRC_SHIFT                    0
#define CRC_CTRLHU_WAS_MASK                      0x2u
#define CRC_CTRLHU_WAS_SHIFT                     1
#define CRC_CTRLHU_FXOR_MASK                     0x4u
#define CRC_CTRLHU_FXOR_SHIFT                    2
#define CRC_CTRLHU_TOTR_MASK                     0x30u
#define CRC_CTRLHU_TOTR_SHIFT                    4
#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK                      0xC0u
#define CRC_CTRLHU_TOT_SHIFT                     6
#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)

/**
 * @}
 */ /* end of group CRC_Register_Masks */


/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE                                 (0x40033000u)
/** Peripheral CRC base pointer */
#define CRC                                      ((CRC_Type *)CRC_BASE)
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASES                                { CRC }

/**
 * @}
 */ /* end of group CRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CSU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
 * @{
 */

/** CSU - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSL[64];                           /**< Config Security Level, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[256];
  __IO uint32_t HP[2];                             /**< Hprot Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_1[16];
  __IO uint32_t SA[2];                             /**< Secure Access register, array offset: 0x218, array step: 0x4 */
       uint8_t RESERVED_2[16];
  __IO uint32_t AMK[2];                            /**< Alarm Mask register, array offset: 0x230, array step: 0x4 */
       uint8_t RESERVED_3[12];
  __IO uint32_t AROUT[13];                         /**< Alarm Routing Register, array offset: 0x244, array step: 0x4 */
       uint8_t RESERVED_4[204];
  __IO uint8_t ASOFT;                              /**< Soft Alarm Register, offset: 0x344 */
       uint8_t RESERVED_5[3];
  __IO uint16_t ACOUNTER;                          /**< Alarm Counter Register, offset: 0x348 */
       uint8_t RESERVED_6[2];
  __IO uint16_t ACONTROL;                          /**< Alarm Control Register, offset: 0x34C */
       uint8_t RESERVED_7[10];
  __IO uint32_t HPC[2];                            /**< Hprot Control Register, array offset: 0x358, array step: 0x4 */
       uint8_t RESERVED_8[8];
  __IO uint32_t ICR[2];                            /**< Interrupt Control Register, array offset: 0x368, array step: 0x4 */
       uint8_t RESERVED_9[8];
  __IO uint32_t ISR[2];                            /**< Interrupt Status Register, array offset: 0x378, array step: 0x4 */
} CSU_Type;

/* ----------------------------------------------------------------------------
   -- CSU Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup CSU_Register_Masks CSU Register Masks
 * @{
 */

/* CSL Bit Fields */
#define CSU_CSL_CSL_2n_MASK                      0xFFu
#define CSU_CSL_CSL_2n_SHIFT                     0
#define CSU_CSL_CSL_2n(x)                        (((uint32_t)(((uint32_t)(x))<<CSU_CSL_CSL_2n_SHIFT))&CSU_CSL_CSL_2n_MASK)
#define CSU_CSL_L_2n_MASK                        0x100u
#define CSU_CSL_L_2n_SHIFT                       8
#define CSU_CSL_CSL_2n1_MASK                     0xFF0000u
#define CSU_CSL_CSL_2n1_SHIFT                    16
#define CSU_CSL_CSL_2n1(x)                       (((uint32_t)(((uint32_t)(x))<<CSU_CSL_CSL_2n1_SHIFT))&CSU_CSL_CSL_2n1_MASK)
#define CSU_CSL_L_2n1_MASK                       0x1000000u
#define CSU_CSL_L_2n1_SHIFT                      24
/* HP Bit Fields */
#define CSU_HP_HP0_n_MASK                        0x1u
#define CSU_HP_HP0_n_SHIFT                       0
#define CSU_HP_L0_n_MASK                         0x2u
#define CSU_HP_L0_n_SHIFT                        1
#define CSU_HP_HP1_n_MASK                        0x4u
#define CSU_HP_HP1_n_SHIFT                       2
#define CSU_HP_L1_n_MASK                         0x8u
#define CSU_HP_L1_n_SHIFT                        3
#define CSU_HP_HP2_n_MASK                        0x10u
#define CSU_HP_HP2_n_SHIFT                       4
#define CSU_HP_L2_n_MASK                         0x20u
#define CSU_HP_L2_n_SHIFT                        5
#define CSU_HP_HP3_n_MASK                        0x40u
#define CSU_HP_HP3_n_SHIFT                       6
#define CSU_HP_L3_n_MASK                         0x80u
#define CSU_HP_L3_n_SHIFT                        7
#define CSU_HP_HP4_n_MASK                        0x100u
#define CSU_HP_HP4_n_SHIFT                       8
#define CSU_HP_L4_n_MASK                         0x200u
#define CSU_HP_L4_n_SHIFT                        9
#define CSU_HP_HP5_n_MASK                        0x400u
#define CSU_HP_HP5_n_SHIFT                       10
#define CSU_HP_L5_n_MASK                         0x800u
#define CSU_HP_L5_n_SHIFT                        11
#define CSU_HP_HP6_n_MASK                        0x1000u
#define CSU_HP_HP6_n_SHIFT                       12
#define CSU_HP_L6_n_MASK                         0x2000u
#define CSU_HP_L6_n_SHIFT                        13
#define CSU_HP_HP7_n_MASK                        0x4000u
#define CSU_HP_HP7_n_SHIFT                       14
#define CSU_HP_L7_n_MASK                         0x8000u
#define CSU_HP_L7_n_SHIFT                        15
#define CSU_HP_HP8_n_MASK                        0x10000u
#define CSU_HP_HP8_n_SHIFT                       16
#define CSU_HP_L8_n_MASK                         0x20000u
#define CSU_HP_L8_n_SHIFT                        17
#define CSU_HP_HP9_n_MASK                        0x40000u
#define CSU_HP_HP9_n_SHIFT                       18
#define CSU_HP_L9_n_MASK                         0x80000u
#define CSU_HP_L9_n_SHIFT                        19
#define CSU_HP_HP10_n_MASK                       0x100000u
#define CSU_HP_HP10_n_SHIFT                      20
#define CSU_HP_L10_n_MASK                        0x200000u
#define CSU_HP_L10_n_SHIFT                       21
#define CSU_HP_HP11_n_MASK                       0x400000u
#define CSU_HP_HP11_n_SHIFT                      22
#define CSU_HP_L11_n_MASK                        0x800000u
#define CSU_HP_L11_n_SHIFT                       23
#define CSU_HP_HP12_n_MASK                       0x1000000u
#define CSU_HP_HP12_n_SHIFT                      24
#define CSU_HP_L12_n_MASK                        0x2000000u
#define CSU_HP_L12_n_SHIFT                       25
#define CSU_HP_HP13_n_MASK                       0x4000000u
#define CSU_HP_HP13_n_SHIFT                      26
#define CSU_HP_L13_n_MASK                        0x8000000u
#define CSU_HP_L13_n_SHIFT                       27
#define CSU_HP_HP14_n_MASK                       0x10000000u
#define CSU_HP_HP14_n_SHIFT                      28
#define CSU_HP_L14_n_MASK                        0x20000000u
#define CSU_HP_L14_n_SHIFT                       29
#define CSU_HP_HP15_n_MASK                       0x40000000u
#define CSU_HP_HP15_n_SHIFT                      30
#define CSU_HP_L15_n_MASK                        0x80000000u
#define CSU_HP_L15_n_SHIFT                       31
/* SA Bit Fields */
#define CSU_SA_SA0_n_MASK                        0x1u
#define CSU_SA_SA0_n_SHIFT                       0
#define CSU_SA_L0_n_MASK                         0x2u
#define CSU_SA_L0_n_SHIFT                        1
#define CSU_SA_SA1_n_MASK                        0x4u
#define CSU_SA_SA1_n_SHIFT                       2
#define CSU_SA_L1_n_MASK                         0x8u
#define CSU_SA_L1_n_SHIFT                        3
#define CSU_SA_SA2_n_MASK                        0x10u
#define CSU_SA_SA2_n_SHIFT                       4
#define CSU_SA_L2_n_MASK                         0x20u
#define CSU_SA_L2_n_SHIFT                        5
#define CSU_SA_SA3_n_MASK                        0x40u
#define CSU_SA_SA3_n_SHIFT                       6
#define CSU_SA_L3_n_MASK                         0x80u
#define CSU_SA_L3_n_SHIFT                        7
#define CSU_SA_SA4_n_MASK                        0x100u
#define CSU_SA_SA4_n_SHIFT                       8
#define CSU_SA_L4_n_MASK                         0x200u
#define CSU_SA_L4_n_SHIFT                        9
#define CSU_SA_SA5_n_MASK                        0x400u
#define CSU_SA_SA5_n_SHIFT                       10
#define CSU_SA_L5_n_MASK                         0x800u
#define CSU_SA_L5_n_SHIFT                        11
#define CSU_SA_SA6_n_MASK                        0x1000u
#define CSU_SA_SA6_n_SHIFT                       12
#define CSU_SA_L6_n_MASK                         0x2000u
#define CSU_SA_L6_n_SHIFT                        13
#define CSU_SA_SA7_n_MASK                        0x4000u
#define CSU_SA_SA7_n_SHIFT                       14
#define CSU_SA_L7_n_MASK                         0x8000u
#define CSU_SA_L7_n_SHIFT                        15
#define CSU_SA_SA8_n_MASK                        0x10000u
#define CSU_SA_SA8_n_SHIFT                       16
#define CSU_SA_L8_n_MASK                         0x20000u
#define CSU_SA_L8_n_SHIFT                        17
#define CSU_SA_SA9_n_MASK                        0x40000u
#define CSU_SA_SA9_n_SHIFT                       18
#define CSU_SA_L9_n_MASK                         0x80000u
#define CSU_SA_L9_n_SHIFT                        19
#define CSU_SA_SA10_n_MASK                       0x100000u
#define CSU_SA_SA10_n_SHIFT                      20
#define CSU_SA_L10_n_MASK                        0x200000u
#define CSU_SA_L10_n_SHIFT                       21
#define CSU_SA_SA11_n_MASK                       0x400000u
#define CSU_SA_SA11_n_SHIFT                      22
#define CSU_SA_L11_n_MASK                        0x800000u
#define CSU_SA_L11_n_SHIFT                       23
#define CSU_SA_SA12_n_MASK                       0x1000000u
#define CSU_SA_SA12_n_SHIFT                      24
#define CSU_SA_L12_n_MASK                        0x2000000u
#define CSU_SA_L12_n_SHIFT                       25
#define CSU_SA_SA13_n_MASK                       0x4000000u
#define CSU_SA_SA13_n_SHIFT                      26
#define CSU_SA_L13_n_MASK                        0x8000000u
#define CSU_SA_L13_n_SHIFT                       27
#define CSU_SA_SA14_n_MASK                       0x10000000u
#define CSU_SA_SA14_n_SHIFT                      28
#define CSU_SA_L14_n_MASK                        0x20000000u
#define CSU_SA_L14_n_SHIFT                       29
#define CSU_SA_SA15_n_MASK                       0x40000000u
#define CSU_SA_SA15_n_SHIFT                      30
#define CSU_SA_L15_n_MASK                        0x80000000u
#define CSU_SA_L15_n_SHIFT                       31
/* AMK Bit Fields */
#define CSU_AMK_AMK0_n_MASK                      0x1u
#define CSU_AMK_AMK0_n_SHIFT                     0
#define CSU_AMK_L0_n_MASK                        0x2u
#define CSU_AMK_L0_n_SHIFT                       1
#define CSU_AMK_AMK1_n_MASK                      0x4u
#define CSU_AMK_AMK1_n_SHIFT                     2
#define CSU_AMK_L1_n_MASK                        0x8u
#define CSU_AMK_L1_n_SHIFT                       3
#define CSU_AMK_AMK2_n_MASK                      0x10u
#define CSU_AMK_AMK2_n_SHIFT                     4
#define CSU_AMK_L2_n_MASK                        0x20u
#define CSU_AMK_L2_n_SHIFT                       5
#define CSU_AMK_AMK3_n_MASK                      0x40u
#define CSU_AMK_AMK3_n_SHIFT                     6
#define CSU_AMK_L3_n_MASK                        0x80u
#define CSU_AMK_L3_n_SHIFT                       7
#define CSU_AMK_AMK4_n_MASK                      0x100u
#define CSU_AMK_AMK4_n_SHIFT                     8
#define CSU_AMK_L4_n_MASK                        0x200u
#define CSU_AMK_L4_n_SHIFT                       9
#define CSU_AMK_AMK5_n_MASK                      0x400u
#define CSU_AMK_AMK5_n_SHIFT                     10
#define CSU_AMK_L5_n_MASK                        0x800u
#define CSU_AMK_L5_n_SHIFT                       11
#define CSU_AMK_AMK6_n_MASK                      0x1000u
#define CSU_AMK_AMK6_n_SHIFT                     12
#define CSU_AMK_L6_n_MASK                        0x2000u
#define CSU_AMK_L6_n_SHIFT                       13
#define CSU_AMK_AMK7_n_MASK                      0x4000u
#define CSU_AMK_AMK7_n_SHIFT                     14
#define CSU_AMK_L7_n_MASK                        0x8000u
#define CSU_AMK_L7_n_SHIFT                       15
#define CSU_AMK_AMK8_n_MASK                      0x10000u
#define CSU_AMK_AMK8_n_SHIFT                     16
#define CSU_AMK_L8_n_MASK                        0x20000u
#define CSU_AMK_L8_n_SHIFT                       17
#define CSU_AMK_AMK9_n_MASK                      0x40000u
#define CSU_AMK_AMK9_n_SHIFT                     18
#define CSU_AMK_L9_n_MASK                        0x80000u
#define CSU_AMK_L9_n_SHIFT                       19
#define CSU_AMK_AMK10_n_MASK                     0x100000u
#define CSU_AMK_AMK10_n_SHIFT                    20
#define CSU_AMK_L10_n_MASK                       0x200000u
#define CSU_AMK_L10_n_SHIFT                      21
#define CSU_AMK_AMK11_n_MASK                     0x400000u
#define CSU_AMK_AMK11_n_SHIFT                    22
#define CSU_AMK_L11_n_MASK                       0x800000u
#define CSU_AMK_L11_n_SHIFT                      23
#define CSU_AMK_AMK12_n_MASK                     0x1000000u
#define CSU_AMK_AMK12_n_SHIFT                    24
#define CSU_AMK_L12_n_MASK                       0x2000000u
#define CSU_AMK_L12_n_SHIFT                      25
#define CSU_AMK_AMK13_n_MASK                     0x4000000u
#define CSU_AMK_AMK13_n_SHIFT                    26
#define CSU_AMK_L13_n_MASK                       0x8000000u
#define CSU_AMK_L13_n_SHIFT                      27
#define CSU_AMK_AMK14_n_MASK                     0x10000000u
#define CSU_AMK_AMK14_n_SHIFT                    28
#define CSU_AMK_L14_n_MASK                       0x20000000u
#define CSU_AMK_L14_n_SHIFT                      29
#define CSU_AMK_AMK15_n_MASK                     0x40000000u
#define CSU_AMK_AMK15_n_SHIFT                    30
#define CSU_AMK_L15_n_MASK                       0x80000000u
#define CSU_AMK_L15_n_SHIFT                      31
/* AROUT Bit Fields */
#define CSU_AROUT_AROUT_n_MASK                   0x7FFFFFFFu
#define CSU_AROUT_AROUT_n_SHIFT                  0
#define CSU_AROUT_AROUT_n(x)                     (((uint32_t)(((uint32_t)(x))<<CSU_AROUT_AROUT_n_SHIFT))&CSU_AROUT_AROUT_n_MASK)
#define CSU_AROUT_L_n_MASK                       0x80000000u
#define CSU_AROUT_L_n_SHIFT                      31
/* ASOFT Bit Fields */
#define CSU_ASOFT_NALARM_MASK                    0x3u
#define CSU_ASOFT_NALARM_SHIFT                   0
#define CSU_ASOFT_NALARM(x)                      (((uint8_t)(((uint8_t)(x))<<CSU_ASOFT_NALARM_SHIFT))&CSU_ASOFT_NALARM_MASK)
#define CSU_ASOFT_SALARM_MASK                    0xCu
#define CSU_ASOFT_SALARM_SHIFT                   2
#define CSU_ASOFT_SALARM(x)                      (((uint8_t)(((uint8_t)(x))<<CSU_ASOFT_SALARM_SHIFT))&CSU_ASOFT_SALARM_MASK)
#define CSU_ASOFT_L_MASK                         0x10u
#define CSU_ASOFT_L_SHIFT                        4
/* ACOUNTER Bit Fields */
#define CSU_ACOUNTER_ACOUNTER_MASK               0x7FFFu
#define CSU_ACOUNTER_ACOUNTER_SHIFT              0
#define CSU_ACOUNTER_ACOUNTER(x)                 (((uint16_t)(((uint16_t)(x))<<CSU_ACOUNTER_ACOUNTER_SHIFT))&CSU_ACOUNTER_ACOUNTER_MASK)
#define CSU_ACOUNTER_L_MASK                      0x8000u
#define CSU_ACOUNTER_L_SHIFT                     15
/* ACONTROL Bit Fields */
#define CSU_ACONTROL_CE_MASK                     0x1u
#define CSU_ACONTROL_CE_SHIFT                    0
#define CSU_ACONTROL_SC_MASK                     0x2u
#define CSU_ACONTROL_SC_SHIFT                    1
#define CSU_ACONTROL_L_MASK                      0x4u
#define CSU_ACONTROL_L_SHIFT                     2
/* HPC Bit Fields */
#define CSU_HPC_HPC0_n_MASK                      0x1u
#define CSU_HPC_HPC0_n_SHIFT                     0
#define CSU_HPC_L0_n_MASK                        0x2u
#define CSU_HPC_L0_n_SHIFT                       1
#define CSU_HPC_HPC1_n_MASK                      0x4u
#define CSU_HPC_HPC1_n_SHIFT                     2
#define CSU_HPC_L1_n_MASK                        0x8u
#define CSU_HPC_L1_n_SHIFT                       3
#define CSU_HPC_HPC2_n_MASK                      0x10u
#define CSU_HPC_HPC2_n_SHIFT                     4
#define CSU_HPC_L2_n_MASK                        0x20u
#define CSU_HPC_L2_n_SHIFT                       5
#define CSU_HPC_HPC3_n_MASK                      0x40u
#define CSU_HPC_HPC3_n_SHIFT                     6
#define CSU_HPC_L3_n_MASK                        0x80u
#define CSU_HPC_L3_n_SHIFT                       7
#define CSU_HPC_HPC4_n_MASK                      0x100u
#define CSU_HPC_HPC4_n_SHIFT                     8
#define CSU_HPC_L4_n_MASK                        0x200u
#define CSU_HPC_L4_n_SHIFT                       9
#define CSU_HPC_HPC5_n_MASK                      0x400u
#define CSU_HPC_HPC5_n_SHIFT                     10
#define CSU_HPC_L5_n_MASK                        0x800u
#define CSU_HPC_L5_n_SHIFT                       11
#define CSU_HPC_HPC6_n_MASK                      0x1000u
#define CSU_HPC_HPC6_n_SHIFT                     12
#define CSU_HPC_L6_n_MASK                        0x2000u
#define CSU_HPC_L6_n_SHIFT                       13
#define CSU_HPC_HPC7_n_MASK                      0x4000u
#define CSU_HPC_HPC7_n_SHIFT                     14
#define CSU_HPC_L7_n_MASK                        0x8000u
#define CSU_HPC_L7_n_SHIFT                       15
#define CSU_HPC_HPC8_n_MASK                      0x10000u
#define CSU_HPC_HPC8_n_SHIFT                     16
#define CSU_HPC_L8_n_MASK                        0x20000u
#define CSU_HPC_L8_n_SHIFT                       17
#define CSU_HPC_HPC9_n_MASK                      0x40000u
#define CSU_HPC_HPC9_n_SHIFT                     18
#define CSU_HPC_L9_n_MASK                        0x80000u
#define CSU_HPC_L9_n_SHIFT                       19
#define CSU_HPC_HPC10_n_MASK                     0x100000u
#define CSU_HPC_HPC10_n_SHIFT                    20
#define CSU_HPC_L10_n_MASK                       0x200000u
#define CSU_HPC_L10_n_SHIFT                      21
#define CSU_HPC_HPC11_n_MASK                     0x400000u
#define CSU_HPC_HPC11_n_SHIFT                    22
#define CSU_HPC_L11_n_MASK                       0x800000u
#define CSU_HPC_L11_n_SHIFT                      23
#define CSU_HPC_HPC12_n_MASK                     0x1000000u
#define CSU_HPC_HPC12_n_SHIFT                    24
#define CSU_HPC_L12_n_MASK                       0x2000000u
#define CSU_HPC_L12_n_SHIFT                      25
#define CSU_HPC_HPC13_n_MASK                     0x4000000u
#define CSU_HPC_HPC13_n_SHIFT                    26
#define CSU_HPC_L13_n_MASK                       0x8000000u
#define CSU_HPC_L13_n_SHIFT                      27
#define CSU_HPC_HPC14_n_MASK                     0x10000000u
#define CSU_HPC_HPC14_n_SHIFT                    28
#define CSU_HPC_L14_n_MASK                       0x20000000u
#define CSU_HPC_L14_n_SHIFT                      29
#define CSU_HPC_HPC15_n_MASK                     0x40000000u
#define CSU_HPC_HPC15_n_SHIFT                    30
#define CSU_HPC_L15_n_MASK                       0x80000000u
#define CSU_HPC_L15_n_SHIFT                      31
/* ICR Bit Fields */
#define CSU_ICR_IC0_n_MASK                       0x1u
#define CSU_ICR_IC0_n_SHIFT                      0
#define CSU_ICR_L0_n_MASK                        0x2u
#define CSU_ICR_L0_n_SHIFT                       1
#define CSU_ICR_IC1_n_MASK                       0x4u
#define CSU_ICR_IC1_n_SHIFT                      2
#define CSU_ICR_L1_n_MASK                        0x8u
#define CSU_ICR_L1_n_SHIFT                       3
#define CSU_ICR_IC2_n_MASK                       0x10u
#define CSU_ICR_IC2_n_SHIFT                      4
#define CSU_ICR_L2_n_MASK                        0x20u
#define CSU_ICR_L2_n_SHIFT                       5
#define CSU_ICR_IC3_n_MASK                       0x40u
#define CSU_ICR_IC3_n_SHIFT                      6
#define CSU_ICR_L3_n_MASK                        0x80u
#define CSU_ICR_L3_n_SHIFT                       7
#define CSU_ICR_IC4_n_MASK                       0x100u
#define CSU_ICR_IC4_n_SHIFT                      8
#define CSU_ICR_L4_n_MASK                        0x200u
#define CSU_ICR_L4_n_SHIFT                       9
#define CSU_ICR_IC5_n_MASK                       0x400u
#define CSU_ICR_IC5_n_SHIFT                      10
#define CSU_ICR_L5_n_MASK                        0x800u
#define CSU_ICR_L5_n_SHIFT                       11
#define CSU_ICR_IC6_n_MASK                       0x1000u
#define CSU_ICR_IC6_n_SHIFT                      12
#define CSU_ICR_L6_n_MASK                        0x2000u
#define CSU_ICR_L6_n_SHIFT                       13
#define CSU_ICR_IC7_n_MASK                       0x4000u
#define CSU_ICR_IC7_n_SHIFT                      14
#define CSU_ICR_L7_n_MASK                        0x8000u
#define CSU_ICR_L7_n_SHIFT                       15
#define CSU_ICR_IC8_n_MASK                       0x10000u
#define CSU_ICR_IC8_n_SHIFT                      16
#define CSU_ICR_L8_n_MASK                        0x20000u
#define CSU_ICR_L8_n_SHIFT                       17
#define CSU_ICR_IC9_n_MASK                       0x40000u
#define CSU_ICR_IC9_n_SHIFT                      18
#define CSU_ICR_L9_n_MASK                        0x80000u
#define CSU_ICR_L9_n_SHIFT                       19
#define CSU_ICR_IC10_n_MASK                      0x100000u
#define CSU_ICR_IC10_n_SHIFT                     20
#define CSU_ICR_L10_n_MASK                       0x200000u
#define CSU_ICR_L10_n_SHIFT                      21
#define CSU_ICR_IC11_n_MASK                      0x400000u
#define CSU_ICR_IC11_n_SHIFT                     22
#define CSU_ICR_L11_n_MASK                       0x800000u
#define CSU_ICR_L11_n_SHIFT                      23
#define CSU_ICR_IC12_n_MASK                      0x1000000u
#define CSU_ICR_IC12_n_SHIFT                     24
#define CSU_ICR_L12_n_MASK                       0x2000000u
#define CSU_ICR_L12_n_SHIFT                      25
#define CSU_ICR_IC13_n_MASK                      0x4000000u
#define CSU_ICR_IC13_n_SHIFT                     26
#define CSU_ICR_L13_n_MASK                       0x8000000u
#define CSU_ICR_L13_n_SHIFT                      27
#define CSU_ICR_IC14_n_MASK                      0x10000000u
#define CSU_ICR_IC14_n_SHIFT                     28
#define CSU_ICR_L14_n_MASK                       0x20000000u
#define CSU_ICR_L14_n_SHIFT                      29
#define CSU_ICR_IC15_n_MASK                      0x40000000u
#define CSU_ICR_IC15_n_SHIFT                     30
#define CSU_ICR_L15_n_MASK                       0x80000000u
#define CSU_ICR_L15_n_SHIFT                      31
/* ISR Bit Fields */
#define CSU_ISR_IS0_n_MASK                       0x1u
#define CSU_ISR_IS0_n_SHIFT                      0
#define CSU_ISR_IS1_n_MASK                       0x4u
#define CSU_ISR_IS1_n_SHIFT                      2
#define CSU_ISR_IS2_n_MASK                       0x10u
#define CSU_ISR_IS2_n_SHIFT                      4
#define CSU_ISR_IS3_n_MASK                       0x40u
#define CSU_ISR_IS3_n_SHIFT                      6
#define CSU_ISR_IS4_n_MASK                       0x100u
#define CSU_ISR_IS4_n_SHIFT                      8
#define CSU_ISR_IS5_n_MASK                       0x400u
#define CSU_ISR_IS5_n_SHIFT                      10
#define CSU_ISR_IS6_n_MASK                       0x1000u
#define CSU_ISR_IS6_n_SHIFT                      12
#define CSU_ISR_IS7_n_MASK                       0x4000u
#define CSU_ISR_IS7_n_SHIFT                      14
#define CSU_ISR_IS8_n_MASK                       0x10000u
#define CSU_ISR_IS8_n_SHIFT                      16
#define CSU_ISR_IS9_n_MASK                       0x40000u
#define CSU_ISR_IS9_n_SHIFT                      18
#define CSU_ISR_IS10_n_MASK                      0x100000u
#define CSU_ISR_IS10_n_SHIFT                     20
#define CSU_ISR_IS11_n_MASK                      0x400000u
#define CSU_ISR_IS11_n_SHIFT                     22
#define CSU_ISR_IS12_n_MASK                      0x1000000u
#define CSU_ISR_IS12_n_SHIFT                     24
#define CSU_ISR_IS13_n_MASK                      0x4000000u
#define CSU_ISR_IS13_n_SHIFT                     26
#define CSU_ISR_IS14_n_MASK                      0x10000000u
#define CSU_ISR_IS14_n_SHIFT                     28
#define CSU_ISR_IS15_n_MASK                      0x40000000u
#define CSU_ISR_IS15_n_SHIFT                     30

/**
 * @}
 */ /* end of group CSU_Register_Masks */


/* CSU - Peripheral instance base addresses */
/** Peripheral CSU base address */
#define CSU_BASE                                 (0x40017000u)
/** Peripheral CSU base pointer */
#define CSU                                      ((CSU_Type *)CSU_BASE)
/** Array initializer of CSU peripheral base pointers */
#define CSU_BASES                                { CSU }

/**
 * @}
 */ /* end of group CSU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DAC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
 * @{
 */

/** DAC - Register Layout Typedef */
typedef struct {
  __IO uint16_t DAT[16];                           /**< DAC Data Register, array offset: 0x0, array step: 0x2 */
  __IO uint16_t STATCTRL1;                         /**< DAC Status and Control Register 1, offset: 0x20 */
  __IO uint16_t STATCTRL2;                         /**< DAC Status and Control Register 2, offset: 0x22 */
} DAC_Type;

/* ----------------------------------------------------------------------------
   -- DAC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DAC_Register_Masks DAC Register Masks
 * @{
 */

/* DAT Bit Fields */
#define DAC_DAT_DATA2_MASK                       0xFFu
#define DAC_DAT_DATA2_SHIFT                      0
#define DAC_DAT_DATA2(x)                         (((uint16_t)(((uint16_t)(x))<<DAC_DAT_DATA2_SHIFT))&DAC_DAT_DATA2_MASK)
#define DAC_DAT_DATA3_MASK                       0xF00u
#define DAC_DAT_DATA3_SHIFT                      8
#define DAC_DAT_DATA3(x)                         (((uint16_t)(((uint16_t)(x))<<DAC_DAT_DATA3_SHIFT))&DAC_DAT_DATA3_MASK)
/* STATCTRL1 Bit Fields */
#define DAC_STATCTRL1_DACBFRPBF_MASK             0x1u
#define DAC_STATCTRL1_DACBFRPBF_SHIFT            0
#define DAC_STATCTRL1_DACBFRPTF_MASK             0x2u
#define DAC_STATCTRL1_DACBFRPTF_SHIFT            1
#define DAC_STATCTRL1_DACBFWMF_MASK              0x4u
#define DAC_STATCTRL1_DACBFWMF_SHIFT             2
#define DAC_STATCTRL1_DACBBIEN_MASK              0x100u
#define DAC_STATCTRL1_DACBBIEN_SHIFT             8
#define DAC_STATCTRL1_DACBTIEN_MASK              0x200u
#define DAC_STATCTRL1_DACBTIEN_SHIFT             9
#define DAC_STATCTRL1_DACBWIEN_MASK              0x400u
#define DAC_STATCTRL1_DACBWIEN_SHIFT             10
#define DAC_STATCTRL1_LPEN_MASK                  0x800u
#define DAC_STATCTRL1_LPEN_SHIFT                 11
#define DAC_STATCTRL1_DACSWTRG_MASK              0x1000u
#define DAC_STATCTRL1_DACSWTRG_SHIFT             12
#define DAC_STATCTRL1_DACTRGSEL_MASK             0x2000u
#define DAC_STATCTRL1_DACTRGSEL_SHIFT            13
#define DAC_STATCTRL1_DACRFS_MASK                0x4000u
#define DAC_STATCTRL1_DACRFS_SHIFT               14
#define DAC_STATCTRL1_DACEN_MASK                 0x8000u
#define DAC_STATCTRL1_DACEN_SHIFT                15
/* STATCTRL2 Bit Fields */
#define DAC_STATCTRL2_DACBFEN_MASK               0x1u
#define DAC_STATCTRL2_DACBFEN_SHIFT              0
#define DAC_STATCTRL2_DACBFMD_MASK               0x6u
#define DAC_STATCTRL2_DACBFMD_SHIFT              1
#define DAC_STATCTRL2_DACBFMD(x)                 (((uint16_t)(((uint16_t)(x))<<DAC_STATCTRL2_DACBFMD_SHIFT))&DAC_STATCTRL2_DACBFMD_MASK)
#define DAC_STATCTRL2_DACBFWM_MASK               0x18u
#define DAC_STATCTRL2_DACBFWM_SHIFT              3
#define DAC_STATCTRL2_DACBFWM(x)                 (((uint16_t)(((uint16_t)(x))<<DAC_STATCTRL2_DACBFWM_SHIFT))&DAC_STATCTRL2_DACBFWM_MASK)
#define DAC_STATCTRL2_DMAEN_MASK                 0x80u
#define DAC_STATCTRL2_DMAEN_SHIFT                7
#define DAC_STATCTRL2_DACBFUP_MASK               0xF00u
#define DAC_STATCTRL2_DACBFUP_SHIFT              8
#define DAC_STATCTRL2_DACBFUP(x)                 (((uint16_t)(((uint16_t)(x))<<DAC_STATCTRL2_DACBFUP_SHIFT))&DAC_STATCTRL2_DACBFUP_MASK)
#define DAC_STATCTRL2_DACBFRP_MASK               0xF000u
#define DAC_STATCTRL2_DACBFRP_SHIFT              12
#define DAC_STATCTRL2_DACBFRP(x)                 (((uint16_t)(((uint16_t)(x))<<DAC_STATCTRL2_DACBFRP_SHIFT))&DAC_STATCTRL2_DACBFRP_MASK)

/**
 * @}
 */ /* end of group DAC_Register_Masks */


/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base address */
#define DAC0_BASE                                (0x400CC000u)
/** Peripheral DAC0 base pointer */
#define DAC0                                     ((DAC_Type *)DAC0_BASE)
/** Peripheral DAC1 base address */
#define DAC1_BASE                                (0x400CD000u)
/** Peripheral DAC1 base pointer */
#define DAC1                                     ((DAC_Type *)DAC1_BASE)
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASES                                { DAC0, DAC1 }

/**
 * @}
 */ /* end of group DAC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DCU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DCU_Peripheral_Access_Layer DCU Peripheral Access Layer
 * @{
 */

/** DCU - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRLDESCCURSOR1;                   /**< Control Descriptor Cursor 1 Register, offset: 0x0 */
  __IO uint32_t CTRLDESCCURSOR2;                   /**< Control Descriptor Cursor 2 Register, offset: 0x4 */
  __IO uint32_t CTRLDESCCURSOR3;                   /**< Control Descriptor Cursor 3 Register, offset: 0x8 */
  __IO uint32_t CTRLDESCCURSOR4;                   /**< Control Descriptor Cursor 4 Register, offset: 0xC */
  __IO uint32_t DCU_MODE;                          /**< DCU4 Mode Register, offset: 0x10 */
  __IO uint32_t BGND;                              /**< Background Register, offset: 0x14 */
  __IO uint32_t DISP_SIZE;                         /**< Display Size Register, offset: 0x18 */
  __IO uint32_t HSYN_PARA;                         /**< Horizontal Sync Parameter Register, offset: 0x1C */
  __IO uint32_t VSYN_PARA;                         /**< Vertical Sync Parameter Register, offset: 0x20 */
  __IO uint32_t SYNPOL;                            /**< Synchronize Polarity Register, offset: 0x24 */
  __IO uint32_t THRESHOLD;                         /**< Threshold Register, offset: 0x28 */
  __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x2C */
  __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x30 */
  __IO uint32_t COLBAR_1;                          /**< COLBAR_1 Register, offset: 0x34 */
  __IO uint32_t COLBAR_2;                          /**< COLBAR_2 Register, offset: 0x38 */
  __IO uint32_t COLBAR_3;                          /**< COLBAR_3 Register, offset: 0x3C */
  __IO uint32_t COLBAR_4;                          /**< COLBAR_4 Register, offset: 0x40 */
  __IO uint32_t COLBAR_5;                          /**< COLBAR_5 Register, offset: 0x44 */
  __IO uint32_t COLBAR_6;                          /**< COLBAR_6 Register, offset: 0x48 */
  __IO uint32_t COLBAR_7;                          /**< COLBAR_7 Register, offset: 0x4C */
  __IO uint32_t COLBAR_8;                          /**< COLBAR_8 Register, offset: 0x50 */
  __IO uint32_t DIV_RATIO;                         /**< Divide Ratio Register, offset: 0x54 */
  __IO uint32_t SIGN_CALC_1;                       /**< Sign Calculation 1 Register, offset: 0x58 */
  __IO uint32_t SIGN_CALC_2;                       /**< Sign Calculation 2 Register, offset: 0x5C */
  __IO uint32_t CRC_VAL;                           /**< CRC Value Register, offset: 0x60 */
  __IO uint32_t PDI_STATUS;                        /**< PDI Status Register, offset: 0x64 */
  __IO uint32_t PDI_STA_MSK;                       /**< PDI Status Mask Register, offset: 0x68 */
  __IO uint32_t PARR_ERR_STATUS1;                  /**< Parameter Error Status 1 Register, offset: 0x6C */
  __IO uint32_t PARR_ERR_STATUS2;                  /**< Parameter Error Status 2 Register, offset: 0x70 */
       uint8_t RESERVED_0[8];
  __IO uint32_t PARR_ERR_STATUS3;                  /**< Parameter Error Status 3 Register, offset: 0x7C */
  __IO uint32_t MASK_PARR_ERR_STATUS1;             /**< Mask Parameter Error Status 1 Register, offset: 0x80 */
  __IO uint32_t MASK_PARR_ERR_STATUS2;             /**< Mask Parameter Error Status 2 Register, offset: 0x84 */
       uint8_t RESERVED_1[8];
  __IO uint32_t MASK_PARR_ERR_STATUS3;             /**< Mask Parameter Error Status 3 Register, offset: 0x90 */
  __IO uint32_t THRESHOLD_INP_BUF_1;               /**< Threshold Input 1 Register, offset: 0x94 */
  __IO uint32_t THRESHOLD_INP_BUF_2;               /**< Threshold Input 2 Register, offset: 0x98 */
  __IO uint32_t THRESHOLD_INP_BUF_3;               /**< Threshold Input 3 Register, offset: 0x9C */
  __IO uint32_t LUMA_COMP;                         /**< LUMA Component Register, offset: 0xA0 */
  __IO uint32_t CHROMA_RED;                        /**< Red Chroma Components Register, offset: 0xA4 */
  __IO uint32_t CHROMA_GREEN;                      /**< Green Chroma Components Register, offset: 0xA8 */
  __IO uint32_t CHROMA_BLUE;                       /**< Blue Chroma Components Register, offset: 0xAC */
  __IO uint32_t CRC_POS;                           /**< CRC Position Register, offset: 0xB0 */
  __IO uint32_t LYR_INTPOL_EN;                     /**< Layer Interpolation Enable Register, offset: 0xB4 */
  __IO uint32_t LYR_LUMA_COMP;                     /**< Layer Luminance Component Register, offset: 0xB8 */
  __IO uint32_t LYR_CHRM_RED;                      /**< Layer Chroma Red Register, offset: 0xBC */
  __IO uint32_t LYR_CHRM_GRN;                      /**< Layer Chroma Green Register, offset: 0xC0 */
  __IO uint32_t LYR_CHRM_BLUE;                     /**< Layer Chroma Blue Register, offset: 0xC4 */
  __IO uint32_t COMP_IMSIZE;                       /**< Compression Image Size Register, offset: 0xC8 */
  __IO uint32_t UPDATE_MODE;                       /**< Update Mode Register, offset: 0xCC */
  __IO uint32_t UNDERRUN;                          /**< Underrun Register, offset: 0xD0 */
       uint8_t RESERVED_2[300];
  __IO uint32_t CTRLDESCL0_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x200 */
  __IO uint32_t CTRLDESCL0_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x204 */
  __IO uint32_t CTRLDESCL0_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x208 */
  __IO uint32_t CTRLDESCL0_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x20C */
  __IO uint32_t CTRLDESCL0_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x210 */
  __IO uint32_t CTRLDESCL0_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x214 */
  __IO uint32_t CTRLDESCL0_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x218 */
  __IO uint32_t CTRLDESCL0_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x21C */
  __IO uint32_t CTRLDESCL0_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x220 */
       uint8_t RESERVED_3[28];
  __IO uint32_t CTRLDESCL1_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x240 */
  __IO uint32_t CTRLDESCL1_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x244 */
  __IO uint32_t CTRLDESCL1_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x248 */
  __IO uint32_t CTRLDESCL1_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x24C */
  __IO uint32_t CTRLDESCL1_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x250 */
  __IO uint32_t CTRLDESCL1_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x254 */
  __IO uint32_t CTRLDESCL1_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x258 */
  __IO uint32_t CTRLDESCL1_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x25C */
  __IO uint32_t CTRLDESCL1_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x260 */
       uint8_t RESERVED_4[28];
  __IO uint32_t CTRLDESCL2_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x280 */
  __IO uint32_t CTRLDESCL2_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x284 */
  __IO uint32_t CTRLDESCL2_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x288 */
  __IO uint32_t CTRLDESCL2_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x28C */
  __IO uint32_t CTRLDESCL2_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x290 */
  __IO uint32_t CTRLDESCL2_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x294 */
  __IO uint32_t CTRLDESCL2_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x298 */
  __IO uint32_t CTRLDESCL2_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x29C */
  __IO uint32_t CTRLDESCL2_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x2A0 */
       uint8_t RESERVED_5[28];
  __IO uint32_t CTRLDESCL3_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x2C0 */
  __IO uint32_t CTRLDESCL3_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x2C4 */
  __IO uint32_t CTRLDESCL3_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x2C8 */
  __IO uint32_t CTRLDESCL3_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x2CC */
  __IO uint32_t CTRLDESCL3_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x2D0 */
  __IO uint32_t CTRLDESCL3_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x2D4 */
  __IO uint32_t CTRLDESCL3_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x2D8 */
  __IO uint32_t CTRLDESCL3_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x2DC */
  __IO uint32_t CTRLDESCL3_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x2E0 */
       uint8_t RESERVED_6[28];
  __IO uint32_t CTRLDESCL4_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x300 */
  __IO uint32_t CTRLDESCL4_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x304 */
  __IO uint32_t CTRLDESCL4_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x308 */
  __IO uint32_t CTRLDESCL4_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x30C */
  __IO uint32_t CTRLDESCL4_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x310 */
  __IO uint32_t CTRLDESCL4_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x314 */
  __IO uint32_t CTRLDESCL4_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x318 */
  __IO uint32_t CTRLDESCL4_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x31C */
  __IO uint32_t CTRLDESCL4_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x320 */
       uint8_t RESERVED_7[28];
  __IO uint32_t CTRLDESCL5_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x340 */
  __IO uint32_t CTRLDESCL5_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x344 */
  __IO uint32_t CTRLDESCL5_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x348 */
  __IO uint32_t CTRLDESCL5_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x34C */
  __IO uint32_t CTRLDESCL5_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x350 */
  __IO uint32_t CTRLDESCL5_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x354 */
  __IO uint32_t CTRLDESCL5_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x358 */
  __IO uint32_t CTRLDESCL5_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x35C */
  __IO uint32_t CTRLDESCL5_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x360 */
       uint8_t RESERVED_8[28];
  __IO uint32_t CTRLDESCL6_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x380 */
  __IO uint32_t CTRLDESCL6_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x384 */
  __IO uint32_t CTRLDESCL6_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x388 */
  __IO uint32_t CTRLDESCL6_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x38C */
  __IO uint32_t CTRLDESCL6_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x390 */
  __IO uint32_t CTRLDESCL6_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x394 */
  __IO uint32_t CTRLDESCL6_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x398 */
  __IO uint32_t CTRLDESCL6_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x39C */
  __IO uint32_t CTRLDESCL6_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x3A0 */
       uint8_t RESERVED_9[28];
  __IO uint32_t CTRLDESCL7_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x3C0 */
  __IO uint32_t CTRLDESCL7_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x3C4 */
  __IO uint32_t CTRLDESCL7_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x3C8 */
  __IO uint32_t CTRLDESCL7_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x3CC */
  __IO uint32_t CTRLDESCL7_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x3D0 */
  __IO uint32_t CTRLDESCL7_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x3D4 */
  __IO uint32_t CTRLDESCL7_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x3D8 */
  __IO uint32_t CTRLDESCL7_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x3DC */
  __IO uint32_t CTRLDESCL7_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x3E0 */
       uint8_t RESERVED_10[28];
  __IO uint32_t CTRLDESCL8_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x400 */
  __IO uint32_t CTRLDESCL8_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x404 */
  __IO uint32_t CTRLDESCL8_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x408 */
  __IO uint32_t CTRLDESCL8_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x40C */
  __IO uint32_t CTRLDESCL8_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x410 */
  __IO uint32_t CTRLDESCL8_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x414 */
  __IO uint32_t CTRLDESCL8_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x418 */
  __IO uint32_t CTRLDESCL8_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x41C */
  __IO uint32_t CTRLDESCL8_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x420 */
       uint8_t RESERVED_11[28];
  __IO uint32_t CTRLDESCL9_0;                      /**< Control Descriptor Ln_0 Register, offset: 0x440 */
  __IO uint32_t CTRLDESCL9_1;                      /**< Control Descriptor Ln_1 Register, offset: 0x444 */
  __IO uint32_t CTRLDESCL9_2;                      /**< Control Descriptor Ln_2 Register, offset: 0x448 */
  __IO uint32_t CTRLDESCL9_3;                      /**< Control Descriptor Ln_3 Register, offset: 0x44C */
  __IO uint32_t CTRLDESCL9_4;                      /**< Control Descriptor Ln_4 Register, offset: 0x450 */
  __IO uint32_t CTRLDESCL9_5;                      /**< Control Descriptor Ln_5 Register, offset: 0x454 */
  __IO uint32_t CTRLDESCL9_6;                      /**< Control Descriptor Ln_6 Register, offset: 0x458 */
  __IO uint32_t CTRLDESCL9_7;                      /**< Control Descriptor Ln_7 Register, offset: 0x45C */
  __IO uint32_t CTRLDESCL9_8;                      /**< Control Descriptor Ln_8 Register, offset: 0x460 */
       uint8_t RESERVED_12[28];
  __IO uint32_t CTRLDESCL10_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x480 */
  __IO uint32_t CTRLDESCL10_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x484 */
  __IO uint32_t CTRLDESCL10_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x488 */
  __IO uint32_t CTRLDESCL10_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x48C */
  __IO uint32_t CTRLDESCL10_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x490 */
  __IO uint32_t CTRLDESCL10_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x494 */
  __IO uint32_t CTRLDESCL10_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x498 */
  __IO uint32_t CTRLDESCL10_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x49C */
  __IO uint32_t CTRLDESCL10_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x4A0 */
       uint8_t RESERVED_13[28];
  __IO uint32_t CTRLDESCL11_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x4C0 */
  __IO uint32_t CTRLDESCL11_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x4C4 */
  __IO uint32_t CTRLDESCL11_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x4C8 */
  __IO uint32_t CTRLDESCL11_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x4CC */
  __IO uint32_t CTRLDESCL11_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x4D0 */
  __IO uint32_t CTRLDESCL11_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x4D4 */
  __IO uint32_t CTRLDESCL11_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x4D8 */
  __IO uint32_t CTRLDESCL11_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x4DC */
  __IO uint32_t CTRLDESCL11_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x4E0 */
       uint8_t RESERVED_14[28];
  __IO uint32_t CTRLDESCL12_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x500 */
  __IO uint32_t CTRLDESCL12_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x504 */
  __IO uint32_t CTRLDESCL12_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x508 */
  __IO uint32_t CTRLDESCL12_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x50C */
  __IO uint32_t CTRLDESCL12_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x510 */
  __IO uint32_t CTRLDESCL12_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x514 */
  __IO uint32_t CTRLDESCL12_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x518 */
  __IO uint32_t CTRLDESCL12_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x51C */
  __IO uint32_t CTRLDESCL12_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x520 */
       uint8_t RESERVED_15[28];
  __IO uint32_t CTRLDESCL13_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x540 */
  __IO uint32_t CTRLDESCL13_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x544 */
  __IO uint32_t CTRLDESCL13_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x548 */
  __IO uint32_t CTRLDESCL13_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x54C */
  __IO uint32_t CTRLDESCL13_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x550 */
  __IO uint32_t CTRLDESCL13_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x554 */
  __IO uint32_t CTRLDESCL13_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x558 */
  __IO uint32_t CTRLDESCL13_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x55C */
  __IO uint32_t CTRLDESCL13_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x560 */
       uint8_t RESERVED_16[28];
  __IO uint32_t CTRLDESCL14_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x580 */
  __IO uint32_t CTRLDESCL14_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x584 */
  __IO uint32_t CTRLDESCL14_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x588 */
  __IO uint32_t CTRLDESCL14_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x58C */
  __IO uint32_t CTRLDESCL14_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x590 */
  __IO uint32_t CTRLDESCL14_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x594 */
  __IO uint32_t CTRLDESCL14_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x598 */
  __IO uint32_t CTRLDESCL14_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x59C */
  __IO uint32_t CTRLDESCL14_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x5A0 */
       uint8_t RESERVED_17[28];
  __IO uint32_t CTRLDESCL15_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x5C0 */
  __IO uint32_t CTRLDESCL15_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x5C4 */
  __IO uint32_t CTRLDESCL15_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x5C8 */
  __IO uint32_t CTRLDESCL15_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x5CC */
  __IO uint32_t CTRLDESCL15_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x5D0 */
  __IO uint32_t CTRLDESCL15_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x5D4 */
  __IO uint32_t CTRLDESCL15_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x5D8 */
  __IO uint32_t CTRLDESCL15_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x5DC */
  __IO uint32_t CTRLDESCL15_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x5E0 */
       uint8_t RESERVED_18[28];
  __IO uint32_t CTRLDESCL16_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x600 */
  __IO uint32_t CTRLDESCL16_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x604 */
  __IO uint32_t CTRLDESCL16_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x608 */
  __IO uint32_t CTRLDESCL16_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x60C */
  __IO uint32_t CTRLDESCL16_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x610 */
  __IO uint32_t CTRLDESCL16_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x614 */
  __IO uint32_t CTRLDESCL16_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x618 */
  __IO uint32_t CTRLDESCL16_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x61C */
  __IO uint32_t CTRLDESCL16_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x620 */
       uint8_t RESERVED_19[28];
  __IO uint32_t CTRLDESCL17_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x640 */
  __IO uint32_t CTRLDESCL17_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x644 */
  __IO uint32_t CTRLDESCL17_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x648 */
  __IO uint32_t CTRLDESCL17_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x64C */
  __IO uint32_t CTRLDESCL17_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x650 */
  __IO uint32_t CTRLDESCL17_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x654 */
  __IO uint32_t CTRLDESCL17_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x658 */
  __IO uint32_t CTRLDESCL17_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x65C */
  __IO uint32_t CTRLDESCL17_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x660 */
       uint8_t RESERVED_20[28];
  __IO uint32_t CTRLDESCL18_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x680 */
  __IO uint32_t CTRLDESCL18_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x684 */
  __IO uint32_t CTRLDESCL18_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x688 */
  __IO uint32_t CTRLDESCL18_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x68C */
  __IO uint32_t CTRLDESCL18_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x690 */
  __IO uint32_t CTRLDESCL18_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x694 */
  __IO uint32_t CTRLDESCL18_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x698 */
  __IO uint32_t CTRLDESCL18_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x69C */
  __IO uint32_t CTRLDESCL18_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x6A0 */
       uint8_t RESERVED_21[28];
  __IO uint32_t CTRLDESCL19_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x6C0 */
  __IO uint32_t CTRLDESCL19_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x6C4 */
  __IO uint32_t CTRLDESCL19_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x6C8 */
  __IO uint32_t CTRLDESCL19_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x6CC */
  __IO uint32_t CTRLDESCL19_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x6D0 */
  __IO uint32_t CTRLDESCL19_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x6D4 */
  __IO uint32_t CTRLDESCL19_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x6D8 */
  __IO uint32_t CTRLDESCL19_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x6DC */
  __IO uint32_t CTRLDESCL19_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x6E0 */
       uint8_t RESERVED_22[28];
  __IO uint32_t CTRLDESCL20_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x700 */
  __IO uint32_t CTRLDESCL20_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x704 */
  __IO uint32_t CTRLDESCL20_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x708 */
  __IO uint32_t CTRLDESCL20_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x70C */
  __IO uint32_t CTRLDESCL20_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x710 */
  __IO uint32_t CTRLDESCL20_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x714 */
  __IO uint32_t CTRLDESCL20_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x718 */
  __IO uint32_t CTRLDESCL20_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x71C */
  __IO uint32_t CTRLDESCL20_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x720 */
       uint8_t RESERVED_23[28];
  __IO uint32_t CTRLDESCL21_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x740 */
  __IO uint32_t CTRLDESCL21_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x744 */
  __IO uint32_t CTRLDESCL21_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x748 */
  __IO uint32_t CTRLDESCL21_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x74C */
  __IO uint32_t CTRLDESCL21_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x750 */
  __IO uint32_t CTRLDESCL21_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x754 */
  __IO uint32_t CTRLDESCL21_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x758 */
  __IO uint32_t CTRLDESCL21_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x75C */
  __IO uint32_t CTRLDESCL21_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x760 */
       uint8_t RESERVED_24[28];
  __IO uint32_t CTRLDESCL22_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x780 */
  __IO uint32_t CTRLDESCL22_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x784 */
  __IO uint32_t CTRLDESCL22_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x788 */
  __IO uint32_t CTRLDESCL22_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x78C */
  __IO uint32_t CTRLDESCL22_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x790 */
  __IO uint32_t CTRLDESCL22_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x794 */
  __IO uint32_t CTRLDESCL22_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x798 */
  __IO uint32_t CTRLDESCL22_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x79C */
  __IO uint32_t CTRLDESCL22_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x7A0 */
       uint8_t RESERVED_25[28];
  __IO uint32_t CTRLDESCL23_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x7C0 */
  __IO uint32_t CTRLDESCL23_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x7C4 */
  __IO uint32_t CTRLDESCL23_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x7C8 */
  __IO uint32_t CTRLDESCL23_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x7CC */
  __IO uint32_t CTRLDESCL23_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x7D0 */
  __IO uint32_t CTRLDESCL23_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x7D4 */
  __IO uint32_t CTRLDESCL23_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x7D8 */
  __IO uint32_t CTRLDESCL23_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x7DC */
  __IO uint32_t CTRLDESCL23_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x7E0 */
       uint8_t RESERVED_26[28];
  __IO uint32_t CTRLDESCL24_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x800 */
  __IO uint32_t CTRLDESCL24_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x804 */
  __IO uint32_t CTRLDESCL24_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x808 */
  __IO uint32_t CTRLDESCL24_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x80C */
  __IO uint32_t CTRLDESCL24_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x810 */
  __IO uint32_t CTRLDESCL24_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x814 */
  __IO uint32_t CTRLDESCL24_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x818 */
  __IO uint32_t CTRLDESCL24_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x81C */
  __IO uint32_t CTRLDESCL24_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x820 */
       uint8_t RESERVED_27[28];
  __IO uint32_t CTRLDESCL25_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x840 */
  __IO uint32_t CTRLDESCL25_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x844 */
  __IO uint32_t CTRLDESCL25_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x848 */
  __IO uint32_t CTRLDESCL25_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x84C */
  __IO uint32_t CTRLDESCL25_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x850 */
  __IO uint32_t CTRLDESCL25_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x854 */
  __IO uint32_t CTRLDESCL25_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x858 */
  __IO uint32_t CTRLDESCL25_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x85C */
  __IO uint32_t CTRLDESCL25_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x860 */
       uint8_t RESERVED_28[28];
  __IO uint32_t CTRLDESCL26_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x880 */
  __IO uint32_t CTRLDESCL26_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x884 */
  __IO uint32_t CTRLDESCL26_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x888 */
  __IO uint32_t CTRLDESCL26_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x88C */
  __IO uint32_t CTRLDESCL26_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x890 */
  __IO uint32_t CTRLDESCL26_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x894 */
  __IO uint32_t CTRLDESCL26_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x898 */
  __IO uint32_t CTRLDESCL26_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x89C */
  __IO uint32_t CTRLDESCL26_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x8A0 */
       uint8_t RESERVED_29[28];
  __IO uint32_t CTRLDESCL27_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x8C0 */
  __IO uint32_t CTRLDESCL27_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x8C4 */
  __IO uint32_t CTRLDESCL27_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x8C8 */
  __IO uint32_t CTRLDESCL27_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x8CC */
  __IO uint32_t CTRLDESCL27_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x8D0 */
  __IO uint32_t CTRLDESCL27_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x8D4 */
  __IO uint32_t CTRLDESCL27_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x8D8 */
  __IO uint32_t CTRLDESCL27_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x8DC */
  __IO uint32_t CTRLDESCL27_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x8E0 */
       uint8_t RESERVED_30[28];
  __IO uint32_t CTRLDESCL28_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x900 */
  __IO uint32_t CTRLDESCL28_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x904 */
  __IO uint32_t CTRLDESCL28_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x908 */
  __IO uint32_t CTRLDESCL28_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x90C */
  __IO uint32_t CTRLDESCL28_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x910 */
  __IO uint32_t CTRLDESCL28_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x914 */
  __IO uint32_t CTRLDESCL28_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x918 */
  __IO uint32_t CTRLDESCL28_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x91C */
  __IO uint32_t CTRLDESCL28_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x920 */
       uint8_t RESERVED_31[28];
  __IO uint32_t CTRLDESCL29_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x940 */
  __IO uint32_t CTRLDESCL29_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x944 */
  __IO uint32_t CTRLDESCL29_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x948 */
  __IO uint32_t CTRLDESCL29_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x94C */
  __IO uint32_t CTRLDESCL29_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x950 */
  __IO uint32_t CTRLDESCL29_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x954 */
  __IO uint32_t CTRLDESCL29_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x958 */
  __IO uint32_t CTRLDESCL29_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x95C */
  __IO uint32_t CTRLDESCL29_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x960 */
       uint8_t RESERVED_32[28];
  __IO uint32_t CTRLDESCL30_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x980 */
  __IO uint32_t CTRLDESCL30_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x984 */
  __IO uint32_t CTRLDESCL30_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x988 */
  __IO uint32_t CTRLDESCL30_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x98C */
  __IO uint32_t CTRLDESCL30_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x990 */
  __IO uint32_t CTRLDESCL30_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x994 */
  __IO uint32_t CTRLDESCL30_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x998 */
  __IO uint32_t CTRLDESCL30_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x99C */
  __IO uint32_t CTRLDESCL30_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x9A0 */
       uint8_t RESERVED_33[28];
  __IO uint32_t CTRLDESCL31_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x9C0 */
  __IO uint32_t CTRLDESCL31_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x9C4 */
  __IO uint32_t CTRLDESCL31_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x9C8 */
  __IO uint32_t CTRLDESCL31_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x9CC */
  __IO uint32_t CTRLDESCL31_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x9D0 */
  __IO uint32_t CTRLDESCL31_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x9D4 */
  __IO uint32_t CTRLDESCL31_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x9D8 */
  __IO uint32_t CTRLDESCL31_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x9DC */
  __IO uint32_t CTRLDESCL31_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x9E0 */
       uint8_t RESERVED_34[28];
  __IO uint32_t CTRLDESCL32_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xA00 */
  __IO uint32_t CTRLDESCL32_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xA04 */
  __IO uint32_t CTRLDESCL32_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xA08 */
  __IO uint32_t CTRLDESCL32_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xA0C */
  __IO uint32_t CTRLDESCL32_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xA10 */
  __IO uint32_t CTRLDESCL32_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xA14 */
  __IO uint32_t CTRLDESCL32_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xA18 */
  __IO uint32_t CTRLDESCL32_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xA1C */
  __IO uint32_t CTRLDESCL32_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xA20 */
       uint8_t RESERVED_35[28];
  __IO uint32_t CTRLDESCL33_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xA40 */
  __IO uint32_t CTRLDESCL33_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xA44 */
  __IO uint32_t CTRLDESCL33_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xA48 */
  __IO uint32_t CTRLDESCL33_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xA4C */
  __IO uint32_t CTRLDESCL33_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xA50 */
  __IO uint32_t CTRLDESCL33_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xA54 */
  __IO uint32_t CTRLDESCL33_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xA58 */
  __IO uint32_t CTRLDESCL33_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xA5C */
  __IO uint32_t CTRLDESCL33_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xA60 */
       uint8_t RESERVED_36[28];
  __IO uint32_t CTRLDESCL34_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xA80 */
  __IO uint32_t CTRLDESCL34_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xA84 */
  __IO uint32_t CTRLDESCL34_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xA88 */
  __IO uint32_t CTRLDESCL34_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xA8C */
  __IO uint32_t CTRLDESCL34_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xA90 */
  __IO uint32_t CTRLDESCL34_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xA94 */
  __IO uint32_t CTRLDESCL34_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xA98 */
  __IO uint32_t CTRLDESCL34_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xA9C */
  __IO uint32_t CTRLDESCL34_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xAA0 */
       uint8_t RESERVED_37[28];
  __IO uint32_t CTRLDESCL35_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xAC0 */
  __IO uint32_t CTRLDESCL35_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xAC4 */
  __IO uint32_t CTRLDESCL35_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xAC8 */
  __IO uint32_t CTRLDESCL35_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xACC */
  __IO uint32_t CTRLDESCL35_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xAD0 */
  __IO uint32_t CTRLDESCL35_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xAD4 */
  __IO uint32_t CTRLDESCL35_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xAD8 */
  __IO uint32_t CTRLDESCL35_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xADC */
  __IO uint32_t CTRLDESCL35_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xAE0 */
       uint8_t RESERVED_38[28];
  __IO uint32_t CTRLDESCL36_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xB00 */
  __IO uint32_t CTRLDESCL36_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xB04 */
  __IO uint32_t CTRLDESCL36_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xB08 */
  __IO uint32_t CTRLDESCL36_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xB0C */
  __IO uint32_t CTRLDESCL36_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xB10 */
  __IO uint32_t CTRLDESCL36_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xB14 */
  __IO uint32_t CTRLDESCL36_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xB18 */
  __IO uint32_t CTRLDESCL36_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xB1C */
  __IO uint32_t CTRLDESCL36_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xB20 */
       uint8_t RESERVED_39[28];
  __IO uint32_t CTRLDESCL37_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xB40 */
  __IO uint32_t CTRLDESCL37_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xB44 */
  __IO uint32_t CTRLDESCL37_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xB48 */
  __IO uint32_t CTRLDESCL37_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xB4C */
  __IO uint32_t CTRLDESCL37_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xB50 */
  __IO uint32_t CTRLDESCL37_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xB54 */
  __IO uint32_t CTRLDESCL37_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xB58 */
  __IO uint32_t CTRLDESCL37_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xB5C */
  __IO uint32_t CTRLDESCL37_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xB60 */
       uint8_t RESERVED_40[28];
  __IO uint32_t CTRLDESCL38_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xB80 */
  __IO uint32_t CTRLDESCL38_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xB84 */
  __IO uint32_t CTRLDESCL38_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xB88 */
  __IO uint32_t CTRLDESCL38_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xB8C */
  __IO uint32_t CTRLDESCL38_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xB90 */
  __IO uint32_t CTRLDESCL38_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xB94 */
  __IO uint32_t CTRLDESCL38_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xB98 */
  __IO uint32_t CTRLDESCL38_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xB9C */
  __IO uint32_t CTRLDESCL38_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xBA0 */
       uint8_t RESERVED_41[28];
  __IO uint32_t CTRLDESCL39_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xBC0 */
  __IO uint32_t CTRLDESCL39_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xBC4 */
  __IO uint32_t CTRLDESCL39_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xBC8 */
  __IO uint32_t CTRLDESCL39_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xBCC */
  __IO uint32_t CTRLDESCL39_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xBD0 */
  __IO uint32_t CTRLDESCL39_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xBD4 */
  __IO uint32_t CTRLDESCL39_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xBD8 */
  __IO uint32_t CTRLDESCL39_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xBDC */
  __IO uint32_t CTRLDESCL39_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xBE0 */
       uint8_t RESERVED_42[28];
  __IO uint32_t CTRLDESCL40_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xC00 */
  __IO uint32_t CTRLDESCL40_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xC04 */
  __IO uint32_t CTRLDESCL40_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xC08 */
  __IO uint32_t CTRLDESCL40_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xC0C */
  __IO uint32_t CTRLDESCL40_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xC10 */
  __IO uint32_t CTRLDESCL40_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xC14 */
  __IO uint32_t CTRLDESCL40_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xC18 */
  __IO uint32_t CTRLDESCL40_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xC1C */
  __IO uint32_t CTRLDESCL40_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xC20 */
       uint8_t RESERVED_43[28];
  __IO uint32_t CTRLDESCL41_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xC40 */
  __IO uint32_t CTRLDESCL41_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xC44 */
  __IO uint32_t CTRLDESCL41_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xC48 */
  __IO uint32_t CTRLDESCL41_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xC4C */
  __IO uint32_t CTRLDESCL41_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xC50 */
  __IO uint32_t CTRLDESCL41_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xC54 */
  __IO uint32_t CTRLDESCL41_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xC58 */
  __IO uint32_t CTRLDESCL41_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xC5C */
  __IO uint32_t CTRLDESCL41_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xC60 */
       uint8_t RESERVED_44[28];
  __IO uint32_t CTRLDESCL42_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xC80 */
  __IO uint32_t CTRLDESCL42_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xC84 */
  __IO uint32_t CTRLDESCL42_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xC88 */
  __IO uint32_t CTRLDESCL42_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xC8C */
  __IO uint32_t CTRLDESCL42_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xC90 */
  __IO uint32_t CTRLDESCL42_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xC94 */
  __IO uint32_t CTRLDESCL42_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xC98 */
  __IO uint32_t CTRLDESCL42_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xC9C */
  __IO uint32_t CTRLDESCL42_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xCA0 */
       uint8_t RESERVED_45[28];
  __IO uint32_t CTRLDESCL43_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xCC0 */
  __IO uint32_t CTRLDESCL43_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xCC4 */
  __IO uint32_t CTRLDESCL43_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xCC8 */
  __IO uint32_t CTRLDESCL43_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xCCC */
  __IO uint32_t CTRLDESCL43_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xCD0 */
  __IO uint32_t CTRLDESCL43_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xCD4 */
  __IO uint32_t CTRLDESCL43_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xCD8 */
  __IO uint32_t CTRLDESCL43_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xCDC */
  __IO uint32_t CTRLDESCL43_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xCE0 */
       uint8_t RESERVED_46[28];
  __IO uint32_t CTRLDESCL44_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xD00 */
  __IO uint32_t CTRLDESCL44_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xD04 */
  __IO uint32_t CTRLDESCL44_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xD08 */
  __IO uint32_t CTRLDESCL44_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xD0C */
  __IO uint32_t CTRLDESCL44_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xD10 */
  __IO uint32_t CTRLDESCL44_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xD14 */
  __IO uint32_t CTRLDESCL44_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xD18 */
  __IO uint32_t CTRLDESCL44_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xD1C */
  __IO uint32_t CTRLDESCL44_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xD20 */
       uint8_t RESERVED_47[28];
  __IO uint32_t CTRLDESCL45_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xD40 */
  __IO uint32_t CTRLDESCL45_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xD44 */
  __IO uint32_t CTRLDESCL45_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xD48 */
  __IO uint32_t CTRLDESCL45_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xD4C */
  __IO uint32_t CTRLDESCL45_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xD50 */
  __IO uint32_t CTRLDESCL45_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xD54 */
  __IO uint32_t CTRLDESCL45_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xD58 */
  __IO uint32_t CTRLDESCL45_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xD5C */
  __IO uint32_t CTRLDESCL45_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xD60 */
       uint8_t RESERVED_48[28];
  __IO uint32_t CTRLDESCL46_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xD80 */
  __IO uint32_t CTRLDESCL46_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xD84 */
  __IO uint32_t CTRLDESCL46_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xD88 */
  __IO uint32_t CTRLDESCL46_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xD8C */
  __IO uint32_t CTRLDESCL46_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xD90 */
  __IO uint32_t CTRLDESCL46_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xD94 */
  __IO uint32_t CTRLDESCL46_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xD98 */
  __IO uint32_t CTRLDESCL46_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xD9C */
  __IO uint32_t CTRLDESCL46_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xDA0 */
       uint8_t RESERVED_49[28];
  __IO uint32_t CTRLDESCL47_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xDC0 */
  __IO uint32_t CTRLDESCL47_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xDC4 */
  __IO uint32_t CTRLDESCL47_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xDC8 */
  __IO uint32_t CTRLDESCL47_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xDCC */
  __IO uint32_t CTRLDESCL47_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xDD0 */
  __IO uint32_t CTRLDESCL47_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xDD4 */
  __IO uint32_t CTRLDESCL47_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xDD8 */
  __IO uint32_t CTRLDESCL47_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xDDC */
  __IO uint32_t CTRLDESCL47_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xDE0 */
       uint8_t RESERVED_50[28];
  __IO uint32_t CTRLDESCL48_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xE00 */
  __IO uint32_t CTRLDESCL48_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xE04 */
  __IO uint32_t CTRLDESCL48_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xE08 */
  __IO uint32_t CTRLDESCL48_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xE0C */
  __IO uint32_t CTRLDESCL48_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xE10 */
  __IO uint32_t CTRLDESCL48_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xE14 */
  __IO uint32_t CTRLDESCL48_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xE18 */
  __IO uint32_t CTRLDESCL48_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xE1C */
  __IO uint32_t CTRLDESCL48_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xE20 */
       uint8_t RESERVED_51[28];
  __IO uint32_t CTRLDESCL49_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xE40 */
  __IO uint32_t CTRLDESCL49_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xE44 */
  __IO uint32_t CTRLDESCL49_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xE48 */
  __IO uint32_t CTRLDESCL49_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xE4C */
  __IO uint32_t CTRLDESCL49_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xE50 */
  __IO uint32_t CTRLDESCL49_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xE54 */
  __IO uint32_t CTRLDESCL49_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xE58 */
  __IO uint32_t CTRLDESCL49_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xE5C */
  __IO uint32_t CTRLDESCL49_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xE60 */
       uint8_t RESERVED_52[28];
  __IO uint32_t CTRLDESCL50_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xE80 */
  __IO uint32_t CTRLDESCL50_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xE84 */
  __IO uint32_t CTRLDESCL50_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xE88 */
  __IO uint32_t CTRLDESCL50_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xE8C */
  __IO uint32_t CTRLDESCL50_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xE90 */
  __IO uint32_t CTRLDESCL50_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xE94 */
  __IO uint32_t CTRLDESCL50_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xE98 */
  __IO uint32_t CTRLDESCL50_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xE9C */
  __IO uint32_t CTRLDESCL50_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xEA0 */
       uint8_t RESERVED_53[28];
  __IO uint32_t CTRLDESCL51_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xEC0 */
  __IO uint32_t CTRLDESCL51_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xEC4 */
  __IO uint32_t CTRLDESCL51_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xEC8 */
  __IO uint32_t CTRLDESCL51_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xECC */
  __IO uint32_t CTRLDESCL51_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xED0 */
  __IO uint32_t CTRLDESCL51_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xED4 */
  __IO uint32_t CTRLDESCL51_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xED8 */
  __IO uint32_t CTRLDESCL51_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xEDC */
  __IO uint32_t CTRLDESCL51_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xEE0 */
       uint8_t RESERVED_54[28];
  __IO uint32_t CTRLDESCL52_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xF00 */
  __IO uint32_t CTRLDESCL52_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xF04 */
  __IO uint32_t CTRLDESCL52_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xF08 */
  __IO uint32_t CTRLDESCL52_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xF0C */
  __IO uint32_t CTRLDESCL52_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xF10 */
  __IO uint32_t CTRLDESCL52_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xF14 */
  __IO uint32_t CTRLDESCL52_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xF18 */
  __IO uint32_t CTRLDESCL52_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xF1C */
  __IO uint32_t CTRLDESCL52_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xF20 */
       uint8_t RESERVED_55[28];
  __IO uint32_t CTRLDESCL53_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xF40 */
  __IO uint32_t CTRLDESCL53_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xF44 */
  __IO uint32_t CTRLDESCL53_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xF48 */
  __IO uint32_t CTRLDESCL53_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xF4C */
  __IO uint32_t CTRLDESCL53_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xF50 */
  __IO uint32_t CTRLDESCL53_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xF54 */
  __IO uint32_t CTRLDESCL53_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xF58 */
  __IO uint32_t CTRLDESCL53_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xF5C */
  __IO uint32_t CTRLDESCL53_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xF60 */
       uint8_t RESERVED_56[28];
  __IO uint32_t CTRLDESCL54_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xF80 */
  __IO uint32_t CTRLDESCL54_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xF84 */
  __IO uint32_t CTRLDESCL54_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xF88 */
  __IO uint32_t CTRLDESCL54_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xF8C */
  __IO uint32_t CTRLDESCL54_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xF90 */
  __IO uint32_t CTRLDESCL54_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xF94 */
  __IO uint32_t CTRLDESCL54_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xF98 */
  __IO uint32_t CTRLDESCL54_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xF9C */
  __IO uint32_t CTRLDESCL54_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xFA0 */
       uint8_t RESERVED_57[28];
  __IO uint32_t CTRLDESCL55_0;                     /**< Control Descriptor Ln_0 Register, offset: 0xFC0 */
  __IO uint32_t CTRLDESCL55_1;                     /**< Control Descriptor Ln_1 Register, offset: 0xFC4 */
  __IO uint32_t CTRLDESCL55_2;                     /**< Control Descriptor Ln_2 Register, offset: 0xFC8 */
  __IO uint32_t CTRLDESCL55_3;                     /**< Control Descriptor Ln_3 Register, offset: 0xFCC */
  __IO uint32_t CTRLDESCL55_4;                     /**< Control Descriptor Ln_4 Register, offset: 0xFD0 */
  __IO uint32_t CTRLDESCL55_5;                     /**< Control Descriptor Ln_5 Register, offset: 0xFD4 */
  __IO uint32_t CTRLDESCL55_6;                     /**< Control Descriptor Ln_6 Register, offset: 0xFD8 */
  __IO uint32_t CTRLDESCL55_7;                     /**< Control Descriptor Ln_7 Register, offset: 0xFDC */
  __IO uint32_t CTRLDESCL55_8;                     /**< Control Descriptor Ln_8 Register, offset: 0xFE0 */
       uint8_t RESERVED_58[28];
  __IO uint32_t CTRLDESCL56_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x1000 */
  __IO uint32_t CTRLDESCL56_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x1004 */
  __IO uint32_t CTRLDESCL56_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x1008 */
  __IO uint32_t CTRLDESCL56_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x100C */
  __IO uint32_t CTRLDESCL56_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x1010 */
  __IO uint32_t CTRLDESCL56_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x1014 */
  __IO uint32_t CTRLDESCL56_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x1018 */
  __IO uint32_t CTRLDESCL56_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x101C */
  __IO uint32_t CTRLDESCL56_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x1020 */
       uint8_t RESERVED_59[28];
  __IO uint32_t CTRLDESCL57_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x1040 */
  __IO uint32_t CTRLDESCL57_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x1044 */
  __IO uint32_t CTRLDESCL57_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x1048 */
  __IO uint32_t CTRLDESCL57_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x104C */
  __IO uint32_t CTRLDESCL57_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x1050 */
  __IO uint32_t CTRLDESCL57_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x1054 */
  __IO uint32_t CTRLDESCL57_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x1058 */
  __IO uint32_t CTRLDESCL57_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x105C */
  __IO uint32_t CTRLDESCL57_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x1060 */
       uint8_t RESERVED_60[28];
  __IO uint32_t CTRLDESCL58_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x1080 */
  __IO uint32_t CTRLDESCL58_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x1084 */
  __IO uint32_t CTRLDESCL58_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x1088 */
  __IO uint32_t CTRLDESCL58_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x108C */
  __IO uint32_t CTRLDESCL58_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x1090 */
  __IO uint32_t CTRLDESCL58_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x1094 */
  __IO uint32_t CTRLDESCL58_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x1098 */
  __IO uint32_t CTRLDESCL58_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x109C */
  __IO uint32_t CTRLDESCL58_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x10A0 */
       uint8_t RESERVED_61[28];
  __IO uint32_t CTRLDESCL59_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x10C0 */
  __IO uint32_t CTRLDESCL59_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x10C4 */
  __IO uint32_t CTRLDESCL59_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x10C8 */
  __IO uint32_t CTRLDESCL59_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x10CC */
  __IO uint32_t CTRLDESCL59_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x10D0 */
  __IO uint32_t CTRLDESCL59_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x10D4 */
  __IO uint32_t CTRLDESCL59_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x10D8 */
  __IO uint32_t CTRLDESCL59_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x10DC */
  __IO uint32_t CTRLDESCL59_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x10E0 */
       uint8_t RESERVED_62[28];
  __IO uint32_t CTRLDESCL60_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x1100 */
  __IO uint32_t CTRLDESCL60_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x1104 */
  __IO uint32_t CTRLDESCL60_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x1108 */
  __IO uint32_t CTRLDESCL60_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x110C */
  __IO uint32_t CTRLDESCL60_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x1110 */
  __IO uint32_t CTRLDESCL60_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x1114 */
  __IO uint32_t CTRLDESCL60_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x1118 */
  __IO uint32_t CTRLDESCL60_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x111C */
  __IO uint32_t CTRLDESCL60_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x1120 */
       uint8_t RESERVED_63[28];
  __IO uint32_t CTRLDESCL61_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x1140 */
  __IO uint32_t CTRLDESCL61_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x1144 */
  __IO uint32_t CTRLDESCL61_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x1148 */
  __IO uint32_t CTRLDESCL61_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x114C */
  __IO uint32_t CTRLDESCL61_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x1150 */
  __IO uint32_t CTRLDESCL61_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x1154 */
  __IO uint32_t CTRLDESCL61_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x1158 */
  __IO uint32_t CTRLDESCL61_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x115C */
  __IO uint32_t CTRLDESCL61_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x1160 */
       uint8_t RESERVED_64[28];
  __IO uint32_t CTRLDESCL62_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x1180 */
  __IO uint32_t CTRLDESCL62_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x1184 */
  __IO uint32_t CTRLDESCL62_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x1188 */
  __IO uint32_t CTRLDESCL62_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x118C */
  __IO uint32_t CTRLDESCL62_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x1190 */
  __IO uint32_t CTRLDESCL62_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x1194 */
  __IO uint32_t CTRLDESCL62_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x1198 */
  __IO uint32_t CTRLDESCL62_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x119C */
  __IO uint32_t CTRLDESCL62_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x11A0 */
       uint8_t RESERVED_65[28];
  __IO uint32_t CTRLDESCL63_0;                     /**< Control Descriptor Ln_0 Register, offset: 0x11C0 */
  __IO uint32_t CTRLDESCL63_1;                     /**< Control Descriptor Ln_1 Register, offset: 0x11C4 */
  __IO uint32_t CTRLDESCL63_2;                     /**< Control Descriptor Ln_2 Register, offset: 0x11C8 */
  __IO uint32_t CTRLDESCL63_3;                     /**< Control Descriptor Ln_3 Register, offset: 0x11CC */
  __IO uint32_t CTRLDESCL63_4;                     /**< Control Descriptor Ln_4 Register, offset: 0x11D0 */
  __IO uint32_t CTRLDESCL63_5;                     /**< Control Descriptor Ln_5 Register, offset: 0x11D4 */
  __IO uint32_t CTRLDESCL63_6;                     /**< Control Descriptor Ln_6 Register, offset: 0x11D8 */
  __IO uint32_t CTRLDESCL63_7;                     /**< Control Descriptor Ln_7 Register, offset: 0x11DC */
  __IO uint32_t CTRLDESCL63_8;                     /**< Control Descriptor Ln_8 Register, offset: 0x11E0 */
} DCU_Type;

/* ----------------------------------------------------------------------------
   -- DCU Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DCU_Register_Masks DCU Register Masks
 * @{
 */

/* CTRLDESCCURSOR1 Bit Fields */
#define DCU_CTRLDESCCURSOR1_WIDTH_MASK           0x7FFu
#define DCU_CTRLDESCCURSOR1_WIDTH_SHIFT          0
#define DCU_CTRLDESCCURSOR1_WIDTH(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR1_WIDTH_SHIFT))&DCU_CTRLDESCCURSOR1_WIDTH_MASK)
#define DCU_CTRLDESCCURSOR1_HEIGHT_MASK          0x7FF0000u
#define DCU_CTRLDESCCURSOR1_HEIGHT_SHIFT         16
#define DCU_CTRLDESCCURSOR1_HEIGHT(x)            (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR1_HEIGHT_SHIFT))&DCU_CTRLDESCCURSOR1_HEIGHT_MASK)
/* CTRLDESCCURSOR2 Bit Fields */
#define DCU_CTRLDESCCURSOR2_POSX_MASK            0x7FFu
#define DCU_CTRLDESCCURSOR2_POSX_SHIFT           0
#define DCU_CTRLDESCCURSOR2_POSX(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR2_POSX_SHIFT))&DCU_CTRLDESCCURSOR2_POSX_MASK)
#define DCU_CTRLDESCCURSOR2_POSY_MASK            0x7FF0000u
#define DCU_CTRLDESCCURSOR2_POSY_SHIFT           16
#define DCU_CTRLDESCCURSOR2_POSY(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR2_POSY_SHIFT))&DCU_CTRLDESCCURSOR2_POSY_MASK)
/* CTRLDESCCURSOR3 Bit Fields */
#define DCU_CTRLDESCCURSOR3_DEFAULT_CURSOR_COLOR_MASK 0xFFFFFFu
#define DCU_CTRLDESCCURSOR3_DEFAULT_CURSOR_COLOR_SHIFT 0
#define DCU_CTRLDESCCURSOR3_DEFAULT_CURSOR_COLOR(x) (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR3_DEFAULT_CURSOR_COLOR_SHIFT))&DCU_CTRLDESCCURSOR3_DEFAULT_CURSOR_COLOR_MASK)
#define DCU_CTRLDESCCURSOR3_CUR_EN_MASK          0x80000000u
#define DCU_CTRLDESCCURSOR3_CUR_EN_SHIFT         31
/* CTRLDESCCURSOR4 Bit Fields */
#define DCU_CTRLDESCCURSOR4_HWC_BLINK_ON_MASK    0xFFu
#define DCU_CTRLDESCCURSOR4_HWC_BLINK_ON_SHIFT   0
#define DCU_CTRLDESCCURSOR4_HWC_BLINK_ON(x)      (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR4_HWC_BLINK_ON_SHIFT))&DCU_CTRLDESCCURSOR4_HWC_BLINK_ON_MASK)
#define DCU_CTRLDESCCURSOR4_EN_BLINK_MASK        0x100u
#define DCU_CTRLDESCCURSOR4_EN_BLINK_SHIFT       8
#define DCU_CTRLDESCCURSOR4_HWC_BLINK_OFF_MASK   0xFF0000u
#define DCU_CTRLDESCCURSOR4_HWC_BLINK_OFF_SHIFT  16
#define DCU_CTRLDESCCURSOR4_HWC_BLINK_OFF(x)     (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCCURSOR4_HWC_BLINK_OFF_SHIFT))&DCU_CTRLDESCCURSOR4_HWC_BLINK_OFF_MASK)
/* DCU_MODE Bit Fields */
#define DCU_DCU_MODE_DCU_MODE_MASK               0x3u
#define DCU_DCU_MODE_DCU_MODE_SHIFT              0
#define DCU_DCU_MODE_DCU_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_DCU_MODE_SHIFT))&DCU_DCU_MODE_DCU_MODE_MASK)
#define DCU_DCU_MODE_EN_GAMMA_MASK               0x4u
#define DCU_DCU_MODE_EN_GAMMA_SHIFT              2
#define DCU_DCU_MODE_SIG_EN_MASK                 0x20u
#define DCU_DCU_MODE_SIG_EN_SHIFT                5
#define DCU_DCU_MODE_TAG_EN_MASK                 0x40u
#define DCU_DCU_MODE_TAG_EN_SHIFT                6
#define DCU_DCU_MODE_PDI_SLAVE_MODE_MASK         0x80u
#define DCU_DCU_MODE_PDI_SLAVE_MODE_SHIFT        7
#define DCU_DCU_MODE_PDI_MODE_MASK               0x300u
#define DCU_DCU_MODE_PDI_MODE_SHIFT              8
#define DCU_DCU_MODE_PDI_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_PDI_MODE_SHIFT))&DCU_DCU_MODE_PDI_MODE_MASK)
#define DCU_DCU_MODE_PDI_NARROW_MODE_MASK        0x400u
#define DCU_DCU_MODE_PDI_NARROW_MODE_SHIFT       10
#define DCU_DCU_MODE_PDI_DE_MODE_MASK            0x800u
#define DCU_DCU_MODE_PDI_DE_MODE_SHIFT           11
#define DCU_DCU_MODE_PDI_BYTE_REV_MASK           0x1000u
#define DCU_DCU_MODE_PDI_BYTE_REV_SHIFT          12
#define DCU_DCU_MODE_PDI_EN_MASK                 0x2000u
#define DCU_DCU_MODE_PDI_EN_SHIFT                13
#define DCU_DCU_MODE_RASTER_EN_MASK              0x4000u
#define DCU_DCU_MODE_RASTER_EN_SHIFT             14
#define DCU_DCU_MODE_PDI_INTERPOL_EN_MASK        0x8000u
#define DCU_DCU_MODE_PDI_INTERPOL_EN_SHIFT       15
#define DCU_DCU_MODE_PDI_SYNC_LOCK_MASK          0xF0000u
#define DCU_DCU_MODE_PDI_SYNC_LOCK_SHIFT         16
#define DCU_DCU_MODE_PDI_SYNC_LOCK(x)            (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_PDI_SYNC_LOCK_SHIFT))&DCU_DCU_MODE_PDI_SYNC_LOCK_MASK)
#define DCU_DCU_MODE_BLEND_ITER_MASK             0x700000u
#define DCU_DCU_MODE_BLEND_ITER_SHIFT            20
#define DCU_DCU_MODE_BLEND_ITER(x)               (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_BLEND_ITER_SHIFT))&DCU_DCU_MODE_BLEND_ITER_MASK)
#define DCU_DCU_MODE_DDR_MODE_MASK               0x800000u
#define DCU_DCU_MODE_DDR_MODE_SHIFT              23
#define DCU_DCU_MODE_ADDR_MASK                   0x3000000u
#define DCU_DCU_MODE_ADDR_SHIFT                  24
#define DCU_DCU_MODE_ADDR(x)                     (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_ADDR_SHIFT))&DCU_DCU_MODE_ADDR_MASK)
#define DCU_DCU_MODE_ADDG_MASK                   0xC000000u
#define DCU_DCU_MODE_ADDG_SHIFT                  26
#define DCU_DCU_MODE_ADDG(x)                     (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_ADDG_SHIFT))&DCU_DCU_MODE_ADDG_MASK)
#define DCU_DCU_MODE_ADDB_MASK                   0x30000000u
#define DCU_DCU_MODE_ADDB_SHIFT                  28
#define DCU_DCU_MODE_ADDB(x)                     (((uint32_t)(((uint32_t)(x))<<DCU_DCU_MODE_ADDB_SHIFT))&DCU_DCU_MODE_ADDB_MASK)
#define DCU_DCU_MODE_EN_DITHER_MASK              0x40000000u
#define DCU_DCU_MODE_EN_DITHER_SHIFT             30
#define DCU_DCU_MODE_DCU_SW_RESET_MASK           0x80000000u
#define DCU_DCU_MODE_DCU_SW_RESET_SHIFT          31
/* BGND Bit Fields */
#define DCU_BGND_BGND_B_MASK                     0xFFu
#define DCU_BGND_BGND_B_SHIFT                    0
#define DCU_BGND_BGND_B(x)                       (((uint32_t)(((uint32_t)(x))<<DCU_BGND_BGND_B_SHIFT))&DCU_BGND_BGND_B_MASK)
#define DCU_BGND_BGND_G_MASK                     0xFF00u
#define DCU_BGND_BGND_G_SHIFT                    8
#define DCU_BGND_BGND_G(x)                       (((uint32_t)(((uint32_t)(x))<<DCU_BGND_BGND_G_SHIFT))&DCU_BGND_BGND_G_MASK)
#define DCU_BGND_BGND_R_MASK                     0xFF0000u
#define DCU_BGND_BGND_R_SHIFT                    16
#define DCU_BGND_BGND_R(x)                       (((uint32_t)(((uint32_t)(x))<<DCU_BGND_BGND_R_SHIFT))&DCU_BGND_BGND_R_MASK)
/* DISP_SIZE Bit Fields */
#define DCU_DISP_SIZE_DELTA_X_MASK               0x7Fu
#define DCU_DISP_SIZE_DELTA_X_SHIFT              0
#define DCU_DISP_SIZE_DELTA_X(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_DISP_SIZE_DELTA_X_SHIFT))&DCU_DISP_SIZE_DELTA_X_MASK)
#define DCU_DISP_SIZE_DELTA_Y_MASK               0x7FF0000u
#define DCU_DISP_SIZE_DELTA_Y_SHIFT              16
#define DCU_DISP_SIZE_DELTA_Y(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_DISP_SIZE_DELTA_Y_SHIFT))&DCU_DISP_SIZE_DELTA_Y_MASK)
/* HSYN_PARA Bit Fields */
#define DCU_HSYN_PARA_FP_H_MASK                  0x1FFu
#define DCU_HSYN_PARA_FP_H_SHIFT                 0
#define DCU_HSYN_PARA_FP_H(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_HSYN_PARA_FP_H_SHIFT))&DCU_HSYN_PARA_FP_H_MASK)
#define DCU_HSYN_PARA_PW_H_MASK                  0xFF800u
#define DCU_HSYN_PARA_PW_H_SHIFT                 11
#define DCU_HSYN_PARA_PW_H(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_HSYN_PARA_PW_H_SHIFT))&DCU_HSYN_PARA_PW_H_MASK)
#define DCU_HSYN_PARA_BP_H_MASK                  0x7FC00000u
#define DCU_HSYN_PARA_BP_H_SHIFT                 22
#define DCU_HSYN_PARA_BP_H(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_HSYN_PARA_BP_H_SHIFT))&DCU_HSYN_PARA_BP_H_MASK)
/* VSYN_PARA Bit Fields */
#define DCU_VSYN_PARA_FP_V_MASK                  0x1FFu
#define DCU_VSYN_PARA_FP_V_SHIFT                 0
#define DCU_VSYN_PARA_FP_V(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_VSYN_PARA_FP_V_SHIFT))&DCU_VSYN_PARA_FP_V_MASK)
#define DCU_VSYN_PARA_PW_V_MASK                  0xFF800u
#define DCU_VSYN_PARA_PW_V_SHIFT                 11
#define DCU_VSYN_PARA_PW_V(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_VSYN_PARA_PW_V_SHIFT))&DCU_VSYN_PARA_PW_V_MASK)
#define DCU_VSYN_PARA_BP_V_MASK                  0x7FC00000u
#define DCU_VSYN_PARA_BP_V_SHIFT                 22
#define DCU_VSYN_PARA_BP_V(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_VSYN_PARA_BP_V_SHIFT))&DCU_VSYN_PARA_BP_V_MASK)
/* SYNPOL Bit Fields */
#define DCU_SYNPOL_INV_HS_MASK                   0x1u
#define DCU_SYNPOL_INV_HS_SHIFT                  0
#define DCU_SYNPOL_INV_VS_MASK                   0x2u
#define DCU_SYNPOL_INV_VS_SHIFT                  1
#define DCU_SYNPOL_NEG_MASK                      0x20u
#define DCU_SYNPOL_NEG_SHIFT                     5
#define DCU_SYNPOL_INV_PXCK_MASK                 0x40u
#define DCU_SYNPOL_INV_PXCK_SHIFT                6
#define DCU_SYNPOL_INV_PDI_CLK_MASK              0x80u
#define DCU_SYNPOL_INV_PDI_CLK_SHIFT             7
#define DCU_SYNPOL_INV_PDI_VS_MASK               0x100u
#define DCU_SYNPOL_INV_PDI_VS_SHIFT              8
#define DCU_SYNPOL_INV_PDI_HS_MASK               0x200u
#define DCU_SYNPOL_INV_PDI_HS_SHIFT              9
#define DCU_SYNPOL_INV_PDI_DE_MASK               0x400u
#define DCU_SYNPOL_INV_PDI_DE_SHIFT              10
/* THRESHOLD Bit Fields */
#define DCU_THRESHOLD_OUT_BUF_LOW_MASK           0xFFu
#define DCU_THRESHOLD_OUT_BUF_LOW_SHIFT          0
#define DCU_THRESHOLD_OUT_BUF_LOW(x)             (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_OUT_BUF_LOW_SHIFT))&DCU_THRESHOLD_OUT_BUF_LOW_MASK)
#define DCU_THRESHOLD_OUT_BUF_HIGH_MASK          0xFF00u
#define DCU_THRESHOLD_OUT_BUF_HIGH_SHIFT         8
#define DCU_THRESHOLD_OUT_BUF_HIGH(x)            (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_OUT_BUF_HIGH_SHIFT))&DCU_THRESHOLD_OUT_BUF_HIGH_MASK)
#define DCU_THRESHOLD_LS_BF_VS_MASK              0x7FF0000u
#define DCU_THRESHOLD_LS_BF_VS_SHIFT             16
#define DCU_THRESHOLD_LS_BF_VS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_LS_BF_VS_SHIFT))&DCU_THRESHOLD_LS_BF_VS_MASK)
/* INT_STATUS Bit Fields */
#define DCU_INT_STATUS_VSYNC_MASK                0x1u
#define DCU_INT_STATUS_VSYNC_SHIFT               0
#define DCU_INT_STATUS_UNDRUN_MASK               0x2u
#define DCU_INT_STATUS_UNDRUN_SHIFT              1
#define DCU_INT_STATUS_LS_BF_VS_MASK             0x4u
#define DCU_INT_STATUS_LS_BF_VS_SHIFT            2
#define DCU_INT_STATUS_VS_BLANK_MASK             0x8u
#define DCU_INT_STATUS_VS_BLANK_SHIFT            3
#define DCU_INT_STATUS_CRC_READY_MASK            0x10u
#define DCU_INT_STATUS_CRC_READY_SHIFT           4
#define DCU_INT_STATUS_CRC_OVERFLOW_MASK         0x20u
#define DCU_INT_STATUS_CRC_OVERFLOW_SHIFT        5
#define DCU_INT_STATUS_P1_FIFO_LO_FLAG_MASK      0x40u
#define DCU_INT_STATUS_P1_FIFO_LO_FLAG_SHIFT     6
#define DCU_INT_STATUS_P1_FIFO_HI_FLAG_MASK      0x80u
#define DCU_INT_STATUS_P1_FIFO_HI_FLAG_SHIFT     7
#define DCU_INT_STATUS_P2_FIFO_LO_FLAG_MASK      0x100u
#define DCU_INT_STATUS_P2_FIFO_LO_FLAG_SHIFT     8
#define DCU_INT_STATUS_P2_FIFO_HI_FLAG_MASK      0x200u
#define DCU_INT_STATUS_P2_FIFO_HI_FLAG_SHIFT     9
#define DCU_INT_STATUS_PROG_END_MASK             0x400u
#define DCU_INT_STATUS_PROG_END_SHIFT            10
#define DCU_INT_STATUS_IPM_ERROR_MASK            0x800u
#define DCU_INT_STATUS_IPM_ERROR_SHIFT           11
#define DCU_INT_STATUS_LYR_TRANS_FINISH_MASK     0x1000u
#define DCU_INT_STATUS_LYR_TRANS_FINISH_SHIFT    12
#define DCU_INT_STATUS_DMA_TRANS_FINISH_MASK     0x4000u
#define DCU_INT_STATUS_DMA_TRANS_FINISH_SHIFT    14
#define DCU_INT_STATUS_P3_FIFO_LO_FLAG_MASK      0x10000u
#define DCU_INT_STATUS_P3_FIFO_LO_FLAG_SHIFT     16
#define DCU_INT_STATUS_P3_FIFO_HI_FLAG_MASK      0x20000u
#define DCU_INT_STATUS_P3_FIFO_HI_FLAG_SHIFT     17
#define DCU_INT_STATUS_P4_FIFO_LO_FLAG_MASK      0x40000u
#define DCU_INT_STATUS_P4_FIFO_LO_FLAG_SHIFT     18
#define DCU_INT_STATUS_P4_FIFO_HI_FLAG_MASK      0x80000u
#define DCU_INT_STATUS_P4_FIFO_HI_FLAG_SHIFT     19
#define DCU_INT_STATUS_P5_FIFO_LO_FLAG_MASK      0x100000u
#define DCU_INT_STATUS_P5_FIFO_LO_FLAG_SHIFT     20
#define DCU_INT_STATUS_P5_FIFO_HI_FLAG_MASK      0x200000u
#define DCU_INT_STATUS_P5_FIFO_HI_FLAG_SHIFT     21
#define DCU_INT_STATUS_P6_FIFO_LO_FLAG_MASK      0x400000u
#define DCU_INT_STATUS_P6_FIFO_LO_FLAG_SHIFT     22
#define DCU_INT_STATUS_P6_FIFO_HI_FLAG_MASK      0x800000u
#define DCU_INT_STATUS_P6_FIFO_HI_FLAG_SHIFT     23
#define DCU_INT_STATUS_P1_EMPTY_MASK             0x4000000u
#define DCU_INT_STATUS_P1_EMPTY_SHIFT            26
#define DCU_INT_STATUS_P2_EMPTY_MASK             0x8000000u
#define DCU_INT_STATUS_P2_EMPTY_SHIFT            27
#define DCU_INT_STATUS_P3_EMPTY_MASK             0x10000000u
#define DCU_INT_STATUS_P3_EMPTY_SHIFT            28
#define DCU_INT_STATUS_P4_EMPTY_MASK             0x20000000u
#define DCU_INT_STATUS_P4_EMPTY_SHIFT            29
#define DCU_INT_STATUS_P5_EMPTY_MASK             0x40000000u
#define DCU_INT_STATUS_P5_EMPTY_SHIFT            30
#define DCU_INT_STATUS_P6_EMPTY_MASK             0x80000000u
#define DCU_INT_STATUS_P6_EMPTY_SHIFT            31
/* INT_MASK Bit Fields */
#define DCU_INT_MASK_M_VSYNC_MASK                0x1u
#define DCU_INT_MASK_M_VSYNC_SHIFT               0
#define DCU_INT_MASK_M_UNDRUN_MASK               0x2u
#define DCU_INT_MASK_M_UNDRUN_SHIFT              1
#define DCU_INT_MASK_M_LS_BF_VS_MASK             0x4u
#define DCU_INT_MASK_M_LS_BF_VS_SHIFT            2
#define DCU_INT_MASK_M_VS_BLANK_MASK             0x8u
#define DCU_INT_MASK_M_VS_BLANK_SHIFT            3
#define DCU_INT_MASK_M_CRC_READY_MASK            0x10u
#define DCU_INT_MASK_M_CRC_READY_SHIFT           4
#define DCU_INT_MASK_M_CRC_OVERFLOW_MASK         0x20u
#define DCU_INT_MASK_M_CRC_OVERFLOW_SHIFT        5
#define DCU_INT_MASK_M_P1_FIFO_LO_FLAG_MASK      0x40u
#define DCU_INT_MASK_M_P1_FIFO_LO_FLAG_SHIFT     6
#define DCU_INT_MASK_M_P1_FIFO_HI_FLAG_MASK      0x80u
#define DCU_INT_MASK_M_P1_FIFO_HI_FLAG_SHIFT     7
#define DCU_INT_MASK_M_P2_FIFO_LO_FLAG_MASK      0x100u
#define DCU_INT_MASK_M_P2_FIFO_LO_FLAG_SHIFT     8
#define DCU_INT_MASK_M_P2_FIFO_HI_FLAG_MASK      0x200u
#define DCU_INT_MASK_M_P2_FIFO_HI_FLAG_SHIFT     9
#define DCU_INT_MASK_M_PROG_END_MASK             0x400u
#define DCU_INT_MASK_M_PROG_END_SHIFT            10
#define DCU_INT_MASK_M_IPM_ERROR_MASK            0x800u
#define DCU_INT_MASK_M_IPM_ERROR_SHIFT           11
#define DCU_INT_MASK_M_LYR_TRANS_FINISH_MASK     0x1000u
#define DCU_INT_MASK_M_LYR_TRANS_FINISH_SHIFT    12
#define DCU_INT_MASK_M_DMA_TRANS_FINISH_MASK     0x4000u
#define DCU_INT_MASK_M_DMA_TRANS_FINISH_SHIFT    14
#define DCU_INT_MASK_M_P3_FIFO_LO_FLAG_MASK      0x10000u
#define DCU_INT_MASK_M_P3_FIFO_LO_FLAG_SHIFT     16
#define DCU_INT_MASK_M_P3_FIFO_HI_FLAG_MASK      0x20000u
#define DCU_INT_MASK_M_P3_FIFO_HI_FLAG_SHIFT     17
#define DCU_INT_MASK_M_P4_FIFO_LO_FLAG_MASK      0x40000u
#define DCU_INT_MASK_M_P4_FIFO_LO_FLAG_SHIFT     18
#define DCU_INT_MASK_M_P4_FIFO_HI_FLAG_MASK      0x80000u
#define DCU_INT_MASK_M_P4_FIFO_HI_FLAG_SHIFT     19
#define DCU_INT_MASK_M_P5_FIFO_LO_FLAG_MASK      0x100000u
#define DCU_INT_MASK_M_P5_FIFO_LO_FLAG_SHIFT     20
#define DCU_INT_MASK_M_P5_FIFO_HI_FLAG_MASK      0x200000u
#define DCU_INT_MASK_M_P5_FIFO_HI_FLAG_SHIFT     21
#define DCU_INT_MASK_M_P6_FIFO_LO_FLAG_MASK      0x400000u
#define DCU_INT_MASK_M_P6_FIFO_LO_FLAG_SHIFT     22
#define DCU_INT_MASK_M_P6_FIFO_HI_FLAG_MASK      0x800000u
#define DCU_INT_MASK_M_P6_FIFO_HI_FLAG_SHIFT     23
#define DCU_INT_MASK_M_P1_EMPTY_MASK             0x4000000u
#define DCU_INT_MASK_M_P1_EMPTY_SHIFT            26
#define DCU_INT_MASK_M_P2_EMPTY_MASK             0x8000000u
#define DCU_INT_MASK_M_P2_EMPTY_SHIFT            27
#define DCU_INT_MASK_M_P3_EMPTY_MASK             0x10000000u
#define DCU_INT_MASK_M_P3_EMPTY_SHIFT            28
#define DCU_INT_MASK_M_P4_EMPTY_MASK             0x20000000u
#define DCU_INT_MASK_M_P4_EMPTY_SHIFT            29
#define DCU_INT_MASK_M_P5_EMPTY_MASK             0x40000000u
#define DCU_INT_MASK_M_P5_EMPTY_SHIFT            30
#define DCU_INT_MASK_M_P6_EMPTY_MASK             0x80000000u
#define DCU_INT_MASK_M_P6_EMPTY_SHIFT            31
/* COLBAR_1 Bit Fields */
#define DCU_COLBAR_1_COLBAR_1_B_MASK             0xFFu
#define DCU_COLBAR_1_COLBAR_1_B_SHIFT            0
#define DCU_COLBAR_1_COLBAR_1_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_1_COLBAR_1_B_SHIFT))&DCU_COLBAR_1_COLBAR_1_B_MASK)
#define DCU_COLBAR_1_COLBAR_1_G_MASK             0xFF00u
#define DCU_COLBAR_1_COLBAR_1_G_SHIFT            8
#define DCU_COLBAR_1_COLBAR_1_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_1_COLBAR_1_G_SHIFT))&DCU_COLBAR_1_COLBAR_1_G_MASK)
#define DCU_COLBAR_1_COLBAR_1_R_MASK             0xFF0000u
#define DCU_COLBAR_1_COLBAR_1_R_SHIFT            16
#define DCU_COLBAR_1_COLBAR_1_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_1_COLBAR_1_R_SHIFT))&DCU_COLBAR_1_COLBAR_1_R_MASK)
/* COLBAR_2 Bit Fields */
#define DCU_COLBAR_2_COLBAR_2_B_MASK             0xFFu
#define DCU_COLBAR_2_COLBAR_2_B_SHIFT            0
#define DCU_COLBAR_2_COLBAR_2_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_2_COLBAR_2_B_SHIFT))&DCU_COLBAR_2_COLBAR_2_B_MASK)
#define DCU_COLBAR_2_COLBAR_2_G_MASK             0xFF00u
#define DCU_COLBAR_2_COLBAR_2_G_SHIFT            8
#define DCU_COLBAR_2_COLBAR_2_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_2_COLBAR_2_G_SHIFT))&DCU_COLBAR_2_COLBAR_2_G_MASK)
#define DCU_COLBAR_2_COLBAR_2_R_MASK             0xFF0000u
#define DCU_COLBAR_2_COLBAR_2_R_SHIFT            16
#define DCU_COLBAR_2_COLBAR_2_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_2_COLBAR_2_R_SHIFT))&DCU_COLBAR_2_COLBAR_2_R_MASK)
/* COLBAR_3 Bit Fields */
#define DCU_COLBAR_3_COLBAR_3_B_MASK             0xFFu
#define DCU_COLBAR_3_COLBAR_3_B_SHIFT            0
#define DCU_COLBAR_3_COLBAR_3_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_3_COLBAR_3_B_SHIFT))&DCU_COLBAR_3_COLBAR_3_B_MASK)
#define DCU_COLBAR_3_COLBAR_3_G_MASK             0xFF00u
#define DCU_COLBAR_3_COLBAR_3_G_SHIFT            8
#define DCU_COLBAR_3_COLBAR_3_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_3_COLBAR_3_G_SHIFT))&DCU_COLBAR_3_COLBAR_3_G_MASK)
#define DCU_COLBAR_3_COLBAR_3_R_MASK             0xFF0000u
#define DCU_COLBAR_3_COLBAR_3_R_SHIFT            16
#define DCU_COLBAR_3_COLBAR_3_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_3_COLBAR_3_R_SHIFT))&DCU_COLBAR_3_COLBAR_3_R_MASK)
/* COLBAR_4 Bit Fields */
#define DCU_COLBAR_4_COLBAR_4_B_MASK             0xFFu
#define DCU_COLBAR_4_COLBAR_4_B_SHIFT            0
#define DCU_COLBAR_4_COLBAR_4_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_4_COLBAR_4_B_SHIFT))&DCU_COLBAR_4_COLBAR_4_B_MASK)
#define DCU_COLBAR_4_COLBAR_4_G_MASK             0xFF00u
#define DCU_COLBAR_4_COLBAR_4_G_SHIFT            8
#define DCU_COLBAR_4_COLBAR_4_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_4_COLBAR_4_G_SHIFT))&DCU_COLBAR_4_COLBAR_4_G_MASK)
#define DCU_COLBAR_4_COLBAR_4_R_MASK             0xFF0000u
#define DCU_COLBAR_4_COLBAR_4_R_SHIFT            16
#define DCU_COLBAR_4_COLBAR_4_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_4_COLBAR_4_R_SHIFT))&DCU_COLBAR_4_COLBAR_4_R_MASK)
/* COLBAR_5 Bit Fields */
#define DCU_COLBAR_5_COLBAR_5_B_MASK             0xFFu
#define DCU_COLBAR_5_COLBAR_5_B_SHIFT            0
#define DCU_COLBAR_5_COLBAR_5_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_5_COLBAR_5_B_SHIFT))&DCU_COLBAR_5_COLBAR_5_B_MASK)
#define DCU_COLBAR_5_COLBAR_5_G_MASK             0xFF00u
#define DCU_COLBAR_5_COLBAR_5_G_SHIFT            8
#define DCU_COLBAR_5_COLBAR_5_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_5_COLBAR_5_G_SHIFT))&DCU_COLBAR_5_COLBAR_5_G_MASK)
#define DCU_COLBAR_5_COLBAR_5_R_MASK             0xFF0000u
#define DCU_COLBAR_5_COLBAR_5_R_SHIFT            16
#define DCU_COLBAR_5_COLBAR_5_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_5_COLBAR_5_R_SHIFT))&DCU_COLBAR_5_COLBAR_5_R_MASK)
/* COLBAR_6 Bit Fields */
#define DCU_COLBAR_6_COLBAR_6_B_MASK             0xFFu
#define DCU_COLBAR_6_COLBAR_6_B_SHIFT            0
#define DCU_COLBAR_6_COLBAR_6_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_6_COLBAR_6_B_SHIFT))&DCU_COLBAR_6_COLBAR_6_B_MASK)
#define DCU_COLBAR_6_COLBAR_6_G_MASK             0xFF00u
#define DCU_COLBAR_6_COLBAR_6_G_SHIFT            8
#define DCU_COLBAR_6_COLBAR_6_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_6_COLBAR_6_G_SHIFT))&DCU_COLBAR_6_COLBAR_6_G_MASK)
#define DCU_COLBAR_6_COLBAR_6_R_MASK             0xFF0000u
#define DCU_COLBAR_6_COLBAR_6_R_SHIFT            16
#define DCU_COLBAR_6_COLBAR_6_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_6_COLBAR_6_R_SHIFT))&DCU_COLBAR_6_COLBAR_6_R_MASK)
/* COLBAR_7 Bit Fields */
#define DCU_COLBAR_7_COLBAR_7_B_MASK             0xFFu
#define DCU_COLBAR_7_COLBAR_7_B_SHIFT            0
#define DCU_COLBAR_7_COLBAR_7_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_7_COLBAR_7_B_SHIFT))&DCU_COLBAR_7_COLBAR_7_B_MASK)
#define DCU_COLBAR_7_COLBAR_7_G_MASK             0xFF00u
#define DCU_COLBAR_7_COLBAR_7_G_SHIFT            8
#define DCU_COLBAR_7_COLBAR_7_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_7_COLBAR_7_G_SHIFT))&DCU_COLBAR_7_COLBAR_7_G_MASK)
#define DCU_COLBAR_7_COLBAR_7_R_MASK             0xFF0000u
#define DCU_COLBAR_7_COLBAR_7_R_SHIFT            16
#define DCU_COLBAR_7_COLBAR_7_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_7_COLBAR_7_R_SHIFT))&DCU_COLBAR_7_COLBAR_7_R_MASK)
/* COLBAR_8 Bit Fields */
#define DCU_COLBAR_8_COLBAR_8_B_MASK             0xFFu
#define DCU_COLBAR_8_COLBAR_8_B_SHIFT            0
#define DCU_COLBAR_8_COLBAR_8_B(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_8_COLBAR_8_B_SHIFT))&DCU_COLBAR_8_COLBAR_8_B_MASK)
#define DCU_COLBAR_8_COLBAR_8_G_MASK             0xFF00u
#define DCU_COLBAR_8_COLBAR_8_G_SHIFT            8
#define DCU_COLBAR_8_COLBAR_8_G(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_8_COLBAR_8_G_SHIFT))&DCU_COLBAR_8_COLBAR_8_G_MASK)
#define DCU_COLBAR_8_COLBAR_8_R_MASK             0xFF0000u
#define DCU_COLBAR_8_COLBAR_8_R_SHIFT            16
#define DCU_COLBAR_8_COLBAR_8_R(x)               (((uint32_t)(((uint32_t)(x))<<DCU_COLBAR_8_COLBAR_8_R_SHIFT))&DCU_COLBAR_8_COLBAR_8_R_MASK)
/* DIV_RATIO Bit Fields */
#define DCU_DIV_RATIO_DIV_RATIO_MASK             0xFFu
#define DCU_DIV_RATIO_DIV_RATIO_SHIFT            0
#define DCU_DIV_RATIO_DIV_RATIO(x)               (((uint32_t)(((uint32_t)(x))<<DCU_DIV_RATIO_DIV_RATIO_SHIFT))&DCU_DIV_RATIO_DIV_RATIO_MASK)
/* SIGN_CALC_1 Bit Fields */
#define DCU_SIGN_CALC_1_SIG_HOR_SIZE_MASK        0x7FFu
#define DCU_SIGN_CALC_1_SIG_HOR_SIZE_SHIFT       0
#define DCU_SIGN_CALC_1_SIG_HOR_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<DCU_SIGN_CALC_1_SIG_HOR_SIZE_SHIFT))&DCU_SIGN_CALC_1_SIG_HOR_SIZE_MASK)
#define DCU_SIGN_CALC_1_SIG_VER_SIZE_MASK        0x7FF0000u
#define DCU_SIGN_CALC_1_SIG_VER_SIZE_SHIFT       16
#define DCU_SIGN_CALC_1_SIG_VER_SIZE(x)          (((uint32_t)(((uint32_t)(x))<<DCU_SIGN_CALC_1_SIG_VER_SIZE_SHIFT))&DCU_SIGN_CALC_1_SIG_VER_SIZE_MASK)
/* SIGN_CALC_2 Bit Fields */
#define DCU_SIGN_CALC_2_SIG_HOR_POS_MASK         0x7FFu
#define DCU_SIGN_CALC_2_SIG_HOR_POS_SHIFT        0
#define DCU_SIGN_CALC_2_SIG_HOR_POS(x)           (((uint32_t)(((uint32_t)(x))<<DCU_SIGN_CALC_2_SIG_HOR_POS_SHIFT))&DCU_SIGN_CALC_2_SIG_HOR_POS_MASK)
#define DCU_SIGN_CALC_2_SIG_VER_POS_MASK         0x7FF0000u
#define DCU_SIGN_CALC_2_SIG_VER_POS_SHIFT        16
#define DCU_SIGN_CALC_2_SIG_VER_POS(x)           (((uint32_t)(((uint32_t)(x))<<DCU_SIGN_CALC_2_SIG_VER_POS_SHIFT))&DCU_SIGN_CALC_2_SIG_VER_POS_MASK)
/* CRC_VAL Bit Fields */
#define DCU_CRC_VAL_CRC_VAL_MASK                 0xFFFFFFFFu
#define DCU_CRC_VAL_CRC_VAL_SHIFT                0
#define DCU_CRC_VAL_CRC_VAL(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CRC_VAL_CRC_VAL_SHIFT))&DCU_CRC_VAL_CRC_VAL_MASK)
/* PDI_STATUS Bit Fields */
#define DCU_PDI_STATUS_PDI_CLK_DET_MASK          0x1u
#define DCU_PDI_STATUS_PDI_CLK_DET_SHIFT         0
#define DCU_PDI_STATUS_PDI_CLK_LOST_MASK         0x2u
#define DCU_PDI_STATUS_PDI_CLK_LOST_SHIFT        1
#define DCU_PDI_STATUS_PDI_DE_DET_MASK           0x4u
#define DCU_PDI_STATUS_PDI_DE_DET_SHIFT          2
#define DCU_PDI_STATUS_PDI_HSYNC_DET_MASK        0x8u
#define DCU_PDI_STATUS_PDI_HSYNC_DET_SHIFT       3
#define DCU_PDI_STATUS_PDI_VSYNC_DET_MASK        0x10u
#define DCU_PDI_STATUS_PDI_VSYNC_DET_SHIFT       4
#define DCU_PDI_STATUS_PDI_LOCK_DET_MASK         0x20u
#define DCU_PDI_STATUS_PDI_LOCK_DET_SHIFT        5
#define DCU_PDI_STATUS_PDI_LOCK_LOST_MASK        0x40u
#define DCU_PDI_STATUS_PDI_LOCK_LOST_SHIFT       6
#define DCU_PDI_STATUS_PDI_ECC_ERR1_MASK         0x80u
#define DCU_PDI_STATUS_PDI_ECC_ERR1_SHIFT        7
#define DCU_PDI_STATUS_PDI_ECC_ERR2_MASK         0x100u
#define DCU_PDI_STATUS_PDI_ECC_ERR2_SHIFT        8
#define DCU_PDI_STATUS_PDI_BLANKING_ERR_MASK     0x200u
#define DCU_PDI_STATUS_PDI_BLANKING_ERR_SHIFT    9
/* PDI_STA_MSK Bit Fields */
#define DCU_PDI_STA_MSK_M_PDI_CLK_DET_MASK       0x1u
#define DCU_PDI_STA_MSK_M_PDI_CLK_DET_SHIFT      0
#define DCU_PDI_STA_MSK_M_PDI_CLK_LOST_MASK      0x2u
#define DCU_PDI_STA_MSK_M_PDI_CLK_LOST_SHIFT     1
#define DCU_PDI_STA_MSK_M_PDI_DE_DET_MASK        0x4u
#define DCU_PDI_STA_MSK_M_PDI_DE_DET_SHIFT       2
#define DCU_PDI_STA_MSK_M_PDI_HSYNC_DET_MASK     0x8u
#define DCU_PDI_STA_MSK_M_PDI_HSYNC_DET_SHIFT    3
#define DCU_PDI_STA_MSK_M_PDI_VSYNC_DET_MASK     0x10u
#define DCU_PDI_STA_MSK_M_PDI_VSYNC_DET_SHIFT    4
#define DCU_PDI_STA_MSK_M_PDI_LOCK_DET_MASK      0x20u
#define DCU_PDI_STA_MSK_M_PDI_LOCK_DET_SHIFT     5
#define DCU_PDI_STA_MSK_M_PDI_LOCK_LOST_MASK     0x40u
#define DCU_PDI_STA_MSK_M_PDI_LOCK_LOST_SHIFT    6
#define DCU_PDI_STA_MSK_M_PDI_ECC_ERR1_MASK      0x80u
#define DCU_PDI_STA_MSK_M_PDI_ECC_ERR1_SHIFT     7
#define DCU_PDI_STA_MSK_M_PDI_ECC_ERR2_MASK      0x100u
#define DCU_PDI_STA_MSK_M_PDI_ECC_ERR2_SHIFT     8
#define DCU_PDI_STA_MSK_M_PDI_BLANKING_ERR_MASK  0x200u
#define DCU_PDI_STA_MSK_M_PDI_BLANKING_ERR_SHIFT 9
/* PARR_ERR_STATUS1 Bit Fields */
#define DCU_PARR_ERR_STATUS1_L_MASK              0xFFFFFFFFu
#define DCU_PARR_ERR_STATUS1_L_SHIFT             0
#define DCU_PARR_ERR_STATUS1_L(x)                (((uint32_t)(((uint32_t)(x))<<DCU_PARR_ERR_STATUS1_L_SHIFT))&DCU_PARR_ERR_STATUS1_L_MASK)
/* PARR_ERR_STATUS2 Bit Fields */
#define DCU_PARR_ERR_STATUS2_L_MASK              0xFFFFFFFFu
#define DCU_PARR_ERR_STATUS2_L_SHIFT             0
#define DCU_PARR_ERR_STATUS2_L(x)                (((uint32_t)(((uint32_t)(x))<<DCU_PARR_ERR_STATUS2_L_SHIFT))&DCU_PARR_ERR_STATUS2_L_MASK)
/* PARR_ERR_STATUS3 Bit Fields */
#define DCU_PARR_ERR_STATUS3_DISP_ERR_MASK       0x1u
#define DCU_PARR_ERR_STATUS3_DISP_ERR_SHIFT      0
#define DCU_PARR_ERR_STATUS3_SIG_ERR_MASK        0x2u
#define DCU_PARR_ERR_STATUS3_SIG_ERR_SHIFT       1
#define DCU_PARR_ERR_STATUS3_HWC_ERR_MASK        0x4u
#define DCU_PARR_ERR_STATUS3_HWC_ERR_SHIFT       2
#define DCU_PARR_ERR_STATUS3_RLE_ERR_MASK        0x8u
#define DCU_PARR_ERR_STATUS3_RLE_ERR_SHIFT       3
/* MASK_PARR_ERR_STATUS1 Bit Fields */
#define DCU_MASK_PARR_ERR_STATUS1_M_L_PARR_ERR_MASK 0xFFFFFFFFu
#define DCU_MASK_PARR_ERR_STATUS1_M_L_PARR_ERR_SHIFT 0
#define DCU_MASK_PARR_ERR_STATUS1_M_L_PARR_ERR(x) (((uint32_t)(((uint32_t)(x))<<DCU_MASK_PARR_ERR_STATUS1_M_L_PARR_ERR_SHIFT))&DCU_MASK_PARR_ERR_STATUS1_M_L_PARR_ERR_MASK)
/* MASK_PARR_ERR_STATUS2 Bit Fields */
#define DCU_MASK_PARR_ERR_STATUS2_M_L_PARR_ERR_MASK 0xFFFFFFFFu
#define DCU_MASK_PARR_ERR_STATUS2_M_L_PARR_ERR_SHIFT 0
#define DCU_MASK_PARR_ERR_STATUS2_M_L_PARR_ERR(x) (((uint32_t)(((uint32_t)(x))<<DCU_MASK_PARR_ERR_STATUS2_M_L_PARR_ERR_SHIFT))&DCU_MASK_PARR_ERR_STATUS2_M_L_PARR_ERR_MASK)
/* MASK_PARR_ERR_STATUS3 Bit Fields */
#define DCU_MASK_PARR_ERR_STATUS3_M_DISP_ERR_MASK 0x1u
#define DCU_MASK_PARR_ERR_STATUS3_M_DISP_ERR_SHIFT 0
#define DCU_MASK_PARR_ERR_STATUS3_M_SIG_ERR_MASK 0x2u
#define DCU_MASK_PARR_ERR_STATUS3_M_SIG_ERR_SHIFT 1
#define DCU_MASK_PARR_ERR_STATUS3_M_HWC_ERR_MASK 0x4u
#define DCU_MASK_PARR_ERR_STATUS3_M_HWC_ERR_SHIFT 2
#define DCU_MASK_PARR_ERR_STATUS3_M_RLE_ERR_MASK 0x8u
#define DCU_MASK_PARR_ERR_STATUS3_M_RLE_ERR_SHIFT 3
/* THRESHOLD_INP_BUF_1 Bit Fields */
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_LO_MASK 0x7Fu
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_LO_SHIFT 0
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_LO(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_LO_SHIFT))&DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_LO_MASK)
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_HI_MASK 0x7F00u
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_HI_SHIFT 8
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_HI(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_HI_SHIFT))&DCU_THRESHOLD_INP_BUF_1_INP_BUF_P1_HI_MASK)
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_LO_MASK 0x7F0000u
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_LO_SHIFT 16
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_LO(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_LO_SHIFT))&DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_LO_MASK)
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_HI_MASK 0x7F000000u
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_HI_SHIFT 24
#define DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_HI(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_HI_SHIFT))&DCU_THRESHOLD_INP_BUF_1_INP_BUF_P2_HI_MASK)
/* THRESHOLD_INP_BUF_2 Bit Fields */
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_LO_MASK 0x7Fu
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_LO_SHIFT 0
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_LO(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_LO_SHIFT))&DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_LO_MASK)
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_HI_MASK 0x7F00u
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_HI_SHIFT 8
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_HI(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_HI_SHIFT))&DCU_THRESHOLD_INP_BUF_2_INP_BUF_P3_HI_MASK)
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_LO_MASK 0x7F0000u
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_LO_SHIFT 16
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_LO(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_LO_SHIFT))&DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_LO_MASK)
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_HI_MASK 0x7F000000u
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_HI_SHIFT 24
#define DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_HI(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_HI_SHIFT))&DCU_THRESHOLD_INP_BUF_2_INP_BUF_P4_HI_MASK)
/* THRESHOLD_INP_BUF_3 Bit Fields */
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_LO_MASK 0x7Fu
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_LO_SHIFT 0
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_LO(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_LO_SHIFT))&DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_LO_MASK)
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_HI_MASK 0x7F00u
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_HI_SHIFT 8
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_HI(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_HI_SHIFT))&DCU_THRESHOLD_INP_BUF_3_INP_BUF_P5_HI_MASK)
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_LO_MASK 0x7F0000u
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_LO_SHIFT 16
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_LO(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_LO_SHIFT))&DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_LO_MASK)
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_HI_MASK 0x7F000000u
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_HI_SHIFT 24
#define DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_HI(x) (((uint32_t)(((uint32_t)(x))<<DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_HI_SHIFT))&DCU_THRESHOLD_INP_BUF_3_INP_BUF_P6_HI_MASK)
/* LUMA_COMP Bit Fields */
#define DCU_LUMA_COMP_Y_BLUE_MASK                0x3FFu
#define DCU_LUMA_COMP_Y_BLUE_SHIFT               0
#define DCU_LUMA_COMP_Y_BLUE(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_LUMA_COMP_Y_BLUE_SHIFT))&DCU_LUMA_COMP_Y_BLUE_MASK)
#define DCU_LUMA_COMP_Y_GREEN_MASK               0x1FF800u
#define DCU_LUMA_COMP_Y_GREEN_SHIFT              11
#define DCU_LUMA_COMP_Y_GREEN(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_LUMA_COMP_Y_GREEN_SHIFT))&DCU_LUMA_COMP_Y_GREEN_MASK)
#define DCU_LUMA_COMP_Y_RED_MASK                 0xFFC00000u
#define DCU_LUMA_COMP_Y_RED_SHIFT                22
#define DCU_LUMA_COMP_Y_RED(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_LUMA_COMP_Y_RED_SHIFT))&DCU_LUMA_COMP_Y_RED_MASK)
/* CHROMA_RED Bit Fields */
#define DCU_CHROMA_RED_CB_RED_MASK               0xFFFu
#define DCU_CHROMA_RED_CB_RED_SHIFT              0
#define DCU_CHROMA_RED_CB_RED(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CHROMA_RED_CB_RED_SHIFT))&DCU_CHROMA_RED_CB_RED_MASK)
#define DCU_CHROMA_RED_CR_RED_MASK               0x7FF0000u
#define DCU_CHROMA_RED_CR_RED_SHIFT              16
#define DCU_CHROMA_RED_CR_RED(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CHROMA_RED_CR_RED_SHIFT))&DCU_CHROMA_RED_CR_RED_MASK)
/* CHROMA_GREEN Bit Fields */
#define DCU_CHROMA_GREEN_CB_GREEN_MASK           0xFFFu
#define DCU_CHROMA_GREEN_CB_GREEN_SHIFT          0
#define DCU_CHROMA_GREEN_CB_GREEN(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CHROMA_GREEN_CB_GREEN_SHIFT))&DCU_CHROMA_GREEN_CB_GREEN_MASK)
#define DCU_CHROMA_GREEN_CR_GREEN_MASK           0x7FF0000u
#define DCU_CHROMA_GREEN_CR_GREEN_SHIFT          16
#define DCU_CHROMA_GREEN_CR_GREEN(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CHROMA_GREEN_CR_GREEN_SHIFT))&DCU_CHROMA_GREEN_CR_GREEN_MASK)
/* CHROMA_BLUE Bit Fields */
#define DCU_CHROMA_BLUE_CB_BLUE_MASK             0xFFFu
#define DCU_CHROMA_BLUE_CB_BLUE_SHIFT            0
#define DCU_CHROMA_BLUE_CB_BLUE(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CHROMA_BLUE_CB_BLUE_SHIFT))&DCU_CHROMA_BLUE_CB_BLUE_MASK)
#define DCU_CHROMA_BLUE_CR_BLUE_MASK             0x7FF0000u
#define DCU_CHROMA_BLUE_CR_BLUE_SHIFT            16
#define DCU_CHROMA_BLUE_CR_BLUE(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CHROMA_BLUE_CR_BLUE_SHIFT))&DCU_CHROMA_BLUE_CR_BLUE_MASK)
/* CRC_POS Bit Fields */
#define DCU_CRC_POS_CRC_POS_MASK                 0xFFFFFFFFu
#define DCU_CRC_POS_CRC_POS_SHIFT                0
#define DCU_CRC_POS_CRC_POS(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CRC_POS_CRC_POS_SHIFT))&DCU_CRC_POS_CRC_POS_MASK)
/* LYR_INTPOL_EN Bit Fields */
#define DCU_LYR_INTPOL_EN_EN_MASK                0x80000000u
#define DCU_LYR_INTPOL_EN_EN_SHIFT               31
/* LYR_LUMA_COMP Bit Fields */
#define DCU_LYR_LUMA_COMP_Y_BLUE_MASK            0x3FFu
#define DCU_LYR_LUMA_COMP_Y_BLUE_SHIFT           0
#define DCU_LYR_LUMA_COMP_Y_BLUE(x)              (((uint32_t)(((uint32_t)(x))<<DCU_LYR_LUMA_COMP_Y_BLUE_SHIFT))&DCU_LYR_LUMA_COMP_Y_BLUE_MASK)
#define DCU_LYR_LUMA_COMP_Y_GREEN_MASK           0x1FF800u
#define DCU_LYR_LUMA_COMP_Y_GREEN_SHIFT          11
#define DCU_LYR_LUMA_COMP_Y_GREEN(x)             (((uint32_t)(((uint32_t)(x))<<DCU_LYR_LUMA_COMP_Y_GREEN_SHIFT))&DCU_LYR_LUMA_COMP_Y_GREEN_MASK)
#define DCU_LYR_LUMA_COMP_Y_RED_MASK             0xFFC00000u
#define DCU_LYR_LUMA_COMP_Y_RED_SHIFT            22
#define DCU_LYR_LUMA_COMP_Y_RED(x)               (((uint32_t)(((uint32_t)(x))<<DCU_LYR_LUMA_COMP_Y_RED_SHIFT))&DCU_LYR_LUMA_COMP_Y_RED_MASK)
/* LYR_CHRM_RED Bit Fields */
#define DCU_LYR_CHRM_RED_Cb_RED_MASK             0xFFFu
#define DCU_LYR_CHRM_RED_Cb_RED_SHIFT            0
#define DCU_LYR_CHRM_RED_Cb_RED(x)               (((uint32_t)(((uint32_t)(x))<<DCU_LYR_CHRM_RED_Cb_RED_SHIFT))&DCU_LYR_CHRM_RED_Cb_RED_MASK)
#define DCU_LYR_CHRM_RED_Cr_RED_MASK             0x7FF0000u
#define DCU_LYR_CHRM_RED_Cr_RED_SHIFT            16
#define DCU_LYR_CHRM_RED_Cr_RED(x)               (((uint32_t)(((uint32_t)(x))<<DCU_LYR_CHRM_RED_Cr_RED_SHIFT))&DCU_LYR_CHRM_RED_Cr_RED_MASK)
/* LYR_CHRM_GRN Bit Fields */
#define DCU_LYR_CHRM_GRN_Cb_GREEN_MASK           0xFFFu
#define DCU_LYR_CHRM_GRN_Cb_GREEN_SHIFT          0
#define DCU_LYR_CHRM_GRN_Cb_GREEN(x)             (((uint32_t)(((uint32_t)(x))<<DCU_LYR_CHRM_GRN_Cb_GREEN_SHIFT))&DCU_LYR_CHRM_GRN_Cb_GREEN_MASK)
#define DCU_LYR_CHRM_GRN_Cr_GREEN_MASK           0x7FF0000u
#define DCU_LYR_CHRM_GRN_Cr_GREEN_SHIFT          16
#define DCU_LYR_CHRM_GRN_Cr_GREEN(x)             (((uint32_t)(((uint32_t)(x))<<DCU_LYR_CHRM_GRN_Cr_GREEN_SHIFT))&DCU_LYR_CHRM_GRN_Cr_GREEN_MASK)
/* LYR_CHRM_BLUE Bit Fields */
#define DCU_LYR_CHRM_BLUE_Cb_BLUE_MASK           0xFFFu
#define DCU_LYR_CHRM_BLUE_Cb_BLUE_SHIFT          0
#define DCU_LYR_CHRM_BLUE_Cb_BLUE(x)             (((uint32_t)(((uint32_t)(x))<<DCU_LYR_CHRM_BLUE_Cb_BLUE_SHIFT))&DCU_LYR_CHRM_BLUE_Cb_BLUE_MASK)
#define DCU_LYR_CHRM_BLUE_Cr_BLUE_MASK           0x7FF0000u
#define DCU_LYR_CHRM_BLUE_Cr_BLUE_SHIFT          16
#define DCU_LYR_CHRM_BLUE_Cr_BLUE(x)             (((uint32_t)(((uint32_t)(x))<<DCU_LYR_CHRM_BLUE_Cr_BLUE_SHIFT))&DCU_LYR_CHRM_BLUE_Cr_BLUE_MASK)
/* COMP_IMSIZE Bit Fields */
#define DCU_COMP_IMSIZE_COMP_IMSIZE_MASK         0x3FFFFFu
#define DCU_COMP_IMSIZE_COMP_IMSIZE_SHIFT        0
#define DCU_COMP_IMSIZE_COMP_IMSIZE(x)           (((uint32_t)(((uint32_t)(x))<<DCU_COMP_IMSIZE_COMP_IMSIZE_SHIFT))&DCU_COMP_IMSIZE_COMP_IMSIZE_MASK)
/* UPDATE_MODE Bit Fields */
#define DCU_UPDATE_MODE_READREG_MASK             0x40000000u
#define DCU_UPDATE_MODE_READREG_SHIFT            30
#define DCU_UPDATE_MODE_MODE_MASK                0x80000000u
#define DCU_UPDATE_MODE_MODE_SHIFT               31
/* UNDERRUN Bit Fields */
#define DCU_UNDERRUN_PIXEL_MASK                  0x7FFu
#define DCU_UNDERRUN_PIXEL_SHIFT                 0
#define DCU_UNDERRUN_PIXEL(x)                    (((uint32_t)(((uint32_t)(x))<<DCU_UNDERRUN_PIXEL_SHIFT))&DCU_UNDERRUN_PIXEL_MASK)
#define DCU_UNDERRUN_LINE_MASK                   0x7FF0000u
#define DCU_UNDERRUN_LINE_SHIFT                  16
#define DCU_UNDERRUN_LINE(x)                     (((uint32_t)(((uint32_t)(x))<<DCU_UNDERRUN_LINE_SHIFT))&DCU_UNDERRUN_LINE_MASK)
/* CTRLDESCL0_0 Bit Fields */
#define DCU_CTRLDESCL0_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL0_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL0_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_0_WIDTH_SHIFT))&DCU_CTRLDESCL0_0_WIDTH_MASK)
#define DCU_CTRLDESCL0_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL0_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL0_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_0_HEIGHT_SHIFT))&DCU_CTRLDESCL0_0_HEIGHT_MASK)
/* CTRLDESCL0_1 Bit Fields */
#define DCU_CTRLDESCL0_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL0_1_POSX_SHIFT              0
#define DCU_CTRLDESCL0_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_1_POSX_SHIFT))&DCU_CTRLDESCL0_1_POSX_MASK)
#define DCU_CTRLDESCL0_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL0_1_POSY_SHIFT              16
#define DCU_CTRLDESCL0_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_1_POSY_SHIFT))&DCU_CTRLDESCL0_1_POSY_MASK)
/* CTRLDESCL0_2 Bit Fields */
#define DCU_CTRLDESCL0_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL0_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL0_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_2_ADDR_SHIFT))&DCU_CTRLDESCL0_2_ADDR_MASK)
/* CTRLDESCL0_3 Bit Fields */
#define DCU_CTRLDESCL0_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL0_3_AB_SHIFT                0
#define DCU_CTRLDESCL0_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_3_AB_SHIFT))&DCU_CTRLDESCL0_3_AB_MASK)
#define DCU_CTRLDESCL0_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL0_3_BB_SHIFT                2
#define DCU_CTRLDESCL0_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL0_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL0_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_3_LUOFFS_SHIFT))&DCU_CTRLDESCL0_3_LUOFFS_MASK)
#define DCU_CTRLDESCL0_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL0_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL0_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL0_3_BPP_SHIFT               16
#define DCU_CTRLDESCL0_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_3_BPP_SHIFT))&DCU_CTRLDESCL0_3_BPP_MASK)
#define DCU_CTRLDESCL0_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL0_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL0_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_3_TRANS_SHIFT))&DCU_CTRLDESCL0_3_TRANS_MASK)
#define DCU_CTRLDESCL0_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL0_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL0_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL0_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL0_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL0_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL0_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL0_3_EN_SHIFT                31
/* CTRLDESCL0_4 Bit Fields */
#define DCU_CTRLDESCL0_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL0_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL0_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL0_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL0_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL0_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL0_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL0_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL0_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL0_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL0_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL0_4_CKMAX_R_MASK)
/* CTRLDESCL0_5 Bit Fields */
#define DCU_CTRLDESCL0_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL0_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL0_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL0_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL0_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL0_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL0_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL0_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL0_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL0_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL0_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL0_5_CKMIN_R_MASK)
/* CTRLDESCL0_6 Bit Fields */
#define DCU_CTRLDESCL0_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL0_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL0_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL0_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL0_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL0_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL0_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL0_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL0_7 Bit Fields */
#define DCU_CTRLDESCL0_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL0_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL0_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL0_7_FGn_FCOLOR_MASK)
/* CTRLDESCL0_8 Bit Fields */
#define DCU_CTRLDESCL0_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL0_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL0_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL0_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL0_8_FGn_BCOLOR_MASK)
/* CTRLDESCL1_0 Bit Fields */
#define DCU_CTRLDESCL1_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL1_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL1_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_0_WIDTH_SHIFT))&DCU_CTRLDESCL1_0_WIDTH_MASK)
#define DCU_CTRLDESCL1_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL1_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL1_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_0_HEIGHT_SHIFT))&DCU_CTRLDESCL1_0_HEIGHT_MASK)
/* CTRLDESCL1_1 Bit Fields */
#define DCU_CTRLDESCL1_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL1_1_POSX_SHIFT              0
#define DCU_CTRLDESCL1_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_1_POSX_SHIFT))&DCU_CTRLDESCL1_1_POSX_MASK)
#define DCU_CTRLDESCL1_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL1_1_POSY_SHIFT              16
#define DCU_CTRLDESCL1_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_1_POSY_SHIFT))&DCU_CTRLDESCL1_1_POSY_MASK)
/* CTRLDESCL1_2 Bit Fields */
#define DCU_CTRLDESCL1_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL1_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL1_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_2_ADDR_SHIFT))&DCU_CTRLDESCL1_2_ADDR_MASK)
/* CTRLDESCL1_3 Bit Fields */
#define DCU_CTRLDESCL1_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL1_3_AB_SHIFT                0
#define DCU_CTRLDESCL1_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_3_AB_SHIFT))&DCU_CTRLDESCL1_3_AB_MASK)
#define DCU_CTRLDESCL1_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL1_3_BB_SHIFT                2
#define DCU_CTRLDESCL1_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL1_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL1_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_3_LUOFFS_SHIFT))&DCU_CTRLDESCL1_3_LUOFFS_MASK)
#define DCU_CTRLDESCL1_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL1_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL1_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL1_3_BPP_SHIFT               16
#define DCU_CTRLDESCL1_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_3_BPP_SHIFT))&DCU_CTRLDESCL1_3_BPP_MASK)
#define DCU_CTRLDESCL1_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL1_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL1_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_3_TRANS_SHIFT))&DCU_CTRLDESCL1_3_TRANS_MASK)
#define DCU_CTRLDESCL1_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL1_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL1_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL1_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL1_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL1_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL1_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL1_3_EN_SHIFT                31
/* CTRLDESCL1_4 Bit Fields */
#define DCU_CTRLDESCL1_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL1_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL1_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL1_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL1_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL1_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL1_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL1_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL1_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL1_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL1_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL1_4_CKMAX_R_MASK)
/* CTRLDESCL1_5 Bit Fields */
#define DCU_CTRLDESCL1_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL1_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL1_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL1_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL1_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL1_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL1_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL1_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL1_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL1_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL1_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL1_5_CKMIN_R_MASK)
/* CTRLDESCL1_6 Bit Fields */
#define DCU_CTRLDESCL1_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL1_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL1_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL1_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL1_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL1_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL1_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL1_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL1_7 Bit Fields */
#define DCU_CTRLDESCL1_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL1_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL1_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL1_7_FGn_FCOLOR_MASK)
/* CTRLDESCL1_8 Bit Fields */
#define DCU_CTRLDESCL1_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL1_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL1_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL1_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL1_8_FGn_BCOLOR_MASK)
/* CTRLDESCL2_0 Bit Fields */
#define DCU_CTRLDESCL2_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL2_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL2_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_0_WIDTH_SHIFT))&DCU_CTRLDESCL2_0_WIDTH_MASK)
#define DCU_CTRLDESCL2_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL2_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL2_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_0_HEIGHT_SHIFT))&DCU_CTRLDESCL2_0_HEIGHT_MASK)
/* CTRLDESCL2_1 Bit Fields */
#define DCU_CTRLDESCL2_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL2_1_POSX_SHIFT              0
#define DCU_CTRLDESCL2_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_1_POSX_SHIFT))&DCU_CTRLDESCL2_1_POSX_MASK)
#define DCU_CTRLDESCL2_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL2_1_POSY_SHIFT              16
#define DCU_CTRLDESCL2_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_1_POSY_SHIFT))&DCU_CTRLDESCL2_1_POSY_MASK)
/* CTRLDESCL2_2 Bit Fields */
#define DCU_CTRLDESCL2_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL2_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL2_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_2_ADDR_SHIFT))&DCU_CTRLDESCL2_2_ADDR_MASK)
/* CTRLDESCL2_3 Bit Fields */
#define DCU_CTRLDESCL2_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL2_3_AB_SHIFT                0
#define DCU_CTRLDESCL2_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_3_AB_SHIFT))&DCU_CTRLDESCL2_3_AB_MASK)
#define DCU_CTRLDESCL2_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL2_3_BB_SHIFT                2
#define DCU_CTRLDESCL2_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL2_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL2_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_3_LUOFFS_SHIFT))&DCU_CTRLDESCL2_3_LUOFFS_MASK)
#define DCU_CTRLDESCL2_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL2_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL2_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL2_3_BPP_SHIFT               16
#define DCU_CTRLDESCL2_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_3_BPP_SHIFT))&DCU_CTRLDESCL2_3_BPP_MASK)
#define DCU_CTRLDESCL2_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL2_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL2_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_3_TRANS_SHIFT))&DCU_CTRLDESCL2_3_TRANS_MASK)
#define DCU_CTRLDESCL2_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL2_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL2_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL2_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL2_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL2_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL2_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL2_3_EN_SHIFT                31
/* CTRLDESCL2_4 Bit Fields */
#define DCU_CTRLDESCL2_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL2_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL2_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL2_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL2_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL2_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL2_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL2_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL2_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL2_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL2_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL2_4_CKMAX_R_MASK)
/* CTRLDESCL2_5 Bit Fields */
#define DCU_CTRLDESCL2_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL2_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL2_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL2_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL2_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL2_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL2_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL2_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL2_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL2_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL2_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL2_5_CKMIN_R_MASK)
/* CTRLDESCL2_6 Bit Fields */
#define DCU_CTRLDESCL2_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL2_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL2_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL2_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL2_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL2_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL2_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL2_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL2_7 Bit Fields */
#define DCU_CTRLDESCL2_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL2_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL2_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL2_7_FGn_FCOLOR_MASK)
/* CTRLDESCL2_8 Bit Fields */
#define DCU_CTRLDESCL2_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL2_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL2_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL2_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL2_8_FGn_BCOLOR_MASK)
/* CTRLDESCL3_0 Bit Fields */
#define DCU_CTRLDESCL3_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL3_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL3_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_0_WIDTH_SHIFT))&DCU_CTRLDESCL3_0_WIDTH_MASK)
#define DCU_CTRLDESCL3_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL3_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL3_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_0_HEIGHT_SHIFT))&DCU_CTRLDESCL3_0_HEIGHT_MASK)
/* CTRLDESCL3_1 Bit Fields */
#define DCU_CTRLDESCL3_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL3_1_POSX_SHIFT              0
#define DCU_CTRLDESCL3_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_1_POSX_SHIFT))&DCU_CTRLDESCL3_1_POSX_MASK)
#define DCU_CTRLDESCL3_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL3_1_POSY_SHIFT              16
#define DCU_CTRLDESCL3_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_1_POSY_SHIFT))&DCU_CTRLDESCL3_1_POSY_MASK)
/* CTRLDESCL3_2 Bit Fields */
#define DCU_CTRLDESCL3_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL3_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL3_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_2_ADDR_SHIFT))&DCU_CTRLDESCL3_2_ADDR_MASK)
/* CTRLDESCL3_3 Bit Fields */
#define DCU_CTRLDESCL3_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL3_3_AB_SHIFT                0
#define DCU_CTRLDESCL3_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_3_AB_SHIFT))&DCU_CTRLDESCL3_3_AB_MASK)
#define DCU_CTRLDESCL3_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL3_3_BB_SHIFT                2
#define DCU_CTRLDESCL3_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL3_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL3_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_3_LUOFFS_SHIFT))&DCU_CTRLDESCL3_3_LUOFFS_MASK)
#define DCU_CTRLDESCL3_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL3_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL3_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL3_3_BPP_SHIFT               16
#define DCU_CTRLDESCL3_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_3_BPP_SHIFT))&DCU_CTRLDESCL3_3_BPP_MASK)
#define DCU_CTRLDESCL3_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL3_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL3_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_3_TRANS_SHIFT))&DCU_CTRLDESCL3_3_TRANS_MASK)
#define DCU_CTRLDESCL3_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL3_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL3_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL3_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL3_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL3_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL3_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL3_3_EN_SHIFT                31
/* CTRLDESCL3_4 Bit Fields */
#define DCU_CTRLDESCL3_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL3_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL3_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL3_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL3_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL3_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL3_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL3_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL3_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL3_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL3_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL3_4_CKMAX_R_MASK)
/* CTRLDESCL3_5 Bit Fields */
#define DCU_CTRLDESCL3_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL3_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL3_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL3_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL3_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL3_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL3_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL3_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL3_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL3_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL3_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL3_5_CKMIN_R_MASK)
/* CTRLDESCL3_6 Bit Fields */
#define DCU_CTRLDESCL3_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL3_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL3_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL3_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL3_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL3_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL3_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL3_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL3_7 Bit Fields */
#define DCU_CTRLDESCL3_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL3_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL3_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL3_7_FGn_FCOLOR_MASK)
/* CTRLDESCL3_8 Bit Fields */
#define DCU_CTRLDESCL3_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL3_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL3_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL3_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL3_8_FGn_BCOLOR_MASK)
/* CTRLDESCL4_0 Bit Fields */
#define DCU_CTRLDESCL4_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL4_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL4_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_0_WIDTH_SHIFT))&DCU_CTRLDESCL4_0_WIDTH_MASK)
#define DCU_CTRLDESCL4_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL4_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL4_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_0_HEIGHT_SHIFT))&DCU_CTRLDESCL4_0_HEIGHT_MASK)
/* CTRLDESCL4_1 Bit Fields */
#define DCU_CTRLDESCL4_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL4_1_POSX_SHIFT              0
#define DCU_CTRLDESCL4_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_1_POSX_SHIFT))&DCU_CTRLDESCL4_1_POSX_MASK)
#define DCU_CTRLDESCL4_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL4_1_POSY_SHIFT              16
#define DCU_CTRLDESCL4_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_1_POSY_SHIFT))&DCU_CTRLDESCL4_1_POSY_MASK)
/* CTRLDESCL4_2 Bit Fields */
#define DCU_CTRLDESCL4_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL4_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL4_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_2_ADDR_SHIFT))&DCU_CTRLDESCL4_2_ADDR_MASK)
/* CTRLDESCL4_3 Bit Fields */
#define DCU_CTRLDESCL4_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL4_3_AB_SHIFT                0
#define DCU_CTRLDESCL4_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_3_AB_SHIFT))&DCU_CTRLDESCL4_3_AB_MASK)
#define DCU_CTRLDESCL4_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL4_3_BB_SHIFT                2
#define DCU_CTRLDESCL4_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL4_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL4_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_3_LUOFFS_SHIFT))&DCU_CTRLDESCL4_3_LUOFFS_MASK)
#define DCU_CTRLDESCL4_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL4_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL4_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL4_3_BPP_SHIFT               16
#define DCU_CTRLDESCL4_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_3_BPP_SHIFT))&DCU_CTRLDESCL4_3_BPP_MASK)
#define DCU_CTRLDESCL4_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL4_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL4_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_3_TRANS_SHIFT))&DCU_CTRLDESCL4_3_TRANS_MASK)
#define DCU_CTRLDESCL4_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL4_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL4_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL4_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL4_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL4_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL4_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL4_3_EN_SHIFT                31
/* CTRLDESCL4_4 Bit Fields */
#define DCU_CTRLDESCL4_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL4_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL4_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL4_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL4_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL4_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL4_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL4_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL4_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL4_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL4_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL4_4_CKMAX_R_MASK)
/* CTRLDESCL4_5 Bit Fields */
#define DCU_CTRLDESCL4_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL4_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL4_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL4_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL4_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL4_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL4_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL4_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL4_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL4_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL4_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL4_5_CKMIN_R_MASK)
/* CTRLDESCL4_6 Bit Fields */
#define DCU_CTRLDESCL4_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL4_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL4_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL4_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL4_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL4_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL4_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL4_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL4_7 Bit Fields */
#define DCU_CTRLDESCL4_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL4_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL4_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL4_7_FGn_FCOLOR_MASK)
/* CTRLDESCL4_8 Bit Fields */
#define DCU_CTRLDESCL4_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL4_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL4_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL4_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL4_8_FGn_BCOLOR_MASK)
/* CTRLDESCL5_0 Bit Fields */
#define DCU_CTRLDESCL5_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL5_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL5_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_0_WIDTH_SHIFT))&DCU_CTRLDESCL5_0_WIDTH_MASK)
#define DCU_CTRLDESCL5_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL5_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL5_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_0_HEIGHT_SHIFT))&DCU_CTRLDESCL5_0_HEIGHT_MASK)
/* CTRLDESCL5_1 Bit Fields */
#define DCU_CTRLDESCL5_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL5_1_POSX_SHIFT              0
#define DCU_CTRLDESCL5_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_1_POSX_SHIFT))&DCU_CTRLDESCL5_1_POSX_MASK)
#define DCU_CTRLDESCL5_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL5_1_POSY_SHIFT              16
#define DCU_CTRLDESCL5_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_1_POSY_SHIFT))&DCU_CTRLDESCL5_1_POSY_MASK)
/* CTRLDESCL5_2 Bit Fields */
#define DCU_CTRLDESCL5_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL5_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL5_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_2_ADDR_SHIFT))&DCU_CTRLDESCL5_2_ADDR_MASK)
/* CTRLDESCL5_3 Bit Fields */
#define DCU_CTRLDESCL5_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL5_3_AB_SHIFT                0
#define DCU_CTRLDESCL5_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_3_AB_SHIFT))&DCU_CTRLDESCL5_3_AB_MASK)
#define DCU_CTRLDESCL5_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL5_3_BB_SHIFT                2
#define DCU_CTRLDESCL5_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL5_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL5_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_3_LUOFFS_SHIFT))&DCU_CTRLDESCL5_3_LUOFFS_MASK)
#define DCU_CTRLDESCL5_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL5_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL5_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL5_3_BPP_SHIFT               16
#define DCU_CTRLDESCL5_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_3_BPP_SHIFT))&DCU_CTRLDESCL5_3_BPP_MASK)
#define DCU_CTRLDESCL5_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL5_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL5_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_3_TRANS_SHIFT))&DCU_CTRLDESCL5_3_TRANS_MASK)
#define DCU_CTRLDESCL5_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL5_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL5_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL5_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL5_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL5_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL5_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL5_3_EN_SHIFT                31
/* CTRLDESCL5_4 Bit Fields */
#define DCU_CTRLDESCL5_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL5_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL5_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL5_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL5_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL5_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL5_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL5_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL5_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL5_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL5_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL5_4_CKMAX_R_MASK)
/* CTRLDESCL5_5 Bit Fields */
#define DCU_CTRLDESCL5_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL5_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL5_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL5_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL5_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL5_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL5_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL5_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL5_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL5_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL5_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL5_5_CKMIN_R_MASK)
/* CTRLDESCL5_6 Bit Fields */
#define DCU_CTRLDESCL5_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL5_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL5_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL5_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL5_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL5_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL5_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL5_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL5_7 Bit Fields */
#define DCU_CTRLDESCL5_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL5_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL5_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL5_7_FGn_FCOLOR_MASK)
/* CTRLDESCL5_8 Bit Fields */
#define DCU_CTRLDESCL5_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL5_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL5_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL5_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL5_8_FGn_BCOLOR_MASK)
/* CTRLDESCL6_0 Bit Fields */
#define DCU_CTRLDESCL6_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL6_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL6_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_0_WIDTH_SHIFT))&DCU_CTRLDESCL6_0_WIDTH_MASK)
#define DCU_CTRLDESCL6_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL6_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL6_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_0_HEIGHT_SHIFT))&DCU_CTRLDESCL6_0_HEIGHT_MASK)
/* CTRLDESCL6_1 Bit Fields */
#define DCU_CTRLDESCL6_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL6_1_POSX_SHIFT              0
#define DCU_CTRLDESCL6_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_1_POSX_SHIFT))&DCU_CTRLDESCL6_1_POSX_MASK)
#define DCU_CTRLDESCL6_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL6_1_POSY_SHIFT              16
#define DCU_CTRLDESCL6_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_1_POSY_SHIFT))&DCU_CTRLDESCL6_1_POSY_MASK)
/* CTRLDESCL6_2 Bit Fields */
#define DCU_CTRLDESCL6_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL6_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL6_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_2_ADDR_SHIFT))&DCU_CTRLDESCL6_2_ADDR_MASK)
/* CTRLDESCL6_3 Bit Fields */
#define DCU_CTRLDESCL6_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL6_3_AB_SHIFT                0
#define DCU_CTRLDESCL6_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_3_AB_SHIFT))&DCU_CTRLDESCL6_3_AB_MASK)
#define DCU_CTRLDESCL6_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL6_3_BB_SHIFT                2
#define DCU_CTRLDESCL6_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL6_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL6_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_3_LUOFFS_SHIFT))&DCU_CTRLDESCL6_3_LUOFFS_MASK)
#define DCU_CTRLDESCL6_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL6_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL6_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL6_3_BPP_SHIFT               16
#define DCU_CTRLDESCL6_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_3_BPP_SHIFT))&DCU_CTRLDESCL6_3_BPP_MASK)
#define DCU_CTRLDESCL6_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL6_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL6_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_3_TRANS_SHIFT))&DCU_CTRLDESCL6_3_TRANS_MASK)
#define DCU_CTRLDESCL6_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL6_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL6_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL6_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL6_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL6_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL6_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL6_3_EN_SHIFT                31
/* CTRLDESCL6_4 Bit Fields */
#define DCU_CTRLDESCL6_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL6_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL6_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL6_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL6_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL6_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL6_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL6_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL6_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL6_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL6_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL6_4_CKMAX_R_MASK)
/* CTRLDESCL6_5 Bit Fields */
#define DCU_CTRLDESCL6_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL6_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL6_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL6_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL6_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL6_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL6_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL6_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL6_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL6_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL6_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL6_5_CKMIN_R_MASK)
/* CTRLDESCL6_6 Bit Fields */
#define DCU_CTRLDESCL6_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL6_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL6_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL6_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL6_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL6_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL6_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL6_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL6_7 Bit Fields */
#define DCU_CTRLDESCL6_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL6_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL6_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL6_7_FGn_FCOLOR_MASK)
/* CTRLDESCL6_8 Bit Fields */
#define DCU_CTRLDESCL6_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL6_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL6_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL6_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL6_8_FGn_BCOLOR_MASK)
/* CTRLDESCL7_0 Bit Fields */
#define DCU_CTRLDESCL7_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL7_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL7_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_0_WIDTH_SHIFT))&DCU_CTRLDESCL7_0_WIDTH_MASK)
#define DCU_CTRLDESCL7_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL7_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL7_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_0_HEIGHT_SHIFT))&DCU_CTRLDESCL7_0_HEIGHT_MASK)
/* CTRLDESCL7_1 Bit Fields */
#define DCU_CTRLDESCL7_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL7_1_POSX_SHIFT              0
#define DCU_CTRLDESCL7_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_1_POSX_SHIFT))&DCU_CTRLDESCL7_1_POSX_MASK)
#define DCU_CTRLDESCL7_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL7_1_POSY_SHIFT              16
#define DCU_CTRLDESCL7_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_1_POSY_SHIFT))&DCU_CTRLDESCL7_1_POSY_MASK)
/* CTRLDESCL7_2 Bit Fields */
#define DCU_CTRLDESCL7_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL7_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL7_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_2_ADDR_SHIFT))&DCU_CTRLDESCL7_2_ADDR_MASK)
/* CTRLDESCL7_3 Bit Fields */
#define DCU_CTRLDESCL7_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL7_3_AB_SHIFT                0
#define DCU_CTRLDESCL7_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_3_AB_SHIFT))&DCU_CTRLDESCL7_3_AB_MASK)
#define DCU_CTRLDESCL7_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL7_3_BB_SHIFT                2
#define DCU_CTRLDESCL7_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL7_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL7_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_3_LUOFFS_SHIFT))&DCU_CTRLDESCL7_3_LUOFFS_MASK)
#define DCU_CTRLDESCL7_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL7_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL7_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL7_3_BPP_SHIFT               16
#define DCU_CTRLDESCL7_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_3_BPP_SHIFT))&DCU_CTRLDESCL7_3_BPP_MASK)
#define DCU_CTRLDESCL7_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL7_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL7_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_3_TRANS_SHIFT))&DCU_CTRLDESCL7_3_TRANS_MASK)
#define DCU_CTRLDESCL7_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL7_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL7_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL7_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL7_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL7_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL7_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL7_3_EN_SHIFT                31
/* CTRLDESCL7_4 Bit Fields */
#define DCU_CTRLDESCL7_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL7_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL7_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL7_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL7_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL7_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL7_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL7_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL7_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL7_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL7_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL7_4_CKMAX_R_MASK)
/* CTRLDESCL7_5 Bit Fields */
#define DCU_CTRLDESCL7_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL7_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL7_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL7_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL7_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL7_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL7_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL7_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL7_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL7_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL7_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL7_5_CKMIN_R_MASK)
/* CTRLDESCL7_6 Bit Fields */
#define DCU_CTRLDESCL7_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL7_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL7_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL7_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL7_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL7_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL7_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL7_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL7_7 Bit Fields */
#define DCU_CTRLDESCL7_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL7_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL7_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL7_7_FGn_FCOLOR_MASK)
/* CTRLDESCL7_8 Bit Fields */
#define DCU_CTRLDESCL7_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL7_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL7_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL7_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL7_8_FGn_BCOLOR_MASK)
/* CTRLDESCL8_0 Bit Fields */
#define DCU_CTRLDESCL8_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL8_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL8_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_0_WIDTH_SHIFT))&DCU_CTRLDESCL8_0_WIDTH_MASK)
#define DCU_CTRLDESCL8_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL8_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL8_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_0_HEIGHT_SHIFT))&DCU_CTRLDESCL8_0_HEIGHT_MASK)
/* CTRLDESCL8_1 Bit Fields */
#define DCU_CTRLDESCL8_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL8_1_POSX_SHIFT              0
#define DCU_CTRLDESCL8_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_1_POSX_SHIFT))&DCU_CTRLDESCL8_1_POSX_MASK)
#define DCU_CTRLDESCL8_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL8_1_POSY_SHIFT              16
#define DCU_CTRLDESCL8_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_1_POSY_SHIFT))&DCU_CTRLDESCL8_1_POSY_MASK)
/* CTRLDESCL8_2 Bit Fields */
#define DCU_CTRLDESCL8_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL8_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL8_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_2_ADDR_SHIFT))&DCU_CTRLDESCL8_2_ADDR_MASK)
/* CTRLDESCL8_3 Bit Fields */
#define DCU_CTRLDESCL8_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL8_3_AB_SHIFT                0
#define DCU_CTRLDESCL8_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_3_AB_SHIFT))&DCU_CTRLDESCL8_3_AB_MASK)
#define DCU_CTRLDESCL8_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL8_3_BB_SHIFT                2
#define DCU_CTRLDESCL8_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL8_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL8_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_3_LUOFFS_SHIFT))&DCU_CTRLDESCL8_3_LUOFFS_MASK)
#define DCU_CTRLDESCL8_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL8_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL8_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL8_3_BPP_SHIFT               16
#define DCU_CTRLDESCL8_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_3_BPP_SHIFT))&DCU_CTRLDESCL8_3_BPP_MASK)
#define DCU_CTRLDESCL8_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL8_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL8_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_3_TRANS_SHIFT))&DCU_CTRLDESCL8_3_TRANS_MASK)
#define DCU_CTRLDESCL8_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL8_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL8_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL8_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL8_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL8_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL8_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL8_3_EN_SHIFT                31
/* CTRLDESCL8_4 Bit Fields */
#define DCU_CTRLDESCL8_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL8_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL8_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL8_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL8_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL8_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL8_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL8_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL8_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL8_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL8_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL8_4_CKMAX_R_MASK)
/* CTRLDESCL8_5 Bit Fields */
#define DCU_CTRLDESCL8_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL8_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL8_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL8_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL8_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL8_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL8_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL8_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL8_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL8_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL8_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL8_5_CKMIN_R_MASK)
/* CTRLDESCL8_6 Bit Fields */
#define DCU_CTRLDESCL8_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL8_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL8_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL8_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL8_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL8_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL8_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL8_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL8_7 Bit Fields */
#define DCU_CTRLDESCL8_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL8_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL8_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL8_7_FGn_FCOLOR_MASK)
/* CTRLDESCL8_8 Bit Fields */
#define DCU_CTRLDESCL8_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL8_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL8_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL8_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL8_8_FGn_BCOLOR_MASK)
/* CTRLDESCL9_0 Bit Fields */
#define DCU_CTRLDESCL9_0_WIDTH_MASK              0x7FFu
#define DCU_CTRLDESCL9_0_WIDTH_SHIFT             0
#define DCU_CTRLDESCL9_0_WIDTH(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_0_WIDTH_SHIFT))&DCU_CTRLDESCL9_0_WIDTH_MASK)
#define DCU_CTRLDESCL9_0_HEIGHT_MASK             0x7FF0000u
#define DCU_CTRLDESCL9_0_HEIGHT_SHIFT            16
#define DCU_CTRLDESCL9_0_HEIGHT(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_0_HEIGHT_SHIFT))&DCU_CTRLDESCL9_0_HEIGHT_MASK)
/* CTRLDESCL9_1 Bit Fields */
#define DCU_CTRLDESCL9_1_POSX_MASK               0xFFFu
#define DCU_CTRLDESCL9_1_POSX_SHIFT              0
#define DCU_CTRLDESCL9_1_POSX(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_1_POSX_SHIFT))&DCU_CTRLDESCL9_1_POSX_MASK)
#define DCU_CTRLDESCL9_1_POSY_MASK               0xFFF0000u
#define DCU_CTRLDESCL9_1_POSY_SHIFT              16
#define DCU_CTRLDESCL9_1_POSY(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_1_POSY_SHIFT))&DCU_CTRLDESCL9_1_POSY_MASK)
/* CTRLDESCL9_2 Bit Fields */
#define DCU_CTRLDESCL9_2_ADDR_MASK               0xFFFFFFFFu
#define DCU_CTRLDESCL9_2_ADDR_SHIFT              0
#define DCU_CTRLDESCL9_2_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_2_ADDR_SHIFT))&DCU_CTRLDESCL9_2_ADDR_MASK)
/* CTRLDESCL9_3 Bit Fields */
#define DCU_CTRLDESCL9_3_AB_MASK                 0x3u
#define DCU_CTRLDESCL9_3_AB_SHIFT                0
#define DCU_CTRLDESCL9_3_AB(x)                   (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_3_AB_SHIFT))&DCU_CTRLDESCL9_3_AB_MASK)
#define DCU_CTRLDESCL9_3_BB_MASK                 0x4u
#define DCU_CTRLDESCL9_3_BB_SHIFT                2
#define DCU_CTRLDESCL9_3_LUOFFS_MASK             0x7FF0u
#define DCU_CTRLDESCL9_3_LUOFFS_SHIFT            4
#define DCU_CTRLDESCL9_3_LUOFFS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_3_LUOFFS_SHIFT))&DCU_CTRLDESCL9_3_LUOFFS_MASK)
#define DCU_CTRLDESCL9_3_RLE_EN_MASK             0x8000u
#define DCU_CTRLDESCL9_3_RLE_EN_SHIFT            15
#define DCU_CTRLDESCL9_3_BPP_MASK                0xF0000u
#define DCU_CTRLDESCL9_3_BPP_SHIFT               16
#define DCU_CTRLDESCL9_3_BPP(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_3_BPP_SHIFT))&DCU_CTRLDESCL9_3_BPP_MASK)
#define DCU_CTRLDESCL9_3_TRANS_MASK              0xFF00000u
#define DCU_CTRLDESCL9_3_TRANS_SHIFT             20
#define DCU_CTRLDESCL9_3_TRANS(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_3_TRANS_SHIFT))&DCU_CTRLDESCL9_3_TRANS_MASK)
#define DCU_CTRLDESCL9_3_SAFETY_EN_MASK          0x10000000u
#define DCU_CTRLDESCL9_3_SAFETY_EN_SHIFT         28
#define DCU_CTRLDESCL9_3_DATA_SEL_MASK           0x20000000u
#define DCU_CTRLDESCL9_3_DATA_SEL_SHIFT          29
#define DCU_CTRLDESCL9_3_TILE_EN_MASK            0x40000000u
#define DCU_CTRLDESCL9_3_TILE_EN_SHIFT           30
#define DCU_CTRLDESCL9_3_EN_MASK                 0x80000000u
#define DCU_CTRLDESCL9_3_EN_SHIFT                31
/* CTRLDESCL9_4 Bit Fields */
#define DCU_CTRLDESCL9_4_CKMAX_B_MASK            0xFFu
#define DCU_CTRLDESCL9_4_CKMAX_B_SHIFT           0
#define DCU_CTRLDESCL9_4_CKMAX_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL9_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL9_4_CKMAX_G_MASK            0xFF00u
#define DCU_CTRLDESCL9_4_CKMAX_G_SHIFT           8
#define DCU_CTRLDESCL9_4_CKMAX_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL9_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL9_4_CKMAX_R_MASK            0xFF0000u
#define DCU_CTRLDESCL9_4_CKMAX_R_SHIFT           16
#define DCU_CTRLDESCL9_4_CKMAX_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL9_4_CKMAX_R_MASK)
/* CTRLDESCL9_5 Bit Fields */
#define DCU_CTRLDESCL9_5_CKMIN_B_MASK            0xFFu
#define DCU_CTRLDESCL9_5_CKMIN_B_SHIFT           0
#define DCU_CTRLDESCL9_5_CKMIN_B(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL9_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL9_5_CKMIN_G_MASK            0xFF00u
#define DCU_CTRLDESCL9_5_CKMIN_G_SHIFT           8
#define DCU_CTRLDESCL9_5_CKMIN_G(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL9_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL9_5_CKMIN_R_MASK            0xFF0000u
#define DCU_CTRLDESCL9_5_CKMIN_R_SHIFT           16
#define DCU_CTRLDESCL9_5_CKMIN_R(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL9_5_CKMIN_R_MASK)
/* CTRLDESCL9_6 Bit Fields */
#define DCU_CTRLDESCL9_6_TILE_HOR_SIZE_MASK      0x7Fu
#define DCU_CTRLDESCL9_6_TILE_HOR_SIZE_SHIFT     0
#define DCU_CTRLDESCL9_6_TILE_HOR_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL9_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL9_6_TILE_VER_SIZE_MASK      0x7FF0000u
#define DCU_CTRLDESCL9_6_TILE_VER_SIZE_SHIFT     16
#define DCU_CTRLDESCL9_6_TILE_VER_SIZE(x)        (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL9_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL9_7 Bit Fields */
#define DCU_CTRLDESCL9_7_FGn_FCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL9_7_FGn_FCOLOR_SHIFT        0
#define DCU_CTRLDESCL9_7_FGn_FCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL9_7_FGn_FCOLOR_MASK)
/* CTRLDESCL9_8 Bit Fields */
#define DCU_CTRLDESCL9_8_FGn_BCOLOR_MASK         0xFFFFFFu
#define DCU_CTRLDESCL9_8_FGn_BCOLOR_SHIFT        0
#define DCU_CTRLDESCL9_8_FGn_BCOLOR(x)           (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL9_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL9_8_FGn_BCOLOR_MASK)
/* CTRLDESCL10_0 Bit Fields */
#define DCU_CTRLDESCL10_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL10_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL10_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_0_WIDTH_SHIFT))&DCU_CTRLDESCL10_0_WIDTH_MASK)
#define DCU_CTRLDESCL10_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL10_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL10_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_0_HEIGHT_SHIFT))&DCU_CTRLDESCL10_0_HEIGHT_MASK)
/* CTRLDESCL10_1 Bit Fields */
#define DCU_CTRLDESCL10_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL10_1_POSX_SHIFT             0
#define DCU_CTRLDESCL10_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_1_POSX_SHIFT))&DCU_CTRLDESCL10_1_POSX_MASK)
#define DCU_CTRLDESCL10_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL10_1_POSY_SHIFT             16
#define DCU_CTRLDESCL10_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_1_POSY_SHIFT))&DCU_CTRLDESCL10_1_POSY_MASK)
/* CTRLDESCL10_2 Bit Fields */
#define DCU_CTRLDESCL10_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL10_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL10_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_2_ADDR_SHIFT))&DCU_CTRLDESCL10_2_ADDR_MASK)
/* CTRLDESCL10_3 Bit Fields */
#define DCU_CTRLDESCL10_3_AB_MASK                0x3u
#define DCU_CTRLDESCL10_3_AB_SHIFT               0
#define DCU_CTRLDESCL10_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_3_AB_SHIFT))&DCU_CTRLDESCL10_3_AB_MASK)
#define DCU_CTRLDESCL10_3_BB_MASK                0x4u
#define DCU_CTRLDESCL10_3_BB_SHIFT               2
#define DCU_CTRLDESCL10_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL10_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL10_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_3_LUOFFS_SHIFT))&DCU_CTRLDESCL10_3_LUOFFS_MASK)
#define DCU_CTRLDESCL10_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL10_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL10_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL10_3_BPP_SHIFT              16
#define DCU_CTRLDESCL10_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_3_BPP_SHIFT))&DCU_CTRLDESCL10_3_BPP_MASK)
#define DCU_CTRLDESCL10_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL10_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL10_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_3_TRANS_SHIFT))&DCU_CTRLDESCL10_3_TRANS_MASK)
#define DCU_CTRLDESCL10_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL10_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL10_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL10_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL10_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL10_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL10_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL10_3_EN_SHIFT               31
/* CTRLDESCL10_4 Bit Fields */
#define DCU_CTRLDESCL10_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL10_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL10_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL10_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL10_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL10_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL10_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL10_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL10_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL10_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL10_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL10_4_CKMAX_R_MASK)
/* CTRLDESCL10_5 Bit Fields */
#define DCU_CTRLDESCL10_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL10_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL10_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL10_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL10_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL10_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL10_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL10_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL10_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL10_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL10_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL10_5_CKMIN_R_MASK)
/* CTRLDESCL10_6 Bit Fields */
#define DCU_CTRLDESCL10_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL10_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL10_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL10_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL10_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL10_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL10_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL10_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL10_7 Bit Fields */
#define DCU_CTRLDESCL10_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL10_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL10_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL10_7_FGn_FCOLOR_MASK)
/* CTRLDESCL10_8 Bit Fields */
#define DCU_CTRLDESCL10_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL10_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL10_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL10_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL10_8_FGn_BCOLOR_MASK)
/* CTRLDESCL11_0 Bit Fields */
#define DCU_CTRLDESCL11_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL11_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL11_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_0_WIDTH_SHIFT))&DCU_CTRLDESCL11_0_WIDTH_MASK)
#define DCU_CTRLDESCL11_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL11_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL11_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_0_HEIGHT_SHIFT))&DCU_CTRLDESCL11_0_HEIGHT_MASK)
/* CTRLDESCL11_1 Bit Fields */
#define DCU_CTRLDESCL11_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL11_1_POSX_SHIFT             0
#define DCU_CTRLDESCL11_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_1_POSX_SHIFT))&DCU_CTRLDESCL11_1_POSX_MASK)
#define DCU_CTRLDESCL11_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL11_1_POSY_SHIFT             16
#define DCU_CTRLDESCL11_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_1_POSY_SHIFT))&DCU_CTRLDESCL11_1_POSY_MASK)
/* CTRLDESCL11_2 Bit Fields */
#define DCU_CTRLDESCL11_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL11_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL11_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_2_ADDR_SHIFT))&DCU_CTRLDESCL11_2_ADDR_MASK)
/* CTRLDESCL11_3 Bit Fields */
#define DCU_CTRLDESCL11_3_AB_MASK                0x3u
#define DCU_CTRLDESCL11_3_AB_SHIFT               0
#define DCU_CTRLDESCL11_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_3_AB_SHIFT))&DCU_CTRLDESCL11_3_AB_MASK)
#define DCU_CTRLDESCL11_3_BB_MASK                0x4u
#define DCU_CTRLDESCL11_3_BB_SHIFT               2
#define DCU_CTRLDESCL11_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL11_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL11_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_3_LUOFFS_SHIFT))&DCU_CTRLDESCL11_3_LUOFFS_MASK)
#define DCU_CTRLDESCL11_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL11_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL11_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL11_3_BPP_SHIFT              16
#define DCU_CTRLDESCL11_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_3_BPP_SHIFT))&DCU_CTRLDESCL11_3_BPP_MASK)
#define DCU_CTRLDESCL11_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL11_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL11_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_3_TRANS_SHIFT))&DCU_CTRLDESCL11_3_TRANS_MASK)
#define DCU_CTRLDESCL11_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL11_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL11_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL11_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL11_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL11_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL11_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL11_3_EN_SHIFT               31
/* CTRLDESCL11_4 Bit Fields */
#define DCU_CTRLDESCL11_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL11_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL11_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL11_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL11_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL11_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL11_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL11_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL11_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL11_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL11_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL11_4_CKMAX_R_MASK)
/* CTRLDESCL11_5 Bit Fields */
#define DCU_CTRLDESCL11_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL11_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL11_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL11_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL11_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL11_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL11_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL11_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL11_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL11_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL11_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL11_5_CKMIN_R_MASK)
/* CTRLDESCL11_6 Bit Fields */
#define DCU_CTRLDESCL11_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL11_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL11_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL11_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL11_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL11_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL11_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL11_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL11_7 Bit Fields */
#define DCU_CTRLDESCL11_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL11_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL11_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL11_7_FGn_FCOLOR_MASK)
/* CTRLDESCL11_8 Bit Fields */
#define DCU_CTRLDESCL11_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL11_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL11_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL11_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL11_8_FGn_BCOLOR_MASK)
/* CTRLDESCL12_0 Bit Fields */
#define DCU_CTRLDESCL12_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL12_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL12_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_0_WIDTH_SHIFT))&DCU_CTRLDESCL12_0_WIDTH_MASK)
#define DCU_CTRLDESCL12_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL12_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL12_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_0_HEIGHT_SHIFT))&DCU_CTRLDESCL12_0_HEIGHT_MASK)
/* CTRLDESCL12_1 Bit Fields */
#define DCU_CTRLDESCL12_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL12_1_POSX_SHIFT             0
#define DCU_CTRLDESCL12_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_1_POSX_SHIFT))&DCU_CTRLDESCL12_1_POSX_MASK)
#define DCU_CTRLDESCL12_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL12_1_POSY_SHIFT             16
#define DCU_CTRLDESCL12_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_1_POSY_SHIFT))&DCU_CTRLDESCL12_1_POSY_MASK)
/* CTRLDESCL12_2 Bit Fields */
#define DCU_CTRLDESCL12_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL12_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL12_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_2_ADDR_SHIFT))&DCU_CTRLDESCL12_2_ADDR_MASK)
/* CTRLDESCL12_3 Bit Fields */
#define DCU_CTRLDESCL12_3_AB_MASK                0x3u
#define DCU_CTRLDESCL12_3_AB_SHIFT               0
#define DCU_CTRLDESCL12_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_3_AB_SHIFT))&DCU_CTRLDESCL12_3_AB_MASK)
#define DCU_CTRLDESCL12_3_BB_MASK                0x4u
#define DCU_CTRLDESCL12_3_BB_SHIFT               2
#define DCU_CTRLDESCL12_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL12_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL12_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_3_LUOFFS_SHIFT))&DCU_CTRLDESCL12_3_LUOFFS_MASK)
#define DCU_CTRLDESCL12_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL12_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL12_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL12_3_BPP_SHIFT              16
#define DCU_CTRLDESCL12_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_3_BPP_SHIFT))&DCU_CTRLDESCL12_3_BPP_MASK)
#define DCU_CTRLDESCL12_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL12_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL12_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_3_TRANS_SHIFT))&DCU_CTRLDESCL12_3_TRANS_MASK)
#define DCU_CTRLDESCL12_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL12_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL12_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL12_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL12_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL12_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL12_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL12_3_EN_SHIFT               31
/* CTRLDESCL12_4 Bit Fields */
#define DCU_CTRLDESCL12_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL12_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL12_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL12_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL12_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL12_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL12_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL12_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL12_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL12_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL12_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL12_4_CKMAX_R_MASK)
/* CTRLDESCL12_5 Bit Fields */
#define DCU_CTRLDESCL12_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL12_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL12_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL12_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL12_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL12_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL12_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL12_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL12_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL12_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL12_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL12_5_CKMIN_R_MASK)
/* CTRLDESCL12_6 Bit Fields */
#define DCU_CTRLDESCL12_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL12_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL12_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL12_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL12_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL12_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL12_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL12_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL12_7 Bit Fields */
#define DCU_CTRLDESCL12_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL12_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL12_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL12_7_FGn_FCOLOR_MASK)
/* CTRLDESCL12_8 Bit Fields */
#define DCU_CTRLDESCL12_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL12_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL12_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL12_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL12_8_FGn_BCOLOR_MASK)
/* CTRLDESCL13_0 Bit Fields */
#define DCU_CTRLDESCL13_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL13_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL13_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_0_WIDTH_SHIFT))&DCU_CTRLDESCL13_0_WIDTH_MASK)
#define DCU_CTRLDESCL13_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL13_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL13_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_0_HEIGHT_SHIFT))&DCU_CTRLDESCL13_0_HEIGHT_MASK)
/* CTRLDESCL13_1 Bit Fields */
#define DCU_CTRLDESCL13_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL13_1_POSX_SHIFT             0
#define DCU_CTRLDESCL13_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_1_POSX_SHIFT))&DCU_CTRLDESCL13_1_POSX_MASK)
#define DCU_CTRLDESCL13_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL13_1_POSY_SHIFT             16
#define DCU_CTRLDESCL13_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_1_POSY_SHIFT))&DCU_CTRLDESCL13_1_POSY_MASK)
/* CTRLDESCL13_2 Bit Fields */
#define DCU_CTRLDESCL13_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL13_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL13_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_2_ADDR_SHIFT))&DCU_CTRLDESCL13_2_ADDR_MASK)
/* CTRLDESCL13_3 Bit Fields */
#define DCU_CTRLDESCL13_3_AB_MASK                0x3u
#define DCU_CTRLDESCL13_3_AB_SHIFT               0
#define DCU_CTRLDESCL13_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_3_AB_SHIFT))&DCU_CTRLDESCL13_3_AB_MASK)
#define DCU_CTRLDESCL13_3_BB_MASK                0x4u
#define DCU_CTRLDESCL13_3_BB_SHIFT               2
#define DCU_CTRLDESCL13_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL13_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL13_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_3_LUOFFS_SHIFT))&DCU_CTRLDESCL13_3_LUOFFS_MASK)
#define DCU_CTRLDESCL13_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL13_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL13_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL13_3_BPP_SHIFT              16
#define DCU_CTRLDESCL13_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_3_BPP_SHIFT))&DCU_CTRLDESCL13_3_BPP_MASK)
#define DCU_CTRLDESCL13_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL13_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL13_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_3_TRANS_SHIFT))&DCU_CTRLDESCL13_3_TRANS_MASK)
#define DCU_CTRLDESCL13_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL13_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL13_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL13_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL13_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL13_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL13_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL13_3_EN_SHIFT               31
/* CTRLDESCL13_4 Bit Fields */
#define DCU_CTRLDESCL13_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL13_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL13_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL13_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL13_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL13_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL13_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL13_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL13_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL13_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL13_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL13_4_CKMAX_R_MASK)
/* CTRLDESCL13_5 Bit Fields */
#define DCU_CTRLDESCL13_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL13_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL13_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL13_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL13_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL13_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL13_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL13_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL13_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL13_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL13_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL13_5_CKMIN_R_MASK)
/* CTRLDESCL13_6 Bit Fields */
#define DCU_CTRLDESCL13_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL13_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL13_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL13_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL13_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL13_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL13_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL13_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL13_7 Bit Fields */
#define DCU_CTRLDESCL13_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL13_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL13_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL13_7_FGn_FCOLOR_MASK)
/* CTRLDESCL13_8 Bit Fields */
#define DCU_CTRLDESCL13_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL13_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL13_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL13_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL13_8_FGn_BCOLOR_MASK)
/* CTRLDESCL14_0 Bit Fields */
#define DCU_CTRLDESCL14_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL14_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL14_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_0_WIDTH_SHIFT))&DCU_CTRLDESCL14_0_WIDTH_MASK)
#define DCU_CTRLDESCL14_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL14_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL14_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_0_HEIGHT_SHIFT))&DCU_CTRLDESCL14_0_HEIGHT_MASK)
/* CTRLDESCL14_1 Bit Fields */
#define DCU_CTRLDESCL14_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL14_1_POSX_SHIFT             0
#define DCU_CTRLDESCL14_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_1_POSX_SHIFT))&DCU_CTRLDESCL14_1_POSX_MASK)
#define DCU_CTRLDESCL14_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL14_1_POSY_SHIFT             16
#define DCU_CTRLDESCL14_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_1_POSY_SHIFT))&DCU_CTRLDESCL14_1_POSY_MASK)
/* CTRLDESCL14_2 Bit Fields */
#define DCU_CTRLDESCL14_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL14_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL14_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_2_ADDR_SHIFT))&DCU_CTRLDESCL14_2_ADDR_MASK)
/* CTRLDESCL14_3 Bit Fields */
#define DCU_CTRLDESCL14_3_AB_MASK                0x3u
#define DCU_CTRLDESCL14_3_AB_SHIFT               0
#define DCU_CTRLDESCL14_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_3_AB_SHIFT))&DCU_CTRLDESCL14_3_AB_MASK)
#define DCU_CTRLDESCL14_3_BB_MASK                0x4u
#define DCU_CTRLDESCL14_3_BB_SHIFT               2
#define DCU_CTRLDESCL14_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL14_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL14_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_3_LUOFFS_SHIFT))&DCU_CTRLDESCL14_3_LUOFFS_MASK)
#define DCU_CTRLDESCL14_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL14_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL14_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL14_3_BPP_SHIFT              16
#define DCU_CTRLDESCL14_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_3_BPP_SHIFT))&DCU_CTRLDESCL14_3_BPP_MASK)
#define DCU_CTRLDESCL14_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL14_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL14_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_3_TRANS_SHIFT))&DCU_CTRLDESCL14_3_TRANS_MASK)
#define DCU_CTRLDESCL14_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL14_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL14_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL14_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL14_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL14_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL14_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL14_3_EN_SHIFT               31
/* CTRLDESCL14_4 Bit Fields */
#define DCU_CTRLDESCL14_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL14_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL14_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL14_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL14_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL14_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL14_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL14_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL14_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL14_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL14_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL14_4_CKMAX_R_MASK)
/* CTRLDESCL14_5 Bit Fields */
#define DCU_CTRLDESCL14_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL14_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL14_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL14_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL14_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL14_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL14_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL14_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL14_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL14_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL14_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL14_5_CKMIN_R_MASK)
/* CTRLDESCL14_6 Bit Fields */
#define DCU_CTRLDESCL14_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL14_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL14_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL14_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL14_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL14_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL14_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL14_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL14_7 Bit Fields */
#define DCU_CTRLDESCL14_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL14_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL14_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL14_7_FGn_FCOLOR_MASK)
/* CTRLDESCL14_8 Bit Fields */
#define DCU_CTRLDESCL14_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL14_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL14_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL14_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL14_8_FGn_BCOLOR_MASK)
/* CTRLDESCL15_0 Bit Fields */
#define DCU_CTRLDESCL15_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL15_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL15_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_0_WIDTH_SHIFT))&DCU_CTRLDESCL15_0_WIDTH_MASK)
#define DCU_CTRLDESCL15_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL15_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL15_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_0_HEIGHT_SHIFT))&DCU_CTRLDESCL15_0_HEIGHT_MASK)
/* CTRLDESCL15_1 Bit Fields */
#define DCU_CTRLDESCL15_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL15_1_POSX_SHIFT             0
#define DCU_CTRLDESCL15_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_1_POSX_SHIFT))&DCU_CTRLDESCL15_1_POSX_MASK)
#define DCU_CTRLDESCL15_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL15_1_POSY_SHIFT             16
#define DCU_CTRLDESCL15_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_1_POSY_SHIFT))&DCU_CTRLDESCL15_1_POSY_MASK)
/* CTRLDESCL15_2 Bit Fields */
#define DCU_CTRLDESCL15_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL15_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL15_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_2_ADDR_SHIFT))&DCU_CTRLDESCL15_2_ADDR_MASK)
/* CTRLDESCL15_3 Bit Fields */
#define DCU_CTRLDESCL15_3_AB_MASK                0x3u
#define DCU_CTRLDESCL15_3_AB_SHIFT               0
#define DCU_CTRLDESCL15_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_3_AB_SHIFT))&DCU_CTRLDESCL15_3_AB_MASK)
#define DCU_CTRLDESCL15_3_BB_MASK                0x4u
#define DCU_CTRLDESCL15_3_BB_SHIFT               2
#define DCU_CTRLDESCL15_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL15_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL15_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_3_LUOFFS_SHIFT))&DCU_CTRLDESCL15_3_LUOFFS_MASK)
#define DCU_CTRLDESCL15_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL15_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL15_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL15_3_BPP_SHIFT              16
#define DCU_CTRLDESCL15_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_3_BPP_SHIFT))&DCU_CTRLDESCL15_3_BPP_MASK)
#define DCU_CTRLDESCL15_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL15_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL15_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_3_TRANS_SHIFT))&DCU_CTRLDESCL15_3_TRANS_MASK)
#define DCU_CTRLDESCL15_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL15_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL15_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL15_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL15_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL15_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL15_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL15_3_EN_SHIFT               31
/* CTRLDESCL15_4 Bit Fields */
#define DCU_CTRLDESCL15_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL15_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL15_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL15_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL15_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL15_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL15_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL15_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL15_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL15_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL15_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL15_4_CKMAX_R_MASK)
/* CTRLDESCL15_5 Bit Fields */
#define DCU_CTRLDESCL15_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL15_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL15_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL15_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL15_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL15_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL15_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL15_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL15_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL15_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL15_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL15_5_CKMIN_R_MASK)
/* CTRLDESCL15_6 Bit Fields */
#define DCU_CTRLDESCL15_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL15_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL15_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL15_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL15_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL15_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL15_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL15_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL15_7 Bit Fields */
#define DCU_CTRLDESCL15_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL15_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL15_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL15_7_FGn_FCOLOR_MASK)
/* CTRLDESCL15_8 Bit Fields */
#define DCU_CTRLDESCL15_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL15_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL15_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL15_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL15_8_FGn_BCOLOR_MASK)
/* CTRLDESCL16_0 Bit Fields */
#define DCU_CTRLDESCL16_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL16_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL16_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_0_WIDTH_SHIFT))&DCU_CTRLDESCL16_0_WIDTH_MASK)
#define DCU_CTRLDESCL16_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL16_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL16_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_0_HEIGHT_SHIFT))&DCU_CTRLDESCL16_0_HEIGHT_MASK)
/* CTRLDESCL16_1 Bit Fields */
#define DCU_CTRLDESCL16_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL16_1_POSX_SHIFT             0
#define DCU_CTRLDESCL16_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_1_POSX_SHIFT))&DCU_CTRLDESCL16_1_POSX_MASK)
#define DCU_CTRLDESCL16_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL16_1_POSY_SHIFT             16
#define DCU_CTRLDESCL16_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_1_POSY_SHIFT))&DCU_CTRLDESCL16_1_POSY_MASK)
/* CTRLDESCL16_2 Bit Fields */
#define DCU_CTRLDESCL16_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL16_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL16_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_2_ADDR_SHIFT))&DCU_CTRLDESCL16_2_ADDR_MASK)
/* CTRLDESCL16_3 Bit Fields */
#define DCU_CTRLDESCL16_3_AB_MASK                0x3u
#define DCU_CTRLDESCL16_3_AB_SHIFT               0
#define DCU_CTRLDESCL16_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_3_AB_SHIFT))&DCU_CTRLDESCL16_3_AB_MASK)
#define DCU_CTRLDESCL16_3_BB_MASK                0x4u
#define DCU_CTRLDESCL16_3_BB_SHIFT               2
#define DCU_CTRLDESCL16_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL16_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL16_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_3_LUOFFS_SHIFT))&DCU_CTRLDESCL16_3_LUOFFS_MASK)
#define DCU_CTRLDESCL16_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL16_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL16_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL16_3_BPP_SHIFT              16
#define DCU_CTRLDESCL16_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_3_BPP_SHIFT))&DCU_CTRLDESCL16_3_BPP_MASK)
#define DCU_CTRLDESCL16_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL16_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL16_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_3_TRANS_SHIFT))&DCU_CTRLDESCL16_3_TRANS_MASK)
#define DCU_CTRLDESCL16_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL16_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL16_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL16_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL16_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL16_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL16_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL16_3_EN_SHIFT               31
/* CTRLDESCL16_4 Bit Fields */
#define DCU_CTRLDESCL16_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL16_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL16_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL16_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL16_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL16_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL16_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL16_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL16_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL16_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL16_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL16_4_CKMAX_R_MASK)
/* CTRLDESCL16_5 Bit Fields */
#define DCU_CTRLDESCL16_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL16_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL16_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL16_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL16_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL16_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL16_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL16_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL16_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL16_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL16_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL16_5_CKMIN_R_MASK)
/* CTRLDESCL16_6 Bit Fields */
#define DCU_CTRLDESCL16_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL16_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL16_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL16_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL16_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL16_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL16_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL16_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL16_7 Bit Fields */
#define DCU_CTRLDESCL16_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL16_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL16_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL16_7_FGn_FCOLOR_MASK)
/* CTRLDESCL16_8 Bit Fields */
#define DCU_CTRLDESCL16_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL16_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL16_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL16_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL16_8_FGn_BCOLOR_MASK)
/* CTRLDESCL17_0 Bit Fields */
#define DCU_CTRLDESCL17_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL17_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL17_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_0_WIDTH_SHIFT))&DCU_CTRLDESCL17_0_WIDTH_MASK)
#define DCU_CTRLDESCL17_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL17_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL17_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_0_HEIGHT_SHIFT))&DCU_CTRLDESCL17_0_HEIGHT_MASK)
/* CTRLDESCL17_1 Bit Fields */
#define DCU_CTRLDESCL17_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL17_1_POSX_SHIFT             0
#define DCU_CTRLDESCL17_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_1_POSX_SHIFT))&DCU_CTRLDESCL17_1_POSX_MASK)
#define DCU_CTRLDESCL17_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL17_1_POSY_SHIFT             16
#define DCU_CTRLDESCL17_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_1_POSY_SHIFT))&DCU_CTRLDESCL17_1_POSY_MASK)
/* CTRLDESCL17_2 Bit Fields */
#define DCU_CTRLDESCL17_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL17_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL17_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_2_ADDR_SHIFT))&DCU_CTRLDESCL17_2_ADDR_MASK)
/* CTRLDESCL17_3 Bit Fields */
#define DCU_CTRLDESCL17_3_AB_MASK                0x3u
#define DCU_CTRLDESCL17_3_AB_SHIFT               0
#define DCU_CTRLDESCL17_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_3_AB_SHIFT))&DCU_CTRLDESCL17_3_AB_MASK)
#define DCU_CTRLDESCL17_3_BB_MASK                0x4u
#define DCU_CTRLDESCL17_3_BB_SHIFT               2
#define DCU_CTRLDESCL17_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL17_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL17_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_3_LUOFFS_SHIFT))&DCU_CTRLDESCL17_3_LUOFFS_MASK)
#define DCU_CTRLDESCL17_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL17_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL17_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL17_3_BPP_SHIFT              16
#define DCU_CTRLDESCL17_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_3_BPP_SHIFT))&DCU_CTRLDESCL17_3_BPP_MASK)
#define DCU_CTRLDESCL17_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL17_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL17_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_3_TRANS_SHIFT))&DCU_CTRLDESCL17_3_TRANS_MASK)
#define DCU_CTRLDESCL17_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL17_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL17_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL17_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL17_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL17_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL17_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL17_3_EN_SHIFT               31
/* CTRLDESCL17_4 Bit Fields */
#define DCU_CTRLDESCL17_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL17_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL17_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL17_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL17_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL17_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL17_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL17_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL17_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL17_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL17_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL17_4_CKMAX_R_MASK)
/* CTRLDESCL17_5 Bit Fields */
#define DCU_CTRLDESCL17_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL17_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL17_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL17_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL17_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL17_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL17_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL17_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL17_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL17_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL17_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL17_5_CKMIN_R_MASK)
/* CTRLDESCL17_6 Bit Fields */
#define DCU_CTRLDESCL17_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL17_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL17_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL17_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL17_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL17_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL17_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL17_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL17_7 Bit Fields */
#define DCU_CTRLDESCL17_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL17_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL17_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL17_7_FGn_FCOLOR_MASK)
/* CTRLDESCL17_8 Bit Fields */
#define DCU_CTRLDESCL17_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL17_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL17_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL17_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL17_8_FGn_BCOLOR_MASK)
/* CTRLDESCL18_0 Bit Fields */
#define DCU_CTRLDESCL18_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL18_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL18_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_0_WIDTH_SHIFT))&DCU_CTRLDESCL18_0_WIDTH_MASK)
#define DCU_CTRLDESCL18_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL18_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL18_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_0_HEIGHT_SHIFT))&DCU_CTRLDESCL18_0_HEIGHT_MASK)
/* CTRLDESCL18_1 Bit Fields */
#define DCU_CTRLDESCL18_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL18_1_POSX_SHIFT             0
#define DCU_CTRLDESCL18_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_1_POSX_SHIFT))&DCU_CTRLDESCL18_1_POSX_MASK)
#define DCU_CTRLDESCL18_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL18_1_POSY_SHIFT             16
#define DCU_CTRLDESCL18_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_1_POSY_SHIFT))&DCU_CTRLDESCL18_1_POSY_MASK)
/* CTRLDESCL18_2 Bit Fields */
#define DCU_CTRLDESCL18_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL18_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL18_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_2_ADDR_SHIFT))&DCU_CTRLDESCL18_2_ADDR_MASK)
/* CTRLDESCL18_3 Bit Fields */
#define DCU_CTRLDESCL18_3_AB_MASK                0x3u
#define DCU_CTRLDESCL18_3_AB_SHIFT               0
#define DCU_CTRLDESCL18_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_3_AB_SHIFT))&DCU_CTRLDESCL18_3_AB_MASK)
#define DCU_CTRLDESCL18_3_BB_MASK                0x4u
#define DCU_CTRLDESCL18_3_BB_SHIFT               2
#define DCU_CTRLDESCL18_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL18_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL18_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_3_LUOFFS_SHIFT))&DCU_CTRLDESCL18_3_LUOFFS_MASK)
#define DCU_CTRLDESCL18_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL18_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL18_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL18_3_BPP_SHIFT              16
#define DCU_CTRLDESCL18_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_3_BPP_SHIFT))&DCU_CTRLDESCL18_3_BPP_MASK)
#define DCU_CTRLDESCL18_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL18_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL18_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_3_TRANS_SHIFT))&DCU_CTRLDESCL18_3_TRANS_MASK)
#define DCU_CTRLDESCL18_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL18_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL18_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL18_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL18_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL18_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL18_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL18_3_EN_SHIFT               31
/* CTRLDESCL18_4 Bit Fields */
#define DCU_CTRLDESCL18_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL18_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL18_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL18_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL18_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL18_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL18_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL18_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL18_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL18_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL18_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL18_4_CKMAX_R_MASK)
/* CTRLDESCL18_5 Bit Fields */
#define DCU_CTRLDESCL18_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL18_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL18_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL18_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL18_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL18_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL18_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL18_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL18_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL18_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL18_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL18_5_CKMIN_R_MASK)
/* CTRLDESCL18_6 Bit Fields */
#define DCU_CTRLDESCL18_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL18_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL18_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL18_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL18_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL18_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL18_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL18_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL18_7 Bit Fields */
#define DCU_CTRLDESCL18_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL18_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL18_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL18_7_FGn_FCOLOR_MASK)
/* CTRLDESCL18_8 Bit Fields */
#define DCU_CTRLDESCL18_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL18_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL18_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL18_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL18_8_FGn_BCOLOR_MASK)
/* CTRLDESCL19_0 Bit Fields */
#define DCU_CTRLDESCL19_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL19_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL19_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_0_WIDTH_SHIFT))&DCU_CTRLDESCL19_0_WIDTH_MASK)
#define DCU_CTRLDESCL19_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL19_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL19_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_0_HEIGHT_SHIFT))&DCU_CTRLDESCL19_0_HEIGHT_MASK)
/* CTRLDESCL19_1 Bit Fields */
#define DCU_CTRLDESCL19_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL19_1_POSX_SHIFT             0
#define DCU_CTRLDESCL19_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_1_POSX_SHIFT))&DCU_CTRLDESCL19_1_POSX_MASK)
#define DCU_CTRLDESCL19_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL19_1_POSY_SHIFT             16
#define DCU_CTRLDESCL19_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_1_POSY_SHIFT))&DCU_CTRLDESCL19_1_POSY_MASK)
/* CTRLDESCL19_2 Bit Fields */
#define DCU_CTRLDESCL19_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL19_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL19_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_2_ADDR_SHIFT))&DCU_CTRLDESCL19_2_ADDR_MASK)
/* CTRLDESCL19_3 Bit Fields */
#define DCU_CTRLDESCL19_3_AB_MASK                0x3u
#define DCU_CTRLDESCL19_3_AB_SHIFT               0
#define DCU_CTRLDESCL19_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_3_AB_SHIFT))&DCU_CTRLDESCL19_3_AB_MASK)
#define DCU_CTRLDESCL19_3_BB_MASK                0x4u
#define DCU_CTRLDESCL19_3_BB_SHIFT               2
#define DCU_CTRLDESCL19_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL19_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL19_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_3_LUOFFS_SHIFT))&DCU_CTRLDESCL19_3_LUOFFS_MASK)
#define DCU_CTRLDESCL19_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL19_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL19_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL19_3_BPP_SHIFT              16
#define DCU_CTRLDESCL19_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_3_BPP_SHIFT))&DCU_CTRLDESCL19_3_BPP_MASK)
#define DCU_CTRLDESCL19_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL19_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL19_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_3_TRANS_SHIFT))&DCU_CTRLDESCL19_3_TRANS_MASK)
#define DCU_CTRLDESCL19_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL19_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL19_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL19_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL19_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL19_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL19_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL19_3_EN_SHIFT               31
/* CTRLDESCL19_4 Bit Fields */
#define DCU_CTRLDESCL19_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL19_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL19_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL19_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL19_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL19_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL19_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL19_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL19_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL19_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL19_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL19_4_CKMAX_R_MASK)
/* CTRLDESCL19_5 Bit Fields */
#define DCU_CTRLDESCL19_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL19_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL19_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL19_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL19_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL19_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL19_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL19_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL19_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL19_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL19_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL19_5_CKMIN_R_MASK)
/* CTRLDESCL19_6 Bit Fields */
#define DCU_CTRLDESCL19_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL19_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL19_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL19_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL19_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL19_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL19_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL19_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL19_7 Bit Fields */
#define DCU_CTRLDESCL19_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL19_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL19_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL19_7_FGn_FCOLOR_MASK)
/* CTRLDESCL19_8 Bit Fields */
#define DCU_CTRLDESCL19_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL19_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL19_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL19_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL19_8_FGn_BCOLOR_MASK)
/* CTRLDESCL20_0 Bit Fields */
#define DCU_CTRLDESCL20_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL20_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL20_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_0_WIDTH_SHIFT))&DCU_CTRLDESCL20_0_WIDTH_MASK)
#define DCU_CTRLDESCL20_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL20_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL20_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_0_HEIGHT_SHIFT))&DCU_CTRLDESCL20_0_HEIGHT_MASK)
/* CTRLDESCL20_1 Bit Fields */
#define DCU_CTRLDESCL20_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL20_1_POSX_SHIFT             0
#define DCU_CTRLDESCL20_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_1_POSX_SHIFT))&DCU_CTRLDESCL20_1_POSX_MASK)
#define DCU_CTRLDESCL20_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL20_1_POSY_SHIFT             16
#define DCU_CTRLDESCL20_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_1_POSY_SHIFT))&DCU_CTRLDESCL20_1_POSY_MASK)
/* CTRLDESCL20_2 Bit Fields */
#define DCU_CTRLDESCL20_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL20_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL20_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_2_ADDR_SHIFT))&DCU_CTRLDESCL20_2_ADDR_MASK)
/* CTRLDESCL20_3 Bit Fields */
#define DCU_CTRLDESCL20_3_AB_MASK                0x3u
#define DCU_CTRLDESCL20_3_AB_SHIFT               0
#define DCU_CTRLDESCL20_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_3_AB_SHIFT))&DCU_CTRLDESCL20_3_AB_MASK)
#define DCU_CTRLDESCL20_3_BB_MASK                0x4u
#define DCU_CTRLDESCL20_3_BB_SHIFT               2
#define DCU_CTRLDESCL20_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL20_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL20_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_3_LUOFFS_SHIFT))&DCU_CTRLDESCL20_3_LUOFFS_MASK)
#define DCU_CTRLDESCL20_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL20_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL20_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL20_3_BPP_SHIFT              16
#define DCU_CTRLDESCL20_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_3_BPP_SHIFT))&DCU_CTRLDESCL20_3_BPP_MASK)
#define DCU_CTRLDESCL20_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL20_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL20_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_3_TRANS_SHIFT))&DCU_CTRLDESCL20_3_TRANS_MASK)
#define DCU_CTRLDESCL20_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL20_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL20_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL20_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL20_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL20_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL20_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL20_3_EN_SHIFT               31
/* CTRLDESCL20_4 Bit Fields */
#define DCU_CTRLDESCL20_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL20_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL20_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL20_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL20_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL20_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL20_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL20_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL20_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL20_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL20_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL20_4_CKMAX_R_MASK)
/* CTRLDESCL20_5 Bit Fields */
#define DCU_CTRLDESCL20_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL20_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL20_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL20_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL20_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL20_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL20_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL20_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL20_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL20_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL20_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL20_5_CKMIN_R_MASK)
/* CTRLDESCL20_6 Bit Fields */
#define DCU_CTRLDESCL20_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL20_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL20_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL20_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL20_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL20_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL20_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL20_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL20_7 Bit Fields */
#define DCU_CTRLDESCL20_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL20_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL20_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL20_7_FGn_FCOLOR_MASK)
/* CTRLDESCL20_8 Bit Fields */
#define DCU_CTRLDESCL20_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL20_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL20_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL20_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL20_8_FGn_BCOLOR_MASK)
/* CTRLDESCL21_0 Bit Fields */
#define DCU_CTRLDESCL21_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL21_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL21_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_0_WIDTH_SHIFT))&DCU_CTRLDESCL21_0_WIDTH_MASK)
#define DCU_CTRLDESCL21_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL21_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL21_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_0_HEIGHT_SHIFT))&DCU_CTRLDESCL21_0_HEIGHT_MASK)
/* CTRLDESCL21_1 Bit Fields */
#define DCU_CTRLDESCL21_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL21_1_POSX_SHIFT             0
#define DCU_CTRLDESCL21_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_1_POSX_SHIFT))&DCU_CTRLDESCL21_1_POSX_MASK)
#define DCU_CTRLDESCL21_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL21_1_POSY_SHIFT             16
#define DCU_CTRLDESCL21_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_1_POSY_SHIFT))&DCU_CTRLDESCL21_1_POSY_MASK)
/* CTRLDESCL21_2 Bit Fields */
#define DCU_CTRLDESCL21_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL21_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL21_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_2_ADDR_SHIFT))&DCU_CTRLDESCL21_2_ADDR_MASK)
/* CTRLDESCL21_3 Bit Fields */
#define DCU_CTRLDESCL21_3_AB_MASK                0x3u
#define DCU_CTRLDESCL21_3_AB_SHIFT               0
#define DCU_CTRLDESCL21_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_3_AB_SHIFT))&DCU_CTRLDESCL21_3_AB_MASK)
#define DCU_CTRLDESCL21_3_BB_MASK                0x4u
#define DCU_CTRLDESCL21_3_BB_SHIFT               2
#define DCU_CTRLDESCL21_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL21_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL21_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_3_LUOFFS_SHIFT))&DCU_CTRLDESCL21_3_LUOFFS_MASK)
#define DCU_CTRLDESCL21_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL21_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL21_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL21_3_BPP_SHIFT              16
#define DCU_CTRLDESCL21_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_3_BPP_SHIFT))&DCU_CTRLDESCL21_3_BPP_MASK)
#define DCU_CTRLDESCL21_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL21_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL21_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_3_TRANS_SHIFT))&DCU_CTRLDESCL21_3_TRANS_MASK)
#define DCU_CTRLDESCL21_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL21_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL21_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL21_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL21_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL21_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL21_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL21_3_EN_SHIFT               31
/* CTRLDESCL21_4 Bit Fields */
#define DCU_CTRLDESCL21_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL21_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL21_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL21_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL21_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL21_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL21_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL21_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL21_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL21_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL21_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL21_4_CKMAX_R_MASK)
/* CTRLDESCL21_5 Bit Fields */
#define DCU_CTRLDESCL21_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL21_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL21_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL21_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL21_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL21_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL21_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL21_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL21_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL21_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL21_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL21_5_CKMIN_R_MASK)
/* CTRLDESCL21_6 Bit Fields */
#define DCU_CTRLDESCL21_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL21_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL21_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL21_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL21_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL21_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL21_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL21_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL21_7 Bit Fields */
#define DCU_CTRLDESCL21_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL21_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL21_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL21_7_FGn_FCOLOR_MASK)
/* CTRLDESCL21_8 Bit Fields */
#define DCU_CTRLDESCL21_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL21_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL21_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL21_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL21_8_FGn_BCOLOR_MASK)
/* CTRLDESCL22_0 Bit Fields */
#define DCU_CTRLDESCL22_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL22_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL22_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_0_WIDTH_SHIFT))&DCU_CTRLDESCL22_0_WIDTH_MASK)
#define DCU_CTRLDESCL22_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL22_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL22_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_0_HEIGHT_SHIFT))&DCU_CTRLDESCL22_0_HEIGHT_MASK)
/* CTRLDESCL22_1 Bit Fields */
#define DCU_CTRLDESCL22_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL22_1_POSX_SHIFT             0
#define DCU_CTRLDESCL22_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_1_POSX_SHIFT))&DCU_CTRLDESCL22_1_POSX_MASK)
#define DCU_CTRLDESCL22_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL22_1_POSY_SHIFT             16
#define DCU_CTRLDESCL22_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_1_POSY_SHIFT))&DCU_CTRLDESCL22_1_POSY_MASK)
/* CTRLDESCL22_2 Bit Fields */
#define DCU_CTRLDESCL22_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL22_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL22_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_2_ADDR_SHIFT))&DCU_CTRLDESCL22_2_ADDR_MASK)
/* CTRLDESCL22_3 Bit Fields */
#define DCU_CTRLDESCL22_3_AB_MASK                0x3u
#define DCU_CTRLDESCL22_3_AB_SHIFT               0
#define DCU_CTRLDESCL22_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_3_AB_SHIFT))&DCU_CTRLDESCL22_3_AB_MASK)
#define DCU_CTRLDESCL22_3_BB_MASK                0x4u
#define DCU_CTRLDESCL22_3_BB_SHIFT               2
#define DCU_CTRLDESCL22_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL22_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL22_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_3_LUOFFS_SHIFT))&DCU_CTRLDESCL22_3_LUOFFS_MASK)
#define DCU_CTRLDESCL22_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL22_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL22_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL22_3_BPP_SHIFT              16
#define DCU_CTRLDESCL22_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_3_BPP_SHIFT))&DCU_CTRLDESCL22_3_BPP_MASK)
#define DCU_CTRLDESCL22_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL22_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL22_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_3_TRANS_SHIFT))&DCU_CTRLDESCL22_3_TRANS_MASK)
#define DCU_CTRLDESCL22_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL22_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL22_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL22_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL22_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL22_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL22_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL22_3_EN_SHIFT               31
/* CTRLDESCL22_4 Bit Fields */
#define DCU_CTRLDESCL22_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL22_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL22_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL22_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL22_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL22_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL22_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL22_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL22_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL22_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL22_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL22_4_CKMAX_R_MASK)
/* CTRLDESCL22_5 Bit Fields */
#define DCU_CTRLDESCL22_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL22_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL22_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL22_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL22_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL22_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL22_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL22_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL22_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL22_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL22_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL22_5_CKMIN_R_MASK)
/* CTRLDESCL22_6 Bit Fields */
#define DCU_CTRLDESCL22_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL22_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL22_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL22_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL22_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL22_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL22_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL22_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL22_7 Bit Fields */
#define DCU_CTRLDESCL22_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL22_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL22_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL22_7_FGn_FCOLOR_MASK)
/* CTRLDESCL22_8 Bit Fields */
#define DCU_CTRLDESCL22_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL22_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL22_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL22_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL22_8_FGn_BCOLOR_MASK)
/* CTRLDESCL23_0 Bit Fields */
#define DCU_CTRLDESCL23_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL23_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL23_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_0_WIDTH_SHIFT))&DCU_CTRLDESCL23_0_WIDTH_MASK)
#define DCU_CTRLDESCL23_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL23_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL23_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_0_HEIGHT_SHIFT))&DCU_CTRLDESCL23_0_HEIGHT_MASK)
/* CTRLDESCL23_1 Bit Fields */
#define DCU_CTRLDESCL23_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL23_1_POSX_SHIFT             0
#define DCU_CTRLDESCL23_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_1_POSX_SHIFT))&DCU_CTRLDESCL23_1_POSX_MASK)
#define DCU_CTRLDESCL23_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL23_1_POSY_SHIFT             16
#define DCU_CTRLDESCL23_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_1_POSY_SHIFT))&DCU_CTRLDESCL23_1_POSY_MASK)
/* CTRLDESCL23_2 Bit Fields */
#define DCU_CTRLDESCL23_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL23_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL23_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_2_ADDR_SHIFT))&DCU_CTRLDESCL23_2_ADDR_MASK)
/* CTRLDESCL23_3 Bit Fields */
#define DCU_CTRLDESCL23_3_AB_MASK                0x3u
#define DCU_CTRLDESCL23_3_AB_SHIFT               0
#define DCU_CTRLDESCL23_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_3_AB_SHIFT))&DCU_CTRLDESCL23_3_AB_MASK)
#define DCU_CTRLDESCL23_3_BB_MASK                0x4u
#define DCU_CTRLDESCL23_3_BB_SHIFT               2
#define DCU_CTRLDESCL23_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL23_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL23_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_3_LUOFFS_SHIFT))&DCU_CTRLDESCL23_3_LUOFFS_MASK)
#define DCU_CTRLDESCL23_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL23_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL23_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL23_3_BPP_SHIFT              16
#define DCU_CTRLDESCL23_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_3_BPP_SHIFT))&DCU_CTRLDESCL23_3_BPP_MASK)
#define DCU_CTRLDESCL23_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL23_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL23_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_3_TRANS_SHIFT))&DCU_CTRLDESCL23_3_TRANS_MASK)
#define DCU_CTRLDESCL23_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL23_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL23_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL23_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL23_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL23_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL23_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL23_3_EN_SHIFT               31
/* CTRLDESCL23_4 Bit Fields */
#define DCU_CTRLDESCL23_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL23_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL23_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL23_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL23_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL23_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL23_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL23_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL23_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL23_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL23_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL23_4_CKMAX_R_MASK)
/* CTRLDESCL23_5 Bit Fields */
#define DCU_CTRLDESCL23_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL23_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL23_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL23_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL23_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL23_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL23_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL23_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL23_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL23_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL23_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL23_5_CKMIN_R_MASK)
/* CTRLDESCL23_6 Bit Fields */
#define DCU_CTRLDESCL23_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL23_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL23_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL23_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL23_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL23_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL23_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL23_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL23_7 Bit Fields */
#define DCU_CTRLDESCL23_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL23_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL23_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL23_7_FGn_FCOLOR_MASK)
/* CTRLDESCL23_8 Bit Fields */
#define DCU_CTRLDESCL23_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL23_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL23_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL23_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL23_8_FGn_BCOLOR_MASK)
/* CTRLDESCL24_0 Bit Fields */
#define DCU_CTRLDESCL24_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL24_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL24_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_0_WIDTH_SHIFT))&DCU_CTRLDESCL24_0_WIDTH_MASK)
#define DCU_CTRLDESCL24_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL24_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL24_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_0_HEIGHT_SHIFT))&DCU_CTRLDESCL24_0_HEIGHT_MASK)
/* CTRLDESCL24_1 Bit Fields */
#define DCU_CTRLDESCL24_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL24_1_POSX_SHIFT             0
#define DCU_CTRLDESCL24_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_1_POSX_SHIFT))&DCU_CTRLDESCL24_1_POSX_MASK)
#define DCU_CTRLDESCL24_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL24_1_POSY_SHIFT             16
#define DCU_CTRLDESCL24_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_1_POSY_SHIFT))&DCU_CTRLDESCL24_1_POSY_MASK)
/* CTRLDESCL24_2 Bit Fields */
#define DCU_CTRLDESCL24_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL24_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL24_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_2_ADDR_SHIFT))&DCU_CTRLDESCL24_2_ADDR_MASK)
/* CTRLDESCL24_3 Bit Fields */
#define DCU_CTRLDESCL24_3_AB_MASK                0x3u
#define DCU_CTRLDESCL24_3_AB_SHIFT               0
#define DCU_CTRLDESCL24_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_3_AB_SHIFT))&DCU_CTRLDESCL24_3_AB_MASK)
#define DCU_CTRLDESCL24_3_BB_MASK                0x4u
#define DCU_CTRLDESCL24_3_BB_SHIFT               2
#define DCU_CTRLDESCL24_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL24_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL24_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_3_LUOFFS_SHIFT))&DCU_CTRLDESCL24_3_LUOFFS_MASK)
#define DCU_CTRLDESCL24_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL24_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL24_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL24_3_BPP_SHIFT              16
#define DCU_CTRLDESCL24_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_3_BPP_SHIFT))&DCU_CTRLDESCL24_3_BPP_MASK)
#define DCU_CTRLDESCL24_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL24_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL24_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_3_TRANS_SHIFT))&DCU_CTRLDESCL24_3_TRANS_MASK)
#define DCU_CTRLDESCL24_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL24_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL24_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL24_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL24_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL24_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL24_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL24_3_EN_SHIFT               31
/* CTRLDESCL24_4 Bit Fields */
#define DCU_CTRLDESCL24_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL24_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL24_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL24_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL24_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL24_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL24_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL24_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL24_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL24_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL24_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL24_4_CKMAX_R_MASK)
/* CTRLDESCL24_5 Bit Fields */
#define DCU_CTRLDESCL24_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL24_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL24_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL24_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL24_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL24_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL24_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL24_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL24_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL24_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL24_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL24_5_CKMIN_R_MASK)
/* CTRLDESCL24_6 Bit Fields */
#define DCU_CTRLDESCL24_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL24_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL24_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL24_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL24_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL24_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL24_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL24_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL24_7 Bit Fields */
#define DCU_CTRLDESCL24_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL24_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL24_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL24_7_FGn_FCOLOR_MASK)
/* CTRLDESCL24_8 Bit Fields */
#define DCU_CTRLDESCL24_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL24_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL24_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL24_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL24_8_FGn_BCOLOR_MASK)
/* CTRLDESCL25_0 Bit Fields */
#define DCU_CTRLDESCL25_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL25_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL25_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_0_WIDTH_SHIFT))&DCU_CTRLDESCL25_0_WIDTH_MASK)
#define DCU_CTRLDESCL25_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL25_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL25_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_0_HEIGHT_SHIFT))&DCU_CTRLDESCL25_0_HEIGHT_MASK)
/* CTRLDESCL25_1 Bit Fields */
#define DCU_CTRLDESCL25_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL25_1_POSX_SHIFT             0
#define DCU_CTRLDESCL25_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_1_POSX_SHIFT))&DCU_CTRLDESCL25_1_POSX_MASK)
#define DCU_CTRLDESCL25_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL25_1_POSY_SHIFT             16
#define DCU_CTRLDESCL25_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_1_POSY_SHIFT))&DCU_CTRLDESCL25_1_POSY_MASK)
/* CTRLDESCL25_2 Bit Fields */
#define DCU_CTRLDESCL25_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL25_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL25_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_2_ADDR_SHIFT))&DCU_CTRLDESCL25_2_ADDR_MASK)
/* CTRLDESCL25_3 Bit Fields */
#define DCU_CTRLDESCL25_3_AB_MASK                0x3u
#define DCU_CTRLDESCL25_3_AB_SHIFT               0
#define DCU_CTRLDESCL25_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_3_AB_SHIFT))&DCU_CTRLDESCL25_3_AB_MASK)
#define DCU_CTRLDESCL25_3_BB_MASK                0x4u
#define DCU_CTRLDESCL25_3_BB_SHIFT               2
#define DCU_CTRLDESCL25_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL25_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL25_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_3_LUOFFS_SHIFT))&DCU_CTRLDESCL25_3_LUOFFS_MASK)
#define DCU_CTRLDESCL25_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL25_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL25_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL25_3_BPP_SHIFT              16
#define DCU_CTRLDESCL25_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_3_BPP_SHIFT))&DCU_CTRLDESCL25_3_BPP_MASK)
#define DCU_CTRLDESCL25_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL25_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL25_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_3_TRANS_SHIFT))&DCU_CTRLDESCL25_3_TRANS_MASK)
#define DCU_CTRLDESCL25_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL25_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL25_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL25_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL25_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL25_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL25_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL25_3_EN_SHIFT               31
/* CTRLDESCL25_4 Bit Fields */
#define DCU_CTRLDESCL25_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL25_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL25_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL25_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL25_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL25_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL25_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL25_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL25_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL25_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL25_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL25_4_CKMAX_R_MASK)
/* CTRLDESCL25_5 Bit Fields */
#define DCU_CTRLDESCL25_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL25_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL25_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL25_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL25_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL25_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL25_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL25_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL25_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL25_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL25_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL25_5_CKMIN_R_MASK)
/* CTRLDESCL25_6 Bit Fields */
#define DCU_CTRLDESCL25_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL25_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL25_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL25_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL25_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL25_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL25_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL25_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL25_7 Bit Fields */
#define DCU_CTRLDESCL25_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL25_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL25_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL25_7_FGn_FCOLOR_MASK)
/* CTRLDESCL25_8 Bit Fields */
#define DCU_CTRLDESCL25_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL25_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL25_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL25_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL25_8_FGn_BCOLOR_MASK)
/* CTRLDESCL26_0 Bit Fields */
#define DCU_CTRLDESCL26_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL26_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL26_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_0_WIDTH_SHIFT))&DCU_CTRLDESCL26_0_WIDTH_MASK)
#define DCU_CTRLDESCL26_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL26_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL26_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_0_HEIGHT_SHIFT))&DCU_CTRLDESCL26_0_HEIGHT_MASK)
/* CTRLDESCL26_1 Bit Fields */
#define DCU_CTRLDESCL26_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL26_1_POSX_SHIFT             0
#define DCU_CTRLDESCL26_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_1_POSX_SHIFT))&DCU_CTRLDESCL26_1_POSX_MASK)
#define DCU_CTRLDESCL26_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL26_1_POSY_SHIFT             16
#define DCU_CTRLDESCL26_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_1_POSY_SHIFT))&DCU_CTRLDESCL26_1_POSY_MASK)
/* CTRLDESCL26_2 Bit Fields */
#define DCU_CTRLDESCL26_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL26_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL26_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_2_ADDR_SHIFT))&DCU_CTRLDESCL26_2_ADDR_MASK)
/* CTRLDESCL26_3 Bit Fields */
#define DCU_CTRLDESCL26_3_AB_MASK                0x3u
#define DCU_CTRLDESCL26_3_AB_SHIFT               0
#define DCU_CTRLDESCL26_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_3_AB_SHIFT))&DCU_CTRLDESCL26_3_AB_MASK)
#define DCU_CTRLDESCL26_3_BB_MASK                0x4u
#define DCU_CTRLDESCL26_3_BB_SHIFT               2
#define DCU_CTRLDESCL26_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL26_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL26_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_3_LUOFFS_SHIFT))&DCU_CTRLDESCL26_3_LUOFFS_MASK)
#define DCU_CTRLDESCL26_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL26_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL26_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL26_3_BPP_SHIFT              16
#define DCU_CTRLDESCL26_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_3_BPP_SHIFT))&DCU_CTRLDESCL26_3_BPP_MASK)
#define DCU_CTRLDESCL26_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL26_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL26_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_3_TRANS_SHIFT))&DCU_CTRLDESCL26_3_TRANS_MASK)
#define DCU_CTRLDESCL26_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL26_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL26_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL26_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL26_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL26_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL26_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL26_3_EN_SHIFT               31
/* CTRLDESCL26_4 Bit Fields */
#define DCU_CTRLDESCL26_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL26_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL26_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL26_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL26_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL26_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL26_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL26_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL26_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL26_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL26_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL26_4_CKMAX_R_MASK)
/* CTRLDESCL26_5 Bit Fields */
#define DCU_CTRLDESCL26_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL26_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL26_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL26_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL26_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL26_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL26_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL26_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL26_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL26_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL26_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL26_5_CKMIN_R_MASK)
/* CTRLDESCL26_6 Bit Fields */
#define DCU_CTRLDESCL26_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL26_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL26_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL26_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL26_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL26_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL26_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL26_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL26_7 Bit Fields */
#define DCU_CTRLDESCL26_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL26_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL26_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL26_7_FGn_FCOLOR_MASK)
/* CTRLDESCL26_8 Bit Fields */
#define DCU_CTRLDESCL26_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL26_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL26_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL26_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL26_8_FGn_BCOLOR_MASK)
/* CTRLDESCL27_0 Bit Fields */
#define DCU_CTRLDESCL27_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL27_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL27_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_0_WIDTH_SHIFT))&DCU_CTRLDESCL27_0_WIDTH_MASK)
#define DCU_CTRLDESCL27_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL27_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL27_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_0_HEIGHT_SHIFT))&DCU_CTRLDESCL27_0_HEIGHT_MASK)
/* CTRLDESCL27_1 Bit Fields */
#define DCU_CTRLDESCL27_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL27_1_POSX_SHIFT             0
#define DCU_CTRLDESCL27_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_1_POSX_SHIFT))&DCU_CTRLDESCL27_1_POSX_MASK)
#define DCU_CTRLDESCL27_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL27_1_POSY_SHIFT             16
#define DCU_CTRLDESCL27_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_1_POSY_SHIFT))&DCU_CTRLDESCL27_1_POSY_MASK)
/* CTRLDESCL27_2 Bit Fields */
#define DCU_CTRLDESCL27_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL27_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL27_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_2_ADDR_SHIFT))&DCU_CTRLDESCL27_2_ADDR_MASK)
/* CTRLDESCL27_3 Bit Fields */
#define DCU_CTRLDESCL27_3_AB_MASK                0x3u
#define DCU_CTRLDESCL27_3_AB_SHIFT               0
#define DCU_CTRLDESCL27_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_3_AB_SHIFT))&DCU_CTRLDESCL27_3_AB_MASK)
#define DCU_CTRLDESCL27_3_BB_MASK                0x4u
#define DCU_CTRLDESCL27_3_BB_SHIFT               2
#define DCU_CTRLDESCL27_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL27_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL27_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_3_LUOFFS_SHIFT))&DCU_CTRLDESCL27_3_LUOFFS_MASK)
#define DCU_CTRLDESCL27_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL27_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL27_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL27_3_BPP_SHIFT              16
#define DCU_CTRLDESCL27_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_3_BPP_SHIFT))&DCU_CTRLDESCL27_3_BPP_MASK)
#define DCU_CTRLDESCL27_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL27_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL27_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_3_TRANS_SHIFT))&DCU_CTRLDESCL27_3_TRANS_MASK)
#define DCU_CTRLDESCL27_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL27_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL27_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL27_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL27_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL27_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL27_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL27_3_EN_SHIFT               31
/* CTRLDESCL27_4 Bit Fields */
#define DCU_CTRLDESCL27_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL27_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL27_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL27_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL27_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL27_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL27_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL27_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL27_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL27_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL27_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL27_4_CKMAX_R_MASK)
/* CTRLDESCL27_5 Bit Fields */
#define DCU_CTRLDESCL27_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL27_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL27_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL27_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL27_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL27_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL27_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL27_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL27_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL27_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL27_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL27_5_CKMIN_R_MASK)
/* CTRLDESCL27_6 Bit Fields */
#define DCU_CTRLDESCL27_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL27_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL27_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL27_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL27_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL27_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL27_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL27_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL27_7 Bit Fields */
#define DCU_CTRLDESCL27_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL27_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL27_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL27_7_FGn_FCOLOR_MASK)
/* CTRLDESCL27_8 Bit Fields */
#define DCU_CTRLDESCL27_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL27_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL27_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL27_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL27_8_FGn_BCOLOR_MASK)
/* CTRLDESCL28_0 Bit Fields */
#define DCU_CTRLDESCL28_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL28_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL28_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_0_WIDTH_SHIFT))&DCU_CTRLDESCL28_0_WIDTH_MASK)
#define DCU_CTRLDESCL28_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL28_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL28_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_0_HEIGHT_SHIFT))&DCU_CTRLDESCL28_0_HEIGHT_MASK)
/* CTRLDESCL28_1 Bit Fields */
#define DCU_CTRLDESCL28_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL28_1_POSX_SHIFT             0
#define DCU_CTRLDESCL28_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_1_POSX_SHIFT))&DCU_CTRLDESCL28_1_POSX_MASK)
#define DCU_CTRLDESCL28_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL28_1_POSY_SHIFT             16
#define DCU_CTRLDESCL28_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_1_POSY_SHIFT))&DCU_CTRLDESCL28_1_POSY_MASK)
/* CTRLDESCL28_2 Bit Fields */
#define DCU_CTRLDESCL28_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL28_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL28_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_2_ADDR_SHIFT))&DCU_CTRLDESCL28_2_ADDR_MASK)
/* CTRLDESCL28_3 Bit Fields */
#define DCU_CTRLDESCL28_3_AB_MASK                0x3u
#define DCU_CTRLDESCL28_3_AB_SHIFT               0
#define DCU_CTRLDESCL28_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_3_AB_SHIFT))&DCU_CTRLDESCL28_3_AB_MASK)
#define DCU_CTRLDESCL28_3_BB_MASK                0x4u
#define DCU_CTRLDESCL28_3_BB_SHIFT               2
#define DCU_CTRLDESCL28_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL28_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL28_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_3_LUOFFS_SHIFT))&DCU_CTRLDESCL28_3_LUOFFS_MASK)
#define DCU_CTRLDESCL28_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL28_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL28_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL28_3_BPP_SHIFT              16
#define DCU_CTRLDESCL28_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_3_BPP_SHIFT))&DCU_CTRLDESCL28_3_BPP_MASK)
#define DCU_CTRLDESCL28_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL28_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL28_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_3_TRANS_SHIFT))&DCU_CTRLDESCL28_3_TRANS_MASK)
#define DCU_CTRLDESCL28_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL28_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL28_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL28_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL28_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL28_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL28_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL28_3_EN_SHIFT               31
/* CTRLDESCL28_4 Bit Fields */
#define DCU_CTRLDESCL28_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL28_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL28_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL28_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL28_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL28_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL28_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL28_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL28_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL28_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL28_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL28_4_CKMAX_R_MASK)
/* CTRLDESCL28_5 Bit Fields */
#define DCU_CTRLDESCL28_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL28_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL28_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL28_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL28_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL28_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL28_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL28_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL28_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL28_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL28_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL28_5_CKMIN_R_MASK)
/* CTRLDESCL28_6 Bit Fields */
#define DCU_CTRLDESCL28_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL28_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL28_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL28_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL28_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL28_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL28_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL28_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL28_7 Bit Fields */
#define DCU_CTRLDESCL28_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL28_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL28_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL28_7_FGn_FCOLOR_MASK)
/* CTRLDESCL28_8 Bit Fields */
#define DCU_CTRLDESCL28_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL28_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL28_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL28_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL28_8_FGn_BCOLOR_MASK)
/* CTRLDESCL29_0 Bit Fields */
#define DCU_CTRLDESCL29_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL29_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL29_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_0_WIDTH_SHIFT))&DCU_CTRLDESCL29_0_WIDTH_MASK)
#define DCU_CTRLDESCL29_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL29_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL29_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_0_HEIGHT_SHIFT))&DCU_CTRLDESCL29_0_HEIGHT_MASK)
/* CTRLDESCL29_1 Bit Fields */
#define DCU_CTRLDESCL29_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL29_1_POSX_SHIFT             0
#define DCU_CTRLDESCL29_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_1_POSX_SHIFT))&DCU_CTRLDESCL29_1_POSX_MASK)
#define DCU_CTRLDESCL29_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL29_1_POSY_SHIFT             16
#define DCU_CTRLDESCL29_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_1_POSY_SHIFT))&DCU_CTRLDESCL29_1_POSY_MASK)
/* CTRLDESCL29_2 Bit Fields */
#define DCU_CTRLDESCL29_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL29_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL29_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_2_ADDR_SHIFT))&DCU_CTRLDESCL29_2_ADDR_MASK)
/* CTRLDESCL29_3 Bit Fields */
#define DCU_CTRLDESCL29_3_AB_MASK                0x3u
#define DCU_CTRLDESCL29_3_AB_SHIFT               0
#define DCU_CTRLDESCL29_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_3_AB_SHIFT))&DCU_CTRLDESCL29_3_AB_MASK)
#define DCU_CTRLDESCL29_3_BB_MASK                0x4u
#define DCU_CTRLDESCL29_3_BB_SHIFT               2
#define DCU_CTRLDESCL29_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL29_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL29_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_3_LUOFFS_SHIFT))&DCU_CTRLDESCL29_3_LUOFFS_MASK)
#define DCU_CTRLDESCL29_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL29_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL29_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL29_3_BPP_SHIFT              16
#define DCU_CTRLDESCL29_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_3_BPP_SHIFT))&DCU_CTRLDESCL29_3_BPP_MASK)
#define DCU_CTRLDESCL29_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL29_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL29_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_3_TRANS_SHIFT))&DCU_CTRLDESCL29_3_TRANS_MASK)
#define DCU_CTRLDESCL29_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL29_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL29_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL29_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL29_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL29_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL29_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL29_3_EN_SHIFT               31
/* CTRLDESCL29_4 Bit Fields */
#define DCU_CTRLDESCL29_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL29_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL29_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL29_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL29_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL29_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL29_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL29_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL29_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL29_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL29_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL29_4_CKMAX_R_MASK)
/* CTRLDESCL29_5 Bit Fields */
#define DCU_CTRLDESCL29_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL29_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL29_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL29_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL29_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL29_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL29_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL29_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL29_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL29_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL29_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL29_5_CKMIN_R_MASK)
/* CTRLDESCL29_6 Bit Fields */
#define DCU_CTRLDESCL29_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL29_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL29_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL29_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL29_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL29_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL29_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL29_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL29_7 Bit Fields */
#define DCU_CTRLDESCL29_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL29_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL29_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL29_7_FGn_FCOLOR_MASK)
/* CTRLDESCL29_8 Bit Fields */
#define DCU_CTRLDESCL29_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL29_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL29_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL29_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL29_8_FGn_BCOLOR_MASK)
/* CTRLDESCL30_0 Bit Fields */
#define DCU_CTRLDESCL30_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL30_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL30_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_0_WIDTH_SHIFT))&DCU_CTRLDESCL30_0_WIDTH_MASK)
#define DCU_CTRLDESCL30_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL30_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL30_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_0_HEIGHT_SHIFT))&DCU_CTRLDESCL30_0_HEIGHT_MASK)
/* CTRLDESCL30_1 Bit Fields */
#define DCU_CTRLDESCL30_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL30_1_POSX_SHIFT             0
#define DCU_CTRLDESCL30_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_1_POSX_SHIFT))&DCU_CTRLDESCL30_1_POSX_MASK)
#define DCU_CTRLDESCL30_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL30_1_POSY_SHIFT             16
#define DCU_CTRLDESCL30_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_1_POSY_SHIFT))&DCU_CTRLDESCL30_1_POSY_MASK)
/* CTRLDESCL30_2 Bit Fields */
#define DCU_CTRLDESCL30_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL30_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL30_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_2_ADDR_SHIFT))&DCU_CTRLDESCL30_2_ADDR_MASK)
/* CTRLDESCL30_3 Bit Fields */
#define DCU_CTRLDESCL30_3_AB_MASK                0x3u
#define DCU_CTRLDESCL30_3_AB_SHIFT               0
#define DCU_CTRLDESCL30_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_3_AB_SHIFT))&DCU_CTRLDESCL30_3_AB_MASK)
#define DCU_CTRLDESCL30_3_BB_MASK                0x4u
#define DCU_CTRLDESCL30_3_BB_SHIFT               2
#define DCU_CTRLDESCL30_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL30_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL30_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_3_LUOFFS_SHIFT))&DCU_CTRLDESCL30_3_LUOFFS_MASK)
#define DCU_CTRLDESCL30_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL30_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL30_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL30_3_BPP_SHIFT              16
#define DCU_CTRLDESCL30_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_3_BPP_SHIFT))&DCU_CTRLDESCL30_3_BPP_MASK)
#define DCU_CTRLDESCL30_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL30_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL30_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_3_TRANS_SHIFT))&DCU_CTRLDESCL30_3_TRANS_MASK)
#define DCU_CTRLDESCL30_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL30_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL30_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL30_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL30_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL30_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL30_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL30_3_EN_SHIFT               31
/* CTRLDESCL30_4 Bit Fields */
#define DCU_CTRLDESCL30_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL30_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL30_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL30_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL30_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL30_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL30_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL30_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL30_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL30_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL30_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL30_4_CKMAX_R_MASK)
/* CTRLDESCL30_5 Bit Fields */
#define DCU_CTRLDESCL30_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL30_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL30_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL30_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL30_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL30_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL30_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL30_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL30_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL30_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL30_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL30_5_CKMIN_R_MASK)
/* CTRLDESCL30_6 Bit Fields */
#define DCU_CTRLDESCL30_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL30_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL30_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL30_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL30_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL30_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL30_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL30_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL30_7 Bit Fields */
#define DCU_CTRLDESCL30_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL30_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL30_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL30_7_FGn_FCOLOR_MASK)
/* CTRLDESCL30_8 Bit Fields */
#define DCU_CTRLDESCL30_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL30_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL30_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL30_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL30_8_FGn_BCOLOR_MASK)
/* CTRLDESCL31_0 Bit Fields */
#define DCU_CTRLDESCL31_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL31_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL31_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_0_WIDTH_SHIFT))&DCU_CTRLDESCL31_0_WIDTH_MASK)
#define DCU_CTRLDESCL31_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL31_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL31_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_0_HEIGHT_SHIFT))&DCU_CTRLDESCL31_0_HEIGHT_MASK)
/* CTRLDESCL31_1 Bit Fields */
#define DCU_CTRLDESCL31_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL31_1_POSX_SHIFT             0
#define DCU_CTRLDESCL31_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_1_POSX_SHIFT))&DCU_CTRLDESCL31_1_POSX_MASK)
#define DCU_CTRLDESCL31_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL31_1_POSY_SHIFT             16
#define DCU_CTRLDESCL31_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_1_POSY_SHIFT))&DCU_CTRLDESCL31_1_POSY_MASK)
/* CTRLDESCL31_2 Bit Fields */
#define DCU_CTRLDESCL31_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL31_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL31_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_2_ADDR_SHIFT))&DCU_CTRLDESCL31_2_ADDR_MASK)
/* CTRLDESCL31_3 Bit Fields */
#define DCU_CTRLDESCL31_3_AB_MASK                0x3u
#define DCU_CTRLDESCL31_3_AB_SHIFT               0
#define DCU_CTRLDESCL31_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_3_AB_SHIFT))&DCU_CTRLDESCL31_3_AB_MASK)
#define DCU_CTRLDESCL31_3_BB_MASK                0x4u
#define DCU_CTRLDESCL31_3_BB_SHIFT               2
#define DCU_CTRLDESCL31_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL31_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL31_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_3_LUOFFS_SHIFT))&DCU_CTRLDESCL31_3_LUOFFS_MASK)
#define DCU_CTRLDESCL31_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL31_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL31_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL31_3_BPP_SHIFT              16
#define DCU_CTRLDESCL31_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_3_BPP_SHIFT))&DCU_CTRLDESCL31_3_BPP_MASK)
#define DCU_CTRLDESCL31_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL31_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL31_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_3_TRANS_SHIFT))&DCU_CTRLDESCL31_3_TRANS_MASK)
#define DCU_CTRLDESCL31_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL31_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL31_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL31_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL31_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL31_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL31_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL31_3_EN_SHIFT               31
/* CTRLDESCL31_4 Bit Fields */
#define DCU_CTRLDESCL31_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL31_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL31_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL31_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL31_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL31_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL31_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL31_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL31_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL31_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL31_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL31_4_CKMAX_R_MASK)
/* CTRLDESCL31_5 Bit Fields */
#define DCU_CTRLDESCL31_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL31_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL31_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL31_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL31_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL31_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL31_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL31_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL31_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL31_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL31_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL31_5_CKMIN_R_MASK)
/* CTRLDESCL31_6 Bit Fields */
#define DCU_CTRLDESCL31_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL31_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL31_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL31_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL31_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL31_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL31_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL31_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL31_7 Bit Fields */
#define DCU_CTRLDESCL31_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL31_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL31_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL31_7_FGn_FCOLOR_MASK)
/* CTRLDESCL31_8 Bit Fields */
#define DCU_CTRLDESCL31_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL31_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL31_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL31_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL31_8_FGn_BCOLOR_MASK)
/* CTRLDESCL32_0 Bit Fields */
#define DCU_CTRLDESCL32_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL32_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL32_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_0_WIDTH_SHIFT))&DCU_CTRLDESCL32_0_WIDTH_MASK)
#define DCU_CTRLDESCL32_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL32_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL32_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_0_HEIGHT_SHIFT))&DCU_CTRLDESCL32_0_HEIGHT_MASK)
/* CTRLDESCL32_1 Bit Fields */
#define DCU_CTRLDESCL32_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL32_1_POSX_SHIFT             0
#define DCU_CTRLDESCL32_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_1_POSX_SHIFT))&DCU_CTRLDESCL32_1_POSX_MASK)
#define DCU_CTRLDESCL32_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL32_1_POSY_SHIFT             16
#define DCU_CTRLDESCL32_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_1_POSY_SHIFT))&DCU_CTRLDESCL32_1_POSY_MASK)
/* CTRLDESCL32_2 Bit Fields */
#define DCU_CTRLDESCL32_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL32_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL32_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_2_ADDR_SHIFT))&DCU_CTRLDESCL32_2_ADDR_MASK)
/* CTRLDESCL32_3 Bit Fields */
#define DCU_CTRLDESCL32_3_AB_MASK                0x3u
#define DCU_CTRLDESCL32_3_AB_SHIFT               0
#define DCU_CTRLDESCL32_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_3_AB_SHIFT))&DCU_CTRLDESCL32_3_AB_MASK)
#define DCU_CTRLDESCL32_3_BB_MASK                0x4u
#define DCU_CTRLDESCL32_3_BB_SHIFT               2
#define DCU_CTRLDESCL32_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL32_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL32_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_3_LUOFFS_SHIFT))&DCU_CTRLDESCL32_3_LUOFFS_MASK)
#define DCU_CTRLDESCL32_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL32_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL32_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL32_3_BPP_SHIFT              16
#define DCU_CTRLDESCL32_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_3_BPP_SHIFT))&DCU_CTRLDESCL32_3_BPP_MASK)
#define DCU_CTRLDESCL32_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL32_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL32_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_3_TRANS_SHIFT))&DCU_CTRLDESCL32_3_TRANS_MASK)
#define DCU_CTRLDESCL32_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL32_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL32_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL32_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL32_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL32_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL32_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL32_3_EN_SHIFT               31
/* CTRLDESCL32_4 Bit Fields */
#define DCU_CTRLDESCL32_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL32_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL32_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL32_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL32_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL32_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL32_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL32_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL32_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL32_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL32_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL32_4_CKMAX_R_MASK)
/* CTRLDESCL32_5 Bit Fields */
#define DCU_CTRLDESCL32_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL32_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL32_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL32_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL32_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL32_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL32_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL32_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL32_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL32_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL32_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL32_5_CKMIN_R_MASK)
/* CTRLDESCL32_6 Bit Fields */
#define DCU_CTRLDESCL32_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL32_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL32_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL32_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL32_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL32_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL32_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL32_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL32_7 Bit Fields */
#define DCU_CTRLDESCL32_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL32_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL32_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL32_7_FGn_FCOLOR_MASK)
/* CTRLDESCL32_8 Bit Fields */
#define DCU_CTRLDESCL32_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL32_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL32_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL32_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL32_8_FGn_BCOLOR_MASK)
/* CTRLDESCL33_0 Bit Fields */
#define DCU_CTRLDESCL33_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL33_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL33_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_0_WIDTH_SHIFT))&DCU_CTRLDESCL33_0_WIDTH_MASK)
#define DCU_CTRLDESCL33_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL33_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL33_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_0_HEIGHT_SHIFT))&DCU_CTRLDESCL33_0_HEIGHT_MASK)
/* CTRLDESCL33_1 Bit Fields */
#define DCU_CTRLDESCL33_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL33_1_POSX_SHIFT             0
#define DCU_CTRLDESCL33_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_1_POSX_SHIFT))&DCU_CTRLDESCL33_1_POSX_MASK)
#define DCU_CTRLDESCL33_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL33_1_POSY_SHIFT             16
#define DCU_CTRLDESCL33_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_1_POSY_SHIFT))&DCU_CTRLDESCL33_1_POSY_MASK)
/* CTRLDESCL33_2 Bit Fields */
#define DCU_CTRLDESCL33_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL33_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL33_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_2_ADDR_SHIFT))&DCU_CTRLDESCL33_2_ADDR_MASK)
/* CTRLDESCL33_3 Bit Fields */
#define DCU_CTRLDESCL33_3_AB_MASK                0x3u
#define DCU_CTRLDESCL33_3_AB_SHIFT               0
#define DCU_CTRLDESCL33_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_3_AB_SHIFT))&DCU_CTRLDESCL33_3_AB_MASK)
#define DCU_CTRLDESCL33_3_BB_MASK                0x4u
#define DCU_CTRLDESCL33_3_BB_SHIFT               2
#define DCU_CTRLDESCL33_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL33_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL33_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_3_LUOFFS_SHIFT))&DCU_CTRLDESCL33_3_LUOFFS_MASK)
#define DCU_CTRLDESCL33_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL33_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL33_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL33_3_BPP_SHIFT              16
#define DCU_CTRLDESCL33_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_3_BPP_SHIFT))&DCU_CTRLDESCL33_3_BPP_MASK)
#define DCU_CTRLDESCL33_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL33_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL33_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_3_TRANS_SHIFT))&DCU_CTRLDESCL33_3_TRANS_MASK)
#define DCU_CTRLDESCL33_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL33_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL33_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL33_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL33_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL33_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL33_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL33_3_EN_SHIFT               31
/* CTRLDESCL33_4 Bit Fields */
#define DCU_CTRLDESCL33_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL33_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL33_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL33_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL33_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL33_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL33_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL33_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL33_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL33_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL33_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL33_4_CKMAX_R_MASK)
/* CTRLDESCL33_5 Bit Fields */
#define DCU_CTRLDESCL33_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL33_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL33_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL33_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL33_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL33_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL33_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL33_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL33_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL33_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL33_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL33_5_CKMIN_R_MASK)
/* CTRLDESCL33_6 Bit Fields */
#define DCU_CTRLDESCL33_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL33_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL33_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL33_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL33_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL33_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL33_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL33_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL33_7 Bit Fields */
#define DCU_CTRLDESCL33_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL33_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL33_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL33_7_FGn_FCOLOR_MASK)
/* CTRLDESCL33_8 Bit Fields */
#define DCU_CTRLDESCL33_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL33_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL33_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL33_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL33_8_FGn_BCOLOR_MASK)
/* CTRLDESCL34_0 Bit Fields */
#define DCU_CTRLDESCL34_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL34_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL34_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_0_WIDTH_SHIFT))&DCU_CTRLDESCL34_0_WIDTH_MASK)
#define DCU_CTRLDESCL34_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL34_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL34_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_0_HEIGHT_SHIFT))&DCU_CTRLDESCL34_0_HEIGHT_MASK)
/* CTRLDESCL34_1 Bit Fields */
#define DCU_CTRLDESCL34_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL34_1_POSX_SHIFT             0
#define DCU_CTRLDESCL34_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_1_POSX_SHIFT))&DCU_CTRLDESCL34_1_POSX_MASK)
#define DCU_CTRLDESCL34_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL34_1_POSY_SHIFT             16
#define DCU_CTRLDESCL34_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_1_POSY_SHIFT))&DCU_CTRLDESCL34_1_POSY_MASK)
/* CTRLDESCL34_2 Bit Fields */
#define DCU_CTRLDESCL34_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL34_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL34_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_2_ADDR_SHIFT))&DCU_CTRLDESCL34_2_ADDR_MASK)
/* CTRLDESCL34_3 Bit Fields */
#define DCU_CTRLDESCL34_3_AB_MASK                0x3u
#define DCU_CTRLDESCL34_3_AB_SHIFT               0
#define DCU_CTRLDESCL34_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_3_AB_SHIFT))&DCU_CTRLDESCL34_3_AB_MASK)
#define DCU_CTRLDESCL34_3_BB_MASK                0x4u
#define DCU_CTRLDESCL34_3_BB_SHIFT               2
#define DCU_CTRLDESCL34_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL34_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL34_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_3_LUOFFS_SHIFT))&DCU_CTRLDESCL34_3_LUOFFS_MASK)
#define DCU_CTRLDESCL34_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL34_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL34_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL34_3_BPP_SHIFT              16
#define DCU_CTRLDESCL34_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_3_BPP_SHIFT))&DCU_CTRLDESCL34_3_BPP_MASK)
#define DCU_CTRLDESCL34_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL34_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL34_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_3_TRANS_SHIFT))&DCU_CTRLDESCL34_3_TRANS_MASK)
#define DCU_CTRLDESCL34_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL34_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL34_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL34_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL34_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL34_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL34_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL34_3_EN_SHIFT               31
/* CTRLDESCL34_4 Bit Fields */
#define DCU_CTRLDESCL34_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL34_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL34_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL34_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL34_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL34_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL34_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL34_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL34_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL34_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL34_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL34_4_CKMAX_R_MASK)
/* CTRLDESCL34_5 Bit Fields */
#define DCU_CTRLDESCL34_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL34_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL34_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL34_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL34_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL34_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL34_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL34_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL34_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL34_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL34_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL34_5_CKMIN_R_MASK)
/* CTRLDESCL34_6 Bit Fields */
#define DCU_CTRLDESCL34_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL34_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL34_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL34_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL34_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL34_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL34_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL34_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL34_7 Bit Fields */
#define DCU_CTRLDESCL34_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL34_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL34_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL34_7_FGn_FCOLOR_MASK)
/* CTRLDESCL34_8 Bit Fields */
#define DCU_CTRLDESCL34_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL34_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL34_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL34_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL34_8_FGn_BCOLOR_MASK)
/* CTRLDESCL35_0 Bit Fields */
#define DCU_CTRLDESCL35_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL35_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL35_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_0_WIDTH_SHIFT))&DCU_CTRLDESCL35_0_WIDTH_MASK)
#define DCU_CTRLDESCL35_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL35_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL35_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_0_HEIGHT_SHIFT))&DCU_CTRLDESCL35_0_HEIGHT_MASK)
/* CTRLDESCL35_1 Bit Fields */
#define DCU_CTRLDESCL35_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL35_1_POSX_SHIFT             0
#define DCU_CTRLDESCL35_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_1_POSX_SHIFT))&DCU_CTRLDESCL35_1_POSX_MASK)
#define DCU_CTRLDESCL35_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL35_1_POSY_SHIFT             16
#define DCU_CTRLDESCL35_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_1_POSY_SHIFT))&DCU_CTRLDESCL35_1_POSY_MASK)
/* CTRLDESCL35_2 Bit Fields */
#define DCU_CTRLDESCL35_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL35_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL35_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_2_ADDR_SHIFT))&DCU_CTRLDESCL35_2_ADDR_MASK)
/* CTRLDESCL35_3 Bit Fields */
#define DCU_CTRLDESCL35_3_AB_MASK                0x3u
#define DCU_CTRLDESCL35_3_AB_SHIFT               0
#define DCU_CTRLDESCL35_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_3_AB_SHIFT))&DCU_CTRLDESCL35_3_AB_MASK)
#define DCU_CTRLDESCL35_3_BB_MASK                0x4u
#define DCU_CTRLDESCL35_3_BB_SHIFT               2
#define DCU_CTRLDESCL35_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL35_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL35_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_3_LUOFFS_SHIFT))&DCU_CTRLDESCL35_3_LUOFFS_MASK)
#define DCU_CTRLDESCL35_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL35_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL35_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL35_3_BPP_SHIFT              16
#define DCU_CTRLDESCL35_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_3_BPP_SHIFT))&DCU_CTRLDESCL35_3_BPP_MASK)
#define DCU_CTRLDESCL35_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL35_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL35_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_3_TRANS_SHIFT))&DCU_CTRLDESCL35_3_TRANS_MASK)
#define DCU_CTRLDESCL35_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL35_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL35_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL35_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL35_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL35_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL35_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL35_3_EN_SHIFT               31
/* CTRLDESCL35_4 Bit Fields */
#define DCU_CTRLDESCL35_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL35_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL35_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL35_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL35_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL35_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL35_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL35_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL35_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL35_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL35_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL35_4_CKMAX_R_MASK)
/* CTRLDESCL35_5 Bit Fields */
#define DCU_CTRLDESCL35_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL35_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL35_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL35_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL35_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL35_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL35_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL35_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL35_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL35_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL35_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL35_5_CKMIN_R_MASK)
/* CTRLDESCL35_6 Bit Fields */
#define DCU_CTRLDESCL35_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL35_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL35_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL35_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL35_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL35_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL35_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL35_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL35_7 Bit Fields */
#define DCU_CTRLDESCL35_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL35_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL35_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL35_7_FGn_FCOLOR_MASK)
/* CTRLDESCL35_8 Bit Fields */
#define DCU_CTRLDESCL35_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL35_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL35_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL35_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL35_8_FGn_BCOLOR_MASK)
/* CTRLDESCL36_0 Bit Fields */
#define DCU_CTRLDESCL36_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL36_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL36_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_0_WIDTH_SHIFT))&DCU_CTRLDESCL36_0_WIDTH_MASK)
#define DCU_CTRLDESCL36_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL36_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL36_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_0_HEIGHT_SHIFT))&DCU_CTRLDESCL36_0_HEIGHT_MASK)
/* CTRLDESCL36_1 Bit Fields */
#define DCU_CTRLDESCL36_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL36_1_POSX_SHIFT             0
#define DCU_CTRLDESCL36_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_1_POSX_SHIFT))&DCU_CTRLDESCL36_1_POSX_MASK)
#define DCU_CTRLDESCL36_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL36_1_POSY_SHIFT             16
#define DCU_CTRLDESCL36_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_1_POSY_SHIFT))&DCU_CTRLDESCL36_1_POSY_MASK)
/* CTRLDESCL36_2 Bit Fields */
#define DCU_CTRLDESCL36_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL36_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL36_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_2_ADDR_SHIFT))&DCU_CTRLDESCL36_2_ADDR_MASK)
/* CTRLDESCL36_3 Bit Fields */
#define DCU_CTRLDESCL36_3_AB_MASK                0x3u
#define DCU_CTRLDESCL36_3_AB_SHIFT               0
#define DCU_CTRLDESCL36_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_3_AB_SHIFT))&DCU_CTRLDESCL36_3_AB_MASK)
#define DCU_CTRLDESCL36_3_BB_MASK                0x4u
#define DCU_CTRLDESCL36_3_BB_SHIFT               2
#define DCU_CTRLDESCL36_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL36_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL36_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_3_LUOFFS_SHIFT))&DCU_CTRLDESCL36_3_LUOFFS_MASK)
#define DCU_CTRLDESCL36_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL36_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL36_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL36_3_BPP_SHIFT              16
#define DCU_CTRLDESCL36_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_3_BPP_SHIFT))&DCU_CTRLDESCL36_3_BPP_MASK)
#define DCU_CTRLDESCL36_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL36_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL36_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_3_TRANS_SHIFT))&DCU_CTRLDESCL36_3_TRANS_MASK)
#define DCU_CTRLDESCL36_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL36_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL36_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL36_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL36_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL36_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL36_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL36_3_EN_SHIFT               31
/* CTRLDESCL36_4 Bit Fields */
#define DCU_CTRLDESCL36_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL36_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL36_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL36_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL36_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL36_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL36_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL36_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL36_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL36_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL36_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL36_4_CKMAX_R_MASK)
/* CTRLDESCL36_5 Bit Fields */
#define DCU_CTRLDESCL36_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL36_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL36_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL36_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL36_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL36_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL36_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL36_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL36_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL36_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL36_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL36_5_CKMIN_R_MASK)
/* CTRLDESCL36_6 Bit Fields */
#define DCU_CTRLDESCL36_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL36_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL36_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL36_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL36_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL36_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL36_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL36_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL36_7 Bit Fields */
#define DCU_CTRLDESCL36_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL36_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL36_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL36_7_FGn_FCOLOR_MASK)
/* CTRLDESCL36_8 Bit Fields */
#define DCU_CTRLDESCL36_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL36_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL36_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL36_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL36_8_FGn_BCOLOR_MASK)
/* CTRLDESCL37_0 Bit Fields */
#define DCU_CTRLDESCL37_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL37_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL37_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_0_WIDTH_SHIFT))&DCU_CTRLDESCL37_0_WIDTH_MASK)
#define DCU_CTRLDESCL37_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL37_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL37_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_0_HEIGHT_SHIFT))&DCU_CTRLDESCL37_0_HEIGHT_MASK)
/* CTRLDESCL37_1 Bit Fields */
#define DCU_CTRLDESCL37_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL37_1_POSX_SHIFT             0
#define DCU_CTRLDESCL37_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_1_POSX_SHIFT))&DCU_CTRLDESCL37_1_POSX_MASK)
#define DCU_CTRLDESCL37_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL37_1_POSY_SHIFT             16
#define DCU_CTRLDESCL37_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_1_POSY_SHIFT))&DCU_CTRLDESCL37_1_POSY_MASK)
/* CTRLDESCL37_2 Bit Fields */
#define DCU_CTRLDESCL37_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL37_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL37_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_2_ADDR_SHIFT))&DCU_CTRLDESCL37_2_ADDR_MASK)
/* CTRLDESCL37_3 Bit Fields */
#define DCU_CTRLDESCL37_3_AB_MASK                0x3u
#define DCU_CTRLDESCL37_3_AB_SHIFT               0
#define DCU_CTRLDESCL37_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_3_AB_SHIFT))&DCU_CTRLDESCL37_3_AB_MASK)
#define DCU_CTRLDESCL37_3_BB_MASK                0x4u
#define DCU_CTRLDESCL37_3_BB_SHIFT               2
#define DCU_CTRLDESCL37_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL37_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL37_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_3_LUOFFS_SHIFT))&DCU_CTRLDESCL37_3_LUOFFS_MASK)
#define DCU_CTRLDESCL37_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL37_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL37_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL37_3_BPP_SHIFT              16
#define DCU_CTRLDESCL37_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_3_BPP_SHIFT))&DCU_CTRLDESCL37_3_BPP_MASK)
#define DCU_CTRLDESCL37_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL37_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL37_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_3_TRANS_SHIFT))&DCU_CTRLDESCL37_3_TRANS_MASK)
#define DCU_CTRLDESCL37_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL37_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL37_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL37_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL37_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL37_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL37_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL37_3_EN_SHIFT               31
/* CTRLDESCL37_4 Bit Fields */
#define DCU_CTRLDESCL37_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL37_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL37_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL37_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL37_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL37_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL37_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL37_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL37_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL37_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL37_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL37_4_CKMAX_R_MASK)
/* CTRLDESCL37_5 Bit Fields */
#define DCU_CTRLDESCL37_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL37_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL37_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL37_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL37_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL37_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL37_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL37_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL37_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL37_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL37_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL37_5_CKMIN_R_MASK)
/* CTRLDESCL37_6 Bit Fields */
#define DCU_CTRLDESCL37_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL37_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL37_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL37_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL37_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL37_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL37_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL37_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL37_7 Bit Fields */
#define DCU_CTRLDESCL37_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL37_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL37_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL37_7_FGn_FCOLOR_MASK)
/* CTRLDESCL37_8 Bit Fields */
#define DCU_CTRLDESCL37_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL37_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL37_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL37_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL37_8_FGn_BCOLOR_MASK)
/* CTRLDESCL38_0 Bit Fields */
#define DCU_CTRLDESCL38_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL38_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL38_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_0_WIDTH_SHIFT))&DCU_CTRLDESCL38_0_WIDTH_MASK)
#define DCU_CTRLDESCL38_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL38_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL38_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_0_HEIGHT_SHIFT))&DCU_CTRLDESCL38_0_HEIGHT_MASK)
/* CTRLDESCL38_1 Bit Fields */
#define DCU_CTRLDESCL38_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL38_1_POSX_SHIFT             0
#define DCU_CTRLDESCL38_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_1_POSX_SHIFT))&DCU_CTRLDESCL38_1_POSX_MASK)
#define DCU_CTRLDESCL38_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL38_1_POSY_SHIFT             16
#define DCU_CTRLDESCL38_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_1_POSY_SHIFT))&DCU_CTRLDESCL38_1_POSY_MASK)
/* CTRLDESCL38_2 Bit Fields */
#define DCU_CTRLDESCL38_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL38_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL38_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_2_ADDR_SHIFT))&DCU_CTRLDESCL38_2_ADDR_MASK)
/* CTRLDESCL38_3 Bit Fields */
#define DCU_CTRLDESCL38_3_AB_MASK                0x3u
#define DCU_CTRLDESCL38_3_AB_SHIFT               0
#define DCU_CTRLDESCL38_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_3_AB_SHIFT))&DCU_CTRLDESCL38_3_AB_MASK)
#define DCU_CTRLDESCL38_3_BB_MASK                0x4u
#define DCU_CTRLDESCL38_3_BB_SHIFT               2
#define DCU_CTRLDESCL38_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL38_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL38_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_3_LUOFFS_SHIFT))&DCU_CTRLDESCL38_3_LUOFFS_MASK)
#define DCU_CTRLDESCL38_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL38_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL38_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL38_3_BPP_SHIFT              16
#define DCU_CTRLDESCL38_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_3_BPP_SHIFT))&DCU_CTRLDESCL38_3_BPP_MASK)
#define DCU_CTRLDESCL38_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL38_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL38_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_3_TRANS_SHIFT))&DCU_CTRLDESCL38_3_TRANS_MASK)
#define DCU_CTRLDESCL38_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL38_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL38_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL38_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL38_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL38_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL38_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL38_3_EN_SHIFT               31
/* CTRLDESCL38_4 Bit Fields */
#define DCU_CTRLDESCL38_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL38_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL38_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL38_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL38_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL38_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL38_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL38_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL38_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL38_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL38_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL38_4_CKMAX_R_MASK)
/* CTRLDESCL38_5 Bit Fields */
#define DCU_CTRLDESCL38_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL38_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL38_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL38_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL38_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL38_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL38_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL38_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL38_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL38_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL38_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL38_5_CKMIN_R_MASK)
/* CTRLDESCL38_6 Bit Fields */
#define DCU_CTRLDESCL38_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL38_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL38_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL38_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL38_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL38_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL38_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL38_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL38_7 Bit Fields */
#define DCU_CTRLDESCL38_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL38_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL38_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL38_7_FGn_FCOLOR_MASK)
/* CTRLDESCL38_8 Bit Fields */
#define DCU_CTRLDESCL38_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL38_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL38_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL38_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL38_8_FGn_BCOLOR_MASK)
/* CTRLDESCL39_0 Bit Fields */
#define DCU_CTRLDESCL39_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL39_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL39_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_0_WIDTH_SHIFT))&DCU_CTRLDESCL39_0_WIDTH_MASK)
#define DCU_CTRLDESCL39_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL39_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL39_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_0_HEIGHT_SHIFT))&DCU_CTRLDESCL39_0_HEIGHT_MASK)
/* CTRLDESCL39_1 Bit Fields */
#define DCU_CTRLDESCL39_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL39_1_POSX_SHIFT             0
#define DCU_CTRLDESCL39_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_1_POSX_SHIFT))&DCU_CTRLDESCL39_1_POSX_MASK)
#define DCU_CTRLDESCL39_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL39_1_POSY_SHIFT             16
#define DCU_CTRLDESCL39_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_1_POSY_SHIFT))&DCU_CTRLDESCL39_1_POSY_MASK)
/* CTRLDESCL39_2 Bit Fields */
#define DCU_CTRLDESCL39_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL39_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL39_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_2_ADDR_SHIFT))&DCU_CTRLDESCL39_2_ADDR_MASK)
/* CTRLDESCL39_3 Bit Fields */
#define DCU_CTRLDESCL39_3_AB_MASK                0x3u
#define DCU_CTRLDESCL39_3_AB_SHIFT               0
#define DCU_CTRLDESCL39_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_3_AB_SHIFT))&DCU_CTRLDESCL39_3_AB_MASK)
#define DCU_CTRLDESCL39_3_BB_MASK                0x4u
#define DCU_CTRLDESCL39_3_BB_SHIFT               2
#define DCU_CTRLDESCL39_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL39_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL39_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_3_LUOFFS_SHIFT))&DCU_CTRLDESCL39_3_LUOFFS_MASK)
#define DCU_CTRLDESCL39_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL39_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL39_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL39_3_BPP_SHIFT              16
#define DCU_CTRLDESCL39_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_3_BPP_SHIFT))&DCU_CTRLDESCL39_3_BPP_MASK)
#define DCU_CTRLDESCL39_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL39_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL39_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_3_TRANS_SHIFT))&DCU_CTRLDESCL39_3_TRANS_MASK)
#define DCU_CTRLDESCL39_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL39_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL39_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL39_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL39_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL39_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL39_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL39_3_EN_SHIFT               31
/* CTRLDESCL39_4 Bit Fields */
#define DCU_CTRLDESCL39_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL39_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL39_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL39_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL39_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL39_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL39_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL39_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL39_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL39_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL39_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL39_4_CKMAX_R_MASK)
/* CTRLDESCL39_5 Bit Fields */
#define DCU_CTRLDESCL39_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL39_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL39_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL39_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL39_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL39_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL39_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL39_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL39_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL39_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL39_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL39_5_CKMIN_R_MASK)
/* CTRLDESCL39_6 Bit Fields */
#define DCU_CTRLDESCL39_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL39_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL39_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL39_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL39_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL39_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL39_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL39_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL39_7 Bit Fields */
#define DCU_CTRLDESCL39_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL39_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL39_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL39_7_FGn_FCOLOR_MASK)
/* CTRLDESCL39_8 Bit Fields */
#define DCU_CTRLDESCL39_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL39_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL39_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL39_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL39_8_FGn_BCOLOR_MASK)
/* CTRLDESCL40_0 Bit Fields */
#define DCU_CTRLDESCL40_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL40_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL40_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_0_WIDTH_SHIFT))&DCU_CTRLDESCL40_0_WIDTH_MASK)
#define DCU_CTRLDESCL40_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL40_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL40_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_0_HEIGHT_SHIFT))&DCU_CTRLDESCL40_0_HEIGHT_MASK)
/* CTRLDESCL40_1 Bit Fields */
#define DCU_CTRLDESCL40_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL40_1_POSX_SHIFT             0
#define DCU_CTRLDESCL40_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_1_POSX_SHIFT))&DCU_CTRLDESCL40_1_POSX_MASK)
#define DCU_CTRLDESCL40_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL40_1_POSY_SHIFT             16
#define DCU_CTRLDESCL40_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_1_POSY_SHIFT))&DCU_CTRLDESCL40_1_POSY_MASK)
/* CTRLDESCL40_2 Bit Fields */
#define DCU_CTRLDESCL40_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL40_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL40_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_2_ADDR_SHIFT))&DCU_CTRLDESCL40_2_ADDR_MASK)
/* CTRLDESCL40_3 Bit Fields */
#define DCU_CTRLDESCL40_3_AB_MASK                0x3u
#define DCU_CTRLDESCL40_3_AB_SHIFT               0
#define DCU_CTRLDESCL40_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_3_AB_SHIFT))&DCU_CTRLDESCL40_3_AB_MASK)
#define DCU_CTRLDESCL40_3_BB_MASK                0x4u
#define DCU_CTRLDESCL40_3_BB_SHIFT               2
#define DCU_CTRLDESCL40_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL40_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL40_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_3_LUOFFS_SHIFT))&DCU_CTRLDESCL40_3_LUOFFS_MASK)
#define DCU_CTRLDESCL40_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL40_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL40_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL40_3_BPP_SHIFT              16
#define DCU_CTRLDESCL40_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_3_BPP_SHIFT))&DCU_CTRLDESCL40_3_BPP_MASK)
#define DCU_CTRLDESCL40_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL40_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL40_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_3_TRANS_SHIFT))&DCU_CTRLDESCL40_3_TRANS_MASK)
#define DCU_CTRLDESCL40_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL40_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL40_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL40_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL40_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL40_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL40_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL40_3_EN_SHIFT               31
/* CTRLDESCL40_4 Bit Fields */
#define DCU_CTRLDESCL40_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL40_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL40_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL40_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL40_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL40_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL40_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL40_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL40_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL40_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL40_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL40_4_CKMAX_R_MASK)
/* CTRLDESCL40_5 Bit Fields */
#define DCU_CTRLDESCL40_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL40_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL40_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL40_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL40_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL40_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL40_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL40_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL40_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL40_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL40_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL40_5_CKMIN_R_MASK)
/* CTRLDESCL40_6 Bit Fields */
#define DCU_CTRLDESCL40_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL40_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL40_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL40_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL40_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL40_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL40_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL40_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL40_7 Bit Fields */
#define DCU_CTRLDESCL40_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL40_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL40_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL40_7_FGn_FCOLOR_MASK)
/* CTRLDESCL40_8 Bit Fields */
#define DCU_CTRLDESCL40_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL40_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL40_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL40_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL40_8_FGn_BCOLOR_MASK)
/* CTRLDESCL41_0 Bit Fields */
#define DCU_CTRLDESCL41_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL41_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL41_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_0_WIDTH_SHIFT))&DCU_CTRLDESCL41_0_WIDTH_MASK)
#define DCU_CTRLDESCL41_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL41_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL41_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_0_HEIGHT_SHIFT))&DCU_CTRLDESCL41_0_HEIGHT_MASK)
/* CTRLDESCL41_1 Bit Fields */
#define DCU_CTRLDESCL41_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL41_1_POSX_SHIFT             0
#define DCU_CTRLDESCL41_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_1_POSX_SHIFT))&DCU_CTRLDESCL41_1_POSX_MASK)
#define DCU_CTRLDESCL41_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL41_1_POSY_SHIFT             16
#define DCU_CTRLDESCL41_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_1_POSY_SHIFT))&DCU_CTRLDESCL41_1_POSY_MASK)
/* CTRLDESCL41_2 Bit Fields */
#define DCU_CTRLDESCL41_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL41_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL41_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_2_ADDR_SHIFT))&DCU_CTRLDESCL41_2_ADDR_MASK)
/* CTRLDESCL41_3 Bit Fields */
#define DCU_CTRLDESCL41_3_AB_MASK                0x3u
#define DCU_CTRLDESCL41_3_AB_SHIFT               0
#define DCU_CTRLDESCL41_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_3_AB_SHIFT))&DCU_CTRLDESCL41_3_AB_MASK)
#define DCU_CTRLDESCL41_3_BB_MASK                0x4u
#define DCU_CTRLDESCL41_3_BB_SHIFT               2
#define DCU_CTRLDESCL41_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL41_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL41_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_3_LUOFFS_SHIFT))&DCU_CTRLDESCL41_3_LUOFFS_MASK)
#define DCU_CTRLDESCL41_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL41_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL41_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL41_3_BPP_SHIFT              16
#define DCU_CTRLDESCL41_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_3_BPP_SHIFT))&DCU_CTRLDESCL41_3_BPP_MASK)
#define DCU_CTRLDESCL41_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL41_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL41_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_3_TRANS_SHIFT))&DCU_CTRLDESCL41_3_TRANS_MASK)
#define DCU_CTRLDESCL41_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL41_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL41_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL41_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL41_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL41_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL41_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL41_3_EN_SHIFT               31
/* CTRLDESCL41_4 Bit Fields */
#define DCU_CTRLDESCL41_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL41_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL41_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL41_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL41_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL41_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL41_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL41_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL41_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL41_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL41_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL41_4_CKMAX_R_MASK)
/* CTRLDESCL41_5 Bit Fields */
#define DCU_CTRLDESCL41_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL41_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL41_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL41_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL41_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL41_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL41_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL41_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL41_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL41_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL41_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL41_5_CKMIN_R_MASK)
/* CTRLDESCL41_6 Bit Fields */
#define DCU_CTRLDESCL41_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL41_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL41_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL41_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL41_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL41_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL41_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL41_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL41_7 Bit Fields */
#define DCU_CTRLDESCL41_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL41_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL41_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL41_7_FGn_FCOLOR_MASK)
/* CTRLDESCL41_8 Bit Fields */
#define DCU_CTRLDESCL41_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL41_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL41_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL41_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL41_8_FGn_BCOLOR_MASK)
/* CTRLDESCL42_0 Bit Fields */
#define DCU_CTRLDESCL42_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL42_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL42_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_0_WIDTH_SHIFT))&DCU_CTRLDESCL42_0_WIDTH_MASK)
#define DCU_CTRLDESCL42_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL42_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL42_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_0_HEIGHT_SHIFT))&DCU_CTRLDESCL42_0_HEIGHT_MASK)
/* CTRLDESCL42_1 Bit Fields */
#define DCU_CTRLDESCL42_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL42_1_POSX_SHIFT             0
#define DCU_CTRLDESCL42_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_1_POSX_SHIFT))&DCU_CTRLDESCL42_1_POSX_MASK)
#define DCU_CTRLDESCL42_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL42_1_POSY_SHIFT             16
#define DCU_CTRLDESCL42_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_1_POSY_SHIFT))&DCU_CTRLDESCL42_1_POSY_MASK)
/* CTRLDESCL42_2 Bit Fields */
#define DCU_CTRLDESCL42_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL42_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL42_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_2_ADDR_SHIFT))&DCU_CTRLDESCL42_2_ADDR_MASK)
/* CTRLDESCL42_3 Bit Fields */
#define DCU_CTRLDESCL42_3_AB_MASK                0x3u
#define DCU_CTRLDESCL42_3_AB_SHIFT               0
#define DCU_CTRLDESCL42_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_3_AB_SHIFT))&DCU_CTRLDESCL42_3_AB_MASK)
#define DCU_CTRLDESCL42_3_BB_MASK                0x4u
#define DCU_CTRLDESCL42_3_BB_SHIFT               2
#define DCU_CTRLDESCL42_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL42_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL42_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_3_LUOFFS_SHIFT))&DCU_CTRLDESCL42_3_LUOFFS_MASK)
#define DCU_CTRLDESCL42_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL42_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL42_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL42_3_BPP_SHIFT              16
#define DCU_CTRLDESCL42_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_3_BPP_SHIFT))&DCU_CTRLDESCL42_3_BPP_MASK)
#define DCU_CTRLDESCL42_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL42_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL42_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_3_TRANS_SHIFT))&DCU_CTRLDESCL42_3_TRANS_MASK)
#define DCU_CTRLDESCL42_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL42_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL42_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL42_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL42_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL42_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL42_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL42_3_EN_SHIFT               31
/* CTRLDESCL42_4 Bit Fields */
#define DCU_CTRLDESCL42_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL42_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL42_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL42_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL42_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL42_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL42_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL42_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL42_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL42_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL42_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL42_4_CKMAX_R_MASK)
/* CTRLDESCL42_5 Bit Fields */
#define DCU_CTRLDESCL42_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL42_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL42_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL42_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL42_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL42_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL42_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL42_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL42_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL42_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL42_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL42_5_CKMIN_R_MASK)
/* CTRLDESCL42_6 Bit Fields */
#define DCU_CTRLDESCL42_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL42_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL42_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL42_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL42_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL42_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL42_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL42_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL42_7 Bit Fields */
#define DCU_CTRLDESCL42_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL42_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL42_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL42_7_FGn_FCOLOR_MASK)
/* CTRLDESCL42_8 Bit Fields */
#define DCU_CTRLDESCL42_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL42_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL42_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL42_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL42_8_FGn_BCOLOR_MASK)
/* CTRLDESCL43_0 Bit Fields */
#define DCU_CTRLDESCL43_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL43_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL43_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_0_WIDTH_SHIFT))&DCU_CTRLDESCL43_0_WIDTH_MASK)
#define DCU_CTRLDESCL43_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL43_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL43_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_0_HEIGHT_SHIFT))&DCU_CTRLDESCL43_0_HEIGHT_MASK)
/* CTRLDESCL43_1 Bit Fields */
#define DCU_CTRLDESCL43_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL43_1_POSX_SHIFT             0
#define DCU_CTRLDESCL43_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_1_POSX_SHIFT))&DCU_CTRLDESCL43_1_POSX_MASK)
#define DCU_CTRLDESCL43_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL43_1_POSY_SHIFT             16
#define DCU_CTRLDESCL43_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_1_POSY_SHIFT))&DCU_CTRLDESCL43_1_POSY_MASK)
/* CTRLDESCL43_2 Bit Fields */
#define DCU_CTRLDESCL43_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL43_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL43_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_2_ADDR_SHIFT))&DCU_CTRLDESCL43_2_ADDR_MASK)
/* CTRLDESCL43_3 Bit Fields */
#define DCU_CTRLDESCL43_3_AB_MASK                0x3u
#define DCU_CTRLDESCL43_3_AB_SHIFT               0
#define DCU_CTRLDESCL43_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_3_AB_SHIFT))&DCU_CTRLDESCL43_3_AB_MASK)
#define DCU_CTRLDESCL43_3_BB_MASK                0x4u
#define DCU_CTRLDESCL43_3_BB_SHIFT               2
#define DCU_CTRLDESCL43_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL43_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL43_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_3_LUOFFS_SHIFT))&DCU_CTRLDESCL43_3_LUOFFS_MASK)
#define DCU_CTRLDESCL43_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL43_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL43_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL43_3_BPP_SHIFT              16
#define DCU_CTRLDESCL43_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_3_BPP_SHIFT))&DCU_CTRLDESCL43_3_BPP_MASK)
#define DCU_CTRLDESCL43_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL43_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL43_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_3_TRANS_SHIFT))&DCU_CTRLDESCL43_3_TRANS_MASK)
#define DCU_CTRLDESCL43_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL43_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL43_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL43_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL43_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL43_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL43_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL43_3_EN_SHIFT               31
/* CTRLDESCL43_4 Bit Fields */
#define DCU_CTRLDESCL43_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL43_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL43_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL43_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL43_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL43_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL43_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL43_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL43_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL43_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL43_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL43_4_CKMAX_R_MASK)
/* CTRLDESCL43_5 Bit Fields */
#define DCU_CTRLDESCL43_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL43_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL43_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL43_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL43_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL43_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL43_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL43_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL43_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL43_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL43_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL43_5_CKMIN_R_MASK)
/* CTRLDESCL43_6 Bit Fields */
#define DCU_CTRLDESCL43_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL43_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL43_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL43_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL43_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL43_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL43_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL43_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL43_7 Bit Fields */
#define DCU_CTRLDESCL43_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL43_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL43_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL43_7_FGn_FCOLOR_MASK)
/* CTRLDESCL43_8 Bit Fields */
#define DCU_CTRLDESCL43_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL43_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL43_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL43_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL43_8_FGn_BCOLOR_MASK)
/* CTRLDESCL44_0 Bit Fields */
#define DCU_CTRLDESCL44_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL44_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL44_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_0_WIDTH_SHIFT))&DCU_CTRLDESCL44_0_WIDTH_MASK)
#define DCU_CTRLDESCL44_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL44_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL44_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_0_HEIGHT_SHIFT))&DCU_CTRLDESCL44_0_HEIGHT_MASK)
/* CTRLDESCL44_1 Bit Fields */
#define DCU_CTRLDESCL44_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL44_1_POSX_SHIFT             0
#define DCU_CTRLDESCL44_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_1_POSX_SHIFT))&DCU_CTRLDESCL44_1_POSX_MASK)
#define DCU_CTRLDESCL44_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL44_1_POSY_SHIFT             16
#define DCU_CTRLDESCL44_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_1_POSY_SHIFT))&DCU_CTRLDESCL44_1_POSY_MASK)
/* CTRLDESCL44_2 Bit Fields */
#define DCU_CTRLDESCL44_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL44_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL44_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_2_ADDR_SHIFT))&DCU_CTRLDESCL44_2_ADDR_MASK)
/* CTRLDESCL44_3 Bit Fields */
#define DCU_CTRLDESCL44_3_AB_MASK                0x3u
#define DCU_CTRLDESCL44_3_AB_SHIFT               0
#define DCU_CTRLDESCL44_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_3_AB_SHIFT))&DCU_CTRLDESCL44_3_AB_MASK)
#define DCU_CTRLDESCL44_3_BB_MASK                0x4u
#define DCU_CTRLDESCL44_3_BB_SHIFT               2
#define DCU_CTRLDESCL44_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL44_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL44_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_3_LUOFFS_SHIFT))&DCU_CTRLDESCL44_3_LUOFFS_MASK)
#define DCU_CTRLDESCL44_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL44_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL44_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL44_3_BPP_SHIFT              16
#define DCU_CTRLDESCL44_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_3_BPP_SHIFT))&DCU_CTRLDESCL44_3_BPP_MASK)
#define DCU_CTRLDESCL44_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL44_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL44_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_3_TRANS_SHIFT))&DCU_CTRLDESCL44_3_TRANS_MASK)
#define DCU_CTRLDESCL44_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL44_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL44_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL44_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL44_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL44_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL44_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL44_3_EN_SHIFT               31
/* CTRLDESCL44_4 Bit Fields */
#define DCU_CTRLDESCL44_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL44_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL44_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL44_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL44_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL44_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL44_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL44_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL44_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL44_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL44_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL44_4_CKMAX_R_MASK)
/* CTRLDESCL44_5 Bit Fields */
#define DCU_CTRLDESCL44_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL44_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL44_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL44_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL44_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL44_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL44_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL44_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL44_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL44_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL44_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL44_5_CKMIN_R_MASK)
/* CTRLDESCL44_6 Bit Fields */
#define DCU_CTRLDESCL44_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL44_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL44_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL44_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL44_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL44_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL44_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL44_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL44_7 Bit Fields */
#define DCU_CTRLDESCL44_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL44_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL44_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL44_7_FGn_FCOLOR_MASK)
/* CTRLDESCL44_8 Bit Fields */
#define DCU_CTRLDESCL44_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL44_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL44_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL44_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL44_8_FGn_BCOLOR_MASK)
/* CTRLDESCL45_0 Bit Fields */
#define DCU_CTRLDESCL45_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL45_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL45_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_0_WIDTH_SHIFT))&DCU_CTRLDESCL45_0_WIDTH_MASK)
#define DCU_CTRLDESCL45_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL45_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL45_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_0_HEIGHT_SHIFT))&DCU_CTRLDESCL45_0_HEIGHT_MASK)
/* CTRLDESCL45_1 Bit Fields */
#define DCU_CTRLDESCL45_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL45_1_POSX_SHIFT             0
#define DCU_CTRLDESCL45_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_1_POSX_SHIFT))&DCU_CTRLDESCL45_1_POSX_MASK)
#define DCU_CTRLDESCL45_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL45_1_POSY_SHIFT             16
#define DCU_CTRLDESCL45_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_1_POSY_SHIFT))&DCU_CTRLDESCL45_1_POSY_MASK)
/* CTRLDESCL45_2 Bit Fields */
#define DCU_CTRLDESCL45_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL45_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL45_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_2_ADDR_SHIFT))&DCU_CTRLDESCL45_2_ADDR_MASK)
/* CTRLDESCL45_3 Bit Fields */
#define DCU_CTRLDESCL45_3_AB_MASK                0x3u
#define DCU_CTRLDESCL45_3_AB_SHIFT               0
#define DCU_CTRLDESCL45_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_3_AB_SHIFT))&DCU_CTRLDESCL45_3_AB_MASK)
#define DCU_CTRLDESCL45_3_BB_MASK                0x4u
#define DCU_CTRLDESCL45_3_BB_SHIFT               2
#define DCU_CTRLDESCL45_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL45_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL45_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_3_LUOFFS_SHIFT))&DCU_CTRLDESCL45_3_LUOFFS_MASK)
#define DCU_CTRLDESCL45_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL45_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL45_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL45_3_BPP_SHIFT              16
#define DCU_CTRLDESCL45_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_3_BPP_SHIFT))&DCU_CTRLDESCL45_3_BPP_MASK)
#define DCU_CTRLDESCL45_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL45_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL45_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_3_TRANS_SHIFT))&DCU_CTRLDESCL45_3_TRANS_MASK)
#define DCU_CTRLDESCL45_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL45_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL45_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL45_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL45_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL45_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL45_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL45_3_EN_SHIFT               31
/* CTRLDESCL45_4 Bit Fields */
#define DCU_CTRLDESCL45_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL45_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL45_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL45_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL45_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL45_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL45_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL45_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL45_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL45_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL45_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL45_4_CKMAX_R_MASK)
/* CTRLDESCL45_5 Bit Fields */
#define DCU_CTRLDESCL45_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL45_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL45_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL45_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL45_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL45_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL45_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL45_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL45_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL45_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL45_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL45_5_CKMIN_R_MASK)
/* CTRLDESCL45_6 Bit Fields */
#define DCU_CTRLDESCL45_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL45_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL45_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL45_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL45_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL45_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL45_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL45_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL45_7 Bit Fields */
#define DCU_CTRLDESCL45_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL45_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL45_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL45_7_FGn_FCOLOR_MASK)
/* CTRLDESCL45_8 Bit Fields */
#define DCU_CTRLDESCL45_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL45_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL45_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL45_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL45_8_FGn_BCOLOR_MASK)
/* CTRLDESCL46_0 Bit Fields */
#define DCU_CTRLDESCL46_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL46_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL46_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_0_WIDTH_SHIFT))&DCU_CTRLDESCL46_0_WIDTH_MASK)
#define DCU_CTRLDESCL46_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL46_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL46_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_0_HEIGHT_SHIFT))&DCU_CTRLDESCL46_0_HEIGHT_MASK)
/* CTRLDESCL46_1 Bit Fields */
#define DCU_CTRLDESCL46_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL46_1_POSX_SHIFT             0
#define DCU_CTRLDESCL46_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_1_POSX_SHIFT))&DCU_CTRLDESCL46_1_POSX_MASK)
#define DCU_CTRLDESCL46_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL46_1_POSY_SHIFT             16
#define DCU_CTRLDESCL46_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_1_POSY_SHIFT))&DCU_CTRLDESCL46_1_POSY_MASK)
/* CTRLDESCL46_2 Bit Fields */
#define DCU_CTRLDESCL46_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL46_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL46_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_2_ADDR_SHIFT))&DCU_CTRLDESCL46_2_ADDR_MASK)
/* CTRLDESCL46_3 Bit Fields */
#define DCU_CTRLDESCL46_3_AB_MASK                0x3u
#define DCU_CTRLDESCL46_3_AB_SHIFT               0
#define DCU_CTRLDESCL46_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_3_AB_SHIFT))&DCU_CTRLDESCL46_3_AB_MASK)
#define DCU_CTRLDESCL46_3_BB_MASK                0x4u
#define DCU_CTRLDESCL46_3_BB_SHIFT               2
#define DCU_CTRLDESCL46_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL46_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL46_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_3_LUOFFS_SHIFT))&DCU_CTRLDESCL46_3_LUOFFS_MASK)
#define DCU_CTRLDESCL46_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL46_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL46_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL46_3_BPP_SHIFT              16
#define DCU_CTRLDESCL46_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_3_BPP_SHIFT))&DCU_CTRLDESCL46_3_BPP_MASK)
#define DCU_CTRLDESCL46_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL46_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL46_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_3_TRANS_SHIFT))&DCU_CTRLDESCL46_3_TRANS_MASK)
#define DCU_CTRLDESCL46_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL46_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL46_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL46_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL46_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL46_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL46_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL46_3_EN_SHIFT               31
/* CTRLDESCL46_4 Bit Fields */
#define DCU_CTRLDESCL46_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL46_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL46_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL46_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL46_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL46_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL46_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL46_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL46_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL46_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL46_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL46_4_CKMAX_R_MASK)
/* CTRLDESCL46_5 Bit Fields */
#define DCU_CTRLDESCL46_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL46_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL46_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL46_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL46_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL46_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL46_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL46_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL46_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL46_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL46_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL46_5_CKMIN_R_MASK)
/* CTRLDESCL46_6 Bit Fields */
#define DCU_CTRLDESCL46_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL46_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL46_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL46_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL46_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL46_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL46_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL46_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL46_7 Bit Fields */
#define DCU_CTRLDESCL46_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL46_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL46_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL46_7_FGn_FCOLOR_MASK)
/* CTRLDESCL46_8 Bit Fields */
#define DCU_CTRLDESCL46_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL46_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL46_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL46_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL46_8_FGn_BCOLOR_MASK)
/* CTRLDESCL47_0 Bit Fields */
#define DCU_CTRLDESCL47_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL47_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL47_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_0_WIDTH_SHIFT))&DCU_CTRLDESCL47_0_WIDTH_MASK)
#define DCU_CTRLDESCL47_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL47_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL47_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_0_HEIGHT_SHIFT))&DCU_CTRLDESCL47_0_HEIGHT_MASK)
/* CTRLDESCL47_1 Bit Fields */
#define DCU_CTRLDESCL47_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL47_1_POSX_SHIFT             0
#define DCU_CTRLDESCL47_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_1_POSX_SHIFT))&DCU_CTRLDESCL47_1_POSX_MASK)
#define DCU_CTRLDESCL47_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL47_1_POSY_SHIFT             16
#define DCU_CTRLDESCL47_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_1_POSY_SHIFT))&DCU_CTRLDESCL47_1_POSY_MASK)
/* CTRLDESCL47_2 Bit Fields */
#define DCU_CTRLDESCL47_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL47_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL47_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_2_ADDR_SHIFT))&DCU_CTRLDESCL47_2_ADDR_MASK)
/* CTRLDESCL47_3 Bit Fields */
#define DCU_CTRLDESCL47_3_AB_MASK                0x3u
#define DCU_CTRLDESCL47_3_AB_SHIFT               0
#define DCU_CTRLDESCL47_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_3_AB_SHIFT))&DCU_CTRLDESCL47_3_AB_MASK)
#define DCU_CTRLDESCL47_3_BB_MASK                0x4u
#define DCU_CTRLDESCL47_3_BB_SHIFT               2
#define DCU_CTRLDESCL47_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL47_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL47_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_3_LUOFFS_SHIFT))&DCU_CTRLDESCL47_3_LUOFFS_MASK)
#define DCU_CTRLDESCL47_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL47_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL47_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL47_3_BPP_SHIFT              16
#define DCU_CTRLDESCL47_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_3_BPP_SHIFT))&DCU_CTRLDESCL47_3_BPP_MASK)
#define DCU_CTRLDESCL47_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL47_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL47_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_3_TRANS_SHIFT))&DCU_CTRLDESCL47_3_TRANS_MASK)
#define DCU_CTRLDESCL47_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL47_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL47_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL47_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL47_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL47_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL47_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL47_3_EN_SHIFT               31
/* CTRLDESCL47_4 Bit Fields */
#define DCU_CTRLDESCL47_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL47_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL47_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL47_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL47_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL47_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL47_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL47_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL47_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL47_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL47_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL47_4_CKMAX_R_MASK)
/* CTRLDESCL47_5 Bit Fields */
#define DCU_CTRLDESCL47_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL47_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL47_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL47_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL47_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL47_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL47_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL47_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL47_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL47_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL47_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL47_5_CKMIN_R_MASK)
/* CTRLDESCL47_6 Bit Fields */
#define DCU_CTRLDESCL47_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL47_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL47_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL47_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL47_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL47_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL47_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL47_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL47_7 Bit Fields */
#define DCU_CTRLDESCL47_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL47_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL47_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL47_7_FGn_FCOLOR_MASK)
/* CTRLDESCL47_8 Bit Fields */
#define DCU_CTRLDESCL47_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL47_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL47_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL47_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL47_8_FGn_BCOLOR_MASK)
/* CTRLDESCL48_0 Bit Fields */
#define DCU_CTRLDESCL48_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL48_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL48_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_0_WIDTH_SHIFT))&DCU_CTRLDESCL48_0_WIDTH_MASK)
#define DCU_CTRLDESCL48_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL48_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL48_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_0_HEIGHT_SHIFT))&DCU_CTRLDESCL48_0_HEIGHT_MASK)
/* CTRLDESCL48_1 Bit Fields */
#define DCU_CTRLDESCL48_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL48_1_POSX_SHIFT             0
#define DCU_CTRLDESCL48_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_1_POSX_SHIFT))&DCU_CTRLDESCL48_1_POSX_MASK)
#define DCU_CTRLDESCL48_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL48_1_POSY_SHIFT             16
#define DCU_CTRLDESCL48_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_1_POSY_SHIFT))&DCU_CTRLDESCL48_1_POSY_MASK)
/* CTRLDESCL48_2 Bit Fields */
#define DCU_CTRLDESCL48_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL48_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL48_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_2_ADDR_SHIFT))&DCU_CTRLDESCL48_2_ADDR_MASK)
/* CTRLDESCL48_3 Bit Fields */
#define DCU_CTRLDESCL48_3_AB_MASK                0x3u
#define DCU_CTRLDESCL48_3_AB_SHIFT               0
#define DCU_CTRLDESCL48_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_3_AB_SHIFT))&DCU_CTRLDESCL48_3_AB_MASK)
#define DCU_CTRLDESCL48_3_BB_MASK                0x4u
#define DCU_CTRLDESCL48_3_BB_SHIFT               2
#define DCU_CTRLDESCL48_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL48_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL48_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_3_LUOFFS_SHIFT))&DCU_CTRLDESCL48_3_LUOFFS_MASK)
#define DCU_CTRLDESCL48_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL48_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL48_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL48_3_BPP_SHIFT              16
#define DCU_CTRLDESCL48_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_3_BPP_SHIFT))&DCU_CTRLDESCL48_3_BPP_MASK)
#define DCU_CTRLDESCL48_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL48_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL48_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_3_TRANS_SHIFT))&DCU_CTRLDESCL48_3_TRANS_MASK)
#define DCU_CTRLDESCL48_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL48_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL48_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL48_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL48_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL48_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL48_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL48_3_EN_SHIFT               31
/* CTRLDESCL48_4 Bit Fields */
#define DCU_CTRLDESCL48_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL48_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL48_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL48_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL48_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL48_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL48_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL48_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL48_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL48_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL48_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL48_4_CKMAX_R_MASK)
/* CTRLDESCL48_5 Bit Fields */
#define DCU_CTRLDESCL48_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL48_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL48_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL48_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL48_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL48_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL48_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL48_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL48_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL48_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL48_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL48_5_CKMIN_R_MASK)
/* CTRLDESCL48_6 Bit Fields */
#define DCU_CTRLDESCL48_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL48_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL48_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL48_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL48_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL48_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL48_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL48_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL48_7 Bit Fields */
#define DCU_CTRLDESCL48_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL48_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL48_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL48_7_FGn_FCOLOR_MASK)
/* CTRLDESCL48_8 Bit Fields */
#define DCU_CTRLDESCL48_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL48_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL48_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL48_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL48_8_FGn_BCOLOR_MASK)
/* CTRLDESCL49_0 Bit Fields */
#define DCU_CTRLDESCL49_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL49_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL49_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_0_WIDTH_SHIFT))&DCU_CTRLDESCL49_0_WIDTH_MASK)
#define DCU_CTRLDESCL49_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL49_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL49_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_0_HEIGHT_SHIFT))&DCU_CTRLDESCL49_0_HEIGHT_MASK)
/* CTRLDESCL49_1 Bit Fields */
#define DCU_CTRLDESCL49_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL49_1_POSX_SHIFT             0
#define DCU_CTRLDESCL49_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_1_POSX_SHIFT))&DCU_CTRLDESCL49_1_POSX_MASK)
#define DCU_CTRLDESCL49_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL49_1_POSY_SHIFT             16
#define DCU_CTRLDESCL49_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_1_POSY_SHIFT))&DCU_CTRLDESCL49_1_POSY_MASK)
/* CTRLDESCL49_2 Bit Fields */
#define DCU_CTRLDESCL49_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL49_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL49_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_2_ADDR_SHIFT))&DCU_CTRLDESCL49_2_ADDR_MASK)
/* CTRLDESCL49_3 Bit Fields */
#define DCU_CTRLDESCL49_3_AB_MASK                0x3u
#define DCU_CTRLDESCL49_3_AB_SHIFT               0
#define DCU_CTRLDESCL49_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_3_AB_SHIFT))&DCU_CTRLDESCL49_3_AB_MASK)
#define DCU_CTRLDESCL49_3_BB_MASK                0x4u
#define DCU_CTRLDESCL49_3_BB_SHIFT               2
#define DCU_CTRLDESCL49_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL49_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL49_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_3_LUOFFS_SHIFT))&DCU_CTRLDESCL49_3_LUOFFS_MASK)
#define DCU_CTRLDESCL49_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL49_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL49_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL49_3_BPP_SHIFT              16
#define DCU_CTRLDESCL49_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_3_BPP_SHIFT))&DCU_CTRLDESCL49_3_BPP_MASK)
#define DCU_CTRLDESCL49_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL49_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL49_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_3_TRANS_SHIFT))&DCU_CTRLDESCL49_3_TRANS_MASK)
#define DCU_CTRLDESCL49_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL49_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL49_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL49_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL49_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL49_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL49_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL49_3_EN_SHIFT               31
/* CTRLDESCL49_4 Bit Fields */
#define DCU_CTRLDESCL49_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL49_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL49_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL49_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL49_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL49_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL49_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL49_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL49_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL49_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL49_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL49_4_CKMAX_R_MASK)
/* CTRLDESCL49_5 Bit Fields */
#define DCU_CTRLDESCL49_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL49_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL49_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL49_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL49_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL49_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL49_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL49_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL49_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL49_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL49_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL49_5_CKMIN_R_MASK)
/* CTRLDESCL49_6 Bit Fields */
#define DCU_CTRLDESCL49_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL49_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL49_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL49_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL49_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL49_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL49_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL49_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL49_7 Bit Fields */
#define DCU_CTRLDESCL49_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL49_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL49_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL49_7_FGn_FCOLOR_MASK)
/* CTRLDESCL49_8 Bit Fields */
#define DCU_CTRLDESCL49_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL49_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL49_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL49_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL49_8_FGn_BCOLOR_MASK)
/* CTRLDESCL50_0 Bit Fields */
#define DCU_CTRLDESCL50_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL50_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL50_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_0_WIDTH_SHIFT))&DCU_CTRLDESCL50_0_WIDTH_MASK)
#define DCU_CTRLDESCL50_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL50_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL50_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_0_HEIGHT_SHIFT))&DCU_CTRLDESCL50_0_HEIGHT_MASK)
/* CTRLDESCL50_1 Bit Fields */
#define DCU_CTRLDESCL50_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL50_1_POSX_SHIFT             0
#define DCU_CTRLDESCL50_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_1_POSX_SHIFT))&DCU_CTRLDESCL50_1_POSX_MASK)
#define DCU_CTRLDESCL50_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL50_1_POSY_SHIFT             16
#define DCU_CTRLDESCL50_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_1_POSY_SHIFT))&DCU_CTRLDESCL50_1_POSY_MASK)
/* CTRLDESCL50_2 Bit Fields */
#define DCU_CTRLDESCL50_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL50_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL50_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_2_ADDR_SHIFT))&DCU_CTRLDESCL50_2_ADDR_MASK)
/* CTRLDESCL50_3 Bit Fields */
#define DCU_CTRLDESCL50_3_AB_MASK                0x3u
#define DCU_CTRLDESCL50_3_AB_SHIFT               0
#define DCU_CTRLDESCL50_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_3_AB_SHIFT))&DCU_CTRLDESCL50_3_AB_MASK)
#define DCU_CTRLDESCL50_3_BB_MASK                0x4u
#define DCU_CTRLDESCL50_3_BB_SHIFT               2
#define DCU_CTRLDESCL50_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL50_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL50_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_3_LUOFFS_SHIFT))&DCU_CTRLDESCL50_3_LUOFFS_MASK)
#define DCU_CTRLDESCL50_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL50_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL50_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL50_3_BPP_SHIFT              16
#define DCU_CTRLDESCL50_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_3_BPP_SHIFT))&DCU_CTRLDESCL50_3_BPP_MASK)
#define DCU_CTRLDESCL50_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL50_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL50_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_3_TRANS_SHIFT))&DCU_CTRLDESCL50_3_TRANS_MASK)
#define DCU_CTRLDESCL50_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL50_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL50_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL50_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL50_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL50_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL50_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL50_3_EN_SHIFT               31
/* CTRLDESCL50_4 Bit Fields */
#define DCU_CTRLDESCL50_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL50_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL50_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL50_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL50_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL50_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL50_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL50_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL50_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL50_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL50_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL50_4_CKMAX_R_MASK)
/* CTRLDESCL50_5 Bit Fields */
#define DCU_CTRLDESCL50_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL50_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL50_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL50_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL50_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL50_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL50_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL50_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL50_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL50_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL50_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL50_5_CKMIN_R_MASK)
/* CTRLDESCL50_6 Bit Fields */
#define DCU_CTRLDESCL50_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL50_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL50_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL50_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL50_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL50_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL50_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL50_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL50_7 Bit Fields */
#define DCU_CTRLDESCL50_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL50_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL50_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL50_7_FGn_FCOLOR_MASK)
/* CTRLDESCL50_8 Bit Fields */
#define DCU_CTRLDESCL50_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL50_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL50_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL50_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL50_8_FGn_BCOLOR_MASK)
/* CTRLDESCL51_0 Bit Fields */
#define DCU_CTRLDESCL51_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL51_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL51_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_0_WIDTH_SHIFT))&DCU_CTRLDESCL51_0_WIDTH_MASK)
#define DCU_CTRLDESCL51_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL51_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL51_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_0_HEIGHT_SHIFT))&DCU_CTRLDESCL51_0_HEIGHT_MASK)
/* CTRLDESCL51_1 Bit Fields */
#define DCU_CTRLDESCL51_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL51_1_POSX_SHIFT             0
#define DCU_CTRLDESCL51_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_1_POSX_SHIFT))&DCU_CTRLDESCL51_1_POSX_MASK)
#define DCU_CTRLDESCL51_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL51_1_POSY_SHIFT             16
#define DCU_CTRLDESCL51_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_1_POSY_SHIFT))&DCU_CTRLDESCL51_1_POSY_MASK)
/* CTRLDESCL51_2 Bit Fields */
#define DCU_CTRLDESCL51_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL51_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL51_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_2_ADDR_SHIFT))&DCU_CTRLDESCL51_2_ADDR_MASK)
/* CTRLDESCL51_3 Bit Fields */
#define DCU_CTRLDESCL51_3_AB_MASK                0x3u
#define DCU_CTRLDESCL51_3_AB_SHIFT               0
#define DCU_CTRLDESCL51_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_3_AB_SHIFT))&DCU_CTRLDESCL51_3_AB_MASK)
#define DCU_CTRLDESCL51_3_BB_MASK                0x4u
#define DCU_CTRLDESCL51_3_BB_SHIFT               2
#define DCU_CTRLDESCL51_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL51_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL51_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_3_LUOFFS_SHIFT))&DCU_CTRLDESCL51_3_LUOFFS_MASK)
#define DCU_CTRLDESCL51_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL51_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL51_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL51_3_BPP_SHIFT              16
#define DCU_CTRLDESCL51_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_3_BPP_SHIFT))&DCU_CTRLDESCL51_3_BPP_MASK)
#define DCU_CTRLDESCL51_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL51_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL51_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_3_TRANS_SHIFT))&DCU_CTRLDESCL51_3_TRANS_MASK)
#define DCU_CTRLDESCL51_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL51_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL51_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL51_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL51_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL51_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL51_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL51_3_EN_SHIFT               31
/* CTRLDESCL51_4 Bit Fields */
#define DCU_CTRLDESCL51_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL51_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL51_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL51_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL51_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL51_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL51_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL51_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL51_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL51_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL51_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL51_4_CKMAX_R_MASK)
/* CTRLDESCL51_5 Bit Fields */
#define DCU_CTRLDESCL51_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL51_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL51_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL51_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL51_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL51_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL51_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL51_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL51_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL51_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL51_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL51_5_CKMIN_R_MASK)
/* CTRLDESCL51_6 Bit Fields */
#define DCU_CTRLDESCL51_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL51_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL51_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL51_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL51_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL51_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL51_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL51_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL51_7 Bit Fields */
#define DCU_CTRLDESCL51_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL51_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL51_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL51_7_FGn_FCOLOR_MASK)
/* CTRLDESCL51_8 Bit Fields */
#define DCU_CTRLDESCL51_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL51_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL51_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL51_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL51_8_FGn_BCOLOR_MASK)
/* CTRLDESCL52_0 Bit Fields */
#define DCU_CTRLDESCL52_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL52_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL52_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_0_WIDTH_SHIFT))&DCU_CTRLDESCL52_0_WIDTH_MASK)
#define DCU_CTRLDESCL52_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL52_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL52_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_0_HEIGHT_SHIFT))&DCU_CTRLDESCL52_0_HEIGHT_MASK)
/* CTRLDESCL52_1 Bit Fields */
#define DCU_CTRLDESCL52_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL52_1_POSX_SHIFT             0
#define DCU_CTRLDESCL52_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_1_POSX_SHIFT))&DCU_CTRLDESCL52_1_POSX_MASK)
#define DCU_CTRLDESCL52_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL52_1_POSY_SHIFT             16
#define DCU_CTRLDESCL52_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_1_POSY_SHIFT))&DCU_CTRLDESCL52_1_POSY_MASK)
/* CTRLDESCL52_2 Bit Fields */
#define DCU_CTRLDESCL52_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL52_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL52_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_2_ADDR_SHIFT))&DCU_CTRLDESCL52_2_ADDR_MASK)
/* CTRLDESCL52_3 Bit Fields */
#define DCU_CTRLDESCL52_3_AB_MASK                0x3u
#define DCU_CTRLDESCL52_3_AB_SHIFT               0
#define DCU_CTRLDESCL52_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_3_AB_SHIFT))&DCU_CTRLDESCL52_3_AB_MASK)
#define DCU_CTRLDESCL52_3_BB_MASK                0x4u
#define DCU_CTRLDESCL52_3_BB_SHIFT               2
#define DCU_CTRLDESCL52_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL52_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL52_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_3_LUOFFS_SHIFT))&DCU_CTRLDESCL52_3_LUOFFS_MASK)
#define DCU_CTRLDESCL52_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL52_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL52_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL52_3_BPP_SHIFT              16
#define DCU_CTRLDESCL52_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_3_BPP_SHIFT))&DCU_CTRLDESCL52_3_BPP_MASK)
#define DCU_CTRLDESCL52_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL52_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL52_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_3_TRANS_SHIFT))&DCU_CTRLDESCL52_3_TRANS_MASK)
#define DCU_CTRLDESCL52_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL52_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL52_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL52_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL52_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL52_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL52_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL52_3_EN_SHIFT               31
/* CTRLDESCL52_4 Bit Fields */
#define DCU_CTRLDESCL52_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL52_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL52_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL52_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL52_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL52_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL52_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL52_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL52_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL52_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL52_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL52_4_CKMAX_R_MASK)
/* CTRLDESCL52_5 Bit Fields */
#define DCU_CTRLDESCL52_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL52_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL52_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL52_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL52_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL52_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL52_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL52_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL52_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL52_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL52_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL52_5_CKMIN_R_MASK)
/* CTRLDESCL52_6 Bit Fields */
#define DCU_CTRLDESCL52_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL52_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL52_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL52_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL52_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL52_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL52_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL52_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL52_7 Bit Fields */
#define DCU_CTRLDESCL52_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL52_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL52_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL52_7_FGn_FCOLOR_MASK)
/* CTRLDESCL52_8 Bit Fields */
#define DCU_CTRLDESCL52_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL52_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL52_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL52_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL52_8_FGn_BCOLOR_MASK)
/* CTRLDESCL53_0 Bit Fields */
#define DCU_CTRLDESCL53_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL53_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL53_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_0_WIDTH_SHIFT))&DCU_CTRLDESCL53_0_WIDTH_MASK)
#define DCU_CTRLDESCL53_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL53_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL53_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_0_HEIGHT_SHIFT))&DCU_CTRLDESCL53_0_HEIGHT_MASK)
/* CTRLDESCL53_1 Bit Fields */
#define DCU_CTRLDESCL53_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL53_1_POSX_SHIFT             0
#define DCU_CTRLDESCL53_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_1_POSX_SHIFT))&DCU_CTRLDESCL53_1_POSX_MASK)
#define DCU_CTRLDESCL53_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL53_1_POSY_SHIFT             16
#define DCU_CTRLDESCL53_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_1_POSY_SHIFT))&DCU_CTRLDESCL53_1_POSY_MASK)
/* CTRLDESCL53_2 Bit Fields */
#define DCU_CTRLDESCL53_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL53_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL53_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_2_ADDR_SHIFT))&DCU_CTRLDESCL53_2_ADDR_MASK)
/* CTRLDESCL53_3 Bit Fields */
#define DCU_CTRLDESCL53_3_AB_MASK                0x3u
#define DCU_CTRLDESCL53_3_AB_SHIFT               0
#define DCU_CTRLDESCL53_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_3_AB_SHIFT))&DCU_CTRLDESCL53_3_AB_MASK)
#define DCU_CTRLDESCL53_3_BB_MASK                0x4u
#define DCU_CTRLDESCL53_3_BB_SHIFT               2
#define DCU_CTRLDESCL53_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL53_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL53_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_3_LUOFFS_SHIFT))&DCU_CTRLDESCL53_3_LUOFFS_MASK)
#define DCU_CTRLDESCL53_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL53_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL53_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL53_3_BPP_SHIFT              16
#define DCU_CTRLDESCL53_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_3_BPP_SHIFT))&DCU_CTRLDESCL53_3_BPP_MASK)
#define DCU_CTRLDESCL53_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL53_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL53_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_3_TRANS_SHIFT))&DCU_CTRLDESCL53_3_TRANS_MASK)
#define DCU_CTRLDESCL53_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL53_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL53_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL53_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL53_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL53_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL53_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL53_3_EN_SHIFT               31
/* CTRLDESCL53_4 Bit Fields */
#define DCU_CTRLDESCL53_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL53_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL53_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL53_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL53_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL53_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL53_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL53_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL53_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL53_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL53_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL53_4_CKMAX_R_MASK)
/* CTRLDESCL53_5 Bit Fields */
#define DCU_CTRLDESCL53_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL53_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL53_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL53_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL53_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL53_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL53_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL53_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL53_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL53_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL53_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL53_5_CKMIN_R_MASK)
/* CTRLDESCL53_6 Bit Fields */
#define DCU_CTRLDESCL53_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL53_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL53_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL53_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL53_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL53_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL53_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL53_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL53_7 Bit Fields */
#define DCU_CTRLDESCL53_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL53_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL53_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL53_7_FGn_FCOLOR_MASK)
/* CTRLDESCL53_8 Bit Fields */
#define DCU_CTRLDESCL53_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL53_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL53_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL53_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL53_8_FGn_BCOLOR_MASK)
/* CTRLDESCL54_0 Bit Fields */
#define DCU_CTRLDESCL54_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL54_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL54_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_0_WIDTH_SHIFT))&DCU_CTRLDESCL54_0_WIDTH_MASK)
#define DCU_CTRLDESCL54_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL54_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL54_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_0_HEIGHT_SHIFT))&DCU_CTRLDESCL54_0_HEIGHT_MASK)
/* CTRLDESCL54_1 Bit Fields */
#define DCU_CTRLDESCL54_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL54_1_POSX_SHIFT             0
#define DCU_CTRLDESCL54_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_1_POSX_SHIFT))&DCU_CTRLDESCL54_1_POSX_MASK)
#define DCU_CTRLDESCL54_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL54_1_POSY_SHIFT             16
#define DCU_CTRLDESCL54_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_1_POSY_SHIFT))&DCU_CTRLDESCL54_1_POSY_MASK)
/* CTRLDESCL54_2 Bit Fields */
#define DCU_CTRLDESCL54_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL54_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL54_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_2_ADDR_SHIFT))&DCU_CTRLDESCL54_2_ADDR_MASK)
/* CTRLDESCL54_3 Bit Fields */
#define DCU_CTRLDESCL54_3_AB_MASK                0x3u
#define DCU_CTRLDESCL54_3_AB_SHIFT               0
#define DCU_CTRLDESCL54_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_3_AB_SHIFT))&DCU_CTRLDESCL54_3_AB_MASK)
#define DCU_CTRLDESCL54_3_BB_MASK                0x4u
#define DCU_CTRLDESCL54_3_BB_SHIFT               2
#define DCU_CTRLDESCL54_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL54_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL54_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_3_LUOFFS_SHIFT))&DCU_CTRLDESCL54_3_LUOFFS_MASK)
#define DCU_CTRLDESCL54_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL54_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL54_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL54_3_BPP_SHIFT              16
#define DCU_CTRLDESCL54_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_3_BPP_SHIFT))&DCU_CTRLDESCL54_3_BPP_MASK)
#define DCU_CTRLDESCL54_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL54_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL54_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_3_TRANS_SHIFT))&DCU_CTRLDESCL54_3_TRANS_MASK)
#define DCU_CTRLDESCL54_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL54_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL54_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL54_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL54_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL54_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL54_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL54_3_EN_SHIFT               31
/* CTRLDESCL54_4 Bit Fields */
#define DCU_CTRLDESCL54_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL54_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL54_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL54_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL54_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL54_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL54_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL54_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL54_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL54_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL54_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL54_4_CKMAX_R_MASK)
/* CTRLDESCL54_5 Bit Fields */
#define DCU_CTRLDESCL54_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL54_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL54_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL54_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL54_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL54_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL54_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL54_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL54_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL54_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL54_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL54_5_CKMIN_R_MASK)
/* CTRLDESCL54_6 Bit Fields */
#define DCU_CTRLDESCL54_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL54_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL54_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL54_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL54_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL54_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL54_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL54_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL54_7 Bit Fields */
#define DCU_CTRLDESCL54_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL54_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL54_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL54_7_FGn_FCOLOR_MASK)
/* CTRLDESCL54_8 Bit Fields */
#define DCU_CTRLDESCL54_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL54_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL54_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL54_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL54_8_FGn_BCOLOR_MASK)
/* CTRLDESCL55_0 Bit Fields */
#define DCU_CTRLDESCL55_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL55_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL55_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_0_WIDTH_SHIFT))&DCU_CTRLDESCL55_0_WIDTH_MASK)
#define DCU_CTRLDESCL55_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL55_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL55_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_0_HEIGHT_SHIFT))&DCU_CTRLDESCL55_0_HEIGHT_MASK)
/* CTRLDESCL55_1 Bit Fields */
#define DCU_CTRLDESCL55_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL55_1_POSX_SHIFT             0
#define DCU_CTRLDESCL55_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_1_POSX_SHIFT))&DCU_CTRLDESCL55_1_POSX_MASK)
#define DCU_CTRLDESCL55_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL55_1_POSY_SHIFT             16
#define DCU_CTRLDESCL55_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_1_POSY_SHIFT))&DCU_CTRLDESCL55_1_POSY_MASK)
/* CTRLDESCL55_2 Bit Fields */
#define DCU_CTRLDESCL55_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL55_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL55_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_2_ADDR_SHIFT))&DCU_CTRLDESCL55_2_ADDR_MASK)
/* CTRLDESCL55_3 Bit Fields */
#define DCU_CTRLDESCL55_3_AB_MASK                0x3u
#define DCU_CTRLDESCL55_3_AB_SHIFT               0
#define DCU_CTRLDESCL55_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_3_AB_SHIFT))&DCU_CTRLDESCL55_3_AB_MASK)
#define DCU_CTRLDESCL55_3_BB_MASK                0x4u
#define DCU_CTRLDESCL55_3_BB_SHIFT               2
#define DCU_CTRLDESCL55_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL55_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL55_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_3_LUOFFS_SHIFT))&DCU_CTRLDESCL55_3_LUOFFS_MASK)
#define DCU_CTRLDESCL55_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL55_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL55_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL55_3_BPP_SHIFT              16
#define DCU_CTRLDESCL55_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_3_BPP_SHIFT))&DCU_CTRLDESCL55_3_BPP_MASK)
#define DCU_CTRLDESCL55_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL55_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL55_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_3_TRANS_SHIFT))&DCU_CTRLDESCL55_3_TRANS_MASK)
#define DCU_CTRLDESCL55_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL55_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL55_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL55_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL55_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL55_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL55_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL55_3_EN_SHIFT               31
/* CTRLDESCL55_4 Bit Fields */
#define DCU_CTRLDESCL55_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL55_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL55_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL55_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL55_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL55_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL55_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL55_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL55_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL55_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL55_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL55_4_CKMAX_R_MASK)
/* CTRLDESCL55_5 Bit Fields */
#define DCU_CTRLDESCL55_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL55_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL55_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL55_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL55_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL55_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL55_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL55_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL55_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL55_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL55_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL55_5_CKMIN_R_MASK)
/* CTRLDESCL55_6 Bit Fields */
#define DCU_CTRLDESCL55_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL55_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL55_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL55_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL55_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL55_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL55_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL55_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL55_7 Bit Fields */
#define DCU_CTRLDESCL55_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL55_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL55_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL55_7_FGn_FCOLOR_MASK)
/* CTRLDESCL55_8 Bit Fields */
#define DCU_CTRLDESCL55_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL55_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL55_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL55_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL55_8_FGn_BCOLOR_MASK)
/* CTRLDESCL56_0 Bit Fields */
#define DCU_CTRLDESCL56_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL56_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL56_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_0_WIDTH_SHIFT))&DCU_CTRLDESCL56_0_WIDTH_MASK)
#define DCU_CTRLDESCL56_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL56_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL56_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_0_HEIGHT_SHIFT))&DCU_CTRLDESCL56_0_HEIGHT_MASK)
/* CTRLDESCL56_1 Bit Fields */
#define DCU_CTRLDESCL56_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL56_1_POSX_SHIFT             0
#define DCU_CTRLDESCL56_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_1_POSX_SHIFT))&DCU_CTRLDESCL56_1_POSX_MASK)
#define DCU_CTRLDESCL56_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL56_1_POSY_SHIFT             16
#define DCU_CTRLDESCL56_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_1_POSY_SHIFT))&DCU_CTRLDESCL56_1_POSY_MASK)
/* CTRLDESCL56_2 Bit Fields */
#define DCU_CTRLDESCL56_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL56_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL56_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_2_ADDR_SHIFT))&DCU_CTRLDESCL56_2_ADDR_MASK)
/* CTRLDESCL56_3 Bit Fields */
#define DCU_CTRLDESCL56_3_AB_MASK                0x3u
#define DCU_CTRLDESCL56_3_AB_SHIFT               0
#define DCU_CTRLDESCL56_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_3_AB_SHIFT))&DCU_CTRLDESCL56_3_AB_MASK)
#define DCU_CTRLDESCL56_3_BB_MASK                0x4u
#define DCU_CTRLDESCL56_3_BB_SHIFT               2
#define DCU_CTRLDESCL56_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL56_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL56_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_3_LUOFFS_SHIFT))&DCU_CTRLDESCL56_3_LUOFFS_MASK)
#define DCU_CTRLDESCL56_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL56_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL56_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL56_3_BPP_SHIFT              16
#define DCU_CTRLDESCL56_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_3_BPP_SHIFT))&DCU_CTRLDESCL56_3_BPP_MASK)
#define DCU_CTRLDESCL56_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL56_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL56_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_3_TRANS_SHIFT))&DCU_CTRLDESCL56_3_TRANS_MASK)
#define DCU_CTRLDESCL56_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL56_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL56_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL56_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL56_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL56_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL56_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL56_3_EN_SHIFT               31
/* CTRLDESCL56_4 Bit Fields */
#define DCU_CTRLDESCL56_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL56_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL56_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL56_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL56_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL56_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL56_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL56_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL56_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL56_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL56_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL56_4_CKMAX_R_MASK)
/* CTRLDESCL56_5 Bit Fields */
#define DCU_CTRLDESCL56_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL56_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL56_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL56_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL56_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL56_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL56_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL56_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL56_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL56_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL56_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL56_5_CKMIN_R_MASK)
/* CTRLDESCL56_6 Bit Fields */
#define DCU_CTRLDESCL56_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL56_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL56_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL56_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL56_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL56_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL56_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL56_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL56_7 Bit Fields */
#define DCU_CTRLDESCL56_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL56_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL56_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL56_7_FGn_FCOLOR_MASK)
/* CTRLDESCL56_8 Bit Fields */
#define DCU_CTRLDESCL56_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL56_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL56_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL56_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL56_8_FGn_BCOLOR_MASK)
/* CTRLDESCL57_0 Bit Fields */
#define DCU_CTRLDESCL57_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL57_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL57_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_0_WIDTH_SHIFT))&DCU_CTRLDESCL57_0_WIDTH_MASK)
#define DCU_CTRLDESCL57_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL57_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL57_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_0_HEIGHT_SHIFT))&DCU_CTRLDESCL57_0_HEIGHT_MASK)
/* CTRLDESCL57_1 Bit Fields */
#define DCU_CTRLDESCL57_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL57_1_POSX_SHIFT             0
#define DCU_CTRLDESCL57_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_1_POSX_SHIFT))&DCU_CTRLDESCL57_1_POSX_MASK)
#define DCU_CTRLDESCL57_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL57_1_POSY_SHIFT             16
#define DCU_CTRLDESCL57_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_1_POSY_SHIFT))&DCU_CTRLDESCL57_1_POSY_MASK)
/* CTRLDESCL57_2 Bit Fields */
#define DCU_CTRLDESCL57_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL57_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL57_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_2_ADDR_SHIFT))&DCU_CTRLDESCL57_2_ADDR_MASK)
/* CTRLDESCL57_3 Bit Fields */
#define DCU_CTRLDESCL57_3_AB_MASK                0x3u
#define DCU_CTRLDESCL57_3_AB_SHIFT               0
#define DCU_CTRLDESCL57_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_3_AB_SHIFT))&DCU_CTRLDESCL57_3_AB_MASK)
#define DCU_CTRLDESCL57_3_BB_MASK                0x4u
#define DCU_CTRLDESCL57_3_BB_SHIFT               2
#define DCU_CTRLDESCL57_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL57_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL57_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_3_LUOFFS_SHIFT))&DCU_CTRLDESCL57_3_LUOFFS_MASK)
#define DCU_CTRLDESCL57_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL57_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL57_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL57_3_BPP_SHIFT              16
#define DCU_CTRLDESCL57_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_3_BPP_SHIFT))&DCU_CTRLDESCL57_3_BPP_MASK)
#define DCU_CTRLDESCL57_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL57_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL57_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_3_TRANS_SHIFT))&DCU_CTRLDESCL57_3_TRANS_MASK)
#define DCU_CTRLDESCL57_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL57_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL57_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL57_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL57_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL57_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL57_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL57_3_EN_SHIFT               31
/* CTRLDESCL57_4 Bit Fields */
#define DCU_CTRLDESCL57_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL57_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL57_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL57_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL57_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL57_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL57_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL57_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL57_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL57_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL57_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL57_4_CKMAX_R_MASK)
/* CTRLDESCL57_5 Bit Fields */
#define DCU_CTRLDESCL57_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL57_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL57_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL57_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL57_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL57_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL57_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL57_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL57_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL57_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL57_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL57_5_CKMIN_R_MASK)
/* CTRLDESCL57_6 Bit Fields */
#define DCU_CTRLDESCL57_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL57_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL57_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL57_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL57_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL57_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL57_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL57_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL57_7 Bit Fields */
#define DCU_CTRLDESCL57_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL57_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL57_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL57_7_FGn_FCOLOR_MASK)
/* CTRLDESCL57_8 Bit Fields */
#define DCU_CTRLDESCL57_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL57_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL57_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL57_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL57_8_FGn_BCOLOR_MASK)
/* CTRLDESCL58_0 Bit Fields */
#define DCU_CTRLDESCL58_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL58_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL58_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_0_WIDTH_SHIFT))&DCU_CTRLDESCL58_0_WIDTH_MASK)
#define DCU_CTRLDESCL58_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL58_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL58_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_0_HEIGHT_SHIFT))&DCU_CTRLDESCL58_0_HEIGHT_MASK)
/* CTRLDESCL58_1 Bit Fields */
#define DCU_CTRLDESCL58_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL58_1_POSX_SHIFT             0
#define DCU_CTRLDESCL58_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_1_POSX_SHIFT))&DCU_CTRLDESCL58_1_POSX_MASK)
#define DCU_CTRLDESCL58_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL58_1_POSY_SHIFT             16
#define DCU_CTRLDESCL58_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_1_POSY_SHIFT))&DCU_CTRLDESCL58_1_POSY_MASK)
/* CTRLDESCL58_2 Bit Fields */
#define DCU_CTRLDESCL58_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL58_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL58_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_2_ADDR_SHIFT))&DCU_CTRLDESCL58_2_ADDR_MASK)
/* CTRLDESCL58_3 Bit Fields */
#define DCU_CTRLDESCL58_3_AB_MASK                0x3u
#define DCU_CTRLDESCL58_3_AB_SHIFT               0
#define DCU_CTRLDESCL58_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_3_AB_SHIFT))&DCU_CTRLDESCL58_3_AB_MASK)
#define DCU_CTRLDESCL58_3_BB_MASK                0x4u
#define DCU_CTRLDESCL58_3_BB_SHIFT               2
#define DCU_CTRLDESCL58_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL58_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL58_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_3_LUOFFS_SHIFT))&DCU_CTRLDESCL58_3_LUOFFS_MASK)
#define DCU_CTRLDESCL58_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL58_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL58_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL58_3_BPP_SHIFT              16
#define DCU_CTRLDESCL58_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_3_BPP_SHIFT))&DCU_CTRLDESCL58_3_BPP_MASK)
#define DCU_CTRLDESCL58_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL58_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL58_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_3_TRANS_SHIFT))&DCU_CTRLDESCL58_3_TRANS_MASK)
#define DCU_CTRLDESCL58_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL58_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL58_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL58_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL58_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL58_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL58_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL58_3_EN_SHIFT               31
/* CTRLDESCL58_4 Bit Fields */
#define DCU_CTRLDESCL58_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL58_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL58_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL58_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL58_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL58_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL58_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL58_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL58_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL58_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL58_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL58_4_CKMAX_R_MASK)
/* CTRLDESCL58_5 Bit Fields */
#define DCU_CTRLDESCL58_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL58_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL58_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL58_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL58_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL58_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL58_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL58_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL58_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL58_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL58_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL58_5_CKMIN_R_MASK)
/* CTRLDESCL58_6 Bit Fields */
#define DCU_CTRLDESCL58_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL58_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL58_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL58_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL58_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL58_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL58_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL58_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL58_7 Bit Fields */
#define DCU_CTRLDESCL58_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL58_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL58_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL58_7_FGn_FCOLOR_MASK)
/* CTRLDESCL58_8 Bit Fields */
#define DCU_CTRLDESCL58_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL58_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL58_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL58_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL58_8_FGn_BCOLOR_MASK)
/* CTRLDESCL59_0 Bit Fields */
#define DCU_CTRLDESCL59_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL59_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL59_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_0_WIDTH_SHIFT))&DCU_CTRLDESCL59_0_WIDTH_MASK)
#define DCU_CTRLDESCL59_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL59_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL59_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_0_HEIGHT_SHIFT))&DCU_CTRLDESCL59_0_HEIGHT_MASK)
/* CTRLDESCL59_1 Bit Fields */
#define DCU_CTRLDESCL59_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL59_1_POSX_SHIFT             0
#define DCU_CTRLDESCL59_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_1_POSX_SHIFT))&DCU_CTRLDESCL59_1_POSX_MASK)
#define DCU_CTRLDESCL59_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL59_1_POSY_SHIFT             16
#define DCU_CTRLDESCL59_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_1_POSY_SHIFT))&DCU_CTRLDESCL59_1_POSY_MASK)
/* CTRLDESCL59_2 Bit Fields */
#define DCU_CTRLDESCL59_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL59_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL59_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_2_ADDR_SHIFT))&DCU_CTRLDESCL59_2_ADDR_MASK)
/* CTRLDESCL59_3 Bit Fields */
#define DCU_CTRLDESCL59_3_AB_MASK                0x3u
#define DCU_CTRLDESCL59_3_AB_SHIFT               0
#define DCU_CTRLDESCL59_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_3_AB_SHIFT))&DCU_CTRLDESCL59_3_AB_MASK)
#define DCU_CTRLDESCL59_3_BB_MASK                0x4u
#define DCU_CTRLDESCL59_3_BB_SHIFT               2
#define DCU_CTRLDESCL59_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL59_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL59_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_3_LUOFFS_SHIFT))&DCU_CTRLDESCL59_3_LUOFFS_MASK)
#define DCU_CTRLDESCL59_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL59_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL59_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL59_3_BPP_SHIFT              16
#define DCU_CTRLDESCL59_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_3_BPP_SHIFT))&DCU_CTRLDESCL59_3_BPP_MASK)
#define DCU_CTRLDESCL59_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL59_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL59_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_3_TRANS_SHIFT))&DCU_CTRLDESCL59_3_TRANS_MASK)
#define DCU_CTRLDESCL59_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL59_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL59_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL59_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL59_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL59_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL59_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL59_3_EN_SHIFT               31
/* CTRLDESCL59_4 Bit Fields */
#define DCU_CTRLDESCL59_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL59_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL59_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL59_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL59_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL59_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL59_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL59_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL59_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL59_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL59_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL59_4_CKMAX_R_MASK)
/* CTRLDESCL59_5 Bit Fields */
#define DCU_CTRLDESCL59_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL59_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL59_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL59_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL59_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL59_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL59_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL59_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL59_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL59_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL59_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL59_5_CKMIN_R_MASK)
/* CTRLDESCL59_6 Bit Fields */
#define DCU_CTRLDESCL59_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL59_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL59_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL59_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL59_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL59_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL59_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL59_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL59_7 Bit Fields */
#define DCU_CTRLDESCL59_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL59_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL59_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL59_7_FGn_FCOLOR_MASK)
/* CTRLDESCL59_8 Bit Fields */
#define DCU_CTRLDESCL59_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL59_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL59_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL59_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL59_8_FGn_BCOLOR_MASK)
/* CTRLDESCL60_0 Bit Fields */
#define DCU_CTRLDESCL60_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL60_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL60_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_0_WIDTH_SHIFT))&DCU_CTRLDESCL60_0_WIDTH_MASK)
#define DCU_CTRLDESCL60_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL60_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL60_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_0_HEIGHT_SHIFT))&DCU_CTRLDESCL60_0_HEIGHT_MASK)
/* CTRLDESCL60_1 Bit Fields */
#define DCU_CTRLDESCL60_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL60_1_POSX_SHIFT             0
#define DCU_CTRLDESCL60_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_1_POSX_SHIFT))&DCU_CTRLDESCL60_1_POSX_MASK)
#define DCU_CTRLDESCL60_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL60_1_POSY_SHIFT             16
#define DCU_CTRLDESCL60_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_1_POSY_SHIFT))&DCU_CTRLDESCL60_1_POSY_MASK)
/* CTRLDESCL60_2 Bit Fields */
#define DCU_CTRLDESCL60_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL60_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL60_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_2_ADDR_SHIFT))&DCU_CTRLDESCL60_2_ADDR_MASK)
/* CTRLDESCL60_3 Bit Fields */
#define DCU_CTRLDESCL60_3_AB_MASK                0x3u
#define DCU_CTRLDESCL60_3_AB_SHIFT               0
#define DCU_CTRLDESCL60_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_3_AB_SHIFT))&DCU_CTRLDESCL60_3_AB_MASK)
#define DCU_CTRLDESCL60_3_BB_MASK                0x4u
#define DCU_CTRLDESCL60_3_BB_SHIFT               2
#define DCU_CTRLDESCL60_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL60_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL60_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_3_LUOFFS_SHIFT))&DCU_CTRLDESCL60_3_LUOFFS_MASK)
#define DCU_CTRLDESCL60_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL60_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL60_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL60_3_BPP_SHIFT              16
#define DCU_CTRLDESCL60_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_3_BPP_SHIFT))&DCU_CTRLDESCL60_3_BPP_MASK)
#define DCU_CTRLDESCL60_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL60_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL60_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_3_TRANS_SHIFT))&DCU_CTRLDESCL60_3_TRANS_MASK)
#define DCU_CTRLDESCL60_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL60_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL60_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL60_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL60_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL60_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL60_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL60_3_EN_SHIFT               31
/* CTRLDESCL60_4 Bit Fields */
#define DCU_CTRLDESCL60_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL60_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL60_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL60_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL60_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL60_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL60_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL60_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL60_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL60_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL60_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL60_4_CKMAX_R_MASK)
/* CTRLDESCL60_5 Bit Fields */
#define DCU_CTRLDESCL60_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL60_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL60_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL60_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL60_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL60_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL60_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL60_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL60_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL60_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL60_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL60_5_CKMIN_R_MASK)
/* CTRLDESCL60_6 Bit Fields */
#define DCU_CTRLDESCL60_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL60_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL60_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL60_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL60_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL60_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL60_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL60_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL60_7 Bit Fields */
#define DCU_CTRLDESCL60_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL60_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL60_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL60_7_FGn_FCOLOR_MASK)
/* CTRLDESCL60_8 Bit Fields */
#define DCU_CTRLDESCL60_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL60_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL60_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL60_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL60_8_FGn_BCOLOR_MASK)
/* CTRLDESCL61_0 Bit Fields */
#define DCU_CTRLDESCL61_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL61_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL61_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_0_WIDTH_SHIFT))&DCU_CTRLDESCL61_0_WIDTH_MASK)
#define DCU_CTRLDESCL61_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL61_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL61_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_0_HEIGHT_SHIFT))&DCU_CTRLDESCL61_0_HEIGHT_MASK)
/* CTRLDESCL61_1 Bit Fields */
#define DCU_CTRLDESCL61_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL61_1_POSX_SHIFT             0
#define DCU_CTRLDESCL61_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_1_POSX_SHIFT))&DCU_CTRLDESCL61_1_POSX_MASK)
#define DCU_CTRLDESCL61_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL61_1_POSY_SHIFT             16
#define DCU_CTRLDESCL61_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_1_POSY_SHIFT))&DCU_CTRLDESCL61_1_POSY_MASK)
/* CTRLDESCL61_2 Bit Fields */
#define DCU_CTRLDESCL61_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL61_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL61_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_2_ADDR_SHIFT))&DCU_CTRLDESCL61_2_ADDR_MASK)
/* CTRLDESCL61_3 Bit Fields */
#define DCU_CTRLDESCL61_3_AB_MASK                0x3u
#define DCU_CTRLDESCL61_3_AB_SHIFT               0
#define DCU_CTRLDESCL61_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_3_AB_SHIFT))&DCU_CTRLDESCL61_3_AB_MASK)
#define DCU_CTRLDESCL61_3_BB_MASK                0x4u
#define DCU_CTRLDESCL61_3_BB_SHIFT               2
#define DCU_CTRLDESCL61_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL61_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL61_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_3_LUOFFS_SHIFT))&DCU_CTRLDESCL61_3_LUOFFS_MASK)
#define DCU_CTRLDESCL61_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL61_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL61_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL61_3_BPP_SHIFT              16
#define DCU_CTRLDESCL61_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_3_BPP_SHIFT))&DCU_CTRLDESCL61_3_BPP_MASK)
#define DCU_CTRLDESCL61_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL61_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL61_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_3_TRANS_SHIFT))&DCU_CTRLDESCL61_3_TRANS_MASK)
#define DCU_CTRLDESCL61_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL61_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL61_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL61_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL61_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL61_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL61_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL61_3_EN_SHIFT               31
/* CTRLDESCL61_4 Bit Fields */
#define DCU_CTRLDESCL61_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL61_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL61_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL61_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL61_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL61_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL61_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL61_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL61_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL61_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL61_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL61_4_CKMAX_R_MASK)
/* CTRLDESCL61_5 Bit Fields */
#define DCU_CTRLDESCL61_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL61_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL61_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL61_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL61_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL61_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL61_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL61_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL61_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL61_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL61_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL61_5_CKMIN_R_MASK)
/* CTRLDESCL61_6 Bit Fields */
#define DCU_CTRLDESCL61_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL61_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL61_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL61_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL61_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL61_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL61_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL61_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL61_7 Bit Fields */
#define DCU_CTRLDESCL61_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL61_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL61_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL61_7_FGn_FCOLOR_MASK)
/* CTRLDESCL61_8 Bit Fields */
#define DCU_CTRLDESCL61_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL61_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL61_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL61_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL61_8_FGn_BCOLOR_MASK)
/* CTRLDESCL62_0 Bit Fields */
#define DCU_CTRLDESCL62_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL62_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL62_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_0_WIDTH_SHIFT))&DCU_CTRLDESCL62_0_WIDTH_MASK)
#define DCU_CTRLDESCL62_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL62_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL62_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_0_HEIGHT_SHIFT))&DCU_CTRLDESCL62_0_HEIGHT_MASK)
/* CTRLDESCL62_1 Bit Fields */
#define DCU_CTRLDESCL62_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL62_1_POSX_SHIFT             0
#define DCU_CTRLDESCL62_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_1_POSX_SHIFT))&DCU_CTRLDESCL62_1_POSX_MASK)
#define DCU_CTRLDESCL62_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL62_1_POSY_SHIFT             16
#define DCU_CTRLDESCL62_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_1_POSY_SHIFT))&DCU_CTRLDESCL62_1_POSY_MASK)
/* CTRLDESCL62_2 Bit Fields */
#define DCU_CTRLDESCL62_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL62_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL62_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_2_ADDR_SHIFT))&DCU_CTRLDESCL62_2_ADDR_MASK)
/* CTRLDESCL62_3 Bit Fields */
#define DCU_CTRLDESCL62_3_AB_MASK                0x3u
#define DCU_CTRLDESCL62_3_AB_SHIFT               0
#define DCU_CTRLDESCL62_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_3_AB_SHIFT))&DCU_CTRLDESCL62_3_AB_MASK)
#define DCU_CTRLDESCL62_3_BB_MASK                0x4u
#define DCU_CTRLDESCL62_3_BB_SHIFT               2
#define DCU_CTRLDESCL62_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL62_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL62_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_3_LUOFFS_SHIFT))&DCU_CTRLDESCL62_3_LUOFFS_MASK)
#define DCU_CTRLDESCL62_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL62_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL62_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL62_3_BPP_SHIFT              16
#define DCU_CTRLDESCL62_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_3_BPP_SHIFT))&DCU_CTRLDESCL62_3_BPP_MASK)
#define DCU_CTRLDESCL62_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL62_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL62_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_3_TRANS_SHIFT))&DCU_CTRLDESCL62_3_TRANS_MASK)
#define DCU_CTRLDESCL62_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL62_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL62_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL62_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL62_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL62_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL62_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL62_3_EN_SHIFT               31
/* CTRLDESCL62_4 Bit Fields */
#define DCU_CTRLDESCL62_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL62_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL62_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL62_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL62_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL62_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL62_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL62_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL62_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL62_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL62_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL62_4_CKMAX_R_MASK)
/* CTRLDESCL62_5 Bit Fields */
#define DCU_CTRLDESCL62_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL62_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL62_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL62_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL62_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL62_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL62_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL62_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL62_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL62_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL62_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL62_5_CKMIN_R_MASK)
/* CTRLDESCL62_6 Bit Fields */
#define DCU_CTRLDESCL62_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL62_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL62_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL62_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL62_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL62_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL62_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL62_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL62_7 Bit Fields */
#define DCU_CTRLDESCL62_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL62_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL62_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL62_7_FGn_FCOLOR_MASK)
/* CTRLDESCL62_8 Bit Fields */
#define DCU_CTRLDESCL62_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL62_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL62_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL62_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL62_8_FGn_BCOLOR_MASK)
/* CTRLDESCL63_0 Bit Fields */
#define DCU_CTRLDESCL63_0_WIDTH_MASK             0x7FFu
#define DCU_CTRLDESCL63_0_WIDTH_SHIFT            0
#define DCU_CTRLDESCL63_0_WIDTH(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_0_WIDTH_SHIFT))&DCU_CTRLDESCL63_0_WIDTH_MASK)
#define DCU_CTRLDESCL63_0_HEIGHT_MASK            0x7FF0000u
#define DCU_CTRLDESCL63_0_HEIGHT_SHIFT           16
#define DCU_CTRLDESCL63_0_HEIGHT(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_0_HEIGHT_SHIFT))&DCU_CTRLDESCL63_0_HEIGHT_MASK)
/* CTRLDESCL63_1 Bit Fields */
#define DCU_CTRLDESCL63_1_POSX_MASK              0xFFFu
#define DCU_CTRLDESCL63_1_POSX_SHIFT             0
#define DCU_CTRLDESCL63_1_POSX(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_1_POSX_SHIFT))&DCU_CTRLDESCL63_1_POSX_MASK)
#define DCU_CTRLDESCL63_1_POSY_MASK              0xFFF0000u
#define DCU_CTRLDESCL63_1_POSY_SHIFT             16
#define DCU_CTRLDESCL63_1_POSY(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_1_POSY_SHIFT))&DCU_CTRLDESCL63_1_POSY_MASK)
/* CTRLDESCL63_2 Bit Fields */
#define DCU_CTRLDESCL63_2_ADDR_MASK              0xFFFFFFFFu
#define DCU_CTRLDESCL63_2_ADDR_SHIFT             0
#define DCU_CTRLDESCL63_2_ADDR(x)                (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_2_ADDR_SHIFT))&DCU_CTRLDESCL63_2_ADDR_MASK)
/* CTRLDESCL63_3 Bit Fields */
#define DCU_CTRLDESCL63_3_AB_MASK                0x3u
#define DCU_CTRLDESCL63_3_AB_SHIFT               0
#define DCU_CTRLDESCL63_3_AB(x)                  (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_3_AB_SHIFT))&DCU_CTRLDESCL63_3_AB_MASK)
#define DCU_CTRLDESCL63_3_BB_MASK                0x4u
#define DCU_CTRLDESCL63_3_BB_SHIFT               2
#define DCU_CTRLDESCL63_3_LUOFFS_MASK            0x7FF0u
#define DCU_CTRLDESCL63_3_LUOFFS_SHIFT           4
#define DCU_CTRLDESCL63_3_LUOFFS(x)              (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_3_LUOFFS_SHIFT))&DCU_CTRLDESCL63_3_LUOFFS_MASK)
#define DCU_CTRLDESCL63_3_RLE_EN_MASK            0x8000u
#define DCU_CTRLDESCL63_3_RLE_EN_SHIFT           15
#define DCU_CTRLDESCL63_3_BPP_MASK               0xF0000u
#define DCU_CTRLDESCL63_3_BPP_SHIFT              16
#define DCU_CTRLDESCL63_3_BPP(x)                 (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_3_BPP_SHIFT))&DCU_CTRLDESCL63_3_BPP_MASK)
#define DCU_CTRLDESCL63_3_TRANS_MASK             0xFF00000u
#define DCU_CTRLDESCL63_3_TRANS_SHIFT            20
#define DCU_CTRLDESCL63_3_TRANS(x)               (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_3_TRANS_SHIFT))&DCU_CTRLDESCL63_3_TRANS_MASK)
#define DCU_CTRLDESCL63_3_SAFETY_EN_MASK         0x10000000u
#define DCU_CTRLDESCL63_3_SAFETY_EN_SHIFT        28
#define DCU_CTRLDESCL63_3_DATA_SEL_MASK          0x20000000u
#define DCU_CTRLDESCL63_3_DATA_SEL_SHIFT         29
#define DCU_CTRLDESCL63_3_TILE_EN_MASK           0x40000000u
#define DCU_CTRLDESCL63_3_TILE_EN_SHIFT          30
#define DCU_CTRLDESCL63_3_EN_MASK                0x80000000u
#define DCU_CTRLDESCL63_3_EN_SHIFT               31
/* CTRLDESCL63_4 Bit Fields */
#define DCU_CTRLDESCL63_4_CKMAX_B_MASK           0xFFu
#define DCU_CTRLDESCL63_4_CKMAX_B_SHIFT          0
#define DCU_CTRLDESCL63_4_CKMAX_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_4_CKMAX_B_SHIFT))&DCU_CTRLDESCL63_4_CKMAX_B_MASK)
#define DCU_CTRLDESCL63_4_CKMAX_G_MASK           0xFF00u
#define DCU_CTRLDESCL63_4_CKMAX_G_SHIFT          8
#define DCU_CTRLDESCL63_4_CKMAX_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_4_CKMAX_G_SHIFT))&DCU_CTRLDESCL63_4_CKMAX_G_MASK)
#define DCU_CTRLDESCL63_4_CKMAX_R_MASK           0xFF0000u
#define DCU_CTRLDESCL63_4_CKMAX_R_SHIFT          16
#define DCU_CTRLDESCL63_4_CKMAX_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_4_CKMAX_R_SHIFT))&DCU_CTRLDESCL63_4_CKMAX_R_MASK)
/* CTRLDESCL63_5 Bit Fields */
#define DCU_CTRLDESCL63_5_CKMIN_B_MASK           0xFFu
#define DCU_CTRLDESCL63_5_CKMIN_B_SHIFT          0
#define DCU_CTRLDESCL63_5_CKMIN_B(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_5_CKMIN_B_SHIFT))&DCU_CTRLDESCL63_5_CKMIN_B_MASK)
#define DCU_CTRLDESCL63_5_CKMIN_G_MASK           0xFF00u
#define DCU_CTRLDESCL63_5_CKMIN_G_SHIFT          8
#define DCU_CTRLDESCL63_5_CKMIN_G(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_5_CKMIN_G_SHIFT))&DCU_CTRLDESCL63_5_CKMIN_G_MASK)
#define DCU_CTRLDESCL63_5_CKMIN_R_MASK           0xFF0000u
#define DCU_CTRLDESCL63_5_CKMIN_R_SHIFT          16
#define DCU_CTRLDESCL63_5_CKMIN_R(x)             (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_5_CKMIN_R_SHIFT))&DCU_CTRLDESCL63_5_CKMIN_R_MASK)
/* CTRLDESCL63_6 Bit Fields */
#define DCU_CTRLDESCL63_6_TILE_HOR_SIZE_MASK     0x7Fu
#define DCU_CTRLDESCL63_6_TILE_HOR_SIZE_SHIFT    0
#define DCU_CTRLDESCL63_6_TILE_HOR_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_6_TILE_HOR_SIZE_SHIFT))&DCU_CTRLDESCL63_6_TILE_HOR_SIZE_MASK)
#define DCU_CTRLDESCL63_6_TILE_VER_SIZE_MASK     0x7FF0000u
#define DCU_CTRLDESCL63_6_TILE_VER_SIZE_SHIFT    16
#define DCU_CTRLDESCL63_6_TILE_VER_SIZE(x)       (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_6_TILE_VER_SIZE_SHIFT))&DCU_CTRLDESCL63_6_TILE_VER_SIZE_MASK)
/* CTRLDESCL63_7 Bit Fields */
#define DCU_CTRLDESCL63_7_FGn_FCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL63_7_FGn_FCOLOR_SHIFT       0
#define DCU_CTRLDESCL63_7_FGn_FCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_7_FGn_FCOLOR_SHIFT))&DCU_CTRLDESCL63_7_FGn_FCOLOR_MASK)
/* CTRLDESCL63_8 Bit Fields */
#define DCU_CTRLDESCL63_8_FGn_BCOLOR_MASK        0xFFFFFFu
#define DCU_CTRLDESCL63_8_FGn_BCOLOR_SHIFT       0
#define DCU_CTRLDESCL63_8_FGn_BCOLOR(x)          (((uint32_t)(((uint32_t)(x))<<DCU_CTRLDESCL63_8_FGn_BCOLOR_SHIFT))&DCU_CTRLDESCL63_8_FGn_BCOLOR_MASK)

/**
 * @}
 */ /* end of group DCU_Register_Masks */


/* DCU - Peripheral instance base addresses */
/** Peripheral DCU0 base address */
#define DCU0_BASE                                (0x40058000u)
/** Peripheral DCU0 base pointer */
#define DCU0                                     ((DCU_Type *)DCU0_BASE)
/** Peripheral DCU1 base address */
#define DCU1_BASE                                (0x400D8000u)
/** Peripheral DCU1 base pointer */
#define DCU1                                     ((DCU_Type *)DCU1_BASE)
/** Array initializer of DCU peripheral base pointers */
#define DCU_BASES                                { DCU0, DCU1 }

/**
 * @}
 */ /* end of group DCU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DDRMC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DDRMC_Peripheral_Access_Layer DDRMC Peripheral Access Layer
 * @{
 */

/** DDRMC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR00;                              /**< Control Register 0, offset: 0x0 */
  __I  uint32_t CR01;                              /**< Control Register 1, offset: 0x4 */
  __IO uint32_t CR02;                              /**< Control Register 2, offset: 0x8 */
  __IO uint32_t CR03;                              /**< Control Register 3, offset: 0xC */
  __IO uint32_t CR04;                              /**< Control Register 4, offset: 0x10 */
  __IO uint32_t CR05;                              /**< Control Register 5, offset: 0x14 */
  __I  uint32_t CR06;                              /**< Control Register 6, offset: 0x18 */
  __I  uint32_t CR07;                              /**< Control Register 7, offset: 0x1C */
  __I  uint32_t CR08;                              /**< Control Register 8, offset: 0x20 */
  __IO uint32_t CR09;                              /**< Control Register 9, offset: 0x24 */
  __IO uint32_t CR10;                              /**< Control Register 10, offset: 0x28 */
  __IO uint32_t CR11;                              /**< Control Register 11, offset: 0x2C */
  __IO uint32_t CR12;                              /**< Control Register 12, offset: 0x30 */
  __IO uint32_t CR13;                              /**< Control Register 13, offset: 0x34 */
  __IO uint32_t CR14;                              /**< Control Register 14, offset: 0x38 */
  __I  uint32_t CR15;                              /**< Control Register 15, offset: 0x3C */
  __IO uint32_t CR16;                              /**< Control Register 16, offset: 0x40 */
  __IO uint32_t CR17;                              /**< Control Register 17, offset: 0x44 */
  __IO uint32_t CR18;                              /**< Control Register 18, offset: 0x48 */
  __I  uint32_t CR19;                              /**< Control Register 19, offset: 0x4C */
  __IO uint32_t CR20;                              /**< Control Register 20, offset: 0x50 */
  __IO uint32_t CR21;                              /**< Control Register 21, offset: 0x54 */
  __IO uint32_t CR22;                              /**< Control Register 22, offset: 0x58 */
  __IO uint32_t CR23;                              /**< Control register 23, offset: 0x5C */
  __IO uint32_t CR24;                              /**< Control Register 24, offset: 0x60 */
  __IO uint32_t CR25;                              /**< Control Register 25, offset: 0x64 */
  __IO uint32_t CR26;                              /**< Control Register 26, offset: 0x68 */
  __I  uint32_t CR27;                              /**< Control Register 27, offset: 0x6C */
  __IO uint32_t CR28;                              /**< Control Register 28, offset: 0x70 */
  __IO uint32_t CR29;                              /**< Control Register 29, offset: 0x74 */
  __IO uint32_t CR30;                              /**< Control Register 30, offset: 0x78 */
  __IO uint32_t CR31;                              /**< Control Register 31, offset: 0x7C */
  __I  uint32_t CR32;                              /**< Control Register 32, offset: 0x80 */
  __IO uint32_t CR33;                              /**< Control Register 33, offset: 0x84 */
  __IO uint32_t CR34;                              /**< Control Register 34, offset: 0x88 */
  __IO uint32_t CR35;                              /**< Control Register 35, offset: 0x8C */
  __IO uint32_t CR36;                              /**< Control register 36, offset: 0x90 */
  __IO uint32_t CR37;                              /**< Control Register 37, offset: 0x94 */
  __IO uint32_t CR38;                              /**< Control Register 38, offset: 0x98 */
  __IO uint32_t CR39;                              /**< Control Register 39, offset: 0x9C */
  __I  uint32_t CR40;                              /**< Control Register 40, offset: 0xA0 */
  __IO uint32_t CR41;                              /**< Control Register 41, offset: 0xA4 */
  __I  uint32_t CR42;                              /**< Control Register 42, offset: 0xA8 */
  __I  uint32_t CR43;                              /**< Control Register 43, offset: 0xAC */
  __I  uint32_t CR44;                              /**< Control Register 44, offset: 0xB0 */
  __IO uint32_t CR45;                              /**< Control Register 45, offset: 0xB4 */
  __IO uint32_t CR46;                              /**< Control Register 46, offset: 0xB8 */
  __IO uint32_t CR47;                              /**< Control Register 47, offset: 0xBC */
  __IO uint32_t CR48;                              /**< Control Register 48, offset: 0xC0 */
  __IO uint32_t CR49;                              /**< Control Register 49, offset: 0xC4 */
  __I  uint32_t CR50;                              /**< Control Register 50, offset: 0xC8 */
  __IO uint32_t CR51;                              /**< Control Register 51, offset: 0xCC */
  __IO uint32_t CR52;                              /**< Control Register 52, offset: 0xD0 */
  __I  uint32_t CR53;                              /**< Control Register 53, offset: 0xD4 */
  __I  uint32_t CR54;                              /**< Control Register 54, offset: 0xD8 */
  __I  uint32_t CR55;                              /**< Control Register 55, offset: 0xDC */
  __I  uint32_t CR56;                              /**< Control Register 56, offset: 0xE0 */
  __IO uint32_t CR57;                              /**< Control Register 57, offset: 0xE4 */
  __IO uint32_t CR58;                              /**< Control Register 58, offset: 0xE8 */
  __I  uint32_t CR59;                              /**< Control Register 59, offset: 0xEC */
  __I  uint32_t CR60;                              /**< Control Register 60, offset: 0xF0 */
  __I  uint32_t CR61;                              /**< Control Register 61, offset: 0xF4 */
  __I  uint32_t CR62;                              /**< Control Register 62, offset: 0xF8 */
  __I  uint32_t CR63;                              /**< Control Register 63, offset: 0xFC */
  __I  uint32_t CR64;                              /**< Control Register 64, offset: 0x100 */
  __I  uint32_t CR65;                              /**< Control Register 65, offset: 0x104 */
  __IO uint32_t CR66;                              /**< Control Register 66, offset: 0x108 */
  __IO uint32_t CR67;                              /**< Control Register 67, offset: 0x10C */
  __I  uint32_t CR68;                              /**< Control Register 68, offset: 0x110 */
  __IO uint32_t CR69;                              /**< Control Register 69, offset: 0x114 */
  __IO uint32_t CR70;                              /**< Control Register 70, offset: 0x118 */
  __I  uint32_t CR71;                              /**< Control Register 71, offset: 0x11C */
  __IO uint32_t CR72;                              /**< Control Register 72, offset: 0x120 */
  __IO uint32_t CR73;                              /**< Control Register 73, offset: 0x124 */
  __IO uint32_t CR74;                              /**< Control Register 74, offset: 0x128 */
  __IO uint32_t CR75;                              /**< Control Register 75, offset: 0x12C */
  __IO uint32_t CR76;                              /**< Control Register 76, offset: 0x130 */
  __IO uint32_t CR77;                              /**< Control Register 77, offset: 0x134 */
  __IO uint32_t CR78;                              /**< Control Register 78, offset: 0x138 */
  __IO uint32_t CR79;                              /**< Control Register 79, offset: 0x13C */
  __I  uint32_t CR80;                              /**< Control Register 80, offset: 0x140 */
  __IO uint32_t CR81;                              /**< Control Register 81, offset: 0x144 */
  __IO uint32_t CR82;                              /**< Control Register 82, offset: 0x148 */
  __I  uint32_t CR83;                              /**< Control Register 83, offset: 0x14C */
  __I  uint32_t CR84;                              /**< Control Register 84, offset: 0x150 */
  __I  uint32_t CR85;                              /**< Control Register 85, offset: 0x154 */
  __I  uint32_t CR86;                              /**< Control Register 86, offset: 0x158 */
  __IO uint32_t CR87;                              /**< Control Register 87, offset: 0x15C */
  __IO uint32_t CR88;                              /**< Control Register 88, offset: 0x160 */
  __IO uint32_t CR89;                              /**< Control Register 89, offset: 0x164 */
  __I  uint32_t CR90;                              /**< Control Register 90, offset: 0x168 */
  __IO uint32_t CR91;                              /**< Control Register 91, offset: 0x16C */
  __IO uint32_t CR92;                              /**< Control Register 92, offset: 0x170 */
  __IO uint32_t CR93;                              /**< Control Register 93, offset: 0x174 */
  __IO uint32_t CR94;                              /**< Control Register 94, offset: 0x178 */
  __IO uint32_t CR95;                              /**< Control Register 95, offset: 0x17C */
  __IO uint32_t CR96;                              /**< Control Register 96, offset: 0x180 */
  __IO uint32_t CR97;                              /**< Control Register 97, offset: 0x184 */
  __IO uint32_t CR98;                              /**< Control Register 98, offset: 0x188 */
  __IO uint32_t CR99;                              /**< Control Register 99, offset: 0x18C */
  __IO uint32_t CR100;                             /**< Control Register 100, offset: 0x190 */
  __IO uint32_t CR101;                             /**< Control Register 101, offset: 0x194 */
  __IO uint32_t CR102;                             /**< Control Register 102, offset: 0x198 */
  __I  uint32_t CR103;                             /**< Control Register 103, offset: 0x19C */
  __IO uint32_t CR104;                             /**< Control Register 104, offset: 0x1A0 */
  __IO uint32_t CR105;                             /**< Control Register 105, offset: 0x1A4 */
  __IO uint32_t CR106;                             /**< Control Register 106, offset: 0x1A8 */
  __I  uint32_t CR107;                             /**< Control Register 107, offset: 0x1AC */
  __I  uint32_t CR108;                             /**< Control Register 108, offset: 0x1B0 */
  __IO uint32_t CR109;                             /**< Control Register 109, offset: 0x1B4 */
  __IO uint32_t CR110;                             /**< Control Register 110, offset: 0x1B8 */
  __I  uint32_t CR111;                             /**< Control Register 111, offset: 0x1BC */
  __I  uint32_t CR112;                             /**< Control Register 112, offset: 0x1C0 */
  __IO uint32_t CR113;                             /**< Control Register 113, offset: 0x1C4 */
  __IO uint32_t CR114;                             /**< Control Register 114, offset: 0x1C8 */
  __IO uint32_t CR115;                             /**< Control Register 115, offset: 0x1CC */
  __I  uint32_t CR116;                             /**< Control Register 116, offset: 0x1D0 */
  __IO uint32_t CR117;                             /**< Control Register 117, offset: 0x1D4 */
  __IO uint32_t CR118;                             /**< Control Register 118, offset: 0x1D8 */
  __IO uint32_t CR119;                             /**< Control Register 119, offset: 0x1DC */
  __IO uint32_t CR120;                             /**< Control Register 120, offset: 0x1E0 */
  __IO uint32_t CR121;                             /**< Control Register 121, offset: 0x1E4 */
  __IO uint32_t CR122;                             /**< Control Register 122, offset: 0x1E8 */
  __IO uint32_t CR123;                             /**< Control Register 123, offset: 0x1EC */
  __IO uint32_t CR124;                             /**< Control Register 124, offset: 0x1F0 */
  __IO uint32_t CR125;                             /**< Control Register 125, offset: 0x1F4 */
  __IO uint32_t CR126;                             /**< Control Register 126, offset: 0x1F8 */
  __IO uint32_t CR127;                             /**< Controla Register 127, offset: 0x1FC */
  __I  uint32_t CR128;                             /**< Control Register 128, offset: 0x200 */
  __I  uint32_t CR129;                             /**< Control Register 129, offset: 0x204 */
  __I  uint32_t CR130;                             /**< Control Register 130, offset: 0x208 */
  __IO uint32_t CR131;                             /**< Control Register 131, offset: 0x20C */
  __IO uint32_t CR132;                             /**< Control Register 132, offset: 0x210 */
  __I  uint32_t CR133;                             /**< Control Register 133, offset: 0x214 */
  __I  uint32_t CR134;                             /**< Control Register 134, offset: 0x218 */
  __I  uint32_t CR135;                             /**< Control Register 135, offset: 0x21C */
  __I  uint32_t CR136;                             /**< Control Register 136, offset: 0x220 */
  __IO uint32_t CR137;                             /**< Control Register 137, offset: 0x224 */
  __IO uint32_t CR138;                             /**< Control Register 138, offset: 0x228 */
  __IO uint32_t CR139;                             /**< Control Register 139, offset: 0x22C */
  __IO uint32_t CR140;                             /**< Control Register 140, offset: 0x230 */
  __IO uint32_t CR141;                             /**< Control Register 141, offset: 0x234 */
  __IO uint32_t CR142;                             /**< Control Register 142, offset: 0x238 */
  __IO uint32_t CR143;                             /**< Control Register 143, offset: 0x23C */
  __IO uint32_t CR144;                             /**< Control Register 144, offset: 0x240 */
  __IO uint32_t CR145;                             /**< Control Register 145, offset: 0x244 */
  __IO uint32_t CR146;                             /**< Control Register 146, offset: 0x248 */
  __IO uint32_t CR147;                             /**< Control Register 147, offset: 0x24C */
  __IO uint32_t CR148;                             /**< Control Register 148, offset: 0x250 */
  __IO uint32_t CR149;                             /**< Control Register 149, offset: 0x254 */
  __IO uint32_t CR150;                             /**< Control Register 150, offset: 0x258 */
  __IO uint32_t CR151;                             /**< Control Register 151, offset: 0x25C */
  __IO uint32_t CR152;                             /**< Control Register 152, offset: 0x260 */
  __IO uint32_t CR153;                             /**< Control Register 153, offset: 0x264 */
  __IO uint32_t CR154;                             /**< Control Register 154, offset: 0x268 */
  __IO uint32_t CR155;                             /**< Control Register 155, offset: 0x26C */
  __IO uint32_t CR156;                             /**< Control Register 156, offset: 0x270 */
  __IO uint32_t CR157;                             /**< Control Register 157, offset: 0x274 */
  __IO uint32_t CR158;                             /**< Control Register 158, offset: 0x278 */
  __I  uint32_t CR159;                             /**< Control Register 159, offset: 0x27C */
  __I  uint32_t CR160;                             /**< Control Register 160, offset: 0x280 */
  __IO uint32_t CR161;                             /**< Control Register 161, offset: 0x284 */
       uint8_t RESERVED_0[376];
  __IO uint32_t PHY00;                             /**< PHY Register 00, offset: 0x400 */
  __IO uint32_t PHY01;                             /**< PHY Register 01, offset: 0x404 */
  __IO uint32_t PHY02;                             /**< PHY Register 02, offset: 0x408 */
  __IO uint32_t PHY03;                             /**< PHY Register 03, offset: 0x40C */
  __IO uint32_t PHY04;                             /**< PHY Register 04, offset: 0x410 */
       uint8_t RESERVED_1[20];
  __IO uint32_t PHY10;                             /**< PHY Register 10, offset: 0x428 */
  __IO uint32_t PHY11;                             /**< PHY Register 11, offset: 0x42C */
  __IO uint32_t PHY12;                             /**< PHY Register 12, offset: 0x430 */
  __I  uint32_t PHY13;                             /**< PHY Register 13, offset: 0x434 */
       uint8_t RESERVED_2[8];
  __IO uint32_t PHY16;                             /**< PHY Register 01, offset: 0x440 */
  __IO uint32_t PHY17;                             /**< PHY Register 17, offset: 0x444 */
  __IO uint32_t PHY18;                             /**< PHY Register 18, offset: 0x448 */
  __IO uint32_t PHY19;                             /**< PHY Register 19, offset: 0x44C */
  __IO uint32_t PHY20;                             /**< PHY Register 20, offset: 0x450 */
       uint8_t RESERVED_3[20];
  __IO uint32_t PHY26;                             /**< PHY Register 26, offset: 0x468 */
  __IO uint32_t PHY27;                             /**< PHY Register 27, offset: 0x46C */
  __IO uint32_t PHY28;                             /**< PHY Register 28, offset: 0x470 */
  __I  uint32_t PHY29;                             /**< PHY Register 29, offset: 0x474 */
       uint8_t RESERVED_4[8];
  __IO uint32_t PHY32;                             /**< PHY Register 32, offset: 0x480 */
  __IO uint32_t PHY33;                             /**< PHY Register 33, offset: 0x484 */
  __IO uint32_t PHY34;                             /**< PHY Register 34, offset: 0x488 */
  __IO uint32_t PHY35;                             /**< PHY Register 35, offset: 0x48C */
  __IO uint32_t PHY36;                             /**< PHY Register 36, offset: 0x490 */
       uint8_t RESERVED_5[20];
  __IO uint32_t PHY42;                             /**< PHY Register 42, offset: 0x4A8 */
  __IO uint32_t PHY43;                             /**< PHY Register 43, offset: 0x4AC */
  __IO uint32_t PHY44;                             /**< PHY Register 44, offset: 0x4B0 */
  __I  uint32_t PHY45;                             /**< PHY Register 45, offset: 0x4B4 */
       uint8_t RESERVED_6[12];
  __IO uint32_t PHY49;                             /**< PHY Register 49, offset: 0x4C4 */
  __IO uint32_t PHY50;                             /**< PHY Register 50, offset: 0x4C8 */
       uint8_t RESERVED_7[4];
  __IO uint32_t PHY52;                             /**< PHY Register 52, offset: 0x4D0 */
} DDRMC_Type;

/* ----------------------------------------------------------------------------
   -- DDRMC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DDRMC_Register_Masks DDRMC Register Masks
 * @{
 */

/* CR00 Bit Fields */
#define DDRMC_CR00_START_MASK                    0x1u
#define DDRMC_CR00_START_SHIFT                   0
#define DDRMC_CR00_DRAM_CLASS_MASK               0xF00u
#define DDRMC_CR00_DRAM_CLASS_SHIFT              8
#define DDRMC_CR00_DRAM_CLASS(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR00_DRAM_CLASS_SHIFT))&DDRMC_CR00_DRAM_CLASS_MASK)
#define DDRMC_CR00_VERSION_MASK                  0xFFFF0000u
#define DDRMC_CR00_VERSION_SHIFT                 16
#define DDRMC_CR00_VERSION(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR00_VERSION_SHIFT))&DDRMC_CR00_VERSION_MASK)
/* CR01 Bit Fields */
#define DDRMC_CR01_MAX_ROW_REG_MASK              0x1Fu
#define DDRMC_CR01_MAX_ROW_REG_SHIFT             0
#define DDRMC_CR01_MAX_ROW_REG(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR01_MAX_ROW_REG_SHIFT))&DDRMC_CR01_MAX_ROW_REG_MASK)
#define DDRMC_CR01_MAX_COL_REG_MASK              0xF00u
#define DDRMC_CR01_MAX_COL_REG_SHIFT             8
#define DDRMC_CR01_MAX_COL_REG(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR01_MAX_COL_REG_SHIFT))&DDRMC_CR01_MAX_COL_REG_MASK)
#define DDRMC_CR01_MAX_CS_REG_MASK               0x10000u
#define DDRMC_CR01_MAX_CS_REG_SHIFT              16
/* CR02 Bit Fields */
#define DDRMC_CR02_TINIT_MASK                    0xFFFFFFu
#define DDRMC_CR02_TINIT_SHIFT                   0
#define DDRMC_CR02_TINIT(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR02_TINIT_SHIFT))&DDRMC_CR02_TINIT_MASK)
/* CR03 Bit Fields */
#define DDRMC_CR03_TINIT3_MASK                   0xFFFFFFu
#define DDRMC_CR03_TINIT3_SHIFT                  0
#define DDRMC_CR03_TINIT3(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR03_TINIT3_SHIFT))&DDRMC_CR03_TINIT3_MASK)
/* CR04 Bit Fields */
#define DDRMC_CR04_TINIT4_MASK                   0xFFFFFFu
#define DDRMC_CR04_TINIT4_SHIFT                  0
#define DDRMC_CR04_TINIT4(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR04_TINIT4_SHIFT))&DDRMC_CR04_TINIT4_MASK)
/* CR05 Bit Fields */
#define DDRMC_CR05_TINIT5_MASK                   0xFFFFFFu
#define DDRMC_CR05_TINIT5_SHIFT                  0
#define DDRMC_CR05_TINIT5(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR05_TINIT5_SHIFT))&DDRMC_CR05_TINIT5_MASK)
/* CR09 Bit Fields */
#define DDRMC_CR09_NO_MRR_MASK                   0x1000000u
#define DDRMC_CR09_NO_MRR_SHIFT                  24
/* CR10 Bit Fields */
#define DDRMC_CR10_TRST_PWRON_MASK               0xFFFFFFFFu
#define DDRMC_CR10_TRST_PWRON_SHIFT              0
#define DDRMC_CR10_TRST_PWRON(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR10_TRST_PWRON_SHIFT))&DDRMC_CR10_TRST_PWRON_MASK)
/* CR11 Bit Fields */
#define DDRMC_CR11_CKE_INACTIVE_MASK             0xFFFFFFFFu
#define DDRMC_CR11_CKE_INACTIVE_SHIFT            0
#define DDRMC_CR11_CKE_INACTIVE(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR11_CKE_INACTIVE_SHIFT))&DDRMC_CR11_CKE_INACTIVE_MASK)
/* CR12 Bit Fields */
#define DDRMC_CR12_CASLAT_LIN_MASK               0x3Fu
#define DDRMC_CR12_CASLAT_LIN_SHIFT              0
#define DDRMC_CR12_CASLAT_LIN(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR12_CASLAT_LIN_SHIFT))&DDRMC_CR12_CASLAT_LIN_MASK)
#define DDRMC_CR12_WRLAT_MASK                    0x1F00u
#define DDRMC_CR12_WRLAT_SHIFT                   8
#define DDRMC_CR12_WRLAT(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR12_WRLAT_SHIFT))&DDRMC_CR12_WRLAT_MASK)
/* CR13 Bit Fields */
#define DDRMC_CR13_TBST_INT_INTERVAL_MASK        0x7u
#define DDRMC_CR13_TBST_INT_INTERVAL_SHIFT       0
#define DDRMC_CR13_TBST_INT_INTERVAL(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_CR13_TBST_INT_INTERVAL_SHIFT))&DDRMC_CR13_TBST_INT_INTERVAL_MASK)
#define DDRMC_CR13_TCCD_MASK                     0x1F00u
#define DDRMC_CR13_TCCD_SHIFT                    8
#define DDRMC_CR13_TCCD(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR13_TCCD_SHIFT))&DDRMC_CR13_TCCD_MASK)
#define DDRMC_CR13_TRRD_MASK                     0xFF0000u
#define DDRMC_CR13_TRRD_SHIFT                    16
#define DDRMC_CR13_TRRD(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR13_TRRD_SHIFT))&DDRMC_CR13_TRRD_MASK)
#define DDRMC_CR13_TRC_MASK                      0xFF000000u
#define DDRMC_CR13_TRC_SHIFT                     24
#define DDRMC_CR13_TRC(x)                        (((uint32_t)(((uint32_t)(x))<<DDRMC_CR13_TRC_SHIFT))&DDRMC_CR13_TRC_MASK)
/* CR14 Bit Fields */
#define DDRMC_CR14_TRAS_MIN_MASK                 0xFFu
#define DDRMC_CR14_TRAS_MIN_SHIFT                0
#define DDRMC_CR14_TRAS_MIN(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR14_TRAS_MIN_SHIFT))&DDRMC_CR14_TRAS_MIN_MASK)
#define DDRMC_CR14_TWTR_MASK                     0xF00u
#define DDRMC_CR14_TWTR_SHIFT                    8
#define DDRMC_CR14_TWTR(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR14_TWTR_SHIFT))&DDRMC_CR14_TWTR_MASK)
#define DDRMC_CR14_TRP_MASK                      0x1F0000u
#define DDRMC_CR14_TRP_SHIFT                     16
#define DDRMC_CR14_TRP(x)                        (((uint32_t)(((uint32_t)(x))<<DDRMC_CR14_TRP_SHIFT))&DDRMC_CR14_TRP_MASK)
#define DDRMC_CR14_TFAW_MASK                     0x3F000000u
#define DDRMC_CR14_TFAW_SHIFT                    24
#define DDRMC_CR14_TFAW(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR14_TFAW_SHIFT))&DDRMC_CR14_TFAW_MASK)
/* CR16 Bit Fields */
#define DDRMC_CR16_TRTP_MASK                     0xF0000u
#define DDRMC_CR16_TRTP_SHIFT                    16
#define DDRMC_CR16_TRTP(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR16_TRTP_SHIFT))&DDRMC_CR16_TRTP_MASK)
#define DDRMC_CR16_TMRD_MASK                     0x1F000000u
#define DDRMC_CR16_TMRD_SHIFT                    24
#define DDRMC_CR16_TMRD(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR16_TMRD_SHIFT))&DDRMC_CR16_TMRD_MASK)
/* CR17 Bit Fields */
#define DDRMC_CR17_TMOD_MASK                     0xFFu
#define DDRMC_CR17_TMOD_SHIFT                    0
#define DDRMC_CR17_TMOD(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR17_TMOD_SHIFT))&DDRMC_CR17_TMOD_MASK)
#define DDRMC_CR17_TRAS_MAX_MASK                 0x1FFFF00u
#define DDRMC_CR17_TRAS_MAX_SHIFT                8
#define DDRMC_CR17_TRAS_MAX(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR17_TRAS_MAX_SHIFT))&DDRMC_CR17_TRAS_MAX_MASK)
/* CR18 Bit Fields */
#define DDRMC_CR18_TCKE_MASK                     0x7u
#define DDRMC_CR18_TCKE_SHIFT                    0
#define DDRMC_CR18_TCKE(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR18_TCKE_SHIFT))&DDRMC_CR18_TCKE_MASK)
#define DDRMC_CR18_TCKESR_MASK                   0x1F00u
#define DDRMC_CR18_TCKESR_SHIFT                  8
#define DDRMC_CR18_TCKESR(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR18_TCKESR_SHIFT))&DDRMC_CR18_TCKESR_MASK)
/* CR20 Bit Fields */
#define DDRMC_CR20_WRITEINTERP_MASK              0x10000u
#define DDRMC_CR20_WRITEINTERP_SHIFT             16
#define DDRMC_CR20_AP_MASK                       0x1000000u
#define DDRMC_CR20_AP_SHIFT                      24
/* CR21 Bit Fields */
#define DDRMC_CR21_CCMAP_MASK                    0x1u
#define DDRMC_CR21_CCMAP_SHIFT                   0
#define DDRMC_CR21_TRAS_LOCKOUT_MASK             0x100u
#define DDRMC_CR21_TRAS_LOCKOUT_SHIFT            8
#define DDRMC_CR21_TRCD_INT_MASK                 0xFF0000u
#define DDRMC_CR21_TRCD_INT_SHIFT                16
#define DDRMC_CR21_TRCD_INT(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR21_TRCD_INT_SHIFT))&DDRMC_CR21_TRCD_INT_MASK)
#define DDRMC_CR21_TWR_INT_MASK                  0x3F000000u
#define DDRMC_CR21_TWR_INT_SHIFT                 24
#define DDRMC_CR21_TWR_INT(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR21_TWR_INT_SHIFT))&DDRMC_CR21_TWR_INT_MASK)
/* CR22 Bit Fields */
#define DDRMC_CR22_TDAL_MASK                     0x3F0000u
#define DDRMC_CR22_TDAL_SHIFT                    16
#define DDRMC_CR22_TDAL(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR22_TDAL_SHIFT))&DDRMC_CR22_TDAL_MASK)
/* CR23 Bit Fields */
#define DDRMC_CR23_TDLL_MASK                     0xFFFFu
#define DDRMC_CR23_TDLL_SHIFT                    0
#define DDRMC_CR23_TDLL(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR23_TDLL_SHIFT))&DDRMC_CR23_TDLL_MASK)
#define DDRMC_CR23_TMRR_MASK                     0xF0000u
#define DDRMC_CR23_TMRR_SHIFT                    16
#define DDRMC_CR23_TMRR(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR23_TMRR_SHIFT))&DDRMC_CR23_TMRR_MASK)
#define DDRMC_CR23_BSTLEN_MASK                   0x7000000u
#define DDRMC_CR23_BSTLEN_SHIFT                  24
#define DDRMC_CR23_BSTLEN(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR23_BSTLEN_SHIFT))&DDRMC_CR23_BSTLEN_MASK)
/* CR24 Bit Fields */
#define DDRMC_CR24_TRP_AB_MASK                   0x1Fu
#define DDRMC_CR24_TRP_AB_SHIFT                  0
#define DDRMC_CR24_TRP_AB(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR24_TRP_AB_SHIFT))&DDRMC_CR24_TRP_AB_MASK)
#define DDRMC_CR24_ADD_MIR_MASK                  0x1000000u
#define DDRMC_CR24_ADD_MIR_SHIFT                 24
/* CR25 Bit Fields */
#define DDRMC_CR25_AREF_MASK                     0x1u
#define DDRMC_CR25_AREF_SHIFT                    0
#define DDRMC_CR25_AUTO_REFMOD_MASK              0x100u
#define DDRMC_CR25_AUTO_REFMOD_SHIFT             8
#define DDRMC_CR25_TREF_EN_MASK                  0x10000u
#define DDRMC_CR25_TREF_EN_SHIFT                 16
/* CR26 Bit Fields */
#define DDRMC_CR26_TRFC_MASK                     0x3FFu
#define DDRMC_CR26_TRFC_SHIFT                    0
#define DDRMC_CR26_TRFC(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR26_TRFC_SHIFT))&DDRMC_CR26_TRFC_MASK)
#define DDRMC_CR26_TREF_MASK                     0xFFFF0000u
#define DDRMC_CR26_TREF_SHIFT                    16
#define DDRMC_CR26_TREF(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR26_TREF_SHIFT))&DDRMC_CR26_TREF_MASK)
/* CR28 Bit Fields */
#define DDRMC_CR28_TREF_INT_MASK                 0xFFFFu
#define DDRMC_CR28_TREF_INT_SHIFT                0
#define DDRMC_CR28_TREF_INT(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR28_TREF_INT_SHIFT))&DDRMC_CR28_TREF_INT_MASK)
/* CR29 Bit Fields */
#define DDRMC_CR29_TPDEX_MASK                    0xFFFFu
#define DDRMC_CR29_TPDEX_SHIFT                   0
#define DDRMC_CR29_TPDEX(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR29_TPDEX_SHIFT))&DDRMC_CR29_TPDEX_MASK)
/* CR30 Bit Fields */
#define DDRMC_CR30_TXPDLL_MASK                   0xFFFFu
#define DDRMC_CR30_TXPDLL_SHIFT                  0
#define DDRMC_CR30_TXPDLL(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR30_TXPDLL_SHIFT))&DDRMC_CR30_TXPDLL_MASK)
/* CR31 Bit Fields */
#define DDRMC_CR31_TXSR_MASK                     0xFFFFu
#define DDRMC_CR31_TXSR_SHIFT                    0
#define DDRMC_CR31_TXSR(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR31_TXSR_SHIFT))&DDRMC_CR31_TXSR_MASK)
#define DDRMC_CR31_TXSNR_MASK                    0xFFFF0000u
#define DDRMC_CR31_TXSNR_SHIFT                   16
#define DDRMC_CR31_TXSNR(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR31_TXSNR_SHIFT))&DDRMC_CR31_TXSNR_MASK)
/* CR33 Bit Fields */
#define DDRMC_CR33_PWUP_SREF_EX_MASK             0x1u
#define DDRMC_CR33_PWUP_SREF_EX_SHIFT            0
#define DDRMC_CR33_SREF_EX_NOREF_MASK            0x100u
#define DDRMC_CR33_SREF_EX_NOREF_SHIFT           8
#define DDRMC_CR33_EN_QK_SREF_MASK               0x10000u
#define DDRMC_CR33_EN_QK_SREF_SHIFT              16
#define DDRMC_CR33_CKE_DELAY_MASK                0x7000000u
#define DDRMC_CR33_CKE_DELAY_SHIFT               24
#define DDRMC_CR33_CKE_DELAY(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR33_CKE_DELAY_SHIFT))&DDRMC_CR33_CKE_DELAY_MASK)
/* CR34 Bit Fields */
#define DDRMC_CR34_LP_REFEN_MASK                 0x1u
#define DDRMC_CR34_LP_REFEN_SHIFT                0
#define DDRMC_CR34_CKSRE_MASK                    0xF00u
#define DDRMC_CR34_CKSRE_SHIFT                   8
#define DDRMC_CR34_CKSRE(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR34_CKSRE_SHIFT))&DDRMC_CR34_CKSRE_MASK)
#define DDRMC_CR34_CKSRX_MASK                    0xF0000u
#define DDRMC_CR34_CKSRX_SHIFT                   16
#define DDRMC_CR34_CKSRX(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR34_CKSRX_SHIFT))&DDRMC_CR34_CKSRX_MASK)
/* CR35 Bit Fields */
#define DDRMC_CR35_LP_CMD_MASK                   0xFF00u
#define DDRMC_CR35_LP_CMD_SHIFT                  8
#define DDRMC_CR35_LP_CMD(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR35_LP_CMD_SHIFT))&DDRMC_CR35_LP_CMD_MASK)
#define DDRMC_CR35_LP_ST_MASK                    0x3F0000u
#define DDRMC_CR35_LP_ST_SHIFT                   16
#define DDRMC_CR35_LP_ST(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR35_LP_ST_SHIFT))&DDRMC_CR35_LP_ST_MASK)
#define DDRMC_CR35_LP_ARBST_MASK                 0xF000000u
#define DDRMC_CR35_LP_ARBST_SHIFT                24
#define DDRMC_CR35_LP_ARBST(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR35_LP_ARBST_SHIFT))&DDRMC_CR35_LP_ARBST_MASK)
/* CR36 Bit Fields */
#define DDRMC_CR36_LPAUTO_MASK                   0x7u
#define DDRMC_CR36_LPAUTO_SHIFT                  0
#define DDRMC_CR36_LPAUTO(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR36_LPAUTO_SHIFT))&DDRMC_CR36_LPAUTO_MASK)
#define DDRMC_CR36_LP_AEXEN_MASK                 0x700u
#define DDRMC_CR36_LP_AEXEN_SHIFT                8
#define DDRMC_CR36_LP_AEXEN(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR36_LP_AEXEN_SHIFT))&DDRMC_CR36_LP_AEXEN_MASK)
#define DDRMC_CR36_LP_AMEMEN_MASK                0x30000u
#define DDRMC_CR36_LP_AMEMEN_SHIFT               16
#define DDRMC_CR36_LP_AMEMEN(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR36_LP_AMEMEN_SHIFT))&DDRMC_CR36_LP_AMEMEN_MASK)
/* CR37 Bit Fields */
#define DDRMC_CR37_LP_A_PD_IDL_MASK              0xFFFu
#define DDRMC_CR37_LP_A_PD_IDL_SHIFT             0
#define DDRMC_CR37_LP_A_PD_IDL(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR37_LP_A_PD_IDL_SHIFT))&DDRMC_CR37_LP_A_PD_IDL_MASK)
#define DDRMC_CR37_LP_A_SR_IDL_MASK              0xFF0000u
#define DDRMC_CR37_LP_A_SR_IDL_SHIFT             16
#define DDRMC_CR37_LP_A_SR_IDL(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR37_LP_A_SR_IDL_SHIFT))&DDRMC_CR37_LP_A_SR_IDL_MASK)
#define DDRMC_CR37_LP_A_SR_MC_IDL_MASK           0xFF000000u
#define DDRMC_CR37_LP_A_SR_MC_IDL_SHIFT          24
#define DDRMC_CR37_LP_A_SR_MC_IDL(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR37_LP_A_SR_MC_IDL_SHIFT))&DDRMC_CR37_LP_A_SR_MC_IDL_MASK)
/* CR38 Bit Fields */
#define DDRMC_CR38_FREQ_CHG_EN_MASK              0x100u
#define DDRMC_CR38_FREQ_CHG_EN_SHIFT             8
#define DDRMC_CR38_FRQ_CHG_HOEN_MASK             0x10000u
#define DDRMC_CR38_FRQ_CHG_HOEN_SHIFT            16
#define DDRMC_CR38_FREQ_CHG_HOCL_MASK            0x1000000u
#define DDRMC_CR38_FREQ_CHG_HOCL_SHIFT           24
/* CR39 Bit Fields */
#define DDRMC_CR39_FRQ_CH_DLLOFF_MASK            0x3u
#define DDRMC_CR39_FRQ_CH_DLLOFF_SHIFT           0
#define DDRMC_CR39_FRQ_CH_DLLOFF(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR39_FRQ_CH_DLLOFF_SHIFT))&DDRMC_CR39_FRQ_CH_DLLOFF_MASK)
#define DDRMC_CR39_PHY_INI_STA_MASK              0xFF00u
#define DDRMC_CR39_PHY_INI_STA_SHIFT             8
#define DDRMC_CR39_PHY_INI_STA(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR39_PHY_INI_STA_SHIFT))&DDRMC_CR39_PHY_INI_STA_MASK)
#define DDRMC_CR39_PHY_INI_COM_MASK              0xFFFF0000u
#define DDRMC_CR39_PHY_INI_COM_SHIFT             16
#define DDRMC_CR39_PHY_INI_COM(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR39_PHY_INI_COM_SHIFT))&DDRMC_CR39_PHY_INI_COM_MASK)
/* CR40 Bit Fields */
#define DDRMC_CR40_CURR_REG_CP_MASK              0x1000000u
#define DDRMC_CR40_CURR_REG_CP_SHIFT             24
/* CR41 Bit Fields */
#define DDRMC_CR41_PHY_INI_STRT_INI_DIS_MASK     0x1u
#define DDRMC_CR41_PHY_INI_STRT_INI_DIS_SHIFT    0
/* CR45 Bit Fields */
#define DDRMC_CR45_WRMD_MASK                     0x3FFFFFFu
#define DDRMC_CR45_WRMD_SHIFT                    0
#define DDRMC_CR45_WRMD(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR45_WRMD_SHIFT))&DDRMC_CR45_WRMD_MASK)
/* CR46 Bit Fields */
#define DDRMC_CR46_MRW_STAT_MASK                 0xFFu
#define DDRMC_CR46_MRW_STAT_SHIFT                0
#define DDRMC_CR46_MRW_STAT(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR46_MRW_STAT_SHIFT))&DDRMC_CR46_MRW_STAT_MASK)
#define DDRMC_CR46_RMD_MASK                      0x1FFFF00u
#define DDRMC_CR46_RMD_SHIFT                     8
#define DDRMC_CR46_RMD(x)                        (((uint32_t)(((uint32_t)(x))<<DDRMC_CR46_RMD_SHIFT))&DDRMC_CR46_RMD_MASK)
/* CR47 Bit Fields */
#define DDRMC_CR47_PERI_MRR_DA_MASK              0xFFFFu
#define DDRMC_CR47_PERI_MRR_DA_SHIFT             0
#define DDRMC_CR47_PERI_MRR_DA(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR47_PERI_MRR_DA_SHIFT))&DDRMC_CR47_PERI_MRR_DA_MASK)
#define DDRMC_CR47_AU_TMPCHK_VAL_MASK            0xF0000u
#define DDRMC_CR47_AU_TMPCHK_VAL_SHIFT           16
#define DDRMC_CR47_AU_TMPCHK_VAL(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR47_AU_TMPCHK_VAL_SHIFT))&DDRMC_CR47_AU_TMPCHK_VAL_MASK)
#define DDRMC_CR47_REF_AU_TMPCHK_MASK            0xFF000000u
#define DDRMC_CR47_REF_AU_TMPCHK_SHIFT           24
#define DDRMC_CR47_REF_AU_TMPCHK(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR47_REF_AU_TMPCHK_SHIFT))&DDRMC_CR47_REF_AU_TMPCHK_MASK)
/* CR48 Bit Fields */
#define DDRMC_CR48_MR0_DA_0_MASK                 0xFFFFu
#define DDRMC_CR48_MR0_DA_0_SHIFT                0
#define DDRMC_CR48_MR0_DA_0(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR48_MR0_DA_0_SHIFT))&DDRMC_CR48_MR0_DA_0_MASK)
#define DDRMC_CR48_MR1_DA_0_MASK                 0xFFFF0000u
#define DDRMC_CR48_MR1_DA_0_SHIFT                16
#define DDRMC_CR48_MR1_DA_0(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR48_MR1_DA_0_SHIFT))&DDRMC_CR48_MR1_DA_0_MASK)
/* CR49 Bit Fields */
#define DDRMC_CR49_MR2_DA_0_MASK                 0xFFFFu
#define DDRMC_CR49_MR2_DA_0_SHIFT                0
#define DDRMC_CR49_MR2_DA_0(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR49_MR2_DA_0_SHIFT))&DDRMC_CR49_MR2_DA_0_MASK)
/* CR51 Bit Fields */
#define DDRMC_CR51_MR_SINDA0_MASK                0xFFFFu
#define DDRMC_CR51_MR_SINDA0_SHIFT               0
#define DDRMC_CR51_MR_SINDA0(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR51_MR_SINDA0_SHIFT))&DDRMC_CR51_MR_SINDA0_MASK)
#define DDRMC_CR51_MR3_DA0_MASK                  0xFFFF0000u
#define DDRMC_CR51_MR3_DA0_SHIFT                 16
#define DDRMC_CR51_MR3_DA0(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR51_MR3_DA0_SHIFT))&DDRMC_CR51_MR3_DA0_MASK)
/* CR52 Bit Fields */
#define DDRMC_CR52_MR18_DA0_MASK                 0xFFu
#define DDRMC_CR52_MR18_DA0_SHIFT                0
#define DDRMC_CR52_MR18_DA0(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR52_MR18_DA0_SHIFT))&DDRMC_CR52_MR18_DA0_MASK)
#define DDRMC_CR52_MR16_DA0_MASK                 0xFF00u
#define DDRMC_CR52_MR16_DA0_SHIFT                8
#define DDRMC_CR52_MR16_DA0(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR52_MR16_DA0_SHIFT))&DDRMC_CR52_MR16_DA0_MASK)
#define DDRMC_CR52_MR17_DA0_MASK                 0xFF0000u
#define DDRMC_CR52_MR17_DA0_SHIFT                16
#define DDRMC_CR52_MR17_DA0(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR52_MR17_DA0_SHIFT))&DDRMC_CR52_MR17_DA0_MASK)
/* CR57 Bit Fields */
#define DDRMC_CR57_CTRL_RAW_MASK                 0x3000000u
#define DDRMC_CR57_CTRL_RAW_SHIFT                24
#define DDRMC_CR57_CTRL_RAW(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR57_CTRL_RAW_SHIFT))&DDRMC_CR57_CTRL_RAW_MASK)
/* CR58 Bit Fields */
#define DDRMC_CR58_FWC_MASK                      0x1u
#define DDRMC_CR58_FWC_SHIFT                     0
#define DDRMC_CR58_XOR_CHK_BITS_MASK             0x3FFF00u
#define DDRMC_CR58_XOR_CHK_BITS_SHIFT            8
#define DDRMC_CR58_XOR_CHK_BITS(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR58_XOR_CHK_BITS_SHIFT))&DDRMC_CR58_XOR_CHK_BITS_MASK)
#define DDRMC_CR58_ECC_DIS_WCRER_MASK            0x1000000u
#define DDRMC_CR58_ECC_DIS_WCRER_SHIFT           24
/* CR59 Bit Fields */
#define DDRMC_CR59_ECC_U_ADR_MASK                0xFFFFFFFFu
#define DDRMC_CR59_ECC_U_ADR_SHIFT               0
#define DDRMC_CR59_ECC_U_ADR(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR59_ECC_U_ADR_SHIFT))&DDRMC_CR59_ECC_U_ADR_MASK)
/* CR60 Bit Fields */
#define DDRMC_CR60_ECC_U_SYND_MASK               0x7Fu
#define DDRMC_CR60_ECC_U_SYND_SHIFT              0
#define DDRMC_CR60_ECC_U_SYND(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR60_ECC_U_SYND_SHIFT))&DDRMC_CR60_ECC_U_SYND_MASK)
/* CR61 Bit Fields */
#define DDRMC_CR61_ECC_U_DATA_MASK               0xFFFFFFFFu
#define DDRMC_CR61_ECC_U_DATA_SHIFT              0
#define DDRMC_CR61_ECC_U_DATA(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR61_ECC_U_DATA_SHIFT))&DDRMC_CR61_ECC_U_DATA_MASK)
/* CR62 Bit Fields */
#define DDRMC_CR62_ECC_C_ADDR_MASK               0xFFFFFFFFu
#define DDRMC_CR62_ECC_C_ADDR_SHIFT              0
#define DDRMC_CR62_ECC_C_ADDR(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR62_ECC_C_ADDR_SHIFT))&DDRMC_CR62_ECC_C_ADDR_MASK)
/* CR63 Bit Fields */
#define DDRMC_CR63_ECC_C_SYND_MASK               0x3Fu
#define DDRMC_CR63_ECC_C_SYND_SHIFT              0
#define DDRMC_CR63_ECC_C_SYND(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR63_ECC_C_SYND_SHIFT))&DDRMC_CR63_ECC_C_SYND_MASK)
/* CR64 Bit Fields */
#define DDRMC_CR64_ECC_C_DATA_MASK               0xFFFFFFFFu
#define DDRMC_CR64_ECC_C_DATA_SHIFT              0
#define DDRMC_CR64_ECC_C_DATA(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR64_ECC_C_DATA_SHIFT))&DDRMC_CR64_ECC_C_DATA_MASK)
/* CR65 Bit Fields */
#define DDRMC_CR65_ECC_U_ID_MASK                 0x1FFFu
#define DDRMC_CR65_ECC_U_ID_SHIFT                0
#define DDRMC_CR65_ECC_U_ID(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR65_ECC_U_ID_SHIFT))&DDRMC_CR65_ECC_U_ID_MASK)
#define DDRMC_CR65_ECC_C_ID_MASK                 0x3FFF0000u
#define DDRMC_CR65_ECC_C_ID_SHIFT                16
#define DDRMC_CR65_ECC_C_ID(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR65_ECC_C_ID_SHIFT))&DDRMC_CR65_ECC_C_ID_MASK)
/* CR66 Bit Fields */
#define DDRMC_CR66_ZQINIT_MASK                   0xFFFu
#define DDRMC_CR66_ZQINIT_SHIFT                  0
#define DDRMC_CR66_ZQINIT(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR66_ZQINIT_SHIFT))&DDRMC_CR66_ZQINIT_MASK)
#define DDRMC_CR66_ZQCL_MASK                     0xFFF0000u
#define DDRMC_CR66_ZQCL_SHIFT                    16
#define DDRMC_CR66_ZQCL(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR66_ZQCL_SHIFT))&DDRMC_CR66_ZQCL_MASK)
/* CR67 Bit Fields */
#define DDRMC_CR67_ZQCS_MASK                     0xFFFu
#define DDRMC_CR67_ZQCS_SHIFT                    0
#define DDRMC_CR67_ZQCS(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR67_ZQCS_SHIFT))&DDRMC_CR67_ZQCS_MASK)
/* CR69 Bit Fields */
#define DDRMC_CR69_ZQ_REQ_MASK                   0xFu
#define DDRMC_CR69_ZQ_REQ_SHIFT                  0
#define DDRMC_CR69_ZQ_REQ(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR69_ZQ_REQ_SHIFT))&DDRMC_CR69_ZQ_REQ_MASK)
#define DDRMC_CR69_ZQ_ON_SREF_EX_MASK            0xF00u
#define DDRMC_CR69_ZQ_ON_SREF_EX_SHIFT           8
#define DDRMC_CR69_ZQ_ON_SREF_EX(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR69_ZQ_ON_SREF_EX_SHIFT))&DDRMC_CR69_ZQ_ON_SREF_EX_MASK)
/* CR70 Bit Fields */
#define DDRMC_CR70_REF_PER_ZQ_MASK               0xFFFFFFFFu
#define DDRMC_CR70_REF_PER_ZQ_SHIFT              0
#define DDRMC_CR70_REF_PER_ZQ(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR70_REF_PER_ZQ_SHIFT))&DDRMC_CR70_REF_PER_ZQ_MASK)
/* CR71 Bit Fields */
#define DDRMC_CR71_ZQ_IN_PROG_MASK               0x1u
#define DDRMC_CR71_ZQ_IN_PROG_SHIFT              0
#define DDRMC_CR71_ZQRESET_MASK                  0xFFF00u
#define DDRMC_CR71_ZQRESET_SHIFT                 8
#define DDRMC_CR71_ZQRESET(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR71_ZQRESET_SHIFT))&DDRMC_CR71_ZQRESET_MASK)
/* CR72 Bit Fields */
#define DDRMC_CR72_NO_ZQ_INIT_MASK               0x10000u
#define DDRMC_CR72_NO_ZQ_INIT_SHIFT              16
#define DDRMC_CR72_ZQCS_ROTATE_MASK              0x1000000u
#define DDRMC_CR72_ZQCS_ROTATE_SHIFT             24
/* CR73 Bit Fields */
#define DDRMC_CR73_BANK_DIFF_MASK                0x3u
#define DDRMC_CR73_BANK_DIFF_SHIFT               0
#define DDRMC_CR73_BANK_DIFF(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR73_BANK_DIFF_SHIFT))&DDRMC_CR73_BANK_DIFF_MASK)
#define DDRMC_CR73_ROW_DIFF_MASK                 0x300u
#define DDRMC_CR73_ROW_DIFF_SHIFT                8
#define DDRMC_CR73_ROW_DIFF(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR73_ROW_DIFF_SHIFT))&DDRMC_CR73_ROW_DIFF_MASK)
#define DDRMC_CR73_COL_DIFF_MASK                 0x70000u
#define DDRMC_CR73_COL_DIFF_SHIFT                16
#define DDRMC_CR73_COL_DIFF(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR73_COL_DIFF_SHIFT))&DDRMC_CR73_COL_DIFF_MASK)
#define DDRMC_CR73_APREBIT_MASK                  0xF000000u
#define DDRMC_CR73_APREBIT_SHIFT                 24
#define DDRMC_CR73_APREBIT(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR73_APREBIT_SHIFT))&DDRMC_CR73_APREBIT_MASK)
/* CR74 Bit Fields */
#define DDRMC_CR74_AGE_CNT_MASK                  0xFFu
#define DDRMC_CR74_AGE_CNT_SHIFT                 0
#define DDRMC_CR74_AGE_CNT(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR74_AGE_CNT_SHIFT))&DDRMC_CR74_AGE_CNT_MASK)
#define DDRMC_CR74_CMD_AGE_CNT_MASK              0xFF00u
#define DDRMC_CR74_CMD_AGE_CNT_SHIFT             8
#define DDRMC_CR74_CMD_AGE_CNT(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR74_CMD_AGE_CNT_SHIFT))&DDRMC_CR74_CMD_AGE_CNT_MASK)
#define DDRMC_CR74_ADDR_CMP_EN_MASK              0x10000u
#define DDRMC_CR74_ADDR_CMP_EN_SHIFT             16
#define DDRMC_CR74_BANKSPLT_EN_MASK              0x1000000u
#define DDRMC_CR74_BANKSPLT_EN_SHIFT             24
/* CR75 Bit Fields */
#define DDRMC_CR75_PLEN_MASK                     0x1u
#define DDRMC_CR75_PLEN_SHIFT                    0
#define DDRMC_CR75_PRI_EN_MASK                   0x100u
#define DDRMC_CR75_PRI_EN_SHIFT                  8
#define DDRMC_CR75_RW_EN_MASK                    0x10000u
#define DDRMC_CR75_RW_EN_SHIFT                   16
#define DDRMC_CR75_RW_PG_EN_MASK                 0x1000000u
#define DDRMC_CR75_RW_PG_EN_SHIFT                24
/* CR76 Bit Fields */
#define DDRMC_CR76_CS_EN_MASK                    0x1u
#define DDRMC_CR76_CS_EN_SHIFT                   0
#define DDRMC_CR76_W2R_SPLT_EN_MASK              0x100u
#define DDRMC_CR76_W2R_SPLT_EN_SHIFT             8
#define DDRMC_CR76_D_RW_G_BKCN_MASK              0x30000u
#define DDRMC_CR76_D_RW_G_BKCN_SHIFT             16
#define DDRMC_CR76_D_RW_G_BKCN(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR76_D_RW_G_BKCN_SHIFT))&DDRMC_CR76_D_RW_G_BKCN_MASK)
#define DDRMC_CR76_NQENT_ACTDIS_MASK             0x7000000u
#define DDRMC_CR76_NQENT_ACTDIS_SHIFT            24
#define DDRMC_CR76_NQENT_ACTDIS(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR76_NQENT_ACTDIS_SHIFT))&DDRMC_CR76_NQENT_ACTDIS_MASK)
/* CR77 Bit Fields */
#define DDRMC_CR77_SWAP_EN_MASK                  0x1u
#define DDRMC_CR77_SWAP_EN_SHIFT                 0
#define DDRMC_CR77_DI_RD_INTLEAVE_MASK           0x100u
#define DDRMC_CR77_DI_RD_INTLEAVE_SHIFT          8
#define DDRMC_CR77_IN_DRAM_CMD_MASK              0x30000u
#define DDRMC_CR77_IN_DRAM_CMD_SHIFT             16
#define DDRMC_CR77_IN_DRAM_CMD(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR77_IN_DRAM_CMD_SHIFT))&DDRMC_CR77_IN_DRAM_CMD_MASK)
#define DDRMC_CR77_CS_MAP_MASK                   0x1000000u
#define DDRMC_CR77_CS_MAP_SHIFT                  24
/* CR78 Bit Fields */
#define DDRMC_CR78_BUR_ON_FLY_BIT_MASK           0xFu
#define DDRMC_CR78_BUR_ON_FLY_BIT_SHIFT          0
#define DDRMC_CR78_BUR_ON_FLY_BIT(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR78_BUR_ON_FLY_BIT_SHIFT))&DDRMC_CR78_BUR_ON_FLY_BIT_MASK)
#define DDRMC_CR78_REDUC_MASK                    0x100u
#define DDRMC_CR78_REDUC_SHIFT                   8
#define DDRMC_CR78_LPDDR2_S4_MASK                0x10000u
#define DDRMC_CR78_LPDDR2_S4_SHIFT               16
#define DDRMC_CR78_Q_FULLNESS_MASK               0x7000000u
#define DDRMC_CR78_Q_FULLNESS_SHIFT              24
#define DDRMC_CR78_Q_FULLNESS(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR78_Q_FULLNESS_SHIFT))&DDRMC_CR78_Q_FULLNESS_MASK)
/* CR79 Bit Fields */
#define DDRMC_CR79_INODR_ACT_MASK                0x1u
#define DDRMC_CR79_INODR_ACT_SHIFT               0
#define DDRMC_CR79_CTLBUSY_MASK                  0x100u
#define DDRMC_CR79_CTLBUSY_SHIFT                 8
#define DDRMC_CR79_CTLUPD_REQ_MASK               0x10000u
#define DDRMC_CR79_CTLUPD_REQ_SHIFT              16
#define DDRMC_CR79_CTLUPD_AREF_MASK              0x1000000u
#define DDRMC_CR79_CTLUPD_AREF_SHIFT             24
/* CR80 Bit Fields */
#define DDRMC_CR80_INT_STAT_MASK                 0x1FFFFFFFu
#define DDRMC_CR80_INT_STAT_SHIFT                0
#define DDRMC_CR80_INT_STAT(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR80_INT_STAT_SHIFT))&DDRMC_CR80_INT_STAT_MASK)
/* CR81 Bit Fields */
#define DDRMC_CR81_INT_ACK_MASK                  0xFFFFFFFu
#define DDRMC_CR81_INT_ACK_SHIFT                 0
#define DDRMC_CR81_INT_ACK(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR81_INT_ACK_SHIFT))&DDRMC_CR81_INT_ACK_MASK)
/* CR82 Bit Fields */
#define DDRMC_CR82_INT_MASK_MASK                 0x1FFFFFFFu
#define DDRMC_CR82_INT_MASK_SHIFT                0
#define DDRMC_CR82_INT_MASK(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR82_INT_MASK_SHIFT))&DDRMC_CR82_INT_MASK_MASK)
/* CR83 Bit Fields */
#define DDRMC_CR83_OORAD_MASK                    0xFFFFFFFFu
#define DDRMC_CR83_OORAD_SHIFT                   0
#define DDRMC_CR83_OORAD(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR83_OORAD_SHIFT))&DDRMC_CR83_OORAD_MASK)
/* CR84 Bit Fields */
#define DDRMC_CR84_OORLEN_MASK                   0x7Fu
#define DDRMC_CR84_OORLEN_SHIFT                  0
#define DDRMC_CR84_OORLEN(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR84_OORLEN_SHIFT))&DDRMC_CR84_OORLEN_MASK)
#define DDRMC_CR84_OORTYP_MASK                   0x3F00u
#define DDRMC_CR84_OORTYP_SHIFT                  8
#define DDRMC_CR84_OORTYP(x)                     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR84_OORTYP_SHIFT))&DDRMC_CR84_OORTYP_MASK)
#define DDRMC_CR84_OORID_MASK                    0x3FFF0000u
#define DDRMC_CR84_OORID_SHIFT                   16
#define DDRMC_CR84_OORID(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR84_OORID_SHIFT))&DDRMC_CR84_OORID_MASK)
/* CR85 Bit Fields */
#define DDRMC_CR85_P_CMDERRADD_MASK              0xFFFFFFFFu
#define DDRMC_CR85_P_CMDERRADD_SHIFT             0
#define DDRMC_CR85_P_CMDERRADD(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR85_P_CMDERRADD_SHIFT))&DDRMC_CR85_P_CMDERRADD_MASK)
/* CR86 Bit Fields */
#define DDRMC_CR86_P_CMDERRID_MASK               0x3FFFu
#define DDRMC_CR86_P_CMDERRID_SHIFT              0
#define DDRMC_CR86_P_CMDERRID(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR86_P_CMDERRID_SHIFT))&DDRMC_CR86_P_CMDERRID_MASK)
#define DDRMC_CR86_P_CMDERR_TYP_MASK             0x30000u
#define DDRMC_CR86_P_CMDERR_TYP_SHIFT            16
#define DDRMC_CR86_P_CMDERR_TYP(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR86_P_CMDERR_TYP_SHIFT))&DDRMC_CR86_P_CMDERR_TYP_MASK)
/* CR87 Bit Fields */
#define DDRMC_CR87_ODT_RD_MAPCS0_MASK            0x10000u
#define DDRMC_CR87_ODT_RD_MAPCS0_SHIFT           16
#define DDRMC_CR87_ODT_WR_MAPCS0_MASK            0x1000000u
#define DDRMC_CR87_ODT_WR_MAPCS0_SHIFT           24
/* CR88 Bit Fields */
#define DDRMC_CR88_TODTL_CMD_MASK                0x1F0000u
#define DDRMC_CR88_TODTL_CMD_SHIFT               16
#define DDRMC_CR88_TODTL_CMD(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR88_TODTL_CMD_SHIFT))&DDRMC_CR88_TODTL_CMD_MASK)
/* CR89 Bit Fields */
#define DDRMC_CR89_AODT_RWSMCS_MASK              0xFu
#define DDRMC_CR89_AODT_RWSMCS_SHIFT             0
#define DDRMC_CR89_AODT_RWSMCS(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR89_AODT_RWSMCS_SHIFT))&DDRMC_CR89_AODT_RWSMCS_MASK)
#define DDRMC_CR89_AODT_WRSMCS_MASK              0xF00u
#define DDRMC_CR89_AODT_WRSMCS_SHIFT             8
#define DDRMC_CR89_AODT_WRSMCS(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR89_AODT_WRSMCS_SHIFT))&DDRMC_CR89_AODT_WRSMCS_MASK)
/* CR91 Bit Fields */
#define DDRMC_CR91_R2R_SMCSDL_MASK               0x700u
#define DDRMC_CR91_R2R_SMCSDL_SHIFT              8
#define DDRMC_CR91_R2R_SMCSDL(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR91_R2R_SMCSDL_SHIFT))&DDRMC_CR91_R2R_SMCSDL_MASK)
#define DDRMC_CR91_R2W_SMCSDL_MASK               0x70000u
#define DDRMC_CR91_R2W_SMCSDL_SHIFT              16
#define DDRMC_CR91_R2W_SMCSDL(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR91_R2W_SMCSDL_SHIFT))&DDRMC_CR91_R2W_SMCSDL_MASK)
#define DDRMC_CR91_W2R_SMCSDL_MASK               0x7000000u
#define DDRMC_CR91_W2R_SMCSDL_SHIFT              24
#define DDRMC_CR91_W2R_SMCSDL(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR91_W2R_SMCSDL_SHIFT))&DDRMC_CR91_W2R_SMCSDL_MASK)
/* CR92 Bit Fields */
#define DDRMC_CR92_W2W_SMCSDL_MASK               0x7u
#define DDRMC_CR92_W2W_SMCSDL_SHIFT              0
#define DDRMC_CR92_W2W_SMCSDL(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR92_W2W_SMCSDL_SHIFT))&DDRMC_CR92_W2W_SMCSDL_MASK)
#define DDRMC_CR92_TDQSCK_MAX_MASK               0x300u
#define DDRMC_CR92_TDQSCK_MAX_SHIFT              8
#define DDRMC_CR92_TDQSCK_MAX(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR92_TDQSCK_MAX_SHIFT))&DDRMC_CR92_TDQSCK_MAX_MASK)
#define DDRMC_CR92_TDQSCK_MIN_MASK               0x30000u
#define DDRMC_CR92_TDQSCK_MIN_SHIFT              16
#define DDRMC_CR92_TDQSCK_MIN(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR92_TDQSCK_MIN_SHIFT))&DDRMC_CR92_TDQSCK_MIN_MASK)
/* CR93 Bit Fields */
#define DDRMC_CR93_SW_LVL_MODE_MASK              0x300u
#define DDRMC_CR93_SW_LVL_MODE_SHIFT             8
#define DDRMC_CR93_SW_LVL_MODE(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR93_SW_LVL_MODE_SHIFT))&DDRMC_CR93_SW_LVL_MODE_MASK)
#define DDRMC_CR93_SWLVL_LOAD_MASK               0x10000u
#define DDRMC_CR93_SWLVL_LOAD_SHIFT              16
#define DDRMC_CR93_SWLVL_START_MASK              0x1000000u
#define DDRMC_CR93_SWLVL_START_SHIFT             24
/* CR94 Bit Fields */
#define DDRMC_CR94_SWLVL_EXIT_MASK               0x1u
#define DDRMC_CR94_SWLVL_EXIT_SHIFT              0
#define DDRMC_CR94_SWLVL_OP_DONE_MASK            0x100u
#define DDRMC_CR94_SWLVL_OP_DONE_SHIFT           8
#define DDRMC_CR94_LVL_STATUS_MASK               0x70000u
#define DDRMC_CR94_LVL_STATUS_SHIFT              16
#define DDRMC_CR94_LVL_STATUS(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR94_LVL_STATUS_SHIFT))&DDRMC_CR94_LVL_STATUS_MASK)
#define DDRMC_CR94_SWLVL_RESP_0_MASK             0xFF000000u
#define DDRMC_CR94_SWLVL_RESP_0_SHIFT            24
#define DDRMC_CR94_SWLVL_RESP_0(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR94_SWLVL_RESP_0_SHIFT))&DDRMC_CR94_SWLVL_RESP_0_MASK)
/* CR95 Bit Fields */
#define DDRMC_CR95_SWLVL_RESP_1_MASK             0xFFu
#define DDRMC_CR95_SWLVL_RESP_1_SHIFT            0
#define DDRMC_CR95_SWLVL_RESP_1(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR95_SWLVL_RESP_1_SHIFT))&DDRMC_CR95_SWLVL_RESP_1_MASK)
#define DDRMC_CR95_SWLVL_RESP_2_MASK             0xFF00u
#define DDRMC_CR95_SWLVL_RESP_2_SHIFT            8
#define DDRMC_CR95_SWLVL_RESP_2(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR95_SWLVL_RESP_2_SHIFT))&DDRMC_CR95_SWLVL_RESP_2_MASK)
#define DDRMC_CR95_WRLVL_REQ_MASK                0x10000u
#define DDRMC_CR95_WRLVL_REQ_SHIFT               16
#define DDRMC_CR95_WRLVL_CS_MASK                 0x1000000u
#define DDRMC_CR95_WRLVL_CS_SHIFT                24
/* CR96 Bit Fields */
#define DDRMC_CR96_WLDQSEN_MASK                  0x3Fu
#define DDRMC_CR96_WLDQSEN_SHIFT                 0
#define DDRMC_CR96_WLDQSEN(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_CR96_WLDQSEN_SHIFT))&DDRMC_CR96_WLDQSEN_MASK)
#define DDRMC_CR96_WLMRD_MASK                    0x3F00u
#define DDRMC_CR96_WLMRD_SHIFT                   8
#define DDRMC_CR96_WLMRD(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR96_WLMRD_SHIFT))&DDRMC_CR96_WLMRD_MASK)
#define DDRMC_CR96_WRLVL_EN_MASK                 0x10000u
#define DDRMC_CR96_WRLVL_EN_SHIFT                16
/* CR97 Bit Fields */
#define DDRMC_CR97_WRLVL_REFRESH_INTERVAL_MASK   0xFFFFu
#define DDRMC_CR97_WRLVL_REFRESH_INTERVAL_SHIFT  0
#define DDRMC_CR97_WRLVL_REFRESH_INTERVAL(x)     (((uint32_t)(((uint32_t)(x))<<DDRMC_CR97_WRLVL_REFRESH_INTERVAL_SHIFT))&DDRMC_CR97_WRLVL_REFRESH_INTERVAL_MASK)
#define DDRMC_CR97_WRLVL_ERR_STAT_MASK           0xFF0000u
#define DDRMC_CR97_WRLVL_ERR_STAT_SHIFT          16
#define DDRMC_CR97_WRLVL_ERR_STAT(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR97_WRLVL_ERR_STAT_SHIFT))&DDRMC_CR97_WRLVL_ERR_STAT_MASK)
#define DDRMC_CR97_WRLVL_REG_EN_MASK             0x1000000u
#define DDRMC_CR97_WRLVL_REG_EN_SHIFT            24
/* CR98 Bit Fields */
#define DDRMC_CR98_WRLVL_DL_0_MASK               0xFFFFu
#define DDRMC_CR98_WRLVL_DL_0_SHIFT              0
#define DDRMC_CR98_WRLVL_DL_0(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR98_WRLVL_DL_0_SHIFT))&DDRMC_CR98_WRLVL_DL_0_MASK)
/* CR99 Bit Fields */
#define DDRMC_CR99_WRLVL_DL_1_MASK               0xFFFFu
#define DDRMC_CR99_WRLVL_DL_1_SHIFT              0
#define DDRMC_CR99_WRLVL_DL_1(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR99_WRLVL_DL_1_SHIFT))&DDRMC_CR99_WRLVL_DL_1_MASK)
/* CR100 Bit Fields */
#define DDRMC_CR100_WRLVL_DL_2_MASK              0xFFFFu
#define DDRMC_CR100_WRLVL_DL_2_SHIFT             0
#define DDRMC_CR100_WRLVL_DL_2(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR100_WRLVL_DL_2_SHIFT))&DDRMC_CR100_WRLVL_DL_2_MASK)
/* CR101 Bit Fields */
#define DDRMC_CR101_RDLVL_REQ_MASK               0x1u
#define DDRMC_CR101_RDLVL_REQ_SHIFT              0
#define DDRMC_CR101_RDLVL_GT_REQ_MASK            0x100u
#define DDRMC_CR101_RDLVL_GT_REQ_SHIFT           8
#define DDRMC_CR101_RDLVL_CS_MASK                0x10000u
#define DDRMC_CR101_RDLVL_CS_SHIFT               16
#define DDRMC_CR101_RDLVL_EDGE_MASK              0x1000000u
#define DDRMC_CR101_RDLVL_EDGE_SHIFT             24
/* CR102 Bit Fields */
#define DDRMC_CR102_RDLVL_BGN_DLEN_MASK          0x1u
#define DDRMC_CR102_RDLVL_BGN_DLEN_SHIFT         0
#define DDRMC_CR102_RDLVL_REG_EN_MASK            0x100u
#define DDRMC_CR102_RDLVL_REG_EN_SHIFT           8
#define DDRMC_CR102_RDLVL_GT_REGEN_MASK          0x10000u
#define DDRMC_CR102_RDLVL_GT_REGEN_SHIFT         16
/* CR103 Bit Fields */
#define DDRMC_CR103_RDLVL_BGN_DL0_MASK           0xFFFFu
#define DDRMC_CR103_RDLVL_BGN_DL0_SHIFT          0
#define DDRMC_CR103_RDLVL_BGN_DL0(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR103_RDLVL_BGN_DL0_SHIFT))&DDRMC_CR103_RDLVL_BGN_DL0_MASK)
#define DDRMC_CR103_RDLVL_END_DL0_MASK           0xFFFF0000u
#define DDRMC_CR103_RDLVL_END_DL0_SHIFT          16
#define DDRMC_CR103_RDLVL_END_DL0(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR103_RDLVL_END_DL0_SHIFT))&DDRMC_CR103_RDLVL_END_DL0_MASK)
/* CR104 Bit Fields */
#define DDRMC_CR104_RDLVL_MP_DL0_MASK            0xFFFFu
#define DDRMC_CR104_RDLVL_MP_DL0_SHIFT           0
#define DDRMC_CR104_RDLVL_MP_DL0(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR104_RDLVL_MP_DL0_SHIFT))&DDRMC_CR104_RDLVL_MP_DL0_MASK)
#define DDRMC_CR104_RDLVL_OFF_DL0_MASK           0xFFFF0000u
#define DDRMC_CR104_RDLVL_OFF_DL0_SHIFT          16
#define DDRMC_CR104_RDLVL_OFF_DL0(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR104_RDLVL_OFF_DL0_SHIFT))&DDRMC_CR104_RDLVL_OFF_DL0_MASK)
/* CR105 Bit Fields */
#define DDRMC_CR105_RDLVL_OFF_DIR_0_MASK         0x1u
#define DDRMC_CR105_RDLVL_OFF_DIR_0_SHIFT        0
#define DDRMC_CR105_RDLVL_DL_0_MASK              0xFF00u
#define DDRMC_CR105_RDLVL_DL_0_SHIFT             8
#define DDRMC_CR105_RDLVL_DL_0(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR105_RDLVL_DL_0_SHIFT))&DDRMC_CR105_RDLVL_DL_0_MASK)
/* CR106 Bit Fields */
#define DDRMC_CR106_RDLVL_GTDL_0_MASK            0xFFu
#define DDRMC_CR106_RDLVL_GTDL_0_SHIFT           0
#define DDRMC_CR106_RDLVL_GTDL_0(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR106_RDLVL_GTDL_0_SHIFT))&DDRMC_CR106_RDLVL_GTDL_0_MASK)
/* CR107 Bit Fields */
#define DDRMC_CR107_RDLVL_BGN_DL1_MASK           0xFF0000u
#define DDRMC_CR107_RDLVL_BGN_DL1_SHIFT          16
#define DDRMC_CR107_RDLVL_BGN_DL1(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR107_RDLVL_BGN_DL1_SHIFT))&DDRMC_CR107_RDLVL_BGN_DL1_MASK)
/* CR108 Bit Fields */
#define DDRMC_CR108_RDLVL_END_DL1_MASK           0xFFFFu
#define DDRMC_CR108_RDLVL_END_DL1_SHIFT          0
#define DDRMC_CR108_RDLVL_END_DL1(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR108_RDLVL_END_DL1_SHIFT))&DDRMC_CR108_RDLVL_END_DL1_MASK)
#define DDRMC_CR108_RDLVL_MP_DL1_MASK            0xFFFF0000u
#define DDRMC_CR108_RDLVL_MP_DL1_SHIFT           16
#define DDRMC_CR108_RDLVL_MP_DL1(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR108_RDLVL_MP_DL1_SHIFT))&DDRMC_CR108_RDLVL_MP_DL1_MASK)
/* CR109 Bit Fields */
#define DDRMC_CR109_RDLVL_OFF_DL1_MASK           0xFFFFu
#define DDRMC_CR109_RDLVL_OFF_DL1_SHIFT          0
#define DDRMC_CR109_RDLVL_OFF_DL1(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR109_RDLVL_OFF_DL1_SHIFT))&DDRMC_CR109_RDLVL_OFF_DL1_MASK)
#define DDRMC_CR109_RDLVL_OFF_DIR1_MASK          0x10000u
#define DDRMC_CR109_RDLVL_OFF_DIR1_SHIFT         16
/* CR110 Bit Fields */
#define DDRMC_CR110_RDLVL_DL_1_MASK              0xFFu
#define DDRMC_CR110_RDLVL_DL_1_SHIFT             0
#define DDRMC_CR110_RDLVL_DL_1(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR110_RDLVL_DL_1_SHIFT))&DDRMC_CR110_RDLVL_DL_1_MASK)
#define DDRMC_CR110_RDLVL_GTDL_1_MASK            0xFF0000u
#define DDRMC_CR110_RDLVL_GTDL_1_SHIFT           16
#define DDRMC_CR110_RDLVL_GTDL_1(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR110_RDLVL_GTDL_1_SHIFT))&DDRMC_CR110_RDLVL_GTDL_1_MASK)
/* CR112 Bit Fields */
#define DDRMC_CR112_RDLVL_BGN_DL2_MASK           0xFFFFu
#define DDRMC_CR112_RDLVL_BGN_DL2_SHIFT          0
#define DDRMC_CR112_RDLVL_BGN_DL2(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR112_RDLVL_BGN_DL2_SHIFT))&DDRMC_CR112_RDLVL_BGN_DL2_MASK)
#define DDRMC_CR112_RDLVL_END_DL2_MASK           0xFFFF0000u
#define DDRMC_CR112_RDLVL_END_DL2_SHIFT          16
#define DDRMC_CR112_RDLVL_END_DL2(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR112_RDLVL_END_DL2_SHIFT))&DDRMC_CR112_RDLVL_END_DL2_MASK)
/* CR113 Bit Fields */
#define DDRMC_CR113_RDLVL_MP_DL2_MASK            0xFFFFu
#define DDRMC_CR113_RDLVL_MP_DL2_SHIFT           0
#define DDRMC_CR113_RDLVL_MP_DL2(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR113_RDLVL_MP_DL2_SHIFT))&DDRMC_CR113_RDLVL_MP_DL2_MASK)
#define DDRMC_CR113_RDLVL_OFF_DL2_MASK           0xFFFF0000u
#define DDRMC_CR113_RDLVL_OFF_DL2_SHIFT          16
#define DDRMC_CR113_RDLVL_OFF_DL2(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR113_RDLVL_OFF_DL2_SHIFT))&DDRMC_CR113_RDLVL_OFF_DL2_MASK)
/* CR114 Bit Fields */
#define DDRMC_CR114_RDLVL_OFF_DIR2_MASK          0x1u
#define DDRMC_CR114_RDLVL_OFF_DIR2_SHIFT         0
/* CR115 Bit Fields */
#define DDRMC_CR115_RDLVL_GTDL_2_MASK            0xFFu
#define DDRMC_CR115_RDLVL_GTDL_2_SHIFT           0
#define DDRMC_CR115_RDLVL_GTDL_2(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR115_RDLVL_GTDL_2_SHIFT))&DDRMC_CR115_RDLVL_GTDL_2_MASK)
/* CR117 Bit Fields */
#define DDRMC_CR117_AXI0_R_PRI_MASK              0x3u
#define DDRMC_CR117_AXI0_R_PRI_SHIFT             0
#define DDRMC_CR117_AXI0_R_PRI(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR117_AXI0_R_PRI_SHIFT))&DDRMC_CR117_AXI0_R_PRI_MASK)
#define DDRMC_CR117_AXI0_W_PRI_MASK              0x300u
#define DDRMC_CR117_AXI0_W_PRI_SHIFT             8
#define DDRMC_CR117_AXI0_W_PRI(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR117_AXI0_W_PRI_SHIFT))&DDRMC_CR117_AXI0_W_PRI_MASK)
#define DDRMC_CR117_AXI0_FITYPREG_MASK           0x30000u
#define DDRMC_CR117_AXI0_FITYPREG_SHIFT          16
#define DDRMC_CR117_AXI0_FITYPREG(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR117_AXI0_FITYPREG_SHIFT))&DDRMC_CR117_AXI0_FITYPREG_MASK)
/* CR118 Bit Fields */
#define DDRMC_CR118_AXI1_R_PRI_MASK              0x30000u
#define DDRMC_CR118_AXI1_R_PRI_SHIFT             16
#define DDRMC_CR118_AXI1_R_PRI(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR118_AXI1_R_PRI_SHIFT))&DDRMC_CR118_AXI1_R_PRI_MASK)
#define DDRMC_CR118_AXI1_W_PRI_MASK              0x3000000u
#define DDRMC_CR118_AXI1_W_PRI_SHIFT             24
#define DDRMC_CR118_AXI1_W_PRI(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR118_AXI1_W_PRI_SHIFT))&DDRMC_CR118_AXI1_W_PRI_MASK)
/* CR119 Bit Fields */
#define DDRMC_CR119_AXI1_FITYPREG_MASK           0x3u
#define DDRMC_CR119_AXI1_FITYPREG_SHIFT          0
#define DDRMC_CR119_AXI1_FITYPREG(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR119_AXI1_FITYPREG_SHIFT))&DDRMC_CR119_AXI1_FITYPREG_MASK)
#define DDRMC_CR119_AXI_ASTB_DIS_MASK            0x30000u
#define DDRMC_CR119_AXI_ASTB_DIS_SHIFT           16
#define DDRMC_CR119_AXI_ASTB_DIS(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR119_AXI_ASTB_DIS_SHIFT))&DDRMC_CR119_AXI_ASTB_DIS_MASK)
#define DDRMC_CR119_WRR_LATCTL_MASK              0x1000000u
#define DDRMC_CR119_WRR_LATCTL_SHIFT             24
/* CR120 Bit Fields */
#define DDRMC_CR120_W_RR_WSHR_MASK               0x1u
#define DDRMC_CR120_W_RR_WSHR_SHIFT              0
#define DDRMC_CR120_WRR_ERR_MASK                 0xF00u
#define DDRMC_CR120_WRR_ERR_SHIFT                8
#define DDRMC_CR120_WRR_ERR(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR120_WRR_ERR_SHIFT))&DDRMC_CR120_WRR_ERR_MASK)
#define DDRMC_CR120_AXI0_PRI0_RPRI_MASK          0xF0000u
#define DDRMC_CR120_AXI0_PRI0_RPRI_SHIFT         16
#define DDRMC_CR120_AXI0_PRI0_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR120_AXI0_PRI0_RPRI_SHIFT))&DDRMC_CR120_AXI0_PRI0_RPRI_MASK)
#define DDRMC_CR120_AXI0_PRI1_RPRI_MASK          0xF000000u
#define DDRMC_CR120_AXI0_PRI1_RPRI_SHIFT         24
#define DDRMC_CR120_AXI0_PRI1_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR120_AXI0_PRI1_RPRI_SHIFT))&DDRMC_CR120_AXI0_PRI1_RPRI_MASK)
/* CR121 Bit Fields */
#define DDRMC_CR121_AXI0_PRI2_RPRI_MASK          0xFu
#define DDRMC_CR121_AXI0_PRI2_RPRI_SHIFT         0
#define DDRMC_CR121_AXI0_PRI2_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR121_AXI0_PRI2_RPRI_SHIFT))&DDRMC_CR121_AXI0_PRI2_RPRI_MASK)
#define DDRMC_CR121_AXI0_PRI3_RPRI_MASK          0xF00u
#define DDRMC_CR121_AXI0_PRI3_RPRI_SHIFT         8
#define DDRMC_CR121_AXI0_PRI3_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR121_AXI0_PRI3_RPRI_SHIFT))&DDRMC_CR121_AXI0_PRI3_RPRI_MASK)
#define DDRMC_CR121_AXI0_P_ODR_MASK              0x10000u
#define DDRMC_CR121_AXI0_P_ODR_SHIFT             16
/* CR122 Bit Fields */
#define DDRMC_CR122_AXI0_PRIRLX_MASK             0x3FFu
#define DDRMC_CR122_AXI0_PRIRLX_SHIFT            0
#define DDRMC_CR122_AXI0_PRIRLX(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR122_AXI0_PRIRLX_SHIFT))&DDRMC_CR122_AXI0_PRIRLX_MASK)
#define DDRMC_CR122_AXI1_PRI0_RPRI_MASK          0xF0000u
#define DDRMC_CR122_AXI1_PRI0_RPRI_SHIFT         16
#define DDRMC_CR122_AXI1_PRI0_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR122_AXI1_PRI0_RPRI_SHIFT))&DDRMC_CR122_AXI1_PRI0_RPRI_MASK)
#define DDRMC_CR122_AXI1_PRI1_RPRI_MASK          0xF000000u
#define DDRMC_CR122_AXI1_PRI1_RPRI_SHIFT         24
#define DDRMC_CR122_AXI1_PRI1_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR122_AXI1_PRI1_RPRI_SHIFT))&DDRMC_CR122_AXI1_PRI1_RPRI_MASK)
/* CR123 Bit Fields */
#define DDRMC_CR123_AXI1_PRI2_RPRI_MASK          0xFu
#define DDRMC_CR123_AXI1_PRI2_RPRI_SHIFT         0
#define DDRMC_CR123_AXI1_PRI2_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR123_AXI1_PRI2_RPRI_SHIFT))&DDRMC_CR123_AXI1_PRI2_RPRI_MASK)
#define DDRMC_CR123_AXI1_PRI3_RPRI_MASK          0xF00u
#define DDRMC_CR123_AXI1_PRI3_RPRI_SHIFT         8
#define DDRMC_CR123_AXI1_PRI3_RPRI(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR123_AXI1_PRI3_RPRI_SHIFT))&DDRMC_CR123_AXI1_PRI3_RPRI_MASK)
#define DDRMC_CR123_AXI1_P_ODR_MASK              0x10000u
#define DDRMC_CR123_AXI1_P_ODR_SHIFT             16
/* CR124 Bit Fields */
#define DDRMC_CR124_AXI1_PRIRLX_MASK             0x3FFu
#define DDRMC_CR124_AXI1_PRIRLX_SHIFT            0
#define DDRMC_CR124_AXI1_PRIRLX(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR124_AXI1_PRIRLX_SHIFT))&DDRMC_CR124_AXI1_PRIRLX_MASK)
#define DDRMC_CR124_CKE_STAT_MASK                0x30000u
#define DDRMC_CR124_CKE_STAT_SHIFT               16
#define DDRMC_CR124_CKE_STAT(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR124_CKE_STAT_SHIFT))&DDRMC_CR124_CKE_STAT_MASK)
#define DDRMC_CR124_MEM_RST_VAL_MASK             0x1000000u
#define DDRMC_CR124_MEM_RST_VAL_SHIFT            24
/* CR125 Bit Fields */
#define DDRMC_CR125_DLL_RST_DELAY_MASK           0xFFFFu
#define DDRMC_CR125_DLL_RST_DELAY_SHIFT          0
#define DDRMC_CR125_DLL_RST_DELAY(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR125_DLL_RST_DELAY_SHIFT))&DDRMC_CR125_DLL_RST_DELAY_MASK)
#define DDRMC_CR125_DLL_RST_ADJ_DLY_MASK         0xFF0000u
#define DDRMC_CR125_DLL_RST_ADJ_DLY_SHIFT        16
#define DDRMC_CR125_DLL_RST_ADJ_DLY(x)           (((uint32_t)(((uint32_t)(x))<<DDRMC_CR125_DLL_RST_ADJ_DLY_SHIFT))&DDRMC_CR125_DLL_RST_ADJ_DLY_MASK)
#define DDRMC_CR125_PHY_WRLAT_MASK               0x1F000000u
#define DDRMC_CR125_PHY_WRLAT_SHIFT              24
#define DDRMC_CR125_PHY_WRLAT(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR125_PHY_WRLAT_SHIFT))&DDRMC_CR125_PHY_WRLAT_MASK)
/* CR126 Bit Fields */
#define DDRMC_CR126_UP_ERR_STAT_MASK             0x7Fu
#define DDRMC_CR126_UP_ERR_STAT_SHIFT            0
#define DDRMC_CR126_UP_ERR_STAT(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR126_UP_ERR_STAT_SHIFT))&DDRMC_CR126_UP_ERR_STAT_MASK)
#define DDRMC_CR126_PHY_RDLAT_MASK               0x3F00u
#define DDRMC_CR126_PHY_RDLAT_SHIFT              8
#define DDRMC_CR126_PHY_RDLAT(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR126_PHY_RDLAT_SHIFT))&DDRMC_CR126_PHY_RDLAT_MASK)
#define DDRMC_CR126_PHY_RDDATA_EN_MASK           0x3F000000u
#define DDRMC_CR126_PHY_RDDATA_EN_SHIFT          24
#define DDRMC_CR126_PHY_RDDATA_EN(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR126_PHY_RDDATA_EN_SHIFT))&DDRMC_CR126_PHY_RDDATA_EN_MASK)
/* CR127 Bit Fields */
#define DDRMC_CR127_DRAM_CK_DI_MASK              0x1u
#define DDRMC_CR127_DRAM_CK_DI_SHIFT             0
/* CR131 Bit Fields */
#define DDRMC_CR131_PHYUPD_INT_MASK              0xFFFFFFFFu
#define DDRMC_CR131_PHYUPD_INT_SHIFT             0
#define DDRMC_CR131_PHYUPD_INT(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_CR131_PHYUPD_INT_SHIFT))&DDRMC_CR131_PHYUPD_INT_MASK)
/* CR132 Bit Fields */
#define DDRMC_CR132_RDLAT_ADJ_MASK               0x3Fu
#define DDRMC_CR132_RDLAT_ADJ_SHIFT              0
#define DDRMC_CR132_RDLAT_ADJ(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR132_RDLAT_ADJ_SHIFT))&DDRMC_CR132_RDLAT_ADJ_MASK)
#define DDRMC_CR132_WRLAT_ADJ_MASK               0x1F00u
#define DDRMC_CR132_WRLAT_ADJ_SHIFT              8
#define DDRMC_CR132_WRLAT_ADJ(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR132_WRLAT_ADJ_SHIFT))&DDRMC_CR132_WRLAT_ADJ_MASK)
/* CR137 Bit Fields */
#define DDRMC_CR137_PHYCTL_DL_MASK               0xF0000u
#define DDRMC_CR137_PHYCTL_DL_SHIFT              16
#define DDRMC_CR137_PHYCTL_DL(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR137_PHYCTL_DL_SHIFT))&DDRMC_CR137_PHYCTL_DL_MASK)
/* CR138 Bit Fields */
#define DDRMC_CR138_PHYDRAM_CK_DIS_MASK          0xFu
#define DDRMC_CR138_PHYDRAM_CK_DIS_SHIFT         0
#define DDRMC_CR138_PHYDRAM_CK_DIS(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR138_PHYDRAM_CK_DIS_SHIFT))&DDRMC_CR138_PHYDRAM_CK_DIS_MASK)
#define DDRMC_CR138_PHYDRAM_CK_EN_MASK           0x700u
#define DDRMC_CR138_PHYDRAM_CK_EN_SHIFT          8
#define DDRMC_CR138_PHYDRAM_CK_EN(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR138_PHYDRAM_CK_EN_SHIFT))&DDRMC_CR138_PHYDRAM_CK_EN_MASK)
#define DDRMC_CR138_PHY_WRLV_MXDL_MASK           0xFFFF0000u
#define DDRMC_CR138_PHY_WRLV_MXDL_SHIFT          16
#define DDRMC_CR138_PHY_WRLV_MXDL(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR138_PHY_WRLV_MXDL_SHIFT))&DDRMC_CR138_PHY_WRLV_MXDL_MASK)
/* CR139 Bit Fields */
#define DDRMC_CR139_PHY_WRLV_EN_MASK             0xFFu
#define DDRMC_CR139_PHY_WRLV_EN_SHIFT            0
#define DDRMC_CR139_PHY_WRLV_EN(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR139_PHY_WRLV_EN_SHIFT))&DDRMC_CR139_PHY_WRLV_EN_MASK)
#define DDRMC_CR139_PHY_WRLV_DLL_MASK            0xFF00u
#define DDRMC_CR139_PHY_WRLV_DLL_SHIFT           8
#define DDRMC_CR139_PHY_WRLV_DLL(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR139_PHY_WRLV_DLL_SHIFT))&DDRMC_CR139_PHY_WRLV_DLL_MASK)
#define DDRMC_CR139_PHY_WRLV_LOAD_MASK           0xFF0000u
#define DDRMC_CR139_PHY_WRLV_LOAD_SHIFT          16
#define DDRMC_CR139_PHY_WRLV_LOAD(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR139_PHY_WRLV_LOAD_SHIFT))&DDRMC_CR139_PHY_WRLV_LOAD_MASK)
#define DDRMC_CR139_PHY_WRLV_RESPLAT_MASK        0xFF000000u
#define DDRMC_CR139_PHY_WRLV_RESPLAT_SHIFT       24
#define DDRMC_CR139_PHY_WRLV_RESPLAT(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_CR139_PHY_WRLV_RESPLAT_SHIFT))&DDRMC_CR139_PHY_WRLV_RESPLAT_MASK)
/* CR140 Bit Fields */
#define DDRMC_CR140_PHY_WRLV_WW_MASK             0x3FFu
#define DDRMC_CR140_PHY_WRLV_WW_SHIFT            0
#define DDRMC_CR140_PHY_WRLV_WW(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR140_PHY_WRLV_WW_SHIFT))&DDRMC_CR140_PHY_WRLV_WW_MASK)
/* CR141 Bit Fields */
#define DDRMC_CR141_PHY_WRLV_RESP_MASK           0xFFFFFFFFu
#define DDRMC_CR141_PHY_WRLV_RESP_SHIFT          0
#define DDRMC_CR141_PHY_WRLV_RESP(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR141_PHY_WRLV_RESP_SHIFT))&DDRMC_CR141_PHY_WRLV_RESP_MASK)
/* CR142 Bit Fields */
#define DDRMC_CR142_PHY_WRLV_MAX_MASK            0xFFFFFFFFu
#define DDRMC_CR142_PHY_WRLV_MAX_SHIFT           0
#define DDRMC_CR142_PHY_WRLV_MAX(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR142_PHY_WRLV_MAX_SHIFT))&DDRMC_CR142_PHY_WRLV_MAX_MASK)
/* CR143 Bit Fields */
#define DDRMC_CR143_RDLV_MXDL_MASK               0xFFFFu
#define DDRMC_CR143_RDLV_MXDL_SHIFT              0
#define DDRMC_CR143_RDLV_MXDL(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_CR143_RDLV_MXDL_SHIFT))&DDRMC_CR143_RDLV_MXDL_MASK)
#define DDRMC_CR143_RDLV_GAT_MXDL_MASK           0xFFFF0000u
#define DDRMC_CR143_RDLV_GAT_MXDL_SHIFT          16
#define DDRMC_CR143_RDLV_GAT_MXDL(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR143_RDLV_GAT_MXDL_SHIFT))&DDRMC_CR143_RDLV_GAT_MXDL_MASK)
/* CR144 Bit Fields */
#define DDRMC_CR144_PHY_RDLV_EN_MASK             0xFFu
#define DDRMC_CR144_PHY_RDLV_EN_SHIFT            0
#define DDRMC_CR144_PHY_RDLV_EN(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR144_PHY_RDLV_EN_SHIFT))&DDRMC_CR144_PHY_RDLV_EN_MASK)
#define DDRMC_CR144_PHY_RDLV_DLL_MASK            0xFF00u
#define DDRMC_CR144_PHY_RDLV_DLL_SHIFT           8
#define DDRMC_CR144_PHY_RDLV_DLL(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR144_PHY_RDLV_DLL_SHIFT))&DDRMC_CR144_PHY_RDLV_DLL_MASK)
#define DDRMC_CR144_PHY_RDLV_LOAD_MASK           0xFF0000u
#define DDRMC_CR144_PHY_RDLV_LOAD_SHIFT          16
#define DDRMC_CR144_PHY_RDLV_LOAD(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR144_PHY_RDLV_LOAD_SHIFT))&DDRMC_CR144_PHY_RDLV_LOAD_MASK)
#define DDRMC_CR144_PHY_RDLVL_RES_MASK           0xFF000000u
#define DDRMC_CR144_PHY_RDLVL_RES_SHIFT          24
#define DDRMC_CR144_PHY_RDLVL_RES(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR144_PHY_RDLVL_RES_SHIFT))&DDRMC_CR144_PHY_RDLVL_RES_MASK)
/* CR145 Bit Fields */
#define DDRMC_CR145_PHY_RDLV_RR_MASK             0x3FFu
#define DDRMC_CR145_PHY_RDLV_RR_SHIFT            0
#define DDRMC_CR145_PHY_RDLV_RR(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR145_PHY_RDLV_RR_SHIFT))&DDRMC_CR145_PHY_RDLV_RR_MASK)
/* CR146 Bit Fields */
#define DDRMC_CR146_PHY_RDLVL_RESP_MASK          0xFFFFFFFFu
#define DDRMC_CR146_PHY_RDLVL_RESP_SHIFT         0
#define DDRMC_CR146_PHY_RDLVL_RESP(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR146_PHY_RDLVL_RESP_SHIFT))&DDRMC_CR146_PHY_RDLVL_RESP_MASK)
/* CR147 Bit Fields */
#define DDRMC_CR147_RDLV_RESP_MASK_MASK          0xFFFFFu
#define DDRMC_CR147_RDLV_RESP_MASK_SHIFT         0
#define DDRMC_CR147_RDLV_RESP_MASK(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_CR147_RDLV_RESP_MASK_SHIFT))&DDRMC_CR147_RDLV_RESP_MASK_MASK)
/* CR148 Bit Fields */
#define DDRMC_CR148_RDLV_GATE_RESP_MASK_MASK     0xFFFFFu
#define DDRMC_CR148_RDLV_GATE_RESP_MASK_SHIFT    0
#define DDRMC_CR148_RDLV_GATE_RESP_MASK(x)       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR148_RDLV_GATE_RESP_MASK_SHIFT))&DDRMC_CR148_RDLV_GATE_RESP_MASK_MASK)
#define DDRMC_CR148_RDLVL_EN_MASK                0x1000000u
#define DDRMC_CR148_RDLVL_EN_SHIFT               24
/* CR149 Bit Fields */
#define DDRMC_CR149_RDLVL_GATE_EN_MASK           0x1u
#define DDRMC_CR149_RDLVL_GATE_EN_SHIFT          0
#define DDRMC_CR149_RDLV_GT_CHKENS_MASK          0x100u
#define DDRMC_CR149_RDLV_GT_CHKENS_SHIFT         8
/* CR150 Bit Fields */
#define DDRMC_CR150_PHY_RDLVLMAX_MASK            0xFFFFFFFFu
#define DDRMC_CR150_PHY_RDLVLMAX_SHIFT           0
#define DDRMC_CR150_PHY_RDLVLMAX(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR150_PHY_RDLVLMAX_SHIFT))&DDRMC_CR150_PHY_RDLVLMAX_MASK)
/* CR151 Bit Fields */
#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT_MASK       0xFu
#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT_SHIFT      0
#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(x)         (((uint32_t)(((uint32_t)(x))<<DDRMC_CR151_RDLVL_DQ_ZERO_CNT_SHIFT))&DDRMC_CR151_RDLVL_DQ_ZERO_CNT_MASK)
#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT_MASK    0xF00u
#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT_SHIFT   8
#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(x)      (((uint32_t)(((uint32_t)(x))<<DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT_SHIFT))&DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT_MASK)
#define DDRMC_CR151_RDLV_ERR_STA_MASK            0x3FFF0000u
#define DDRMC_CR151_RDLV_ERR_STA_SHIFT           16
#define DDRMC_CR151_RDLV_ERR_STA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_CR151_RDLV_ERR_STA_SHIFT))&DDRMC_CR151_RDLV_ERR_STA_MASK)
/* CR152 Bit Fields */
#define DDRMC_CR152_RDLV_REFINT_MASK             0xFFFFu
#define DDRMC_CR152_RDLV_REFINT_SHIFT            0
#define DDRMC_CR152_RDLV_REFINT(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR152_RDLV_REFINT_SHIFT))&DDRMC_CR152_RDLV_REFINT_MASK)
#define DDRMC_CR152_RDLV_GTREFINT_MASK           0xFFFF0000u
#define DDRMC_CR152_RDLV_GTREFINT_SHIFT          16
#define DDRMC_CR152_RDLV_GTREFINT(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR152_RDLV_GTREFINT_SHIFT))&DDRMC_CR152_RDLV_GTREFINT_MASK)
/* CR153 Bit Fields */
#define DDRMC_CR153_EN_1T_TMG_MASK               0x100u
#define DDRMC_CR153_EN_1T_TMG_SHIFT              8
/* CR154 Bit Fields */
#define DDRMC_CR154_PAD_ZQ_CMP_OUT_SMP_MASK      0x3000u
#define DDRMC_CR154_PAD_ZQ_CMP_OUT_SMP_SHIFT     12
#define DDRMC_CR154_PAD_ZQ_CMP_OUT_SMP(x)        (((uint32_t)(((uint32_t)(x))<<DDRMC_CR154_PAD_ZQ_CMP_OUT_SMP_SHIFT))&DDRMC_CR154_PAD_ZQ_CMP_OUT_SMP_MASK)
#define DDRMC_CR154_PAD_ZQ_HW_FOR_MASK           0x4000u
#define DDRMC_CR154_PAD_ZQ_HW_FOR_SHIFT          14
#define DDRMC_CR154_PAD_ZQ_MODE_MASK             0x600000u
#define DDRMC_CR154_PAD_ZQ_MODE_SHIFT            21
#define DDRMC_CR154_PAD_ZQ_MODE(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR154_PAD_ZQ_MODE_SHIFT))&DDRMC_CR154_PAD_ZQ_MODE_MASK)
#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER_MASK 0xF8000000u
#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER_SHIFT 27
#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(x) (((uint32_t)(((uint32_t)(x))<<DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER_SHIFT))&DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER_MASK)
/* CR155 Bit Fields */
#define DDRMC_CR155_PAD_ODT_BYTE1_MASK           0x7u
#define DDRMC_CR155_PAD_ODT_BYTE1_SHIFT          0
#define DDRMC_CR155_PAD_ODT_BYTE1(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR155_PAD_ODT_BYTE1_SHIFT))&DDRMC_CR155_PAD_ODT_BYTE1_MASK)
#define DDRMC_CR155_PAD_ODT_BYTE0_MASK           0x38u
#define DDRMC_CR155_PAD_ODT_BYTE0_SHIFT          3
#define DDRMC_CR155_PAD_ODT_BYTE0(x)             (((uint32_t)(((uint32_t)(x))<<DDRMC_CR155_PAD_ODT_BYTE0_SHIFT))&DDRMC_CR155_PAD_ODT_BYTE0_MASK)
#define DDRMC_CR155_AXI0_COBUF_MASK              0x100u
#define DDRMC_CR155_AXI0_COBUF_SHIFT             8
#define DDRMC_CR155_AXI1_COBUF_MASK              0x200u
#define DDRMC_CR155_AXI1_COBUF_SHIFT             9
#define DDRMC_CR155_AXI0_AWCACHE_MASK            0x400u
#define DDRMC_CR155_AXI0_AWCACHE_SHIFT           10
#define DDRMC_CR155_AXI1_AWCACHE_MASK            0x800u
#define DDRMC_CR155_AXI1_AWCACHE_SHIFT           11
#define DDRMC_CR155_PAD_IBE_SEL0_MASK            0x10000u
#define DDRMC_CR155_PAD_IBE_SEL0_SHIFT           16
#define DDRMC_CR155_PAD_IBE_SEL1_MASK            0x20000u
#define DDRMC_CR155_PAD_IBE_SEL1_SHIFT           17
#define DDRMC_CR155_PAD_IBE0_MASK                0x40000u
#define DDRMC_CR155_PAD_IBE0_SHIFT               18
#define DDRMC_CR155_PAD_IBE1_MASK                0x80000u
#define DDRMC_CR155_PAD_IBE1_SHIFT               19
/* CR156 Bit Fields */
#define DDRMC_CR156_PAD_ZQ_HW_PU_RES_MASK        0x3Eu
#define DDRMC_CR156_PAD_ZQ_HW_PU_RES_SHIFT       1
#define DDRMC_CR156_PAD_ZQ_HW_PU_RES(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_CR156_PAD_ZQ_HW_PU_RES_SHIFT))&DDRMC_CR156_PAD_ZQ_HW_PU_RES_MASK)
#define DDRMC_CR156_PAD_ZQ_HW_PD_RES_MASK        0x7C0u
#define DDRMC_CR156_PAD_ZQ_HW_PD_RES_SHIFT       6
#define DDRMC_CR156_PAD_ZQ_HW_PD_RES(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_CR156_PAD_ZQ_HW_PD_RES_SHIFT))&DDRMC_CR156_PAD_ZQ_HW_PD_RES_MASK)
#define DDRMC_CR156_PAD_ZQ_HW_IN_PROG_MASK       0x1000u
#define DDRMC_CR156_PAD_ZQ_HW_IN_PROG_SHIFT      12
/* CR157 Bit Fields */
#define DDRMC_CR157_PAD_IBE_MASK                 0x3u
#define DDRMC_CR157_PAD_IBE_SHIFT                0
#define DDRMC_CR157_PAD_IBE(x)                   (((uint32_t)(((uint32_t)(x))<<DDRMC_CR157_PAD_IBE_SHIFT))&DDRMC_CR157_PAD_IBE_MASK)
#define DDRMC_CR157_RD_PEND_UFLO_MASK            0x4u
#define DDRMC_CR157_RD_PEND_UFLO_SHIFT           2
#define DDRMC_CR157_RD_PEND_OFLO_MASK            0x8u
#define DDRMC_CR157_RD_PEND_OFLO_SHIFT           3
#define DDRMC_CR157_RD_PEND_CNT_MASK             0xFF00u
#define DDRMC_CR157_RD_PEND_CNT_SHIFT            8
#define DDRMC_CR157_RD_PEND_CNT(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_CR157_RD_PEND_CNT_SHIFT))&DDRMC_CR157_RD_PEND_CNT_MASK)
/* CR158 Bit Fields */
#define DDRMC_CR158_TWR_MASK                     0x3Fu
#define DDRMC_CR158_TWR_SHIFT                    0
#define DDRMC_CR158_TWR(x)                       (((uint32_t)(((uint32_t)(x))<<DDRMC_CR158_TWR_SHIFT))&DDRMC_CR158_TWR_MASK)
/* CR161 Bit Fields */
#define DDRMC_CR161_TODTH_WR_MASK                0xFu
#define DDRMC_CR161_TODTH_WR_SHIFT               0
#define DDRMC_CR161_TODTH_WR(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR161_TODTH_WR_SHIFT))&DDRMC_CR161_TODTH_WR_MASK)
#define DDRMC_CR161_TODTH_RD_MASK                0xF00u
#define DDRMC_CR161_TODTH_RD_SHIFT               8
#define DDRMC_CR161_TODTH_RD(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_CR161_TODTH_RD_SHIFT))&DDRMC_CR161_TODTH_RD_MASK)
#define DDRMC_CR161_ODT_EN_MASK                  0x10000u
#define DDRMC_CR161_ODT_EN_SHIFT                 16
/* PHY00 Bit Fields */
#define DDRMC_PHY00_OE_END_MASK                  0x7u
#define DDRMC_PHY00_OE_END_SHIFT                 0
#define DDRMC_PHY00_OE_END(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY00_OE_END_SHIFT))&DDRMC_PHY00_OE_END_MASK)
#define DDRMC_PHY00_OE_START_MASK                0x70u
#define DDRMC_PHY00_OE_START_SHIFT               4
#define DDRMC_PHY00_OE_START(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY00_OE_START_SHIFT))&DDRMC_PHY00_OE_START_MASK)
#define DDRMC_PHY00_TSEL_END_MASK                0xF00u
#define DDRMC_PHY00_TSEL_END_SHIFT               8
#define DDRMC_PHY00_TSEL_END(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY00_TSEL_END_SHIFT))&DDRMC_PHY00_TSEL_END_MASK)
#define DDRMC_PHY00_TSEL_START_MASK              0xF000u
#define DDRMC_PHY00_TSEL_START_SHIFT             12
#define DDRMC_PHY00_TSEL_START(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY00_TSEL_START_SHIFT))&DDRMC_PHY00_TSEL_START_MASK)
/* PHY01 Bit Fields */
#define DDRMC_PHY01_OE_END_MASK                  0xFu
#define DDRMC_PHY01_OE_END_SHIFT                 0
#define DDRMC_PHY01_OE_END(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY01_OE_END_SHIFT))&DDRMC_PHY01_OE_END_MASK)
#define DDRMC_PHY01_OE_START_MASK                0xF0u
#define DDRMC_PHY01_OE_START_SHIFT               4
#define DDRMC_PHY01_OE_START(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY01_OE_START_SHIFT))&DDRMC_PHY01_OE_START_MASK)
#define DDRMC_PHY01_TSEL_END_MASK                0xF00u
#define DDRMC_PHY01_TSEL_END_SHIFT               8
#define DDRMC_PHY01_TSEL_END(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY01_TSEL_END_SHIFT))&DDRMC_PHY01_TSEL_END_MASK)
#define DDRMC_PHY01_TSEL_START_MASK              0xF000u
#define DDRMC_PHY01_TSEL_START_SHIFT             12
#define DDRMC_PHY01_TSEL_START(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY01_TSEL_START_SHIFT))&DDRMC_PHY01_TSEL_START_MASK)
/* PHY02 Bit Fields */
#define DDRMC_PHY02_Gate_CFG_MASK                0x7u
#define DDRMC_PHY02_Gate_CFG_SHIFT               0
#define DDRMC_PHY02_Gate_CFG(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY02_Gate_CFG_SHIFT))&DDRMC_PHY02_Gate_CFG_MASK)
#define DDRMC_PHY02_RD_DL_SET_MASK               0x380000u
#define DDRMC_PHY02_RD_DL_SET_SHIFT              19
#define DDRMC_PHY02_RD_DL_SET(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY02_RD_DL_SET_SHIFT))&DDRMC_PHY02_RD_DL_SET_MASK)
#define DDRMC_PHY02_WRLVL_CLKDL_MASK             0x2000000u
#define DDRMC_PHY02_WRLVL_CLKDL_SHIFT            25
#define DDRMC_PHY02_SW_HALF_CYCLE_SHIFT_MASK     0x8000000u
#define DDRMC_PHY02_SW_HALF_CYCLE_SHIFT_SHIFT    27
#define DDRMC_PHY02_EN_HALF_CAS_MASK             0x20000000u
#define DDRMC_PHY02_EN_HALF_CAS_SHIFT            29
/* PHY03 Bit Fields */
#define DDRMC_PHY03_DLL_START_POINT_MASK         0xFFu
#define DDRMC_PHY03_DLL_START_POINT_SHIFT        0
#define DDRMC_PHY03_DLL_START_POINT(x)           (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY03_DLL_START_POINT_SHIFT))&DDRMC_PHY03_DLL_START_POINT_MASK)
/* PHY04 Bit Fields */
#define DDRMC_PHY04_DLL_WRITE_DL_MASK            0x7F00u
#define DDRMC_PHY04_DLL_WRITE_DL_SHIFT           8
#define DDRMC_PHY04_DLL_WRITE_DL(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY04_DLL_WRITE_DL_SHIFT))&DDRMC_PHY04_DLL_WRITE_DL_MASK)
/* PHY10 Bit Fields */
#define DDRMC_PHY10_LPBK_START_MASK              0x1u
#define DDRMC_PHY10_LPBK_START_SHIFT             0
#define DDRMC_PHY10_LPBK_STATUS_MASK             0x2u
#define DDRMC_PHY10_LPBK_STATUS_SHIFT            1
#define DDRMC_PHY10_LPBK_DM_DATA_MASK            0xF0u
#define DDRMC_PHY10_LPBK_DM_DATA_SHIFT           4
#define DDRMC_PHY10_LPBK_DM_DATA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY10_LPBK_DM_DATA_SHIFT))&DDRMC_PHY10_LPBK_DM_DATA_MASK)
#define DDRMC_PHY10_LPBK_DQ_DATA_MASK            0xFFFF00u
#define DDRMC_PHY10_LPBK_DQ_DATA_SHIFT           8
#define DDRMC_PHY10_LPBK_DQ_DATA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY10_LPBK_DQ_DATA_SHIFT))&DDRMC_PHY10_LPBK_DQ_DATA_MASK)
#define DDRMC_PHY10_DQS_ERROR_STATUS_MASK        0x1000000u
#define DDRMC_PHY10_DQS_ERROR_STATUS_SHIFT       24
/* PHY11 Bit Fields */
#define DDRMC_PHY11_DLL_LOCK_MASK                0x1u
#define DDRMC_PHY11_DLL_LOCK_SHIFT               0
#define DDRMC_PHY11_DLL_LOCK_VALUE_MASK          0xFF00u
#define DDRMC_PHY11_DLL_LOCK_VALUE_SHIFT         8
#define DDRMC_PHY11_DLL_LOCK_VALUE(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY11_DLL_LOCK_VALUE_SHIFT))&DDRMC_PHY11_DLL_LOCK_VALUE_MASK)
#define DDRMC_PHY11_LOCK_MASK                    0xFF0000u
#define DDRMC_PHY11_LOCK_SHIFT                   16
#define DDRMC_PHY11_LOCK(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY11_LOCK_SHIFT))&DDRMC_PHY11_LOCK_MASK)
#define DDRMC_PHY11_DLL_UNLOCK_VALUE_MASK        0xFF000000u
#define DDRMC_PHY11_DLL_UNLOCK_VALUE_SHIFT       24
#define DDRMC_PHY11_DLL_UNLOCK_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY11_DLL_UNLOCK_VALUE_SHIFT))&DDRMC_PHY11_DLL_UNLOCK_VALUE_MASK)
/* PHY12 Bit Fields */
#define DDRMC_PHY12_DLL_LOCK_MASK                0x1u
#define DDRMC_PHY12_DLL_LOCK_SHIFT               0
#define DDRMC_PHY12_DEC_OUT_RD_MASK              0xFEu
#define DDRMC_PHY12_DEC_OUT_RD_SHIFT             1
#define DDRMC_PHY12_DEC_OUT_RD(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY12_DEC_OUT_RD_SHIFT))&DDRMC_PHY12_DEC_OUT_RD_MASK)
#define DDRMC_PHY12_DEC_OUT_WR_MASK              0xFF0000u
#define DDRMC_PHY12_DEC_OUT_WR_SHIFT             16
#define DDRMC_PHY12_DEC_OUT_WR(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY12_DEC_OUT_WR_SHIFT))&DDRMC_PHY12_DEC_OUT_WR_MASK)
/* PHY13 Bit Fields */
#define DDRMC_PHY13_DEC_OUT_WR_DQS_MASK          0xFFFFu
#define DDRMC_PHY13_DEC_OUT_WR_DQS_SHIFT         0
#define DDRMC_PHY13_DEC_OUT_WR_DQS(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY13_DEC_OUT_WR_DQS_SHIFT))&DDRMC_PHY13_DEC_OUT_WR_DQS_MASK)
/* PHY16 Bit Fields */
#define DDRMC_PHY16_OE_END_MASK                  0x7u
#define DDRMC_PHY16_OE_END_SHIFT                 0
#define DDRMC_PHY16_OE_END(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY16_OE_END_SHIFT))&DDRMC_PHY16_OE_END_MASK)
#define DDRMC_PHY16_OE_START_MASK                0x70u
#define DDRMC_PHY16_OE_START_SHIFT               4
#define DDRMC_PHY16_OE_START(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY16_OE_START_SHIFT))&DDRMC_PHY16_OE_START_MASK)
#define DDRMC_PHY16_TSEL_END_MASK                0xF00u
#define DDRMC_PHY16_TSEL_END_SHIFT               8
#define DDRMC_PHY16_TSEL_END(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY16_TSEL_END_SHIFT))&DDRMC_PHY16_TSEL_END_MASK)
#define DDRMC_PHY16_TSEL_START_MASK              0xF000u
#define DDRMC_PHY16_TSEL_START_SHIFT             12
#define DDRMC_PHY16_TSEL_START(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY16_TSEL_START_SHIFT))&DDRMC_PHY16_TSEL_START_MASK)
/* PHY17 Bit Fields */
#define DDRMC_PHY17_OE_END_MASK                  0xFu
#define DDRMC_PHY17_OE_END_SHIFT                 0
#define DDRMC_PHY17_OE_END(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY17_OE_END_SHIFT))&DDRMC_PHY17_OE_END_MASK)
#define DDRMC_PHY17_OE_START_MASK                0xF0u
#define DDRMC_PHY17_OE_START_SHIFT               4
#define DDRMC_PHY17_OE_START(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY17_OE_START_SHIFT))&DDRMC_PHY17_OE_START_MASK)
#define DDRMC_PHY17_TSEL_END_MASK                0xF00u
#define DDRMC_PHY17_TSEL_END_SHIFT               8
#define DDRMC_PHY17_TSEL_END(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY17_TSEL_END_SHIFT))&DDRMC_PHY17_TSEL_END_MASK)
#define DDRMC_PHY17_TSEL_START_MASK              0xF000u
#define DDRMC_PHY17_TSEL_START_SHIFT             12
#define DDRMC_PHY17_TSEL_START(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY17_TSEL_START_SHIFT))&DDRMC_PHY17_TSEL_START_MASK)
/* PHY18 Bit Fields */
#define DDRMC_PHY18_Gate_CFG_MASK                0x7u
#define DDRMC_PHY18_Gate_CFG_SHIFT               0
#define DDRMC_PHY18_Gate_CFG(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY18_Gate_CFG_SHIFT))&DDRMC_PHY18_Gate_CFG_MASK)
#define DDRMC_PHY18_RD_DL_SET_MASK               0x380000u
#define DDRMC_PHY18_RD_DL_SET_SHIFT              19
#define DDRMC_PHY18_RD_DL_SET(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY18_RD_DL_SET_SHIFT))&DDRMC_PHY18_RD_DL_SET_MASK)
#define DDRMC_PHY18_WRLVL_CLKDL_MASK             0x2000000u
#define DDRMC_PHY18_WRLVL_CLKDL_SHIFT            25
#define DDRMC_PHY18_SW_HALF_CYCLE_SHIFT_MASK     0x8000000u
#define DDRMC_PHY18_SW_HALF_CYCLE_SHIFT_SHIFT    27
#define DDRMC_PHY18_EN_HALF_CAS_MASK             0x20000000u
#define DDRMC_PHY18_EN_HALF_CAS_SHIFT            29
/* PHY19 Bit Fields */
#define DDRMC_PHY19_DLL_START_POINT_MASK         0xFFu
#define DDRMC_PHY19_DLL_START_POINT_SHIFT        0
#define DDRMC_PHY19_DLL_START_POINT(x)           (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY19_DLL_START_POINT_SHIFT))&DDRMC_PHY19_DLL_START_POINT_MASK)
/* PHY20 Bit Fields */
#define DDRMC_PHY20_DLL_WRITE_DL_MASK            0x7F00u
#define DDRMC_PHY20_DLL_WRITE_DL_SHIFT           8
#define DDRMC_PHY20_DLL_WRITE_DL(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY20_DLL_WRITE_DL_SHIFT))&DDRMC_PHY20_DLL_WRITE_DL_MASK)
/* PHY26 Bit Fields */
#define DDRMC_PHY26_LPBK_START_MASK              0x1u
#define DDRMC_PHY26_LPBK_START_SHIFT             0
#define DDRMC_PHY26_LPBK_STATUS_MASK             0x2u
#define DDRMC_PHY26_LPBK_STATUS_SHIFT            1
#define DDRMC_PHY26_LPBK_DM_DATA_MASK            0xF0u
#define DDRMC_PHY26_LPBK_DM_DATA_SHIFT           4
#define DDRMC_PHY26_LPBK_DM_DATA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY26_LPBK_DM_DATA_SHIFT))&DDRMC_PHY26_LPBK_DM_DATA_MASK)
#define DDRMC_PHY26_LPBK_DQ_DATA_MASK            0xFFFF00u
#define DDRMC_PHY26_LPBK_DQ_DATA_SHIFT           8
#define DDRMC_PHY26_LPBK_DQ_DATA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY26_LPBK_DQ_DATA_SHIFT))&DDRMC_PHY26_LPBK_DQ_DATA_MASK)
#define DDRMC_PHY26_DQS_ERROR_STATUS_MASK        0x1000000u
#define DDRMC_PHY26_DQS_ERROR_STATUS_SHIFT       24
/* PHY27 Bit Fields */
#define DDRMC_PHY27_DLL_LOCK_MASK                0x1u
#define DDRMC_PHY27_DLL_LOCK_SHIFT               0
#define DDRMC_PHY27_DLL_LOCK_VALUE_MASK          0xFF00u
#define DDRMC_PHY27_DLL_LOCK_VALUE_SHIFT         8
#define DDRMC_PHY27_DLL_LOCK_VALUE(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY27_DLL_LOCK_VALUE_SHIFT))&DDRMC_PHY27_DLL_LOCK_VALUE_MASK)
#define DDRMC_PHY27_LOCK_MASK                    0xFF0000u
#define DDRMC_PHY27_LOCK_SHIFT                   16
#define DDRMC_PHY27_LOCK(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY27_LOCK_SHIFT))&DDRMC_PHY27_LOCK_MASK)
#define DDRMC_PHY27_DLL_UNLOCK_VALUE_MASK        0xFF000000u
#define DDRMC_PHY27_DLL_UNLOCK_VALUE_SHIFT       24
#define DDRMC_PHY27_DLL_UNLOCK_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY27_DLL_UNLOCK_VALUE_SHIFT))&DDRMC_PHY27_DLL_UNLOCK_VALUE_MASK)
/* PHY28 Bit Fields */
#define DDRMC_PHY28_DLL_LOCK_MASK                0x1u
#define DDRMC_PHY28_DLL_LOCK_SHIFT               0
#define DDRMC_PHY28_DEC_OUT_RD_MASK              0xFEu
#define DDRMC_PHY28_DEC_OUT_RD_SHIFT             1
#define DDRMC_PHY28_DEC_OUT_RD(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY28_DEC_OUT_RD_SHIFT))&DDRMC_PHY28_DEC_OUT_RD_MASK)
#define DDRMC_PHY28_DEC_OUT_WR_MASK              0xFF0000u
#define DDRMC_PHY28_DEC_OUT_WR_SHIFT             16
#define DDRMC_PHY28_DEC_OUT_WR(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY28_DEC_OUT_WR_SHIFT))&DDRMC_PHY28_DEC_OUT_WR_MASK)
/* PHY29 Bit Fields */
#define DDRMC_PHY29_DEC_OUT_WR_DQS_MASK          0xFFFFu
#define DDRMC_PHY29_DEC_OUT_WR_DQS_SHIFT         0
#define DDRMC_PHY29_DEC_OUT_WR_DQS(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY29_DEC_OUT_WR_DQS_SHIFT))&DDRMC_PHY29_DEC_OUT_WR_DQS_MASK)
/* PHY32 Bit Fields */
#define DDRMC_PHY32_OE_END_MASK                  0xFu
#define DDRMC_PHY32_OE_END_SHIFT                 0
#define DDRMC_PHY32_OE_END(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY32_OE_END_SHIFT))&DDRMC_PHY32_OE_END_MASK)
#define DDRMC_PHY32_OE_START_MASK                0xF0u
#define DDRMC_PHY32_OE_START_SHIFT               4
#define DDRMC_PHY32_OE_START(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY32_OE_START_SHIFT))&DDRMC_PHY32_OE_START_MASK)
#define DDRMC_PHY32_TSEL_END_MASK                0xF00u
#define DDRMC_PHY32_TSEL_END_SHIFT               8
#define DDRMC_PHY32_TSEL_END(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY32_TSEL_END_SHIFT))&DDRMC_PHY32_TSEL_END_MASK)
#define DDRMC_PHY32_TSEL_START_MASK              0xF000u
#define DDRMC_PHY32_TSEL_START_SHIFT             12
#define DDRMC_PHY32_TSEL_START(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY32_TSEL_START_SHIFT))&DDRMC_PHY32_TSEL_START_MASK)
/* PHY33 Bit Fields */
#define DDRMC_PHY33_OE_END_MASK                  0x7u
#define DDRMC_PHY33_OE_END_SHIFT                 0
#define DDRMC_PHY33_OE_END(x)                    (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY33_OE_END_SHIFT))&DDRMC_PHY33_OE_END_MASK)
#define DDRMC_PHY33_OE_START_MASK                0x70u
#define DDRMC_PHY33_OE_START_SHIFT               4
#define DDRMC_PHY33_OE_START(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY33_OE_START_SHIFT))&DDRMC_PHY33_OE_START_MASK)
#define DDRMC_PHY33_TSEL_END_MASK                0xF00u
#define DDRMC_PHY33_TSEL_END_SHIFT               8
#define DDRMC_PHY33_TSEL_END(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY33_TSEL_END_SHIFT))&DDRMC_PHY33_TSEL_END_MASK)
#define DDRMC_PHY33_TSEL_START_MASK              0xF000u
#define DDRMC_PHY33_TSEL_START_SHIFT             12
#define DDRMC_PHY33_TSEL_START(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY33_TSEL_START_SHIFT))&DDRMC_PHY33_TSEL_START_MASK)
/* PHY34 Bit Fields */
#define DDRMC_PHY34_Gate_CFG_MASK                0x7u
#define DDRMC_PHY34_Gate_CFG_SHIFT               0
#define DDRMC_PHY34_Gate_CFG(x)                  (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY34_Gate_CFG_SHIFT))&DDRMC_PHY34_Gate_CFG_MASK)
#define DDRMC_PHY34_RD_DL_SET_MASK               0x380000u
#define DDRMC_PHY34_RD_DL_SET_SHIFT              19
#define DDRMC_PHY34_RD_DL_SET(x)                 (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY34_RD_DL_SET_SHIFT))&DDRMC_PHY34_RD_DL_SET_MASK)
#define DDRMC_PHY34_WRLVL_CLKDL_MASK             0x2000000u
#define DDRMC_PHY34_WRLVL_CLKDL_SHIFT            25
#define DDRMC_PHY34_SW_HALF_CYCLE_SHIFT_MASK     0x8000000u
#define DDRMC_PHY34_SW_HALF_CYCLE_SHIFT_SHIFT    27
#define DDRMC_PHY34_EN_HALF_CAS_MASK             0x20000000u
#define DDRMC_PHY34_EN_HALF_CAS_SHIFT            29
/* PHY35 Bit Fields */
#define DDRMC_PHY35_DLL_START_POINT_MASK         0xFFu
#define DDRMC_PHY35_DLL_START_POINT_SHIFT        0
#define DDRMC_PHY35_DLL_START_POINT(x)           (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY35_DLL_START_POINT_SHIFT))&DDRMC_PHY35_DLL_START_POINT_MASK)
/* PHY36 Bit Fields */
#define DDRMC_PHY36_DLL_WRITE_DL_MASK            0x7F00u
#define DDRMC_PHY36_DLL_WRITE_DL_SHIFT           8
#define DDRMC_PHY36_DLL_WRITE_DL(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY36_DLL_WRITE_DL_SHIFT))&DDRMC_PHY36_DLL_WRITE_DL_MASK)
/* PHY42 Bit Fields */
#define DDRMC_PHY42_LPBK_START_MASK              0x1u
#define DDRMC_PHY42_LPBK_START_SHIFT             0
#define DDRMC_PHY42_LPBK_STATUS_MASK             0x2u
#define DDRMC_PHY42_LPBK_STATUS_SHIFT            1
#define DDRMC_PHY42_LPBK_DM_DATA_MASK            0xF0u
#define DDRMC_PHY42_LPBK_DM_DATA_SHIFT           4
#define DDRMC_PHY42_LPBK_DM_DATA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY42_LPBK_DM_DATA_SHIFT))&DDRMC_PHY42_LPBK_DM_DATA_MASK)
#define DDRMC_PHY42_LPBK_DQ_DATA_MASK            0xFFFF00u
#define DDRMC_PHY42_LPBK_DQ_DATA_SHIFT           8
#define DDRMC_PHY42_LPBK_DQ_DATA(x)              (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY42_LPBK_DQ_DATA_SHIFT))&DDRMC_PHY42_LPBK_DQ_DATA_MASK)
#define DDRMC_PHY42_DQS_ERROR_STATUS_MASK        0x1000000u
#define DDRMC_PHY42_DQS_ERROR_STATUS_SHIFT       24
/* PHY43 Bit Fields */
#define DDRMC_PHY43_DLL_LOCK_MASK                0x1u
#define DDRMC_PHY43_DLL_LOCK_SHIFT               0
#define DDRMC_PHY43_DLL_LOCK_VALUE_MASK          0xFF00u
#define DDRMC_PHY43_DLL_LOCK_VALUE_SHIFT         8
#define DDRMC_PHY43_DLL_LOCK_VALUE(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY43_DLL_LOCK_VALUE_SHIFT))&DDRMC_PHY43_DLL_LOCK_VALUE_MASK)
#define DDRMC_PHY43_LOCK_MASK                    0xFF0000u
#define DDRMC_PHY43_LOCK_SHIFT                   16
#define DDRMC_PHY43_LOCK(x)                      (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY43_LOCK_SHIFT))&DDRMC_PHY43_LOCK_MASK)
#define DDRMC_PHY43_DLL_UNLOCK_VALUE_MASK        0xFF000000u
#define DDRMC_PHY43_DLL_UNLOCK_VALUE_SHIFT       24
#define DDRMC_PHY43_DLL_UNLOCK_VALUE(x)          (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY43_DLL_UNLOCK_VALUE_SHIFT))&DDRMC_PHY43_DLL_UNLOCK_VALUE_MASK)
/* PHY44 Bit Fields */
#define DDRMC_PHY44_DLL_LOCK_MASK                0x1u
#define DDRMC_PHY44_DLL_LOCK_SHIFT               0
#define DDRMC_PHY44_DEC_OUT_RD_MASK              0xFEu
#define DDRMC_PHY44_DEC_OUT_RD_SHIFT             1
#define DDRMC_PHY44_DEC_OUT_RD(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY44_DEC_OUT_RD_SHIFT))&DDRMC_PHY44_DEC_OUT_RD_MASK)
#define DDRMC_PHY44_DEC_OUT_WR_MASK              0xFF0000u
#define DDRMC_PHY44_DEC_OUT_WR_SHIFT             16
#define DDRMC_PHY44_DEC_OUT_WR(x)                (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY44_DEC_OUT_WR_SHIFT))&DDRMC_PHY44_DEC_OUT_WR_MASK)
/* PHY45 Bit Fields */
#define DDRMC_PHY45_DEC_OUT_WR_DQS_MASK          0xFFFFu
#define DDRMC_PHY45_DEC_OUT_WR_DQS_SHIFT         0
#define DDRMC_PHY45_DEC_OUT_WR_DQS(x)            (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY45_DEC_OUT_WR_DQS_SHIFT))&DDRMC_PHY45_DEC_OUT_WR_DQS_MASK)
/* PHY49 Bit Fields */
#define DDRMC_PHY49_PHY_RDLV_DL_MASK             0xFF0000u
#define DDRMC_PHY49_PHY_RDLV_DL_SHIFT            16
#define DDRMC_PHY49_PHY_RDLV_DL(x)               (((uint32_t)(((uint32_t)(x))<<DDRMC_PHY49_PHY_RDLV_DL_SHIFT))&DDRMC_PHY49_PHY_RDLV_DL_MASK)
/* PHY50 Bit Fields */
#define DDRMC_PHY50_CLEAR_FIFO_MASK              0x10u
#define DDRMC_PHY50_CLEAR_FIFO_SHIFT             4
#define DDRMC_PHY50_EN_SW_HALF_CYCLE_MASK        0x100u
#define DDRMC_PHY50_EN_SW_HALF_CYCLE_SHIFT       8
#define DDRMC_PHY50_DDR_SEL_MASK                 0x800u
#define DDRMC_PHY50_DDR_SEL_SHIFT                11
#define DDRMC_PHY50_DDR3_MODE_MASK               0x1000u
#define DDRMC_PHY50_DDR3_MODE_SHIFT              12
#define DDRMC_PHY50_DFI_MOBILE_EN_MASK           0x2000u
#define DDRMC_PHY50_DFI_MOBILE_EN_SHIFT          13
/* PHY52 Bit Fields */
#define DDRMC_PHY52_tsel_rd_value_dm_MASK        0x1u
#define DDRMC_PHY52_tsel_rd_value_dm_SHIFT       0
#define DDRMC_PHY52_tsel_off_value_dm_MASK       0x10u
#define DDRMC_PHY52_tsel_off_value_dm_SHIFT      4
#define DDRMC_PHY52_tsel_rd_value_dqs_MASK       0x100u
#define DDRMC_PHY52_tsel_rd_value_dqs_SHIFT      8
#define DDRMC_PHY52_tsel_off_value_dqs_MASK      0x1000u
#define DDRMC_PHY52_tsel_off_value_dqs_SHIFT     12
#define DDRMC_PHY52_tsel_rd_value_data_MASK      0x10000u
#define DDRMC_PHY52_tsel_rd_value_data_SHIFT     16
#define DDRMC_PHY52_tsel_off_value_data_MASK     0x100000u
#define DDRMC_PHY52_tsel_off_value_data_SHIFT    20

/**
 * @}
 */ /* end of group DDRMC_Register_Masks */


/* DDRMC - Peripheral instance base addresses */
/** Peripheral DDRMC base address */
#define DDRMC_BASE                               (0x400AE000u)
/** Peripheral DDRMC base pointer */
#define DDRMC                                    ((DDRMC_Type *)DDRMC_BASE)
/** Array initializer of DDRMC peripheral base pointers */
#define DDRMC_BASES                              { DDRMC }

/**
 * @}
 */ /* end of group DDRMC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
       uint8_t RESERVED_1[4];
  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
       uint8_t RESERVED_2[4];
  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
       uint8_t RESERVED_3[4];
  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
       uint8_t RESERVED_4[4];
  __IO uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
       uint8_t RESERVED_5[200];
  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
  __IO uint8_t DCHPRI19;                           /**< Channel n Priority Register, offset: 0x110 */
  __IO uint8_t DCHPRI18;                           /**< Channel n Priority Register, offset: 0x111 */
  __IO uint8_t DCHPRI17;                           /**< Channel n Priority Register, offset: 0x112 */
  __IO uint8_t DCHPRI16;                           /**< Channel n Priority Register, offset: 0x113 */
  __IO uint8_t DCHPRI23;                           /**< Channel n Priority Register, offset: 0x114 */
  __IO uint8_t DCHPRI22;                           /**< Channel n Priority Register, offset: 0x115 */
  __IO uint8_t DCHPRI21;                           /**< Channel n Priority Register, offset: 0x116 */
  __IO uint8_t DCHPRI20;                           /**< Channel n Priority Register, offset: 0x117 */
  __IO uint8_t DCHPRI27;                           /**< Channel n Priority Register, offset: 0x118 */
  __IO uint8_t DCHPRI26;                           /**< Channel n Priority Register, offset: 0x119 */
  __IO uint8_t DCHPRI25;                           /**< Channel n Priority Register, offset: 0x11A */
  __IO uint8_t DCHPRI24;                           /**< Channel n Priority Register, offset: 0x11B */
  __IO uint8_t DCHPRI31;                           /**< Channel n Priority Register, offset: 0x11C */
  __IO uint8_t DCHPRI30;                           /**< Channel n Priority Register, offset: 0x11D */
  __IO uint8_t DCHPRI29;                           /**< Channel n Priority Register, offset: 0x11E */
  __IO uint8_t DCHPRI28;                           /**< Channel n Priority Register, offset: 0x11F */
       uint8_t RESERVED_6[3808];
  struct {                                         /* offset: 0x1000, array step: 0x20 */
    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
    union {                                          /* offset: 0x1008, array step: 0x20 */
      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
    };
    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
    union {                                          /* offset: 0x1016, array step: 0x20 */
      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
    };
    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
    union {                                          /* offset: 0x101E, array step: 0x20 */
      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
    };
  } TCD[32];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/* CR Bit Fields */
#define DMA_CR_EDBG_MASK                         0x2u
#define DMA_CR_EDBG_SHIFT                        1
#define DMA_CR_ERCA_MASK                         0x4u
#define DMA_CR_ERCA_SHIFT                        2
#define DMA_CR_ERGA_MASK                         0x8u
#define DMA_CR_ERGA_SHIFT                        3
#define DMA_CR_HOE_MASK                          0x10u
#define DMA_CR_HOE_SHIFT                         4
#define DMA_CR_HALT_MASK                         0x20u
#define DMA_CR_HALT_SHIFT                        5
#define DMA_CR_CLM_MASK                          0x40u
#define DMA_CR_CLM_SHIFT                         6
#define DMA_CR_EMLM_MASK                         0x80u
#define DMA_CR_EMLM_SHIFT                        7
#define DMA_CR_GRP0PRI_MASK                      0x300u
#define DMA_CR_GRP0PRI_SHIFT                     8
#define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_CR_GRP0PRI_SHIFT))&DMA_CR_GRP0PRI_MASK)
#define DMA_CR_GRP1PRI_MASK                      0xC00u
#define DMA_CR_GRP1PRI_SHIFT                     10
#define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_CR_GRP1PRI_SHIFT))&DMA_CR_GRP1PRI_MASK)
#define DMA_CR_ECX_MASK                          0x10000u
#define DMA_CR_ECX_SHIFT                         16
#define DMA_CR_CX_MASK                           0x20000u
#define DMA_CR_CX_SHIFT                          17
/* ES Bit Fields */
#define DMA_ES_DBE_MASK                          0x1u
#define DMA_ES_DBE_SHIFT                         0
#define DMA_ES_SBE_MASK                          0x2u
#define DMA_ES_SBE_SHIFT                         1
#define DMA_ES_SGE_MASK                          0x4u
#define DMA_ES_SGE_SHIFT                         2
#define DMA_ES_NCE_MASK                          0x8u
#define DMA_ES_NCE_SHIFT                         3
#define DMA_ES_DOE_MASK                          0x10u
#define DMA_ES_DOE_SHIFT                         4
#define DMA_ES_DAE_MASK                          0x20u
#define DMA_ES_DAE_SHIFT                         5
#define DMA_ES_SOE_MASK                          0x40u
#define DMA_ES_SOE_SHIFT                         6
#define DMA_ES_SAE_MASK                          0x80u
#define DMA_ES_SAE_SHIFT                         7
#define DMA_ES_ERRCHN_MASK                       0x1F00u
#define DMA_ES_ERRCHN_SHIFT                      8
#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK                          0x4000u
#define DMA_ES_CPE_SHIFT                         14
#define DMA_ES_GPE_MASK                          0x8000u
#define DMA_ES_GPE_SHIFT                         15
#define DMA_ES_ECX_MASK                          0x10000u
#define DMA_ES_ECX_SHIFT                         16
#define DMA_ES_VLD_MASK                          0x80000000u
#define DMA_ES_VLD_SHIFT                         31
/* ERQ Bit Fields */
#define DMA_ERQ_ERQ0_MASK                        0x1u
#define DMA_ERQ_ERQ0_SHIFT                       0
#define DMA_ERQ_ERQ1_MASK                        0x2u
#define DMA_ERQ_ERQ1_SHIFT                       1
#define DMA_ERQ_ERQ2_MASK                        0x4u
#define DMA_ERQ_ERQ2_SHIFT                       2
#define DMA_ERQ_ERQ3_MASK                        0x8u
#define DMA_ERQ_ERQ3_SHIFT                       3
#define DMA_ERQ_ERQ4_MASK                        0x10u
#define DMA_ERQ_ERQ4_SHIFT                       4
#define DMA_ERQ_ERQ5_MASK                        0x20u
#define DMA_ERQ_ERQ5_SHIFT                       5
#define DMA_ERQ_ERQ6_MASK                        0x40u
#define DMA_ERQ_ERQ6_SHIFT                       6
#define DMA_ERQ_ERQ7_MASK                        0x80u
#define DMA_ERQ_ERQ7_SHIFT                       7
#define DMA_ERQ_ERQ8_MASK                        0x100u
#define DMA_ERQ_ERQ8_SHIFT                       8
#define DMA_ERQ_ERQ9_MASK                        0x200u
#define DMA_ERQ_ERQ9_SHIFT                       9
#define DMA_ERQ_ERQ10_MASK                       0x400u
#define DMA_ERQ_ERQ10_SHIFT                      10
#define DMA_ERQ_ERQ11_MASK                       0x800u
#define DMA_ERQ_ERQ11_SHIFT                      11
#define DMA_ERQ_ERQ12_MASK                       0x1000u
#define DMA_ERQ_ERQ12_SHIFT                      12
#define DMA_ERQ_ERQ13_MASK                       0x2000u
#define DMA_ERQ_ERQ13_SHIFT                      13
#define DMA_ERQ_ERQ14_MASK                       0x4000u
#define DMA_ERQ_ERQ14_SHIFT                      14
#define DMA_ERQ_ERQ15_MASK                       0x8000u
#define DMA_ERQ_ERQ15_SHIFT                      15
#define DMA_ERQ_ERQ16_MASK                       0x10000u
#define DMA_ERQ_ERQ16_SHIFT                      16
#define DMA_ERQ_ERQ17_MASK                       0x20000u
#define DMA_ERQ_ERQ17_SHIFT                      17
#define DMA_ERQ_ERQ18_MASK                       0x40000u
#define DMA_ERQ_ERQ18_SHIFT                      18
#define DMA_ERQ_ERQ19_MASK                       0x80000u
#define DMA_ERQ_ERQ19_SHIFT                      19
#define DMA_ERQ_ERQ20_MASK                       0x100000u
#define DMA_ERQ_ERQ20_SHIFT                      20
#define DMA_ERQ_ERQ21_MASK                       0x200000u
#define DMA_ERQ_ERQ21_SHIFT                      21
#define DMA_ERQ_ERQ22_MASK                       0x400000u
#define DMA_ERQ_ERQ22_SHIFT                      22
#define DMA_ERQ_ERQ23_MASK                       0x800000u
#define DMA_ERQ_ERQ23_SHIFT                      23
#define DMA_ERQ_ERQ24_MASK                       0x1000000u
#define DMA_ERQ_ERQ24_SHIFT                      24
#define DMA_ERQ_ERQ25_MASK                       0x2000000u
#define DMA_ERQ_ERQ25_SHIFT                      25
#define DMA_ERQ_ERQ26_MASK                       0x4000000u
#define DMA_ERQ_ERQ26_SHIFT                      26
#define DMA_ERQ_ERQ27_MASK                       0x8000000u
#define DMA_ERQ_ERQ27_SHIFT                      27
#define DMA_ERQ_ERQ28_MASK                       0x10000000u
#define DMA_ERQ_ERQ28_SHIFT                      28
#define DMA_ERQ_ERQ29_MASK                       0x20000000u
#define DMA_ERQ_ERQ29_SHIFT                      29
#define DMA_ERQ_ERQ30_MASK                       0x40000000u
#define DMA_ERQ_ERQ30_SHIFT                      30
#define DMA_ERQ_ERQ31_MASK                       0x80000000u
#define DMA_ERQ_ERQ31_SHIFT                      31
/* EEI Bit Fields */
#define DMA_EEI_EEI0_MASK                        0x1u
#define DMA_EEI_EEI0_SHIFT                       0
#define DMA_EEI_EEI1_MASK                        0x2u
#define DMA_EEI_EEI1_SHIFT                       1
#define DMA_EEI_EEI2_MASK                        0x4u
#define DMA_EEI_EEI2_SHIFT                       2
#define DMA_EEI_EEI3_MASK                        0x8u
#define DMA_EEI_EEI3_SHIFT                       3
#define DMA_EEI_EEI4_MASK                        0x10u
#define DMA_EEI_EEI4_SHIFT                       4
#define DMA_EEI_EEI5_MASK                        0x20u
#define DMA_EEI_EEI5_SHIFT                       5
#define DMA_EEI_EEI6_MASK                        0x40u
#define DMA_EEI_EEI6_SHIFT                       6
#define DMA_EEI_EEI7_MASK                        0x80u
#define DMA_EEI_EEI7_SHIFT                       7
#define DMA_EEI_EEI8_MASK                        0x100u
#define DMA_EEI_EEI8_SHIFT                       8
#define DMA_EEI_EEI9_MASK                        0x200u
#define DMA_EEI_EEI9_SHIFT                       9
#define DMA_EEI_EEI10_MASK                       0x400u
#define DMA_EEI_EEI10_SHIFT                      10
#define DMA_EEI_EEI11_MASK                       0x800u
#define DMA_EEI_EEI11_SHIFT                      11
#define DMA_EEI_EEI12_MASK                       0x1000u
#define DMA_EEI_EEI12_SHIFT                      12
#define DMA_EEI_EEI13_MASK                       0x2000u
#define DMA_EEI_EEI13_SHIFT                      13
#define DMA_EEI_EEI14_MASK                       0x4000u
#define DMA_EEI_EEI14_SHIFT                      14
#define DMA_EEI_EEI15_MASK                       0x8000u
#define DMA_EEI_EEI15_SHIFT                      15
#define DMA_EEI_EEI16_MASK                       0x10000u
#define DMA_EEI_EEI16_SHIFT                      16
#define DMA_EEI_EEI17_MASK                       0x20000u
#define DMA_EEI_EEI17_SHIFT                      17
#define DMA_EEI_EEI18_MASK                       0x40000u
#define DMA_EEI_EEI18_SHIFT                      18
#define DMA_EEI_EEI19_MASK                       0x80000u
#define DMA_EEI_EEI19_SHIFT                      19
#define DMA_EEI_EEI20_MASK                       0x100000u
#define DMA_EEI_EEI20_SHIFT                      20
#define DMA_EEI_EEI21_MASK                       0x200000u
#define DMA_EEI_EEI21_SHIFT                      21
#define DMA_EEI_EEI22_MASK                       0x400000u
#define DMA_EEI_EEI22_SHIFT                      22
#define DMA_EEI_EEI23_MASK                       0x800000u
#define DMA_EEI_EEI23_SHIFT                      23
#define DMA_EEI_EEI24_MASK                       0x1000000u
#define DMA_EEI_EEI24_SHIFT                      24
#define DMA_EEI_EEI25_MASK                       0x2000000u
#define DMA_EEI_EEI25_SHIFT                      25
#define DMA_EEI_EEI26_MASK                       0x4000000u
#define DMA_EEI_EEI26_SHIFT                      26
#define DMA_EEI_EEI27_MASK                       0x8000000u
#define DMA_EEI_EEI27_SHIFT                      27
#define DMA_EEI_EEI28_MASK                       0x10000000u
#define DMA_EEI_EEI28_SHIFT                      28
#define DMA_EEI_EEI29_MASK                       0x20000000u
#define DMA_EEI_EEI29_SHIFT                      29
#define DMA_EEI_EEI30_MASK                       0x40000000u
#define DMA_EEI_EEI30_SHIFT                      30
#define DMA_EEI_EEI31_MASK                       0x80000000u
#define DMA_EEI_EEI31_SHIFT                      31
/* CEEI Bit Fields */
#define DMA_CEEI_CEEI_MASK                       0x1Fu
#define DMA_CEEI_CEEI_SHIFT                      0
#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK                       0x40u
#define DMA_CEEI_CAEE_SHIFT                      6
#define DMA_CEEI_NOP_MASK                        0x80u
#define DMA_CEEI_NOP_SHIFT                       7
/* SEEI Bit Fields */
#define DMA_SEEI_SEEI_MASK                       0x1Fu
#define DMA_SEEI_SEEI_SHIFT                      0
#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK                       0x40u
#define DMA_SEEI_SAEE_SHIFT                      6
#define DMA_SEEI_NOP_MASK                        0x80u
#define DMA_SEEI_NOP_SHIFT                       7
/* CERQ Bit Fields */
#define DMA_CERQ_CERQ_MASK                       0x1Fu
#define DMA_CERQ_CERQ_SHIFT                      0
#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK                       0x40u
#define DMA_CERQ_CAER_SHIFT                      6
#define DMA_CERQ_NOP_MASK                        0x80u
#define DMA_CERQ_NOP_SHIFT                       7
/* SERQ Bit Fields */
#define DMA_SERQ_SERQ_MASK                       0x1Fu
#define DMA_SERQ_SERQ_SHIFT                      0
#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK                       0x40u
#define DMA_SERQ_SAER_SHIFT                      6
#define DMA_SERQ_NOP_MASK                        0x80u
#define DMA_SERQ_NOP_SHIFT                       7
/* CDNE Bit Fields */
#define DMA_CDNE_CDNE_MASK                       0x1Fu
#define DMA_CDNE_CDNE_SHIFT                      0
#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK                       0x40u
#define DMA_CDNE_CADN_SHIFT                      6
#define DMA_CDNE_NOP_MASK                        0x80u
#define DMA_CDNE_NOP_SHIFT                       7
/* SSRT Bit Fields */
#define DMA_SSRT_SSRT_MASK                       0x1Fu
#define DMA_SSRT_SSRT_SHIFT                      0
#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK                       0x40u
#define DMA_SSRT_SAST_SHIFT                      6
#define DMA_SSRT_NOP_MASK                        0x80u
#define DMA_SSRT_NOP_SHIFT                       7
/* CERR Bit Fields */
#define DMA_CERR_CERR_MASK                       0x1Fu
#define DMA_CERR_CERR_SHIFT                      0
#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK                       0x40u
#define DMA_CERR_CAEI_SHIFT                      6
#define DMA_CERR_NOP_MASK                        0x80u
#define DMA_CERR_NOP_SHIFT                       7
/* CINT Bit Fields */
#define DMA_CINT_CINT_MASK                       0x1Fu
#define DMA_CINT_CINT_SHIFT                      0
#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK                       0x40u
#define DMA_CINT_CAIR_SHIFT                      6
#define DMA_CINT_NOP_MASK                        0x80u
#define DMA_CINT_NOP_SHIFT                       7
/* INT Bit Fields */
#define DMA_INT_INT0_MASK                        0x1u
#define DMA_INT_INT0_SHIFT                       0
#define DMA_INT_INT1_MASK                        0x2u
#define DMA_INT_INT1_SHIFT                       1
#define DMA_INT_INT2_MASK                        0x4u
#define DMA_INT_INT2_SHIFT                       2
#define DMA_INT_INT3_MASK                        0x8u
#define DMA_INT_INT3_SHIFT                       3
#define DMA_INT_INT4_MASK                        0x10u
#define DMA_INT_INT4_SHIFT                       4
#define DMA_INT_INT5_MASK                        0x20u
#define DMA_INT_INT5_SHIFT                       5
#define DMA_INT_INT6_MASK                        0x40u
#define DMA_INT_INT6_SHIFT                       6
#define DMA_INT_INT7_MASK                        0x80u
#define DMA_INT_INT7_SHIFT                       7
#define DMA_INT_INT8_MASK                        0x100u
#define DMA_INT_INT8_SHIFT                       8
#define DMA_INT_INT9_MASK                        0x200u
#define DMA_INT_INT9_SHIFT                       9
#define DMA_INT_INT10_MASK                       0x400u
#define DMA_INT_INT10_SHIFT                      10
#define DMA_INT_INT11_MASK                       0x800u
#define DMA_INT_INT11_SHIFT                      11
#define DMA_INT_INT12_MASK                       0x1000u
#define DMA_INT_INT12_SHIFT                      12
#define DMA_INT_INT13_MASK                       0x2000u
#define DMA_INT_INT13_SHIFT                      13
#define DMA_INT_INT14_MASK                       0x4000u
#define DMA_INT_INT14_SHIFT                      14
#define DMA_INT_INT15_MASK                       0x8000u
#define DMA_INT_INT15_SHIFT                      15
#define DMA_INT_INT16_MASK                       0x10000u
#define DMA_INT_INT16_SHIFT                      16
#define DMA_INT_INT17_MASK                       0x20000u
#define DMA_INT_INT17_SHIFT                      17
#define DMA_INT_INT18_MASK                       0x40000u
#define DMA_INT_INT18_SHIFT                      18
#define DMA_INT_INT19_MASK                       0x80000u
#define DMA_INT_INT19_SHIFT                      19
#define DMA_INT_INT20_MASK                       0x100000u
#define DMA_INT_INT20_SHIFT                      20
#define DMA_INT_INT21_MASK                       0x200000u
#define DMA_INT_INT21_SHIFT                      21
#define DMA_INT_INT22_MASK                       0x400000u
#define DMA_INT_INT22_SHIFT                      22
#define DMA_INT_INT23_MASK                       0x800000u
#define DMA_INT_INT23_SHIFT                      23
#define DMA_INT_INT24_MASK                       0x1000000u
#define DMA_INT_INT24_SHIFT                      24
#define DMA_INT_INT25_MASK                       0x2000000u
#define DMA_INT_INT25_SHIFT                      25
#define DMA_INT_INT26_MASK                       0x4000000u
#define DMA_INT_INT26_SHIFT                      26
#define DMA_INT_INT27_MASK                       0x8000000u
#define DMA_INT_INT27_SHIFT                      27
#define DMA_INT_INT28_MASK                       0x10000000u
#define DMA_INT_INT28_SHIFT                      28
#define DMA_INT_INT29_MASK                       0x20000000u
#define DMA_INT_INT29_SHIFT                      29
#define DMA_INT_INT30_MASK                       0x40000000u
#define DMA_INT_INT30_SHIFT                      30
#define DMA_INT_INT31_MASK                       0x80000000u
#define DMA_INT_INT31_SHIFT                      31
/* ERR Bit Fields */
#define DMA_ERR_ERR0_MASK                        0x1u
#define DMA_ERR_ERR0_SHIFT                       0
#define DMA_ERR_ERR1_MASK                        0x2u
#define DMA_ERR_ERR1_SHIFT                       1
#define DMA_ERR_ERR2_MASK                        0x4u
#define DMA_ERR_ERR2_SHIFT                       2
#define DMA_ERR_ERR3_MASK                        0x8u
#define DMA_ERR_ERR3_SHIFT                       3
#define DMA_ERR_ERR4_MASK                        0x10u
#define DMA_ERR_ERR4_SHIFT                       4
#define DMA_ERR_ERR5_MASK                        0x20u
#define DMA_ERR_ERR5_SHIFT                       5
#define DMA_ERR_ERR6_MASK                        0x40u
#define DMA_ERR_ERR6_SHIFT                       6
#define DMA_ERR_ERR7_MASK                        0x80u
#define DMA_ERR_ERR7_SHIFT                       7
#define DMA_ERR_ERR8_MASK                        0x100u
#define DMA_ERR_ERR8_SHIFT                       8
#define DMA_ERR_ERR9_MASK                        0x200u
#define DMA_ERR_ERR9_SHIFT                       9
#define DMA_ERR_ERR10_MASK                       0x400u
#define DMA_ERR_ERR10_SHIFT                      10
#define DMA_ERR_ERR11_MASK                       0x800u
#define DMA_ERR_ERR11_SHIFT                      11
#define DMA_ERR_ERR12_MASK                       0x1000u
#define DMA_ERR_ERR12_SHIFT                      12
#define DMA_ERR_ERR13_MASK                       0x2000u
#define DMA_ERR_ERR13_SHIFT                      13
#define DMA_ERR_ERR14_MASK                       0x4000u
#define DMA_ERR_ERR14_SHIFT                      14
#define DMA_ERR_ERR15_MASK                       0x8000u
#define DMA_ERR_ERR15_SHIFT                      15
#define DMA_ERR_ERR16_MASK                       0x10000u
#define DMA_ERR_ERR16_SHIFT                      16
#define DMA_ERR_ERR17_MASK                       0x20000u
#define DMA_ERR_ERR17_SHIFT                      17
#define DMA_ERR_ERR18_MASK                       0x40000u
#define DMA_ERR_ERR18_SHIFT                      18
#define DMA_ERR_ERR19_MASK                       0x80000u
#define DMA_ERR_ERR19_SHIFT                      19
#define DMA_ERR_ERR20_MASK                       0x100000u
#define DMA_ERR_ERR20_SHIFT                      20
#define DMA_ERR_ERR21_MASK                       0x200000u
#define DMA_ERR_ERR21_SHIFT                      21
#define DMA_ERR_ERR22_MASK                       0x400000u
#define DMA_ERR_ERR22_SHIFT                      22
#define DMA_ERR_ERR23_MASK                       0x800000u
#define DMA_ERR_ERR23_SHIFT                      23
#define DMA_ERR_ERR24_MASK                       0x1000000u
#define DMA_ERR_ERR24_SHIFT                      24
#define DMA_ERR_ERR25_MASK                       0x2000000u
#define DMA_ERR_ERR25_SHIFT                      25
#define DMA_ERR_ERR26_MASK                       0x4000000u
#define DMA_ERR_ERR26_SHIFT                      26
#define DMA_ERR_ERR27_MASK                       0x8000000u
#define DMA_ERR_ERR27_SHIFT                      27
#define DMA_ERR_ERR28_MASK                       0x10000000u
#define DMA_ERR_ERR28_SHIFT                      28
#define DMA_ERR_ERR29_MASK                       0x20000000u
#define DMA_ERR_ERR29_SHIFT                      29
#define DMA_ERR_ERR30_MASK                       0x40000000u
#define DMA_ERR_ERR30_SHIFT                      30
#define DMA_ERR_ERR31_MASK                       0x80000000u
#define DMA_ERR_ERR31_SHIFT                      31
/* HRS Bit Fields */
#define DMA_HRS_HRS0_MASK                        0x1u
#define DMA_HRS_HRS0_SHIFT                       0
#define DMA_HRS_HRS1_MASK                        0x2u
#define DMA_HRS_HRS1_SHIFT                       1
#define DMA_HRS_HRS2_MASK                        0x4u
#define DMA_HRS_HRS2_SHIFT                       2
#define DMA_HRS_HRS3_MASK                        0x8u
#define DMA_HRS_HRS3_SHIFT                       3
#define DMA_HRS_HRS4_MASK                        0x10u
#define DMA_HRS_HRS4_SHIFT                       4
#define DMA_HRS_HRS5_MASK                        0x20u
#define DMA_HRS_HRS5_SHIFT                       5
#define DMA_HRS_HRS6_MASK                        0x40u
#define DMA_HRS_HRS6_SHIFT                       6
#define DMA_HRS_HRS7_MASK                        0x80u
#define DMA_HRS_HRS7_SHIFT                       7
#define DMA_HRS_HRS8_MASK                        0x100u
#define DMA_HRS_HRS8_SHIFT                       8
#define DMA_HRS_HRS9_MASK                        0x200u
#define DMA_HRS_HRS9_SHIFT                       9
#define DMA_HRS_HRS10_MASK                       0x400u
#define DMA_HRS_HRS10_SHIFT                      10
#define DMA_HRS_HRS11_MASK                       0x800u
#define DMA_HRS_HRS11_SHIFT                      11
#define DMA_HRS_HRS12_MASK                       0x1000u
#define DMA_HRS_HRS12_SHIFT                      12
#define DMA_HRS_HRS13_MASK                       0x2000u
#define DMA_HRS_HRS13_SHIFT                      13
#define DMA_HRS_HRS14_MASK                       0x4000u
#define DMA_HRS_HRS14_SHIFT                      14
#define DMA_HRS_HRS15_MASK                       0x8000u
#define DMA_HRS_HRS15_SHIFT                      15
#define DMA_HRS_HRS16_MASK                       0x10000u
#define DMA_HRS_HRS16_SHIFT                      16
#define DMA_HRS_HRS17_MASK                       0x20000u
#define DMA_HRS_HRS17_SHIFT                      17
#define DMA_HRS_HRS18_MASK                       0x40000u
#define DMA_HRS_HRS18_SHIFT                      18
#define DMA_HRS_HRS19_MASK                       0x80000u
#define DMA_HRS_HRS19_SHIFT                      19
#define DMA_HRS_HRS20_MASK                       0x100000u
#define DMA_HRS_HRS20_SHIFT                      20
#define DMA_HRS_HRS21_MASK                       0x200000u
#define DMA_HRS_HRS21_SHIFT                      21
#define DMA_HRS_HRS22_MASK                       0x400000u
#define DMA_HRS_HRS22_SHIFT                      22
#define DMA_HRS_HRS23_MASK                       0x800000u
#define DMA_HRS_HRS23_SHIFT                      23
#define DMA_HRS_HRS24_MASK                       0x1000000u
#define DMA_HRS_HRS24_SHIFT                      24
#define DMA_HRS_HRS25_MASK                       0x2000000u
#define DMA_HRS_HRS25_SHIFT                      25
#define DMA_HRS_HRS26_MASK                       0x4000000u
#define DMA_HRS_HRS26_SHIFT                      26
#define DMA_HRS_HRS27_MASK                       0x8000000u
#define DMA_HRS_HRS27_SHIFT                      27
#define DMA_HRS_HRS28_MASK                       0x10000000u
#define DMA_HRS_HRS28_SHIFT                      28
#define DMA_HRS_HRS29_MASK                       0x20000000u
#define DMA_HRS_HRS29_SHIFT                      29
#define DMA_HRS_HRS30_MASK                       0x40000000u
#define DMA_HRS_HRS30_SHIFT                      30
#define DMA_HRS_HRS31_MASK                       0x80000000u
#define DMA_HRS_HRS31_SHIFT                      31
/* DCHPRI3 Bit Fields */
#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
#define DMA_DCHPRI3_CHPRI_SHIFT                  0
#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI3_GRPPRI_SHIFT                 4
#define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_GRPPRI_SHIFT))&DMA_DCHPRI3_GRPPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK                     0x40u
#define DMA_DCHPRI3_DPA_SHIFT                    6
#define DMA_DCHPRI3_ECP_MASK                     0x80u
#define DMA_DCHPRI3_ECP_SHIFT                    7
/* DCHPRI2 Bit Fields */
#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
#define DMA_DCHPRI2_CHPRI_SHIFT                  0
#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI2_GRPPRI_SHIFT                 4
#define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_GRPPRI_SHIFT))&DMA_DCHPRI2_GRPPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK                     0x40u
#define DMA_DCHPRI2_DPA_SHIFT                    6
#define DMA_DCHPRI2_ECP_MASK                     0x80u
#define DMA_DCHPRI2_ECP_SHIFT                    7
/* DCHPRI1 Bit Fields */
#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
#define DMA_DCHPRI1_CHPRI_SHIFT                  0
#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI1_GRPPRI_SHIFT                 4
#define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_GRPPRI_SHIFT))&DMA_DCHPRI1_GRPPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK                     0x40u
#define DMA_DCHPRI1_DPA_SHIFT                    6
#define DMA_DCHPRI1_ECP_MASK                     0x80u
#define DMA_DCHPRI1_ECP_SHIFT                    7
/* DCHPRI0 Bit Fields */
#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
#define DMA_DCHPRI0_CHPRI_SHIFT                  0
#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI0_GRPPRI_SHIFT                 4
#define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_GRPPRI_SHIFT))&DMA_DCHPRI0_GRPPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK                     0x40u
#define DMA_DCHPRI0_DPA_SHIFT                    6
#define DMA_DCHPRI0_ECP_MASK                     0x80u
#define DMA_DCHPRI0_ECP_SHIFT                    7
/* DCHPRI7 Bit Fields */
#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
#define DMA_DCHPRI7_CHPRI_SHIFT                  0
#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI7_GRPPRI_SHIFT                 4
#define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_GRPPRI_SHIFT))&DMA_DCHPRI7_GRPPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK                     0x40u
#define DMA_DCHPRI7_DPA_SHIFT                    6
#define DMA_DCHPRI7_ECP_MASK                     0x80u
#define DMA_DCHPRI7_ECP_SHIFT                    7
/* DCHPRI6 Bit Fields */
#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
#define DMA_DCHPRI6_CHPRI_SHIFT                  0
#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI6_GRPPRI_SHIFT                 4
#define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_GRPPRI_SHIFT))&DMA_DCHPRI6_GRPPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK                     0x40u
#define DMA_DCHPRI6_DPA_SHIFT                    6
#define DMA_DCHPRI6_ECP_MASK                     0x80u
#define DMA_DCHPRI6_ECP_SHIFT                    7
/* DCHPRI5 Bit Fields */
#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
#define DMA_DCHPRI5_CHPRI_SHIFT                  0
#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI5_GRPPRI_SHIFT                 4
#define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_GRPPRI_SHIFT))&DMA_DCHPRI5_GRPPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK                     0x40u
#define DMA_DCHPRI5_DPA_SHIFT                    6
#define DMA_DCHPRI5_ECP_MASK                     0x80u
#define DMA_DCHPRI5_ECP_SHIFT                    7
/* DCHPRI4 Bit Fields */
#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
#define DMA_DCHPRI4_CHPRI_SHIFT                  0
#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI4_GRPPRI_SHIFT                 4
#define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_GRPPRI_SHIFT))&DMA_DCHPRI4_GRPPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK                     0x40u
#define DMA_DCHPRI4_DPA_SHIFT                    6
#define DMA_DCHPRI4_ECP_MASK                     0x80u
#define DMA_DCHPRI4_ECP_SHIFT                    7
/* DCHPRI11 Bit Fields */
#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
#define DMA_DCHPRI11_CHPRI_SHIFT                 0
#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
#define DMA_DCHPRI11_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI11_GRPPRI_SHIFT                4
#define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_GRPPRI_SHIFT))&DMA_DCHPRI11_GRPPRI_MASK)
#define DMA_DCHPRI11_DPA_MASK                    0x40u
#define DMA_DCHPRI11_DPA_SHIFT                   6
#define DMA_DCHPRI11_ECP_MASK                    0x80u
#define DMA_DCHPRI11_ECP_SHIFT                   7
/* DCHPRI10 Bit Fields */
#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
#define DMA_DCHPRI10_CHPRI_SHIFT                 0
#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
#define DMA_DCHPRI10_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI10_GRPPRI_SHIFT                4
#define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_GRPPRI_SHIFT))&DMA_DCHPRI10_GRPPRI_MASK)
#define DMA_DCHPRI10_DPA_MASK                    0x40u
#define DMA_DCHPRI10_DPA_SHIFT                   6
#define DMA_DCHPRI10_ECP_MASK                    0x80u
#define DMA_DCHPRI10_ECP_SHIFT                   7
/* DCHPRI9 Bit Fields */
#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
#define DMA_DCHPRI9_CHPRI_SHIFT                  0
#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
#define DMA_DCHPRI9_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI9_GRPPRI_SHIFT                 4
#define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_GRPPRI_SHIFT))&DMA_DCHPRI9_GRPPRI_MASK)
#define DMA_DCHPRI9_DPA_MASK                     0x40u
#define DMA_DCHPRI9_DPA_SHIFT                    6
#define DMA_DCHPRI9_ECP_MASK                     0x80u
#define DMA_DCHPRI9_ECP_SHIFT                    7
/* DCHPRI8 Bit Fields */
#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
#define DMA_DCHPRI8_CHPRI_SHIFT                  0
#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
#define DMA_DCHPRI8_GRPPRI_MASK                  0x30u
#define DMA_DCHPRI8_GRPPRI_SHIFT                 4
#define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_GRPPRI_SHIFT))&DMA_DCHPRI8_GRPPRI_MASK)
#define DMA_DCHPRI8_DPA_MASK                     0x40u
#define DMA_DCHPRI8_DPA_SHIFT                    6
#define DMA_DCHPRI8_ECP_MASK                     0x80u
#define DMA_DCHPRI8_ECP_SHIFT                    7
/* DCHPRI15 Bit Fields */
#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
#define DMA_DCHPRI15_CHPRI_SHIFT                 0
#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
#define DMA_DCHPRI15_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI15_GRPPRI_SHIFT                4
#define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_GRPPRI_SHIFT))&DMA_DCHPRI15_GRPPRI_MASK)
#define DMA_DCHPRI15_DPA_MASK                    0x40u
#define DMA_DCHPRI15_DPA_SHIFT                   6
#define DMA_DCHPRI15_ECP_MASK                    0x80u
#define DMA_DCHPRI15_ECP_SHIFT                   7
/* DCHPRI14 Bit Fields */
#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
#define DMA_DCHPRI14_CHPRI_SHIFT                 0
#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
#define DMA_DCHPRI14_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI14_GRPPRI_SHIFT                4
#define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_GRPPRI_SHIFT))&DMA_DCHPRI14_GRPPRI_MASK)
#define DMA_DCHPRI14_DPA_MASK                    0x40u
#define DMA_DCHPRI14_DPA_SHIFT                   6
#define DMA_DCHPRI14_ECP_MASK                    0x80u
#define DMA_DCHPRI14_ECP_SHIFT                   7
/* DCHPRI13 Bit Fields */
#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
#define DMA_DCHPRI13_CHPRI_SHIFT                 0
#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
#define DMA_DCHPRI13_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI13_GRPPRI_SHIFT                4
#define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_GRPPRI_SHIFT))&DMA_DCHPRI13_GRPPRI_MASK)
#define DMA_DCHPRI13_DPA_MASK                    0x40u
#define DMA_DCHPRI13_DPA_SHIFT                   6
#define DMA_DCHPRI13_ECP_MASK                    0x80u
#define DMA_DCHPRI13_ECP_SHIFT                   7
/* DCHPRI12 Bit Fields */
#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
#define DMA_DCHPRI12_CHPRI_SHIFT                 0
#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
#define DMA_DCHPRI12_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI12_GRPPRI_SHIFT                4
#define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_GRPPRI_SHIFT))&DMA_DCHPRI12_GRPPRI_MASK)
#define DMA_DCHPRI12_DPA_MASK                    0x40u
#define DMA_DCHPRI12_DPA_SHIFT                   6
#define DMA_DCHPRI12_ECP_MASK                    0x80u
#define DMA_DCHPRI12_ECP_SHIFT                   7
/* DCHPRI19 Bit Fields */
#define DMA_DCHPRI19_CHPRI_MASK                  0xFu
#define DMA_DCHPRI19_CHPRI_SHIFT                 0
#define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI19_CHPRI_SHIFT))&DMA_DCHPRI19_CHPRI_MASK)
#define DMA_DCHPRI19_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI19_GRPPRI_SHIFT                4
#define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI19_GRPPRI_SHIFT))&DMA_DCHPRI19_GRPPRI_MASK)
#define DMA_DCHPRI19_DPA_MASK                    0x40u
#define DMA_DCHPRI19_DPA_SHIFT                   6
#define DMA_DCHPRI19_ECP_MASK                    0x80u
#define DMA_DCHPRI19_ECP_SHIFT                   7
/* DCHPRI18 Bit Fields */
#define DMA_DCHPRI18_CHPRI_MASK                  0xFu
#define DMA_DCHPRI18_CHPRI_SHIFT                 0
#define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI18_CHPRI_SHIFT))&DMA_DCHPRI18_CHPRI_MASK)
#define DMA_DCHPRI18_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI18_GRPPRI_SHIFT                4
#define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI18_GRPPRI_SHIFT))&DMA_DCHPRI18_GRPPRI_MASK)
#define DMA_DCHPRI18_DPA_MASK                    0x40u
#define DMA_DCHPRI18_DPA_SHIFT                   6
#define DMA_DCHPRI18_ECP_MASK                    0x80u
#define DMA_DCHPRI18_ECP_SHIFT                   7
/* DCHPRI17 Bit Fields */
#define DMA_DCHPRI17_CHPRI_MASK                  0xFu
#define DMA_DCHPRI17_CHPRI_SHIFT                 0
#define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI17_CHPRI_SHIFT))&DMA_DCHPRI17_CHPRI_MASK)
#define DMA_DCHPRI17_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI17_GRPPRI_SHIFT                4
#define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI17_GRPPRI_SHIFT))&DMA_DCHPRI17_GRPPRI_MASK)
#define DMA_DCHPRI17_DPA_MASK                    0x40u
#define DMA_DCHPRI17_DPA_SHIFT                   6
#define DMA_DCHPRI17_ECP_MASK                    0x80u
#define DMA_DCHPRI17_ECP_SHIFT                   7
/* DCHPRI16 Bit Fields */
#define DMA_DCHPRI16_CHPRI_MASK                  0xFu
#define DMA_DCHPRI16_CHPRI_SHIFT                 0
#define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI16_CHPRI_SHIFT))&DMA_DCHPRI16_CHPRI_MASK)
#define DMA_DCHPRI16_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI16_GRPPRI_SHIFT                4
#define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI16_GRPPRI_SHIFT))&DMA_DCHPRI16_GRPPRI_MASK)
#define DMA_DCHPRI16_DPA_MASK                    0x40u
#define DMA_DCHPRI16_DPA_SHIFT                   6
#define DMA_DCHPRI16_ECP_MASK                    0x80u
#define DMA_DCHPRI16_ECP_SHIFT                   7
/* DCHPRI23 Bit Fields */
#define DMA_DCHPRI23_CHPRI_MASK                  0xFu
#define DMA_DCHPRI23_CHPRI_SHIFT                 0
#define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI23_CHPRI_SHIFT))&DMA_DCHPRI23_CHPRI_MASK)
#define DMA_DCHPRI23_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI23_GRPPRI_SHIFT                4
#define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI23_GRPPRI_SHIFT))&DMA_DCHPRI23_GRPPRI_MASK)
#define DMA_DCHPRI23_DPA_MASK                    0x40u
#define DMA_DCHPRI23_DPA_SHIFT                   6
#define DMA_DCHPRI23_ECP_MASK                    0x80u
#define DMA_DCHPRI23_ECP_SHIFT                   7
/* DCHPRI22 Bit Fields */
#define DMA_DCHPRI22_CHPRI_MASK                  0xFu
#define DMA_DCHPRI22_CHPRI_SHIFT                 0
#define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI22_CHPRI_SHIFT))&DMA_DCHPRI22_CHPRI_MASK)
#define DMA_DCHPRI22_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI22_GRPPRI_SHIFT                4
#define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI22_GRPPRI_SHIFT))&DMA_DCHPRI22_GRPPRI_MASK)
#define DMA_DCHPRI22_DPA_MASK                    0x40u
#define DMA_DCHPRI22_DPA_SHIFT                   6
#define DMA_DCHPRI22_ECP_MASK                    0x80u
#define DMA_DCHPRI22_ECP_SHIFT                   7
/* DCHPRI21 Bit Fields */
#define DMA_DCHPRI21_CHPRI_MASK                  0xFu
#define DMA_DCHPRI21_CHPRI_SHIFT                 0
#define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI21_CHPRI_SHIFT))&DMA_DCHPRI21_CHPRI_MASK)
#define DMA_DCHPRI21_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI21_GRPPRI_SHIFT                4
#define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI21_GRPPRI_SHIFT))&DMA_DCHPRI21_GRPPRI_MASK)
#define DMA_DCHPRI21_DPA_MASK                    0x40u
#define DMA_DCHPRI21_DPA_SHIFT                   6
#define DMA_DCHPRI21_ECP_MASK                    0x80u
#define DMA_DCHPRI21_ECP_SHIFT                   7
/* DCHPRI20 Bit Fields */
#define DMA_DCHPRI20_CHPRI_MASK                  0xFu
#define DMA_DCHPRI20_CHPRI_SHIFT                 0
#define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI20_CHPRI_SHIFT))&DMA_DCHPRI20_CHPRI_MASK)
#define DMA_DCHPRI20_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI20_GRPPRI_SHIFT                4
#define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI20_GRPPRI_SHIFT))&DMA_DCHPRI20_GRPPRI_MASK)
#define DMA_DCHPRI20_DPA_MASK                    0x40u
#define DMA_DCHPRI20_DPA_SHIFT                   6
#define DMA_DCHPRI20_ECP_MASK                    0x80u
#define DMA_DCHPRI20_ECP_SHIFT                   7
/* DCHPRI27 Bit Fields */
#define DMA_DCHPRI27_CHPRI_MASK                  0xFu
#define DMA_DCHPRI27_CHPRI_SHIFT                 0
#define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI27_CHPRI_SHIFT))&DMA_DCHPRI27_CHPRI_MASK)
#define DMA_DCHPRI27_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI27_GRPPRI_SHIFT                4
#define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI27_GRPPRI_SHIFT))&DMA_DCHPRI27_GRPPRI_MASK)
#define DMA_DCHPRI27_DPA_MASK                    0x40u
#define DMA_DCHPRI27_DPA_SHIFT                   6
#define DMA_DCHPRI27_ECP_MASK                    0x80u
#define DMA_DCHPRI27_ECP_SHIFT                   7
/* DCHPRI26 Bit Fields */
#define DMA_DCHPRI26_CHPRI_MASK                  0xFu
#define DMA_DCHPRI26_CHPRI_SHIFT                 0
#define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI26_CHPRI_SHIFT))&DMA_DCHPRI26_CHPRI_MASK)
#define DMA_DCHPRI26_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI26_GRPPRI_SHIFT                4
#define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI26_GRPPRI_SHIFT))&DMA_DCHPRI26_GRPPRI_MASK)
#define DMA_DCHPRI26_DPA_MASK                    0x40u
#define DMA_DCHPRI26_DPA_SHIFT                   6
#define DMA_DCHPRI26_ECP_MASK                    0x80u
#define DMA_DCHPRI26_ECP_SHIFT                   7
/* DCHPRI25 Bit Fields */
#define DMA_DCHPRI25_CHPRI_MASK                  0xFu
#define DMA_DCHPRI25_CHPRI_SHIFT                 0
#define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI25_CHPRI_SHIFT))&DMA_DCHPRI25_CHPRI_MASK)
#define DMA_DCHPRI25_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI25_GRPPRI_SHIFT                4
#define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI25_GRPPRI_SHIFT))&DMA_DCHPRI25_GRPPRI_MASK)
#define DMA_DCHPRI25_DPA_MASK                    0x40u
#define DMA_DCHPRI25_DPA_SHIFT                   6
#define DMA_DCHPRI25_ECP_MASK                    0x80u
#define DMA_DCHPRI25_ECP_SHIFT                   7
/* DCHPRI24 Bit Fields */
#define DMA_DCHPRI24_CHPRI_MASK                  0xFu
#define DMA_DCHPRI24_CHPRI_SHIFT                 0
#define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI24_CHPRI_SHIFT))&DMA_DCHPRI24_CHPRI_MASK)
#define DMA_DCHPRI24_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI24_GRPPRI_SHIFT                4
#define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI24_GRPPRI_SHIFT))&DMA_DCHPRI24_GRPPRI_MASK)
#define DMA_DCHPRI24_DPA_MASK                    0x40u
#define DMA_DCHPRI24_DPA_SHIFT                   6
#define DMA_DCHPRI24_ECP_MASK                    0x80u
#define DMA_DCHPRI24_ECP_SHIFT                   7
/* DCHPRI31 Bit Fields */
#define DMA_DCHPRI31_CHPRI_MASK                  0xFu
#define DMA_DCHPRI31_CHPRI_SHIFT                 0
#define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI31_CHPRI_SHIFT))&DMA_DCHPRI31_CHPRI_MASK)
#define DMA_DCHPRI31_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI31_GRPPRI_SHIFT                4
#define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI31_GRPPRI_SHIFT))&DMA_DCHPRI31_GRPPRI_MASK)
#define DMA_DCHPRI31_DPA_MASK                    0x40u
#define DMA_DCHPRI31_DPA_SHIFT                   6
#define DMA_DCHPRI31_ECP_MASK                    0x80u
#define DMA_DCHPRI31_ECP_SHIFT                   7
/* DCHPRI30 Bit Fields */
#define DMA_DCHPRI30_CHPRI_MASK                  0xFu
#define DMA_DCHPRI30_CHPRI_SHIFT                 0
#define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI30_CHPRI_SHIFT))&DMA_DCHPRI30_CHPRI_MASK)
#define DMA_DCHPRI30_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI30_GRPPRI_SHIFT                4
#define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI30_GRPPRI_SHIFT))&DMA_DCHPRI30_GRPPRI_MASK)
#define DMA_DCHPRI30_DPA_MASK                    0x40u
#define DMA_DCHPRI30_DPA_SHIFT                   6
#define DMA_DCHPRI30_ECP_MASK                    0x80u
#define DMA_DCHPRI30_ECP_SHIFT                   7
/* DCHPRI29 Bit Fields */
#define DMA_DCHPRI29_CHPRI_MASK                  0xFu
#define DMA_DCHPRI29_CHPRI_SHIFT                 0
#define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI29_CHPRI_SHIFT))&DMA_DCHPRI29_CHPRI_MASK)
#define DMA_DCHPRI29_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI29_GRPPRI_SHIFT                4
#define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI29_GRPPRI_SHIFT))&DMA_DCHPRI29_GRPPRI_MASK)
#define DMA_DCHPRI29_DPA_MASK                    0x40u
#define DMA_DCHPRI29_DPA_SHIFT                   6
#define DMA_DCHPRI29_ECP_MASK                    0x80u
#define DMA_DCHPRI29_ECP_SHIFT                   7
/* DCHPRI28 Bit Fields */
#define DMA_DCHPRI28_CHPRI_MASK                  0xFu
#define DMA_DCHPRI28_CHPRI_SHIFT                 0
#define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI28_CHPRI_SHIFT))&DMA_DCHPRI28_CHPRI_MASK)
#define DMA_DCHPRI28_GRPPRI_MASK                 0x30u
#define DMA_DCHPRI28_GRPPRI_SHIFT                4
#define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI28_GRPPRI_SHIFT))&DMA_DCHPRI28_GRPPRI_MASK)
#define DMA_DCHPRI28_DPA_MASK                    0x40u
#define DMA_DCHPRI28_DPA_SHIFT                   6
#define DMA_DCHPRI28_ECP_MASK                    0x80u
#define DMA_DCHPRI28_ECP_SHIFT                   7
/* SADDR Bit Fields */
#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
#define DMA_SADDR_SADDR_SHIFT                    0
#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
/* SOFF Bit Fields */
#define DMA_SOFF_SOFF_MASK                       0xFFFFu
#define DMA_SOFF_SOFF_SHIFT                      0
#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
/* ATTR Bit Fields */
#define DMA_ATTR_DSIZE_MASK                      0x7u
#define DMA_ATTR_DSIZE_SHIFT                     0
#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK                       0xF8u
#define DMA_ATTR_DMOD_SHIFT                      3
#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK                      0x700u
#define DMA_ATTR_SSIZE_SHIFT                     8
#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK                       0xF800u
#define DMA_ATTR_SMOD_SHIFT                      11
#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
/* NBYTES_MLNO Bit Fields */
#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
/* NBYTES_MLOFFNO Bit Fields */
#define DMA_NBYTES_MLOFFNO_NBYTES_OE_MASK        0x3FFFFFFFu
#define DMA_NBYTES_MLOFFNO_NBYTES_OE_SHIFT       0
#define DMA_NBYTES_MLOFFNO_NBYTES_OE(x)          (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_OE_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_OE_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
/* NBYTES_MLOFFYES Bit Fields */
#define DMA_NBYTES_MLOFFYES_NBYTES_OD_MASK       0x3FFu
#define DMA_NBYTES_MLOFFYES_NBYTES_OD_SHIFT      0
#define DMA_NBYTES_MLOFFYES_NBYTES_OD(x)         (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_OD_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_OD_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
/* SLAST Bit Fields */
#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
#define DMA_SLAST_SLAST_SHIFT                    0
#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
/* DADDR Bit Fields */
#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
#define DMA_DADDR_DADDR_SHIFT                    0
#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
/* DOFF Bit Fields */
#define DMA_DOFF_DOFF_MASK                       0xFFFFu
#define DMA_DOFF_DOFF_SHIFT                      0
#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
/* CITER_ELINKNO Bit Fields */
#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
#define DMA_CITER_ELINKNO_CITER_SHIFT            0
#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
/* CITER_ELINKYES Bit Fields */
#define DMA_CITER_ELINKYES_CITER_LE_MASK         0x1FFu
#define DMA_CITER_ELINKYES_CITER_LE_SHIFT        0
#define DMA_CITER_ELINKYES_CITER_LE(x)           (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_LE_SHIFT))&DMA_CITER_ELINKYES_CITER_LE_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK           0x3E00u
#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
/* DLAST_SGA Bit Fields */
#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
/* CSR Bit Fields */
#define DMA_CSR_START_MASK                       0x1u
#define DMA_CSR_START_SHIFT                      0
#define DMA_CSR_INTMAJOR_MASK                    0x2u
#define DMA_CSR_INTMAJOR_SHIFT                   1
#define DMA_CSR_INTHALF_MASK                     0x4u
#define DMA_CSR_INTHALF_SHIFT                    2
#define DMA_CSR_DREQ_MASK                        0x8u
#define DMA_CSR_DREQ_SHIFT                       3
#define DMA_CSR_ESG_MASK                         0x10u
#define DMA_CSR_ESG_SHIFT                        4
#define DMA_CSR_MAJORELINK_MASK                  0x20u
#define DMA_CSR_MAJORELINK_SHIFT                 5
#define DMA_CSR_ACTIVE_MASK                      0x40u
#define DMA_CSR_ACTIVE_SHIFT                     6
#define DMA_CSR_DONE_MASK                        0x80u
#define DMA_CSR_DONE_SHIFT                       7
#define DMA_CSR_MAJORLINKCH_MASK                 0x1F00u
#define DMA_CSR_MAJORLINKCH_SHIFT                8
#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK                         0xC000u
#define DMA_CSR_BWC_SHIFT                        14
#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
/* BITER_ELINKNO Bit Fields */
#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
#define DMA_BITER_ELINKNO_BITER_SHIFT            0
#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
/* BITER_ELINKYES Bit Fields */
#define DMA_BITER_ELINKYES_BITER_LE_MASK         0x1FFu
#define DMA_BITER_ELINKYES_BITER_LE_SHIFT        0
#define DMA_BITER_ELINKYES_BITER_LE(x)           (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_LE_SHIFT))&DMA_BITER_ELINKYES_BITER_LE_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK           0x3E00u
#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
#define DMA_BITER_ELINKYES_ELINK_SHIFT           15

/**
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE                                (0x40018000u)
/** Peripheral DMA0 base pointer */
#define DMA0                                     ((DMA_Type *)DMA0_BASE)
/** Peripheral DMA1 base address */
#define DMA1_BASE                                (0x40098000u)
/** Peripheral DMA1 base pointer */
#define DMA1                                     ((DMA_Type *)DMA1_BASE)
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASES                                { DMA0, DMA1 }

/**
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMAMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
 * @{
 */

/** DMAMUX - Register Layout Typedef */
typedef struct {
  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
} DMAMUX_Type;

/* ----------------------------------------------------------------------------
   -- DMAMUX Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
 * @{
 */

/* CHCFG Bit Fields */
#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
#define DMAMUX_CHCFG_SOURCE_SHIFT                0
#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
#define DMAMUX_CHCFG_TRIG_SHIFT                  6
#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT                  7

/**
 * @}
 */ /* end of group DMAMUX_Register_Masks */


/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX0 base address */
#define DMAMUX0_BASE                             (0x40024000u)
/** Peripheral DMAMUX0 base pointer */
#define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
/** Peripheral DMAMUX1 base address */
#define DMAMUX1_BASE                             (0x40025000u)
/** Peripheral DMAMUX1 base pointer */
#define DMAMUX1                                  ((DMAMUX_Type *)DMAMUX1_BASE)
/** Peripheral DMAMUX2 base address */
#define DMAMUX2_BASE                             (0x400A1000u)
/** Peripheral DMAMUX2 base pointer */
#define DMAMUX2                                  ((DMAMUX_Type *)DMAMUX2_BASE)
/** Peripheral DMAMUX3 base address */
#define DMAMUX3_BASE                             (0x400A2000u)
/** Peripheral DMAMUX3 base pointer */
#define DMAMUX3                                  ((DMAMUX_Type *)DMAMUX3_BASE)
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASES                             { DMAMUX0, DMAMUX1, DMAMUX2, DMAMUX3 }

/**
 * @}
 */ /* end of group DMAMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ENET Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
 * @{
 */

/** ENET - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4];
  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
       uint8_t RESERVED_1[4];
  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
       uint8_t RESERVED_2[12];
  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
       uint8_t RESERVED_3[24];
  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
       uint8_t RESERVED_4[28];
  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
       uint8_t RESERVED_5[28];
  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
       uint8_t RESERVED_6[60];
  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
       uint8_t RESERVED_7[28];
  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
       uint8_t RESERVED_8[40];
  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
       uint8_t RESERVED_9[28];
  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
       uint8_t RESERVED_10[56];
  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
       uint8_t RESERVED_11[4];
  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
       uint8_t RESERVED_12[12];
  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
       uint8_t RESERVED_13[56];
  __IO uint32_t RMON_T_DROP;                       /**< Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200 */
  __IO uint32_t RMON_T_PACKETS;                    /**< RMON Tx packet count (RMON_T_PACKETS), offset: 0x204 */
  __IO uint32_t RMON_T_BC_PKT;                     /**< RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208 */
  __IO uint32_t RMON_T_MC_PKT;                     /**< RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C */
  __IO uint32_t RMON_T_CRC_ALIGN;                  /**< RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210 */
  __IO uint32_t RMON_T_UNDERSIZE;                  /**< RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214 */
  __IO uint32_t RMON_T_OVERSIZE;                   /**< RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */
  __IO uint32_t RMON_T_FRAG;                       /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */
  __IO uint32_t RMON_T_JAB;                        /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */
  __IO uint32_t RMON_T_COL;                        /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */
  __IO uint32_t RMON_T_P64;                        /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */
  __IO uint32_t RMON_T_P65TO127;                   /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */
  __IO uint32_t RMON_T_P128TO255;                  /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */
  __IO uint32_t RMON_T_P256TO511;                  /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */
  __IO uint32_t RMON_T_P512TO1023;                 /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */
  __IO uint32_t RMON_T_P1024TO2047;                /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */
  __IO uint32_t RMON_T_P_GTE2048;                  /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */
  __IO uint32_t RMON_T_OCTETS;                     /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */
  __IO uint32_t IEEE_T_DROP;                       /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */
  __IO uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */
  __IO uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */
  __IO uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */
  __IO uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */
  __IO uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */
  __IO uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */
  __IO uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */
  __IO uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */
  __IO uint32_t IEEE_T_SQE;                        /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */
  __IO uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */
  __IO uint32_t IEEE_T_OCTETS_OK;                  /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */
       uint8_t RESERVED_14[12];
  __IO uint32_t RMON_R_PACKETS;                    /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */
  __IO uint32_t RMON_R_BC_PKT;                     /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */
  __IO uint32_t RMON_R_MC_PKT;                     /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */
  __IO uint32_t RMON_R_CRC_ALIGN;                  /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */
  __IO uint32_t RMON_R_UNDERSIZE;                  /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */
  __IO uint32_t RMON_R_OVERSIZE;                   /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */
  __IO uint32_t RMON_R_FRAG;                       /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */
  __IO uint32_t RMON_R_JAB;                        /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */
  __IO uint32_t RMON_R_RESVD_0;                    /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */
  __IO uint32_t RMON_R_P64;                        /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */
  __IO uint32_t RMON_R_P65TO127;                   /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */
  __IO uint32_t RMON_R_P128TO255;                  /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */
  __IO uint32_t RMON_R_P256TO511;                  /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */
  __IO uint32_t RMON_R_P512TO1023;                 /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */
  __IO uint32_t RMON_R_P1024TO2047;                /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */
  __IO uint32_t RMON_R_P_GTE2048;                  /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */
  __IO uint32_t RMON_R_OCTETS;                     /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */
  __IO uint32_t RMON_R_DROP;                       /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */
  __IO uint32_t RMON_R_FRAME_OK;                   /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */
  __IO uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */
  __IO uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */
  __IO uint32_t IEEE_R_MACERR;                     /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */
  __IO uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */
  __IO uint32_t IEEE_R_OCTETS_OK;                  /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */
       uint8_t RESERVED_15[284];
  __IO uint32_t ATCR;                              /**< Timer Control Register, offset: 0x400 */
  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
  __IO uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
       uint8_t RESERVED_16[488];
  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
  struct {                                         /* offset: 0x608, array step: 0x8 */
    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
  } CHANNEL[4];
} ENET_Type;

/* ----------------------------------------------------------------------------
   -- ENET Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ENET_Register_Masks ENET Register Masks
 * @{
 */

/* EIR Bit Fields */
#define ENET_EIR_TS_TIMER_MASK                   0x8000u
#define ENET_EIR_TS_TIMER_SHIFT                  15
#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
#define ENET_EIR_TS_AVAIL_SHIFT                  16
#define ENET_EIR_WAKEUP_MASK                     0x20000u
#define ENET_EIR_WAKEUP_SHIFT                    17
#define ENET_EIR_PLR_MASK                        0x40000u
#define ENET_EIR_PLR_SHIFT                       18
#define ENET_EIR_UN_MASK                         0x80000u
#define ENET_EIR_UN_SHIFT                        19
#define ENET_EIR_RL_MASK                         0x100000u
#define ENET_EIR_RL_SHIFT                        20
#define ENET_EIR_LC_MASK                         0x200000u
#define ENET_EIR_LC_SHIFT                        21
#define ENET_EIR_EBERR_MASK                      0x400000u
#define ENET_EIR_EBERR_SHIFT                     22
#define ENET_EIR_MII_MASK                        0x800000u
#define ENET_EIR_MII_SHIFT                       23
#define ENET_EIR_RXB_MASK                        0x1000000u
#define ENET_EIR_RXB_SHIFT                       24
#define ENET_EIR_RXF_MASK                        0x2000000u
#define ENET_EIR_RXF_SHIFT                       25
#define ENET_EIR_TXB_MASK                        0x4000000u
#define ENET_EIR_TXB_SHIFT                       26
#define ENET_EIR_TXF_MASK                        0x8000000u
#define ENET_EIR_TXF_SHIFT                       27
#define ENET_EIR_GRA_MASK                        0x10000000u
#define ENET_EIR_GRA_SHIFT                       28
#define ENET_EIR_BABT_MASK                       0x20000000u
#define ENET_EIR_BABT_SHIFT                      29
#define ENET_EIR_BABR_MASK                       0x40000000u
#define ENET_EIR_BABR_SHIFT                      30
/* EIMR Bit Fields */
#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
#define ENET_EIMR_TS_TIMER_SHIFT                 15
#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
#define ENET_EIMR_TS_AVAIL_SHIFT                 16
#define ENET_EIMR_WAKEUP_MASK                    0x20000u
#define ENET_EIMR_WAKEUP_SHIFT                   17
#define ENET_EIMR_PLR_MASK                       0x40000u
#define ENET_EIMR_PLR_SHIFT                      18
#define ENET_EIMR_UN_MASK                        0x80000u
#define ENET_EIMR_UN_SHIFT                       19
#define ENET_EIMR_RL_MASK                        0x100000u
#define ENET_EIMR_RL_SHIFT                       20
#define ENET_EIMR_LC_MASK                        0x200000u
#define ENET_EIMR_LC_SHIFT                       21
#define ENET_EIMR_EBERR_MASK                     0x400000u
#define ENET_EIMR_EBERR_SHIFT                    22
#define ENET_EIMR_MII_MASK                       0x800000u
#define ENET_EIMR_MII_SHIFT                      23
#define ENET_EIMR_RXB_MASK                       0x1000000u
#define ENET_EIMR_RXB_SHIFT                      24
#define ENET_EIMR_RXF_MASK                       0x2000000u
#define ENET_EIMR_RXF_SHIFT                      25
#define ENET_EIMR_TXB_MASK                       0x4000000u
#define ENET_EIMR_TXB_SHIFT                      26
#define ENET_EIMR_TXF_MASK                       0x8000000u
#define ENET_EIMR_TXF_SHIFT                      27
#define ENET_EIMR_GRA_MASK                       0x10000000u
#define ENET_EIMR_GRA_SHIFT                      28
#define ENET_EIMR_BABT_MASK                      0x20000000u
#define ENET_EIMR_BABT_SHIFT                     29
#define ENET_EIMR_BABR_MASK                      0x40000000u
#define ENET_EIMR_BABR_SHIFT                     30
/* RDAR Bit Fields */
#define ENET_RDAR_RDAR_MASK                      0x1000000u
#define ENET_RDAR_RDAR_SHIFT                     24
/* TDAR Bit Fields */
#define ENET_TDAR_TDAR_MASK                      0x1000000u
#define ENET_TDAR_TDAR_SHIFT                     24
/* ECR Bit Fields */
#define ENET_ECR_RESET_MASK                      0x1u
#define ENET_ECR_RESET_SHIFT                     0
#define ENET_ECR_ETHEREN_MASK                    0x2u
#define ENET_ECR_ETHEREN_SHIFT                   1
#define ENET_ECR_MAGICEN_MASK                    0x4u
#define ENET_ECR_MAGICEN_SHIFT                   2
#define ENET_ECR_SLEEP_MASK                      0x8u
#define ENET_ECR_SLEEP_SHIFT                     3
#define ENET_ECR_EN1588_MASK                     0x10u
#define ENET_ECR_EN1588_SHIFT                    4
#define ENET_ECR_DBGEN_MASK                      0x40u
#define ENET_ECR_DBGEN_SHIFT                     6
#define ENET_ECR_STOPEN_MASK                     0x80u
#define ENET_ECR_STOPEN_SHIFT                    7
#define ENET_ECR_DBSWP_MASK                      0x100u
#define ENET_ECR_DBSWP_SHIFT                     8
/* MMFR Bit Fields */
#define ENET_MMFR_DATA_MASK                      0xFFFFu
#define ENET_MMFR_DATA_SHIFT                     0
#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
#define ENET_MMFR_TA_MASK                        0x30000u
#define ENET_MMFR_TA_SHIFT                       16
#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
#define ENET_MMFR_RA_MASK                        0x7C0000u
#define ENET_MMFR_RA_SHIFT                       18
#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
#define ENET_MMFR_PA_MASK                        0xF800000u
#define ENET_MMFR_PA_SHIFT                       23
#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
#define ENET_MMFR_OP_MASK                        0x30000000u
#define ENET_MMFR_OP_SHIFT                       28
#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
#define ENET_MMFR_ST_MASK                        0xC0000000u
#define ENET_MMFR_ST_SHIFT                       30
#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
/* MSCR Bit Fields */
#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
#define ENET_MSCR_MII_SPEED_SHIFT                1
#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
#define ENET_MSCR_DIS_PRE_MASK                   0x80u
#define ENET_MSCR_DIS_PRE_SHIFT                  7
#define ENET_MSCR_HOLDTIME_MASK                  0x700u
#define ENET_MSCR_HOLDTIME_SHIFT                 8
#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
/* MIBC Bit Fields */
#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
#define ENET_MIBC_MIB_CLEAR_SHIFT                29
#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
#define ENET_MIBC_MIB_IDLE_SHIFT                 30
#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
#define ENET_MIBC_MIB_DIS_SHIFT                  31
/* RCR Bit Fields */
#define ENET_RCR_LOOP_MASK                       0x1u
#define ENET_RCR_LOOP_SHIFT                      0
#define ENET_RCR_DRT_MASK                        0x2u
#define ENET_RCR_DRT_SHIFT                       1
#define ENET_RCR_MII_MODE_MASK                   0x4u
#define ENET_RCR_MII_MODE_SHIFT                  2
#define ENET_RCR_PROM_MASK                       0x8u
#define ENET_RCR_PROM_SHIFT                      3
#define ENET_RCR_BC_REJ_MASK                     0x10u
#define ENET_RCR_BC_REJ_SHIFT                    4
#define ENET_RCR_FCE_MASK                        0x20u
#define ENET_RCR_FCE_SHIFT                       5
#define ENET_RCR_RMII_MODE_MASK                  0x100u
#define ENET_RCR_RMII_MODE_SHIFT                 8
#define ENET_RCR_RMII_10T_MASK                   0x200u
#define ENET_RCR_RMII_10T_SHIFT                  9
#define ENET_RCR_PADEN_MASK                      0x1000u
#define ENET_RCR_PADEN_SHIFT                     12
#define ENET_RCR_PAUFWD_MASK                     0x2000u
#define ENET_RCR_PAUFWD_SHIFT                    13
#define ENET_RCR_CRCFWD_MASK                     0x4000u
#define ENET_RCR_CRCFWD_SHIFT                    14
#define ENET_RCR_CFEN_MASK                       0x8000u
#define ENET_RCR_CFEN_SHIFT                      15
#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
#define ENET_RCR_MAX_FL_SHIFT                    16
#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
#define ENET_RCR_NLC_MASK                        0x40000000u
#define ENET_RCR_NLC_SHIFT                       30
#define ENET_RCR_GRS_MASK                        0x80000000u
#define ENET_RCR_GRS_SHIFT                       31
/* TCR Bit Fields */
#define ENET_TCR_GTS_MASK                        0x1u
#define ENET_TCR_GTS_SHIFT                       0
#define ENET_TCR_FDEN_MASK                       0x4u
#define ENET_TCR_FDEN_SHIFT                      2
#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
#define ENET_TCR_TFC_PAUSE_SHIFT                 3
#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
#define ENET_TCR_RFC_PAUSE_SHIFT                 4
#define ENET_TCR_ADDSEL_MASK                     0xE0u
#define ENET_TCR_ADDSEL_SHIFT                    5
#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
#define ENET_TCR_ADDINS_MASK                     0x100u
#define ENET_TCR_ADDINS_SHIFT                    8
#define ENET_TCR_CRCFWD_MASK                     0x200u
#define ENET_TCR_CRCFWD_SHIFT                    9
/* PALR Bit Fields */
#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
#define ENET_PALR_PADDR1_SHIFT                   0
#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
/* PAUR Bit Fields */
#define ENET_PAUR_TYPE_MASK                      0xFFFFu
#define ENET_PAUR_TYPE_SHIFT                     0
#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
#define ENET_PAUR_PADDR2_SHIFT                   16
#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
/* OPD Bit Fields */
#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
#define ENET_OPD_PAUSE_DUR_SHIFT                 0
#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
#define ENET_OPD_OPCODE_SHIFT                    16
#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
/* IAUR Bit Fields */
#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
#define ENET_IAUR_IADDR1_SHIFT                   0
#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
/* IALR Bit Fields */
#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
#define ENET_IALR_IADDR2_SHIFT                   0
#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
/* GAUR Bit Fields */
#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
#define ENET_GAUR_GADDR1_SHIFT                   0
#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
/* GALR Bit Fields */
#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
#define ENET_GALR_GADDR2_SHIFT                   0
#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
/* TFWR Bit Fields */
#define ENET_TFWR_TFWR_MASK                      0x3Fu
#define ENET_TFWR_TFWR_SHIFT                     0
#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
#define ENET_TFWR_STRFWD_MASK                    0x100u
#define ENET_TFWR_STRFWD_SHIFT                   8
/* RDSR Bit Fields */
#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
#define ENET_RDSR_R_DES_START_SHIFT              3
#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
/* TDSR Bit Fields */
#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
#define ENET_TDSR_X_DES_START_SHIFT              3
#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
/* MRBR Bit Fields */
#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
/* RSFL Bit Fields */
#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
/* RSEM Bit Fields */
#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
/* RAEM Bit Fields */
#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
/* RAFL Bit Fields */
#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
/* TSEM Bit Fields */
#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
/* TAEM Bit Fields */
#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
/* TAFL Bit Fields */
#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
/* TIPG Bit Fields */
#define ENET_TIPG_IPG_MASK                       0x1Fu
#define ENET_TIPG_IPG_SHIFT                      0
#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
/* FTRL Bit Fields */
#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
#define ENET_FTRL_TRUNC_FL_SHIFT                 0
#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
/* TACC Bit Fields */
#define ENET_TACC_SHIFT16_MASK                   0x1u
#define ENET_TACC_SHIFT16_SHIFT                  0
#define ENET_TACC_IPCHK_MASK                     0x8u
#define ENET_TACC_IPCHK_SHIFT                    3
#define ENET_TACC_PROCHK_MASK                    0x10u
#define ENET_TACC_PROCHK_SHIFT                   4
/* RACC Bit Fields */
#define ENET_RACC_PADREM_MASK                    0x1u
#define ENET_RACC_PADREM_SHIFT                   0
#define ENET_RACC_IPDIS_MASK                     0x2u
#define ENET_RACC_IPDIS_SHIFT                    1
#define ENET_RACC_PRODIS_MASK                    0x4u
#define ENET_RACC_PRODIS_SHIFT                   2
#define ENET_RACC_LINEDIS_MASK                   0x40u
#define ENET_RACC_LINEDIS_SHIFT                  6
#define ENET_RACC_SHIFT16_MASK                   0x80u
#define ENET_RACC_SHIFT16_SHIFT                  7
/* ATCR Bit Fields */
#define ENET_ATCR_EN_MASK                        0x1u
#define ENET_ATCR_EN_SHIFT                       0
#define ENET_ATCR_OFFEN_MASK                     0x4u
#define ENET_ATCR_OFFEN_SHIFT                    2
#define ENET_ATCR_OFFRST_MASK                    0x8u
#define ENET_ATCR_OFFRST_SHIFT                   3
#define ENET_ATCR_PEREN_MASK                     0x10u
#define ENET_ATCR_PEREN_SHIFT                    4
#define ENET_ATCR_PINPER_MASK                    0x80u
#define ENET_ATCR_PINPER_SHIFT                   7
#define ENET_ATCR_RESTART_MASK                   0x200u
#define ENET_ATCR_RESTART_SHIFT                  9
#define ENET_ATCR_CAPTURE_MASK                   0x800u
#define ENET_ATCR_CAPTURE_SHIFT                  11
#define ENET_ATCR_SLAVE_MASK                     0x2000u
#define ENET_ATCR_SLAVE_SHIFT                    13
/* ATVR Bit Fields */
#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
#define ENET_ATVR_ATIME_SHIFT                    0
#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
/* ATOFF Bit Fields */
#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
#define ENET_ATOFF_OFFSET_SHIFT                  0
#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
/* ATPER Bit Fields */
#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
#define ENET_ATPER_PERIOD_SHIFT                  0
#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
/* ATCOR Bit Fields */
#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
#define ENET_ATCOR_COR_SHIFT                     0
#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
/* ATINC Bit Fields */
#define ENET_ATINC_INC_MASK                      0x7Fu
#define ENET_ATINC_INC_SHIFT                     0
#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
#define ENET_ATINC_INC_CORR_SHIFT                8
#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
/* ATSTMP Bit Fields */
#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
/* TGSR Bit Fields */
#define ENET_TGSR_TF0_MASK                       0x1u
#define ENET_TGSR_TF0_SHIFT                      0
#define ENET_TGSR_TF1_MASK                       0x2u
#define ENET_TGSR_TF1_SHIFT                      1
#define ENET_TGSR_TF2_MASK                       0x4u
#define ENET_TGSR_TF2_SHIFT                      2
#define ENET_TGSR_TF3_MASK                       0x8u
#define ENET_TGSR_TF3_SHIFT                      3
/* TCSR Bit Fields */
#define ENET_TCSR_TDRE_MASK                      0x1u
#define ENET_TCSR_TDRE_SHIFT                     0
#define ENET_TCSR_TMODE_MASK                     0x3Cu
#define ENET_TCSR_TMODE_SHIFT                    2
#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
#define ENET_TCSR_TIE_MASK                       0x40u
#define ENET_TCSR_TIE_SHIFT                      6
#define ENET_TCSR_TF_MASK                        0x80u
#define ENET_TCSR_TF_SHIFT                       7
/* TCCR Bit Fields */
#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
#define ENET_TCCR_TCC_SHIFT                      0
#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)

/**
 * @}
 */ /* end of group ENET_Register_Masks */


/* ENET - Peripheral instance base addresses */
/** Peripheral ENET0 base address */
#define ENET0_BASE                               (0x400D0000u)
/** Peripheral ENET0 base pointer */
#define ENET0                                    ((ENET_Type *)ENET0_BASE)
/** Peripheral ENET1 base address */
#define ENET1_BASE                               (0x400D1000u)
/** Peripheral ENET1 base pointer */
#define ENET1                                    ((ENET_Type *)ENET1_BASE)
/** Array initializer of ENET peripheral base pointers */
#define ENET_BASES                               { ENET0, ENET1 }

/**
 * @}
 */ /* end of group ENET_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ESAI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer
 * @{
 */

/** ESAI - Register Layout Typedef */
typedef struct {
  __O  uint32_t ETDR;                              /**< ESAI Transmit Data Register, offset: 0x0 */
  __I  uint32_t ERDR;                              /**< ESAI Receive Data Register, offset: 0x4 */
  __IO uint32_t ECR;                               /**< ESAI Control Register, offset: 0x8 */
  __I  uint32_t ESR;                               /**< ESAI Status Register, offset: 0xC */
  __IO uint32_t TFCR;                              /**< Transmit FIFO Configuration Register, offset: 0x10 */
  __I  uint32_t TFSR;                              /**< Transmit FIFO Status Register, offset: 0x14 */
  __IO uint32_t RFCR;                              /**< Receive FIFO Configuration Register, offset: 0x18 */
  __I  uint32_t RFSR;                              /**< Receive FIFO Status Register, offset: 0x1C */
       uint8_t RESERVED_0[96];
  __IO uint32_t TX[6];                             /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */
  __IO uint32_t TSR;                               /**< ESAI Transmit Slot Register, offset: 0x98 */
       uint8_t RESERVED_1[4];
  __I  uint32_t RX[4];                             /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_2[28];
  __I  uint32_t SAISR;                             /**< Serial Audio Interface Status Register, offset: 0xCC */
  __IO uint32_t SAICR;                             /**< Serial Audio Interface Control Register, offset: 0xD0 */
  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xD4 */
  __IO uint32_t TCCR;                              /**< Transmit Clock Control Register, offset: 0xD8 */
  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0xDC */
  __IO uint32_t RCCR;                              /**< Receive Clock Control Register, offset: 0xE0 */
  __IO uint32_t TSMA;                              /**< Transmit Slot Mask Register A, offset: 0xE4 */
  __IO uint32_t TSMB;                              /**< Transmit Slot Mask Register B, offset: 0xE8 */
  __IO uint32_t RSMA;                              /**< Receive Slot Mask Register A, offset: 0xEC */
  __IO uint32_t RSMB;                              /**< Receive Slot Mask Register B, offset: 0xF0 */
       uint8_t RESERVED_3[4];
  __IO uint32_t PRRC;                              /**< Port C Direction Register, offset: 0xF8 */
  __IO uint32_t PCRC;                              /**< Port C Control Register, offset: 0xFC */
} ESAI_Type;

/* ----------------------------------------------------------------------------
   -- ESAI Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ESAI_Register_Masks ESAI Register Masks
 * @{
 */

/* ETDR Bit Fields */
#define ESAI_ETDR_ETDR_MASK                      0xFFFFFFFFu
#define ESAI_ETDR_ETDR_SHIFT                     0
#define ESAI_ETDR_ETDR(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_ETDR_ETDR_SHIFT))&ESAI_ETDR_ETDR_MASK)
/* ERDR Bit Fields */
#define ESAI_ERDR_ERDR_MASK                      0xFFFFFFFFu
#define ESAI_ERDR_ERDR_SHIFT                     0
#define ESAI_ERDR_ERDR(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_ERDR_ERDR_SHIFT))&ESAI_ERDR_ERDR_MASK)
/* ECR Bit Fields */
#define ESAI_ECR_ESAIEN_MASK                     0x1u
#define ESAI_ECR_ESAIEN_SHIFT                    0
#define ESAI_ECR_ERST_MASK                       0x2u
#define ESAI_ECR_ERST_SHIFT                      1
#define ESAI_ECR_ERO_MASK                        0x10000u
#define ESAI_ECR_ERO_SHIFT                       16
#define ESAI_ECR_ERI_MASK                        0x20000u
#define ESAI_ECR_ERI_SHIFT                       17
#define ESAI_ECR_ETO_MASK                        0x40000u
#define ESAI_ECR_ETO_SHIFT                       18
#define ESAI_ECR_ETI_MASK                        0x80000u
#define ESAI_ECR_ETI_SHIFT                       19
/* ESR Bit Fields */
#define ESAI_ESR_RD_MASK                         0x1u
#define ESAI_ESR_RD_SHIFT                        0
#define ESAI_ESR_RED_MASK                        0x2u
#define ESAI_ESR_RED_SHIFT                       1
#define ESAI_ESR_RDE_MASK                        0x4u
#define ESAI_ESR_RDE_SHIFT                       2
#define ESAI_ESR_RLS_MASK                        0x8u
#define ESAI_ESR_RLS_SHIFT                       3
#define ESAI_ESR_TD_MASK                         0x10u
#define ESAI_ESR_TD_SHIFT                        4
#define ESAI_ESR_TED_MASK                        0x20u
#define ESAI_ESR_TED_SHIFT                       5
#define ESAI_ESR_TDE_MASK                        0x40u
#define ESAI_ESR_TDE_SHIFT                       6
#define ESAI_ESR_TLS_MASK                        0x80u
#define ESAI_ESR_TLS_SHIFT                       7
#define ESAI_ESR_TFE_MASK                        0x100u
#define ESAI_ESR_TFE_SHIFT                       8
#define ESAI_ESR_RFF_MASK                        0x200u
#define ESAI_ESR_RFF_SHIFT                       9
#define ESAI_ESR_TINIT_MASK                      0x400u
#define ESAI_ESR_TINIT_SHIFT                     10
/* TFCR Bit Fields */
#define ESAI_TFCR_TFE_MASK                       0x1u
#define ESAI_TFCR_TFE_SHIFT                      0
#define ESAI_TFCR_TFR_MASK                       0x2u
#define ESAI_TFCR_TFR_SHIFT                      1
#define ESAI_TFCR_TE0_MASK                       0x4u
#define ESAI_TFCR_TE0_SHIFT                      2
#define ESAI_TFCR_TE1_MASK                       0x8u
#define ESAI_TFCR_TE1_SHIFT                      3
#define ESAI_TFCR_TE2_MASK                       0x10u
#define ESAI_TFCR_TE2_SHIFT                      4
#define ESAI_TFCR_TE3_MASK                       0x20u
#define ESAI_TFCR_TE3_SHIFT                      5
#define ESAI_TFCR_TE4_MASK                       0x40u
#define ESAI_TFCR_TE4_SHIFT                      6
#define ESAI_TFCR_TE5_MASK                       0x80u
#define ESAI_TFCR_TE5_SHIFT                      7
#define ESAI_TFCR_TFWM_MASK                      0xFF00u
#define ESAI_TFCR_TFWM_SHIFT                     8
#define ESAI_TFCR_TFWM(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_TFCR_TFWM_SHIFT))&ESAI_TFCR_TFWM_MASK)
#define ESAI_TFCR_TWA_MASK                       0x70000u
#define ESAI_TFCR_TWA_SHIFT                      16
#define ESAI_TFCR_TWA(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TFCR_TWA_SHIFT))&ESAI_TFCR_TWA_MASK)
#define ESAI_TFCR_TIEN_MASK                      0x80000u
#define ESAI_TFCR_TIEN_SHIFT                     19
/* TFSR Bit Fields */
#define ESAI_TFSR_TFCNT_MASK                     0xFFu
#define ESAI_TFSR_TFCNT_SHIFT                    0
#define ESAI_TFSR_TFCNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_TFCNT_SHIFT))&ESAI_TFSR_TFCNT_MASK)
#define ESAI_TFSR_NTFI_MASK                      0x700u
#define ESAI_TFSR_NTFI_SHIFT                     8
#define ESAI_TFSR_NTFI(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_NTFI_SHIFT))&ESAI_TFSR_NTFI_MASK)
#define ESAI_TFSR_NTFO_MASK                      0x7000u
#define ESAI_TFSR_NTFO_SHIFT                     12
#define ESAI_TFSR_NTFO(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_NTFO_SHIFT))&ESAI_TFSR_NTFO_MASK)
/* RFCR Bit Fields */
#define ESAI_RFCR_RFE_MASK                       0x1u
#define ESAI_RFCR_RFE_SHIFT                      0
#define ESAI_RFCR_RFR_MASK                       0x2u
#define ESAI_RFCR_RFR_SHIFT                      1
#define ESAI_RFCR_RE0_MASK                       0x4u
#define ESAI_RFCR_RE0_SHIFT                      2
#define ESAI_RFCR_RE1_MASK                       0x8u
#define ESAI_RFCR_RE1_SHIFT                      3
#define ESAI_RFCR_RE2_MASK                       0x10u
#define ESAI_RFCR_RE2_SHIFT                      4
#define ESAI_RFCR_RE3_MASK                       0x20u
#define ESAI_RFCR_RE3_SHIFT                      5
#define ESAI_RFCR_RFWM_MASK                      0xFF00u
#define ESAI_RFCR_RFWM_SHIFT                     8
#define ESAI_RFCR_RFWM(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_RFCR_RFWM_SHIFT))&ESAI_RFCR_RFWM_MASK)
#define ESAI_RFCR_RWA_MASK                       0x70000u
#define ESAI_RFCR_RWA_SHIFT                      16
#define ESAI_RFCR_RWA(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RFCR_RWA_SHIFT))&ESAI_RFCR_RWA_MASK)
#define ESAI_RFCR_REXT_MASK                      0x80000u
#define ESAI_RFCR_REXT_SHIFT                     19
/* RFSR Bit Fields */
#define ESAI_RFSR_RFCNT_MASK                     0xFFu
#define ESAI_RFSR_RFCNT_SHIFT                    0
#define ESAI_RFSR_RFCNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_RFCNT_SHIFT))&ESAI_RFSR_RFCNT_MASK)
#define ESAI_RFSR_NRFO_MASK                      0x300u
#define ESAI_RFSR_NRFO_SHIFT                     8
#define ESAI_RFSR_NRFO(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_NRFO_SHIFT))&ESAI_RFSR_NRFO_MASK)
#define ESAI_RFSR_NRFI_MASK                      0x3000u
#define ESAI_RFSR_NRFI_SHIFT                     12
#define ESAI_RFSR_NRFI(x)                        (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_NRFI_SHIFT))&ESAI_RFSR_NRFI_MASK)
/* TX Bit Fields */
#define ESAI_TX_TXn_MASK                         0xFFFFFFu
#define ESAI_TX_TXn_SHIFT                        0
#define ESAI_TX_TXn(x)                           (((uint32_t)(((uint32_t)(x))<<ESAI_TX_TXn_SHIFT))&ESAI_TX_TXn_MASK)
/* TSR Bit Fields */
#define ESAI_TSR_TSR_MASK                        0xFFFFFFu
#define ESAI_TSR_TSR_SHIFT                       0
#define ESAI_TSR_TSR(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_TSR_TSR_SHIFT))&ESAI_TSR_TSR_MASK)
/* RX Bit Fields */
#define ESAI_RX_RXn_MASK                         0xFFFFFFu
#define ESAI_RX_RXn_SHIFT                        0
#define ESAI_RX_RXn(x)                           (((uint32_t)(((uint32_t)(x))<<ESAI_RX_RXn_SHIFT))&ESAI_RX_RXn_MASK)
/* SAISR Bit Fields */
#define ESAI_SAISR_IF0_MASK                      0x1u
#define ESAI_SAISR_IF0_SHIFT                     0
#define ESAI_SAISR_IF1_MASK                      0x2u
#define ESAI_SAISR_IF1_SHIFT                     1
#define ESAI_SAISR_IF2_MASK                      0x4u
#define ESAI_SAISR_IF2_SHIFT                     2
#define ESAI_SAISR_RFS_MASK                      0x40u
#define ESAI_SAISR_RFS_SHIFT                     6
#define ESAI_SAISR_ROE_MASK                      0x80u
#define ESAI_SAISR_ROE_SHIFT                     7
#define ESAI_SAISR_RDF_MASK                      0x100u
#define ESAI_SAISR_RDF_SHIFT                     8
#define ESAI_SAISR_REDF_MASK                     0x200u
#define ESAI_SAISR_REDF_SHIFT                    9
#define ESAI_SAISR_RODF_MASK                     0x400u
#define ESAI_SAISR_RODF_SHIFT                    10
#define ESAI_SAISR_TFS_MASK                      0x2000u
#define ESAI_SAISR_TFS_SHIFT                     13
#define ESAI_SAISR_TUE_MASK                      0x4000u
#define ESAI_SAISR_TUE_SHIFT                     14
#define ESAI_SAISR_TDE_MASK                      0x8000u
#define ESAI_SAISR_TDE_SHIFT                     15
#define ESAI_SAISR_TEDE_MASK                     0x10000u
#define ESAI_SAISR_TEDE_SHIFT                    16
#define ESAI_SAISR_TODFE_MASK                    0x20000u
#define ESAI_SAISR_TODFE_SHIFT                   17
/* SAICR Bit Fields */
#define ESAI_SAICR_OF0_MASK                      0x1u
#define ESAI_SAICR_OF0_SHIFT                     0
#define ESAI_SAICR_OF1_MASK                      0x2u
#define ESAI_SAICR_OF1_SHIFT                     1
#define ESAI_SAICR_OF2_MASK                      0x4u
#define ESAI_SAICR_OF2_SHIFT                     2
#define ESAI_SAICR_SYN_MASK                      0x40u
#define ESAI_SAICR_SYN_SHIFT                     6
#define ESAI_SAICR_TEBE_MASK                     0x80u
#define ESAI_SAICR_TEBE_SHIFT                    7
#define ESAI_SAICR_ALC_MASK                      0x100u
#define ESAI_SAICR_ALC_SHIFT                     8
/* TCR Bit Fields */
#define ESAI_TCR_TE0_MASK                        0x1u
#define ESAI_TCR_TE0_SHIFT                       0
#define ESAI_TCR_TE1_MASK                        0x2u
#define ESAI_TCR_TE1_SHIFT                       1
#define ESAI_TCR_TE2_MASK                        0x4u
#define ESAI_TCR_TE2_SHIFT                       2
#define ESAI_TCR_TE3_MASK                        0x8u
#define ESAI_TCR_TE3_SHIFT                       3
#define ESAI_TCR_TE4_MASK                        0x10u
#define ESAI_TCR_TE4_SHIFT                       4
#define ESAI_TCR_TE5_MASK                        0x20u
#define ESAI_TCR_TE5_SHIFT                       5
#define ESAI_TCR_TSHFD_MASK                      0x40u
#define ESAI_TCR_TSHFD_SHIFT                     6
#define ESAI_TCR_TWA_MASK                        0x80u
#define ESAI_TCR_TWA_SHIFT                       7
#define ESAI_TCR_TMOD_MASK                       0x300u
#define ESAI_TCR_TMOD_SHIFT                      8
#define ESAI_TCR_TMOD(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCR_TMOD_SHIFT))&ESAI_TCR_TMOD_MASK)
#define ESAI_TCR_TSWS_MASK                       0x7C00u
#define ESAI_TCR_TSWS_SHIFT                      10
#define ESAI_TCR_TSWS(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCR_TSWS_SHIFT))&ESAI_TCR_TSWS_MASK)
#define ESAI_TCR_TFSL_MASK                       0x8000u
#define ESAI_TCR_TFSL_SHIFT                      15
#define ESAI_TCR_TFSR_MASK                       0x10000u
#define ESAI_TCR_TFSR_SHIFT                      16
#define ESAI_TCR_PADC_MASK                       0x20000u
#define ESAI_TCR_PADC_SHIFT                      17
#define ESAI_TCR_TPR_MASK                        0x80000u
#define ESAI_TCR_TPR_SHIFT                       19
#define ESAI_TCR_TEIE_MASK                       0x100000u
#define ESAI_TCR_TEIE_SHIFT                      20
#define ESAI_TCR_TEDIE_MASK                      0x200000u
#define ESAI_TCR_TEDIE_SHIFT                     21
#define ESAI_TCR_TIE_MASK                        0x400000u
#define ESAI_TCR_TIE_SHIFT                       22
#define ESAI_TCR_TLIE_MASK                       0x800000u
#define ESAI_TCR_TLIE_SHIFT                      23
/* TCCR Bit Fields */
#define ESAI_TCCR_TPM_MASK                       0xFFu
#define ESAI_TCCR_TPM_SHIFT                      0
#define ESAI_TCCR_TPM(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TPM_SHIFT))&ESAI_TCCR_TPM_MASK)
#define ESAI_TCCR_TPSR_MASK                      0x100u
#define ESAI_TCCR_TPSR_SHIFT                     8
#define ESAI_TCCR_TDC_MASK                       0x3E00u
#define ESAI_TCCR_TDC_SHIFT                      9
#define ESAI_TCCR_TDC(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TDC_SHIFT))&ESAI_TCCR_TDC_MASK)
#define ESAI_TCCR_TFP_MASK                       0x3C000u
#define ESAI_TCCR_TFP_SHIFT                      14
#define ESAI_TCCR_TFP(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TFP_SHIFT))&ESAI_TCCR_TFP_MASK)
#define ESAI_TCCR_TCKP_MASK                      0x40000u
#define ESAI_TCCR_TCKP_SHIFT                     18
#define ESAI_TCCR_TFSP_MASK                      0x80000u
#define ESAI_TCCR_TFSP_SHIFT                     19
#define ESAI_TCCR_THCKP_MASK                     0x100000u
#define ESAI_TCCR_THCKP_SHIFT                    20
#define ESAI_TCCR_TCKD_MASK                      0x200000u
#define ESAI_TCCR_TCKD_SHIFT                     21
#define ESAI_TCCR_TFSD_MASK                      0x400000u
#define ESAI_TCCR_TFSD_SHIFT                     22
#define ESAI_TCCR_THCKD_MASK                     0x800000u
#define ESAI_TCCR_THCKD_SHIFT                    23
/* RCR Bit Fields */
#define ESAI_RCR_RE0_MASK                        0x1u
#define ESAI_RCR_RE0_SHIFT                       0
#define ESAI_RCR_RE1_MASK                        0x2u
#define ESAI_RCR_RE1_SHIFT                       1
#define ESAI_RCR_RE2_MASK                        0x4u
#define ESAI_RCR_RE2_SHIFT                       2
#define ESAI_RCR_RE3_MASK                        0x8u
#define ESAI_RCR_RE3_SHIFT                       3
#define ESAI_RCR_RSHFD_MASK                      0x40u
#define ESAI_RCR_RSHFD_SHIFT                     6
#define ESAI_RCR_RWA_MASK                        0x80u
#define ESAI_RCR_RWA_SHIFT                       7
#define ESAI_RCR_RMOD_MASK                       0x300u
#define ESAI_RCR_RMOD_SHIFT                      8
#define ESAI_RCR_RMOD(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCR_RMOD_SHIFT))&ESAI_RCR_RMOD_MASK)
#define ESAI_RCR_RSWS_MASK                       0x7C00u
#define ESAI_RCR_RSWS_SHIFT                      10
#define ESAI_RCR_RSWS(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCR_RSWS_SHIFT))&ESAI_RCR_RSWS_MASK)
#define ESAI_RCR_RFSL_MASK                       0x8000u
#define ESAI_RCR_RFSL_SHIFT                      15
#define ESAI_RCR_RFSR_MASK                       0x10000u
#define ESAI_RCR_RFSR_SHIFT                      16
#define ESAI_RCR_RPR_MASK                        0x80000u
#define ESAI_RCR_RPR_SHIFT                       19
#define ESAI_RCR_REIE_MASK                       0x100000u
#define ESAI_RCR_REIE_SHIFT                      20
#define ESAI_RCR_REDIE_MASK                      0x200000u
#define ESAI_RCR_REDIE_SHIFT                     21
#define ESAI_RCR_RIE_MASK                        0x400000u
#define ESAI_RCR_RIE_SHIFT                       22
#define ESAI_RCR_RLIE_MASK                       0x800000u
#define ESAI_RCR_RLIE_SHIFT                      23
/* RCCR Bit Fields */
#define ESAI_RCCR_RPM_MASK                       0xFFu
#define ESAI_RCCR_RPM_SHIFT                      0
#define ESAI_RCCR_RPM(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RPM_SHIFT))&ESAI_RCCR_RPM_MASK)
#define ESAI_RCCR_RPSP_MASK                      0x100u
#define ESAI_RCCR_RPSP_SHIFT                     8
#define ESAI_RCCR_RDC_MASK                       0x3E00u
#define ESAI_RCCR_RDC_SHIFT                      9
#define ESAI_RCCR_RDC(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RDC_SHIFT))&ESAI_RCCR_RDC_MASK)
#define ESAI_RCCR_RFP_MASK                       0x3C000u
#define ESAI_RCCR_RFP_SHIFT                      14
#define ESAI_RCCR_RFP(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RFP_SHIFT))&ESAI_RCCR_RFP_MASK)
#define ESAI_RCCR_RCKP_MASK                      0x40000u
#define ESAI_RCCR_RCKP_SHIFT                     18
#define ESAI_RCCR_RFSP_MASK                      0x80000u
#define ESAI_RCCR_RFSP_SHIFT                     19
#define ESAI_RCCR_RHCKP_MASK                     0x100000u
#define ESAI_RCCR_RHCKP_SHIFT                    20
#define ESAI_RCCR_RCKD_MASK                      0x200000u
#define ESAI_RCCR_RCKD_SHIFT                     21
#define ESAI_RCCR_RFSD_MASK                      0x400000u
#define ESAI_RCCR_RFSD_SHIFT                     22
#define ESAI_RCCR_RHCKD_MASK                     0x800000u
#define ESAI_RCCR_RHCKD_SHIFT                    23
/* TSMA Bit Fields */
#define ESAI_TSMA_TS_MASK                        0xFFFFu
#define ESAI_TSMA_TS_SHIFT                       0
#define ESAI_TSMA_TS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_TSMA_TS_SHIFT))&ESAI_TSMA_TS_MASK)
/* TSMB Bit Fields */
#define ESAI_TSMB_TS_MASK                        0xFFFFu
#define ESAI_TSMB_TS_SHIFT                       0
#define ESAI_TSMB_TS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_TSMB_TS_SHIFT))&ESAI_TSMB_TS_MASK)
/* RSMA Bit Fields */
#define ESAI_RSMA_RS_MASK                        0xFFFFu
#define ESAI_RSMA_RS_SHIFT                       0
#define ESAI_RSMA_RS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_RSMA_RS_SHIFT))&ESAI_RSMA_RS_MASK)
/* RSMB Bit Fields */
#define ESAI_RSMB_RS_MASK                        0xFFFFu
#define ESAI_RSMB_RS_SHIFT                       0
#define ESAI_RSMB_RS(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_RSMB_RS_SHIFT))&ESAI_RSMB_RS_MASK)
/* PRRC Bit Fields */
#define ESAI_PRRC_PDC_MASK                       0xFFFu
#define ESAI_PRRC_PDC_SHIFT                      0
#define ESAI_PRRC_PDC(x)                         (((uint32_t)(((uint32_t)(x))<<ESAI_PRRC_PDC_SHIFT))&ESAI_PRRC_PDC_MASK)
/* PCRC Bit Fields */
#define ESAI_PCRC_PC_MASK                        0xFFFu
#define ESAI_PCRC_PC_SHIFT                       0
#define ESAI_PCRC_PC(x)                          (((uint32_t)(((uint32_t)(x))<<ESAI_PCRC_PC_SHIFT))&ESAI_PCRC_PC_MASK)

/**
 * @}
 */ /* end of group ESAI_Register_Masks */


/* ESAI - Peripheral instance base addresses */
/** Peripheral ESAI base address */
#define ESAI_BASE                                (0x40062000u)
/** Peripheral ESAI base pointer */
#define ESAI                                     ((ESAI_Type *)ESAI_BASE)
/** Array initializer of ESAI peripheral base pointers */
#define ESAI_BASES                               { ESAI }

/**
 * @}
 */ /* end of group ESAI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ESW Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ESW_Peripheral_Access_Layer ESW Peripheral Access Layer
 * @{
 */

/** ESW - Register Layout Typedef */
typedef struct {
  __I  uint32_t REV;                               /**< Revision, offset: 0x0 */
  __IO uint32_t SCR;                               /**< Scratch register, offset: 0x4 */
  __IO uint32_t PER;                               /**< Port enable register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t VLANV;                             /**< VLAN verify, offset: 0x10 */
  __IO uint32_t DBCR;                              /**< Default broadcast resolution, offset: 0x14 */
  __IO uint32_t DMCR;                              /**< Default multicast resolution, offset: 0x18 */
  __IO uint32_t BKLR;                              /**< Blocking and learning enable, offset: 0x1C */
  __IO uint32_t BMPC;                              /**< Bridge management port configuration, offset: 0x20 */
  __IO uint32_t MODE;                              /**< Mode configuration, offset: 0x24 */
  __IO uint32_t VIMSEL;                            /**< VLAN input manipulation select, offset: 0x28 */
  __IO uint32_t VOMSEL;                            /**< VLAN output manipulation select, offset: 0x2C */
  __IO uint32_t VIMEN;                             /**< VLAN input manipulation enable, offset: 0x30 */
  __IO uint32_t VID;                               /**< VLAN tag ID, offset: 0x34 */
       uint8_t RESERVED_1[8];
  __IO uint32_t MCR;                               /**< Mirror control register, offset: 0x40 */
  __IO uint32_t EGMAP;                             /**< Egress port definitions, offset: 0x44 */
  __IO uint32_t INGMAP;                            /**< Ingress port definitions, offset: 0x48 */
  __IO uint32_t INGSAL;                            /**< Ingress source MAC address low, offset: 0x4C */
  __IO uint32_t INGSAH;                            /**< Ingress source MAC address high, offset: 0x50 */
  __IO uint32_t INGDAL;                            /**< Ingress destination MAC address low, offset: 0x54 */
  __IO uint32_t INGDAH;                            /**< Ingress destination MAC address high, offset: 0x58 */
  __IO uint32_t EGSAL;                             /**< Egress source MAC address low, offset: 0x5C */
  __IO uint32_t EGSAH;                             /**< Egress source MAC address high, offset: 0x60 */
  __IO uint32_t EGDAL;                             /**< Egress destination MAC address low, offset: 0x64 */
  __IO uint32_t EGDAH;                             /**< Egress destination MAC address high, offset: 0x68 */
  __IO uint32_t MCVAL;                             /**< Mirror count value, offset: 0x6C */
       uint8_t RESERVED_2[16];
  __IO uint32_t MMSR;                              /**< Memory manager status, offset: 0x80 */
  __IO uint32_t LMT;                               /**< Low memory threshold, offset: 0x84 */
  __IO uint32_t LFC;                               /**< Lowest number of free cells, offset: 0x88 */
  __I  uint32_t PCSR;                              /**< Port congestion status, offset: 0x8C */
  __I  uint32_t IOSR;                              /**< Switch input and output interface status, offset: 0x90 */
  __IO uint32_t QWT;                               /**< Queue weights, offset: 0x94 */
       uint8_t RESERVED_3[4];
  __IO uint32_t P0BCT;                             /**< Port 0 Backpressure Congestion Threshold, offset: 0x9C */
       uint8_t RESERVED_4[28];
  __IO uint32_t FFEN;                              /**< Port 0 forced forwarding enable, offset: 0xBC */
  __IO uint32_t PSNP1;                             /**< Port snooping registers, offset: 0xC0 */
  __IO uint32_t PSNP2;                             /**< Port snooping registers, offset: 0xC4 */
  __IO uint32_t PSNP3;                             /**< Port snooping registers, offset: 0xC8 */
  __IO uint32_t PSNP4;                             /**< Port snooping registers, offset: 0xCC */
  __IO uint32_t PSNP5;                             /**< Port snooping registers, offset: 0xD0 */
  __IO uint32_t PSNP6;                             /**< Port snooping registers, offset: 0xD4 */
  __IO uint32_t PSNP7;                             /**< Port snooping registers, offset: 0xD8 */
  __IO uint32_t PSNP8;                             /**< Port snooping registers, offset: 0xDC */
  __IO uint32_t IPSNP1;                            /**< IP snooping registers, offset: 0xE0 */
  __IO uint32_t IPSNP2;                            /**< IP snooping registers, offset: 0xE4 */
  __IO uint32_t IPSNP3;                            /**< IP snooping registers, offset: 0xE8 */
  __IO uint32_t IPSNP4;                            /**< IP snooping registers, offset: 0xEC */
  __IO uint32_t IPSNP5;                            /**< IP snooping registers, offset: 0xF0 */
  __IO uint32_t IPSNP6;                            /**< IP snooping registers, offset: 0xF4 */
  __IO uint32_t IPSNP7;                            /**< IP snooping registers, offset: 0xF8 */
  __IO uint32_t IPSNP8;                            /**< IP snooping registers, offset: 0xFC */
  __IO uint32_t P0VRES;                            /**< Port 0 VLAN priority resolution map, offset: 0x100 */
  __IO uint32_t P1VRES;                            /**< Port 1 VLAN priority resolution map, offset: 0x104 */
  __IO uint32_t P2VRES;                            /**< Port 2 VLAN priority resolution map, offset: 0x108 */
       uint8_t RESERVED_5[52];
  __IO uint32_t IPRES;                             /**< IPv4/v6 priority resolution table, offset: 0x140 */
       uint8_t RESERVED_6[60];
  __IO uint32_t P0RES;                             /**< Port 0 priority resolution configuration, offset: 0x180 */
  __IO uint32_t P1RES;                             /**< Port 1 priority resolution configuration, offset: 0x184 */
  __IO uint32_t P2RES;                             /**< Port 2 priority resolution configuration, offset: 0x188 */
       uint8_t RESERVED_7[116];
  __IO uint32_t P0ID;                              /**< Port 0 VLAN ID, offset: 0x200 */
  __IO uint32_t P1ID;                              /**< Port 1 VLAN ID, offset: 0x204 */
  __IO uint32_t P2ID;                              /**< Port 2 VLAN ID, offset: 0x208 */
       uint8_t RESERVED_8[116];
  __IO uint32_t VRES0;                             /**< VLAN domain resolution entry 0, offset: 0x280 */
  __IO uint32_t VRES1;                             /**< VLAN domain resolution entry 1, offset: 0x284 */
  __IO uint32_t VRES2;                             /**< VLAN domain resolution entry 2, offset: 0x288 */
  __IO uint32_t VRES3;                             /**< VLAN domain resolution entry 4, offset: 0x28C */
  __IO uint32_t VRES4;                             /**< VLAN domain resolution entry 4, offset: 0x290 */
  __IO uint32_t VRES5;                             /**< VLAN domain resolution entry 5, offset: 0x294 */
  __IO uint32_t VRES6;                             /**< VLAN domain resolution entry 6, offset: 0x298 */
  __IO uint32_t VRES7;                             /**< VLAN domain resolution entry 7, offset: 0x29C */
  __IO uint32_t VRES8;                             /**< VLAN domain resolution entry 8, offset: 0x2A0 */
  __IO uint32_t VRES9;                             /**< VLAN domain resolution entry 9, offset: 0x2A4 */
  __IO uint32_t VRES10;                            /**< VLAN domain resolution entry 10, offset: 0x2A8 */
  __IO uint32_t VRES11;                            /**< VLAN domain resolution entry 11, offset: 0x2AC */
  __IO uint32_t VRES12;                            /**< VLAN domain resolution entry 12, offset: 0x2B0 */
  __IO uint32_t VRES13;                            /**< VLAN domain resolution entry 13, offset: 0x2B4 */
  __IO uint32_t VRES14;                            /**< VLAN domain resolution entry 14, offset: 0x2B8 */
  __IO uint32_t VRES15;                            /**< VLAN domain resolution entry 15, offset: 0x2BC */
  __IO uint32_t VRES16;                            /**< VLAN domain resolution entry 16, offset: 0x2C0 */
  __IO uint32_t VRES17;                            /**< VLAN domain resolution entry 17, offset: 0x2C4 */
  __IO uint32_t VRES18;                            /**< VLAN domain resolution entry 18, offset: 0x2C8 */
  __IO uint32_t VRES19;                            /**< VLAN domain resolution entry 19, offset: 0x2CC */
  __IO uint32_t VRES20;                            /**< VLAN domain resolution entry 20, offset: 0x2D0 */
  __IO uint32_t VRES21;                            /**< VLAN domain resolution entry 21, offset: 0x2D4 */
  __IO uint32_t VRES22;                            /**< VLAN domain resolution entry 22, offset: 0x2D8 */
  __IO uint32_t VRES23;                            /**< VLAN domain resolution entry 23, offset: 0x2DC */
  __IO uint32_t VRES24;                            /**< VLAN domain resolution entry 24, offset: 0x2E0 */
  __IO uint32_t VRES25;                            /**< VLAN domain resolution entry 25, offset: 0x2E4 */
  __IO uint32_t VRES26;                            /**< VLAN domain resolution entry 26, offset: 0x2E8 */
  __IO uint32_t VRES27;                            /**< VLAN domain resolution entry 27, offset: 0x2EC */
  __IO uint32_t VRES28;                            /**< VLAN domain resolution entry 28, offset: 0x2F0 */
  __IO uint32_t VRES29;                            /**< VLAN domain resolution entry 29, offset: 0x2F4 */
  __IO uint32_t VRES30;                            /**< VLAN domain resolution entry 30, offset: 0x2F8 */
  __IO uint32_t VRES31;                            /**< VLAN domain resolution entry 31, offset: 0x2FC */
  __I  uint32_t DISCN;                             /**< Number of discarded frames, offset: 0x300 */
  __I  uint32_t DISCB;                             /**< Bytes of discarded frames, offset: 0x304 */
  __I  uint32_t NDISCN;                            /**< Number of non-discarded frames, offset: 0x308 */
  __I  uint32_t NDISCB;                            /**< Bytes of non-discarded frames, offset: 0x30C */
  __I  uint32_t P0OQC;                             /**< Port 0 output queue congestion, offset: 0x310 */
  __I  uint32_t P0MVID;                            /**< Port 0 mismatching VLAN ID, offset: 0x314 */
  __I  uint32_t P0MVTAG;                           /**< Port 0 missing VLAN tag, offset: 0x318 */
  __I  uint32_t P0BL;                              /**< Port 0 blocked, offset: 0x31C */
  __I  uint32_t P1OQC;                             /**< Port 1 output queue congestion, offset: 0x320 */
  __I  uint32_t P1MVID;                            /**< Port 1 mismatching VLAN ID, offset: 0x324 */
  __I  uint32_t P1MVTAG;                           /**< Port 1 missing VLAN tag, offset: 0x328 */
  __I  uint32_t P1BL;                              /**< Port 1 blocked, offset: 0x32C */
  __I  uint32_t P2OQC;                             /**< Port 2 output queue congestion, offset: 0x330 */
  __I  uint32_t P2MVID;                            /**< Port 2 mismatching VLAN ID, offset: 0x334 */
  __I  uint32_t P2MVTAG;                           /**< Port 2 missing VLAN tag, offset: 0x338 */
  __I  uint32_t P2BL;                              /**< Port 2 blocked, offset: 0x33C */
       uint8_t RESERVED_9[192];
  __IO uint32_t ISR;                               /**< Interrupt status register, offset: 0x400 */
  __IO uint32_t IMR;                               /**< Interrupt mask register, offset: 0x404 */
  __IO uint32_t RDSR;                              /**< Receive descriptor ring pointer, offset: 0x408 */
  __IO uint32_t TDSR;                              /**< Transmit descriptor ring pointer, offset: 0x40C */
  __IO uint32_t MRBR;                              /**< Maximum receive buffer size, offset: 0x410 */
  __IO uint32_t RDAR;                              /**< Receive descriptor active, offset: 0x414 */
  __IO uint32_t TDAR;                              /**< Transmit descriptor active, offset: 0x418 */
       uint8_t RESERVED_10[228];
  __I  uint32_t LREC0;                             /**< Learning records A0 & B1, offset: 0x500 */
  __I  uint32_t LREC1;                             /**< Learning record B1, offset: 0x504 */
  __I  uint32_t LSR;                               /**< Learning data available status, offset: 0x508 */
} ESW_Type;

/* ----------------------------------------------------------------------------
   -- ESW Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup ESW_Register_Masks ESW Register Masks
 * @{
 */

/* REV Bit Fields */
#define ESW_REV_CORREV_MASK                      0xFFFFu
#define ESW_REV_CORREV_SHIFT                     0
#define ESW_REV_CORREV(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_REV_CORREV_SHIFT))&ESW_REV_CORREV_MASK)
#define ESW_REV_CSTREV_MASK                      0xFFFF0000u
#define ESW_REV_CSTREV_SHIFT                     16
#define ESW_REV_CSTREV(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_REV_CSTREV_SHIFT))&ESW_REV_CSTREV_MASK)
/* SCR Bit Fields */
#define ESW_SCR_SCRATCH_MASK                     0xFFFFFFFFu
#define ESW_SCR_SCRATCH_SHIFT                    0
#define ESW_SCR_SCRATCH(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_SCR_SCRATCH_SHIFT))&ESW_SCR_SCRATCH_MASK)
/* PER Bit Fields */
#define ESW_PER_TE0_MASK                         0x1u
#define ESW_PER_TE0_SHIFT                        0
#define ESW_PER_TE1_MASK                         0x2u
#define ESW_PER_TE1_SHIFT                        1
#define ESW_PER_TE2_MASK                         0x4u
#define ESW_PER_TE2_SHIFT                        2
#define ESW_PER_RE0_MASK                         0x10000u
#define ESW_PER_RE0_SHIFT                        16
#define ESW_PER_RE1_MASK                         0x20000u
#define ESW_PER_RE1_SHIFT                        17
#define ESW_PER_RE2_MASK                         0x40000u
#define ESW_PER_RE2_SHIFT                        18
/* VLANV Bit Fields */
#define ESW_VLANV_VV0_MASK                       0x1u
#define ESW_VLANV_VV0_SHIFT                      0
#define ESW_VLANV_VV1_MASK                       0x2u
#define ESW_VLANV_VV1_SHIFT                      1
#define ESW_VLANV_VV2_MASK                       0x4u
#define ESW_VLANV_VV2_SHIFT                      2
#define ESW_VLANV_DU0_MASK                       0x10000u
#define ESW_VLANV_DU0_SHIFT                      16
#define ESW_VLANV_DU1_MASK                       0x20000u
#define ESW_VLANV_DU1_SHIFT                      17
#define ESW_VLANV_DU2_MASK                       0x40000u
#define ESW_VLANV_DU2_SHIFT                      18
/* DBCR Bit Fields */
#define ESW_DBCR_P0_MASK                         0x1u
#define ESW_DBCR_P0_SHIFT                        0
#define ESW_DBCR_P1_MASK                         0x2u
#define ESW_DBCR_P1_SHIFT                        1
#define ESW_DBCR_P2_MASK                         0x4u
#define ESW_DBCR_P2_SHIFT                        2
/* DMCR Bit Fields */
#define ESW_DMCR_P0_MASK                         0x1u
#define ESW_DMCR_P0_SHIFT                        0
#define ESW_DMCR_P1_MASK                         0x2u
#define ESW_DMCR_P1_SHIFT                        1
#define ESW_DMCR_P2_MASK                         0x4u
#define ESW_DMCR_P2_SHIFT                        2
/* BKLR Bit Fields */
#define ESW_BKLR_BE0_MASK                        0x1u
#define ESW_BKLR_BE0_SHIFT                       0
#define ESW_BKLR_BE1_MASK                        0x2u
#define ESW_BKLR_BE1_SHIFT                       1
#define ESW_BKLR_BE2_MASK                        0x4u
#define ESW_BKLR_BE2_SHIFT                       2
#define ESW_BKLR_LD0_MASK                        0x10000u
#define ESW_BKLR_LD0_SHIFT                       16
#define ESW_BKLR_LD1_MASK                        0x20000u
#define ESW_BKLR_LD1_SHIFT                       17
#define ESW_BKLR_LD2_MASK                        0x40000u
#define ESW_BKLR_LD2_SHIFT                       18
/* BMPC Bit Fields */
#define ESW_BMPC_PORT_MASK                       0xFu
#define ESW_BMPC_PORT_SHIFT                      0
#define ESW_BMPC_PORT(x)                         (((uint32_t)(((uint32_t)(x))<<ESW_BMPC_PORT_SHIFT))&ESW_BMPC_PORT_MASK)
#define ESW_BMPC_MSGTX_MASK                      0x20u
#define ESW_BMPC_MSGTX_SHIFT                     5
#define ESW_BMPC_EN_MASK                         0x40u
#define ESW_BMPC_EN_SHIFT                        6
#define ESW_BMPC_DIS_MASK                        0x80u
#define ESW_BMPC_DIS_SHIFT                       7
#define ESW_BMPC_PRIORITY_MASK                   0xE000u
#define ESW_BMPC_PRIORITY_SHIFT                  13
#define ESW_BMPC_PRIORITY(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_BMPC_PRIORITY_SHIFT))&ESW_BMPC_PRIORITY_MASK)
#define ESW_BMPC_PORTMASK_MASK                   0x70000u
#define ESW_BMPC_PORTMASK_SHIFT                  16
#define ESW_BMPC_PORTMASK(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_BMPC_PORTMASK_SHIFT))&ESW_BMPC_PORTMASK_MASK)
/* MODE Bit Fields */
#define ESW_MODE_SWRST_MASK                      0x1u
#define ESW_MODE_SWRST_SHIFT                     0
#define ESW_MODE_SWEN_MASK                       0x2u
#define ESW_MODE_SWEN_SHIFT                      1
#define ESW_MODE_STOP_MASK                       0x80u
#define ESW_MODE_STOP_SHIFT                      7
#define ESW_MODE_CRCTRAN_MASK                    0x100u
#define ESW_MODE_CRCTRAN_SHIFT                   8
#define ESW_MODE_P0CT_MASK                       0x200u
#define ESW_MODE_P0CT_SHIFT                      9
#define ESW_MODE_STATRST_MASK                    0x80000000u
#define ESW_MODE_STATRST_SHIFT                   31
/* VIMSEL Bit Fields */
#define ESW_VIMSEL_IM0_MASK                      0x3u
#define ESW_VIMSEL_IM0_SHIFT                     0
#define ESW_VIMSEL_IM0(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_VIMSEL_IM0_SHIFT))&ESW_VIMSEL_IM0_MASK)
#define ESW_VIMSEL_IM1_MASK                      0xCu
#define ESW_VIMSEL_IM1_SHIFT                     2
#define ESW_VIMSEL_IM1(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_VIMSEL_IM1_SHIFT))&ESW_VIMSEL_IM1_MASK)
#define ESW_VIMSEL_IM2_MASK                      0x30u
#define ESW_VIMSEL_IM2_SHIFT                     4
#define ESW_VIMSEL_IM2(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_VIMSEL_IM2_SHIFT))&ESW_VIMSEL_IM2_MASK)
/* VOMSEL Bit Fields */
#define ESW_VOMSEL_OM0_MASK                      0x3u
#define ESW_VOMSEL_OM0_SHIFT                     0
#define ESW_VOMSEL_OM0(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_VOMSEL_OM0_SHIFT))&ESW_VOMSEL_OM0_MASK)
#define ESW_VOMSEL_OM1_MASK                      0xCu
#define ESW_VOMSEL_OM1_SHIFT                     2
#define ESW_VOMSEL_OM1(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_VOMSEL_OM1_SHIFT))&ESW_VOMSEL_OM1_MASK)
#define ESW_VOMSEL_OM2_MASK                      0x30u
#define ESW_VOMSEL_OM2_SHIFT                     4
#define ESW_VOMSEL_OM2(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_VOMSEL_OM2_SHIFT))&ESW_VOMSEL_OM2_MASK)
/* VIMEN Bit Fields */
#define ESW_VIMEN_EN0_MASK                       0x1u
#define ESW_VIMEN_EN0_SHIFT                      0
#define ESW_VIMEN_EN1_MASK                       0x2u
#define ESW_VIMEN_EN1_SHIFT                      1
#define ESW_VIMEN_EN2_MASK                       0x4u
#define ESW_VIMEN_EN2_SHIFT                      2
/* VID Bit Fields */
#define ESW_VID_TAG_MASK                         0xFFFFFFFFu
#define ESW_VID_TAG_SHIFT                        0
#define ESW_VID_TAG(x)                           (((uint32_t)(((uint32_t)(x))<<ESW_VID_TAG_SHIFT))&ESW_VID_TAG_MASK)
/* MCR Bit Fields */
#define ESW_MCR_PORT_MASK                        0xFu
#define ESW_MCR_PORT_SHIFT                       0
#define ESW_MCR_PORT(x)                          (((uint32_t)(((uint32_t)(x))<<ESW_MCR_PORT_SHIFT))&ESW_MCR_PORT_MASK)
#define ESW_MCR_MEN_MASK                         0x10u
#define ESW_MCR_MEN_SHIFT                        4
#define ESW_MCR_INGMAP_MASK                      0x20u
#define ESW_MCR_INGMAP_SHIFT                     5
#define ESW_MCR_EGMAP_MASK                       0x40u
#define ESW_MCR_EGMAP_SHIFT                      6
#define ESW_MCR_INGSA_MASK                       0x80u
#define ESW_MCR_INGSA_SHIFT                      7
#define ESW_MCR_INGDA_MASK                       0x100u
#define ESW_MCR_INGDA_SHIFT                      8
#define ESW_MCR_EGSA_MASK                        0x200u
#define ESW_MCR_EGSA_SHIFT                       9
#define ESW_MCR_EGDA_MASK                        0x400u
#define ESW_MCR_EGDA_SHIFT                       10
/* EGMAP Bit Fields */
#define ESW_EGMAP_EG0_MASK                       0x1u
#define ESW_EGMAP_EG0_SHIFT                      0
#define ESW_EGMAP_EG1_MASK                       0x2u
#define ESW_EGMAP_EG1_SHIFT                      1
#define ESW_EGMAP_EG2_MASK                       0x4u
#define ESW_EGMAP_EG2_SHIFT                      2
/* INGMAP Bit Fields */
#define ESW_INGMAP_ING0_MASK                     0x1u
#define ESW_INGMAP_ING0_SHIFT                    0
#define ESW_INGMAP_ING1_MASK                     0x2u
#define ESW_INGMAP_ING1_SHIFT                    1
#define ESW_INGMAP_ING2_MASK                     0x4u
#define ESW_INGMAP_ING2_SHIFT                    2
/* INGSAL Bit Fields */
#define ESW_INGSAL_ADDLOW_MASK                   0xFFFFFFFFu
#define ESW_INGSAL_ADDLOW_SHIFT                  0
#define ESW_INGSAL_ADDLOW(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_INGSAL_ADDLOW_SHIFT))&ESW_INGSAL_ADDLOW_MASK)
/* INGSAH Bit Fields */
#define ESW_INGSAH_ADDHIGH_MASK                  0xFFFFu
#define ESW_INGSAH_ADDHIGH_SHIFT                 0
#define ESW_INGSAH_ADDHIGH(x)                    (((uint32_t)(((uint32_t)(x))<<ESW_INGSAH_ADDHIGH_SHIFT))&ESW_INGSAH_ADDHIGH_MASK)
/* INGDAL Bit Fields */
#define ESW_INGDAL_ADDLOW_MASK                   0xFFFFFFFFu
#define ESW_INGDAL_ADDLOW_SHIFT                  0
#define ESW_INGDAL_ADDLOW(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_INGDAL_ADDLOW_SHIFT))&ESW_INGDAL_ADDLOW_MASK)
/* INGDAH Bit Fields */
#define ESW_INGDAH_ADDHIGH_MASK                  0xFFFFu
#define ESW_INGDAH_ADDHIGH_SHIFT                 0
#define ESW_INGDAH_ADDHIGH(x)                    (((uint32_t)(((uint32_t)(x))<<ESW_INGDAH_ADDHIGH_SHIFT))&ESW_INGDAH_ADDHIGH_MASK)
/* EGSAL Bit Fields */
#define ESW_EGSAL_ADDLOW_MASK                    0xFFFFFFFFu
#define ESW_EGSAL_ADDLOW_SHIFT                   0
#define ESW_EGSAL_ADDLOW(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_EGSAL_ADDLOW_SHIFT))&ESW_EGSAL_ADDLOW_MASK)
/* EGSAH Bit Fields */
#define ESW_EGSAH_ADDHIGH_MASK                   0xFFFFu
#define ESW_EGSAH_ADDHIGH_SHIFT                  0
#define ESW_EGSAH_ADDHIGH(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_EGSAH_ADDHIGH_SHIFT))&ESW_EGSAH_ADDHIGH_MASK)
/* EGDAL Bit Fields */
#define ESW_EGDAL_ADDLOW_MASK                    0xFFFFFFFFu
#define ESW_EGDAL_ADDLOW_SHIFT                   0
#define ESW_EGDAL_ADDLOW(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_EGDAL_ADDLOW_SHIFT))&ESW_EGDAL_ADDLOW_MASK)
/* EGDAH Bit Fields */
#define ESW_EGDAH_ADDHIGH_MASK                   0xFFFFu
#define ESW_EGDAH_ADDHIGH_SHIFT                  0
#define ESW_EGDAH_ADDHIGH(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_EGDAH_ADDHIGH_SHIFT))&ESW_EGDAH_ADDHIGH_MASK)
/* MCVAL Bit Fields */
#define ESW_MCVAL_COUNT_MASK                     0xFFu
#define ESW_MCVAL_COUNT_SHIFT                    0
#define ESW_MCVAL_COUNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_MCVAL_COUNT_SHIFT))&ESW_MCVAL_COUNT_MASK)
/* MMSR Bit Fields */
#define ESW_MMSR_BUSY_MASK                       0x1u
#define ESW_MMSR_BUSY_SHIFT                      0
#define ESW_MMSR_NOCELL_MASK                     0x2u
#define ESW_MMSR_NOCELL_SHIFT                    1
#define ESW_MMSR_MEMFULL_MASK                    0x4u
#define ESW_MMSR_MEMFULL_SHIFT                   2
#define ESW_MMSR_MFLATCH_MASK                    0x8u
#define ESW_MMSR_MFLATCH_SHIFT                   3
#define ESW_MMSR_DQGRNT_MASK                     0x40u
#define ESW_MMSR_DQGRNT_SHIFT                    6
#define ESW_MMSR_CELLS_AVAIL_MASK                0xFF0000u
#define ESW_MMSR_CELLS_AVAIL_SHIFT               16
#define ESW_MMSR_CELLS_AVAIL(x)                  (((uint32_t)(((uint32_t)(x))<<ESW_MMSR_CELLS_AVAIL_SHIFT))&ESW_MMSR_CELLS_AVAIL_MASK)
/* LMT Bit Fields */
#define ESW_LMT_THRESH_MASK                      0xFFu
#define ESW_LMT_THRESH_SHIFT                     0
#define ESW_LMT_THRESH(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_LMT_THRESH_SHIFT))&ESW_LMT_THRESH_MASK)
/* LFC Bit Fields */
#define ESW_LFC_COUNT_MASK                       0xFFFFFFFFu
#define ESW_LFC_COUNT_SHIFT                      0
#define ESW_LFC_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<ESW_LFC_COUNT_SHIFT))&ESW_LFC_COUNT_MASK)
/* PCSR Bit Fields */
#define ESW_PCSR_PC0_MASK                        0x1u
#define ESW_PCSR_PC0_SHIFT                       0
#define ESW_PCSR_PC1_MASK                        0x2u
#define ESW_PCSR_PC1_SHIFT                       1
#define ESW_PCSR_PC2_MASK                        0x4u
#define ESW_PCSR_PC2_SHIFT                       2
/* IOSR Bit Fields */
#define ESW_IOSR_OR0_MASK                        0x1u
#define ESW_IOSR_OR0_SHIFT                       0
#define ESW_IOSR_OR1_MASK                        0x2u
#define ESW_IOSR_OR1_SHIFT                       1
#define ESW_IOSR_OR2_MASK                        0x4u
#define ESW_IOSR_OR2_SHIFT                       2
#define ESW_IOSR_IR0_MASK                        0x10000u
#define ESW_IOSR_IR0_SHIFT                       16
#define ESW_IOSR_IR1_MASK                        0x20000u
#define ESW_IOSR_IR1_SHIFT                       17
#define ESW_IOSR_IR2_MASK                        0x40000u
#define ESW_IOSR_IR2_SHIFT                       18
/* QWT Bit Fields */
#define ESW_QWT_Q0WT_MASK                        0x1Fu
#define ESW_QWT_Q0WT_SHIFT                       0
#define ESW_QWT_Q0WT(x)                          (((uint32_t)(((uint32_t)(x))<<ESW_QWT_Q0WT_SHIFT))&ESW_QWT_Q0WT_MASK)
#define ESW_QWT_Q1WT_MASK                        0x1F00u
#define ESW_QWT_Q1WT_SHIFT                       8
#define ESW_QWT_Q1WT(x)                          (((uint32_t)(((uint32_t)(x))<<ESW_QWT_Q1WT_SHIFT))&ESW_QWT_Q1WT_MASK)
#define ESW_QWT_Q2WT_MASK                        0x1F0000u
#define ESW_QWT_Q2WT_SHIFT                       16
#define ESW_QWT_Q2WT(x)                          (((uint32_t)(((uint32_t)(x))<<ESW_QWT_Q2WT_SHIFT))&ESW_QWT_Q2WT_MASK)
#define ESW_QWT_Q3WT_MASK                        0x1F000000u
#define ESW_QWT_Q3WT_SHIFT                       24
#define ESW_QWT_Q3WT(x)                          (((uint32_t)(((uint32_t)(x))<<ESW_QWT_Q3WT_SHIFT))&ESW_QWT_Q3WT_MASK)
/* P0BCT Bit Fields */
#define ESW_P0BCT_THRESH_MASK                    0xFFu
#define ESW_P0BCT_THRESH_SHIFT                   0
#define ESW_P0BCT_THRESH(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_P0BCT_THRESH_SHIFT))&ESW_P0BCT_THRESH_MASK)
/* FFEN Bit Fields */
#define ESW_FFEN_FEN_MASK                        0x1u
#define ESW_FFEN_FEN_SHIFT                       0
#define ESW_FFEN_FD_MASK                         0xCu
#define ESW_FFEN_FD_SHIFT                        2
#define ESW_FFEN_FD(x)                           (((uint32_t)(((uint32_t)(x))<<ESW_FFEN_FD_SHIFT))&ESW_FFEN_FD_MASK)
/* PSNP1 Bit Fields */
#define ESW_PSNP1_EN_MASK                        0x1u
#define ESW_PSNP1_EN_SHIFT                       0
#define ESW_PSNP1_MODE_MASK                      0x6u
#define ESW_PSNP1_MODE_SHIFT                     1
#define ESW_PSNP1_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP1_MODE_SHIFT))&ESW_PSNP1_MODE_MASK)
#define ESW_PSNP1_CD_MASK                        0x8u
#define ESW_PSNP1_CD_SHIFT                       3
#define ESW_PSNP1_CS_MASK                        0x10u
#define ESW_PSNP1_CS_SHIFT                       4
#define ESW_PSNP1_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP1_PORT_COMPARE_SHIFT             16
#define ESW_PSNP1_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP1_PORT_COMPARE_SHIFT))&ESW_PSNP1_PORT_COMPARE_MASK)
/* PSNP2 Bit Fields */
#define ESW_PSNP2_EN_MASK                        0x1u
#define ESW_PSNP2_EN_SHIFT                       0
#define ESW_PSNP2_MODE_MASK                      0x6u
#define ESW_PSNP2_MODE_SHIFT                     1
#define ESW_PSNP2_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP2_MODE_SHIFT))&ESW_PSNP2_MODE_MASK)
#define ESW_PSNP2_CD_MASK                        0x8u
#define ESW_PSNP2_CD_SHIFT                       3
#define ESW_PSNP2_CS_MASK                        0x10u
#define ESW_PSNP2_CS_SHIFT                       4
#define ESW_PSNP2_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP2_PORT_COMPARE_SHIFT             16
#define ESW_PSNP2_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP2_PORT_COMPARE_SHIFT))&ESW_PSNP2_PORT_COMPARE_MASK)
/* PSNP3 Bit Fields */
#define ESW_PSNP3_EN_MASK                        0x1u
#define ESW_PSNP3_EN_SHIFT                       0
#define ESW_PSNP3_MODE_MASK                      0x6u
#define ESW_PSNP3_MODE_SHIFT                     1
#define ESW_PSNP3_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP3_MODE_SHIFT))&ESW_PSNP3_MODE_MASK)
#define ESW_PSNP3_CD_MASK                        0x8u
#define ESW_PSNP3_CD_SHIFT                       3
#define ESW_PSNP3_CS_MASK                        0x10u
#define ESW_PSNP3_CS_SHIFT                       4
#define ESW_PSNP3_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP3_PORT_COMPARE_SHIFT             16
#define ESW_PSNP3_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP3_PORT_COMPARE_SHIFT))&ESW_PSNP3_PORT_COMPARE_MASK)
/* PSNP4 Bit Fields */
#define ESW_PSNP4_EN_MASK                        0x1u
#define ESW_PSNP4_EN_SHIFT                       0
#define ESW_PSNP4_MODE_MASK                      0x6u
#define ESW_PSNP4_MODE_SHIFT                     1
#define ESW_PSNP4_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP4_MODE_SHIFT))&ESW_PSNP4_MODE_MASK)
#define ESW_PSNP4_CD_MASK                        0x8u
#define ESW_PSNP4_CD_SHIFT                       3
#define ESW_PSNP4_CS_MASK                        0x10u
#define ESW_PSNP4_CS_SHIFT                       4
#define ESW_PSNP4_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP4_PORT_COMPARE_SHIFT             16
#define ESW_PSNP4_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP4_PORT_COMPARE_SHIFT))&ESW_PSNP4_PORT_COMPARE_MASK)
/* PSNP5 Bit Fields */
#define ESW_PSNP5_EN_MASK                        0x1u
#define ESW_PSNP5_EN_SHIFT                       0
#define ESW_PSNP5_MODE_MASK                      0x6u
#define ESW_PSNP5_MODE_SHIFT                     1
#define ESW_PSNP5_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP5_MODE_SHIFT))&ESW_PSNP5_MODE_MASK)
#define ESW_PSNP5_CD_MASK                        0x8u
#define ESW_PSNP5_CD_SHIFT                       3
#define ESW_PSNP5_CS_MASK                        0x10u
#define ESW_PSNP5_CS_SHIFT                       4
#define ESW_PSNP5_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP5_PORT_COMPARE_SHIFT             16
#define ESW_PSNP5_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP5_PORT_COMPARE_SHIFT))&ESW_PSNP5_PORT_COMPARE_MASK)
/* PSNP6 Bit Fields */
#define ESW_PSNP6_EN_MASK                        0x1u
#define ESW_PSNP6_EN_SHIFT                       0
#define ESW_PSNP6_MODE_MASK                      0x6u
#define ESW_PSNP6_MODE_SHIFT                     1
#define ESW_PSNP6_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP6_MODE_SHIFT))&ESW_PSNP6_MODE_MASK)
#define ESW_PSNP6_CD_MASK                        0x8u
#define ESW_PSNP6_CD_SHIFT                       3
#define ESW_PSNP6_CS_MASK                        0x10u
#define ESW_PSNP6_CS_SHIFT                       4
#define ESW_PSNP6_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP6_PORT_COMPARE_SHIFT             16
#define ESW_PSNP6_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP6_PORT_COMPARE_SHIFT))&ESW_PSNP6_PORT_COMPARE_MASK)
/* PSNP7 Bit Fields */
#define ESW_PSNP7_EN_MASK                        0x1u
#define ESW_PSNP7_EN_SHIFT                       0
#define ESW_PSNP7_MODE_MASK                      0x6u
#define ESW_PSNP7_MODE_SHIFT                     1
#define ESW_PSNP7_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP7_MODE_SHIFT))&ESW_PSNP7_MODE_MASK)
#define ESW_PSNP7_CD_MASK                        0x8u
#define ESW_PSNP7_CD_SHIFT                       3
#define ESW_PSNP7_CS_MASK                        0x10u
#define ESW_PSNP7_CS_SHIFT                       4
#define ESW_PSNP7_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP7_PORT_COMPARE_SHIFT             16
#define ESW_PSNP7_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP7_PORT_COMPARE_SHIFT))&ESW_PSNP7_PORT_COMPARE_MASK)
/* PSNP8 Bit Fields */
#define ESW_PSNP8_EN_MASK                        0x1u
#define ESW_PSNP8_EN_SHIFT                       0
#define ESW_PSNP8_MODE_MASK                      0x6u
#define ESW_PSNP8_MODE_SHIFT                     1
#define ESW_PSNP8_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_PSNP8_MODE_SHIFT))&ESW_PSNP8_MODE_MASK)
#define ESW_PSNP8_CD_MASK                        0x8u
#define ESW_PSNP8_CD_SHIFT                       3
#define ESW_PSNP8_CS_MASK                        0x10u
#define ESW_PSNP8_CS_SHIFT                       4
#define ESW_PSNP8_PORT_COMPARE_MASK              0xFFFF0000u
#define ESW_PSNP8_PORT_COMPARE_SHIFT             16
#define ESW_PSNP8_PORT_COMPARE(x)                (((uint32_t)(((uint32_t)(x))<<ESW_PSNP8_PORT_COMPARE_SHIFT))&ESW_PSNP8_PORT_COMPARE_MASK)
/* IPSNP1 Bit Fields */
#define ESW_IPSNP1_EN_MASK                       0x1u
#define ESW_IPSNP1_EN_SHIFT                      0
#define ESW_IPSNP1_MODE_MASK                     0x6u
#define ESW_IPSNP1_MODE_SHIFT                    1
#define ESW_IPSNP1_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP1_MODE_SHIFT))&ESW_IPSNP1_MODE_MASK)
#define ESW_IPSNP1_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP1_PROTOCOL_SHIFT                8
#define ESW_IPSNP1_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP1_PROTOCOL_SHIFT))&ESW_IPSNP1_PROTOCOL_MASK)
/* IPSNP2 Bit Fields */
#define ESW_IPSNP2_EN_MASK                       0x1u
#define ESW_IPSNP2_EN_SHIFT                      0
#define ESW_IPSNP2_MODE_MASK                     0x6u
#define ESW_IPSNP2_MODE_SHIFT                    1
#define ESW_IPSNP2_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP2_MODE_SHIFT))&ESW_IPSNP2_MODE_MASK)
#define ESW_IPSNP2_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP2_PROTOCOL_SHIFT                8
#define ESW_IPSNP2_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP2_PROTOCOL_SHIFT))&ESW_IPSNP2_PROTOCOL_MASK)
/* IPSNP3 Bit Fields */
#define ESW_IPSNP3_EN_MASK                       0x1u
#define ESW_IPSNP3_EN_SHIFT                      0
#define ESW_IPSNP3_MODE_MASK                     0x6u
#define ESW_IPSNP3_MODE_SHIFT                    1
#define ESW_IPSNP3_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP3_MODE_SHIFT))&ESW_IPSNP3_MODE_MASK)
#define ESW_IPSNP3_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP3_PROTOCOL_SHIFT                8
#define ESW_IPSNP3_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP3_PROTOCOL_SHIFT))&ESW_IPSNP3_PROTOCOL_MASK)
/* IPSNP4 Bit Fields */
#define ESW_IPSNP4_EN_MASK                       0x1u
#define ESW_IPSNP4_EN_SHIFT                      0
#define ESW_IPSNP4_MODE_MASK                     0x6u
#define ESW_IPSNP4_MODE_SHIFT                    1
#define ESW_IPSNP4_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP4_MODE_SHIFT))&ESW_IPSNP4_MODE_MASK)
#define ESW_IPSNP4_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP4_PROTOCOL_SHIFT                8
#define ESW_IPSNP4_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP4_PROTOCOL_SHIFT))&ESW_IPSNP4_PROTOCOL_MASK)
/* IPSNP5 Bit Fields */
#define ESW_IPSNP5_EN_MASK                       0x1u
#define ESW_IPSNP5_EN_SHIFT                      0
#define ESW_IPSNP5_MODE_MASK                     0x6u
#define ESW_IPSNP5_MODE_SHIFT                    1
#define ESW_IPSNP5_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP5_MODE_SHIFT))&ESW_IPSNP5_MODE_MASK)
#define ESW_IPSNP5_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP5_PROTOCOL_SHIFT                8
#define ESW_IPSNP5_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP5_PROTOCOL_SHIFT))&ESW_IPSNP5_PROTOCOL_MASK)
/* IPSNP6 Bit Fields */
#define ESW_IPSNP6_EN_MASK                       0x1u
#define ESW_IPSNP6_EN_SHIFT                      0
#define ESW_IPSNP6_MODE_MASK                     0x6u
#define ESW_IPSNP6_MODE_SHIFT                    1
#define ESW_IPSNP6_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP6_MODE_SHIFT))&ESW_IPSNP6_MODE_MASK)
#define ESW_IPSNP6_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP6_PROTOCOL_SHIFT                8
#define ESW_IPSNP6_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP6_PROTOCOL_SHIFT))&ESW_IPSNP6_PROTOCOL_MASK)
/* IPSNP7 Bit Fields */
#define ESW_IPSNP7_EN_MASK                       0x1u
#define ESW_IPSNP7_EN_SHIFT                      0
#define ESW_IPSNP7_MODE_MASK                     0x6u
#define ESW_IPSNP7_MODE_SHIFT                    1
#define ESW_IPSNP7_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP7_MODE_SHIFT))&ESW_IPSNP7_MODE_MASK)
#define ESW_IPSNP7_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP7_PROTOCOL_SHIFT                8
#define ESW_IPSNP7_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP7_PROTOCOL_SHIFT))&ESW_IPSNP7_PROTOCOL_MASK)
/* IPSNP8 Bit Fields */
#define ESW_IPSNP8_EN_MASK                       0x1u
#define ESW_IPSNP8_EN_SHIFT                      0
#define ESW_IPSNP8_MODE_MASK                     0x6u
#define ESW_IPSNP8_MODE_SHIFT                    1
#define ESW_IPSNP8_MODE(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP8_MODE_SHIFT))&ESW_IPSNP8_MODE_MASK)
#define ESW_IPSNP8_PROTOCOL_MASK                 0xFF00u
#define ESW_IPSNP8_PROTOCOL_SHIFT                8
#define ESW_IPSNP8_PROTOCOL(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_IPSNP8_PROTOCOL_SHIFT))&ESW_IPSNP8_PROTOCOL_MASK)
/* P0VRES Bit Fields */
#define ESW_P0VRES_PRI0_MASK                     0x7u
#define ESW_P0VRES_PRI0_SHIFT                    0
#define ESW_P0VRES_PRI0(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI0_SHIFT))&ESW_P0VRES_PRI0_MASK)
#define ESW_P0VRES_PRI1_MASK                     0x38u
#define ESW_P0VRES_PRI1_SHIFT                    3
#define ESW_P0VRES_PRI1(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI1_SHIFT))&ESW_P0VRES_PRI1_MASK)
#define ESW_P0VRES_PRI2_MASK                     0x1C0u
#define ESW_P0VRES_PRI2_SHIFT                    6
#define ESW_P0VRES_PRI2(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI2_SHIFT))&ESW_P0VRES_PRI2_MASK)
#define ESW_P0VRES_PRI3_MASK                     0xE00u
#define ESW_P0VRES_PRI3_SHIFT                    9
#define ESW_P0VRES_PRI3(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI3_SHIFT))&ESW_P0VRES_PRI3_MASK)
#define ESW_P0VRES_PRI4_MASK                     0x7000u
#define ESW_P0VRES_PRI4_SHIFT                    12
#define ESW_P0VRES_PRI4(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI4_SHIFT))&ESW_P0VRES_PRI4_MASK)
#define ESW_P0VRES_PRI5_MASK                     0x38000u
#define ESW_P0VRES_PRI5_SHIFT                    15
#define ESW_P0VRES_PRI5(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI5_SHIFT))&ESW_P0VRES_PRI5_MASK)
#define ESW_P0VRES_PRI6_MASK                     0x1C0000u
#define ESW_P0VRES_PRI6_SHIFT                    18
#define ESW_P0VRES_PRI6(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI6_SHIFT))&ESW_P0VRES_PRI6_MASK)
#define ESW_P0VRES_PRI7_MASK                     0xE00000u
#define ESW_P0VRES_PRI7_SHIFT                    21
#define ESW_P0VRES_PRI7(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0VRES_PRI7_SHIFT))&ESW_P0VRES_PRI7_MASK)
/* P1VRES Bit Fields */
#define ESW_P1VRES_PRI0_MASK                     0x7u
#define ESW_P1VRES_PRI0_SHIFT                    0
#define ESW_P1VRES_PRI0(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI0_SHIFT))&ESW_P1VRES_PRI0_MASK)
#define ESW_P1VRES_PRI1_MASK                     0x38u
#define ESW_P1VRES_PRI1_SHIFT                    3
#define ESW_P1VRES_PRI1(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI1_SHIFT))&ESW_P1VRES_PRI1_MASK)
#define ESW_P1VRES_PRI2_MASK                     0x1C0u
#define ESW_P1VRES_PRI2_SHIFT                    6
#define ESW_P1VRES_PRI2(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI2_SHIFT))&ESW_P1VRES_PRI2_MASK)
#define ESW_P1VRES_PRI3_MASK                     0xE00u
#define ESW_P1VRES_PRI3_SHIFT                    9
#define ESW_P1VRES_PRI3(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI3_SHIFT))&ESW_P1VRES_PRI3_MASK)
#define ESW_P1VRES_PRI4_MASK                     0x7000u
#define ESW_P1VRES_PRI4_SHIFT                    12
#define ESW_P1VRES_PRI4(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI4_SHIFT))&ESW_P1VRES_PRI4_MASK)
#define ESW_P1VRES_PRI5_MASK                     0x38000u
#define ESW_P1VRES_PRI5_SHIFT                    15
#define ESW_P1VRES_PRI5(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI5_SHIFT))&ESW_P1VRES_PRI5_MASK)
#define ESW_P1VRES_PRI6_MASK                     0x1C0000u
#define ESW_P1VRES_PRI6_SHIFT                    18
#define ESW_P1VRES_PRI6(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI6_SHIFT))&ESW_P1VRES_PRI6_MASK)
#define ESW_P1VRES_PRI7_MASK                     0xE00000u
#define ESW_P1VRES_PRI7_SHIFT                    21
#define ESW_P1VRES_PRI7(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1VRES_PRI7_SHIFT))&ESW_P1VRES_PRI7_MASK)
/* P2VRES Bit Fields */
#define ESW_P2VRES_PRI0_MASK                     0x7u
#define ESW_P2VRES_PRI0_SHIFT                    0
#define ESW_P2VRES_PRI0(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI0_SHIFT))&ESW_P2VRES_PRI0_MASK)
#define ESW_P2VRES_PRI1_MASK                     0x38u
#define ESW_P2VRES_PRI1_SHIFT                    3
#define ESW_P2VRES_PRI1(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI1_SHIFT))&ESW_P2VRES_PRI1_MASK)
#define ESW_P2VRES_PRI2_MASK                     0x1C0u
#define ESW_P2VRES_PRI2_SHIFT                    6
#define ESW_P2VRES_PRI2(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI2_SHIFT))&ESW_P2VRES_PRI2_MASK)
#define ESW_P2VRES_PRI3_MASK                     0xE00u
#define ESW_P2VRES_PRI3_SHIFT                    9
#define ESW_P2VRES_PRI3(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI3_SHIFT))&ESW_P2VRES_PRI3_MASK)
#define ESW_P2VRES_PRI4_MASK                     0x7000u
#define ESW_P2VRES_PRI4_SHIFT                    12
#define ESW_P2VRES_PRI4(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI4_SHIFT))&ESW_P2VRES_PRI4_MASK)
#define ESW_P2VRES_PRI5_MASK                     0x38000u
#define ESW_P2VRES_PRI5_SHIFT                    15
#define ESW_P2VRES_PRI5(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI5_SHIFT))&ESW_P2VRES_PRI5_MASK)
#define ESW_P2VRES_PRI6_MASK                     0x1C0000u
#define ESW_P2VRES_PRI6_SHIFT                    18
#define ESW_P2VRES_PRI6(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI6_SHIFT))&ESW_P2VRES_PRI6_MASK)
#define ESW_P2VRES_PRI7_MASK                     0xE00000u
#define ESW_P2VRES_PRI7_SHIFT                    21
#define ESW_P2VRES_PRI7(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2VRES_PRI7_SHIFT))&ESW_P2VRES_PRI7_MASK)
/* IPRES Bit Fields */
#define ESW_IPRES_ADDRESS_MASK                   0xFFu
#define ESW_IPRES_ADDRESS_SHIFT                  0
#define ESW_IPRES_ADDRESS(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_IPRES_ADDRESS_SHIFT))&ESW_IPRES_ADDRESS_MASK)
#define ESW_IPRES_IPV4SEL_MASK                   0x100u
#define ESW_IPRES_IPV4SEL_SHIFT                  8
#define ESW_IPRES_PRI0_MASK                      0x600u
#define ESW_IPRES_PRI0_SHIFT                     9
#define ESW_IPRES_PRI0(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_IPRES_PRI0_SHIFT))&ESW_IPRES_PRI0_MASK)
#define ESW_IPRES_PRI1_MASK                      0x1800u
#define ESW_IPRES_PRI1_SHIFT                     11
#define ESW_IPRES_PRI1(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_IPRES_PRI1_SHIFT))&ESW_IPRES_PRI1_MASK)
#define ESW_IPRES_PRI2_MASK                      0x6000u
#define ESW_IPRES_PRI2_SHIFT                     13
#define ESW_IPRES_PRI2(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_IPRES_PRI2_SHIFT))&ESW_IPRES_PRI2_MASK)
#define ESW_IPRES_READ_MASK                      0x80000000u
#define ESW_IPRES_READ_SHIFT                     31
/* P0RES Bit Fields */
#define ESW_P0RES_VLAN_MASK                      0x1u
#define ESW_P0RES_VLAN_SHIFT                     0
#define ESW_P0RES_IP_MASK                        0x2u
#define ESW_P0RES_IP_SHIFT                       1
#define ESW_P0RES_MAC_MASK                       0x4u
#define ESW_P0RES_MAC_SHIFT                      2
#define ESW_P0RES_DFLT_PRI_MASK                  0x70u
#define ESW_P0RES_DFLT_PRI_SHIFT                 4
#define ESW_P0RES_DFLT_PRI(x)                    (((uint32_t)(((uint32_t)(x))<<ESW_P0RES_DFLT_PRI_SHIFT))&ESW_P0RES_DFLT_PRI_MASK)
/* P1RES Bit Fields */
#define ESW_P1RES_VLAN_MASK                      0x1u
#define ESW_P1RES_VLAN_SHIFT                     0
#define ESW_P1RES_IP_MASK                        0x2u
#define ESW_P1RES_IP_SHIFT                       1
#define ESW_P1RES_MAC_MASK                       0x4u
#define ESW_P1RES_MAC_SHIFT                      2
#define ESW_P1RES_DFLT_PRI_MASK                  0x70u
#define ESW_P1RES_DFLT_PRI_SHIFT                 4
#define ESW_P1RES_DFLT_PRI(x)                    (((uint32_t)(((uint32_t)(x))<<ESW_P1RES_DFLT_PRI_SHIFT))&ESW_P1RES_DFLT_PRI_MASK)
/* P2RES Bit Fields */
#define ESW_P2RES_VLAN_MASK                      0x1u
#define ESW_P2RES_VLAN_SHIFT                     0
#define ESW_P2RES_IP_MASK                        0x2u
#define ESW_P2RES_IP_SHIFT                       1
#define ESW_P2RES_MAC_MASK                       0x4u
#define ESW_P2RES_MAC_SHIFT                      2
#define ESW_P2RES_DFLT_PRI_MASK                  0x70u
#define ESW_P2RES_DFLT_PRI_SHIFT                 4
#define ESW_P2RES_DFLT_PRI(x)                    (((uint32_t)(((uint32_t)(x))<<ESW_P2RES_DFLT_PRI_SHIFT))&ESW_P2RES_DFLT_PRI_MASK)
/* P0ID Bit Fields */
#define ESW_P0ID_VLANID_MASK                     0xFFFFu
#define ESW_P0ID_VLANID_SHIFT                    0
#define ESW_P0ID_VLANID(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0ID_VLANID_SHIFT))&ESW_P0ID_VLANID_MASK)
/* P1ID Bit Fields */
#define ESW_P1ID_VLANID_MASK                     0xFFFFu
#define ESW_P1ID_VLANID_SHIFT                    0
#define ESW_P1ID_VLANID(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1ID_VLANID_SHIFT))&ESW_P1ID_VLANID_MASK)
/* P2ID Bit Fields */
#define ESW_P2ID_VLANID_MASK                     0xFFFFu
#define ESW_P2ID_VLANID_SHIFT                    0
#define ESW_P2ID_VLANID(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2ID_VLANID_SHIFT))&ESW_P2ID_VLANID_MASK)
/* VRES0 Bit Fields */
#define ESW_VRES0_P0_MASK                        0x1u
#define ESW_VRES0_P0_SHIFT                       0
#define ESW_VRES0_P1_MASK                        0x2u
#define ESW_VRES0_P1_SHIFT                       1
#define ESW_VRES0_P2_MASK                        0x4u
#define ESW_VRES0_P2_SHIFT                       2
#define ESW_VRES0_VLANID_MASK                    0x7FF8u
#define ESW_VRES0_VLANID_SHIFT                   3
#define ESW_VRES0_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES0_VLANID_SHIFT))&ESW_VRES0_VLANID_MASK)
/* VRES1 Bit Fields */
#define ESW_VRES1_P0_MASK                        0x1u
#define ESW_VRES1_P0_SHIFT                       0
#define ESW_VRES1_P1_MASK                        0x2u
#define ESW_VRES1_P1_SHIFT                       1
#define ESW_VRES1_P2_MASK                        0x4u
#define ESW_VRES1_P2_SHIFT                       2
#define ESW_VRES1_VLANID_MASK                    0x7FF8u
#define ESW_VRES1_VLANID_SHIFT                   3
#define ESW_VRES1_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES1_VLANID_SHIFT))&ESW_VRES1_VLANID_MASK)
/* VRES2 Bit Fields */
#define ESW_VRES2_P0_MASK                        0x1u
#define ESW_VRES2_P0_SHIFT                       0
#define ESW_VRES2_P1_MASK                        0x2u
#define ESW_VRES2_P1_SHIFT                       1
#define ESW_VRES2_P2_MASK                        0x4u
#define ESW_VRES2_P2_SHIFT                       2
#define ESW_VRES2_VLANID_MASK                    0x7FF8u
#define ESW_VRES2_VLANID_SHIFT                   3
#define ESW_VRES2_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES2_VLANID_SHIFT))&ESW_VRES2_VLANID_MASK)
/* VRES3 Bit Fields */
#define ESW_VRES3_P0_MASK                        0x1u
#define ESW_VRES3_P0_SHIFT                       0
#define ESW_VRES3_P1_MASK                        0x2u
#define ESW_VRES3_P1_SHIFT                       1
#define ESW_VRES3_P2_MASK                        0x4u
#define ESW_VRES3_P2_SHIFT                       2
#define ESW_VRES3_VLANID_MASK                    0x7FF8u
#define ESW_VRES3_VLANID_SHIFT                   3
#define ESW_VRES3_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES3_VLANID_SHIFT))&ESW_VRES3_VLANID_MASK)
/* VRES4 Bit Fields */
#define ESW_VRES4_P0_MASK                        0x1u
#define ESW_VRES4_P0_SHIFT                       0
#define ESW_VRES4_P1_MASK                        0x2u
#define ESW_VRES4_P1_SHIFT                       1
#define ESW_VRES4_P2_MASK                        0x4u
#define ESW_VRES4_P2_SHIFT                       2
#define ESW_VRES4_VLANID_MASK                    0x7FF8u
#define ESW_VRES4_VLANID_SHIFT                   3
#define ESW_VRES4_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES4_VLANID_SHIFT))&ESW_VRES4_VLANID_MASK)
/* VRES5 Bit Fields */
#define ESW_VRES5_P0_MASK                        0x1u
#define ESW_VRES5_P0_SHIFT                       0
#define ESW_VRES5_P1_MASK                        0x2u
#define ESW_VRES5_P1_SHIFT                       1
#define ESW_VRES5_P2_MASK                        0x4u
#define ESW_VRES5_P2_SHIFT                       2
#define ESW_VRES5_VLANID_MASK                    0x7FF8u
#define ESW_VRES5_VLANID_SHIFT                   3
#define ESW_VRES5_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES5_VLANID_SHIFT))&ESW_VRES5_VLANID_MASK)
/* VRES6 Bit Fields */
#define ESW_VRES6_P0_MASK                        0x1u
#define ESW_VRES6_P0_SHIFT                       0
#define ESW_VRES6_P1_MASK                        0x2u
#define ESW_VRES6_P1_SHIFT                       1
#define ESW_VRES6_P2_MASK                        0x4u
#define ESW_VRES6_P2_SHIFT                       2
#define ESW_VRES6_VLANID_MASK                    0x7FF8u
#define ESW_VRES6_VLANID_SHIFT                   3
#define ESW_VRES6_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES6_VLANID_SHIFT))&ESW_VRES6_VLANID_MASK)
/* VRES7 Bit Fields */
#define ESW_VRES7_P0_MASK                        0x1u
#define ESW_VRES7_P0_SHIFT                       0
#define ESW_VRES7_P1_MASK                        0x2u
#define ESW_VRES7_P1_SHIFT                       1
#define ESW_VRES7_P2_MASK                        0x4u
#define ESW_VRES7_P2_SHIFT                       2
#define ESW_VRES7_VLANID_MASK                    0x7FF8u
#define ESW_VRES7_VLANID_SHIFT                   3
#define ESW_VRES7_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES7_VLANID_SHIFT))&ESW_VRES7_VLANID_MASK)
/* VRES8 Bit Fields */
#define ESW_VRES8_P0_MASK                        0x1u
#define ESW_VRES8_P0_SHIFT                       0
#define ESW_VRES8_P1_MASK                        0x2u
#define ESW_VRES8_P1_SHIFT                       1
#define ESW_VRES8_P2_MASK                        0x4u
#define ESW_VRES8_P2_SHIFT                       2
#define ESW_VRES8_VLANID_MASK                    0x7FF8u
#define ESW_VRES8_VLANID_SHIFT                   3
#define ESW_VRES8_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES8_VLANID_SHIFT))&ESW_VRES8_VLANID_MASK)
/* VRES9 Bit Fields */
#define ESW_VRES9_P0_MASK                        0x1u
#define ESW_VRES9_P0_SHIFT                       0
#define ESW_VRES9_P1_MASK                        0x2u
#define ESW_VRES9_P1_SHIFT                       1
#define ESW_VRES9_P2_MASK                        0x4u
#define ESW_VRES9_P2_SHIFT                       2
#define ESW_VRES9_VLANID_MASK                    0x7FF8u
#define ESW_VRES9_VLANID_SHIFT                   3
#define ESW_VRES9_VLANID(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_VRES9_VLANID_SHIFT))&ESW_VRES9_VLANID_MASK)
/* VRES10 Bit Fields */
#define ESW_VRES10_P0_MASK                       0x1u
#define ESW_VRES10_P0_SHIFT                      0
#define ESW_VRES10_P1_MASK                       0x2u
#define ESW_VRES10_P1_SHIFT                      1
#define ESW_VRES10_P2_MASK                       0x4u
#define ESW_VRES10_P2_SHIFT                      2
#define ESW_VRES10_VLANID_MASK                   0x7FF8u
#define ESW_VRES10_VLANID_SHIFT                  3
#define ESW_VRES10_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES10_VLANID_SHIFT))&ESW_VRES10_VLANID_MASK)
/* VRES11 Bit Fields */
#define ESW_VRES11_P0_MASK                       0x1u
#define ESW_VRES11_P0_SHIFT                      0
#define ESW_VRES11_P1_MASK                       0x2u
#define ESW_VRES11_P1_SHIFT                      1
#define ESW_VRES11_P2_MASK                       0x4u
#define ESW_VRES11_P2_SHIFT                      2
#define ESW_VRES11_VLANID_MASK                   0x7FF8u
#define ESW_VRES11_VLANID_SHIFT                  3
#define ESW_VRES11_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES11_VLANID_SHIFT))&ESW_VRES11_VLANID_MASK)
/* VRES12 Bit Fields */
#define ESW_VRES12_P0_MASK                       0x1u
#define ESW_VRES12_P0_SHIFT                      0
#define ESW_VRES12_P1_MASK                       0x2u
#define ESW_VRES12_P1_SHIFT                      1
#define ESW_VRES12_P2_MASK                       0x4u
#define ESW_VRES12_P2_SHIFT                      2
#define ESW_VRES12_VLANID_MASK                   0x7FF8u
#define ESW_VRES12_VLANID_SHIFT                  3
#define ESW_VRES12_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES12_VLANID_SHIFT))&ESW_VRES12_VLANID_MASK)
/* VRES13 Bit Fields */
#define ESW_VRES13_P0_MASK                       0x1u
#define ESW_VRES13_P0_SHIFT                      0
#define ESW_VRES13_P1_MASK                       0x2u
#define ESW_VRES13_P1_SHIFT                      1
#define ESW_VRES13_P2_MASK                       0x4u
#define ESW_VRES13_P2_SHIFT                      2
#define ESW_VRES13_VLANID_MASK                   0x7FF8u
#define ESW_VRES13_VLANID_SHIFT                  3
#define ESW_VRES13_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES13_VLANID_SHIFT))&ESW_VRES13_VLANID_MASK)
/* VRES14 Bit Fields */
#define ESW_VRES14_P0_MASK                       0x1u
#define ESW_VRES14_P0_SHIFT                      0
#define ESW_VRES14_P1_MASK                       0x2u
#define ESW_VRES14_P1_SHIFT                      1
#define ESW_VRES14_P2_MASK                       0x4u
#define ESW_VRES14_P2_SHIFT                      2
#define ESW_VRES14_VLANID_MASK                   0x7FF8u
#define ESW_VRES14_VLANID_SHIFT                  3
#define ESW_VRES14_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES14_VLANID_SHIFT))&ESW_VRES14_VLANID_MASK)
/* VRES15 Bit Fields */
#define ESW_VRES15_P0_MASK                       0x1u
#define ESW_VRES15_P0_SHIFT                      0
#define ESW_VRES15_P1_MASK                       0x2u
#define ESW_VRES15_P1_SHIFT                      1
#define ESW_VRES15_P2_MASK                       0x4u
#define ESW_VRES15_P2_SHIFT                      2
#define ESW_VRES15_VLANID_MASK                   0x7FF8u
#define ESW_VRES15_VLANID_SHIFT                  3
#define ESW_VRES15_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES15_VLANID_SHIFT))&ESW_VRES15_VLANID_MASK)
/* VRES16 Bit Fields */
#define ESW_VRES16_P0_MASK                       0x1u
#define ESW_VRES16_P0_SHIFT                      0
#define ESW_VRES16_P1_MASK                       0x2u
#define ESW_VRES16_P1_SHIFT                      1
#define ESW_VRES16_P2_MASK                       0x4u
#define ESW_VRES16_P2_SHIFT                      2
#define ESW_VRES16_VLANID_MASK                   0x7FF8u
#define ESW_VRES16_VLANID_SHIFT                  3
#define ESW_VRES16_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES16_VLANID_SHIFT))&ESW_VRES16_VLANID_MASK)
/* VRES17 Bit Fields */
#define ESW_VRES17_P0_MASK                       0x1u
#define ESW_VRES17_P0_SHIFT                      0
#define ESW_VRES17_P1_MASK                       0x2u
#define ESW_VRES17_P1_SHIFT                      1
#define ESW_VRES17_P2_MASK                       0x4u
#define ESW_VRES17_P2_SHIFT                      2
#define ESW_VRES17_VLANID_MASK                   0x7FF8u
#define ESW_VRES17_VLANID_SHIFT                  3
#define ESW_VRES17_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES17_VLANID_SHIFT))&ESW_VRES17_VLANID_MASK)
/* VRES18 Bit Fields */
#define ESW_VRES18_P0_MASK                       0x1u
#define ESW_VRES18_P0_SHIFT                      0
#define ESW_VRES18_P1_MASK                       0x2u
#define ESW_VRES18_P1_SHIFT                      1
#define ESW_VRES18_P2_MASK                       0x4u
#define ESW_VRES18_P2_SHIFT                      2
#define ESW_VRES18_VLANID_MASK                   0x7FF8u
#define ESW_VRES18_VLANID_SHIFT                  3
#define ESW_VRES18_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES18_VLANID_SHIFT))&ESW_VRES18_VLANID_MASK)
/* VRES19 Bit Fields */
#define ESW_VRES19_P0_MASK                       0x1u
#define ESW_VRES19_P0_SHIFT                      0
#define ESW_VRES19_P1_MASK                       0x2u
#define ESW_VRES19_P1_SHIFT                      1
#define ESW_VRES19_P2_MASK                       0x4u
#define ESW_VRES19_P2_SHIFT                      2
#define ESW_VRES19_VLANID_MASK                   0x7FF8u
#define ESW_VRES19_VLANID_SHIFT                  3
#define ESW_VRES19_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES19_VLANID_SHIFT))&ESW_VRES19_VLANID_MASK)
/* VRES20 Bit Fields */
#define ESW_VRES20_P0_MASK                       0x1u
#define ESW_VRES20_P0_SHIFT                      0
#define ESW_VRES20_P1_MASK                       0x2u
#define ESW_VRES20_P1_SHIFT                      1
#define ESW_VRES20_P2_MASK                       0x4u
#define ESW_VRES20_P2_SHIFT                      2
#define ESW_VRES20_VLANID_MASK                   0x7FF8u
#define ESW_VRES20_VLANID_SHIFT                  3
#define ESW_VRES20_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES20_VLANID_SHIFT))&ESW_VRES20_VLANID_MASK)
/* VRES21 Bit Fields */
#define ESW_VRES21_P0_MASK                       0x1u
#define ESW_VRES21_P0_SHIFT                      0
#define ESW_VRES21_P1_MASK                       0x2u
#define ESW_VRES21_P1_SHIFT                      1
#define ESW_VRES21_P2_MASK                       0x4u
#define ESW_VRES21_P2_SHIFT                      2
#define ESW_VRES21_VLANID_MASK                   0x7FF8u
#define ESW_VRES21_VLANID_SHIFT                  3
#define ESW_VRES21_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES21_VLANID_SHIFT))&ESW_VRES21_VLANID_MASK)
/* VRES22 Bit Fields */
#define ESW_VRES22_P0_MASK                       0x1u
#define ESW_VRES22_P0_SHIFT                      0
#define ESW_VRES22_P1_MASK                       0x2u
#define ESW_VRES22_P1_SHIFT                      1
#define ESW_VRES22_P2_MASK                       0x4u
#define ESW_VRES22_P2_SHIFT                      2
#define ESW_VRES22_VLANID_MASK                   0x7FF8u
#define ESW_VRES22_VLANID_SHIFT                  3
#define ESW_VRES22_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES22_VLANID_SHIFT))&ESW_VRES22_VLANID_MASK)
/* VRES23 Bit Fields */
#define ESW_VRES23_P0_MASK                       0x1u
#define ESW_VRES23_P0_SHIFT                      0
#define ESW_VRES23_P1_MASK                       0x2u
#define ESW_VRES23_P1_SHIFT                      1
#define ESW_VRES23_P2_MASK                       0x4u
#define ESW_VRES23_P2_SHIFT                      2
#define ESW_VRES23_VLANID_MASK                   0x7FF8u
#define ESW_VRES23_VLANID_SHIFT                  3
#define ESW_VRES23_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES23_VLANID_SHIFT))&ESW_VRES23_VLANID_MASK)
/* VRES24 Bit Fields */
#define ESW_VRES24_P0_MASK                       0x1u
#define ESW_VRES24_P0_SHIFT                      0
#define ESW_VRES24_P1_MASK                       0x2u
#define ESW_VRES24_P1_SHIFT                      1
#define ESW_VRES24_P2_MASK                       0x4u
#define ESW_VRES24_P2_SHIFT                      2
#define ESW_VRES24_VLANID_MASK                   0x7FF8u
#define ESW_VRES24_VLANID_SHIFT                  3
#define ESW_VRES24_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES24_VLANID_SHIFT))&ESW_VRES24_VLANID_MASK)
/* VRES25 Bit Fields */
#define ESW_VRES25_P0_MASK                       0x1u
#define ESW_VRES25_P0_SHIFT                      0
#define ESW_VRES25_P1_MASK                       0x2u
#define ESW_VRES25_P1_SHIFT                      1
#define ESW_VRES25_P2_MASK                       0x4u
#define ESW_VRES25_P2_SHIFT                      2
#define ESW_VRES25_VLANID_MASK                   0x7FF8u
#define ESW_VRES25_VLANID_SHIFT                  3
#define ESW_VRES25_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES25_VLANID_SHIFT))&ESW_VRES25_VLANID_MASK)
/* VRES26 Bit Fields */
#define ESW_VRES26_P0_MASK                       0x1u
#define ESW_VRES26_P0_SHIFT                      0
#define ESW_VRES26_P1_MASK                       0x2u
#define ESW_VRES26_P1_SHIFT                      1
#define ESW_VRES26_P2_MASK                       0x4u
#define ESW_VRES26_P2_SHIFT                      2
#define ESW_VRES26_VLANID_MASK                   0x7FF8u
#define ESW_VRES26_VLANID_SHIFT                  3
#define ESW_VRES26_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES26_VLANID_SHIFT))&ESW_VRES26_VLANID_MASK)
/* VRES27 Bit Fields */
#define ESW_VRES27_P0_MASK                       0x1u
#define ESW_VRES27_P0_SHIFT                      0
#define ESW_VRES27_P1_MASK                       0x2u
#define ESW_VRES27_P1_SHIFT                      1
#define ESW_VRES27_P2_MASK                       0x4u
#define ESW_VRES27_P2_SHIFT                      2
#define ESW_VRES27_VLANID_MASK                   0x7FF8u
#define ESW_VRES27_VLANID_SHIFT                  3
#define ESW_VRES27_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES27_VLANID_SHIFT))&ESW_VRES27_VLANID_MASK)
/* VRES28 Bit Fields */
#define ESW_VRES28_P0_MASK                       0x1u
#define ESW_VRES28_P0_SHIFT                      0
#define ESW_VRES28_P1_MASK                       0x2u
#define ESW_VRES28_P1_SHIFT                      1
#define ESW_VRES28_P2_MASK                       0x4u
#define ESW_VRES28_P2_SHIFT                      2
#define ESW_VRES28_VLANID_MASK                   0x7FF8u
#define ESW_VRES28_VLANID_SHIFT                  3
#define ESW_VRES28_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES28_VLANID_SHIFT))&ESW_VRES28_VLANID_MASK)
/* VRES29 Bit Fields */
#define ESW_VRES29_P0_MASK                       0x1u
#define ESW_VRES29_P0_SHIFT                      0
#define ESW_VRES29_P1_MASK                       0x2u
#define ESW_VRES29_P1_SHIFT                      1
#define ESW_VRES29_P2_MASK                       0x4u
#define ESW_VRES29_P2_SHIFT                      2
#define ESW_VRES29_VLANID_MASK                   0x7FF8u
#define ESW_VRES29_VLANID_SHIFT                  3
#define ESW_VRES29_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES29_VLANID_SHIFT))&ESW_VRES29_VLANID_MASK)
/* VRES30 Bit Fields */
#define ESW_VRES30_P0_MASK                       0x1u
#define ESW_VRES30_P0_SHIFT                      0
#define ESW_VRES30_P1_MASK                       0x2u
#define ESW_VRES30_P1_SHIFT                      1
#define ESW_VRES30_P2_MASK                       0x4u
#define ESW_VRES30_P2_SHIFT                      2
#define ESW_VRES30_VLANID_MASK                   0x7FF8u
#define ESW_VRES30_VLANID_SHIFT                  3
#define ESW_VRES30_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES30_VLANID_SHIFT))&ESW_VRES30_VLANID_MASK)
/* VRES31 Bit Fields */
#define ESW_VRES31_P0_MASK                       0x1u
#define ESW_VRES31_P0_SHIFT                      0
#define ESW_VRES31_P1_MASK                       0x2u
#define ESW_VRES31_P1_SHIFT                      1
#define ESW_VRES31_P2_MASK                       0x4u
#define ESW_VRES31_P2_SHIFT                      2
#define ESW_VRES31_VLANID_MASK                   0x7FF8u
#define ESW_VRES31_VLANID_SHIFT                  3
#define ESW_VRES31_VLANID(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_VRES31_VLANID_SHIFT))&ESW_VRES31_VLANID_MASK)
/* DISCN Bit Fields */
#define ESW_DISCN_COUNT_MASK                     0xFFFFFFFFu
#define ESW_DISCN_COUNT_SHIFT                    0
#define ESW_DISCN_COUNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_DISCN_COUNT_SHIFT))&ESW_DISCN_COUNT_MASK)
/* DISCB Bit Fields */
#define ESW_DISCB_COUNT_MASK                     0xFFFFFFFFu
#define ESW_DISCB_COUNT_SHIFT                    0
#define ESW_DISCB_COUNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_DISCB_COUNT_SHIFT))&ESW_DISCB_COUNT_MASK)
/* NDISCN Bit Fields */
#define ESW_NDISCN_COUNT_MASK                    0xFFFFFFFFu
#define ESW_NDISCN_COUNT_SHIFT                   0
#define ESW_NDISCN_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_NDISCN_COUNT_SHIFT))&ESW_NDISCN_COUNT_MASK)
/* NDISCB Bit Fields */
#define ESW_NDISCB_COUNT_MASK                    0xFFFFFFFFu
#define ESW_NDISCB_COUNT_SHIFT                   0
#define ESW_NDISCB_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_NDISCB_COUNT_SHIFT))&ESW_NDISCB_COUNT_MASK)
/* P0OQC Bit Fields */
#define ESW_P0OQC_COUNT_MASK                     0xFFFFFFFFu
#define ESW_P0OQC_COUNT_SHIFT                    0
#define ESW_P0OQC_COUNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P0OQC_COUNT_SHIFT))&ESW_P0OQC_COUNT_MASK)
/* P0MVID Bit Fields */
#define ESW_P0MVID_COUNT_MASK                    0xFFFFFFFFu
#define ESW_P0MVID_COUNT_SHIFT                   0
#define ESW_P0MVID_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_P0MVID_COUNT_SHIFT))&ESW_P0MVID_COUNT_MASK)
/* P0MVTAG Bit Fields */
#define ESW_P0MVTAG_COUNT_MASK                   0xFFFFFFFFu
#define ESW_P0MVTAG_COUNT_SHIFT                  0
#define ESW_P0MVTAG_COUNT(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_P0MVTAG_COUNT_SHIFT))&ESW_P0MVTAG_COUNT_MASK)
/* P0BL Bit Fields */
#define ESW_P0BL_COUNT_MASK                      0xFFFFFFFFu
#define ESW_P0BL_COUNT_SHIFT                     0
#define ESW_P0BL_COUNT(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_P0BL_COUNT_SHIFT))&ESW_P0BL_COUNT_MASK)
/* P1OQC Bit Fields */
#define ESW_P1OQC_COUNT_MASK                     0xFFFFFFFFu
#define ESW_P1OQC_COUNT_SHIFT                    0
#define ESW_P1OQC_COUNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P1OQC_COUNT_SHIFT))&ESW_P1OQC_COUNT_MASK)
/* P1MVID Bit Fields */
#define ESW_P1MVID_COUNT_MASK                    0xFFFFFFFFu
#define ESW_P1MVID_COUNT_SHIFT                   0
#define ESW_P1MVID_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_P1MVID_COUNT_SHIFT))&ESW_P1MVID_COUNT_MASK)
/* P1MVTAG Bit Fields */
#define ESW_P1MVTAG_COUNT_MASK                   0xFFFFFFFFu
#define ESW_P1MVTAG_COUNT_SHIFT                  0
#define ESW_P1MVTAG_COUNT(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_P1MVTAG_COUNT_SHIFT))&ESW_P1MVTAG_COUNT_MASK)
/* P1BL Bit Fields */
#define ESW_P1BL_COUNT_MASK                      0xFFFFFFFFu
#define ESW_P1BL_COUNT_SHIFT                     0
#define ESW_P1BL_COUNT(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_P1BL_COUNT_SHIFT))&ESW_P1BL_COUNT_MASK)
/* P2OQC Bit Fields */
#define ESW_P2OQC_COUNT_MASK                     0xFFFFFFFFu
#define ESW_P2OQC_COUNT_SHIFT                    0
#define ESW_P2OQC_COUNT(x)                       (((uint32_t)(((uint32_t)(x))<<ESW_P2OQC_COUNT_SHIFT))&ESW_P2OQC_COUNT_MASK)
/* P2MVID Bit Fields */
#define ESW_P2MVID_COUNT_MASK                    0xFFFFFFFFu
#define ESW_P2MVID_COUNT_SHIFT                   0
#define ESW_P2MVID_COUNT(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_P2MVID_COUNT_SHIFT))&ESW_P2MVID_COUNT_MASK)
/* P2MVTAG Bit Fields */
#define ESW_P2MVTAG_COUNT_MASK                   0xFFFFFFFFu
#define ESW_P2MVTAG_COUNT_SHIFT                  0
#define ESW_P2MVTAG_COUNT(x)                     (((uint32_t)(((uint32_t)(x))<<ESW_P2MVTAG_COUNT_SHIFT))&ESW_P2MVTAG_COUNT_MASK)
/* P2BL Bit Fields */
#define ESW_P2BL_COUNT_MASK                      0xFFFFFFFFu
#define ESW_P2BL_COUNT_SHIFT                     0
#define ESW_P2BL_COUNT(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_P2BL_COUNT_SHIFT))&ESW_P2BL_COUNT_MASK)
/* ISR Bit Fields */
#define ESW_ISR_EBERR_MASK                       0x1u
#define ESW_ISR_EBERR_SHIFT                      0
#define ESW_ISR_RXB_MASK                         0x2u
#define ESW_ISR_RXB_SHIFT                        1
#define ESW_ISR_RXF_MASK                         0x4u
#define ESW_ISR_RXF_SHIFT                        2
#define ESW_ISR_TXB_MASK                         0x8u
#define ESW_ISR_TXB_SHIFT                        3
#define ESW_ISR_TXF_MASK                         0x10u
#define ESW_ISR_TXF_SHIFT                        4
#define ESW_ISR_QM_MASK                          0x20u
#define ESW_ISR_QM_SHIFT                         5
#define ESW_ISR_OD0_MASK                         0x40u
#define ESW_ISR_OD0_SHIFT                        6
#define ESW_ISR_OD1_MASK                         0x80u
#define ESW_ISR_OD1_SHIFT                        7
#define ESW_ISR_OD2_MASK                         0x100u
#define ESW_ISR_OD2_SHIFT                        8
#define ESW_ISR_LRN_MASK                         0x200u
#define ESW_ISR_LRN_SHIFT                        9
/* IMR Bit Fields */
#define ESW_IMR_EBERR_MASK                       0x1u
#define ESW_IMR_EBERR_SHIFT                      0
#define ESW_IMR_RXB_MASK                         0x2u
#define ESW_IMR_RXB_SHIFT                        1
#define ESW_IMR_RXF_MASK                         0x4u
#define ESW_IMR_RXF_SHIFT                        2
#define ESW_IMR_TXB_MASK                         0x8u
#define ESW_IMR_TXB_SHIFT                        3
#define ESW_IMR_TXF_MASK                         0x10u
#define ESW_IMR_TXF_SHIFT                        4
#define ESW_IMR_QM_MASK                          0x20u
#define ESW_IMR_QM_SHIFT                         5
#define ESW_IMR_OD0_MASK                         0x40u
#define ESW_IMR_OD0_SHIFT                        6
#define ESW_IMR_OD1_MASK                         0x80u
#define ESW_IMR_OD1_SHIFT                        7
#define ESW_IMR_OD2_MASK                         0x100u
#define ESW_IMR_OD2_SHIFT                        8
#define ESW_IMR_LRN_MASK                         0x200u
#define ESW_IMR_LRN_SHIFT                        9
/* RDSR Bit Fields */
#define ESW_RDSR_ADDRESS_MASK                    0xFFFFFFFCu
#define ESW_RDSR_ADDRESS_SHIFT                   2
#define ESW_RDSR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_RDSR_ADDRESS_SHIFT))&ESW_RDSR_ADDRESS_MASK)
/* TDSR Bit Fields */
#define ESW_TDSR_ADDRESS_MASK                    0xFFFFFFFCu
#define ESW_TDSR_ADDRESS_SHIFT                   2
#define ESW_TDSR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_TDSR_ADDRESS_SHIFT))&ESW_TDSR_ADDRESS_MASK)
/* MRBR Bit Fields */
#define ESW_MRBR_SIZE_MASK                       0x3FF0u
#define ESW_MRBR_SIZE_SHIFT                      4
#define ESW_MRBR_SIZE(x)                         (((uint32_t)(((uint32_t)(x))<<ESW_MRBR_SIZE_SHIFT))&ESW_MRBR_SIZE_MASK)
/* RDAR Bit Fields */
#define ESW_RDAR_RDAR_MASK                       0x1000000u
#define ESW_RDAR_RDAR_SHIFT                      24
/* TDAR Bit Fields */
#define ESW_TDAR_TDAR_MASK                       0x1000000u
#define ESW_TDAR_TDAR_SHIFT                      24
/* LREC0 Bit Fields */
#define ESW_LREC0_MAC_ADDR0_MASK                 0xFFFFFFFFu
#define ESW_LREC0_MAC_ADDR0_SHIFT                0
#define ESW_LREC0_MAC_ADDR0(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_LREC0_MAC_ADDR0_SHIFT))&ESW_LREC0_MAC_ADDR0_MASK)
/* LREC1 Bit Fields */
#define ESW_LREC1_MAC_ADDR1_MASK                 0xFFFFu
#define ESW_LREC1_MAC_ADDR1_SHIFT                0
#define ESW_LREC1_MAC_ADDR1(x)                   (((uint32_t)(((uint32_t)(x))<<ESW_LREC1_MAC_ADDR1_SHIFT))&ESW_LREC1_MAC_ADDR1_MASK)
#define ESW_LREC1_HASH_MASK                      0xFF0000u
#define ESW_LREC1_HASH_SHIFT                     16
#define ESW_LREC1_HASH(x)                        (((uint32_t)(((uint32_t)(x))<<ESW_LREC1_HASH_SHIFT))&ESW_LREC1_HASH_MASK)
#define ESW_LREC1_SWPORT_MASK                    0x3000000u
#define ESW_LREC1_SWPORT_SHIFT                   24
#define ESW_LREC1_SWPORT(x)                      (((uint32_t)(((uint32_t)(x))<<ESW_LREC1_SWPORT_SHIFT))&ESW_LREC1_SWPORT_MASK)
/* LSR Bit Fields */
#define ESW_LSR_DA_MASK                          0x1u
#define ESW_LSR_DA_SHIFT                         0

/**
 * @}
 */ /* end of group ESW_Register_Masks */


/* ESW - Peripheral instance base addresses */
/** Peripheral ESW base address */
#define ESW_BASE                                 (0x400E8000u)
/** Peripheral ESW base pointer */
#define ESW                                      ((ESW_Type *)ESW_BASE)
/** Array initializer of ESW peripheral base pointers */
#define ESW_BASES                                { ESW }

/**
 * @}
 */ /* end of group ESW_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- EWM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
 * @{
 */

/** EWM - Register Layout Typedef */
typedef struct {
  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
  __IO uint8_t CLKCTRL;                            /**< Clock Control Register, offset: 0x4 */
  __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type;

/* ----------------------------------------------------------------------------
   -- EWM Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup EWM_Register_Masks EWM Register Masks
 * @{
 */

/* CTRL Bit Fields */
#define EWM_CTRL_EWMEN_MASK                      0x1u
#define EWM_CTRL_EWMEN_SHIFT                     0
#define EWM_CTRL_ASSIN_MASK                      0x2u
#define EWM_CTRL_ASSIN_SHIFT                     1
#define EWM_CTRL_INEN_MASK                       0x4u
#define EWM_CTRL_INEN_SHIFT                      2
#define EWM_CTRL_INTEN_MASK                      0x8u
#define EWM_CTRL_INTEN_SHIFT                     3
/* SERV Bit Fields */
#define EWM_SERV_SERVICE_MASK                    0xFFu
#define EWM_SERV_SERVICE_SHIFT                   0
#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
/* CMPL Bit Fields */
#define EWM_CMPL_COMPAREL_MASK                   0xFFu
#define EWM_CMPL_COMPAREL_SHIFT                  0
#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
/* CMPH Bit Fields */
#define EWM_CMPH_COMPAREH_MASK                   0xFFu
#define EWM_CMPH_COMPAREH_SHIFT                  0
#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
/* CLKCTRL Bit Fields */
#define EWM_CLKCTRL_CLKSEL_MASK                  0x3u
#define EWM_CLKCTRL_CLKSEL_SHIFT                 0
#define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x))<<EWM_CLKCTRL_CLKSEL_SHIFT))&EWM_CLKCTRL_CLKSEL_MASK)
/* CLKPRESCALER Bit Fields */
#define EWM_CLKPRESCALER_CLK_DIV_MASK            0xFFu
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT           0
#define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)

/**
 * @}
 */ /* end of group EWM_Register_Masks */


/* EWM - Peripheral instance base addresses */
/** Peripheral EWM base address */
#define EWM_BASE                                 (0x40065000u)
/** Peripheral EWM base pointer */
#define EWM                                      ((EWM_Type *)EWM_BASE)
/** Array initializer of EWM peripheral base pointers */
#define EWM_BASES                                { EWM }

/**
 * @}
 */ /* end of group EWM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
 * @{
 */

/** FB - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0xC */
    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
  } CS[4];
       uint8_t RESERVED_0[48];
  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
} FB_Type;

/* ----------------------------------------------------------------------------
   -- FB Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup FB_Register_Masks FB Register Masks
 * @{
 */

/* CSAR Bit Fields */
#define FB_CSAR_BA_MASK                          0xFFFF0000u
#define FB_CSAR_BA_SHIFT                         16
#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
/* CSMR Bit Fields */
#define FB_CSMR_V_MASK                           0x1u
#define FB_CSMR_V_SHIFT                          0
#define FB_CSMR_WP_MASK                          0x100u
#define FB_CSMR_WP_SHIFT                         8
#define FB_CSMR_BAM_MASK                         0xFFFF0000u
#define FB_CSMR_BAM_SHIFT                        16
#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
/* CSCR Bit Fields */
#define FB_CSCR_BSTW_MASK                        0x8u
#define FB_CSCR_BSTW_SHIFT                       3
#define FB_CSCR_BSTR_MASK                        0x10u
#define FB_CSCR_BSTR_SHIFT                       4
#define FB_CSCR_BEM_MASK                         0x20u
#define FB_CSCR_BEM_SHIFT                        5
#define FB_CSCR_PS_MASK                          0xC0u
#define FB_CSCR_PS_SHIFT                         6
#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
#define FB_CSCR_AA_MASK                          0x100u
#define FB_CSCR_AA_SHIFT                         8
#define FB_CSCR_BLS_MASK                         0x200u
#define FB_CSCR_BLS_SHIFT                        9
#define FB_CSCR_WS_MASK                          0xFC00u
#define FB_CSCR_WS_SHIFT                         10
#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
#define FB_CSCR_WRAH_MASK                        0x30000u
#define FB_CSCR_WRAH_SHIFT                       16
#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
#define FB_CSCR_RDAH_MASK                        0xC0000u
#define FB_CSCR_RDAH_SHIFT                       18
#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
#define FB_CSCR_ASET_MASK                        0x300000u
#define FB_CSCR_ASET_SHIFT                       20
#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
#define FB_CSCR_EXTS_MASK                        0x400000u
#define FB_CSCR_EXTS_SHIFT                       22
#define FB_CSCR_SWSEN_MASK                       0x800000u
#define FB_CSCR_SWSEN_SHIFT                      23
#define FB_CSCR_SWS_MASK                         0xFC000000u
#define FB_CSCR_SWS_SHIFT                        26
#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
/* CSPMCR Bit Fields */
#define FB_CSPMCR_GROUP5_MASK                    0xF000u
#define FB_CSPMCR_GROUP5_SHIFT                   12
#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
#define FB_CSPMCR_GROUP4_SHIFT                   16
#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
#define FB_CSPMCR_GROUP3_SHIFT                   20
#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
#define FB_CSPMCR_GROUP2_SHIFT                   24
#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
#define FB_CSPMCR_GROUP1_SHIFT                   28
#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)

/**
 * @}
 */ /* end of group FB_Register_Masks */


/* FB - Peripheral instance base addresses */
/** Peripheral FB base address */
#define FB_BASE                                  (0x4001E000u)
/** Peripheral FB base pointer */
#define FB                                       ((FB_Type *)FB_BASE)
/** Array initializer of FB peripheral base pointers */
#define FB_BASES                                 { FB }

/**
 * @}
 */ /* end of group FB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FTM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
 * @{
 */

/** FTM - Register Layout Typedef */
typedef struct {
  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
  struct {                                         /* offset: 0xC, array step: 0x8 */
    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
  } CONTROLS[8];
  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
  __I  uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
} FTM_Type;

/* ----------------------------------------------------------------------------
   -- FTM Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup FTM_Register_Masks FTM Register Masks
 * @{
 */

/* SC Bit Fields */
#define FTM_SC_PS_MASK                           0x7u
#define FTM_SC_PS_SHIFT                          0
#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
#define FTM_SC_CLKS_MASK                         0x18u
#define FTM_SC_CLKS_SHIFT                        3
#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
#define FTM_SC_CPWMS_MASK                        0x20u
#define FTM_SC_CPWMS_SHIFT                       5
#define FTM_SC_TOIE_MASK                         0x40u
#define FTM_SC_TOIE_SHIFT                        6
#define FTM_SC_TOF_MASK                          0x80u
#define FTM_SC_TOF_SHIFT                         7
/* CNT Bit Fields */
#define FTM_CNT_COUNT_MASK                       0xFFFFu
#define FTM_CNT_COUNT_SHIFT                      0
#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
/* MOD Bit Fields */
#define FTM_MOD_MOD_MASK                         0xFFFFu
#define FTM_MOD_MOD_SHIFT                        0
#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
/* CnSC Bit Fields */
#define FTM_CnSC_DMA_MASK                        0x1u
#define FTM_CnSC_DMA_SHIFT                       0
#define FTM_CnSC_ELSA_MASK                       0x4u
#define FTM_CnSC_ELSA_SHIFT                      2
#define FTM_CnSC_ELSB_MASK                       0x8u
#define FTM_CnSC_ELSB_SHIFT                      3
#define FTM_CnSC_MSA_MASK                        0x10u
#define FTM_CnSC_MSA_SHIFT                       4
#define FTM_CnSC_MSB_MASK                        0x20u
#define FTM_CnSC_MSB_SHIFT                       5
#define FTM_CnSC_CHIE_MASK                       0x40u
#define FTM_CnSC_CHIE_SHIFT                      6
#define FTM_CnSC_CHF_MASK                        0x80u
#define FTM_CnSC_CHF_SHIFT                       7
/* CnV Bit Fields */
#define FTM_CnV_VAL_MASK                         0xFFFFu
#define FTM_CnV_VAL_SHIFT                        0
#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
/* CNTIN Bit Fields */
#define FTM_CNTIN_INIT_MASK                      0xFFFFu
#define FTM_CNTIN_INIT_SHIFT                     0
#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
/* STATUS Bit Fields */
#define FTM_STATUS_CH0F_MASK                     0x1u
#define FTM_STATUS_CH0F_SHIFT                    0
#define FTM_STATUS_CH1F_MASK                     0x2u
#define FTM_STATUS_CH1F_SHIFT                    1
#define FTM_STATUS_CH2F_MASK                     0x4u
#define FTM_STATUS_CH2F_SHIFT                    2
#define FTM_STATUS_CH3F_MASK                     0x8u
#define FTM_STATUS_CH3F_SHIFT                    3
#define FTM_STATUS_CH4F_MASK                     0x10u
#define FTM_STATUS_CH4F_SHIFT                    4
#define FTM_STATUS_CH5F_MASK                     0x20u
#define FTM_STATUS_CH5F_SHIFT                    5
#define FTM_STATUS_CH6F_MASK                     0x40u
#define FTM_STATUS_CH6F_SHIFT                    6
#define FTM_STATUS_CH7F_MASK                     0x80u
#define FTM_STATUS_CH7F_SHIFT                    7
/* MODE Bit Fields */
#define FTM_MODE_FTMEN_MASK                      0x1u
#define FTM_MODE_FTMEN_SHIFT                     0
#define FTM_MODE_INIT_MASK                       0x2u
#define FTM_MODE_INIT_SHIFT                      1
#define FTM_MODE_WPDIS_MASK                      0x4u
#define FTM_MODE_WPDIS_SHIFT                     2
#define FTM_MODE_PWMSYNC_MASK                    0x8u
#define FTM_MODE_PWMSYNC_SHIFT                   3
#define FTM_MODE_CAPTEST_MASK                    0x10u
#define FTM_MODE_CAPTEST_SHIFT                   4
#define FTM_MODE_FAULTM_MASK                     0x60u
#define FTM_MODE_FAULTM_SHIFT                    5
#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
#define FTM_MODE_FAULTIE_MASK                    0x80u
#define FTM_MODE_FAULTIE_SHIFT                   7
/* SYNC Bit Fields */
#define FTM_SYNC_CNTMIN_MASK                     0x1u
#define FTM_SYNC_CNTMIN_SHIFT                    0
#define FTM_SYNC_CNTMAX_MASK                     0x2u
#define FTM_SYNC_CNTMAX_SHIFT                    1
#define FTM_SYNC_REINIT_MASK                     0x4u
#define FTM_SYNC_REINIT_SHIFT                    2
#define FTM_SYNC_SYNCHOM_MASK                    0x8u
#define FTM_SYNC_SYNCHOM_SHIFT                   3
#define FTM_SYNC_TRIG0_MASK                      0x10u
#define FTM_SYNC_TRIG0_SHIFT                     4
#define FTM_SYNC_TRIG1_MASK                      0x20u
#define FTM_SYNC_TRIG1_SHIFT                     5
#define FTM_SYNC_TRIG2_MASK                      0x40u
#define FTM_SYNC_TRIG2_SHIFT                     6
#define FTM_SYNC_SWSYNC_MASK                     0x80u
#define FTM_SYNC_SWSYNC_SHIFT                    7
/* OUTINIT Bit Fields */
#define FTM_OUTINIT_CH0OI_MASK                   0x1u
#define FTM_OUTINIT_CH0OI_SHIFT                  0
#define FTM_OUTINIT_CH1OI_MASK                   0x2u
#define FTM_OUTINIT_CH1OI_SHIFT                  1
#define FTM_OUTINIT_CH2OI_MASK                   0x4u
#define FTM_OUTINIT_CH2OI_SHIFT                  2
#define FTM_OUTINIT_CH3OI_MASK                   0x8u
#define FTM_OUTINIT_CH3OI_SHIFT                  3
#define FTM_OUTINIT_CH4OI_MASK                   0x10u
#define FTM_OUTINIT_CH4OI_SHIFT                  4
#define FTM_OUTINIT_CH5OI_MASK                   0x20u
#define FTM_OUTINIT_CH5OI_SHIFT                  5
#define FTM_OUTINIT_CH6OI_MASK                   0x40u
#define FTM_OUTINIT_CH6OI_SHIFT                  6
#define FTM_OUTINIT_CH7OI_MASK                   0x80u
#define FTM_OUTINIT_CH7OI_SHIFT                  7
/* OUTMASK Bit Fields */
#define FTM_OUTMASK_CH0OM_MASK                   0x1u
#define FTM_OUTMASK_CH0OM_SHIFT                  0
#define FTM_OUTMASK_CH1OM_MASK                   0x2u
#define FTM_OUTMASK_CH1OM_SHIFT                  1
#define FTM_OUTMASK_CH2OM_MASK                   0x4u
#define FTM_OUTMASK_CH2OM_SHIFT                  2
#define FTM_OUTMASK_CH3OM_MASK                   0x8u
#define FTM_OUTMASK_CH3OM_SHIFT                  3
#define FTM_OUTMASK_CH4OM_MASK                   0x10u
#define FTM_OUTMASK_CH4OM_SHIFT                  4
#define FTM_OUTMASK_CH5OM_MASK                   0x20u
#define FTM_OUTMASK_CH5OM_SHIFT                  5
#define FTM_OUTMASK_CH6OM_MASK                   0x40u
#define FTM_OUTMASK_CH6OM_SHIFT                  6
#define FTM_OUTMASK_CH7OM_MASK                   0x80u
#define FTM_OUTMASK_CH7OM_SHIFT                  7
/* COMBINE Bit Fields */
#define FTM_COMBINE_COMBINE0_MASK                0x1u
#define FTM_COMBINE_COMBINE0_SHIFT               0
#define FTM_COMBINE_COMP0_MASK                   0x2u
#define FTM_COMBINE_COMP0_SHIFT                  1
#define FTM_COMBINE_DECAPEN0_MASK                0x4u
#define FTM_COMBINE_DECAPEN0_SHIFT               2
#define FTM_COMBINE_DECAP0_MASK                  0x8u
#define FTM_COMBINE_DECAP0_SHIFT                 3
#define FTM_COMBINE_DTEN0_MASK                   0x10u
#define FTM_COMBINE_DTEN0_SHIFT                  4
#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
#define FTM_COMBINE_SYNCEN0_SHIFT                5
#define FTM_COMBINE_FAULTEN0_MASK                0x40u
#define FTM_COMBINE_FAULTEN0_SHIFT               6
#define FTM_COMBINE_COMBINE1_MASK                0x100u
#define FTM_COMBINE_COMBINE1_SHIFT               8
#define FTM_COMBINE_COMP1_MASK                   0x200u
#define FTM_COMBINE_COMP1_SHIFT                  9
#define FTM_COMBINE_DECAPEN1_MASK                0x400u
#define FTM_COMBINE_DECAPEN1_SHIFT               10
#define FTM_COMBINE_DECAP1_MASK                  0x800u
#define FTM_COMBINE_DECAP1_SHIFT                 11
#define FTM_COMBINE_DTEN1_MASK                   0x1000u
#define FTM_COMBINE_DTEN1_SHIFT                  12
#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
#define FTM_COMBINE_SYNCEN1_SHIFT                13
#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
#define FTM_COMBINE_FAULTEN1_SHIFT               14
#define FTM_COMBINE_COMBINE2_MASK                0x10000u
#define FTM_COMBINE_COMBINE2_SHIFT               16
#define FTM_COMBINE_COMP2_MASK                   0x20000u
#define FTM_COMBINE_COMP2_SHIFT                  17
#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
#define FTM_COMBINE_DECAPEN2_SHIFT               18
#define FTM_COMBINE_DECAP2_MASK                  0x80000u
#define FTM_COMBINE_DECAP2_SHIFT                 19
#define FTM_COMBINE_DTEN2_MASK                   0x100000u
#define FTM_COMBINE_DTEN2_SHIFT                  20
#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
#define FTM_COMBINE_SYNCEN2_SHIFT                21
#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
#define FTM_COMBINE_FAULTEN2_SHIFT               22
#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
#define FTM_COMBINE_COMBINE3_SHIFT               24
#define FTM_COMBINE_COMP3_MASK                   0x2000000u
#define FTM_COMBINE_COMP3_SHIFT                  25
#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
#define FTM_COMBINE_DECAPEN3_SHIFT               26
#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
#define FTM_COMBINE_DECAP3_SHIFT                 27
#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
#define FTM_COMBINE_DTEN3_SHIFT                  28
#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
#define FTM_COMBINE_SYNCEN3_SHIFT                29
#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
#define FTM_COMBINE_FAULTEN3_SHIFT               30
/* DEADTIME Bit Fields */
#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
#define FTM_DEADTIME_DTVAL_SHIFT                 0
#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
#define FTM_DEADTIME_DTPS_MASK                   0xC0u
#define FTM_DEADTIME_DTPS_SHIFT                  6
#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
/* EXTTRIG Bit Fields */
#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
#define FTM_EXTTRIG_TRIGF_SHIFT                  7
/* POL Bit Fields */
#define FTM_POL_POL0_MASK                        0x1u
#define FTM_POL_POL0_SHIFT                       0
#define FTM_POL_POL1_MASK                        0x2u
#define FTM_POL_POL1_SHIFT                       1
#define FTM_POL_POL2_MASK                        0x4u
#define FTM_POL_POL2_SHIFT                       2
#define FTM_POL_POL3_MASK                        0x8u
#define FTM_POL_POL3_SHIFT                       3
#define FTM_POL_POL4_MASK                        0x10u
#define FTM_POL_POL4_SHIFT                       4
#define FTM_POL_POL5_MASK                        0x20u
#define FTM_POL_POL5_SHIFT                       5
#define FTM_POL_POL6_MASK                        0x40u
#define FTM_POL_POL6_SHIFT                       6
#define FTM_POL_POL7_MASK                        0x80u
#define FTM_POL_POL7_SHIFT                       7
/* FMS Bit Fields */
#define FTM_FMS_FAULTF0_MASK                     0x1u
#define FTM_FMS_FAULTF0_SHIFT                    0
#define FTM_FMS_FAULTF1_MASK                     0x2u
#define FTM_FMS_FAULTF1_SHIFT                    1
#define FTM_FMS_FAULTF2_MASK                     0x4u
#define FTM_FMS_FAULTF2_SHIFT                    2
#define FTM_FMS_FAULTF3_MASK                     0x8u
#define FTM_FMS_FAULTF3_SHIFT                    3
#define FTM_FMS_FAULTIN_MASK                     0x20u
#define FTM_FMS_FAULTIN_SHIFT                    5
#define FTM_FMS_WPEN_MASK                        0x40u
#define FTM_FMS_WPEN_SHIFT                       6
#define FTM_FMS_FAULTF_MASK                      0x80u
#define FTM_FMS_FAULTF_SHIFT                     7
/* FILTER Bit Fields */
#define FTM_FILTER_CH0FVAL_MASK                  0xFu
#define FTM_FILTER_CH0FVAL_SHIFT                 0
#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
#define FTM_FILTER_CH1FVAL_SHIFT                 4
#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
#define FTM_FILTER_CH2FVAL_SHIFT                 8
#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
#define FTM_FILTER_CH3FVAL_SHIFT                 12
#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
/* FLTCTRL Bit Fields */
#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
#define FTM_FLTCTRL_FFVAL_SHIFT                  8
#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
/* QDCTRL Bit Fields */
#define FTM_QDCTRL_QUADEN_MASK                   0x1u
#define FTM_QDCTRL_QUADEN_SHIFT                  0
#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
#define FTM_QDCTRL_TOFDIR_SHIFT                  1
#define FTM_QDCTRL_QUADIR_MASK                   0x4u
#define FTM_QDCTRL_QUADIR_SHIFT                  2
#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
#define FTM_QDCTRL_QUADMODE_SHIFT                3
#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
#define FTM_QDCTRL_PHBPOL_SHIFT                  4
#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
#define FTM_QDCTRL_PHAPOL_SHIFT                  5
#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
/* CONF Bit Fields */
#define FTM_CONF_NUMTOF_MASK                     0x1Fu
#define FTM_CONF_NUMTOF_SHIFT                    0
#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
#define FTM_CONF_BDMMODE_MASK                    0xC0u
#define FTM_CONF_BDMMODE_SHIFT                   6
#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
#define FTM_CONF_GTBEEN_MASK                     0x200u
#define FTM_CONF_GTBEEN_SHIFT                    9
#define FTM_CONF_GTBEOUT_MASK                    0x400u
#define FTM_CONF_GTBEOUT_SHIFT                   10
/* FLTPOL Bit Fields */
#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
#define FTM_FLTPOL_FLT0POL_SHIFT                 0
#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
#define FTM_FLTPOL_FLT1POL_SHIFT                 1
#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
#define FTM_FLTPOL_FLT2POL_SHIFT                 2
#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
#define FTM_FLTPOL_FLT3POL_SHIFT                 3
/* SYNCONF Bit Fields */
#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
#define FTM_SYNCONF_CNTINC_MASK                  0x4u
#define FTM_SYNCONF_CNTINC_SHIFT                 2
#define FTM_SYNCONF_INVC_MASK                    0x10u
#define FTM_SYNCONF_INVC_SHIFT                   4
#define FTM_SYNCONF_SWOC_MASK                    0x20u
#define FTM_SYNCONF_SWOC_SHIFT                   5
#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
#define FTM_SYNCONF_SYNCMODE_SHIFT               7
#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
#define FTM_SYNCONF_SWWRBUF_SHIFT                9
#define FTM_SYNCONF_SWOM_MASK                    0x400u
#define FTM_SYNCONF_SWOM_SHIFT                   10
#define FTM_SYNCONF_SWINVC_MASK                  0x800u
#define FTM_SYNCONF_SWINVC_SHIFT                 11
#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
#define FTM_SYNCONF_SWSOC_SHIFT                  12
#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
#define FTM_SYNCONF_HWWRBUF_SHIFT                17
#define FTM_SYNCONF_HWOM_MASK                    0x40000u
#define FTM_SYNCONF_HWOM_SHIFT                   18
#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
#define FTM_SYNCONF_HWINVC_SHIFT                 19
#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
#define FTM_SYNCONF_HWSOC_SHIFT                  20
/* INVCTRL Bit Fields */
#define FTM_INVCTRL_INV0EN_MASK                  0x1u
#define FTM_INVCTRL_INV0EN_SHIFT                 0
#define FTM_INVCTRL_INV1EN_MASK                  0x2u
#define FTM_INVCTRL_INV1EN_SHIFT                 1
#define FTM_INVCTRL_INV2EN_MASK                  0x4u
#define FTM_INVCTRL_INV2EN_SHIFT                 2
#define FTM_INVCTRL_INV3EN_MASK                  0x8u
#define FTM_INVCTRL_INV3EN_SHIFT                 3
/* SWOCTRL Bit Fields */
#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
#define FTM_SWOCTRL_CH0OC_SHIFT                  0
#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
#define FTM_SWOCTRL_CH1OC_SHIFT                  1
#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
#define FTM_SWOCTRL_CH2OC_SHIFT                  2
#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
#define FTM_SWOCTRL_CH3OC_SHIFT                  3
#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
#define FTM_SWOCTRL_CH4OC_SHIFT                  4
#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
#define FTM_SWOCTRL_CH5OC_SHIFT                  5
#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
#define FTM_SWOCTRL_CH6OC_SHIFT                  6
#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
#define FTM_SWOCTRL_CH7OC_SHIFT                  7
#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
/* PWMLOAD Bit Fields */
#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
#define FTM_PWMLOAD_LDOK_MASK                    0x200u
#define FTM_PWMLOAD_LDOK_SHIFT                   9

/**
 * @}
 */ /* end of group FTM_Register_Masks */


/* FTM - Peripheral instance base addresses */
/** Peripheral FTM0 base address */
#define FTM0_BASE                                (0x40038000u)
/** Peripheral FTM0 base pointer */
#define FTM0                                     ((FTM_Type *)FTM0_BASE)
/** Peripheral FTM1 base address */
#define FTM1_BASE                                (0x40039000u)
/** Peripheral FTM1 base pointer */
#define FTM1                                     ((FTM_Type *)FTM1_BASE)
/** Peripheral FTM2 base address */
#define FTM2_BASE                                (0x400B8000u)
/** Peripheral FTM2 base pointer */
#define FTM2                                     ((FTM_Type *)FTM2_BASE)
/** Peripheral FTM3 base address */
#define FTM3_BASE                                (0x400B9000u)
/** Peripheral FTM3 base pointer */
#define FTM3                                     ((FTM_Type *)FTM3_BASE)
/** Array initializer of FTM peripheral base pointers */
#define FTM_BASES                                { FTM0, FTM1, FTM2, FTM3 }

/**
 * @}
 */ /* end of group FTM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GIC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GIC_Peripheral_Access_Layer GIC Peripheral Access Layer
 * @{
 */

/** GIC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[256];
  __IO uint32_t ICR[1];                            /**< CPU Interface Control Register, array offset: 0x100, array step: 0x4 */
  __IO uint32_t PMR[1];                            /**< Interrupt Priority Mask Register, array offset: 0x104, array step: 0x4 */
  __IO uint32_t BPR[1];                            /**< Binary Point Register, array offset: 0x108, array step: 0x4 */
  __IO uint32_t IAR[1];                            /**< Interrupt Acknowledge Register, array offset: 0x10C, array step: 0x4 */
  __IO uint32_t EOIR[1];                           /**< End of Interrupt Register, array offset: 0x110, array step: 0x4 */
  __IO uint32_t RPR[1];                            /**< Running Priority Register, array offset: 0x114, array step: 0x4 */
  __IO uint32_t HPIR[1];                           /**< Highest Pending Interrupt Register, array offset: 0x118, array step: 0x4 */
  __IO uint32_t ABPR[1];                           /**< Aliased Binary Point Register, array offset: 0x11C, array step: 0x4 */
       uint8_t RESERVED_1[3808];
  __IO uint32_t DCR[1];                            /**< Distributor Control Register, array offset: 0x1000, array step: 0x4 */
       uint8_t RESERVED_2[124];
  __IO uint32_t ICDISR[5];                         /**< Interrupt Security Register 0..Interrupt Security Register 4, array offset: 0x1080, array step: 0x4 */
       uint8_t RESERVED_3[108];
  __IO uint32_t ICDISER[5];                        /**< Interrupt Set-Enable Register 0..Interrupt Set-Enable Register 4, array offset: 0x1100, array step: 0x4 */
       uint8_t RESERVED_4[108];
  __IO uint32_t ICDICER[5];                        /**< Interrupt Clear-Enable Registe 0..Interrupt Clear-Enable Registe 4, array offset: 0x1180, array step: 0x4 */
       uint8_t RESERVED_5[108];
  __IO uint32_t ICDISPR[5];                        /**< Interrupt Set-Pending Register 0..Interrupt Set-Pending Register 4, array offset: 0x1200, array step: 0x4 */
       uint8_t RESERVED_6[108];
  __IO uint32_t ICDICPR[5];                        /**< Interrupt Security Register 0..Interrupt Security Register 4, array offset: 0x1280, array step: 0x4 */
       uint8_t RESERVED_7[108];
  __IO uint32_t ICDABR[5];                         /**< Active Bit Register 0..Active Bit Register 4, array offset: 0x1300, array step: 0x4 */
       uint8_t RESERVED_8[236];
  __IO uint32_t ICDIPR[36];                        /**< Interrupt Priority Register 0..Interrupt Priority Register 35, array offset: 0x1400, array step: 0x4 */
       uint8_t RESERVED_9[880];
  __IO uint32_t ICDIPTR[36];                       /**< Interrupt Processor Targets Register 0..Interrupt Processor Targets Register 35, array offset: 0x1800, array step: 0x4 */
       uint8_t RESERVED_10[880];
  __IO uint32_t ICDICFR[9];                        /**< Interrupt Configuration Register 0..Interrupt Configuration Register 8, array offset: 0x1C00, array step: 0x4 */
       uint8_t RESERVED_11[220];
  __I  uint32_t PPIS[1];                           /**< Private Peripheral Interrupt Status Register, array offset: 0x1D00, array step: 0x4 */
  __IO uint32_t ICDSPIS[5];                        /**< Shared Peripheral Interrupt Status Register 0..Shared Peripheral Interrupt Status Register 4, array offset: 0x1D04, array step: 0x4 */
       uint8_t RESERVED_12[488];
  __IO uint32_t SGIR[1];                           /**< Software Generated Interrupt Register, array offset: 0x1F00, array step: 0x4 */
} GIC_Type;

/* ----------------------------------------------------------------------------
   -- GIC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GIC_Register_Masks GIC Register Masks
 * @{
 */

/* ICR Bit Fields */
#define GIC_ICR_ENABLES_MASK                     0x1u
#define GIC_ICR_ENABLES_SHIFT                    0
#define GIC_ICR_ENABLENS_MASK                    0x2u
#define GIC_ICR_ENABLENS_SHIFT                   1
#define GIC_ICR_ACKCTL_MASK                      0x4u
#define GIC_ICR_ACKCTL_SHIFT                     2
#define GIC_ICR_FIQEN_MASK                       0x8u
#define GIC_ICR_FIQEN_SHIFT                      3
#define GIC_ICR_SBPR_MASK                        0x10u
#define GIC_ICR_SBPR_SHIFT                       4
/* PMR Bit Fields */
#define GIC_PMR_PRIORITY_MASK                    0xFFu
#define GIC_PMR_PRIORITY_SHIFT                   0
#define GIC_PMR_PRIORITY(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_PMR_PRIORITY_SHIFT))&GIC_PMR_PRIORITY_MASK)
/* BPR Bit Fields */
#define GIC_BPR_BINPOINT_MASK                    0x7u
#define GIC_BPR_BINPOINT_SHIFT                   0
#define GIC_BPR_BINPOINT(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_BPR_BINPOINT_SHIFT))&GIC_BPR_BINPOINT_MASK)
/* IAR Bit Fields */
#define GIC_IAR_ACKINTID_MASK                    0x3FFu
#define GIC_IAR_ACKINTID_SHIFT                   0
#define GIC_IAR_ACKINTID(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_IAR_ACKINTID_SHIFT))&GIC_IAR_ACKINTID_MASK)
#define GIC_IAR_CPUID_MASK                       0x1C00u
#define GIC_IAR_CPUID_SHIFT                      10
#define GIC_IAR_CPUID(x)                         (((uint32_t)(((uint32_t)(x))<<GIC_IAR_CPUID_SHIFT))&GIC_IAR_CPUID_MASK)
/* EOIR Bit Fields */
#define GIC_EOIR_EOIINTID_MASK                   0x3FFu
#define GIC_EOIR_EOIINTID_SHIFT                  0
#define GIC_EOIR_EOIINTID(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_EOIR_EOIINTID_SHIFT))&GIC_EOIR_EOIINTID_MASK)
#define GIC_EOIR_CPUID_MASK                      0x1C00u
#define GIC_EOIR_CPUID_SHIFT                     10
#define GIC_EOIR_CPUID(x)                        (((uint32_t)(((uint32_t)(x))<<GIC_EOIR_CPUID_SHIFT))&GIC_EOIR_CPUID_MASK)
/* RPR Bit Fields */
#define GIC_RPR_PRIORITY_MASK                    0xFFu
#define GIC_RPR_PRIORITY_SHIFT                   0
#define GIC_RPR_PRIORITY(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_RPR_PRIORITY_SHIFT))&GIC_RPR_PRIORITY_MASK)
/* HPIR Bit Fields */
#define GIC_HPIR_PENDINTID_MASK                  0x3FFu
#define GIC_HPIR_PENDINTID_SHIFT                 0
#define GIC_HPIR_PENDINTID(x)                    (((uint32_t)(((uint32_t)(x))<<GIC_HPIR_PENDINTID_SHIFT))&GIC_HPIR_PENDINTID_MASK)
#define GIC_HPIR_CPUID_MASK                      0x1C00u
#define GIC_HPIR_CPUID_SHIFT                     10
#define GIC_HPIR_CPUID(x)                        (((uint32_t)(((uint32_t)(x))<<GIC_HPIR_CPUID_SHIFT))&GIC_HPIR_CPUID_MASK)
/* ABPR Bit Fields */
#define GIC_ABPR_BINPOINT_MASK                   0x3u
#define GIC_ABPR_BINPOINT_SHIFT                  0
#define GIC_ABPR_BINPOINT(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ABPR_BINPOINT_SHIFT))&GIC_ABPR_BINPOINT_MASK)
/* DCR Bit Fields */
#define GIC_DCR_ENABLE_MASK                      0x1u
#define GIC_DCR_ENABLE_SHIFT                     0
#define GIC_DCR_ENABLE1_MASK                     0x2u
#define GIC_DCR_ENABLE1_SHIFT                    1
/* ICDISR Bit Fields */
#define GIC_ICDISR_SETSTA_MASK                   0xFFFFFFFFu
#define GIC_ICDISR_SETSTA_SHIFT                  0
#define GIC_ICDISR_SETSTA(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDISR_SETSTA_SHIFT))&GIC_ICDISR_SETSTA_MASK)
/* ICDISER Bit Fields */
#define GIC_ICDISER_SETENA_MASK                  0xFFFFFFFFu
#define GIC_ICDISER_SETENA_SHIFT                 0
#define GIC_ICDISER_SETENA(x)                    (((uint32_t)(((uint32_t)(x))<<GIC_ICDISER_SETENA_SHIFT))&GIC_ICDISER_SETENA_MASK)
/* ICDICER Bit Fields */
#define GIC_ICDICER_CLRENA_MASK                  0xFFFFFFFFu
#define GIC_ICDICER_CLRENA_SHIFT                 0
#define GIC_ICDICER_CLRENA(x)                    (((uint32_t)(((uint32_t)(x))<<GIC_ICDICER_CLRENA_SHIFT))&GIC_ICDICER_CLRENA_MASK)
/* ICDISPR Bit Fields */
#define GIC_ICDISPR_SETPEND_MASK                 0xFFFFFFFFu
#define GIC_ICDISPR_SETPEND_SHIFT                0
#define GIC_ICDISPR_SETPEND(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDISPR_SETPEND_SHIFT))&GIC_ICDISPR_SETPEND_MASK)
/* ICDICPR Bit Fields */
#define GIC_ICDICPR_CLRPEND_MASK                 0xFFFFFFFFu
#define GIC_ICDICPR_CLRPEND_SHIFT                0
#define GIC_ICDICPR_CLRPEND(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICPR_CLRPEND_SHIFT))&GIC_ICDICPR_CLRPEND_MASK)
/* ICDABR Bit Fields */
#define GIC_ICDABR_ACTIVE_MASK                   0xFFFFFFFFu
#define GIC_ICDABR_ACTIVE_SHIFT                  0
#define GIC_ICDABR_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDABR_ACTIVE_SHIFT))&GIC_ICDABR_ACTIVE_MASK)
/* ICDIPR Bit Fields */
#define GIC_ICDIPR_PRI0_MASK                     0xFFu
#define GIC_ICDIPR_PRI0_SHIFT                    0
#define GIC_ICDIPR_PRI0(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI0_SHIFT))&GIC_ICDIPR_PRI0_MASK)
#define GIC_ICDIPR_PRI140_MASK                   0xFFu
#define GIC_ICDIPR_PRI140_SHIFT                  0
#define GIC_ICDIPR_PRI140(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI140_SHIFT))&GIC_ICDIPR_PRI140_MASK)
#define GIC_ICDIPR_PRI136_MASK                   0xFFu
#define GIC_ICDIPR_PRI136_SHIFT                  0
#define GIC_ICDIPR_PRI136(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI136_SHIFT))&GIC_ICDIPR_PRI136_MASK)
#define GIC_ICDIPR_PRI132_MASK                   0xFFu
#define GIC_ICDIPR_PRI132_SHIFT                  0
#define GIC_ICDIPR_PRI132(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI132_SHIFT))&GIC_ICDIPR_PRI132_MASK)
#define GIC_ICDIPR_PRI4_MASK                     0xFFu
#define GIC_ICDIPR_PRI4_SHIFT                    0
#define GIC_ICDIPR_PRI4(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI4_SHIFT))&GIC_ICDIPR_PRI4_MASK)
#define GIC_ICDIPR_PRI128_MASK                   0xFFu
#define GIC_ICDIPR_PRI128_SHIFT                  0
#define GIC_ICDIPR_PRI128(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI128_SHIFT))&GIC_ICDIPR_PRI128_MASK)
#define GIC_ICDIPR_PRI124_MASK                   0xFFu
#define GIC_ICDIPR_PRI124_SHIFT                  0
#define GIC_ICDIPR_PRI124(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI124_SHIFT))&GIC_ICDIPR_PRI124_MASK)
#define GIC_ICDIPR_PRI120_MASK                   0xFFu
#define GIC_ICDIPR_PRI120_SHIFT                  0
#define GIC_ICDIPR_PRI120(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI120_SHIFT))&GIC_ICDIPR_PRI120_MASK)
#define GIC_ICDIPR_PRI8_MASK                     0xFFu
#define GIC_ICDIPR_PRI8_SHIFT                    0
#define GIC_ICDIPR_PRI8(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI8_SHIFT))&GIC_ICDIPR_PRI8_MASK)
#define GIC_ICDIPR_PRI116_MASK                   0xFFu
#define GIC_ICDIPR_PRI116_SHIFT                  0
#define GIC_ICDIPR_PRI116(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI116_SHIFT))&GIC_ICDIPR_PRI116_MASK)
#define GIC_ICDIPR_PRI112_MASK                   0xFFu
#define GIC_ICDIPR_PRI112_SHIFT                  0
#define GIC_ICDIPR_PRI112(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI112_SHIFT))&GIC_ICDIPR_PRI112_MASK)
#define GIC_ICDIPR_PRI108_MASK                   0xFFu
#define GIC_ICDIPR_PRI108_SHIFT                  0
#define GIC_ICDIPR_PRI108(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI108_SHIFT))&GIC_ICDIPR_PRI108_MASK)
#define GIC_ICDIPR_PRI12_MASK                    0xFFu
#define GIC_ICDIPR_PRI12_SHIFT                   0
#define GIC_ICDIPR_PRI12(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI12_SHIFT))&GIC_ICDIPR_PRI12_MASK)
#define GIC_ICDIPR_PRI104_MASK                   0xFFu
#define GIC_ICDIPR_PRI104_SHIFT                  0
#define GIC_ICDIPR_PRI104(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI104_SHIFT))&GIC_ICDIPR_PRI104_MASK)
#define GIC_ICDIPR_PRI100_MASK                   0xFFu
#define GIC_ICDIPR_PRI100_SHIFT                  0
#define GIC_ICDIPR_PRI100(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI100_SHIFT))&GIC_ICDIPR_PRI100_MASK)
#define GIC_ICDIPR_PRI96_MASK                    0xFFu
#define GIC_ICDIPR_PRI96_SHIFT                   0
#define GIC_ICDIPR_PRI96(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI96_SHIFT))&GIC_ICDIPR_PRI96_MASK)
#define GIC_ICDIPR_PRI16_MASK                    0xFFu
#define GIC_ICDIPR_PRI16_SHIFT                   0
#define GIC_ICDIPR_PRI16(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI16_SHIFT))&GIC_ICDIPR_PRI16_MASK)
#define GIC_ICDIPR_PRI92_MASK                    0xFFu
#define GIC_ICDIPR_PRI92_SHIFT                   0
#define GIC_ICDIPR_PRI92(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI92_SHIFT))&GIC_ICDIPR_PRI92_MASK)
#define GIC_ICDIPR_PRI88_MASK                    0xFFu
#define GIC_ICDIPR_PRI88_SHIFT                   0
#define GIC_ICDIPR_PRI88(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI88_SHIFT))&GIC_ICDIPR_PRI88_MASK)
#define GIC_ICDIPR_PRI84_MASK                    0xFFu
#define GIC_ICDIPR_PRI84_SHIFT                   0
#define GIC_ICDIPR_PRI84(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI84_SHIFT))&GIC_ICDIPR_PRI84_MASK)
#define GIC_ICDIPR_PRI20_MASK                    0xFFu
#define GIC_ICDIPR_PRI20_SHIFT                   0
#define GIC_ICDIPR_PRI20(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI20_SHIFT))&GIC_ICDIPR_PRI20_MASK)
#define GIC_ICDIPR_PRI80_MASK                    0xFFu
#define GIC_ICDIPR_PRI80_SHIFT                   0
#define GIC_ICDIPR_PRI80(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI80_SHIFT))&GIC_ICDIPR_PRI80_MASK)
#define GIC_ICDIPR_PRI76_MASK                    0xFFu
#define GIC_ICDIPR_PRI76_SHIFT                   0
#define GIC_ICDIPR_PRI76(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI76_SHIFT))&GIC_ICDIPR_PRI76_MASK)
#define GIC_ICDIPR_PRI72_MASK                    0xFFu
#define GIC_ICDIPR_PRI72_SHIFT                   0
#define GIC_ICDIPR_PRI72(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI72_SHIFT))&GIC_ICDIPR_PRI72_MASK)
#define GIC_ICDIPR_PRI24_MASK                    0xFFu
#define GIC_ICDIPR_PRI24_SHIFT                   0
#define GIC_ICDIPR_PRI24(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI24_SHIFT))&GIC_ICDIPR_PRI24_MASK)
#define GIC_ICDIPR_PRI68_MASK                    0xFFu
#define GIC_ICDIPR_PRI68_SHIFT                   0
#define GIC_ICDIPR_PRI68(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI68_SHIFT))&GIC_ICDIPR_PRI68_MASK)
#define GIC_ICDIPR_PRI64_MASK                    0xFFu
#define GIC_ICDIPR_PRI64_SHIFT                   0
#define GIC_ICDIPR_PRI64(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI64_SHIFT))&GIC_ICDIPR_PRI64_MASK)
#define GIC_ICDIPR_PRI60_MASK                    0xFFu
#define GIC_ICDIPR_PRI60_SHIFT                   0
#define GIC_ICDIPR_PRI60(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI60_SHIFT))&GIC_ICDIPR_PRI60_MASK)
#define GIC_ICDIPR_PRI28_MASK                    0xFFu
#define GIC_ICDIPR_PRI28_SHIFT                   0
#define GIC_ICDIPR_PRI28(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI28_SHIFT))&GIC_ICDIPR_PRI28_MASK)
#define GIC_ICDIPR_PRI56_MASK                    0xFFu
#define GIC_ICDIPR_PRI56_SHIFT                   0
#define GIC_ICDIPR_PRI56(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI56_SHIFT))&GIC_ICDIPR_PRI56_MASK)
#define GIC_ICDIPR_PRI52_MASK                    0xFFu
#define GIC_ICDIPR_PRI52_SHIFT                   0
#define GIC_ICDIPR_PRI52(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI52_SHIFT))&GIC_ICDIPR_PRI52_MASK)
#define GIC_ICDIPR_PRI48_MASK                    0xFFu
#define GIC_ICDIPR_PRI48_SHIFT                   0
#define GIC_ICDIPR_PRI48(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI48_SHIFT))&GIC_ICDIPR_PRI48_MASK)
#define GIC_ICDIPR_PRI32_MASK                    0xFFu
#define GIC_ICDIPR_PRI32_SHIFT                   0
#define GIC_ICDIPR_PRI32(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI32_SHIFT))&GIC_ICDIPR_PRI32_MASK)
#define GIC_ICDIPR_PRI44_MASK                    0xFFu
#define GIC_ICDIPR_PRI44_SHIFT                   0
#define GIC_ICDIPR_PRI44(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI44_SHIFT))&GIC_ICDIPR_PRI44_MASK)
#define GIC_ICDIPR_PRI40_MASK                    0xFFu
#define GIC_ICDIPR_PRI40_SHIFT                   0
#define GIC_ICDIPR_PRI40(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI40_SHIFT))&GIC_ICDIPR_PRI40_MASK)
#define GIC_ICDIPR_PRI36_MASK                    0xFFu
#define GIC_ICDIPR_PRI36_SHIFT                   0
#define GIC_ICDIPR_PRI36(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI36_SHIFT))&GIC_ICDIPR_PRI36_MASK)
#define GIC_ICDIPR_PRI33_MASK                    0xFF00u
#define GIC_ICDIPR_PRI33_SHIFT                   8
#define GIC_ICDIPR_PRI33(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI33_SHIFT))&GIC_ICDIPR_PRI33_MASK)
#define GIC_ICDIPR_PRI109_MASK                   0xFF00u
#define GIC_ICDIPR_PRI109_SHIFT                  8
#define GIC_ICDIPR_PRI109(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI109_SHIFT))&GIC_ICDIPR_PRI109_MASK)
#define GIC_ICDIPR_PRI105_MASK                   0xFF00u
#define GIC_ICDIPR_PRI105_SHIFT                  8
#define GIC_ICDIPR_PRI105(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI105_SHIFT))&GIC_ICDIPR_PRI105_MASK)
#define GIC_ICDIPR_PRI13_MASK                    0xFF00u
#define GIC_ICDIPR_PRI13_SHIFT                   8
#define GIC_ICDIPR_PRI13(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI13_SHIFT))&GIC_ICDIPR_PRI13_MASK)
#define GIC_ICDIPR_PRI1_MASK                     0xFF00u
#define GIC_ICDIPR_PRI1_SHIFT                    8
#define GIC_ICDIPR_PRI1(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI1_SHIFT))&GIC_ICDIPR_PRI1_MASK)
#define GIC_ICDIPR_PRI61_MASK                    0xFF00u
#define GIC_ICDIPR_PRI61_SHIFT                   8
#define GIC_ICDIPR_PRI61(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI61_SHIFT))&GIC_ICDIPR_PRI61_MASK)
#define GIC_ICDIPR_PRI101_MASK                   0xFF00u
#define GIC_ICDIPR_PRI101_SHIFT                  8
#define GIC_ICDIPR_PRI101(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI101_SHIFT))&GIC_ICDIPR_PRI101_MASK)
#define GIC_ICDIPR_PRI69_MASK                    0xFF00u
#define GIC_ICDIPR_PRI69_SHIFT                   8
#define GIC_ICDIPR_PRI69(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI69_SHIFT))&GIC_ICDIPR_PRI69_MASK)
#define GIC_ICDIPR_PRI57_MASK                    0xFF00u
#define GIC_ICDIPR_PRI57_SHIFT                   8
#define GIC_ICDIPR_PRI57(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI57_SHIFT))&GIC_ICDIPR_PRI57_MASK)
#define GIC_ICDIPR_PRI113_MASK                   0xFF00u
#define GIC_ICDIPR_PRI113_SHIFT                  8
#define GIC_ICDIPR_PRI113(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI113_SHIFT))&GIC_ICDIPR_PRI113_MASK)
#define GIC_ICDIPR_PRI97_MASK                    0xFF00u
#define GIC_ICDIPR_PRI97_SHIFT                   8
#define GIC_ICDIPR_PRI97(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI97_SHIFT))&GIC_ICDIPR_PRI97_MASK)
#define GIC_ICDIPR_PRI29_MASK                    0xFF00u
#define GIC_ICDIPR_PRI29_SHIFT                   8
#define GIC_ICDIPR_PRI29(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI29_SHIFT))&GIC_ICDIPR_PRI29_MASK)
#define GIC_ICDIPR_PRI5_MASK                     0xFF00u
#define GIC_ICDIPR_PRI5_SHIFT                    8
#define GIC_ICDIPR_PRI5(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI5_SHIFT))&GIC_ICDIPR_PRI5_MASK)
#define GIC_ICDIPR_PRI129_MASK                   0xFF00u
#define GIC_ICDIPR_PRI129_SHIFT                  8
#define GIC_ICDIPR_PRI129(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI129_SHIFT))&GIC_ICDIPR_PRI129_MASK)
#define GIC_ICDIPR_PRI93_MASK                    0xFF00u
#define GIC_ICDIPR_PRI93_SHIFT                   8
#define GIC_ICDIPR_PRI93(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI93_SHIFT))&GIC_ICDIPR_PRI93_MASK)
#define GIC_ICDIPR_PRI17_MASK                    0xFF00u
#define GIC_ICDIPR_PRI17_SHIFT                   8
#define GIC_ICDIPR_PRI17(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI17_SHIFT))&GIC_ICDIPR_PRI17_MASK)
#define GIC_ICDIPR_PRI9_MASK                     0xFF00u
#define GIC_ICDIPR_PRI9_SHIFT                    8
#define GIC_ICDIPR_PRI9(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI9_SHIFT))&GIC_ICDIPR_PRI9_MASK)
#define GIC_ICDIPR_PRI117_MASK                   0xFF00u
#define GIC_ICDIPR_PRI117_SHIFT                  8
#define GIC_ICDIPR_PRI117(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI117_SHIFT))&GIC_ICDIPR_PRI117_MASK)
#define GIC_ICDIPR_PRI89_MASK                    0xFF00u
#define GIC_ICDIPR_PRI89_SHIFT                   8
#define GIC_ICDIPR_PRI89(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI89_SHIFT))&GIC_ICDIPR_PRI89_MASK)
#define GIC_ICDIPR_PRI141_MASK                   0xFF00u
#define GIC_ICDIPR_PRI141_SHIFT                  8
#define GIC_ICDIPR_PRI141(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI141_SHIFT))&GIC_ICDIPR_PRI141_MASK)
#define GIC_ICDIPR_PRI53_MASK                    0xFF00u
#define GIC_ICDIPR_PRI53_SHIFT                   8
#define GIC_ICDIPR_PRI53(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI53_SHIFT))&GIC_ICDIPR_PRI53_MASK)
#define GIC_ICDIPR_PRI45_MASK                    0xFF00u
#define GIC_ICDIPR_PRI45_SHIFT                   8
#define GIC_ICDIPR_PRI45(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI45_SHIFT))&GIC_ICDIPR_PRI45_MASK)
#define GIC_ICDIPR_PRI85_MASK                    0xFF00u
#define GIC_ICDIPR_PRI85_SHIFT                   8
#define GIC_ICDIPR_PRI85(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI85_SHIFT))&GIC_ICDIPR_PRI85_MASK)
#define GIC_ICDIPR_PRI137_MASK                   0xFF00u
#define GIC_ICDIPR_PRI137_SHIFT                  8
#define GIC_ICDIPR_PRI137(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI137_SHIFT))&GIC_ICDIPR_PRI137_MASK)
#define GIC_ICDIPR_PRI41_MASK                    0xFF00u
#define GIC_ICDIPR_PRI41_SHIFT                   8
#define GIC_ICDIPR_PRI41(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI41_SHIFT))&GIC_ICDIPR_PRI41_MASK)
#define GIC_ICDIPR_PRI121_MASK                   0xFF00u
#define GIC_ICDIPR_PRI121_SHIFT                  8
#define GIC_ICDIPR_PRI121(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI121_SHIFT))&GIC_ICDIPR_PRI121_MASK)
#define GIC_ICDIPR_PRI81_MASK                    0xFF00u
#define GIC_ICDIPR_PRI81_SHIFT                   8
#define GIC_ICDIPR_PRI81(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI81_SHIFT))&GIC_ICDIPR_PRI81_MASK)
#define GIC_ICDIPR_PRI21_MASK                    0xFF00u
#define GIC_ICDIPR_PRI21_SHIFT                   8
#define GIC_ICDIPR_PRI21(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI21_SHIFT))&GIC_ICDIPR_PRI21_MASK)
#define GIC_ICDIPR_PRI25_MASK                    0xFF00u
#define GIC_ICDIPR_PRI25_SHIFT                   8
#define GIC_ICDIPR_PRI25(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI25_SHIFT))&GIC_ICDIPR_PRI25_MASK)
#define GIC_ICDIPR_PRI65_MASK                    0xFF00u
#define GIC_ICDIPR_PRI65_SHIFT                   8
#define GIC_ICDIPR_PRI65(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI65_SHIFT))&GIC_ICDIPR_PRI65_MASK)
#define GIC_ICDIPR_PRI77_MASK                    0xFF00u
#define GIC_ICDIPR_PRI77_SHIFT                   8
#define GIC_ICDIPR_PRI77(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI77_SHIFT))&GIC_ICDIPR_PRI77_MASK)
#define GIC_ICDIPR_PRI133_MASK                   0xFF00u
#define GIC_ICDIPR_PRI133_SHIFT                  8
#define GIC_ICDIPR_PRI133(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI133_SHIFT))&GIC_ICDIPR_PRI133_MASK)
#define GIC_ICDIPR_PRI49_MASK                    0xFF00u
#define GIC_ICDIPR_PRI49_SHIFT                   8
#define GIC_ICDIPR_PRI49(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI49_SHIFT))&GIC_ICDIPR_PRI49_MASK)
#define GIC_ICDIPR_PRI125_MASK                   0xFF00u
#define GIC_ICDIPR_PRI125_SHIFT                  8
#define GIC_ICDIPR_PRI125(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI125_SHIFT))&GIC_ICDIPR_PRI125_MASK)
#define GIC_ICDIPR_PRI73_MASK                    0xFF00u
#define GIC_ICDIPR_PRI73_SHIFT                   8
#define GIC_ICDIPR_PRI73(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI73_SHIFT))&GIC_ICDIPR_PRI73_MASK)
#define GIC_ICDIPR_PRI37_MASK                    0xFF00u
#define GIC_ICDIPR_PRI37_SHIFT                   8
#define GIC_ICDIPR_PRI37(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI37_SHIFT))&GIC_ICDIPR_PRI37_MASK)
#define GIC_ICDIPR_PRI38_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI38_SHIFT                   16
#define GIC_ICDIPR_PRI38(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI38_SHIFT))&GIC_ICDIPR_PRI38_MASK)
#define GIC_ICDIPR_PRI106_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI106_SHIFT                  16
#define GIC_ICDIPR_PRI106(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI106_SHIFT))&GIC_ICDIPR_PRI106_MASK)
#define GIC_ICDIPR_PRI58_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI58_SHIFT                   16
#define GIC_ICDIPR_PRI58(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI58_SHIFT))&GIC_ICDIPR_PRI58_MASK)
#define GIC_ICDIPR_PRI102_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI102_SHIFT                  16
#define GIC_ICDIPR_PRI102(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI102_SHIFT))&GIC_ICDIPR_PRI102_MASK)
#define GIC_ICDIPR_PRI14_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI14_SHIFT                   16
#define GIC_ICDIPR_PRI14(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI14_SHIFT))&GIC_ICDIPR_PRI14_MASK)
#define GIC_ICDIPR_PRI98_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI98_SHIFT                   16
#define GIC_ICDIPR_PRI98(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI98_SHIFT))&GIC_ICDIPR_PRI98_MASK)
#define GIC_ICDIPR_PRI42_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI42_SHIFT                   16
#define GIC_ICDIPR_PRI42(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI42_SHIFT))&GIC_ICDIPR_PRI42_MASK)
#define GIC_ICDIPR_PRI94_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI94_SHIFT                   16
#define GIC_ICDIPR_PRI94(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI94_SHIFT))&GIC_ICDIPR_PRI94_MASK)
#define GIC_ICDIPR_PRI54_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI54_SHIFT                   16
#define GIC_ICDIPR_PRI54(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI54_SHIFT))&GIC_ICDIPR_PRI54_MASK)
#define GIC_ICDIPR_PRI90_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI90_SHIFT                   16
#define GIC_ICDIPR_PRI90(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI90_SHIFT))&GIC_ICDIPR_PRI90_MASK)
#define GIC_ICDIPR_PRI18_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI18_SHIFT                   16
#define GIC_ICDIPR_PRI18(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI18_SHIFT))&GIC_ICDIPR_PRI18_MASK)
#define GIC_ICDIPR_PRI86_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI86_SHIFT                   16
#define GIC_ICDIPR_PRI86(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI86_SHIFT))&GIC_ICDIPR_PRI86_MASK)
#define GIC_ICDIPR_PRI30_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI30_SHIFT                   16
#define GIC_ICDIPR_PRI30(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI30_SHIFT))&GIC_ICDIPR_PRI30_MASK)
#define GIC_ICDIPR_PRI82_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI82_SHIFT                   16
#define GIC_ICDIPR_PRI82(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI82_SHIFT))&GIC_ICDIPR_PRI82_MASK)
#define GIC_ICDIPR_PRI50_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI50_SHIFT                   16
#define GIC_ICDIPR_PRI50(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI50_SHIFT))&GIC_ICDIPR_PRI50_MASK)
#define GIC_ICDIPR_PRI78_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI78_SHIFT                   16
#define GIC_ICDIPR_PRI78(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI78_SHIFT))&GIC_ICDIPR_PRI78_MASK)
#define GIC_ICDIPR_PRI22_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI22_SHIFT                   16
#define GIC_ICDIPR_PRI22(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI22_SHIFT))&GIC_ICDIPR_PRI22_MASK)
#define GIC_ICDIPR_PRI74_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI74_SHIFT                   16
#define GIC_ICDIPR_PRI74(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI74_SHIFT))&GIC_ICDIPR_PRI74_MASK)
#define GIC_ICDIPR_PRI110_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI110_SHIFT                  16
#define GIC_ICDIPR_PRI110(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI110_SHIFT))&GIC_ICDIPR_PRI110_MASK)
#define GIC_ICDIPR_PRI10_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI10_SHIFT                   16
#define GIC_ICDIPR_PRI10(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI10_SHIFT))&GIC_ICDIPR_PRI10_MASK)
#define GIC_ICDIPR_PRI114_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI114_SHIFT                  16
#define GIC_ICDIPR_PRI114(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI114_SHIFT))&GIC_ICDIPR_PRI114_MASK)
#define GIC_ICDIPR_PRI62_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI62_SHIFT                   16
#define GIC_ICDIPR_PRI62(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI62_SHIFT))&GIC_ICDIPR_PRI62_MASK)
#define GIC_ICDIPR_PRI118_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI118_SHIFT                  16
#define GIC_ICDIPR_PRI118(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI118_SHIFT))&GIC_ICDIPR_PRI118_MASK)
#define GIC_ICDIPR_PRI26_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI26_SHIFT                   16
#define GIC_ICDIPR_PRI26(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI26_SHIFT))&GIC_ICDIPR_PRI26_MASK)
#define GIC_ICDIPR_PRI122_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI122_SHIFT                  16
#define GIC_ICDIPR_PRI122(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI122_SHIFT))&GIC_ICDIPR_PRI122_MASK)
#define GIC_ICDIPR_PRI6_MASK                     0xFF0000u
#define GIC_ICDIPR_PRI6_SHIFT                    16
#define GIC_ICDIPR_PRI6(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI6_SHIFT))&GIC_ICDIPR_PRI6_MASK)
#define GIC_ICDIPR_PRI126_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI126_SHIFT                  16
#define GIC_ICDIPR_PRI126(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI126_SHIFT))&GIC_ICDIPR_PRI126_MASK)
#define GIC_ICDIPR_PRI66_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI66_SHIFT                   16
#define GIC_ICDIPR_PRI66(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI66_SHIFT))&GIC_ICDIPR_PRI66_MASK)
#define GIC_ICDIPR_PRI130_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI130_SHIFT                  16
#define GIC_ICDIPR_PRI130(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI130_SHIFT))&GIC_ICDIPR_PRI130_MASK)
#define GIC_ICDIPR_PRI46_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI46_SHIFT                   16
#define GIC_ICDIPR_PRI46(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI46_SHIFT))&GIC_ICDIPR_PRI46_MASK)
#define GIC_ICDIPR_PRI134_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI134_SHIFT                  16
#define GIC_ICDIPR_PRI134(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI134_SHIFT))&GIC_ICDIPR_PRI134_MASK)
#define GIC_ICDIPR_PRI2_MASK                     0xFF0000u
#define GIC_ICDIPR_PRI2_SHIFT                    16
#define GIC_ICDIPR_PRI2(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI2_SHIFT))&GIC_ICDIPR_PRI2_MASK)
#define GIC_ICDIPR_PRI138_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI138_SHIFT                  16
#define GIC_ICDIPR_PRI138(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI138_SHIFT))&GIC_ICDIPR_PRI138_MASK)
#define GIC_ICDIPR_PRI70_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI70_SHIFT                   16
#define GIC_ICDIPR_PRI70(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI70_SHIFT))&GIC_ICDIPR_PRI70_MASK)
#define GIC_ICDIPR_PRI142_MASK                   0xFF0000u
#define GIC_ICDIPR_PRI142_SHIFT                  16
#define GIC_ICDIPR_PRI142(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI142_SHIFT))&GIC_ICDIPR_PRI142_MASK)
#define GIC_ICDIPR_PRI34_MASK                    0xFF0000u
#define GIC_ICDIPR_PRI34_SHIFT                   16
#define GIC_ICDIPR_PRI34(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI34_SHIFT))&GIC_ICDIPR_PRI34_MASK)
#define GIC_ICDIPR_PRI143_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI143_SHIFT                  24
#define GIC_ICDIPR_PRI143(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI143_SHIFT))&GIC_ICDIPR_PRI143_MASK)
#define GIC_ICDIPR_PRI139_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI139_SHIFT                  24
#define GIC_ICDIPR_PRI139(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI139_SHIFT))&GIC_ICDIPR_PRI139_MASK)
#define GIC_ICDIPR_PRI135_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI135_SHIFT                  24
#define GIC_ICDIPR_PRI135(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI135_SHIFT))&GIC_ICDIPR_PRI135_MASK)
#define GIC_ICDIPR_PRI3_MASK                     0xFF000000u
#define GIC_ICDIPR_PRI3_SHIFT                    24
#define GIC_ICDIPR_PRI3(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI3_SHIFT))&GIC_ICDIPR_PRI3_MASK)
#define GIC_ICDIPR_PRI131_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI131_SHIFT                  24
#define GIC_ICDIPR_PRI131(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI131_SHIFT))&GIC_ICDIPR_PRI131_MASK)
#define GIC_ICDIPR_PRI127_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI127_SHIFT                  24
#define GIC_ICDIPR_PRI127(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI127_SHIFT))&GIC_ICDIPR_PRI127_MASK)
#define GIC_ICDIPR_PRI123_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI123_SHIFT                  24
#define GIC_ICDIPR_PRI123(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI123_SHIFT))&GIC_ICDIPR_PRI123_MASK)
#define GIC_ICDIPR_PRI7_MASK                     0xFF000000u
#define GIC_ICDIPR_PRI7_SHIFT                    24
#define GIC_ICDIPR_PRI7(x)                       (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI7_SHIFT))&GIC_ICDIPR_PRI7_MASK)
#define GIC_ICDIPR_PRI119_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI119_SHIFT                  24
#define GIC_ICDIPR_PRI119(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI119_SHIFT))&GIC_ICDIPR_PRI119_MASK)
#define GIC_ICDIPR_PRI115_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI115_SHIFT                  24
#define GIC_ICDIPR_PRI115(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI115_SHIFT))&GIC_ICDIPR_PRI115_MASK)
#define GIC_ICDIPR_PRI111_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI111_SHIFT                  24
#define GIC_ICDIPR_PRI111(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI111_SHIFT))&GIC_ICDIPR_PRI111_MASK)
#define GIC_ICDIPR_PRI11_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI11_SHIFT                   24
#define GIC_ICDIPR_PRI11(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI11_SHIFT))&GIC_ICDIPR_PRI11_MASK)
#define GIC_ICDIPR_PRI107_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI107_SHIFT                  24
#define GIC_ICDIPR_PRI107(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI107_SHIFT))&GIC_ICDIPR_PRI107_MASK)
#define GIC_ICDIPR_PRI103_MASK                   0xFF000000u
#define GIC_ICDIPR_PRI103_SHIFT                  24
#define GIC_ICDIPR_PRI103(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI103_SHIFT))&GIC_ICDIPR_PRI103_MASK)
#define GIC_ICDIPR_PRI99_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI99_SHIFT                   24
#define GIC_ICDIPR_PRI99(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI99_SHIFT))&GIC_ICDIPR_PRI99_MASK)
#define GIC_ICDIPR_PRI15_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI15_SHIFT                   24
#define GIC_ICDIPR_PRI15(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI15_SHIFT))&GIC_ICDIPR_PRI15_MASK)
#define GIC_ICDIPR_PRI95_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI95_SHIFT                   24
#define GIC_ICDIPR_PRI95(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI95_SHIFT))&GIC_ICDIPR_PRI95_MASK)
#define GIC_ICDIPR_PRI91_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI91_SHIFT                   24
#define GIC_ICDIPR_PRI91(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI91_SHIFT))&GIC_ICDIPR_PRI91_MASK)
#define GIC_ICDIPR_PRI87_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI87_SHIFT                   24
#define GIC_ICDIPR_PRI87(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI87_SHIFT))&GIC_ICDIPR_PRI87_MASK)
#define GIC_ICDIPR_PRI19_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI19_SHIFT                   24
#define GIC_ICDIPR_PRI19(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI19_SHIFT))&GIC_ICDIPR_PRI19_MASK)
#define GIC_ICDIPR_PRI83_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI83_SHIFT                   24
#define GIC_ICDIPR_PRI83(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI83_SHIFT))&GIC_ICDIPR_PRI83_MASK)
#define GIC_ICDIPR_PRI79_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI79_SHIFT                   24
#define GIC_ICDIPR_PRI79(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI79_SHIFT))&GIC_ICDIPR_PRI79_MASK)
#define GIC_ICDIPR_PRI75_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI75_SHIFT                   24
#define GIC_ICDIPR_PRI75(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI75_SHIFT))&GIC_ICDIPR_PRI75_MASK)
#define GIC_ICDIPR_PRI23_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI23_SHIFT                   24
#define GIC_ICDIPR_PRI23(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI23_SHIFT))&GIC_ICDIPR_PRI23_MASK)
#define GIC_ICDIPR_PRI71_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI71_SHIFT                   24
#define GIC_ICDIPR_PRI71(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI71_SHIFT))&GIC_ICDIPR_PRI71_MASK)
#define GIC_ICDIPR_PRI67_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI67_SHIFT                   24
#define GIC_ICDIPR_PRI67(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI67_SHIFT))&GIC_ICDIPR_PRI67_MASK)
#define GIC_ICDIPR_PRI63_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI63_SHIFT                   24
#define GIC_ICDIPR_PRI63(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI63_SHIFT))&GIC_ICDIPR_PRI63_MASK)
#define GIC_ICDIPR_PRI27_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI27_SHIFT                   24
#define GIC_ICDIPR_PRI27(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI27_SHIFT))&GIC_ICDIPR_PRI27_MASK)
#define GIC_ICDIPR_PRI59_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI59_SHIFT                   24
#define GIC_ICDIPR_PRI59(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI59_SHIFT))&GIC_ICDIPR_PRI59_MASK)
#define GIC_ICDIPR_PRI55_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI55_SHIFT                   24
#define GIC_ICDIPR_PRI55(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI55_SHIFT))&GIC_ICDIPR_PRI55_MASK)
#define GIC_ICDIPR_PRI51_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI51_SHIFT                   24
#define GIC_ICDIPR_PRI51(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI51_SHIFT))&GIC_ICDIPR_PRI51_MASK)
#define GIC_ICDIPR_PRI31_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI31_SHIFT                   24
#define GIC_ICDIPR_PRI31(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI31_SHIFT))&GIC_ICDIPR_PRI31_MASK)
#define GIC_ICDIPR_PRI47_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI47_SHIFT                   24
#define GIC_ICDIPR_PRI47(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI47_SHIFT))&GIC_ICDIPR_PRI47_MASK)
#define GIC_ICDIPR_PRI43_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI43_SHIFT                   24
#define GIC_ICDIPR_PRI43(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI43_SHIFT))&GIC_ICDIPR_PRI43_MASK)
#define GIC_ICDIPR_PRI39_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI39_SHIFT                   24
#define GIC_ICDIPR_PRI39(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI39_SHIFT))&GIC_ICDIPR_PRI39_MASK)
#define GIC_ICDIPR_PRI35_MASK                    0xFF000000u
#define GIC_ICDIPR_PRI35_SHIFT                   24
#define GIC_ICDIPR_PRI35(x)                      (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPR_PRI35_SHIFT))&GIC_ICDIPR_PRI35_MASK)
/* ICDIPTR Bit Fields */
#define GIC_ICDIPTR_CPUTRGTLST0_MASK             0xFFu
#define GIC_ICDIPTR_CPUTRGTLST0_SHIFT            0
#define GIC_ICDIPTR_CPUTRGTLST0(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST0_SHIFT))&GIC_ICDIPTR_CPUTRGTLST0_MASK)
#define GIC_ICDIPTR_CPUTRGTLST140_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST140_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST140(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST140_SHIFT))&GIC_ICDIPTR_CPUTRGTLST140_MASK)
#define GIC_ICDIPTR_CPUTRGTLST136_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST136_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST136(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST136_SHIFT))&GIC_ICDIPTR_CPUTRGTLST136_MASK)
#define GIC_ICDIPTR_CPUTRGTLST132_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST132_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST132(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST132_SHIFT))&GIC_ICDIPTR_CPUTRGTLST132_MASK)
#define GIC_ICDIPTR_CPUTRGTLST4_MASK             0xFFu
#define GIC_ICDIPTR_CPUTRGTLST4_SHIFT            0
#define GIC_ICDIPTR_CPUTRGTLST4(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST4_SHIFT))&GIC_ICDIPTR_CPUTRGTLST4_MASK)
#define GIC_ICDIPTR_CPUTRGTLST128_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST128_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST128(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST128_SHIFT))&GIC_ICDIPTR_CPUTRGTLST128_MASK)
#define GIC_ICDIPTR_CPUTRGTLST124_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST124_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST124(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST124_SHIFT))&GIC_ICDIPTR_CPUTRGTLST124_MASK)
#define GIC_ICDIPTR_CPUTRGTLST120_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST120_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST120(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST120_SHIFT))&GIC_ICDIPTR_CPUTRGTLST120_MASK)
#define GIC_ICDIPTR_CPUTRGTLST8_MASK             0xFFu
#define GIC_ICDIPTR_CPUTRGTLST8_SHIFT            0
#define GIC_ICDIPTR_CPUTRGTLST8(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST8_SHIFT))&GIC_ICDIPTR_CPUTRGTLST8_MASK)
#define GIC_ICDIPTR_CPUTRGTLST116_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST116_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST116(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST116_SHIFT))&GIC_ICDIPTR_CPUTRGTLST116_MASK)
#define GIC_ICDIPTR_CPUTRGTLST112_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST112_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST112(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST112_SHIFT))&GIC_ICDIPTR_CPUTRGTLST112_MASK)
#define GIC_ICDIPTR_CPUTRGTLST108_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST108_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST108(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST108_SHIFT))&GIC_ICDIPTR_CPUTRGTLST108_MASK)
#define GIC_ICDIPTR_CPUTRGTLST12_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST12_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST12(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST12_SHIFT))&GIC_ICDIPTR_CPUTRGTLST12_MASK)
#define GIC_ICDIPTR_CPUTRGTLST104_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST104_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST104(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST104_SHIFT))&GIC_ICDIPTR_CPUTRGTLST104_MASK)
#define GIC_ICDIPTR_CPUTRGTLST100_MASK           0xFFu
#define GIC_ICDIPTR_CPUTRGTLST100_SHIFT          0
#define GIC_ICDIPTR_CPUTRGTLST100(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST100_SHIFT))&GIC_ICDIPTR_CPUTRGTLST100_MASK)
#define GIC_ICDIPTR_CPUTRGTLST96_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST96_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST96(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST96_SHIFT))&GIC_ICDIPTR_CPUTRGTLST96_MASK)
#define GIC_ICDIPTR_CPUTRGTLST16_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST16_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST16(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST16_SHIFT))&GIC_ICDIPTR_CPUTRGTLST16_MASK)
#define GIC_ICDIPTR_CPUTRGTLST92_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST92_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST92(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST92_SHIFT))&GIC_ICDIPTR_CPUTRGTLST92_MASK)
#define GIC_ICDIPTR_CPUTRGTLST88_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST88_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST88(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST88_SHIFT))&GIC_ICDIPTR_CPUTRGTLST88_MASK)
#define GIC_ICDIPTR_CPUTRGTLST84_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST84_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST84(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST84_SHIFT))&GIC_ICDIPTR_CPUTRGTLST84_MASK)
#define GIC_ICDIPTR_CPUTRGTLST20_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST20_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST20(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST20_SHIFT))&GIC_ICDIPTR_CPUTRGTLST20_MASK)
#define GIC_ICDIPTR_CPUTRGTLST80_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST80_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST80(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST80_SHIFT))&GIC_ICDIPTR_CPUTRGTLST80_MASK)
#define GIC_ICDIPTR_CPUTRGTLST76_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST76_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST76(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST76_SHIFT))&GIC_ICDIPTR_CPUTRGTLST76_MASK)
#define GIC_ICDIPTR_CPUTRGTLST72_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST72_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST72(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST72_SHIFT))&GIC_ICDIPTR_CPUTRGTLST72_MASK)
#define GIC_ICDIPTR_CPUTRGTLST24_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST24_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST24(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST24_SHIFT))&GIC_ICDIPTR_CPUTRGTLST24_MASK)
#define GIC_ICDIPTR_CPUTRGTLST68_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST68_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST68(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST68_SHIFT))&GIC_ICDIPTR_CPUTRGTLST68_MASK)
#define GIC_ICDIPTR_CPUTRGTLST64_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST64_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST64(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST64_SHIFT))&GIC_ICDIPTR_CPUTRGTLST64_MASK)
#define GIC_ICDIPTR_CPUTRGTLST60_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST60_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST60(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST60_SHIFT))&GIC_ICDIPTR_CPUTRGTLST60_MASK)
#define GIC_ICDIPTR_CPUTRGTLST28_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST28_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST28(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST28_SHIFT))&GIC_ICDIPTR_CPUTRGTLST28_MASK)
#define GIC_ICDIPTR_CPUTRGTLST56_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST56_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST56(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST56_SHIFT))&GIC_ICDIPTR_CPUTRGTLST56_MASK)
#define GIC_ICDIPTR_CPUTRGTLST52_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST52_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST52(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST52_SHIFT))&GIC_ICDIPTR_CPUTRGTLST52_MASK)
#define GIC_ICDIPTR_CPUTRGTLST48_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST48_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST48(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST48_SHIFT))&GIC_ICDIPTR_CPUTRGTLST48_MASK)
#define GIC_ICDIPTR_CPUTRGTLST32_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST32_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST32(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST32_SHIFT))&GIC_ICDIPTR_CPUTRGTLST32_MASK)
#define GIC_ICDIPTR_CPUTRGTLST44_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST44_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST44(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST44_SHIFT))&GIC_ICDIPTR_CPUTRGTLST44_MASK)
#define GIC_ICDIPTR_CPUTRGTLST40_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST40_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST40(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST40_SHIFT))&GIC_ICDIPTR_CPUTRGTLST40_MASK)
#define GIC_ICDIPTR_CPUTRGTLST36_MASK            0xFFu
#define GIC_ICDIPTR_CPUTRGTLST36_SHIFT           0
#define GIC_ICDIPTR_CPUTRGTLST36(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST36_SHIFT))&GIC_ICDIPTR_CPUTRGTLST36_MASK)
#define GIC_ICDIPTR_CPUTRGTLST33_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST33_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST33(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST33_SHIFT))&GIC_ICDIPTR_CPUTRGTLST33_MASK)
#define GIC_ICDIPTR_CPUTRGTLST109_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST109_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST109(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST109_SHIFT))&GIC_ICDIPTR_CPUTRGTLST109_MASK)
#define GIC_ICDIPTR_CPUTRGTLST105_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST105_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST105(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST105_SHIFT))&GIC_ICDIPTR_CPUTRGTLST105_MASK)
#define GIC_ICDIPTR_CPUTRGTLST13_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST13_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST13(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST13_SHIFT))&GIC_ICDIPTR_CPUTRGTLST13_MASK)
#define GIC_ICDIPTR_CPUTRGTLST1_MASK             0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST1_SHIFT            8
#define GIC_ICDIPTR_CPUTRGTLST1(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST1_SHIFT))&GIC_ICDIPTR_CPUTRGTLST1_MASK)
#define GIC_ICDIPTR_CPUTRGTLST61_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST61_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST61(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST61_SHIFT))&GIC_ICDIPTR_CPUTRGTLST61_MASK)
#define GIC_ICDIPTR_CPUTRGTLST101_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST101_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST101(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST101_SHIFT))&GIC_ICDIPTR_CPUTRGTLST101_MASK)
#define GIC_ICDIPTR_CPUTRGTLST69_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST69_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST69(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST69_SHIFT))&GIC_ICDIPTR_CPUTRGTLST69_MASK)
#define GIC_ICDIPTR_CPUTRGTLST57_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST57_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST57(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST57_SHIFT))&GIC_ICDIPTR_CPUTRGTLST57_MASK)
#define GIC_ICDIPTR_CPUTRGTLST113_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST113_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST113(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST113_SHIFT))&GIC_ICDIPTR_CPUTRGTLST113_MASK)
#define GIC_ICDIPTR_CPUTRGTLST97_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST97_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST97(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST97_SHIFT))&GIC_ICDIPTR_CPUTRGTLST97_MASK)
#define GIC_ICDIPTR_CPUTRGTLST29_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST29_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST29(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST29_SHIFT))&GIC_ICDIPTR_CPUTRGTLST29_MASK)
#define GIC_ICDIPTR_CPUTRGTLST5_MASK             0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST5_SHIFT            8
#define GIC_ICDIPTR_CPUTRGTLST5(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST5_SHIFT))&GIC_ICDIPTR_CPUTRGTLST5_MASK)
#define GIC_ICDIPTR_CPUTRGTLST129_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST129_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST129(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST129_SHIFT))&GIC_ICDIPTR_CPUTRGTLST129_MASK)
#define GIC_ICDIPTR_CPUTRGTLST93_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST93_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST93(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST93_SHIFT))&GIC_ICDIPTR_CPUTRGTLST93_MASK)
#define GIC_ICDIPTR_CPUTRGTLST17_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST17_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST17(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST17_SHIFT))&GIC_ICDIPTR_CPUTRGTLST17_MASK)
#define GIC_ICDIPTR_CPUTRGTLST9_MASK             0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST9_SHIFT            8
#define GIC_ICDIPTR_CPUTRGTLST9(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST9_SHIFT))&GIC_ICDIPTR_CPUTRGTLST9_MASK)
#define GIC_ICDIPTR_CPUTRGTLST117_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST117_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST117(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST117_SHIFT))&GIC_ICDIPTR_CPUTRGTLST117_MASK)
#define GIC_ICDIPTR_CPUTRGTLST89_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST89_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST89(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST89_SHIFT))&GIC_ICDIPTR_CPUTRGTLST89_MASK)
#define GIC_ICDIPTR_CPUTRGTLST141_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST141_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST141(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST141_SHIFT))&GIC_ICDIPTR_CPUTRGTLST141_MASK)
#define GIC_ICDIPTR_CPUTRGTLST53_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST53_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST53(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST53_SHIFT))&GIC_ICDIPTR_CPUTRGTLST53_MASK)
#define GIC_ICDIPTR_CPUTRGTLST45_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST45_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST45(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST45_SHIFT))&GIC_ICDIPTR_CPUTRGTLST45_MASK)
#define GIC_ICDIPTR_CPUTRGTLST85_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST85_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST85(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST85_SHIFT))&GIC_ICDIPTR_CPUTRGTLST85_MASK)
#define GIC_ICDIPTR_CPUTRGTLST137_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST137_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST137(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST137_SHIFT))&GIC_ICDIPTR_CPUTRGTLST137_MASK)
#define GIC_ICDIPTR_CPUTRGTLST41_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST41_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST41(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST41_SHIFT))&GIC_ICDIPTR_CPUTRGTLST41_MASK)
#define GIC_ICDIPTR_CPUTRGTLST121_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST121_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST121(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST121_SHIFT))&GIC_ICDIPTR_CPUTRGTLST121_MASK)
#define GIC_ICDIPTR_CPUTRGTLST81_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST81_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST81(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST81_SHIFT))&GIC_ICDIPTR_CPUTRGTLST81_MASK)
#define GIC_ICDIPTR_CPUTRGTLST21_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST21_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST21(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST21_SHIFT))&GIC_ICDIPTR_CPUTRGTLST21_MASK)
#define GIC_ICDIPTR_CPUTRGTLST25_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST25_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST25(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST25_SHIFT))&GIC_ICDIPTR_CPUTRGTLST25_MASK)
#define GIC_ICDIPTR_CPUTRGTLST65_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST65_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST65(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST65_SHIFT))&GIC_ICDIPTR_CPUTRGTLST65_MASK)
#define GIC_ICDIPTR_CPUTRGTLST77_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST77_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST77(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST77_SHIFT))&GIC_ICDIPTR_CPUTRGTLST77_MASK)
#define GIC_ICDIPTR_CPUTRGTLST133_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST133_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST133(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST133_SHIFT))&GIC_ICDIPTR_CPUTRGTLST133_MASK)
#define GIC_ICDIPTR_CPUTRGTLST49_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST49_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST49(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST49_SHIFT))&GIC_ICDIPTR_CPUTRGTLST49_MASK)
#define GIC_ICDIPTR_CPUTRGTLST125_MASK           0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST125_SHIFT          8
#define GIC_ICDIPTR_CPUTRGTLST125(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST125_SHIFT))&GIC_ICDIPTR_CPUTRGTLST125_MASK)
#define GIC_ICDIPTR_CPUTRGTLST73_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST73_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST73(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST73_SHIFT))&GIC_ICDIPTR_CPUTRGTLST73_MASK)
#define GIC_ICDIPTR_CPUTRGTLST37_MASK            0xFF00u
#define GIC_ICDIPTR_CPUTRGTLST37_SHIFT           8
#define GIC_ICDIPTR_CPUTRGTLST37(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST37_SHIFT))&GIC_ICDIPTR_CPUTRGTLST37_MASK)
#define GIC_ICDIPTR_CPUTRGTLST38_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST38_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST38(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST38_SHIFT))&GIC_ICDIPTR_CPUTRGTLST38_MASK)
#define GIC_ICDIPTR_CPUTRGTLST106_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST106_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST106(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST106_SHIFT))&GIC_ICDIPTR_CPUTRGTLST106_MASK)
#define GIC_ICDIPTR_CPUTRGTLST58_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST58_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST58(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST58_SHIFT))&GIC_ICDIPTR_CPUTRGTLST58_MASK)
#define GIC_ICDIPTR_CPUTRGTLST102_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST102_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST102(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST102_SHIFT))&GIC_ICDIPTR_CPUTRGTLST102_MASK)
#define GIC_ICDIPTR_CPUTRGTLST14_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST14_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST14(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST14_SHIFT))&GIC_ICDIPTR_CPUTRGTLST14_MASK)
#define GIC_ICDIPTR_CPUTRGTLST98_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST98_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST98(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST98_SHIFT))&GIC_ICDIPTR_CPUTRGTLST98_MASK)
#define GIC_ICDIPTR_CPUTRGTLST42_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST42_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST42(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST42_SHIFT))&GIC_ICDIPTR_CPUTRGTLST42_MASK)
#define GIC_ICDIPTR_CPUTRGTLST94_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST94_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST94(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST94_SHIFT))&GIC_ICDIPTR_CPUTRGTLST94_MASK)
#define GIC_ICDIPTR_CPUTRGTLST54_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST54_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST54(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST54_SHIFT))&GIC_ICDIPTR_CPUTRGTLST54_MASK)
#define GIC_ICDIPTR_CPUTRGTLST90_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST90_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST90(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST90_SHIFT))&GIC_ICDIPTR_CPUTRGTLST90_MASK)
#define GIC_ICDIPTR_CPUTRGTLST18_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST18_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST18(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST18_SHIFT))&GIC_ICDIPTR_CPUTRGTLST18_MASK)
#define GIC_ICDIPTR_CPUTRGTLST86_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST86_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST86(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST86_SHIFT))&GIC_ICDIPTR_CPUTRGTLST86_MASK)
#define GIC_ICDIPTR_CPUTRGTLST30_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST30_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST30(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST30_SHIFT))&GIC_ICDIPTR_CPUTRGTLST30_MASK)
#define GIC_ICDIPTR_CPUTRGTLST82_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST82_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST82(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST82_SHIFT))&GIC_ICDIPTR_CPUTRGTLST82_MASK)
#define GIC_ICDIPTR_CPUTRGTLST50_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST50_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST50(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST50_SHIFT))&GIC_ICDIPTR_CPUTRGTLST50_MASK)
#define GIC_ICDIPTR_CPUTRGTLST78_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST78_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST78(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST78_SHIFT))&GIC_ICDIPTR_CPUTRGTLST78_MASK)
#define GIC_ICDIPTR_CPUTRGTLST22_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST22_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST22(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST22_SHIFT))&GIC_ICDIPTR_CPUTRGTLST22_MASK)
#define GIC_ICDIPTR_CPUTRGTLST74_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST74_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST74(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST74_SHIFT))&GIC_ICDIPTR_CPUTRGTLST74_MASK)
#define GIC_ICDIPTR_CPUTRGTLST110_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST110_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST110(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST110_SHIFT))&GIC_ICDIPTR_CPUTRGTLST110_MASK)
#define GIC_ICDIPTR_CPUTRGTLST10_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST10_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST10(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST10_SHIFT))&GIC_ICDIPTR_CPUTRGTLST10_MASK)
#define GIC_ICDIPTR_CPUTRGTLST114_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST114_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST114(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST114_SHIFT))&GIC_ICDIPTR_CPUTRGTLST114_MASK)
#define GIC_ICDIPTR_CPUTRGTLST62_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST62_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST62(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST62_SHIFT))&GIC_ICDIPTR_CPUTRGTLST62_MASK)
#define GIC_ICDIPTR_CPUTRGTLST118_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST118_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST118(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST118_SHIFT))&GIC_ICDIPTR_CPUTRGTLST118_MASK)
#define GIC_ICDIPTR_CPUTRGTLST26_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST26_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST26(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST26_SHIFT))&GIC_ICDIPTR_CPUTRGTLST26_MASK)
#define GIC_ICDIPTR_CPUTRGTLST122_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST122_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST122(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST122_SHIFT))&GIC_ICDIPTR_CPUTRGTLST122_MASK)
#define GIC_ICDIPTR_CPUTRGTLST6_MASK             0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST6_SHIFT            16
#define GIC_ICDIPTR_CPUTRGTLST6(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST6_SHIFT))&GIC_ICDIPTR_CPUTRGTLST6_MASK)
#define GIC_ICDIPTR_CPUTRGTLST126_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST126_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST126(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST126_SHIFT))&GIC_ICDIPTR_CPUTRGTLST126_MASK)
#define GIC_ICDIPTR_CPUTRGTLST66_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST66_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST66(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST66_SHIFT))&GIC_ICDIPTR_CPUTRGTLST66_MASK)
#define GIC_ICDIPTR_CPUTRGTLST130_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST130_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST130(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST130_SHIFT))&GIC_ICDIPTR_CPUTRGTLST130_MASK)
#define GIC_ICDIPTR_CPUTRGTLST46_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST46_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST46(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST46_SHIFT))&GIC_ICDIPTR_CPUTRGTLST46_MASK)
#define GIC_ICDIPTR_CPUTRGTLST134_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST134_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST134(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST134_SHIFT))&GIC_ICDIPTR_CPUTRGTLST134_MASK)
#define GIC_ICDIPTR_CPUTRGTLST2_MASK             0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST2_SHIFT            16
#define GIC_ICDIPTR_CPUTRGTLST2(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST2_SHIFT))&GIC_ICDIPTR_CPUTRGTLST2_MASK)
#define GIC_ICDIPTR_CPUTRGTLST138_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST138_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST138(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST138_SHIFT))&GIC_ICDIPTR_CPUTRGTLST138_MASK)
#define GIC_ICDIPTR_CPUTRGTLST70_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST70_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST70(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST70_SHIFT))&GIC_ICDIPTR_CPUTRGTLST70_MASK)
#define GIC_ICDIPTR_CPUTRGTLST142_MASK           0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST142_SHIFT          16
#define GIC_ICDIPTR_CPUTRGTLST142(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST142_SHIFT))&GIC_ICDIPTR_CPUTRGTLST142_MASK)
#define GIC_ICDIPTR_CPUTRGTLST34_MASK            0xFF0000u
#define GIC_ICDIPTR_CPUTRGTLST34_SHIFT           16
#define GIC_ICDIPTR_CPUTRGTLST34(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST34_SHIFT))&GIC_ICDIPTR_CPUTRGTLST34_MASK)
#define GIC_ICDIPTR_CPUTRGTLST143_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST143_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST143(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST143_SHIFT))&GIC_ICDIPTR_CPUTRGTLST143_MASK)
#define GIC_ICDIPTR_CPUTRGTLST139_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST139_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST139(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST139_SHIFT))&GIC_ICDIPTR_CPUTRGTLST139_MASK)
#define GIC_ICDIPTR_CPUTRGTLST135_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST135_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST135(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST135_SHIFT))&GIC_ICDIPTR_CPUTRGTLST135_MASK)
#define GIC_ICDIPTR_CPUTRGTLST3_MASK             0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST3_SHIFT            24
#define GIC_ICDIPTR_CPUTRGTLST3(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST3_SHIFT))&GIC_ICDIPTR_CPUTRGTLST3_MASK)
#define GIC_ICDIPTR_CPUTRGTLST131_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST131_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST131(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST131_SHIFT))&GIC_ICDIPTR_CPUTRGTLST131_MASK)
#define GIC_ICDIPTR_CPUTRGTLST127_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST127_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST127(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST127_SHIFT))&GIC_ICDIPTR_CPUTRGTLST127_MASK)
#define GIC_ICDIPTR_CPUTRGTLST123_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST123_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST123(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST123_SHIFT))&GIC_ICDIPTR_CPUTRGTLST123_MASK)
#define GIC_ICDIPTR_CPUTRGTLST7_MASK             0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST7_SHIFT            24
#define GIC_ICDIPTR_CPUTRGTLST7(x)               (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST7_SHIFT))&GIC_ICDIPTR_CPUTRGTLST7_MASK)
#define GIC_ICDIPTR_CPUTRGTLST119_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST119_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST119(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST119_SHIFT))&GIC_ICDIPTR_CPUTRGTLST119_MASK)
#define GIC_ICDIPTR_CPUTRGTLST115_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST115_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST115(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST115_SHIFT))&GIC_ICDIPTR_CPUTRGTLST115_MASK)
#define GIC_ICDIPTR_CPUTRGTLST111_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST111_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST111(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST111_SHIFT))&GIC_ICDIPTR_CPUTRGTLST111_MASK)
#define GIC_ICDIPTR_CPUTRGTLST11_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST11_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST11(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST11_SHIFT))&GIC_ICDIPTR_CPUTRGTLST11_MASK)
#define GIC_ICDIPTR_CPUTRGTLST107_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST107_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST107(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST107_SHIFT))&GIC_ICDIPTR_CPUTRGTLST107_MASK)
#define GIC_ICDIPTR_CPUTRGTLST103_MASK           0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST103_SHIFT          24
#define GIC_ICDIPTR_CPUTRGTLST103(x)             (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST103_SHIFT))&GIC_ICDIPTR_CPUTRGTLST103_MASK)
#define GIC_ICDIPTR_CPUTRGTLST99_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST99_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST99(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST99_SHIFT))&GIC_ICDIPTR_CPUTRGTLST99_MASK)
#define GIC_ICDIPTR_CPUTRGTLST15_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST15_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST15(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST15_SHIFT))&GIC_ICDIPTR_CPUTRGTLST15_MASK)
#define GIC_ICDIPTR_CPUTRGTLST95_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST95_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST95(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST95_SHIFT))&GIC_ICDIPTR_CPUTRGTLST95_MASK)
#define GIC_ICDIPTR_CPUTRGTLST91_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST91_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST91(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST91_SHIFT))&GIC_ICDIPTR_CPUTRGTLST91_MASK)
#define GIC_ICDIPTR_CPUTRGTLST87_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST87_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST87(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST87_SHIFT))&GIC_ICDIPTR_CPUTRGTLST87_MASK)
#define GIC_ICDIPTR_CPUTRGTLST19_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST19_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST19(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST19_SHIFT))&GIC_ICDIPTR_CPUTRGTLST19_MASK)
#define GIC_ICDIPTR_CPUTRGTLST83_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST83_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST83(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST83_SHIFT))&GIC_ICDIPTR_CPUTRGTLST83_MASK)
#define GIC_ICDIPTR_CPUTRGTLST79_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST79_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST79(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST79_SHIFT))&GIC_ICDIPTR_CPUTRGTLST79_MASK)
#define GIC_ICDIPTR_CPUTRGTLST75_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST75_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST75(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST75_SHIFT))&GIC_ICDIPTR_CPUTRGTLST75_MASK)
#define GIC_ICDIPTR_CPUTRGTLST23_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST23_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST23(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST23_SHIFT))&GIC_ICDIPTR_CPUTRGTLST23_MASK)
#define GIC_ICDIPTR_CPUTRGTLST71_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST71_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST71(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST71_SHIFT))&GIC_ICDIPTR_CPUTRGTLST71_MASK)
#define GIC_ICDIPTR_CPUTRGTLST67_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST67_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST67(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST67_SHIFT))&GIC_ICDIPTR_CPUTRGTLST67_MASK)
#define GIC_ICDIPTR_CPUTRGTLST63_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST63_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST63(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST63_SHIFT))&GIC_ICDIPTR_CPUTRGTLST63_MASK)
#define GIC_ICDIPTR_CPUTRGTLST27_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST27_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST27(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST27_SHIFT))&GIC_ICDIPTR_CPUTRGTLST27_MASK)
#define GIC_ICDIPTR_CPUTRGTLST59_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST59_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST59(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST59_SHIFT))&GIC_ICDIPTR_CPUTRGTLST59_MASK)
#define GIC_ICDIPTR_CPUTRGTLST55_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST55_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST55(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST55_SHIFT))&GIC_ICDIPTR_CPUTRGTLST55_MASK)
#define GIC_ICDIPTR_CPUTRGTLST51_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST51_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST51(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST51_SHIFT))&GIC_ICDIPTR_CPUTRGTLST51_MASK)
#define GIC_ICDIPTR_CPUTRGTLST31_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST31_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST31(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST31_SHIFT))&GIC_ICDIPTR_CPUTRGTLST31_MASK)
#define GIC_ICDIPTR_CPUTRGTLST47_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST47_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST47(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST47_SHIFT))&GIC_ICDIPTR_CPUTRGTLST47_MASK)
#define GIC_ICDIPTR_CPUTRGTLST43_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST43_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST43(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST43_SHIFT))&GIC_ICDIPTR_CPUTRGTLST43_MASK)
#define GIC_ICDIPTR_CPUTRGTLST39_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST39_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST39(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST39_SHIFT))&GIC_ICDIPTR_CPUTRGTLST39_MASK)
#define GIC_ICDIPTR_CPUTRGTLST35_MASK            0xFF000000u
#define GIC_ICDIPTR_CPUTRGTLST35_SHIFT           24
#define GIC_ICDIPTR_CPUTRGTLST35(x)              (((uint32_t)(((uint32_t)(x))<<GIC_ICDIPTR_CPUTRGTLST35_SHIFT))&GIC_ICDIPTR_CPUTRGTLST35_MASK)
/* ICDICFR Bit Fields */
#define GIC_ICDICFR_CONFIG128_MASK               0x3u
#define GIC_ICDICFR_CONFIG128_SHIFT              0
#define GIC_ICDICFR_CONFIG128(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG128_SHIFT))&GIC_ICDICFR_CONFIG128_MASK)
#define GIC_ICDICFR_CONFIG16_MASK                0x3u
#define GIC_ICDICFR_CONFIG16_SHIFT               0
#define GIC_ICDICFR_CONFIG16(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG16_SHIFT))&GIC_ICDICFR_CONFIG16_MASK)
#define GIC_ICDICFR_CONFIG80_MASK                0x3u
#define GIC_ICDICFR_CONFIG80_SHIFT               0
#define GIC_ICDICFR_CONFIG80(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG80_SHIFT))&GIC_ICDICFR_CONFIG80_MASK)
#define GIC_ICDICFR_CONFIG0_MASK                 0x3u
#define GIC_ICDICFR_CONFIG0_SHIFT                0
#define GIC_ICDICFR_CONFIG0(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG0_SHIFT))&GIC_ICDICFR_CONFIG0_MASK)
#define GIC_ICDICFR_CONFIG32_MASK                0x3u
#define GIC_ICDICFR_CONFIG32_SHIFT               0
#define GIC_ICDICFR_CONFIG32(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG32_SHIFT))&GIC_ICDICFR_CONFIG32_MASK)
#define GIC_ICDICFR_CONFIG96_MASK                0x3u
#define GIC_ICDICFR_CONFIG96_SHIFT               0
#define GIC_ICDICFR_CONFIG96(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG96_SHIFT))&GIC_ICDICFR_CONFIG96_MASK)
#define GIC_ICDICFR_CONFIG64_MASK                0x3u
#define GIC_ICDICFR_CONFIG64_SHIFT               0
#define GIC_ICDICFR_CONFIG64(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG64_SHIFT))&GIC_ICDICFR_CONFIG64_MASK)
#define GIC_ICDICFR_CONFIG48_MASK                0x3u
#define GIC_ICDICFR_CONFIG48_SHIFT               0
#define GIC_ICDICFR_CONFIG48(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG48_SHIFT))&GIC_ICDICFR_CONFIG48_MASK)
#define GIC_ICDICFR_CONFIG112_MASK               0x3u
#define GIC_ICDICFR_CONFIG112_SHIFT              0
#define GIC_ICDICFR_CONFIG112(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG112_SHIFT))&GIC_ICDICFR_CONFIG112_MASK)
#define GIC_ICDICFR_CONFIG113_MASK               0xCu
#define GIC_ICDICFR_CONFIG113_SHIFT              2
#define GIC_ICDICFR_CONFIG113(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG113_SHIFT))&GIC_ICDICFR_CONFIG113_MASK)
#define GIC_ICDICFR_CONFIG65_MASK                0xCu
#define GIC_ICDICFR_CONFIG65_SHIFT               2
#define GIC_ICDICFR_CONFIG65(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG65_SHIFT))&GIC_ICDICFR_CONFIG65_MASK)
#define GIC_ICDICFR_CONFIG81_MASK                0xCu
#define GIC_ICDICFR_CONFIG81_SHIFT               2
#define GIC_ICDICFR_CONFIG81(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG81_SHIFT))&GIC_ICDICFR_CONFIG81_MASK)
#define GIC_ICDICFR_CONFIG1_MASK                 0xCu
#define GIC_ICDICFR_CONFIG1_SHIFT                2
#define GIC_ICDICFR_CONFIG1(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG1_SHIFT))&GIC_ICDICFR_CONFIG1_MASK)
#define GIC_ICDICFR_CONFIG97_MASK                0xCu
#define GIC_ICDICFR_CONFIG97_SHIFT               2
#define GIC_ICDICFR_CONFIG97(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG97_SHIFT))&GIC_ICDICFR_CONFIG97_MASK)
#define GIC_ICDICFR_CONFIG33_MASK                0xCu
#define GIC_ICDICFR_CONFIG33_SHIFT               2
#define GIC_ICDICFR_CONFIG33(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG33_SHIFT))&GIC_ICDICFR_CONFIG33_MASK)
#define GIC_ICDICFR_CONFIG49_MASK                0xCu
#define GIC_ICDICFR_CONFIG49_SHIFT               2
#define GIC_ICDICFR_CONFIG49(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG49_SHIFT))&GIC_ICDICFR_CONFIG49_MASK)
#define GIC_ICDICFR_CONFIG129_MASK               0xCu
#define GIC_ICDICFR_CONFIG129_SHIFT              2
#define GIC_ICDICFR_CONFIG129(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG129_SHIFT))&GIC_ICDICFR_CONFIG129_MASK)
#define GIC_ICDICFR_CONFIG17_MASK                0xCu
#define GIC_ICDICFR_CONFIG17_SHIFT               2
#define GIC_ICDICFR_CONFIG17(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG17_SHIFT))&GIC_ICDICFR_CONFIG17_MASK)
#define GIC_ICDICFR_CONFIG82_MASK                0x30u
#define GIC_ICDICFR_CONFIG82_SHIFT               4
#define GIC_ICDICFR_CONFIG82(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG82_SHIFT))&GIC_ICDICFR_CONFIG82_MASK)
#define GIC_ICDICFR_CONFIG98_MASK                0x30u
#define GIC_ICDICFR_CONFIG98_SHIFT               4
#define GIC_ICDICFR_CONFIG98(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG98_SHIFT))&GIC_ICDICFR_CONFIG98_MASK)
#define GIC_ICDICFR_CONFIG66_MASK                0x30u
#define GIC_ICDICFR_CONFIG66_SHIFT               4
#define GIC_ICDICFR_CONFIG66(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG66_SHIFT))&GIC_ICDICFR_CONFIG66_MASK)
#define GIC_ICDICFR_CONFIG130_MASK               0x30u
#define GIC_ICDICFR_CONFIG130_SHIFT              4
#define GIC_ICDICFR_CONFIG130(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG130_SHIFT))&GIC_ICDICFR_CONFIG130_MASK)
#define GIC_ICDICFR_CONFIG2_MASK                 0x30u
#define GIC_ICDICFR_CONFIG2_SHIFT                4
#define GIC_ICDICFR_CONFIG2(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG2_SHIFT))&GIC_ICDICFR_CONFIG2_MASK)
#define GIC_ICDICFR_CONFIG50_MASK                0x30u
#define GIC_ICDICFR_CONFIG50_SHIFT               4
#define GIC_ICDICFR_CONFIG50(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG50_SHIFT))&GIC_ICDICFR_CONFIG50_MASK)
#define GIC_ICDICFR_CONFIG34_MASK                0x30u
#define GIC_ICDICFR_CONFIG34_SHIFT               4
#define GIC_ICDICFR_CONFIG34(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG34_SHIFT))&GIC_ICDICFR_CONFIG34_MASK)
#define GIC_ICDICFR_CONFIG114_MASK               0x30u
#define GIC_ICDICFR_CONFIG114_SHIFT              4
#define GIC_ICDICFR_CONFIG114(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG114_SHIFT))&GIC_ICDICFR_CONFIG114_MASK)
#define GIC_ICDICFR_CONFIG18_MASK                0x30u
#define GIC_ICDICFR_CONFIG18_SHIFT               4
#define GIC_ICDICFR_CONFIG18(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG18_SHIFT))&GIC_ICDICFR_CONFIG18_MASK)
#define GIC_ICDICFR_CONFIG3_MASK                 0xC0u
#define GIC_ICDICFR_CONFIG3_SHIFT                6
#define GIC_ICDICFR_CONFIG3(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG3_SHIFT))&GIC_ICDICFR_CONFIG3_MASK)
#define GIC_ICDICFR_CONFIG99_MASK                0xC0u
#define GIC_ICDICFR_CONFIG99_SHIFT               6
#define GIC_ICDICFR_CONFIG99(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG99_SHIFT))&GIC_ICDICFR_CONFIG99_MASK)
#define GIC_ICDICFR_CONFIG67_MASK                0xC0u
#define GIC_ICDICFR_CONFIG67_SHIFT               6
#define GIC_ICDICFR_CONFIG67(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG67_SHIFT))&GIC_ICDICFR_CONFIG67_MASK)
#define GIC_ICDICFR_CONFIG19_MASK                0xC0u
#define GIC_ICDICFR_CONFIG19_SHIFT               6
#define GIC_ICDICFR_CONFIG19(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG19_SHIFT))&GIC_ICDICFR_CONFIG19_MASK)
#define GIC_ICDICFR_CONFIG131_MASK               0xC0u
#define GIC_ICDICFR_CONFIG131_SHIFT              6
#define GIC_ICDICFR_CONFIG131(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG131_SHIFT))&GIC_ICDICFR_CONFIG131_MASK)
#define GIC_ICDICFR_CONFIG83_MASK                0xC0u
#define GIC_ICDICFR_CONFIG83_SHIFT               6
#define GIC_ICDICFR_CONFIG83(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG83_SHIFT))&GIC_ICDICFR_CONFIG83_MASK)
#define GIC_ICDICFR_CONFIG51_MASK                0xC0u
#define GIC_ICDICFR_CONFIG51_SHIFT               6
#define GIC_ICDICFR_CONFIG51(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG51_SHIFT))&GIC_ICDICFR_CONFIG51_MASK)
#define GIC_ICDICFR_CONFIG115_MASK               0xC0u
#define GIC_ICDICFR_CONFIG115_SHIFT              6
#define GIC_ICDICFR_CONFIG115(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG115_SHIFT))&GIC_ICDICFR_CONFIG115_MASK)
#define GIC_ICDICFR_CONFIG35_MASK                0xC0u
#define GIC_ICDICFR_CONFIG35_SHIFT               6
#define GIC_ICDICFR_CONFIG35(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG35_SHIFT))&GIC_ICDICFR_CONFIG35_MASK)
#define GIC_ICDICFR_CONFIG116_MASK               0x300u
#define GIC_ICDICFR_CONFIG116_SHIFT              8
#define GIC_ICDICFR_CONFIG116(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG116_SHIFT))&GIC_ICDICFR_CONFIG116_MASK)
#define GIC_ICDICFR_CONFIG52_MASK                0x300u
#define GIC_ICDICFR_CONFIG52_SHIFT               8
#define GIC_ICDICFR_CONFIG52(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG52_SHIFT))&GIC_ICDICFR_CONFIG52_MASK)
#define GIC_ICDICFR_CONFIG100_MASK               0x300u
#define GIC_ICDICFR_CONFIG100_SHIFT              8
#define GIC_ICDICFR_CONFIG100(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG100_SHIFT))&GIC_ICDICFR_CONFIG100_MASK)
#define GIC_ICDICFR_CONFIG4_MASK                 0x300u
#define GIC_ICDICFR_CONFIG4_SHIFT                8
#define GIC_ICDICFR_CONFIG4(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG4_SHIFT))&GIC_ICDICFR_CONFIG4_MASK)
#define GIC_ICDICFR_CONFIG20_MASK                0x300u
#define GIC_ICDICFR_CONFIG20_SHIFT               8
#define GIC_ICDICFR_CONFIG20(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG20_SHIFT))&GIC_ICDICFR_CONFIG20_MASK)
#define GIC_ICDICFR_CONFIG132_MASK               0x300u
#define GIC_ICDICFR_CONFIG132_SHIFT              8
#define GIC_ICDICFR_CONFIG132(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG132_SHIFT))&GIC_ICDICFR_CONFIG132_MASK)
#define GIC_ICDICFR_CONFIG68_MASK                0x300u
#define GIC_ICDICFR_CONFIG68_SHIFT               8
#define GIC_ICDICFR_CONFIG68(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG68_SHIFT))&GIC_ICDICFR_CONFIG68_MASK)
#define GIC_ICDICFR_CONFIG84_MASK                0x300u
#define GIC_ICDICFR_CONFIG84_SHIFT               8
#define GIC_ICDICFR_CONFIG84(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG84_SHIFT))&GIC_ICDICFR_CONFIG84_MASK)
#define GIC_ICDICFR_CONFIG36_MASK                0x300u
#define GIC_ICDICFR_CONFIG36_SHIFT               8
#define GIC_ICDICFR_CONFIG36(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG36_SHIFT))&GIC_ICDICFR_CONFIG36_MASK)
#define GIC_ICDICFR_CONFIG21_MASK                0xC00u
#define GIC_ICDICFR_CONFIG21_SHIFT               10
#define GIC_ICDICFR_CONFIG21(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG21_SHIFT))&GIC_ICDICFR_CONFIG21_MASK)
#define GIC_ICDICFR_CONFIG53_MASK                0xC00u
#define GIC_ICDICFR_CONFIG53_SHIFT               10
#define GIC_ICDICFR_CONFIG53(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG53_SHIFT))&GIC_ICDICFR_CONFIG53_MASK)
#define GIC_ICDICFR_CONFIG133_MASK               0xC00u
#define GIC_ICDICFR_CONFIG133_SHIFT              10
#define GIC_ICDICFR_CONFIG133(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG133_SHIFT))&GIC_ICDICFR_CONFIG133_MASK)
#define GIC_ICDICFR_CONFIG117_MASK               0xC00u
#define GIC_ICDICFR_CONFIG117_SHIFT              10
#define GIC_ICDICFR_CONFIG117(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG117_SHIFT))&GIC_ICDICFR_CONFIG117_MASK)
#define GIC_ICDICFR_CONFIG37_MASK                0xC00u
#define GIC_ICDICFR_CONFIG37_SHIFT               10
#define GIC_ICDICFR_CONFIG37(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG37_SHIFT))&GIC_ICDICFR_CONFIG37_MASK)
#define GIC_ICDICFR_CONFIG101_MASK               0xC00u
#define GIC_ICDICFR_CONFIG101_SHIFT              10
#define GIC_ICDICFR_CONFIG101(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG101_SHIFT))&GIC_ICDICFR_CONFIG101_MASK)
#define GIC_ICDICFR_CONFIG5_MASK                 0xC00u
#define GIC_ICDICFR_CONFIG5_SHIFT                10
#define GIC_ICDICFR_CONFIG5(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG5_SHIFT))&GIC_ICDICFR_CONFIG5_MASK)
#define GIC_ICDICFR_CONFIG85_MASK                0xC00u
#define GIC_ICDICFR_CONFIG85_SHIFT               10
#define GIC_ICDICFR_CONFIG85(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG85_SHIFT))&GIC_ICDICFR_CONFIG85_MASK)
#define GIC_ICDICFR_CONFIG69_MASK                0xC00u
#define GIC_ICDICFR_CONFIG69_SHIFT               10
#define GIC_ICDICFR_CONFIG69(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG69_SHIFT))&GIC_ICDICFR_CONFIG69_MASK)
#define GIC_ICDICFR_CONFIG22_MASK                0x3000u
#define GIC_ICDICFR_CONFIG22_SHIFT               12
#define GIC_ICDICFR_CONFIG22(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG22_SHIFT))&GIC_ICDICFR_CONFIG22_MASK)
#define GIC_ICDICFR_CONFIG134_MASK               0x3000u
#define GIC_ICDICFR_CONFIG134_SHIFT              12
#define GIC_ICDICFR_CONFIG134(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG134_SHIFT))&GIC_ICDICFR_CONFIG134_MASK)
#define GIC_ICDICFR_CONFIG118_MASK               0x3000u
#define GIC_ICDICFR_CONFIG118_SHIFT              12
#define GIC_ICDICFR_CONFIG118(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG118_SHIFT))&GIC_ICDICFR_CONFIG118_MASK)
#define GIC_ICDICFR_CONFIG86_MASK                0x3000u
#define GIC_ICDICFR_CONFIG86_SHIFT               12
#define GIC_ICDICFR_CONFIG86(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG86_SHIFT))&GIC_ICDICFR_CONFIG86_MASK)
#define GIC_ICDICFR_CONFIG54_MASK                0x3000u
#define GIC_ICDICFR_CONFIG54_SHIFT               12
#define GIC_ICDICFR_CONFIG54(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG54_SHIFT))&GIC_ICDICFR_CONFIG54_MASK)
#define GIC_ICDICFR_CONFIG38_MASK                0x3000u
#define GIC_ICDICFR_CONFIG38_SHIFT               12
#define GIC_ICDICFR_CONFIG38(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG38_SHIFT))&GIC_ICDICFR_CONFIG38_MASK)
#define GIC_ICDICFR_CONFIG102_MASK               0x3000u
#define GIC_ICDICFR_CONFIG102_SHIFT              12
#define GIC_ICDICFR_CONFIG102(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG102_SHIFT))&GIC_ICDICFR_CONFIG102_MASK)
#define GIC_ICDICFR_CONFIG70_MASK                0x3000u
#define GIC_ICDICFR_CONFIG70_SHIFT               12
#define GIC_ICDICFR_CONFIG70(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG70_SHIFT))&GIC_ICDICFR_CONFIG70_MASK)
#define GIC_ICDICFR_CONFIG6_MASK                 0x3000u
#define GIC_ICDICFR_CONFIG6_SHIFT                12
#define GIC_ICDICFR_CONFIG6(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG6_SHIFT))&GIC_ICDICFR_CONFIG6_MASK)
#define GIC_ICDICFR_CONFIG23_MASK                0xC000u
#define GIC_ICDICFR_CONFIG23_SHIFT               14
#define GIC_ICDICFR_CONFIG23(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG23_SHIFT))&GIC_ICDICFR_CONFIG23_MASK)
#define GIC_ICDICFR_CONFIG119_MASK               0xC000u
#define GIC_ICDICFR_CONFIG119_SHIFT              14
#define GIC_ICDICFR_CONFIG119(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG119_SHIFT))&GIC_ICDICFR_CONFIG119_MASK)
#define GIC_ICDICFR_CONFIG135_MASK               0xC000u
#define GIC_ICDICFR_CONFIG135_SHIFT              14
#define GIC_ICDICFR_CONFIG135(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG135_SHIFT))&GIC_ICDICFR_CONFIG135_MASK)
#define GIC_ICDICFR_CONFIG87_MASK                0xC000u
#define GIC_ICDICFR_CONFIG87_SHIFT               14
#define GIC_ICDICFR_CONFIG87(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG87_SHIFT))&GIC_ICDICFR_CONFIG87_MASK)
#define GIC_ICDICFR_CONFIG7_MASK                 0xC000u
#define GIC_ICDICFR_CONFIG7_SHIFT                14
#define GIC_ICDICFR_CONFIG7(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG7_SHIFT))&GIC_ICDICFR_CONFIG7_MASK)
#define GIC_ICDICFR_CONFIG55_MASK                0xC000u
#define GIC_ICDICFR_CONFIG55_SHIFT               14
#define GIC_ICDICFR_CONFIG55(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG55_SHIFT))&GIC_ICDICFR_CONFIG55_MASK)
#define GIC_ICDICFR_CONFIG39_MASK                0xC000u
#define GIC_ICDICFR_CONFIG39_SHIFT               14
#define GIC_ICDICFR_CONFIG39(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG39_SHIFT))&GIC_ICDICFR_CONFIG39_MASK)
#define GIC_ICDICFR_CONFIG103_MASK               0xC000u
#define GIC_ICDICFR_CONFIG103_SHIFT              14
#define GIC_ICDICFR_CONFIG103(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG103_SHIFT))&GIC_ICDICFR_CONFIG103_MASK)
#define GIC_ICDICFR_CONFIG71_MASK                0xC000u
#define GIC_ICDICFR_CONFIG71_SHIFT               14
#define GIC_ICDICFR_CONFIG71(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG71_SHIFT))&GIC_ICDICFR_CONFIG71_MASK)
#define GIC_ICDICFR_CONFIG88_MASK                0x30000u
#define GIC_ICDICFR_CONFIG88_SHIFT               16
#define GIC_ICDICFR_CONFIG88(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG88_SHIFT))&GIC_ICDICFR_CONFIG88_MASK)
#define GIC_ICDICFR_CONFIG56_MASK                0x30000u
#define GIC_ICDICFR_CONFIG56_SHIFT               16
#define GIC_ICDICFR_CONFIG56(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG56_SHIFT))&GIC_ICDICFR_CONFIG56_MASK)
#define GIC_ICDICFR_CONFIG104_MASK               0x30000u
#define GIC_ICDICFR_CONFIG104_SHIFT              16
#define GIC_ICDICFR_CONFIG104(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG104_SHIFT))&GIC_ICDICFR_CONFIG104_MASK)
#define GIC_ICDICFR_CONFIG40_MASK                0x30000u
#define GIC_ICDICFR_CONFIG40_SHIFT               16
#define GIC_ICDICFR_CONFIG40(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG40_SHIFT))&GIC_ICDICFR_CONFIG40_MASK)
#define GIC_ICDICFR_CONFIG120_MASK               0x30000u
#define GIC_ICDICFR_CONFIG120_SHIFT              16
#define GIC_ICDICFR_CONFIG120(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG120_SHIFT))&GIC_ICDICFR_CONFIG120_MASK)
#define GIC_ICDICFR_CONFIG24_MASK                0x30000u
#define GIC_ICDICFR_CONFIG24_SHIFT               16
#define GIC_ICDICFR_CONFIG24(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG24_SHIFT))&GIC_ICDICFR_CONFIG24_MASK)
#define GIC_ICDICFR_CONFIG136_MASK               0x30000u
#define GIC_ICDICFR_CONFIG136_SHIFT              16
#define GIC_ICDICFR_CONFIG136(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG136_SHIFT))&GIC_ICDICFR_CONFIG136_MASK)
#define GIC_ICDICFR_CONFIG8_MASK                 0x30000u
#define GIC_ICDICFR_CONFIG8_SHIFT                16
#define GIC_ICDICFR_CONFIG8(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG8_SHIFT))&GIC_ICDICFR_CONFIG8_MASK)
#define GIC_ICDICFR_CONFIG72_MASK                0x30000u
#define GIC_ICDICFR_CONFIG72_SHIFT               16
#define GIC_ICDICFR_CONFIG72(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG72_SHIFT))&GIC_ICDICFR_CONFIG72_MASK)
#define GIC_ICDICFR_CONFIG89_MASK                0xC0000u
#define GIC_ICDICFR_CONFIG89_SHIFT               18
#define GIC_ICDICFR_CONFIG89(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG89_SHIFT))&GIC_ICDICFR_CONFIG89_MASK)
#define GIC_ICDICFR_CONFIG41_MASK                0xC0000u
#define GIC_ICDICFR_CONFIG41_SHIFT               18
#define GIC_ICDICFR_CONFIG41(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG41_SHIFT))&GIC_ICDICFR_CONFIG41_MASK)
#define GIC_ICDICFR_CONFIG105_MASK               0xC0000u
#define GIC_ICDICFR_CONFIG105_SHIFT              18
#define GIC_ICDICFR_CONFIG105(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG105_SHIFT))&GIC_ICDICFR_CONFIG105_MASK)
#define GIC_ICDICFR_CONFIG25_MASK                0xC0000u
#define GIC_ICDICFR_CONFIG25_SHIFT               18
#define GIC_ICDICFR_CONFIG25(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG25_SHIFT))&GIC_ICDICFR_CONFIG25_MASK)
#define GIC_ICDICFR_CONFIG121_MASK               0xC0000u
#define GIC_ICDICFR_CONFIG121_SHIFT              18
#define GIC_ICDICFR_CONFIG121(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG121_SHIFT))&GIC_ICDICFR_CONFIG121_MASK)
#define GIC_ICDICFR_CONFIG57_MASK                0xC0000u
#define GIC_ICDICFR_CONFIG57_SHIFT               18
#define GIC_ICDICFR_CONFIG57(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG57_SHIFT))&GIC_ICDICFR_CONFIG57_MASK)
#define GIC_ICDICFR_CONFIG73_MASK                0xC0000u
#define GIC_ICDICFR_CONFIG73_SHIFT               18
#define GIC_ICDICFR_CONFIG73(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG73_SHIFT))&GIC_ICDICFR_CONFIG73_MASK)
#define GIC_ICDICFR_CONFIG137_MASK               0xC0000u
#define GIC_ICDICFR_CONFIG137_SHIFT              18
#define GIC_ICDICFR_CONFIG137(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG137_SHIFT))&GIC_ICDICFR_CONFIG137_MASK)
#define GIC_ICDICFR_CONFIG9_MASK                 0xC0000u
#define GIC_ICDICFR_CONFIG9_SHIFT                18
#define GIC_ICDICFR_CONFIG9(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG9_SHIFT))&GIC_ICDICFR_CONFIG9_MASK)
#define GIC_ICDICFR_CONFIG42_MASK                0x300000u
#define GIC_ICDICFR_CONFIG42_SHIFT               20
#define GIC_ICDICFR_CONFIG42(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG42_SHIFT))&GIC_ICDICFR_CONFIG42_MASK)
#define GIC_ICDICFR_CONFIG74_MASK                0x300000u
#define GIC_ICDICFR_CONFIG74_SHIFT               20
#define GIC_ICDICFR_CONFIG74(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG74_SHIFT))&GIC_ICDICFR_CONFIG74_MASK)
#define GIC_ICDICFR_CONFIG122_MASK               0x300000u
#define GIC_ICDICFR_CONFIG122_SHIFT              20
#define GIC_ICDICFR_CONFIG122(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG122_SHIFT))&GIC_ICDICFR_CONFIG122_MASK)
#define GIC_ICDICFR_CONFIG26_MASK                0x300000u
#define GIC_ICDICFR_CONFIG26_SHIFT               20
#define GIC_ICDICFR_CONFIG26(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG26_SHIFT))&GIC_ICDICFR_CONFIG26_MASK)
#define GIC_ICDICFR_CONFIG90_MASK                0x300000u
#define GIC_ICDICFR_CONFIG90_SHIFT               20
#define GIC_ICDICFR_CONFIG90(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG90_SHIFT))&GIC_ICDICFR_CONFIG90_MASK)
#define GIC_ICDICFR_CONFIG138_MASK               0x300000u
#define GIC_ICDICFR_CONFIG138_SHIFT              20
#define GIC_ICDICFR_CONFIG138(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG138_SHIFT))&GIC_ICDICFR_CONFIG138_MASK)
#define GIC_ICDICFR_CONFIG58_MASK                0x300000u
#define GIC_ICDICFR_CONFIG58_SHIFT               20
#define GIC_ICDICFR_CONFIG58(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG58_SHIFT))&GIC_ICDICFR_CONFIG58_MASK)
#define GIC_ICDICFR_CONFIG106_MASK               0x300000u
#define GIC_ICDICFR_CONFIG106_SHIFT              20
#define GIC_ICDICFR_CONFIG106(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG106_SHIFT))&GIC_ICDICFR_CONFIG106_MASK)
#define GIC_ICDICFR_CONFIG10_MASK                0x300000u
#define GIC_ICDICFR_CONFIG10_SHIFT               20
#define GIC_ICDICFR_CONFIG10(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG10_SHIFT))&GIC_ICDICFR_CONFIG10_MASK)
#define GIC_ICDICFR_CONFIG107_MASK               0xC00000u
#define GIC_ICDICFR_CONFIG107_SHIFT              22
#define GIC_ICDICFR_CONFIG107(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG107_SHIFT))&GIC_ICDICFR_CONFIG107_MASK)
#define GIC_ICDICFR_CONFIG75_MASK                0xC00000u
#define GIC_ICDICFR_CONFIG75_SHIFT               22
#define GIC_ICDICFR_CONFIG75(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG75_SHIFT))&GIC_ICDICFR_CONFIG75_MASK)
#define GIC_ICDICFR_CONFIG43_MASK                0xC00000u
#define GIC_ICDICFR_CONFIG43_SHIFT               22
#define GIC_ICDICFR_CONFIG43(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG43_SHIFT))&GIC_ICDICFR_CONFIG43_MASK)
#define GIC_ICDICFR_CONFIG59_MASK                0xC00000u
#define GIC_ICDICFR_CONFIG59_SHIFT               22
#define GIC_ICDICFR_CONFIG59(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG59_SHIFT))&GIC_ICDICFR_CONFIG59_MASK)
#define GIC_ICDICFR_CONFIG27_MASK                0xC00000u
#define GIC_ICDICFR_CONFIG27_SHIFT               22
#define GIC_ICDICFR_CONFIG27(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG27_SHIFT))&GIC_ICDICFR_CONFIG27_MASK)
#define GIC_ICDICFR_CONFIG123_MASK               0xC00000u
#define GIC_ICDICFR_CONFIG123_SHIFT              22
#define GIC_ICDICFR_CONFIG123(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG123_SHIFT))&GIC_ICDICFR_CONFIG123_MASK)
#define GIC_ICDICFR_CONFIG91_MASK                0xC00000u
#define GIC_ICDICFR_CONFIG91_SHIFT               22
#define GIC_ICDICFR_CONFIG91(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG91_SHIFT))&GIC_ICDICFR_CONFIG91_MASK)
#define GIC_ICDICFR_CONFIG139_MASK               0xC00000u
#define GIC_ICDICFR_CONFIG139_SHIFT              22
#define GIC_ICDICFR_CONFIG139(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG139_SHIFT))&GIC_ICDICFR_CONFIG139_MASK)
#define GIC_ICDICFR_CONFIG11_MASK                0xC00000u
#define GIC_ICDICFR_CONFIG11_SHIFT               22
#define GIC_ICDICFR_CONFIG11(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG11_SHIFT))&GIC_ICDICFR_CONFIG11_MASK)
#define GIC_ICDICFR_CONFIG44_MASK                0x3000000u
#define GIC_ICDICFR_CONFIG44_SHIFT               24
#define GIC_ICDICFR_CONFIG44(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG44_SHIFT))&GIC_ICDICFR_CONFIG44_MASK)
#define GIC_ICDICFR_CONFIG124_MASK               0x3000000u
#define GIC_ICDICFR_CONFIG124_SHIFT              24
#define GIC_ICDICFR_CONFIG124(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG124_SHIFT))&GIC_ICDICFR_CONFIG124_MASK)
#define GIC_ICDICFR_CONFIG92_MASK                0x3000000u
#define GIC_ICDICFR_CONFIG92_SHIFT               24
#define GIC_ICDICFR_CONFIG92(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG92_SHIFT))&GIC_ICDICFR_CONFIG92_MASK)
#define GIC_ICDICFR_CONFIG12_MASK                0x3000000u
#define GIC_ICDICFR_CONFIG12_SHIFT               24
#define GIC_ICDICFR_CONFIG12(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG12_SHIFT))&GIC_ICDICFR_CONFIG12_MASK)
#define GIC_ICDICFR_CONFIG108_MASK               0x3000000u
#define GIC_ICDICFR_CONFIG108_SHIFT              24
#define GIC_ICDICFR_CONFIG108(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG108_SHIFT))&GIC_ICDICFR_CONFIG108_MASK)
#define GIC_ICDICFR_CONFIG60_MASK                0x3000000u
#define GIC_ICDICFR_CONFIG60_SHIFT               24
#define GIC_ICDICFR_CONFIG60(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG60_SHIFT))&GIC_ICDICFR_CONFIG60_MASK)
#define GIC_ICDICFR_CONFIG28_MASK                0x3000000u
#define GIC_ICDICFR_CONFIG28_SHIFT               24
#define GIC_ICDICFR_CONFIG28(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG28_SHIFT))&GIC_ICDICFR_CONFIG28_MASK)
#define GIC_ICDICFR_CONFIG76_MASK                0x3000000u
#define GIC_ICDICFR_CONFIG76_SHIFT               24
#define GIC_ICDICFR_CONFIG76(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG76_SHIFT))&GIC_ICDICFR_CONFIG76_MASK)
#define GIC_ICDICFR_CONFIG140_MASK               0x3000000u
#define GIC_ICDICFR_CONFIG140_SHIFT              24
#define GIC_ICDICFR_CONFIG140(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG140_SHIFT))&GIC_ICDICFR_CONFIG140_MASK)
#define GIC_ICDICFR_CONFIG125_MASK               0xC000000u
#define GIC_ICDICFR_CONFIG125_SHIFT              26
#define GIC_ICDICFR_CONFIG125(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG125_SHIFT))&GIC_ICDICFR_CONFIG125_MASK)
#define GIC_ICDICFR_CONFIG93_MASK                0xC000000u
#define GIC_ICDICFR_CONFIG93_SHIFT               26
#define GIC_ICDICFR_CONFIG93(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG93_SHIFT))&GIC_ICDICFR_CONFIG93_MASK)
#define GIC_ICDICFR_CONFIG77_MASK                0xC000000u
#define GIC_ICDICFR_CONFIG77_SHIFT               26
#define GIC_ICDICFR_CONFIG77(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG77_SHIFT))&GIC_ICDICFR_CONFIG77_MASK)
#define GIC_ICDICFR_CONFIG29_MASK                0xC000000u
#define GIC_ICDICFR_CONFIG29_SHIFT               26
#define GIC_ICDICFR_CONFIG29(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG29_SHIFT))&GIC_ICDICFR_CONFIG29_MASK)
#define GIC_ICDICFR_CONFIG141_MASK               0xC000000u
#define GIC_ICDICFR_CONFIG141_SHIFT              26
#define GIC_ICDICFR_CONFIG141(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG141_SHIFT))&GIC_ICDICFR_CONFIG141_MASK)
#define GIC_ICDICFR_CONFIG61_MASK                0xC000000u
#define GIC_ICDICFR_CONFIG61_SHIFT               26
#define GIC_ICDICFR_CONFIG61(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG61_SHIFT))&GIC_ICDICFR_CONFIG61_MASK)
#define GIC_ICDICFR_CONFIG13_MASK                0xC000000u
#define GIC_ICDICFR_CONFIG13_SHIFT               26
#define GIC_ICDICFR_CONFIG13(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG13_SHIFT))&GIC_ICDICFR_CONFIG13_MASK)
#define GIC_ICDICFR_CONFIG109_MASK               0xC000000u
#define GIC_ICDICFR_CONFIG109_SHIFT              26
#define GIC_ICDICFR_CONFIG109(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG109_SHIFT))&GIC_ICDICFR_CONFIG109_MASK)
#define GIC_ICDICFR_CONFIG45_MASK                0xC000000u
#define GIC_ICDICFR_CONFIG45_SHIFT               26
#define GIC_ICDICFR_CONFIG45(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG45_SHIFT))&GIC_ICDICFR_CONFIG45_MASK)
#define GIC_ICDICFR_CONFIG126_MASK               0x30000000u
#define GIC_ICDICFR_CONFIG126_SHIFT              28
#define GIC_ICDICFR_CONFIG126(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG126_SHIFT))&GIC_ICDICFR_CONFIG126_MASK)
#define GIC_ICDICFR_CONFIG30_MASK                0x30000000u
#define GIC_ICDICFR_CONFIG30_SHIFT               28
#define GIC_ICDICFR_CONFIG30(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG30_SHIFT))&GIC_ICDICFR_CONFIG30_MASK)
#define GIC_ICDICFR_CONFIG62_MASK                0x30000000u
#define GIC_ICDICFR_CONFIG62_SHIFT               28
#define GIC_ICDICFR_CONFIG62(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG62_SHIFT))&GIC_ICDICFR_CONFIG62_MASK)
#define GIC_ICDICFR_CONFIG142_MASK               0x30000000u
#define GIC_ICDICFR_CONFIG142_SHIFT              28
#define GIC_ICDICFR_CONFIG142(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG142_SHIFT))&GIC_ICDICFR_CONFIG142_MASK)
#define GIC_ICDICFR_CONFIG78_MASK                0x30000000u
#define GIC_ICDICFR_CONFIG78_SHIFT               28
#define GIC_ICDICFR_CONFIG78(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG78_SHIFT))&GIC_ICDICFR_CONFIG78_MASK)
#define GIC_ICDICFR_CONFIG14_MASK                0x30000000u
#define GIC_ICDICFR_CONFIG14_SHIFT               28
#define GIC_ICDICFR_CONFIG14(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG14_SHIFT))&GIC_ICDICFR_CONFIG14_MASK)
#define GIC_ICDICFR_CONFIG46_MASK                0x30000000u
#define GIC_ICDICFR_CONFIG46_SHIFT               28
#define GIC_ICDICFR_CONFIG46(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG46_SHIFT))&GIC_ICDICFR_CONFIG46_MASK)
#define GIC_ICDICFR_CONFIG110_MASK               0x30000000u
#define GIC_ICDICFR_CONFIG110_SHIFT              28
#define GIC_ICDICFR_CONFIG110(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG110_SHIFT))&GIC_ICDICFR_CONFIG110_MASK)
#define GIC_ICDICFR_CONFIG94_MASK                0x30000000u
#define GIC_ICDICFR_CONFIG94_SHIFT               28
#define GIC_ICDICFR_CONFIG94(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG94_SHIFT))&GIC_ICDICFR_CONFIG94_MASK)
#define GIC_ICDICFR_CONFIG143_MASK               0xC0000000u
#define GIC_ICDICFR_CONFIG143_SHIFT              30
#define GIC_ICDICFR_CONFIG143(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG143_SHIFT))&GIC_ICDICFR_CONFIG143_MASK)
#define GIC_ICDICFR_CONFIG15_MASK                0xC0000000u
#define GIC_ICDICFR_CONFIG15_SHIFT               30
#define GIC_ICDICFR_CONFIG15(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG15_SHIFT))&GIC_ICDICFR_CONFIG15_MASK)
#define GIC_ICDICFR_CONFIG127_MASK               0xC0000000u
#define GIC_ICDICFR_CONFIG127_SHIFT              30
#define GIC_ICDICFR_CONFIG127(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG127_SHIFT))&GIC_ICDICFR_CONFIG127_MASK)
#define GIC_ICDICFR_CONFIG31_MASK                0xC0000000u
#define GIC_ICDICFR_CONFIG31_SHIFT               30
#define GIC_ICDICFR_CONFIG31(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG31_SHIFT))&GIC_ICDICFR_CONFIG31_MASK)
#define GIC_ICDICFR_CONFIG111_MASK               0xC0000000u
#define GIC_ICDICFR_CONFIG111_SHIFT              30
#define GIC_ICDICFR_CONFIG111(x)                 (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG111_SHIFT))&GIC_ICDICFR_CONFIG111_MASK)
#define GIC_ICDICFR_CONFIG47_MASK                0xC0000000u
#define GIC_ICDICFR_CONFIG47_SHIFT               30
#define GIC_ICDICFR_CONFIG47(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG47_SHIFT))&GIC_ICDICFR_CONFIG47_MASK)
#define GIC_ICDICFR_CONFIG95_MASK                0xC0000000u
#define GIC_ICDICFR_CONFIG95_SHIFT               30
#define GIC_ICDICFR_CONFIG95(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG95_SHIFT))&GIC_ICDICFR_CONFIG95_MASK)
#define GIC_ICDICFR_CONFIG63_MASK                0xC0000000u
#define GIC_ICDICFR_CONFIG63_SHIFT               30
#define GIC_ICDICFR_CONFIG63(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG63_SHIFT))&GIC_ICDICFR_CONFIG63_MASK)
#define GIC_ICDICFR_CONFIG79_MASK                0xC0000000u
#define GIC_ICDICFR_CONFIG79_SHIFT               30
#define GIC_ICDICFR_CONFIG79(x)                  (((uint32_t)(((uint32_t)(x))<<GIC_ICDICFR_CONFIG79_SHIFT))&GIC_ICDICFR_CONFIG79_MASK)
/* PPIS Bit Fields */
#define GIC_PPIS_PPISTAT0_MASK                   0x800u
#define GIC_PPIS_PPISTAT0_SHIFT                  11
#define GIC_PPIS_PPISTAT1_MASK                   0x1000u
#define GIC_PPIS_PPISTAT1_SHIFT                  12
#define GIC_PPIS_PPISTAT2_MASK                   0x2000u
#define GIC_PPIS_PPISTAT2_SHIFT                  13
#define GIC_PPIS_PPISTAT3_MASK                   0x4000u
#define GIC_PPIS_PPISTAT3_SHIFT                  14
#define GIC_PPIS_PPISTAT4_MASK                   0x8000u
#define GIC_PPIS_PPISTAT4_SHIFT                  15
/* ICDSPIS Bit Fields */
#define GIC_ICDSPIS_SPISTAT_MASK                 0xFFFFFFFFu
#define GIC_ICDSPIS_SPISTAT_SHIFT                0
#define GIC_ICDSPIS_SPISTAT(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_ICDSPIS_SPISTAT_SHIFT))&GIC_ICDSPIS_SPISTAT_MASK)
/* SGIR Bit Fields */
#define GIC_SGIR_SGIINTID_MASK                   0xFu
#define GIC_SGIR_SGIINTID_SHIFT                  0
#define GIC_SGIR_SGIINTID(x)                     (((uint32_t)(((uint32_t)(x))<<GIC_SGIR_SGIINTID_SHIFT))&GIC_SGIR_SGIINTID_MASK)
#define GIC_SGIR_SATT_MASK                       0x8000u
#define GIC_SGIR_SATT_SHIFT                      15
#define GIC_SGIR_CPUTRGTLST_MASK                 0xFF0000u
#define GIC_SGIR_CPUTRGTLST_SHIFT                16
#define GIC_SGIR_CPUTRGTLST(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_SGIR_CPUTRGTLST_SHIFT))&GIC_SGIR_CPUTRGTLST_MASK)
#define GIC_SGIR_TRGTLSTFLT_MASK                 0x3000000u
#define GIC_SGIR_TRGTLSTFLT_SHIFT                24
#define GIC_SGIR_TRGTLSTFLT(x)                   (((uint32_t)(((uint32_t)(x))<<GIC_SGIR_TRGTLSTFLT_SHIFT))&GIC_SGIR_TRGTLSTFLT_MASK)

/**
 * @}
 */ /* end of group GIC_Register_Masks */


/* GIC - Peripheral instance base addresses */
/** Peripheral GIC base address */
#define GIC_BASE                                 (0x40002000u)
/** Peripheral GIC base pointer */
#define GIC                                      ((GIC_Type *)GIC_BASE)
/** Array initializer of GIC peripheral base pointers */
#define GIC_BASES                                { GIC }

/**
 * @}
 */ /* end of group GIC_Peripheral_Access_Layer */

 
/* ----------------------------------------------------------------------------
   -- GPC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
 * @{
 */

/** GPC - Register Layout Typedef */
typedef struct {
  __IO uint32_t PGCR;                              /**< Power Gating Control Register, offset: 0x0 */
       uint8_t RESERVED_0[8];
  __IO uint32_t PGSR;                              /**< Power Gating Status Register, offset: 0xC */
       uint8_t RESERVED_1[48];
  __IO uint32_t LPMR;                              /**< Low Power Mode Register, offset: 0x40 */
  __IO uint32_t IMR1;                              /**< Interrupt Mask Register 1, offset: 0x44 */
  __IO uint32_t IMR2;                              /**< Interrupt Mask Register 2, offset: 0x48 */
  __IO uint32_t IMR3;                              /**< Interrupt Mask Register 3, offset: 0x4C */
  __IO uint32_t IMR4;                              /**< Interrupt Mask Register, offset: 0x50 */
  __IO uint32_t ISR1;                              /**< Interrupt Status Register 1, offset: 0x54 */
  __IO uint32_t ISR2;                              /**< Interrupt Status Register 2, offset: 0x58 */
  __IO uint32_t ISR3;                              /**< Interrupt Status Register 3, offset: 0x5C */
  __IO uint32_t ISR4;                              /**< Interrupt Status Register 4, offset: 0x60 */
} GPC_Type;

/* ----------------------------------------------------------------------------
   -- GPC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GPC_Register_Masks GPC Register Masks
 * @{
 */

/* PGCR Bit Fields */
#define GPC_PGCR_PG_PD1_MASK                     0x1u
#define GPC_PGCR_PG_PD1_SHIFT                    0
#define GPC_PGCR_PG_16K_MASK                     0x2u
#define GPC_PGCR_PG_16K_SHIFT                    1
#define GPC_PGCR_PG_48K_MASK                     0x4u
#define GPC_PGCR_PG_48K_SHIFT                    2
#define GPC_PGCR_HP_OFF_MASK                     0x8u
#define GPC_PGCR_HP_OFF_SHIFT                    3
#define GPC_PGCR_WB_STOP_MASK                    0x10u
#define GPC_PGCR_WB_STOP_SHIFT                   4
#define GPC_PGCR_DS_LPSTOP_MASK                  0x40u
#define GPC_PGCR_DS_LPSTOP_SHIFT                 6
#define GPC_PGCR_DS_STOP_MASK                    0x80u
#define GPC_PGCR_DS_STOP_SHIFT                   7
/* PGSR Bit Fields */
#define GPC_PGSR_PSR_MASK                        0x1u
#define GPC_PGSR_PSR_SHIFT                       0
#define GPC_PGSR_CUR_LPM_MASK                    0x6u
#define GPC_PGSR_CUR_LPM_SHIFT                   1
#define GPC_PGSR_CUR_LPM(x)                      (((uint32_t)(((uint32_t)(x))<<GPC_PGSR_CUR_LPM_SHIFT))&GPC_PGSR_CUR_LPM_MASK)
#define GPC_PGSR_PREV_LPM_MASK                   0x18u
#define GPC_PGSR_PREV_LPM_SHIFT                  3
#define GPC_PGSR_PREV_LPM(x)                     (((uint32_t)(((uint32_t)(x))<<GPC_PGSR_PREV_LPM_SHIFT))&GPC_PGSR_PREV_LPM_MASK)
/* LPMR Bit Fields */
#define GPC_LPMR_CLPCR_MASK                      0x3u
#define GPC_LPMR_CLPCR_SHIFT                     0
#define GPC_LPMR_CLPCR(x)                        (((uint32_t)(((uint32_t)(x))<<GPC_LPMR_CLPCR_SHIFT))&GPC_LPMR_CLPCR_MASK)
/* IMR1 Bit Fields */
#define GPC_IMR1_WDOGA5_MASK                     0x100000u
#define GPC_IMR1_WDOGA5_SHIFT                    20
#define GPC_IMR1_WDOGM4_MASK                     0x200000u
#define GPC_IMR1_WDOGM4_SHIFT                    21
#define GPC_IMR1_WDOGSNVS_MASK                   0x400000u
#define GPC_IMR1_WDOGSNVS_SHIFT                  22
#define GPC_IMR1_QSPI0_MASK                      0x1000000u
#define GPC_IMR1_QSPI0_SHIFT                     24
#define GPC_IMR1_QSPI1_MASK                      0x2000000u
#define GPC_IMR1_QSPI1_SHIFT                     25
#define GPC_IMR1_DRAMC_MASK                      0x4000000u
#define GPC_IMR1_DRAMC_SHIFT                     26
#define GPC_IMR1_SDHC0_MASK                      0x8000000u
#define GPC_IMR1_SDHC0_SHIFT                     27
#define GPC_IMR1_SDHC1_MASK                      0x10000000u
#define GPC_IMR1_SDHC1_SHIFT                     28
#define GPC_IMR1_DCU0_MASK                       0x40000000u
#define GPC_IMR1_DCU0_SHIFT                      30
#define GPC_IMR1_DCU1_MASK                       0x80000000u
#define GPC_IMR1_DCU1_SHIFT                      31
/* IMR2 Bit Fields */
#define GPC_IMR2_VIU_MASK                        0x1u
#define GPC_IMR2_VIU_SHIFT                       0
#define GPC_IMR2_GPU_MASK                        0x4u
#define GPC_IMR2_GPU_SHIFT                       2
#define GPC_IMR2_RLE_MASK                        0x8u
#define GPC_IMR2_RLE_SHIFT                       3
#define GPC_IMR2_LCD_MASK                        0x10u
#define GPC_IMR2_LCD_SHIFT                       4
#define GPC_IMR2_PIT_MASK                        0x80u
#define GPC_IMR2_PIT_SHIFT                       7
#define GPC_IMR2_LPTMR_MASK                      0x100u
#define GPC_IMR2_LPTMR_SHIFT                     8
#define GPC_IMR2_FTM0_MASK                       0x400u
#define GPC_IMR2_FTM0_SHIFT                      10
#define GPC_IMR2_FTM1_MASK                       0x800u
#define GPC_IMR2_FTM1_SHIFT                      11
#define GPC_IMR2_FTM2_MASK                       0x1000u
#define GPC_IMR2_FTM2_SHIFT                      12
#define GPC_IMR2_FTM3_MASK                       0x2000u
#define GPC_IMR2_FTM3_SHIFT                      13
#define GPC_IMR2_ANADIGB_MASK                    0x40000u
#define GPC_IMR2_ANADIGB_SHIFT                   18
#define GPC_IMR2_ANADIGA_MASK                    0x80000u
#define GPC_IMR2_ANADIGA_SHIFT                   19
#define GPC_IMR2_ADC0_MASK                       0x200000u
#define GPC_IMR2_ADC0_SHIFT                      21
#define GPC_IMR2_ADC1_MASK                       0x400000u
#define GPC_IMR2_ADC1_SHIFT                      22
#define GPC_IMR2_DAC0_MASK                       0x800000u
#define GPC_IMR2_DAC0_SHIFT                      23
#define GPC_IMR2_DAC1_MASK                       0x1000000u
#define GPC_IMR2_DAC1_SHIFT                      24
#define GPC_IMR2_FLEXCAN0_MASK                   0x4000000u
#define GPC_IMR2_FLEXCAN0_SHIFT                  26
#define GPC_IMR2_FLEXCAN1_MASK                   0x8000000u
#define GPC_IMR2_FLEXCAN1_SHIFT                  27
#define GPC_IMR2_MLB_MASK                        0x10000000u
#define GPC_IMR2_MLB_SHIFT                       28
#define GPC_IMR2_UART0_MASK                      0x20000000u
#define GPC_IMR2_UART0_SHIFT                     29
#define GPC_IMR2_UART1_MASK                      0x40000000u
#define GPC_IMR2_UART1_SHIFT                     30
#define GPC_IMR2_UART2_MASK                      0x80000000u
#define GPC_IMR2_UART2_SHIFT                     31
/* IMR3 Bit Fields */
#define GPC_IMR3_UART3_MASK                      0x1u
#define GPC_IMR3_UART3_SHIFT                     0
#define GPC_IMR3_UART4_MASK                      0x2u
#define GPC_IMR3_UART4_SHIFT                     1
#define GPC_IMR3_UART5_MASK                      0x4u
#define GPC_IMR3_UART5_SHIFT                     2
#define GPC_IMR3_DSPI0_MASK                      0x8u
#define GPC_IMR3_DSPI0_SHIFT                     3
#define GPC_IMR3_DSPI1_MASK                      0x10u
#define GPC_IMR3_DSPI1_SHIFT                     4
#define GPC_IMR3_DSPI2_MASK                      0x20u
#define GPC_IMR3_DSPI2_SHIFT                     5
#define GPC_IMR3_DSPI3_MASK                      0x40u
#define GPC_IMR3_DSPI3_SHIFT                     6
#define GPC_IMR3_I2C0_MASK                       0x80u
#define GPC_IMR3_I2C0_SHIFT                      7
#define GPC_IMR3_I2C1_MASK                       0x100u
#define GPC_IMR3_I2C1_SHIFT                      8
#define GPC_IMR3_I2C2_MASK                       0x200u
#define GPC_IMR3_I2C2_SHIFT                      9
#define GPC_IMR3_I2C3_MASK                       0x400u
#define GPC_IMR3_I2C3_SHIFT                      10
#define GPC_IMR3_USBC0_MASK                      0x800u
#define GPC_IMR3_USBC0_SHIFT                     11
#define GPC_IMR3_USBC1_MASK                      0x1000u
#define GPC_IMR3_USBC1_SHIFT                     12
#define GPC_IMR3_ENET0_MASK                      0x4000u
#define GPC_IMR3_ENET0_SHIFT                     14
#define GPC_IMR3_ENET1_MASK                      0x8000u
#define GPC_IMR3_ENET1_SHIFT                     15
#define GPC_IMR3_1588T0_MASK                     0x10000u
#define GPC_IMR3_1588T0_SHIFT                    16
#define GPC_IMR3_1588T1_MASK                     0x20000u
#define GPC_IMR3_1588T1_SHIFT                    17
#define GPC_IMR3_ESW_MASK                        0x40000u
#define GPC_IMR3_ESW_SHIFT                       18
#define GPC_IMR3_NFC_MASK                        0x80000u
#define GPC_IMR3_NFC_SHIFT                       19
#define GPC_IMR3_UNIMPLEMENTED_MASK              0xF00000u
#define GPC_IMR3_UNIMPLEMENTED_SHIFT             20
#define GPC_IMR3_UNIMPLEMENTED(x)                (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_UNIMPLEMENTED_SHIFT))&GPC_IMR3_UNIMPLEMENTED_MASK)
#define GPC_IMR3_ESAI_MASK                       0x1000000u
#define GPC_IMR3_ESAI_SHIFT                      24
#define GPC_IMR3_SPDIF_MASK                      0x2000000u
#define GPC_IMR3_SPDIF_SHIFT                     25
#define GPC_IMR3_ASRC_MASK                       0x4000000u
#define GPC_IMR3_ASRC_SHIFT                      26
#define GPC_IMR3_CMU_MASK                        0x8000000u
#define GPC_IMR3_CMU_SHIFT                       27
#define GPC_IMR3_WKPU0_MASK                      0x10000000u
#define GPC_IMR3_WKPU0_SHIFT                     28
#define GPC_IMR3_CCM_A_MASK                      0x40000000u
#define GPC_IMR3_CCM_A_SHIFT                     30
#define GPC_IMR3_CCM_B_MASK                      0x80000000u
#define GPC_IMR3_CCM_B_SHIFT                     31
/* IMR4 Bit Fields */
#define GPC_IMR4_SRC_MASK                        0x1u
#define GPC_IMR4_SRC_SHIFT                       0
#define GPC_IMR4_PDB_MASK                        0x2u
#define GPC_IMR4_PDB_SHIFT                       1
#define GPC_IMR4_EWM_MASK                        0x4u
#define GPC_IMR4_EWM_SHIFT                       2
#define GPC_IMR4_SNVS_A_MASK                     0x10u
#define GPC_IMR4_SNVS_A_SHIFT                    4
#define GPC_IMR4_SNVS_B_MASK                     0x20u
#define GPC_IMR4_SNVS_B_SHIFT                    5
#define GPC_IMR4_CAAM_MASK                       0x40u
#define GPC_IMR4_CAAM_SHIFT                      6
#define GPC_IMR4_GPIO0_MASK                      0x800u
#define GPC_IMR4_GPIO0_SHIFT                     11
#define GPC_IMR4_GPIO1_MASK                      0x1000u
#define GPC_IMR4_GPIO1_SHIFT                     12
#define GPC_IMR4_GPIO2_MASK                      0x2000u
#define GPC_IMR4_GPIO2_SHIFT                     13
#define GPC_IMR4_GPIO3_MASK                      0x4000u
#define GPC_IMR4_GPIO3_SHIFT                     14
#define GPC_IMR4_GPIO4_MASK                      0x8000u
#define GPC_IMR4_GPIO4_SHIFT                     15
/* ISR1 Bit Fields */
#define GPC_ISR1_WDOGA5_MASK                     0x100000u
#define GPC_ISR1_WDOGA5_SHIFT                    20
#define GPC_ISR1_WDOGM4_MASK                     0x200000u
#define GPC_ISR1_WDOGM4_SHIFT                    21
#define GPC_ISR1_WDOGSNVS_MASK                   0x400000u
#define GPC_ISR1_WDOGSNVS_SHIFT                  22
#define GPC_ISR1_QSPI0_MASK                      0x1000000u
#define GPC_ISR1_QSPI0_SHIFT                     24
#define GPC_ISR1_QSPI1_MASK                      0x2000000u
#define GPC_ISR1_QSPI1_SHIFT                     25
#define GPC_ISR1_DRAMC_MASK                      0x4000000u
#define GPC_ISR1_DRAMC_SHIFT                     26
#define GPC_ISR1_SDHC0_MASK                      0x8000000u
#define GPC_ISR1_SDHC0_SHIFT                     27
#define GPC_ISR1_SDHC1_MASK                      0x10000000u
#define GPC_ISR1_SDHC1_SHIFT                     28
#define GPC_ISR1_DCU0_MASK                       0x40000000u
#define GPC_ISR1_DCU0_SHIFT                      30
#define GPC_ISR1_DCU1_MASK                       0x80000000u
#define GPC_ISR1_DCU1_SHIFT                      31
/* ISR2 Bit Fields */
#define GPC_ISR2_VIU_MASK                        0x1u
#define GPC_ISR2_VIU_SHIFT                       0
#define GPC_ISR2_GPU_MASK                        0x4u
#define GPC_ISR2_GPU_SHIFT                       2
#define GPC_ISR2_RLE_MASK                        0x8u
#define GPC_ISR2_RLE_SHIFT                       3
#define GPC_ISR2_LCD_MASK                        0x10u
#define GPC_ISR2_LCD_SHIFT                       4
#define GPC_ISR2_PIT_MASK                        0x80u
#define GPC_ISR2_PIT_SHIFT                       7
#define GPC_ISR2_LPTMR_MASK                      0x100u
#define GPC_ISR2_LPTMR_SHIFT                     8
#define GPC_ISR2_FTM_MASK                        0x3C00u
#define GPC_ISR2_FTM_SHIFT                       10
#define GPC_ISR2_FTM(x)                          (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_FTM_SHIFT))&GPC_ISR2_FTM_MASK)
#define GPC_ISR2_ANADIGB_MASK                    0x40000u
#define GPC_ISR2_ANADIGB_SHIFT                   18
#define GPC_ISR2_ANADIGA_MASK                    0x80000u
#define GPC_ISR2_ANADIGA_SHIFT                   19
#define GPC_ISR2_ADC0_MASK                       0x200000u
#define GPC_ISR2_ADC0_SHIFT                      21
#define GPC_ISR2_ADC1_MASK                       0x400000u
#define GPC_ISR2_ADC1_SHIFT                      22
#define GPC_ISR2_DAC0_MASK                       0x800000u
#define GPC_ISR2_DAC0_SHIFT                      23
#define GPC_ISR2_DAC1_MASK                       0x1000000u
#define GPC_ISR2_DAC1_SHIFT                      24
#define GPC_ISR2_Flex_MASK                       0xC000000u
#define GPC_ISR2_Flex_SHIFT                      26
#define GPC_ISR2_Flex(x)                         (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_Flex_SHIFT))&GPC_ISR2_Flex_MASK)
#define GPC_ISR2_MLB_MASK                        0x10000000u
#define GPC_ISR2_MLB_SHIFT                       28
#define GPC_ISR2_UART0_MASK                      0x20000000u
#define GPC_ISR2_UART0_SHIFT                     29
#define GPC_ISR2_UART1_MASK                      0x40000000u
#define GPC_ISR2_UART1_SHIFT                     30
#define GPC_ISR2_UART2_MASK                      0x80000000u
#define GPC_ISR2_UART2_SHIFT                     31
/* ISR3 Bit Fields */
#define GPC_ISR3_UART3_MASK                      0x1u
#define GPC_ISR3_UART3_SHIFT                     0
#define GPC_ISR3_UART4_MASK                      0x2u
#define GPC_ISR3_UART4_SHIFT                     1
#define GPC_ISR3_UART5_MASK                      0x4u
#define GPC_ISR3_UART5_SHIFT                     2
#define GPC_ISR3_DSPI0_MASK                      0x8u
#define GPC_ISR3_DSPI0_SHIFT                     3
#define GPC_ISR3_DSPI1_MASK                      0x10u
#define GPC_ISR3_DSPI1_SHIFT                     4
#define GPC_ISR3_DSPI2_MASK                      0x20u
#define GPC_ISR3_DSPI2_SHIFT                     5
#define GPC_ISR3_DSPI3_MASK                      0x40u
#define GPC_ISR3_DSPI3_SHIFT                     6
#define GPC_ISR3_I2C0_MASK                       0x80u
#define GPC_ISR3_I2C0_SHIFT                      7
#define GPC_ISR3_I2C1_MASK                       0x100u
#define GPC_ISR3_I2C1_SHIFT                      8
#define GPC_ISR3_I2C2_MASK                       0x200u
#define GPC_ISR3_I2C2_SHIFT                      9
#define GPC_ISR3_I2C3_MASK                       0x400u
#define GPC_ISR3_I2C3_SHIFT                      10
#define GPC_ISR3_USBC0_MASK                      0x800u
#define GPC_ISR3_USBC0_SHIFT                     11
#define GPC_ISR3_USBC1_MASK                      0x1000u
#define GPC_ISR3_USBC1_SHIFT                     12
#define GPC_ISR3_ENET0_MASK                      0x4000u
#define GPC_ISR3_ENET0_SHIFT                     14
#define GPC_ISR3_ENET1_MASK                      0x8000u
#define GPC_ISR3_ENET1_SHIFT                     15
#define GPC_ISR3_1588T0_MASK                     0x10000u
#define GPC_ISR3_1588T0_SHIFT                    16
#define GPC_ISR3_1588T1_MASK                     0x20000u
#define GPC_ISR3_1588T1_SHIFT                    17
#define GPC_ISR3_ESW_MASK                        0x40000u
#define GPC_ISR3_ESW_SHIFT                       18
#define GPC_ISR3_NFC_MASK                        0x80000u
#define GPC_ISR3_NFC_SHIFT                       19
#define GPC_ISR3_UNIMPLEMENTED_MASK              0xF00000u
#define GPC_ISR3_UNIMPLEMENTED_SHIFT             20
#define GPC_ISR3_UNIMPLEMENTED(x)                (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_UNIMPLEMENTED_SHIFT))&GPC_ISR3_UNIMPLEMENTED_MASK)
#define GPC_ISR3_ESAI_MASK                       0x1000000u
#define GPC_ISR3_ESAI_SHIFT                      24
#define GPC_ISR3_SPDIF_MASK                      0x2000000u
#define GPC_ISR3_SPDIF_SHIFT                     25
#define GPC_ISR3_ASRC_MASK                       0x4000000u
#define GPC_ISR3_ASRC_SHIFT                      26
#define GPC_ISR3_CMU_MASK                        0x8000000u
#define GPC_ISR3_CMU_SHIFT                       27
#define GPC_ISR3_WKPU0_MASK                      0x10000000u
#define GPC_ISR3_WKPU0_SHIFT                     28
#define GPC_ISR3_CCM_A_MASK                      0x40000000u
#define GPC_ISR3_CCM_A_SHIFT                     30
#define GPC_ISR3_CCM_B_MASK                      0x80000000u
#define GPC_ISR3_CCM_B_SHIFT                     31
/* ISR4 Bit Fields */
#define GPC_ISR4_SRC_MASK                        0x1u
#define GPC_ISR4_SRC_SHIFT                       0
#define GPC_ISR4_PDB_MASK                        0x2u
#define GPC_ISR4_PDB_SHIFT                       1
#define GPC_ISR4_EWM_MASK                        0x4u
#define GPC_ISR4_EWM_SHIFT                       2
#define GPC_ISR4_SNVS_A_MASK                     0x10u
#define GPC_ISR4_SNVS_A_SHIFT                    4
#define GPC_ISR4_SNVS_B_MASK                     0x20u
#define GPC_ISR4_SNVS_B_SHIFT                    5
#define GPC_ISR4_CAAM_MASK                       0x40u
#define GPC_ISR4_CAAM_SHIFT                      6
#define GPC_ISR4_GPIO0_MASK                      0x800u
#define GPC_ISR4_GPIO0_SHIFT                     11
#define GPC_ISR4_GPIO1_MASK                      0x1000u
#define GPC_ISR4_GPIO1_SHIFT                     12
#define GPC_ISR4_GPIO2_MASK                      0x2000u
#define GPC_ISR4_GPIO2_SHIFT                     13
#define GPC_ISR4_GPIO3_MASK                      0x4000u
#define GPC_ISR4_GPIO3_SHIFT                     14
#define GPC_ISR4_GPIO4_MASK                      0x8000u
#define GPC_ISR4_GPIO4_SHIFT                     15

/**
 * @}
 */ /* end of group GPC_Register_Masks */


/* GPC - Peripheral instance base addresses */
/** Peripheral GPC base address */
#define GPC_BASE                                 (0x4006C000u)
/** Peripheral GPC base pointer */
#define GPC                                      ((GPC_Type *)GPC_BASE)
/** Array initializer of GPC peripheral base pointers */
#define GPC_BASES                                { GPC }

/**
 * @}
 */ /* end of group GPC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 * @{
 */

/** GPIO - Register Layout Typedef */
typedef struct {
  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
} GPIO_Type;

/* ----------------------------------------------------------------------------
   -- GPIO Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GPIO_Register_Masks GPIO Register Masks
 * @{
 */

/* PDOR Bit Fields */
#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
#define GPIO_PDOR_PDO_SHIFT                      0
#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
/* PSOR Bit Fields */
#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
#define GPIO_PSOR_PTSO_SHIFT                     0
#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
/* PCOR Bit Fields */
#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
#define GPIO_PCOR_PTCO_SHIFT                     0
#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
/* PTOR Bit Fields */
#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
#define GPIO_PTOR_PTTO_SHIFT                     0
#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
/* PDIR Bit Fields */
#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
#define GPIO_PDIR_PDI_SHIFT                      0
#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)

/**
 * @}
 */ /* end of group GPIO_Register_Masks */


/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIO0 base address */
#define GPIO0_BASE                               (0x400FF000u)
/** Peripheral GPIO0 base pointer */
#define GPIO0                                    ((GPIO_Type *)GPIO0_BASE)
/** Peripheral GPIO1 base address */
#define GPIO1_BASE                               (0x400FF040u)
/** Peripheral GPIO1 base pointer */
#define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
/** Peripheral GPIO2 base address */
#define GPIO2_BASE                               (0x400FF080u)
/** Peripheral GPIO2 base pointer */
#define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
/** Peripheral GPIO3 base address */
#define GPIO3_BASE                               (0x400FF0C0u)
/** Peripheral GPIO3 base pointer */
#define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
/** Peripheral GPIO4 base address */
#define GPIO4_BASE                               (0x400FF100u)
/** Peripheral GPIO4 base pointer */
#define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASES                               { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 }

/**
 * @}
 */ /* end of group GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPU2D Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GPU2D_Peripheral_Access_Layer GPU2D Peripheral Access Layer
 * @{
 */

/** GPU2D - Register Layout Typedef */
typedef struct {
  __IO uint32_t AQHiClockControl;                  /**< Clock Control Register, offset: 0x0 */
  __I  uint32_t AQHiIdle;                          /**< Idle Status Register, offset: 0x4 */
  __IO uint32_t AQAxiConfig;                       /**< AXI Configuration Register, offset: 0x8 */
  __IO uint32_t AQAxiStatus;                       /**< AXI Status Register, offset: 0xC */
  __I  uint32_t AQIntrAcknowledge;                 /**< Interrupt Acknowledge Register, offset: 0x10 */
  __IO uint32_t AQIntrEnbl;                        /**< Interrupt Enable Register, offset: 0x14 */
  __I  uint32_t AQIdent;                           /**< Identification Register, offset: 0x18 */
  __I  uint32_t Features;                          /**< Features Register, offset: 0x1C */
  __I  uint32_t ChipId;                            /**< Chip Identification Register, offset: 0x20 */
  __I  uint32_t ChipRev;                           /**< Chip Revision Register, offset: 0x24 */
  __I  uint32_t ChipDate;                          /**< Chip Release Date Register, offset: 0x28 */
  __I  uint32_t ChipTime;                          /**< Chip Release Time Register, offset: 0x2C */
  __I  uint32_t ChipCustomer;                      /**< Chip Customer Register, offset: 0x30 */
  __I  uint32_t MinorFeatures0;                    /**< Minor Features Register 0, offset: 0x34 */
  __IO uint32_t CacheControl;                      /**< Cache Control Register, offset: 0x38 */
  __O  uint32_t ResetMemCounters;                  /**< Reset Mem Counters Register, offset: 0x3C */
  __I  uint32_t TotalReads;                        /**< Read Count Register, offset: 0x40 */
  __I  uint32_t TotalWrites;                       /**< Write Count Register, offset: 0x44 */
  __I  uint32_t ChipSpecs;                         /**< Chip Specification Register, offset: 0x48 */
  __I  uint32_t TotalWriteBursts;                  /**< Write Data Count Register, offset: 0x4C */
  __I  uint32_t TotalWriteReqs;                    /**< Write REQ Count Register, offset: 0x50 */
  __I  uint32_t TotalWriteLasts;                   /**< Total WLAST Count Register, offset: 0x54 */
  __I  uint32_t TotalReadBursts;                   /**< Total Read Data Count Register, offset: 0x58 */
  __I  uint32_t TotalReadReqs;                     /**< Total Read REQ Count Register, offset: 0x5C */
  __I  uint32_t TotalReadLasts;                    /**< Total RLAST Count Register, offset: 0x60 */
  __IO uint32_t GpOut0;                            /**< General Purpose Register 0, offset: 0x64 */
  __IO uint32_t GpOut1;                            /**< General Purpose Register 1, offset: 0x68 */
  __IO uint32_t GpOut2;                            /**< General Purpose Register 2, offset: 0x6C */
  __IO uint32_t AxiControl;                        /**< AXI Control Register, offset: 0x70 */
  __I  uint32_t MinorFeatures1;                    /**< Minor Features Register 1, offset: 0x74 */
  __IO uint32_t TotalCycles;                       /**< Total Cycle Counter Register, offset: 0x78 */
  __IO uint32_t TotalIdleCyles;                    /**< Total Idle Cycle Register, offset: 0x7C */
  __IO uint32_t ChipSpecs2;                        /**< Chip Specification Register, offset: 0x80 */
  __IO uint32_t ModulePowerControls;               /**< Power Control Register, offset: 0x84 */
  __IO uint32_t ModulePowerModuleControl;          /**< Power Level Register, offset: 0x88 */
  __I  uint32_t ModulePowerModuleStatus;           /**< Power Status Register, offset: 0x8C */
} GPU2D_Type;

/* ----------------------------------------------------------------------------
   -- GPU2D Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup GPU2D_Register_Masks GPU2D Register Masks
 * @{
 */

/* AQHiClockControl Bit Fields */
#define GPU2D_AQHiClockControl_MULTI_PIPE_USE_SINGLE_AXI_MASK 0xF0u
#define GPU2D_AQHiClockControl_MULTI_PIPE_USE_SINGLE_AXI_SHIFT 4
#define GPU2D_AQHiClockControl_MULTI_PIPE_USE_SINGLE_AXI(x) (((uint32_t)(((uint32_t)(x))<<GPU2D_AQHiClockControl_MULTI_PIPE_USE_SINGLE_AXI_SHIFT))&GPU2D_AQHiClockControl_MULTI_PIPE_USE_SINGLE_AXI_MASK)
#define GPU2D_AQHiClockControl_MULTI_PIPE_REG_SELECT_MASK 0xF00u
#define GPU2D_AQHiClockControl_MULTI_PIPE_REG_SELECT_SHIFT 8
#define GPU2D_AQHiClockControl_MULTI_PIPE_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<GPU2D_AQHiClockControl_MULTI_PIPE_REG_SELECT_SHIFT))&GPU2D_AQHiClockControl_MULTI_PIPE_REG_SELECT_MASK)
#define GPU2D_AQHiClockControl_ISOLATE_GPU_MASK  0x1000u
#define GPU2D_AQHiClockControl_ISOLATE_GPU_SHIFT 12
#define GPU2D_AQHiClockControl_IDLE_VG_MASK      0x2000u
#define GPU2D_AQHiClockControl_IDLE_VG_SHIFT     13
#define GPU2D_AQHiClockControl_IDLE2_D_MASK      0x4000u
#define GPU2D_AQHiClockControl_IDLE2_D_SHIFT     14
#define GPU2D_AQHiClockControl_IDLE3_D_MASK      0x8000u
#define GPU2D_AQHiClockControl_IDLE3_D_SHIFT     15
#define GPU2D_AQHiClockControl_SOFT_RESET_MASK   0x80000u
#define GPU2D_AQHiClockControl_SOFT_RESET_SHIFT  19
#define GPU2D_AQHiClockControl_DISABLE_DEBUG_REGISTERS_MASK 0x100000u
#define GPU2D_AQHiClockControl_DISABLE_DEBUG_REGISTERS_SHIFT 20
#define GPU2D_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_MASK 0x200000u
#define GPU2D_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_SHIFT 21
#define GPU2D_AQHiClockControl_FSCALE_CMD_LOAD_MASK 0x400000u
#define GPU2D_AQHiClockControl_FSCALE_CMD_LOAD_SHIFT 22
#define GPU2D_AQHiClockControl_FSCALE_VAL_MASK   0x3F800000u
#define GPU2D_AQHiClockControl_FSCALE_VAL_SHIFT  23
#define GPU2D_AQHiClockControl_FSCALE_VAL(x)     (((uint32_t)(((uint32_t)(x))<<GPU2D_AQHiClockControl_FSCALE_VAL_SHIFT))&GPU2D_AQHiClockControl_FSCALE_VAL_MASK)
#define GPU2D_AQHiClockControl_CLK2D_DIS_MASK    0x40000000u
#define GPU2D_AQHiClockControl_CLK2D_DIS_SHIFT   30
#define GPU2D_AQHiClockControl_CLK3D_DIS_MASK    0x80000000u
#define GPU2D_AQHiClockControl_CLK3D_DIS_SHIFT   31
/* AQHiIdle Bit Fields */
#define GPU2D_AQHiIdle_AXI_LP_MASK               0x1u
#define GPU2D_AQHiIdle_AXI_LP_SHIFT              0
#define GPU2D_AQHiIdle_IDLE_TS_MASK              0x100000u
#define GPU2D_AQHiIdle_IDLE_TS_SHIFT             20
#define GPU2D_AQHiIdle_IDLE_FP_MASK              0x200000u
#define GPU2D_AQHiIdle_IDLE_FP_SHIFT             21
#define GPU2D_AQHiIdle_IDLE_IM_MASK              0x400000u
#define GPU2D_AQHiIdle_IDLE_IM_SHIFT             22
#define GPU2D_AQHiIdle_IDLE_VG_MASK              0x800000u
#define GPU2D_AQHiIdle_IDLE_VG_SHIFT             23
#define GPU2D_AQHiIdle_IDLE_TX_MASK              0x1000000u
#define GPU2D_AQHiIdle_IDLE_TX_SHIFT             24
#define GPU2D_AQHiIdle_IDLE_RA_MASK              0x2000000u
#define GPU2D_AQHiIdle_IDLE_RA_SHIFT             25
#define GPU2D_AQHiIdle_IDLE_SE_MASK              0x4000000u
#define GPU2D_AQHiIdle_IDLE_SE_SHIFT             26
#define GPU2D_AQHiIdle_IDLE_PA_MASK              0x8000000u
#define GPU2D_AQHiIdle_IDLE_PA_SHIFT             27
#define GPU2D_AQHiIdle_IDLE_SH_MASK              0x10000000u
#define GPU2D_AQHiIdle_IDLE_SH_SHIFT             28
#define GPU2D_AQHiIdle_IDLE_PE_MASK              0x20000000u
#define GPU2D_AQHiIdle_IDLE_PE_SHIFT             29
#define GPU2D_AQHiIdle_IDLE_DE_MASK              0x40000000u
#define GPU2D_AQHiIdle_IDLE_DE_SHIFT             30
#define GPU2D_AQHiIdle_IDLE_FE_MASK              0x80000000u
#define GPU2D_AQHiIdle_IDLE_FE_SHIFT             31
/* AQAxiConfig Bit Fields */
#define GPU2D_AQAxiConfig_ARCACHE_MASK           0xF0000u
#define GPU2D_AQAxiConfig_ARCACHE_SHIFT          16
#define GPU2D_AQAxiConfig_ARCACHE(x)             (((uint32_t)(((uint32_t)(x))<<GPU2D_AQAxiConfig_ARCACHE_SHIFT))&GPU2D_AQAxiConfig_ARCACHE_MASK)
#define GPU2D_AQAxiConfig_AWCACHE_MASK           0xF00000u
#define GPU2D_AQAxiConfig_AWCACHE_SHIFT          20
#define GPU2D_AQAxiConfig_AWCACHE(x)             (((uint32_t)(((uint32_t)(x))<<GPU2D_AQAxiConfig_AWCACHE_SHIFT))&GPU2D_AQAxiConfig_AWCACHE_MASK)
#define GPU2D_AQAxiConfig_ARID_MASK              0xF000000u
#define GPU2D_AQAxiConfig_ARID_SHIFT             24
#define GPU2D_AQAxiConfig_ARID(x)                (((uint32_t)(((uint32_t)(x))<<GPU2D_AQAxiConfig_ARID_SHIFT))&GPU2D_AQAxiConfig_ARID_MASK)
#define GPU2D_AQAxiConfig_AWID_MASK              0xF0000000u
#define GPU2D_AQAxiConfig_AWID_SHIFT             28
#define GPU2D_AQAxiConfig_AWID(x)                (((uint32_t)(((uint32_t)(x))<<GPU2D_AQAxiConfig_AWID_SHIFT))&GPU2D_AQAxiConfig_AWID_MASK)
/* AQAxiStatus Bit Fields */
#define GPU2D_AQAxiStatus_WR_ERR_ID_MASK         0xFu
#define GPU2D_AQAxiStatus_WR_ERR_ID_SHIFT        0
#define GPU2D_AQAxiStatus_WR_ERR_ID(x)           (((uint32_t)(((uint32_t)(x))<<GPU2D_AQAxiStatus_WR_ERR_ID_SHIFT))&GPU2D_AQAxiStatus_WR_ERR_ID_MASK)
#define GPU2D_AQAxiStatus_RD_ERR_ID_MASK         0xF0u
#define GPU2D_AQAxiStatus_RD_ERR_ID_SHIFT        4
#define GPU2D_AQAxiStatus_RD_ERR_ID(x)           (((uint32_t)(((uint32_t)(x))<<GPU2D_AQAxiStatus_RD_ERR_ID_SHIFT))&GPU2D_AQAxiStatus_RD_ERR_ID_MASK)
#define GPU2D_AQAxiStatus_DET_WR_ERR_MASK        0x100u
#define GPU2D_AQAxiStatus_DET_WR_ERR_SHIFT       8
#define GPU2D_AQAxiStatus_DET_RD_ERR_MASK        0x200u
#define GPU2D_AQAxiStatus_DET_RD_ERR_SHIFT       9
/* AQIntrAcknowledge Bit Fields */
#define GPU2D_AQIntrAcknowledge_INTR_VEC_MASK    0xFFFFFFFFu
#define GPU2D_AQIntrAcknowledge_INTR_VEC_SHIFT   0
#define GPU2D_AQIntrAcknowledge_INTR_VEC(x)      (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIntrAcknowledge_INTR_VEC_SHIFT))&GPU2D_AQIntrAcknowledge_INTR_VEC_MASK)
/* AQIntrEnbl Bit Fields */
#define GPU2D_AQIntrEnbl_INTR_ENBL_VEC_MASK      0xFFFFFFFFu
#define GPU2D_AQIntrEnbl_INTR_ENBL_VEC_SHIFT     0
#define GPU2D_AQIntrEnbl_INTR_ENBL_VEC(x)        (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIntrEnbl_INTR_ENBL_VEC_SHIFT))&GPU2D_AQIntrEnbl_INTR_ENBL_VEC_MASK)
/* AQIdent Bit Fields */
#define GPU2D_AQIdent_CUSTOMER_MASK              0xFFu
#define GPU2D_AQIdent_CUSTOMER_SHIFT             0
#define GPU2D_AQIdent_CUSTOMER(x)                (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIdent_CUSTOMER_SHIFT))&GPU2D_AQIdent_CUSTOMER_MASK)
#define GPU2D_AQIdent_TECHNOLOGY_MASK            0xF00u
#define GPU2D_AQIdent_TECHNOLOGY_SHIFT           8
#define GPU2D_AQIdent_TECHNOLOGY(x)              (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIdent_TECHNOLOGY_SHIFT))&GPU2D_AQIdent_TECHNOLOGY_MASK)
#define GPU2D_AQIdent_REVISION_MASK              0xF000u
#define GPU2D_AQIdent_REVISION_SHIFT             12
#define GPU2D_AQIdent_REVISION(x)                (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIdent_REVISION_SHIFT))&GPU2D_AQIdent_REVISION_MASK)
#define GPU2D_AQIdent_PRODUCT_MASK               0xFF0000u
#define GPU2D_AQIdent_PRODUCT_SHIFT              16
#define GPU2D_AQIdent_PRODUCT(x)                 (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIdent_PRODUCT_SHIFT))&GPU2D_AQIdent_PRODUCT_MASK)
#define GPU2D_AQIdent_FAMILY_MASK                0xFF000000u
#define GPU2D_AQIdent_FAMILY_SHIFT               24
#define GPU2D_AQIdent_FAMILY(x)                  (((uint32_t)(((uint32_t)(x))<<GPU2D_AQIdent_FAMILY_SHIFT))&GPU2D_AQIdent_FAMILY_MASK)
/* Features Bit Fields */
#define GPU2D_Features_FE20_BIT_INDEX_MASK       0x1u
#define GPU2D_Features_FE20_BIT_INDEX_SHIFT      0
#define GPU2D_Features_RS_YUV_TARGET_MASK        0x2u
#define GPU2D_Features_RS_YUV_TARGET_SHIFT       1
#define GPU2D_Features_BYTE_WRITE_3D_MASK        0x4u
#define GPU2D_Features_BYTE_WRITE_3D_SHIFT       2
#define GPU2D_Features_FE20_MASK                 0x8u
#define GPU2D_Features_FE20_SHIFT                3
#define GPU2D_Features_VGTS_MASK                 0x10u
#define GPU2D_Features_VGTS_SHIFT                4
#define GPU2D_Features_PIPE_VG_MASK              0x20u
#define GPU2D_Features_PIPE_VG_SHIFT             5
#define GPU2D_Features_MEM32_BIT_SUPPORT_MASK    0x40u
#define GPU2D_Features_MEM32_BIT_SUPPORT_SHIFT   6
#define GPU2D_Features_YUY2_RENDER_TARGET_MASK   0x80u
#define GPU2D_Features_YUY2_RENDER_TARGET_SHIFT  7
#define GPU2D_Features_HALF_TX_CACHE_MASK        0x100u
#define GPU2D_Features_HALF_TX_CACHE_SHIFT       8
#define GPU2D_Features_HALF_PE_CACHE_MASK        0x200u
#define GPU2D_Features_HALF_PE_CACHE_SHIFT       9
#define GPU2D_Features_YUY2_AVERAGING_MASK       0x400u
#define GPU2D_Features_YUY2_AVERAGING_SHIFT      10
#define GPU2D_Features_NO_SCALER_MASK            0x800u
#define GPU2D_Features_NO_SCALER_SHIFT           11
#define GPU2D_Features_BYTE_WRITE_2D_MASK        0x1000u
#define GPU2D_Features_BYTE_WRITE_2D_SHIFT       12
#define GPU2D_Features_BUFFER_INTERLEAVING_MASK  0x2000u
#define GPU2D_Features_BUFFER_INTERLEAVING_SHIFT 13
#define GPU2D_Features_NO422_TEXTURE_MASK        0x4000u
#define GPU2D_Features_NO422_TEXTURE_SHIFT       14
#define GPU2D_Features_NO_EZ_MASK                0x8000u
#define GPU2D_Features_NO_EZ_SHIFT               15
#define GPU2D_Features_MIN_AREA_MASK             0x10000u
#define GPU2D_Features_MIN_AREA_SHIFT            16
#define GPU2D_Features_MODULE_CG_MASK            0x20000u
#define GPU2D_Features_MODULE_CG_SHIFT           17
#define GPU2D_Features_YUV420_TILER_MASK         0x40000u
#define GPU2D_Features_YUV420_TILER_SHIFT        18
#define GPU2D_Features_HIGH_DYNAMIC_RANGE_MASK   0x80000u
#define GPU2D_Features_HIGH_DYNAMIC_RANGE_SHIFT  19
#define GPU2D_Features_FAST_SCALER_MASK          0x100000u
#define GPU2D_Features_FAST_SCALER_SHIFT         20
#define GPU2D_Features_ETC1_TEXTURE_COMPRESSION_MASK 0x200000u
#define GPU2D_Features_ETC1_TEXTURE_COMPRESSION_SHIFT 21
#define GPU2D_Features_PIPE_2D_MASK              0x400000u
#define GPU2D_Features_PIPE_2D_SHIFT             22
#define GPU2D_Features_DC_MASK                   0x800000u
#define GPU2D_Features_DC_SHIFT                  23
#define GPU2D_Features_MSAA_MASK                 0x1000000u
#define GPU2D_Features_MSAA_SHIFT                24
#define GPU2D_Features_YUV420_FILTER_MASK        0x2000000u
#define GPU2D_Features_YUV420_FILTER_SHIFT       25
#define GPU2D_Features_ZCOMPRESSION_MASK         0x4000000u
#define GPU2D_Features_ZCOMPRESSION_SHIFT        26
#define GPU2D_Features_DEBUG_MODE_MASK           0x8000000u
#define GPU2D_Features_DEBUG_MODE_SHIFT          27
#define GPU2D_Features_DXT_TEXTURE_COMPRESSION_MASK 0x10000000u
#define GPU2D_Features_DXT_TEXTURE_COMPRESSION_SHIFT 28
#define GPU2D_Features_PIPE_3D_MASK              0x20000000u
#define GPU2D_Features_PIPE_3D_SHIFT             29
#define GPU2D_Features_SPECIAL_ANTI_ALIASING_MASK 0x40000000u
#define GPU2D_Features_SPECIAL_ANTI_ALIASING_SHIFT 30
#define GPU2D_Features_FAST_CLEAR_MASK           0x80000000u
#define GPU2D_Features_FAST_CLEAR_SHIFT          31
/* ChipId Bit Fields */
#define GPU2D_ChipId_ID_MASK                     0xFFFFFFFFu
#define GPU2D_ChipId_ID_SHIFT                    0
#define GPU2D_ChipId_ID(x)                       (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipId_ID_SHIFT))&GPU2D_ChipId_ID_MASK)
/* ChipRev Bit Fields */
#define GPU2D_ChipRev_REV_MASK                   0xFFFFFFFFu
#define GPU2D_ChipRev_REV_SHIFT                  0
#define GPU2D_ChipRev_REV(x)                     (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipRev_REV_SHIFT))&GPU2D_ChipRev_REV_MASK)
/* ChipDate Bit Fields */
#define GPU2D_ChipDate_DATE_MASK                 0xFFFFFFFFu
#define GPU2D_ChipDate_DATE_SHIFT                0
#define GPU2D_ChipDate_DATE(x)                   (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipDate_DATE_SHIFT))&GPU2D_ChipDate_DATE_MASK)
/* ChipTime Bit Fields */
#define GPU2D_ChipTime_TIME_MASK                 0xFFFFFFFFu
#define GPU2D_ChipTime_TIME_SHIFT                0
#define GPU2D_ChipTime_TIME(x)                   (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipTime_TIME_SHIFT))&GPU2D_ChipTime_TIME_MASK)
/* ChipCustomer Bit Fields */
#define GPU2D_ChipCustomer_GROUP_MASK            0xFFFFu
#define GPU2D_ChipCustomer_GROUP_SHIFT           0
#define GPU2D_ChipCustomer_GROUP(x)              (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipCustomer_GROUP_SHIFT))&GPU2D_ChipCustomer_GROUP_MASK)
#define GPU2D_ChipCustomer_COMPANY_MASK          0xFFFF0000u
#define GPU2D_ChipCustomer_COMPANY_SHIFT         16
#define GPU2D_ChipCustomer_COMPANY(x)            (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipCustomer_COMPANY_SHIFT))&GPU2D_ChipCustomer_COMPANY_MASK)
/* MinorFeatures0 Bit Fields */
#define GPU2D_MinorFeatures0_FLIP_Y_MASK         0x1u
#define GPU2D_MinorFeatures0_FLIP_Y_SHIFT        0
#define GPU2D_MinorFeatures0_DUAL_RETURN_BUS_MASK 0x2u
#define GPU2D_MinorFeatures0_DUAL_RETURN_BUS_SHIFT 1
#define GPU2D_MinorFeatures0_ENDIANNESS_CONFIG_MASK 0x4u
#define GPU2D_MinorFeatures0_ENDIANNESS_CONFIG_SHIFT 2
#define GPU2D_MinorFeatures0_TEXTURE8_K_MASK     0x8u
#define GPU2D_MinorFeatures0_TEXTURE8_K_SHIFT    3
#define GPU2D_MinorFeatures0_CORRECT_TEXTURE_CONVERTER_MASK 0x10u
#define GPU2D_MinorFeatures0_CORRECT_TEXTURE_CONVERTER_SHIFT 4
#define GPU2D_MinorFeatures0_SPECIAL_MSAA_LOD_MASK 0x20u
#define GPU2D_MinorFeatures0_SPECIAL_MSAA_LOD_SHIFT 5
#define GPU2D_MinorFeatures0_FAST_CLEAR_FLUSH_MASK 0x40u
#define GPU2D_MinorFeatures0_FAST_CLEAR_FLUSH_SHIFT 6
#define GPU2D_MinorFeatures0_2DPE20_MASK         0x80u
#define GPU2D_MinorFeatures0_2DPE20_SHIFT        7
#define GPU2D_MinorFeatures0_CORRECT_AUTO_DISABLE_MASK 0x100u
#define GPU2D_MinorFeatures0_CORRECT_AUTO_DISABLE_SHIFT 8
#define GPU2D_MinorFeatures0_RENDER_8K_MASK      0x200u
#define GPU2D_MinorFeatures0_RENDER_8K_SHIFT     9
#define GPU2D_MinorFeatures0_TILE_STATUS_2BITS_MASK 0x400u
#define GPU2D_MinorFeatures0_TILE_STATUS_2BITS_SHIFT 10
#define GPU2D_MinorFeatures0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_MASK 0x800u
#define GPU2D_MinorFeatures0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED_SHIFT 11
#define GPU2D_MinorFeatures0_SUPER_TILED_32X32_MASK 0x1000u
#define GPU2D_MinorFeatures0_SUPER_TILED_32X32_SHIFT 12
#define GPU2D_MinorFeatures0_VG_20_MASK          0x2000u
#define GPU2D_MinorFeatures0_VG_20_SHIFT         13
#define GPU2D_MinorFeatures0_TS_EXTENDED_COMMANDS_MASK 0x4000u
#define GPU2D_MinorFeatures0_TS_EXTENDED_COMMANDS_SHIFT 14
#define GPU2D_MinorFeatures0_COMPRESSION_FIFO_FIXED_MASK 0x8000u
#define GPU2D_MinorFeatures0_COMPRESSION_FIFO_FIXED_SHIFT 15
#define GPU2D_MinorFeatures0_EXTRA_SHADER_INSTRUCTIONS0_MASK 0x10000u
#define GPU2D_MinorFeatures0_EXTRA_SHADER_INSTRUCTIONS0_SHIFT 16
#define GPU2D_MinorFeatures0_VG_FILTER_MASK      0x20000u
#define GPU2D_MinorFeatures0_VG_FILTER_SHIFT     17
#define GPU2D_MinorFeatures0_VG_21_MASK          0x40000u
#define GPU2D_MinorFeatures0_VG_21_SHIFT         18
#define GPU2D_MinorFeatures0_SHADER_GETS_W_MASK  0x80000u
#define GPU2D_MinorFeatures0_SHADER_GETS_W_SHIFT 19
#define GPU2D_MinorFeatures0_EXTRA_SHADER_INSTRUCTIONS1_MASK 0x100000u
#define GPU2D_MinorFeatures0_EXTRA_SHADER_INSTRUCTIONS1_SHIFT 20
#define GPU2D_MinorFeatures0_DEFAULT_REG0_MASK   0x200000u
#define GPU2D_MinorFeatures0_DEFAULT_REG0_SHIFT  21
#define GPU2D_MinorFeatures0_MC_20_MASK          0x400000u
#define GPU2D_MinorFeatures0_MC_20_SHIFT         22
#define GPU2D_MinorFeatures0_SHADER_MSAA_SIDEBAND_MASK 0x800000u
#define GPU2D_MinorFeatures0_SHADER_MSAA_SIDEBAND_SHIFT 23
#define GPU2D_MinorFeatures0_BUG_FIXES0_MASK     0x1000000u
#define GPU2D_MinorFeatures0_BUG_FIXES0_SHIFT    24
#define GPU2D_MinorFeatures0_VAA_MASK            0x2000000u
#define GPU2D_MinorFeatures0_VAA_SHIFT           25
#define GPU2D_MinorFeatures0_BYPASS_IN_MSAA_MASK 0x4000000u
#define GPU2D_MinorFeatures0_BYPASS_IN_MSAA_SHIFT 26
#define GPU2D_MinorFeatures0_HIERARCHICAL_Z_MASK 0x8000000u
#define GPU2D_MinorFeatures0_HIERARCHICAL_Z_SHIFT 27
#define GPU2D_MinorFeatures0_NEW_TEXTURE_MASK    0x10000000u
#define GPU2D_MinorFeatures0_NEW_TEXTURE_SHIFT   28
#define GPU2D_MinorFeatures0_A8_TARGET_SUPPORT_MASK 0x20000000u
#define GPU2D_MinorFeatures0_A8_TARGET_SUPPORT_SHIFT 29
#define GPU2D_MinorFeatures0_CORRECT_STENCIL_MASK 0x40000000u
#define GPU2D_MinorFeatures0_CORRECT_STENCIL_SHIFT 30
#define GPU2D_MinorFeatures0_ENHANCE_VR_MASK     0x80000000u
#define GPU2D_MinorFeatures0_ENHANCE_VR_SHIFT    31
/* CacheControl Bit Fields */
#define GPU2D_CacheControl_NOT_USED_MASK         0xFFFFFFFFu
#define GPU2D_CacheControl_NOT_USED_SHIFT        0
#define GPU2D_CacheControl_NOT_USED(x)           (((uint32_t)(((uint32_t)(x))<<GPU2D_CacheControl_NOT_USED_SHIFT))&GPU2D_CacheControl_NOT_USED_MASK)
/* ResetMemCounters Bit Fields */
#define GPU2D_ResetMemCounters_RESET_MASK        0xFFFFFFFFu
#define GPU2D_ResetMemCounters_RESET_SHIFT       0
#define GPU2D_ResetMemCounters_RESET(x)          (((uint32_t)(((uint32_t)(x))<<GPU2D_ResetMemCounters_RESET_SHIFT))&GPU2D_ResetMemCounters_RESET_MASK)
/* TotalReads Bit Fields */
#define GPU2D_TotalReads_COUNT_MASK              0xFFFFFFFFu
#define GPU2D_TotalReads_COUNT_SHIFT             0
#define GPU2D_TotalReads_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalReads_COUNT_SHIFT))&GPU2D_TotalReads_COUNT_MASK)
/* TotalWrites Bit Fields */
#define GPU2D_TotalWrites_COUNT_MASK             0xFFFFFFFFu
#define GPU2D_TotalWrites_COUNT_SHIFT            0
#define GPU2D_TotalWrites_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalWrites_COUNT_SHIFT))&GPU2D_TotalWrites_COUNT_MASK)
/* ChipSpecs Bit Fields */
#define GPU2D_ChipSpecs_VERTEX_OUTPUT_BUFFER_SIZE_MASK 0xFu
#define GPU2D_ChipSpecs_VERTEX_OUTPUT_BUFFER_SIZE_SHIFT 0
#define GPU2D_ChipSpecs_VERTEX_OUTPUT_BUFFER_SIZE(x) (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_VERTEX_OUTPUT_BUFFER_SIZE_SHIFT))&GPU2D_ChipSpecs_VERTEX_OUTPUT_BUFFER_SIZE_MASK)
#define GPU2D_ChipSpecs_NUM_PIXEL_PIPES_MASK     0x70u
#define GPU2D_ChipSpecs_NUM_PIXEL_PIPES_SHIFT    4
#define GPU2D_ChipSpecs_NUM_PIXEL_PIPES(x)       (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_NUM_PIXEL_PIPES_SHIFT))&GPU2D_ChipSpecs_NUM_PIXEL_PIPES_MASK)
#define GPU2D_ChipSpecs_NUM_SHADER_CORES_MASK    0xF80u
#define GPU2D_ChipSpecs_NUM_SHADER_CORES_SHIFT   7
#define GPU2D_ChipSpecs_NUM_SHADER_CORES(x)      (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_NUM_SHADER_CORES_SHIFT))&GPU2D_ChipSpecs_NUM_SHADER_CORES_MASK)
#define GPU2D_ChipSpecs_VERTEX_CACHE_SIZE_MASK   0xF8000u
#define GPU2D_ChipSpecs_VERTEX_CACHE_SIZE_SHIFT  15
#define GPU2D_ChipSpecs_VERTEX_CACHE_SIZE(x)     (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_VERTEX_CACHE_SIZE_SHIFT))&GPU2D_ChipSpecs_VERTEX_CACHE_SIZE_MASK)
#define GPU2D_ChipSpecs_THREAD_COUNT_MASK        0xF00000u
#define GPU2D_ChipSpecs_THREAD_COUNT_SHIFT       20
#define GPU2D_ChipSpecs_THREAD_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_THREAD_COUNT_SHIFT))&GPU2D_ChipSpecs_THREAD_COUNT_MASK)
#define GPU2D_ChipSpecs_TEMP_REGISTERS_MASK      0xF000000u
#define GPU2D_ChipSpecs_TEMP_REGISTERS_SHIFT     24
#define GPU2D_ChipSpecs_TEMP_REGISTERS(x)        (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_TEMP_REGISTERS_SHIFT))&GPU2D_ChipSpecs_TEMP_REGISTERS_MASK)
#define GPU2D_ChipSpecs_STREAMS_MASK             0xF0000000u
#define GPU2D_ChipSpecs_STREAMS_SHIFT            28
#define GPU2D_ChipSpecs_STREAMS(x)               (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs_STREAMS_SHIFT))&GPU2D_ChipSpecs_STREAMS_MASK)
/* TotalWriteBursts Bit Fields */
#define GPU2D_TotalWriteBursts_COUNT_MASK        0xFFFFFFFFu
#define GPU2D_TotalWriteBursts_COUNT_SHIFT       0
#define GPU2D_TotalWriteBursts_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalWriteBursts_COUNT_SHIFT))&GPU2D_TotalWriteBursts_COUNT_MASK)
/* TotalWriteReqs Bit Fields */
#define GPU2D_TotalWriteReqs_COUNT_MASK          0xFFFFFFFFu
#define GPU2D_TotalWriteReqs_COUNT_SHIFT         0
#define GPU2D_TotalWriteReqs_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalWriteReqs_COUNT_SHIFT))&GPU2D_TotalWriteReqs_COUNT_MASK)
/* TotalWriteLasts Bit Fields */
#define GPU2D_TotalWriteLasts_COUNT_MASK         0xFFFFFFFFu
#define GPU2D_TotalWriteLasts_COUNT_SHIFT        0
#define GPU2D_TotalWriteLasts_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalWriteLasts_COUNT_SHIFT))&GPU2D_TotalWriteLasts_COUNT_MASK)
/* TotalReadBursts Bit Fields */
#define GPU2D_TotalReadBursts_COUNT_MASK         0xFFFFFFFFu
#define GPU2D_TotalReadBursts_COUNT_SHIFT        0
#define GPU2D_TotalReadBursts_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalReadBursts_COUNT_SHIFT))&GPU2D_TotalReadBursts_COUNT_MASK)
/* TotalReadReqs Bit Fields */
#define GPU2D_TotalReadReqs_COUNT_MASK           0xFFFFFFFFu
#define GPU2D_TotalReadReqs_COUNT_SHIFT          0
#define GPU2D_TotalReadReqs_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalReadReqs_COUNT_SHIFT))&GPU2D_TotalReadReqs_COUNT_MASK)
/* TotalReadLasts Bit Fields */
#define GPU2D_TotalReadLasts_COUNT_MASK          0xFFFFFFFFu
#define GPU2D_TotalReadLasts_COUNT_SHIFT         0
#define GPU2D_TotalReadLasts_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalReadLasts_COUNT_SHIFT))&GPU2D_TotalReadLasts_COUNT_MASK)
/* GpOut0 Bit Fields */
#define GPU2D_GpOut0_COUNT_MASK                  0xFFFFFFFFu
#define GPU2D_GpOut0_COUNT_SHIFT                 0
#define GPU2D_GpOut0_COUNT(x)                    (((uint32_t)(((uint32_t)(x))<<GPU2D_GpOut0_COUNT_SHIFT))&GPU2D_GpOut0_COUNT_MASK)
/* GpOut1 Bit Fields */
#define GPU2D_GpOut1_COUNT_MASK                  0xFFFFFFFFu
#define GPU2D_GpOut1_COUNT_SHIFT                 0
#define GPU2D_GpOut1_COUNT(x)                    (((uint32_t)(((uint32_t)(x))<<GPU2D_GpOut1_COUNT_SHIFT))&GPU2D_GpOut1_COUNT_MASK)
/* GpOut2 Bit Fields */
#define GPU2D_GpOut2_COUNT_MASK                  0xFFFFFFFFu
#define GPU2D_GpOut2_COUNT_SHIFT                 0
#define GPU2D_GpOut2_COUNT(x)                    (((uint32_t)(((uint32_t)(x))<<GPU2D_GpOut2_COUNT_SHIFT))&GPU2D_GpOut2_COUNT_MASK)
/* AxiControl Bit Fields */
#define GPU2D_AxiControl_WR_FULL_BURST_MODE_MASK 0xFFFFFFFFu
#define GPU2D_AxiControl_WR_FULL_BURST_MODE_SHIFT 0
#define GPU2D_AxiControl_WR_FULL_BURST_MODE(x)   (((uint32_t)(((uint32_t)(x))<<GPU2D_AxiControl_WR_FULL_BURST_MODE_SHIFT))&GPU2D_AxiControl_WR_FULL_BURST_MODE_MASK)
/* MinorFeatures1 Bit Fields */
#define GPU2D_MinorFeatures1_TEXTURE_STRIDE_MASK 0x4000000u
#define GPU2D_MinorFeatures1_TEXTURE_STRIDE_SHIFT 26
#define GPU2D_MinorFeatures1_BUG_FIXES2_MASK     0x8000000u
#define GPU2D_MinorFeatures1_BUG_FIXES2_SHIFT    27
#define GPU2D_MinorFeatures1_BUG_FIXES1_MASK     0x10000000u
#define GPU2D_MinorFeatures1_BUG_FIXES1_SHIFT    28
#define GPU2D_MinorFeatures1_VG_DOUBLE_BUFFER_MASK 0x20000000u
#define GPU2D_MinorFeatures1_VG_DOUBLE_BUFFER_SHIFT 29
#define GPU2D_MinorFeatures1_V2_COMPRESSION_MASK 0x40000000u
#define GPU2D_MinorFeatures1_V2_COMPRESSION_SHIFT 30
#define GPU2D_MinorFeatures1_RSUV_SWIZZLE_MASK   0x80000000u
#define GPU2D_MinorFeatures1_RSUV_SWIZZLE_SHIFT  31
/* TotalCycles Bit Fields */
#define GPU2D_TotalCycles_CYCLES_MASK            0xFFFFFFFFu
#define GPU2D_TotalCycles_CYCLES_SHIFT           0
#define GPU2D_TotalCycles_CYCLES(x)              (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalCycles_CYCLES_SHIFT))&GPU2D_TotalCycles_CYCLES_MASK)
/* TotalIdleCyles Bit Fields */
#define GPU2D_TotalIdleCyles_CYCLES_MASK         0xFFFFFFFFu
#define GPU2D_TotalIdleCyles_CYCLES_SHIFT        0
#define GPU2D_TotalIdleCyles_CYCLES(x)           (((uint32_t)(((uint32_t)(x))<<GPU2D_TotalIdleCyles_CYCLES_SHIFT))&GPU2D_TotalIdleCyles_CYCLES_MASK)
/* ChipSpecs2 Bit Fields */
#define GPU2D_ChipSpecs2_CYCLES_MASK             0xFFFFFFFFu
#define GPU2D_ChipSpecs2_CYCLES_SHIFT            0
#define GPU2D_ChipSpecs2_CYCLES(x)               (((uint32_t)(((uint32_t)(x))<<GPU2D_ChipSpecs2_CYCLES_SHIFT))&GPU2D_ChipSpecs2_CYCLES_MASK)
/* ModulePowerControls Bit Fields */
#define GPU2D_ModulePowerControls_TURN_OFF_COUNTER_MASK 0xFFFFu
#define GPU2D_ModulePowerControls_TURN_OFF_COUNTER_SHIFT 0
#define GPU2D_ModulePowerControls_TURN_OFF_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<GPU2D_ModulePowerControls_TURN_OFF_COUNTER_SHIFT))&GPU2D_ModulePowerControls_TURN_OFF_COUNTER_MASK)
#define GPU2D_ModulePowerControls_TURN_ON_COUNTER_MASK 0xF000000u
#define GPU2D_ModulePowerControls_TURN_ON_COUNTER_SHIFT 24
#define GPU2D_ModulePowerControls_TURN_ON_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<GPU2D_ModulePowerControls_TURN_ON_COUNTER_SHIFT))&GPU2D_ModulePowerControls_TURN_ON_COUNTER_MASK)
#define GPU2D_ModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK 0x20000000u
#define GPU2D_ModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT 29
#define GPU2D_ModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_MASK 0x40000000u
#define GPU2D_ModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT 30
#define GPU2D_ModulePowerControls_ENABLE_MODULE_CLOCK_GATING_MASK 0x80000000u
#define GPU2D_ModulePowerControls_ENABLE_MODULE_CLOCK_GATING_SHIFT 31
/* ModulePowerModuleControl Bit Fields */
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_TS_MASK 0x100000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT 20
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_FP_MASK 0x200000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_FP_SHIFT 21
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_IM_MASK 0x400000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT 22
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_VG_MASK 0x800000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT 23
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_TX_MASK 0x1000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_TX_SHIFT 24
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_RA_MASK 0x2000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_RA_SHIFT 25
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_SE_MASK 0x4000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_SE_SHIFT 26
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_PA_MASK 0x8000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_PA_SHIFT 27
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_SH_MASK 0x10000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_SH_SHIFT 28
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_PE_MASK 0x20000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT 29
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_DE_MASK 0x40000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_DE_SHIFT 30
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_FE_MASK 0x80000000u
#define GPU2D_ModulePowerModuleControl_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT 31
/* ModulePowerModuleStatus Bit Fields */
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_TS_MASK 0x100000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_TS_SHIFT 20
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_FP_MASK 0x200000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_FP_SHIFT 21
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_IM_MASK 0x400000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_IM_SHIFT 22
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_VG_MASK 0x800000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_VG_SHIFT 23
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_TX_MASK 0x1000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_TX_SHIFT 24
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_RA_MASK 0x2000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_RA_SHIFT 25
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_SE_MASK 0x4000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_SE_SHIFT 26
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_PA_MASK 0x8000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_PA_SHIFT 27
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_SH_MASK 0x10000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_SH_SHIFT 28
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_PE_MASK 0x20000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_PE_SHIFT 29
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_DE_MASK 0x40000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_DE_SHIFT 30
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_FE_MASK 0x80000000u
#define GPU2D_ModulePowerModuleStatus_MODULE_CLOCK_GATED_FE_SHIFT 31

/**
 * @}
 */ /* end of group GPU2D_Register_Masks */


/* GPU2D - Peripheral instance base addresses */
/** Peripheral GPU2D base address */
#define GPU2D_BASE                               (0x400CF000u)
/** Peripheral GPU2D base pointer */
#define GPU2D                                    ((GPU2D_Type *)GPU2D_BASE)
/** Array initializer of GPU2D peripheral base pointers */
#define GPU2D_BASES                              { GPU2D }

/**
 * @}
 */ /* end of group GPU2D_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
 * @{
 */

/** I2C - Register Layout Typedef */
typedef struct {
  __IO uint8_t IBAD;                               /**< I2C Bus Address Register, offset: 0x0 */
  __IO uint8_t IBFD;                               /**< I2C Bus Frequency Divider Register, offset: 0x1 */
  __IO uint8_t IBCR;                               /**< I2C Bus Control Register, offset: 0x2 */
  __IO uint8_t IBSR;                               /**< I2C Bus Status Register, offset: 0x3 */
  __IO uint8_t IBDR;                               /**< I2C Bus Data I/O Register, offset: 0x4 */
  __IO uint8_t IBIC;                               /**< I2C Bus Interrupt Config Register, offset: 0x5 */
  __IO uint8_t IBDBG;                              /**< I2C Bus Debug Register, offset: 0x6 */
} I2C_Type;

/* ----------------------------------------------------------------------------
   -- I2C Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup I2C_Register_Masks I2C Register Masks
 * @{
 */

/* IBAD Bit Fields */
#define I2C_IBAD_ADR_MASK                        0xFEu
#define I2C_IBAD_ADR_SHIFT                       1
#define I2C_IBAD_ADR(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_IBAD_ADR_SHIFT))&I2C_IBAD_ADR_MASK)
/* IBFD Bit Fields */
#define I2C_IBFD_IBC_MASK                        0xFFu
#define I2C_IBFD_IBC_SHIFT                       0
#define I2C_IBFD_IBC(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_IBFD_IBC_SHIFT))&I2C_IBFD_IBC_MASK)
/* IBCR Bit Fields */
#define I2C_IBCR_DMAEN_MASK                      0x2u
#define I2C_IBCR_DMAEN_SHIFT                     1
#define I2C_IBCR_RSTA_MASK                       0x4u
#define I2C_IBCR_RSTA_SHIFT                      2
#define I2C_IBCR_NOACK_MASK                      0x8u
#define I2C_IBCR_NOACK_SHIFT                     3
#define I2C_IBCR_TXRX_MASK                       0x10u
#define I2C_IBCR_TXRX_SHIFT                      4
#define I2C_IBCR_MSSL_MASK                       0x20u
#define I2C_IBCR_MSSL_SHIFT                      5
#define I2C_IBCR_IBIE_MASK                       0x40u
#define I2C_IBCR_IBIE_SHIFT                      6
#define I2C_IBCR_MDIS_MASK                       0x80u
#define I2C_IBCR_MDIS_SHIFT                      7
/* IBSR Bit Fields */
#define I2C_IBSR_RXAK_MASK                       0x1u
#define I2C_IBSR_RXAK_SHIFT                      0
#define I2C_IBSR_IBIF_MASK                       0x2u
#define I2C_IBSR_IBIF_SHIFT                      1
#define I2C_IBSR_SRW_MASK                        0x4u
#define I2C_IBSR_SRW_SHIFT                       2
#define I2C_IBSR_IBAL_MASK                       0x10u
#define I2C_IBSR_IBAL_SHIFT                      4
#define I2C_IBSR_IBB_MASK                        0x20u
#define I2C_IBSR_IBB_SHIFT                       5
#define I2C_IBSR_IAAS_MASK                       0x40u
#define I2C_IBSR_IAAS_SHIFT                      6
#define I2C_IBSR_TCF_MASK                        0x80u
#define I2C_IBSR_TCF_SHIFT                       7
/* IBDR Bit Fields */
#define I2C_IBDR_DATA_MASK                       0xFFu
#define I2C_IBDR_DATA_SHIFT                      0
#define I2C_IBDR_DATA(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_IBDR_DATA_SHIFT))&I2C_IBDR_DATA_MASK)
/* IBIC Bit Fields */
#define I2C_IBIC_BIIE_MASK                       0x80u
#define I2C_IBIC_BIIE_SHIFT                      7
/* IBDBG Bit Fields */
#define I2C_IBDBG_IPG_DEBUG_EN_MASK              0x1u
#define I2C_IBDBG_IPG_DEBUG_EN_SHIFT             0
#define I2C_IBDBG_IPG_DEBUG_HALTED_MASK          0x2u
#define I2C_IBDBG_IPG_DEBUG_HALTED_SHIFT         1

/**
 * @}
 */ /* end of group I2C_Register_Masks */


/* I2C - Peripheral instance base addresses */
/** Peripheral I2C0 base address */
#define I2C0_BASE                                (0x40066000u)
/** Peripheral I2C0 base pointer */
#define I2C0                                     ((I2C_Type *)I2C0_BASE)
/** Peripheral I2C1 base address */
#define I2C1_BASE                                (0x40067000u)
/** Peripheral I2C1 base pointer */
#define I2C1                                     ((I2C_Type *)I2C1_BASE)
/** Peripheral I2C2 base address */
#define I2C2_BASE                                (0x400E6000u)
/** Peripheral I2C2 base pointer */
#define I2C2                                     ((I2C_Type *)I2C2_BASE)
/** Peripheral I2C3 base address */
#define I2C3_BASE                                (0x400E7000u)
/** Peripheral I2C3 base pointer */
#define I2C3                                     ((I2C_Type *)I2C3_BASE)
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASES                                { I2C0, I2C1, I2C2, I2C3 }

/**
 * @}
 */ /* end of group I2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2S Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
 * @{
 */

/** I2S - Register Layout Typedef */
typedef struct {
  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
       uint8_t RESERVED_0[8];
  __O  uint32_t TDR[1];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_1[28];
  __I  uint32_t TFR[1];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_2[28];
  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
       uint8_t RESERVED_3[28];
  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
       uint8_t RESERVED_4[8];
  __I  uint32_t RDR[1];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
       uint8_t RESERVED_5[28];
  __I  uint32_t RFR[1];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_6[28];
  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
} I2S_Type;

/* ----------------------------------------------------------------------------
   -- I2S Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup I2S_Register_Masks I2S Register Masks
 * @{
 */

/* TCSR Bit Fields */
#define I2S_TCSR_FRDE_MASK                       0x1u
#define I2S_TCSR_FRDE_SHIFT                      0
#define I2S_TCSR_FWDE_MASK                       0x2u
#define I2S_TCSR_FWDE_SHIFT                      1
#define I2S_TCSR_FRIE_MASK                       0x100u
#define I2S_TCSR_FRIE_SHIFT                      8
#define I2S_TCSR_FWIE_MASK                       0x200u
#define I2S_TCSR_FWIE_SHIFT                      9
#define I2S_TCSR_FEIE_MASK                       0x400u
#define I2S_TCSR_FEIE_SHIFT                      10
#define I2S_TCSR_SEIE_MASK                       0x800u
#define I2S_TCSR_SEIE_SHIFT                      11
#define I2S_TCSR_WSIE_MASK                       0x1000u
#define I2S_TCSR_WSIE_SHIFT                      12
#define I2S_TCSR_FRF_MASK                        0x10000u
#define I2S_TCSR_FRF_SHIFT                       16
#define I2S_TCSR_FWF_MASK                        0x20000u
#define I2S_TCSR_FWF_SHIFT                       17
#define I2S_TCSR_FEF_MASK                        0x40000u
#define I2S_TCSR_FEF_SHIFT                       18
#define I2S_TCSR_SEF_MASK                        0x80000u
#define I2S_TCSR_SEF_SHIFT                       19
#define I2S_TCSR_WSF_MASK                        0x100000u
#define I2S_TCSR_WSF_SHIFT                       20
#define I2S_TCSR_SR_MASK                         0x1000000u
#define I2S_TCSR_SR_SHIFT                        24
#define I2S_TCSR_FR_MASK                         0x2000000u
#define I2S_TCSR_FR_SHIFT                        25
#define I2S_TCSR_BCE_MASK                        0x10000000u
#define I2S_TCSR_BCE_SHIFT                       28
#define I2S_TCSR_DBGE_MASK                       0x20000000u
#define I2S_TCSR_DBGE_SHIFT                      29
#define I2S_TCSR_STOPE_MASK                      0x40000000u
#define I2S_TCSR_STOPE_SHIFT                     30
#define I2S_TCSR_TE_MASK                         0x80000000u
#define I2S_TCSR_TE_SHIFT                        31
/* TCR1 Bit Fields */
#define I2S_TCR1_TFW_MASK                        0x3Fu
#define I2S_TCR1_TFW_SHIFT                       0
#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
/* TCR2 Bit Fields */
#define I2S_TCR2_DIV_MASK                        0xFFu
#define I2S_TCR2_DIV_SHIFT                       0
#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BCD_MASK                        0x1000000u
#define I2S_TCR2_BCD_SHIFT                       24
#define I2S_TCR2_BCP_MASK                        0x2000000u
#define I2S_TCR2_BCP_SHIFT                       25
#define I2S_TCR2_MSEL_MASK                       0xC000000u
#define I2S_TCR2_MSEL_SHIFT                      26
#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK                        0x10000000u
#define I2S_TCR2_BCI_SHIFT                       28
#define I2S_TCR2_BCS_MASK                        0x20000000u
#define I2S_TCR2_BCS_SHIFT                       29
#define I2S_TCR2_SYNC_MASK                       0xC0000000u
#define I2S_TCR2_SYNC_SHIFT                      30
#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
/* TCR3 Bit Fields */
#define I2S_TCR3_WDFL_MASK                       0x1Fu
#define I2S_TCR3_WDFL_SHIFT                      0
#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK                        0x10000u
#define I2S_TCR3_TCE_SHIFT                       16
/* TCR4 Bit Fields */
#define I2S_TCR4_FSD_MASK                        0x1u
#define I2S_TCR4_FSD_SHIFT                       0
#define I2S_TCR4_FSP_MASK                        0x2u
#define I2S_TCR4_FSP_SHIFT                       1
#define I2S_TCR4_FSE_MASK                        0x8u
#define I2S_TCR4_FSE_SHIFT                       3
#define I2S_TCR4_MF_MASK                         0x10u
#define I2S_TCR4_MF_SHIFT                        4
#define I2S_TCR4_SYWD_MASK                       0x1F00u
#define I2S_TCR4_SYWD_SHIFT                      8
#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
#define I2S_TCR4_FRSZ_SHIFT                      16
#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
/* TCR5 Bit Fields */
#define I2S_TCR5_FBT_MASK                        0x1F00u
#define I2S_TCR5_FBT_SHIFT                       8
#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK                        0x1F0000u
#define I2S_TCR5_W0W_SHIFT                       16
#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK                        0x1F000000u
#define I2S_TCR5_WNW_SHIFT                       24
#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
/* TDR Bit Fields */
#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
#define I2S_TDR_TDR_SHIFT                        0
#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
/* TFR Bit Fields */
#define I2S_TFR_RFP_MASK                         0x7Fu
#define I2S_TFR_RFP_SHIFT                        0
#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK                         0x7F0000u
#define I2S_TFR_WFP_SHIFT                        16
#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
/* TMR Bit Fields */
#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
#define I2S_TMR_TWM_SHIFT                        0
#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
/* RCSR Bit Fields */
#define I2S_RCSR_FRDE_MASK                       0x1u
#define I2S_RCSR_FRDE_SHIFT                      0
#define I2S_RCSR_FWDE_MASK                       0x2u
#define I2S_RCSR_FWDE_SHIFT                      1
#define I2S_RCSR_FRIE_MASK                       0x100u
#define I2S_RCSR_FRIE_SHIFT                      8
#define I2S_RCSR_FWIE_MASK                       0x200u
#define I2S_RCSR_FWIE_SHIFT                      9
#define I2S_RCSR_FEIE_MASK                       0x400u
#define I2S_RCSR_FEIE_SHIFT                      10
#define I2S_RCSR_SEIE_MASK                       0x800u
#define I2S_RCSR_SEIE_SHIFT                      11
#define I2S_RCSR_WSIE_MASK                       0x1000u
#define I2S_RCSR_WSIE_SHIFT                      12
#define I2S_RCSR_FRF_MASK                        0x10000u
#define I2S_RCSR_FRF_SHIFT                       16
#define I2S_RCSR_FWF_MASK                        0x20000u
#define I2S_RCSR_FWF_SHIFT                       17
#define I2S_RCSR_FEF_MASK                        0x40000u
#define I2S_RCSR_FEF_SHIFT                       18
#define I2S_RCSR_SEF_MASK                        0x80000u
#define I2S_RCSR_SEF_SHIFT                       19
#define I2S_RCSR_WSF_MASK                        0x100000u
#define I2S_RCSR_WSF_SHIFT                       20
#define I2S_RCSR_SR_MASK                         0x1000000u
#define I2S_RCSR_SR_SHIFT                        24
#define I2S_RCSR_FR_MASK                         0x2000000u
#define I2S_RCSR_FR_SHIFT                        25
#define I2S_RCSR_BCE_MASK                        0x10000000u
#define I2S_RCSR_BCE_SHIFT                       28
#define I2S_RCSR_DBGE_MASK                       0x20000000u
#define I2S_RCSR_DBGE_SHIFT                      29
#define I2S_RCSR_STOPE_MASK                      0x40000000u
#define I2S_RCSR_STOPE_SHIFT                     30
#define I2S_RCSR_RE_MASK                         0x80000000u
#define I2S_RCSR_RE_SHIFT                        31
/* RCR1 Bit Fields */
#define I2S_RCR1_RFW_MASK                        0x3Fu
#define I2S_RCR1_RFW_SHIFT                       0
#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
/* RCR2 Bit Fields */
#define I2S_RCR2_DIV_MASK                        0xFFu
#define I2S_RCR2_DIV_SHIFT                       0
#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BCD_MASK                        0x1000000u
#define I2S_RCR2_BCD_SHIFT                       24
#define I2S_RCR2_BCP_MASK                        0x2000000u
#define I2S_RCR2_BCP_SHIFT                       25
#define I2S_RCR2_MSEL_MASK                       0xC000000u
#define I2S_RCR2_MSEL_SHIFT                      26
#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK                        0x10000000u
#define I2S_RCR2_BCI_SHIFT                       28
#define I2S_RCR2_BCS_MASK                        0x20000000u
#define I2S_RCR2_BCS_SHIFT                       29
#define I2S_RCR2_SYNC_MASK                       0xC0000000u
#define I2S_RCR2_SYNC_SHIFT                      30
#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
/* RCR3 Bit Fields */
#define I2S_RCR3_WDFL_MASK                       0x1Fu
#define I2S_RCR3_WDFL_SHIFT                      0
#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK                        0x10000u
#define I2S_RCR3_RCE_SHIFT                       16
/* RCR4 Bit Fields */
#define I2S_RCR4_FSD_MASK                        0x1u
#define I2S_RCR4_FSD_SHIFT                       0
#define I2S_RCR4_FSP_MASK                        0x2u
#define I2S_RCR4_FSP_SHIFT                       1
#define I2S_RCR4_FSE_MASK                        0x8u
#define I2S_RCR4_FSE_SHIFT                       3
#define I2S_RCR4_MF_MASK                         0x10u
#define I2S_RCR4_MF_SHIFT                        4
#define I2S_RCR4_SYWD_MASK                       0x1F00u
#define I2S_RCR4_SYWD_SHIFT                      8
#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
#define I2S_RCR4_FRSZ_SHIFT                      16
#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
/* RCR5 Bit Fields */
#define I2S_RCR5_FBT_MASK                        0x1F00u
#define I2S_RCR5_FBT_SHIFT                       8
#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK                        0x1F0000u
#define I2S_RCR5_W0W_SHIFT                       16
#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK                        0x1F000000u
#define I2S_RCR5_WNW_SHIFT                       24
#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
/* RDR Bit Fields */
#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
#define I2S_RDR_RDR_SHIFT                        0
#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
/* RFR Bit Fields */
#define I2S_RFR_RFP_MASK                         0x7Fu
#define I2S_RFR_RFP_SHIFT                        0
#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
#define I2S_RFR_WFP_MASK                         0x7F0000u
#define I2S_RFR_WFP_SHIFT                        16
#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
/* RMR Bit Fields */
#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
#define I2S_RMR_RWM_SHIFT                        0
#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)

/**
 * @}
 */ /* end of group I2S_Register_Masks */


/* I2S - Peripheral instance base addresses */
/** Peripheral I2S0 base address */
#define I2S0_BASE                                (0x4002F000u)
/** Peripheral I2S0 base pointer */
#define I2S0                                     ((I2S_Type *)I2S0_BASE)
/** Peripheral I2S1 base address */
#define I2S1_BASE                                (0x40030000u)
/** Peripheral I2S1 base pointer */
#define I2S1                                     ((I2S_Type *)I2S1_BASE)
/** Peripheral I2S2 base address */
#define I2S2_BASE                                (0x40031000u)
/** Peripheral I2S2 base pointer */
#define I2S2                                     ((I2S_Type *)I2S2_BASE)
/** Peripheral I2S3 base address */
#define I2S3_BASE                                (0x40032000u)
/** Peripheral I2S3 base pointer */
#define I2S3                                     ((I2S_Type *)I2S3_BASE)
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASES                                { I2S0, I2S1, I2S2, I2S3 }

/**
 * @}
 */ /* end of group I2S_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOMUXC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
 * @{
 */

/** IOMUXC - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    __IO uint32_t RGPIO[135];                        /**< Software MUX Pad Control Register 0..Software MUX Pad Control Register 134, array offset: 0x0, array step: 0x4 */
    struct {                                         /* offset: 0x0 */
      __IO uint32_t PTA6;                              /**< Software MUX Pad Control Register 0, offset: 0x0 */
      __IO uint32_t PTA8;                              /**< Software MUX Pad Control Register 1, offset: 0x4 */
      __IO uint32_t PTA9;                              /**< Software MUX Pad Control Register 2, offset: 0x8 */
      __IO uint32_t PTA10;                             /**< Software MUX Pad Control Register 3, offset: 0xC */
      __IO uint32_t PTA11;                             /**< Software MUX Pad Control Register 4, offset: 0x10 */
      __IO uint32_t PTA12;                             /**< Software MUX Pad Control Register 5, offset: 0x14 */
      __IO uint32_t PTA16;                             /**< Software MUX Pad Control Register 6, offset: 0x18 */
      __IO uint32_t PTA17;                             /**< Software MUX Pad Control Register 7, offset: 0x1C */
      __IO uint32_t PTA18;                             /**< Software MUX Pad Control Register 8, offset: 0x20 */
      __IO uint32_t PTA19;                             /**< Software MUX Pad Control Register 9, offset: 0x24 */
      __IO uint32_t PTA20;                             /**< Software MUX Pad Control Register 10, offset: 0x28 */
      __IO uint32_t PTA21;                             /**< Software MUX Pad Control Register 11, offset: 0x2C */
      __IO uint32_t PTA22;                             /**< Software MUX Pad Control Register 12, offset: 0x30 */
      __IO uint32_t PTA23;                             /**< Software MUX Pad Control Register 13, offset: 0x34 */
      __IO uint32_t PTA24;                             /**< Software MUX Pad Control Register 14, offset: 0x38 */
      __IO uint32_t PTA25;                             /**< Software MUX Pad Control Register 15, offset: 0x3C */
      __IO uint32_t PTA26;                             /**< Software MUX Pad Control Register 16, offset: 0x40 */
      __IO uint32_t PTA27;                             /**< Software MUX Pad Control Register 17, offset: 0x44 */
      __IO uint32_t PTA28;                             /**< Software MUX Pad Control Register 18, offset: 0x48 */
      __IO uint32_t PTA29;                             /**< Software MUX Pad Control Register 19, offset: 0x4C */
      __IO uint32_t PTA30;                             /**< Software MUX Pad Control Register 20, offset: 0x50 */
      __IO uint32_t PTA31;                             /**< Software MUX Pad Control Register 21, offset: 0x54 */
      __IO uint32_t PTB0;                              /**< Software MUX Pad Control Register 22, offset: 0x58 */
      __IO uint32_t PTB1;                              /**< Software MUX Pad Control Register 23, offset: 0x5C */
      __IO uint32_t PTB2;                              /**< Software MUX Pad Control Register 24, offset: 0x60 */
      __IO uint32_t PTB3;                              /**< Software MUX Pad Control Register 25, offset: 0x64 */
      __IO uint32_t PTB4;                              /**< Software MUX Pad Control Register 26, offset: 0x68 */
      __IO uint32_t PTB5;                              /**< Software MUX Pad Control Register 27, offset: 0x6C */
      __IO uint32_t PTB6;                              /**< Software MUX Pad Control Register 28, offset: 0x70 */
      __IO uint32_t PTB7;                              /**< Software MUX Pad Control Register 29, offset: 0x74 */
      __IO uint32_t PTB8;                              /**< Software MUX Pad Control Register 30, offset: 0x78 */
      __IO uint32_t PTB9;                              /**< Software MUX Pad Control Register 31, offset: 0x7C */
      __IO uint32_t PTB10;                             /**< Software MUX Pad Control Register 32, offset: 0x80 */
      __IO uint32_t PTB11;                             /**< Software MUX Pad Control Register 33, offset: 0x84 */
      __IO uint32_t PTB12;                             /**< Software MUX Pad Control Register 34, offset: 0x88 */
      __IO uint32_t PTB13;                             /**< Software MUX Pad Control Register 35, offset: 0x8C */
      __IO uint32_t PTB14;                             /**< Software MUX Pad Control Register 36, offset: 0x90 */
      __IO uint32_t PTB15;                             /**< Software MUX Pad Control Register 37, offset: 0x94 */
      __IO uint32_t PTB16;                             /**< Software MUX Pad Control Register 38, offset: 0x98 */
      __IO uint32_t PTB17;                             /**< Software MUX Pad Control Register 39, offset: 0x9C */
      __IO uint32_t PTB18;                             /**< Software MUX Pad Control Register 40, offset: 0xA0 */
      __IO uint32_t PTB19;                             /**< Software MUX Pad Control Register 41, offset: 0xA4 */
      __IO uint32_t PTB20;                             /**< Software MUX Pad Control Register 42, offset: 0xA8 */
      __IO uint32_t PTB21;                             /**< Software MUX Pad Control Register 43, offset: 0xAC */
      __IO uint32_t PTB22;                             /**< Software MUX Pad Control Register 44, offset: 0xB0 */
      __IO uint32_t PTC0;                              /**< Software MUX Pad Control Register 45, offset: 0xB4 */
      __IO uint32_t PTC1;                              /**< Software MUX Pad Control Register 46, offset: 0xB8 */
      __IO uint32_t PTC2;                              /**< Software MUX Pad Control Register 47, offset: 0xBC */
      __IO uint32_t PTC3;                              /**< Software MUX Pad Control Register 48, offset: 0xC0 */
      __IO uint32_t PTC4;                              /**< Software MUX Pad Control Register 49, offset: 0xC4 */
      __IO uint32_t PTC5;                              /**< Software MUX Pad Control Register 50, offset: 0xC8 */
      __IO uint32_t PTC6;                              /**< Software MUX Pad Control Register 51, offset: 0xCC */
      __IO uint32_t PTC7;                              /**< Software MUX Pad Control Register 52, offset: 0xD0 */
      __IO uint32_t PTC8;                              /**< Software MUX Pad Control Register 53, offset: 0xD4 */
      __IO uint32_t PTC9;                              /**< Software MUX Pad Control Register 54, offset: 0xD8 */
      __IO uint32_t PTC10;                             /**< Software MUX Pad Control Register 55, offset: 0xDC */
      __IO uint32_t PTC11;                             /**< Software MUX Pad Control Register 56, offset: 0xE0 */
      __IO uint32_t PTC12;                             /**< Software MUX Pad Control Register 57, offset: 0xE4 */
      __IO uint32_t PTC13;                             /**< Software MUX Pad Control Register 58, offset: 0xE8 */
      __IO uint32_t PTC14;                             /**< Software MUX Pad Control Register 59, offset: 0xEC */
      __IO uint32_t PTC15;                             /**< Software MUX Pad Control Register 60, offset: 0xF0 */
      __IO uint32_t PTC16;                             /**< Software MUX Pad Control Register 61, offset: 0xF4 */
      __IO uint32_t PTC17;                             /**< Software MUX Pad Control Register 62, offset: 0xF8 */
      __IO uint32_t PTD31;                             /**< Software MUX Pad Control Register 63, offset: 0xFC */
      __IO uint32_t PTD30;                             /**< Software MUX Pad Control Register 64, offset: 0x100 */
      __IO uint32_t PTD29;                             /**< Software MUX Pad Control Register 65, offset: 0x104 */
      __IO uint32_t PTD28;                             /**< Software MUX Pad Control Register 66, offset: 0x108 */
      __IO uint32_t PTD27;                             /**< Software MUX Pad Control Register 67, offset: 0x10C */
      __IO uint32_t PTD26;                             /**< Software MUX Pad Control Register 68, offset: 0x110 */
      __IO uint32_t PTD25;                             /**< Software MUX Pad Control Register 69, offset: 0x114 */
      __IO uint32_t PTD24;                             /**< Software MUX Pad Control Register 70, offset: 0x118 */
      __IO uint32_t PTD23;                             /**< Software MUX Pad Control Register 71, offset: 0x11C */
      __IO uint32_t PTD22;                             /**< Software MUX Pad Control Register 72, offset: 0x120 */
      __IO uint32_t PTD21;                             /**< Software MUX Pad Control Register 73, offset: 0x124 */
      __IO uint32_t PTD20;                             /**< Software MUX Pad Control Register 74, offset: 0x128 */
      __IO uint32_t PTD19;                             /**< Software MUX Pad Control Register 75, offset: 0x12C */
      __IO uint32_t PTD18;                             /**< Software MUX Pad Control Register 76, offset: 0x130 */
      __IO uint32_t PTD17;                             /**< Software MUX Pad Control Register 77, offset: 0x134 */
      __IO uint32_t PTD16;                             /**< Software MUX Pad Control Register 78, offset: 0x138 */
      __IO uint32_t PTD0;                              /**< Software MUX Pad Control Register 79, offset: 0x13C */
      __IO uint32_t PTD1;                              /**< Software MUX Pad Control Register 80, offset: 0x140 */
      __IO uint32_t PTD2;                              /**< Software MUX Pad Control Register 81, offset: 0x144 */
      __IO uint32_t PTD3;                              /**< Software MUX Pad Control Register 82, offset: 0x148 */
      __IO uint32_t PTD4;                              /**< Software MUX Pad Control Register 83, offset: 0x14C */
      __IO uint32_t PTD5;                              /**< Software MUX Pad Control Register 84, offset: 0x150 */
      __IO uint32_t PTD6;                              /**< Software MUX Pad Control Register 85, offset: 0x154 */
      __IO uint32_t PTD7;                              /**< Software MUX Pad Control Register 86, offset: 0x158 */
      __IO uint32_t PTD8;                              /**< Software MUX Pad Control Register 87, offset: 0x15C */
      __IO uint32_t PTD9;                              /**< Software MUX Pad Control Register 88, offset: 0x160 */
      __IO uint32_t PTD10;                             /**< Software MUX Pad Control Register 89, offset: 0x164 */
      __IO uint32_t PTD11;                             /**< Software MUX Pad Control Register 90, offset: 0x168 */
      __IO uint32_t PTD12;                             /**< Software MUX Pad Control Register 91, offset: 0x16C */
      __IO uint32_t PTD13;                             /**< Software MUX Pad Control Register 92, offset: 0x170 */
      __IO uint32_t PTB23;                             /**< Software MUX Pad Control Register 93, offset: 0x174 */
      __IO uint32_t PTB24;                             /**< Software MUX Pad Control Register 94, offset: 0x178 */
      __IO uint32_t PTB25;                             /**< Software MUX Pad Control Register 95, offset: 0x17C */
      __IO uint32_t PTB26;                             /**< Software MUX Pad Control Register 96, offset: 0x180 */
      __IO uint32_t PTB27;                             /**< Software MUX Pad Control Register 97, offset: 0x184 */
      __IO uint32_t PTB28;                             /**< Software MUX Pad Control Register 98, offset: 0x188 */
      __IO uint32_t PTC26;                             /**< Software MUX Pad Control Register 99, offset: 0x18C */
      __IO uint32_t PTC27;                             /**< Software MUX Pad Control Register 100, offset: 0x190 */
      __IO uint32_t PTC28;                             /**< Software MUX Pad Control Register 101, offset: 0x194 */
      __IO uint32_t PTC29;                             /**< Software MUX Pad Control Register 102, offset: 0x198 */
      __IO uint32_t PTC30;                             /**< Software MUX Pad Control Register 103, offset: 0x19C */
      __IO uint32_t PTC31;                             /**< Software MUX Pad Control Register 104, offset: 0x1A0 */
      __IO uint32_t PTE0;                              /**< Software MUX Pad Control Register 105, offset: 0x1A4 */
      __IO uint32_t PTE1;                              /**< Software MUX Pad Control Register 106, offset: 0x1A8 */
      __IO uint32_t PTE2;                              /**< Software MUX Pad Control Register 107, offset: 0x1AC */
      __IO uint32_t PTE3;                              /**< Software MUX Pad Control Register 108, offset: 0x1B0 */
      __IO uint32_t PTE4;                              /**< Software MUX Pad Control Register 109, offset: 0x1B4 */
      __IO uint32_t PTE5;                              /**< Software MUX Pad Control Register 110, offset: 0x1B8 */
      __IO uint32_t PTE6;                              /**< Software MUX Pad Control Register 111, offset: 0x1BC */
      __IO uint32_t PTE7;                              /**< Software MUX Pad Control Register 112, offset: 0x1C0 */
      __IO uint32_t PTE8;                              /**< Software MUX Pad Control Register 113, offset: 0x1C4 */
      __IO uint32_t PTE9;                              /**< Software MUX Pad Control Register 114, offset: 0x1C8 */
      __IO uint32_t PTE10;                             /**< Software MUX Pad Control Register 115, offset: 0x1CC */
      __IO uint32_t PTE11;                             /**< Software MUX Pad Control Register 116, offset: 0x1D0 */
      __IO uint32_t PTE12;                             /**< Software MUX Pad Control Register 117, offset: 0x1D4 */
      __IO uint32_t PTE13;                             /**< Software MUX Pad Control Register 118, offset: 0x1D8 */
      __IO uint32_t PTE14;                             /**< Software MUX Pad Control Register 119, offset: 0x1DC */
      __IO uint32_t PTE15;                             /**< Software MUX Pad Control Register 120, offset: 0x1E0 */
      __IO uint32_t PTE16;                             /**< Software MUX Pad Control Register 121, offset: 0x1E4 */
      __IO uint32_t PTE17;                             /**< Software MUX Pad Control Register 122, offset: 0x1E8 */
      __IO uint32_t PTE18;                             /**< Software MUX Pad Control Register 123, offset: 0x1EC */
      __IO uint32_t PTE19;                             /**< Software MUX Pad Control Register 124, offset: 0x1F0 */
      __IO uint32_t PTE20;                             /**< Software MUX Pad Control Register 125, offset: 0x1F4 */
      __IO uint32_t PTE21;                             /**< Software MUX Pad Control Register 126, offset: 0x1F8 */
      __IO uint32_t PTE22;                             /**< Software MUX Pad Control Register 127, offset: 0x1FC */
      __IO uint32_t PTE23;                             /**< Software MUX Pad Control Register 128, offset: 0x200 */
      __IO uint32_t PTE24;                             /**< Software MUX Pad Control Register 129, offset: 0x204 */
      __IO uint32_t PTE25;                             /**< Software MUX Pad Control Register 130, offset: 0x208 */
      __IO uint32_t PTE26;                             /**< Software MUX Pad Control Register 131, offset: 0x20C */
      __IO uint32_t PTE27;                             /**< Software MUX Pad Control Register 132, offset: 0x210 */
      __IO uint32_t PTE28;                             /**< Software MUX Pad Control Register 133, offset: 0x214 */
      __IO uint32_t PTA7;                              /**< Software MUX Pad Control Register 134, offset: 0x218 */
    } SINGLE;
  };
  __IO uint32_t DDR_RESETB;                        /**< Software MUX DDR RESET Pad Configuration Register, offset: 0x21C */
  __IO uint32_t DDR_A_15;                          /**< Software MUX DDR A15 Pad Control Register, offset: 0x220 */
  __IO uint32_t DDR_A_14;                          /**< Software MUX DDR A14 Pad Control Register, offset: 0x224 */
  __IO uint32_t DDR_A_13;                          /**< Software MUX DDR A13 Pad Control Register, offset: 0x228 */
  __IO uint32_t DDR_A_12;                          /**< Software MUX DDR A12 Pad Control Register, offset: 0x22C */
  __IO uint32_t DDR_A_11;                          /**< Software MUX DDR A11 Pad Control Register, offset: 0x230 */
  __IO uint32_t DDR_A_10;                          /**< Software MUX DDR A10 Pad Control Register, offset: 0x234 */
  __IO uint32_t DDR_A_9;                           /**< Software MUX DDR A9 Pad Control Register, offset: 0x238 */
  __IO uint32_t DDR_A_8;                           /**< Software MUX DDR A8 Pad Control Register, offset: 0x23C */
  __IO uint32_t DDR_A_7;                           /**< Software MUX DDR A7 Pad Control Register, offset: 0x240 */
  __IO uint32_t DDR_A_6;                           /**< Software MUX DDR A6 Pad Control Register, offset: 0x244 */
  __IO uint32_t DDR_A_5;                           /**< Software MUX DDR A5 Pad Control Register, offset: 0x248 */
  __IO uint32_t DDR_A_4;                           /**< Software MUX DDR A4 Pad Control Register, offset: 0x24C */
  __IO uint32_t DDR_A_3;                           /**< Software MUX DDR Pad A3 Control Register, offset: 0x250 */
  __IO uint32_t DDR_A_2;                           /**< Software MUX DDR A2 Pad Control Register, offset: 0x254 */
  __IO uint32_t DDR_A_1;                           /**< Software MUX DDR A1 Pad Control Register, offset: 0x258 */
  __IO uint32_t DDR_A_0;                           /**< Software MUX DDR A0 Pad Control Register, offset: 0x25C */
  __IO uint32_t DDR_BA_2;                          /**< Software MUX DDR BA2 Pad Control Register, offset: 0x260 */
  __IO uint32_t DDR_BA_1;                          /**< Software MUX DDR BA1 Pad Control Register, offset: 0x264 */
  __IO uint32_t DDR_BA_0;                          /**< Software MUX DDR BA0 Pad Control Register, offset: 0x268 */
  __IO uint32_t DDR_CAS_B;                         /**< Software MUX DDR CAS Pad Control Register, offset: 0x26C */
  __IO uint32_t DDR_CKE_0;                         /**< Software MUX DDR CKE0 Pad Control Register, offset: 0x270 */
  __IO uint32_t DDR_CLK_0;                         /**< Software MUX DDR CLK0 Pad Control Register, offset: 0x274 */
  __IO uint32_t DDR_CS_B_0;                        /**< Software MUX DDR CS B0 Pad Control Register, offset: 0x278 */
  __IO uint32_t DDR_CS_D_15;                       /**< Software MUX DDR CS D15 Pad Control Register, offset: 0x27C */
  __IO uint32_t DDR_CS_D_14;                       /**< Software MUX DDR CS D14 Pad Control Register, offset: 0x280 */
  __IO uint32_t DDR_CS_D_13;                       /**< Software MUX DDR CS D13 Pad Control Register, offset: 0x284 */
  __IO uint32_t DDR_CS_D_12;                       /**< Software MUX DDR CS D12 Pad Control Register, offset: 0x288 */
  __IO uint32_t DDR_CS_D_11;                       /**< Software MUX DDR CS D11 Pad Control Register, offset: 0x28C */
  __IO uint32_t DDR_CS_D_10;                       /**< Software MUX DDR CS D10 Pad Control Register, offset: 0x290 */
  __IO uint32_t DDR_CS_D_9;                        /**< Software MUX DDR CS D9 Pad Control Register, offset: 0x294 */
  __IO uint32_t DDR_CS_D_8;                        /**< Software MUX DDR CS D8 Pad Control Register, offset: 0x298 */
  __IO uint32_t DDR_CS_D_7;                        /**< Software MUX DDR CS D7 Pad Control Register, offset: 0x29C */
  __IO uint32_t DDR_CS_D_6;                        /**< Software MUX DDR CS D6 Pad Control Register, offset: 0x2A0 */
  __IO uint32_t DDR_CS_D_5;                        /**< Software MUX DDR CS D5 Pad Control Register, offset: 0x2A4 */
  __IO uint32_t DDR_CS_D_4;                        /**< Software MUX DDR CS D4 Pad Control Register, offset: 0x2A8 */
  __IO uint32_t DDR_CS_D_3;                        /**< Software MUX DDR CS D3 Pad Control Register, offset: 0x2AC */
  __IO uint32_t DDR_CS_D_2;                        /**< Software MUX DDR CS D2 Pad Control Register, offset: 0x2B0 */
  __IO uint32_t DDR_CS_D_1;                        /**< Software MUX DDR CS D1 Pad Control Register, offset: 0x2B4 */
  __IO uint32_t DDR_CS_D_0;                        /**< Software MUX DDR CS D0 Pad Control Register, offset: 0x2B8 */
  __IO uint32_t DDR_DQM_1;                         /**< Software MUX DDR DQM1 Pad Control Register, offset: 0x2BC */
  __IO uint32_t DDR_DQM_0;                         /**< Software MUX DDR DQM0 Pad Control Register 0, offset: 0x2C0 */
  __IO uint32_t DDR_DQS_1;                         /**< Software MUX DDR DQS1 Pad Control Register 1, offset: 0x2C4 */
  __IO uint32_t DDR_DQS_0;                         /**< Software MUX DDR DQS0 Pad Control Register 0, offset: 0x2C8 */
  __IO uint32_t DDR_RAS_B;                         /**< Software MUX DDR RAS Pad Control Register, offset: 0x2CC */
  __IO uint32_t DDR_WE_B;                          /**< Software MUX DDR WE Pad Control Register, offset: 0x2D0 */
  __IO uint32_t DDR_ODT_0;                         /**< Software MUX DDR ODT0 Pad Control Register, offset: 0x2D4 */
  __IO uint32_t DDR_ODT_1;                         /**< Software MUX DDR ODT1 Pad Control Register, offset: 0x2D8 */
  __IO uint32_t DUMMY_DDRBYTE1;                    /**< Software MUX Dummy DDRBYTE1 Pad Control Register, offset: 0x2DC */
  __IO uint32_t DUMMY_DDRBYTE2;                    /**< Software MUX Dummy DDRBYTE2 Pad Control Register, offset: 0x2E0 */
  __IO uint32_t DUMMY_QUADSPI0;                    /**< Software MUX Dummy QUADSPI0 Pad Control Register, offset: 0x2E4 */
  __IO uint32_t DUMMY_QUADSPI1;                    /**< Software MUX Dummy QUADSPI1 Pad Control Register, offset: 0x2E8 */
  __IO uint32_t CCM_AUD_EXT_CLK_SELECT_INPUT;      /**< CCM Audio External Clock Input Select Register, offset: 0x2EC */
  __IO uint32_t CCM_ENET_EXT_CLK_SELECT_INPUT;     /**< CCM Ethernet External Clock Input Select Register, offset: 0x2F0 */
  __IO uint32_t CCM_ENET_TS_CLK_SELECT_INPUT;      /**< CCM Ethernet TS Clock Input Select Register, offset: 0x2F4 */
  __IO uint32_t DSPI1_IPP_IND_SCK_SELECT_INPUT;    /**< DSPI1 SCK Input Select Register, offset: 0x2F8 */
  __IO uint32_t DSPI1_IPP_IND_SIN_SELECT_INPUT;    /**< DSPI1 SIN Input Select Register, offset: 0x2FC */
  __IO uint32_t DSPI1_IPP_IND_SS_B_SELECT_INPUT;   /**< DSPI1 SS Input Select Register, offset: 0x300 */
  __IO uint32_t ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT; /**< Ethernet MAC0 TIMER0 Input Select Register, offset: 0x304 */
  __IO uint32_t ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT; /**< Ethernet MAC0 TIMER1 Input Select Register, offset: 0x308 */
  __IO uint32_t ESAI_IPP_IND_FST_SELECT_INPUT;     /**< ESAI FST Input Select Register, offset: 0x30C */
  __IO uint32_t ESAI_IPP_IND_SCKT_SELECT_INPUT;    /**< ESAI SCKT Input Select Register, offset: 0x310 */
  __IO uint32_t ESAI_IPP_IND_SDO0_SELECT_INPUT;    /**< ESAI SDO0 Input Select Register, offset: 0x314 */
  __IO uint32_t ESAI_IPP_IND_SDO1_SELECT_INPUT;    /**< ESAI SDO1 Input Select Register, offset: 0x318 */
  __IO uint32_t ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT; /**< ESAI SDO2 Input Select Register, offset: 0x31C */
  __IO uint32_t ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT; /**< ESAI SDO3 Input Select Register, offset: 0x320 */
  __IO uint32_t ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT; /**< ESAI SDO4 Input Select Register, offset: 0x324 */
  __IO uint32_t ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT; /**< ESAI SDO5 Input Select Register, offset: 0x328 */
  __IO uint32_t FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT; /**< FlexTimer1 CH0 Input Select Register, offset: 0x32C */
  __IO uint32_t FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT; /**< FlexTimer1 CH1 Input Select Register, offset: 0x330 */
  __IO uint32_t FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT; /**< FlexTimer1 PHA Input Select Register, offset: 0x334 */
  __IO uint32_t FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT; /**< FlexTimer1 PHB Input Select Register, offset: 0x338 */
  __IO uint32_t I2C0_IPP_SCL_IND_SELECT_INPUT;     /**< I2C0 SCL Input Select Register, offset: 0x33C */
  __IO uint32_t I2C0_IPP_SDA_IND_SELECT_INPUT;     /**< I2C0 SDA Input Select Register, offset: 0x340 */
  __IO uint32_t I2C1_IPP_SCL_IND_SELECT_INPUT;     /**< I2C1 SCL Input Select Register, offset: 0x344 */
  __IO uint32_t I2C1_IPP_SDA_IND_SELECT_INPUT;     /**< I2C1 SDA Input Select Register, offset: 0x348 */
  __IO uint32_t I2C2_IPP_SCL_IND_SELECT_INPUT;     /**< I2C2 SCL Input Select Register, offset: 0x34C */
  __IO uint32_t I2C2_IPP_SDA_IND_SELECT_INPUT;     /**< I2C2 SDA Input Select Register, offset: 0x350 */
  __IO uint32_t MLB_TOP_MLBCLK_IN_SELECT_INPUT;    /**< MediaLB Clock Input Select Register, offset: 0x354 */
  __IO uint32_t MLB_TOP_MLBDAT_IN_SELECT_INPUT;    /**< MediaLB Data Input Select Register, offset: 0x358 */
  __IO uint32_t MLB_TOP_MLBSIG_IN_SELECT_INPUT;    /**< MediaLB Signal Input Select Register, offset: 0x35C */
  __IO uint32_t SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT; /**< SAI1 TXSYNC Input Select Register, offset: 0x360 */
  __IO uint32_t SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT; /**< SAI2 RXBCLK Input Select Register, offset: 0x364 */
  __IO uint32_t SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT; /**< SAI2 RXDATA0 Input Select Register, offset: 0x368 */
  __IO uint32_t SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT; /**< SAI2 RXSYNC Input Select Register, offset: 0x36C */
  __IO uint32_t SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT; /**< SAI2 TXBLCK Input Select Register, offset: 0x370 */
  __IO uint32_t SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT; /**< SAI2 TXSYNC Input Select Register, offset: 0x374 */
  __IO uint32_t SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT; /**< UART FLX1 CTS Input Select Register, offset: 0x378 */
  __IO uint32_t SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT; /**< UART FLX1 RX Input Select Register, offset: 0x37C */
  __IO uint32_t SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT; /**< UART FLX1 TX Input Select Register, offset: 0x380 */
  __IO uint32_t SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT; /**< UART FLX2 CTS Input Select Register, offset: 0x384 */
  __IO uint32_t SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT; /**< UART FLX2 RX Input Select Register, offset: 0x388 */
  __IO uint32_t SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT; /**< UART FLX2 TX Input Select Register, offset: 0x38C */
  __IO uint32_t SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT; /**< UART FLX3 RX Input Select Register, offset: 0x390 */
  __IO uint32_t SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT; /**< UART FLX3 TX Input Select Register, offset: 0x394 */
  __IO uint32_t SRC_IPP_BOOT_CFG_18_SELECT_INPUT;  /**< BOOTCFG18 Input Select Register, offset: 0x398 */
  __IO uint32_t SRC_IPP_BOOT_CFG_19_SELECT_INPUT;  /**< BOOTCFG19 Input Select Register, offset: 0x39C */
  __IO uint32_t SRC_IPP_BOOT_CFG_20_SELECT_INPUT;  /**< BOOTCFG20 Input Select Register, offset: 0x3A0 */
  __IO uint32_t VIDEO_IN0_IPP_IND_DE_SELECT_INPUT; /**< Video Decoder Input Select Register, offset: 0x3A4 */
  __IO uint32_t VIDEO_IN0_IPP_IND_FID_SELECT_INPUT; /**< Video IN0 Input Select Register, offset: 0x3A8 */
  __IO uint32_t VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT; /**< Video PIXCLK Input Select Register, offset: 0x3AC */
} IOMUXC_Type;

/* ----------------------------------------------------------------------------
   -- IOMUXC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
 * @{
 */

/* RGPIO Bit Fields */
#define IOMUXC_RGPIO_IBE_MASK                    0x1u
#define IOMUXC_RGPIO_IBE_SHIFT                   0
#define IOMUXC_RGPIO_OBE_MASK                    0x2u
#define IOMUXC_RGPIO_OBE_SHIFT                   1
#define IOMUXC_RGPIO_PUE_MASK                    0x4u
#define IOMUXC_RGPIO_PUE_SHIFT                   2
#define IOMUXC_RGPIO_PKE_MASK                    0x8u
#define IOMUXC_RGPIO_PKE_SHIFT                   3
#define IOMUXC_RGPIO_PUS_MASK                    0x30u
#define IOMUXC_RGPIO_PUS_SHIFT                   4
#define IOMUXC_RGPIO_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_RGPIO_PUS_SHIFT))&IOMUXC_RGPIO_PUS_MASK)
#define IOMUXC_RGPIO_DSE_MASK                    0x1C0u
#define IOMUXC_RGPIO_DSE_SHIFT                   6
#define IOMUXC_RGPIO_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_RGPIO_DSE_SHIFT))&IOMUXC_RGPIO_DSE_MASK)
#define IOMUXC_RGPIO_HYS_MASK                    0x200u
#define IOMUXC_RGPIO_HYS_SHIFT                   9
#define IOMUXC_RGPIO_ODE_MASK                    0x400u
#define IOMUXC_RGPIO_ODE_SHIFT                   10
#define IOMUXC_RGPIO_SRE_MASK                    0x800u
#define IOMUXC_RGPIO_SRE_SHIFT                   11
#define IOMUXC_RGPIO_SPEED_MASK                  0x3000u
#define IOMUXC_RGPIO_SPEED_SHIFT                 12
#define IOMUXC_RGPIO_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_RGPIO_SPEED_SHIFT))&IOMUXC_RGPIO_SPEED_MASK)
#define IOMUXC_RGPIO_MUX_MODE_MASK               0x700000u
#define IOMUXC_RGPIO_MUX_MODE_SHIFT              20
#define IOMUXC_RGPIO_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_RGPIO_MUX_MODE_SHIFT))&IOMUXC_RGPIO_MUX_MODE_MASK)
/* PTA6 Bit Fields */
#define IOMUXC_PTA6_IBE_MASK                     0x1u
#define IOMUXC_PTA6_IBE_SHIFT                    0
#define IOMUXC_PTA6_OBE_MASK                     0x2u
#define IOMUXC_PTA6_OBE_SHIFT                    1
#define IOMUXC_PTA6_PUE_MASK                     0x4u
#define IOMUXC_PTA6_PUE_SHIFT                    2
#define IOMUXC_PTA6_PKE_MASK                     0x8u
#define IOMUXC_PTA6_PKE_SHIFT                    3
#define IOMUXC_PTA6_PUS_MASK                     0x30u
#define IOMUXC_PTA6_PUS_SHIFT                    4
#define IOMUXC_PTA6_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA6_PUS_SHIFT))&IOMUXC_PTA6_PUS_MASK)
#define IOMUXC_PTA6_DSE_MASK                     0x1C0u
#define IOMUXC_PTA6_DSE_SHIFT                    6
#define IOMUXC_PTA6_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA6_DSE_SHIFT))&IOMUXC_PTA6_DSE_MASK)
#define IOMUXC_PTA6_HYS_MASK                     0x200u
#define IOMUXC_PTA6_HYS_SHIFT                    9
#define IOMUXC_PTA6_ODE_MASK                     0x400u
#define IOMUXC_PTA6_ODE_SHIFT                    10
#define IOMUXC_PTA6_SRE_MASK                     0x800u
#define IOMUXC_PTA6_SRE_SHIFT                    11
#define IOMUXC_PTA6_SPEED_MASK                   0x3000u
#define IOMUXC_PTA6_SPEED_SHIFT                  12
#define IOMUXC_PTA6_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA6_SPEED_SHIFT))&IOMUXC_PTA6_SPEED_MASK)
#define IOMUXC_PTA6_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTA6_MUX_MODE_SHIFT               20
#define IOMUXC_PTA6_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA6_MUX_MODE_SHIFT))&IOMUXC_PTA6_MUX_MODE_MASK)
/* PTA8 Bit Fields */
#define IOMUXC_PTA8_IBE_MASK                     0x1u
#define IOMUXC_PTA8_IBE_SHIFT                    0
#define IOMUXC_PTA8_OBE_MASK                     0x2u
#define IOMUXC_PTA8_OBE_SHIFT                    1
#define IOMUXC_PTA8_PUE_MASK                     0x4u
#define IOMUXC_PTA8_PUE_SHIFT                    2
#define IOMUXC_PTA8_PKE_MASK                     0x8u
#define IOMUXC_PTA8_PKE_SHIFT                    3
#define IOMUXC_PTA8_PUS_MASK                     0x30u
#define IOMUXC_PTA8_PUS_SHIFT                    4
#define IOMUXC_PTA8_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA8_PUS_SHIFT))&IOMUXC_PTA8_PUS_MASK)
#define IOMUXC_PTA8_DSE_MASK                     0x1C0u
#define IOMUXC_PTA8_DSE_SHIFT                    6
#define IOMUXC_PTA8_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA8_DSE_SHIFT))&IOMUXC_PTA8_DSE_MASK)
#define IOMUXC_PTA8_HYS_MASK                     0x200u
#define IOMUXC_PTA8_HYS_SHIFT                    9
#define IOMUXC_PTA8_ODE_MASK                     0x400u
#define IOMUXC_PTA8_ODE_SHIFT                    10
#define IOMUXC_PTA8_SRE_MASK                     0x800u
#define IOMUXC_PTA8_SRE_SHIFT                    11
#define IOMUXC_PTA8_SPEED_MASK                   0x3000u
#define IOMUXC_PTA8_SPEED_SHIFT                  12
#define IOMUXC_PTA8_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA8_SPEED_SHIFT))&IOMUXC_PTA8_SPEED_MASK)
#define IOMUXC_PTA8_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTA8_MUX_MODE_SHIFT               20
#define IOMUXC_PTA8_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA8_MUX_MODE_SHIFT))&IOMUXC_PTA8_MUX_MODE_MASK)
/* PTA9 Bit Fields */
#define IOMUXC_PTA9_IBE_MASK                     0x1u
#define IOMUXC_PTA9_IBE_SHIFT                    0
#define IOMUXC_PTA9_OBE_MASK                     0x2u
#define IOMUXC_PTA9_OBE_SHIFT                    1
#define IOMUXC_PTA9_PUE_MASK                     0x4u
#define IOMUXC_PTA9_PUE_SHIFT                    2
#define IOMUXC_PTA9_PKE_MASK                     0x8u
#define IOMUXC_PTA9_PKE_SHIFT                    3
#define IOMUXC_PTA9_PUS_MASK                     0x30u
#define IOMUXC_PTA9_PUS_SHIFT                    4
#define IOMUXC_PTA9_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA9_PUS_SHIFT))&IOMUXC_PTA9_PUS_MASK)
#define IOMUXC_PTA9_DSE_MASK                     0x1C0u
#define IOMUXC_PTA9_DSE_SHIFT                    6
#define IOMUXC_PTA9_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA9_DSE_SHIFT))&IOMUXC_PTA9_DSE_MASK)
#define IOMUXC_PTA9_HYS_MASK                     0x200u
#define IOMUXC_PTA9_HYS_SHIFT                    9
#define IOMUXC_PTA9_ODE_MASK                     0x400u
#define IOMUXC_PTA9_ODE_SHIFT                    10
#define IOMUXC_PTA9_SRE_MASK                     0x800u
#define IOMUXC_PTA9_SRE_SHIFT                    11
#define IOMUXC_PTA9_SPEED_MASK                   0x3000u
#define IOMUXC_PTA9_SPEED_SHIFT                  12
#define IOMUXC_PTA9_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA9_SPEED_SHIFT))&IOMUXC_PTA9_SPEED_MASK)
#define IOMUXC_PTA9_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTA9_MUX_MODE_SHIFT               20
#define IOMUXC_PTA9_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA9_MUX_MODE_SHIFT))&IOMUXC_PTA9_MUX_MODE_MASK)
/* PTA10 Bit Fields */
#define IOMUXC_PTA10_IBE_MASK                    0x1u
#define IOMUXC_PTA10_IBE_SHIFT                   0
#define IOMUXC_PTA10_OBE_MASK                    0x2u
#define IOMUXC_PTA10_OBE_SHIFT                   1
#define IOMUXC_PTA10_PUE_MASK                    0x4u
#define IOMUXC_PTA10_PUE_SHIFT                   2
#define IOMUXC_PTA10_PKE_MASK                    0x8u
#define IOMUXC_PTA10_PKE_SHIFT                   3
#define IOMUXC_PTA10_PUS_MASK                    0x30u
#define IOMUXC_PTA10_PUS_SHIFT                   4
#define IOMUXC_PTA10_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA10_PUS_SHIFT))&IOMUXC_PTA10_PUS_MASK)
#define IOMUXC_PTA10_DSE_MASK                    0x1C0u
#define IOMUXC_PTA10_DSE_SHIFT                   6
#define IOMUXC_PTA10_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA10_DSE_SHIFT))&IOMUXC_PTA10_DSE_MASK)
#define IOMUXC_PTA10_HYS_MASK                    0x200u
#define IOMUXC_PTA10_HYS_SHIFT                   9
#define IOMUXC_PTA10_ODE_MASK                    0x400u
#define IOMUXC_PTA10_ODE_SHIFT                   10
#define IOMUXC_PTA10_SRE_MASK                    0x800u
#define IOMUXC_PTA10_SRE_SHIFT                   11
#define IOMUXC_PTA10_SPEED_MASK                  0x3000u
#define IOMUXC_PTA10_SPEED_SHIFT                 12
#define IOMUXC_PTA10_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA10_SPEED_SHIFT))&IOMUXC_PTA10_SPEED_MASK)
#define IOMUXC_PTA10_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA10_MUX_MODE_SHIFT              20
#define IOMUXC_PTA10_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA10_MUX_MODE_SHIFT))&IOMUXC_PTA10_MUX_MODE_MASK)
/* PTA11 Bit Fields */
#define IOMUXC_PTA11_IBE_MASK                    0x1u
#define IOMUXC_PTA11_IBE_SHIFT                   0
#define IOMUXC_PTA11_OBE_MASK                    0x2u
#define IOMUXC_PTA11_OBE_SHIFT                   1
#define IOMUXC_PTA11_PUE_MASK                    0x4u
#define IOMUXC_PTA11_PUE_SHIFT                   2
#define IOMUXC_PTA11_PKE_MASK                    0x8u
#define IOMUXC_PTA11_PKE_SHIFT                   3
#define IOMUXC_PTA11_PUS_MASK                    0x30u
#define IOMUXC_PTA11_PUS_SHIFT                   4
#define IOMUXC_PTA11_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA11_PUS_SHIFT))&IOMUXC_PTA11_PUS_MASK)
#define IOMUXC_PTA11_DSE_MASK                    0x1C0u
#define IOMUXC_PTA11_DSE_SHIFT                   6
#define IOMUXC_PTA11_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA11_DSE_SHIFT))&IOMUXC_PTA11_DSE_MASK)
#define IOMUXC_PTA11_HYS_MASK                    0x200u
#define IOMUXC_PTA11_HYS_SHIFT                   9
#define IOMUXC_PTA11_ODE_MASK                    0x400u
#define IOMUXC_PTA11_ODE_SHIFT                   10
#define IOMUXC_PTA11_SRE_MASK                    0x800u
#define IOMUXC_PTA11_SRE_SHIFT                   11
#define IOMUXC_PTA11_SPEED_MASK                  0x3000u
#define IOMUXC_PTA11_SPEED_SHIFT                 12
#define IOMUXC_PTA11_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA11_SPEED_SHIFT))&IOMUXC_PTA11_SPEED_MASK)
#define IOMUXC_PTA11_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA11_MUX_MODE_SHIFT              20
#define IOMUXC_PTA11_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA11_MUX_MODE_SHIFT))&IOMUXC_PTA11_MUX_MODE_MASK)
/* PTA12 Bit Fields */
#define IOMUXC_PTA12_IBE_MASK                    0x1u
#define IOMUXC_PTA12_IBE_SHIFT                   0
#define IOMUXC_PTA12_OBE_MASK                    0x2u
#define IOMUXC_PTA12_OBE_SHIFT                   1
#define IOMUXC_PTA12_PUE_MASK                    0x4u
#define IOMUXC_PTA12_PUE_SHIFT                   2
#define IOMUXC_PTA12_PKE_MASK                    0x8u
#define IOMUXC_PTA12_PKE_SHIFT                   3
#define IOMUXC_PTA12_PUS_MASK                    0x30u
#define IOMUXC_PTA12_PUS_SHIFT                   4
#define IOMUXC_PTA12_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA12_PUS_SHIFT))&IOMUXC_PTA12_PUS_MASK)
#define IOMUXC_PTA12_DSE_MASK                    0x1C0u
#define IOMUXC_PTA12_DSE_SHIFT                   6
#define IOMUXC_PTA12_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA12_DSE_SHIFT))&IOMUXC_PTA12_DSE_MASK)
#define IOMUXC_PTA12_HYS_MASK                    0x200u
#define IOMUXC_PTA12_HYS_SHIFT                   9
#define IOMUXC_PTA12_ODE_MASK                    0x400u
#define IOMUXC_PTA12_ODE_SHIFT                   10
#define IOMUXC_PTA12_SRE_MASK                    0x800u
#define IOMUXC_PTA12_SRE_SHIFT                   11
#define IOMUXC_PTA12_SPEED_MASK                  0x3000u
#define IOMUXC_PTA12_SPEED_SHIFT                 12
#define IOMUXC_PTA12_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA12_SPEED_SHIFT))&IOMUXC_PTA12_SPEED_MASK)
#define IOMUXC_PTA12_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA12_MUX_MODE_SHIFT              20
#define IOMUXC_PTA12_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA12_MUX_MODE_SHIFT))&IOMUXC_PTA12_MUX_MODE_MASK)
/* PTA16 Bit Fields */
#define IOMUXC_PTA16_IBE_MASK                    0x1u
#define IOMUXC_PTA16_IBE_SHIFT                   0
#define IOMUXC_PTA16_OBE_MASK                    0x2u
#define IOMUXC_PTA16_OBE_SHIFT                   1
#define IOMUXC_PTA16_PUE_MASK                    0x4u
#define IOMUXC_PTA16_PUE_SHIFT                   2
#define IOMUXC_PTA16_PKE_MASK                    0x8u
#define IOMUXC_PTA16_PKE_SHIFT                   3
#define IOMUXC_PTA16_PUS_MASK                    0x30u
#define IOMUXC_PTA16_PUS_SHIFT                   4
#define IOMUXC_PTA16_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA16_PUS_SHIFT))&IOMUXC_PTA16_PUS_MASK)
#define IOMUXC_PTA16_DSE_MASK                    0x1C0u
#define IOMUXC_PTA16_DSE_SHIFT                   6
#define IOMUXC_PTA16_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA16_DSE_SHIFT))&IOMUXC_PTA16_DSE_MASK)
#define IOMUXC_PTA16_HYS_MASK                    0x200u
#define IOMUXC_PTA16_HYS_SHIFT                   9
#define IOMUXC_PTA16_ODE_MASK                    0x400u
#define IOMUXC_PTA16_ODE_SHIFT                   10
#define IOMUXC_PTA16_SRE_MASK                    0x800u
#define IOMUXC_PTA16_SRE_SHIFT                   11
#define IOMUXC_PTA16_SPEED_MASK                  0x3000u
#define IOMUXC_PTA16_SPEED_SHIFT                 12
#define IOMUXC_PTA16_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA16_SPEED_SHIFT))&IOMUXC_PTA16_SPEED_MASK)
#define IOMUXC_PTA16_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA16_MUX_MODE_SHIFT              20
#define IOMUXC_PTA16_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA16_MUX_MODE_SHIFT))&IOMUXC_PTA16_MUX_MODE_MASK)
/* PTA17 Bit Fields */
#define IOMUXC_PTA17_IBE_MASK                    0x1u
#define IOMUXC_PTA17_IBE_SHIFT                   0
#define IOMUXC_PTA17_OBE_MASK                    0x2u
#define IOMUXC_PTA17_OBE_SHIFT                   1
#define IOMUXC_PTA17_PUE_MASK                    0x4u
#define IOMUXC_PTA17_PUE_SHIFT                   2
#define IOMUXC_PTA17_PKE_MASK                    0x8u
#define IOMUXC_PTA17_PKE_SHIFT                   3
#define IOMUXC_PTA17_PUS_MASK                    0x30u
#define IOMUXC_PTA17_PUS_SHIFT                   4
#define IOMUXC_PTA17_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA17_PUS_SHIFT))&IOMUXC_PTA17_PUS_MASK)
#define IOMUXC_PTA17_DSE_MASK                    0x1C0u
#define IOMUXC_PTA17_DSE_SHIFT                   6
#define IOMUXC_PTA17_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA17_DSE_SHIFT))&IOMUXC_PTA17_DSE_MASK)
#define IOMUXC_PTA17_HYS_MASK                    0x200u
#define IOMUXC_PTA17_HYS_SHIFT                   9
#define IOMUXC_PTA17_ODE_MASK                    0x400u
#define IOMUXC_PTA17_ODE_SHIFT                   10
#define IOMUXC_PTA17_SRE_MASK                    0x800u
#define IOMUXC_PTA17_SRE_SHIFT                   11
#define IOMUXC_PTA17_SPEED_MASK                  0x3000u
#define IOMUXC_PTA17_SPEED_SHIFT                 12
#define IOMUXC_PTA17_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA17_SPEED_SHIFT))&IOMUXC_PTA17_SPEED_MASK)
#define IOMUXC_PTA17_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA17_MUX_MODE_SHIFT              20
#define IOMUXC_PTA17_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA17_MUX_MODE_SHIFT))&IOMUXC_PTA17_MUX_MODE_MASK)
/* PTA18 Bit Fields */
#define IOMUXC_PTA18_IBE_MASK                    0x1u
#define IOMUXC_PTA18_IBE_SHIFT                   0
#define IOMUXC_PTA18_OBE_MASK                    0x2u
#define IOMUXC_PTA18_OBE_SHIFT                   1
#define IOMUXC_PTA18_PUE_MASK                    0x4u
#define IOMUXC_PTA18_PUE_SHIFT                   2
#define IOMUXC_PTA18_PKE_MASK                    0x8u
#define IOMUXC_PTA18_PKE_SHIFT                   3
#define IOMUXC_PTA18_PUS_MASK                    0x30u
#define IOMUXC_PTA18_PUS_SHIFT                   4
#define IOMUXC_PTA18_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA18_PUS_SHIFT))&IOMUXC_PTA18_PUS_MASK)
#define IOMUXC_PTA18_DSE_MASK                    0x1C0u
#define IOMUXC_PTA18_DSE_SHIFT                   6
#define IOMUXC_PTA18_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA18_DSE_SHIFT))&IOMUXC_PTA18_DSE_MASK)
#define IOMUXC_PTA18_HYS_MASK                    0x200u
#define IOMUXC_PTA18_HYS_SHIFT                   9
#define IOMUXC_PTA18_ODE_MASK                    0x400u
#define IOMUXC_PTA18_ODE_SHIFT                   10
#define IOMUXC_PTA18_SRE_MASK                    0x800u
#define IOMUXC_PTA18_SRE_SHIFT                   11
#define IOMUXC_PTA18_SPEED_MASK                  0x3000u
#define IOMUXC_PTA18_SPEED_SHIFT                 12
#define IOMUXC_PTA18_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA18_SPEED_SHIFT))&IOMUXC_PTA18_SPEED_MASK)
#define IOMUXC_PTA18_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA18_MUX_MODE_SHIFT              20
#define IOMUXC_PTA18_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA18_MUX_MODE_SHIFT))&IOMUXC_PTA18_MUX_MODE_MASK)
/* PTA19 Bit Fields */
#define IOMUXC_PTA19_IBE_MASK                    0x1u
#define IOMUXC_PTA19_IBE_SHIFT                   0
#define IOMUXC_PTA19_OBE_MASK                    0x2u
#define IOMUXC_PTA19_OBE_SHIFT                   1
#define IOMUXC_PTA19_PUE_MASK                    0x4u
#define IOMUXC_PTA19_PUE_SHIFT                   2
#define IOMUXC_PTA19_PKE_MASK                    0x8u
#define IOMUXC_PTA19_PKE_SHIFT                   3
#define IOMUXC_PTA19_PUS_MASK                    0x30u
#define IOMUXC_PTA19_PUS_SHIFT                   4
#define IOMUXC_PTA19_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA19_PUS_SHIFT))&IOMUXC_PTA19_PUS_MASK)
#define IOMUXC_PTA19_DSE_MASK                    0x1C0u
#define IOMUXC_PTA19_DSE_SHIFT                   6
#define IOMUXC_PTA19_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA19_DSE_SHIFT))&IOMUXC_PTA19_DSE_MASK)
#define IOMUXC_PTA19_HYS_MASK                    0x200u
#define IOMUXC_PTA19_HYS_SHIFT                   9
#define IOMUXC_PTA19_ODE_MASK                    0x400u
#define IOMUXC_PTA19_ODE_SHIFT                   10
#define IOMUXC_PTA19_SRE_MASK                    0x800u
#define IOMUXC_PTA19_SRE_SHIFT                   11
#define IOMUXC_PTA19_SPEED_MASK                  0x3000u
#define IOMUXC_PTA19_SPEED_SHIFT                 12
#define IOMUXC_PTA19_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA19_SPEED_SHIFT))&IOMUXC_PTA19_SPEED_MASK)
#define IOMUXC_PTA19_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA19_MUX_MODE_SHIFT              20
#define IOMUXC_PTA19_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA19_MUX_MODE_SHIFT))&IOMUXC_PTA19_MUX_MODE_MASK)
/* PTA20 Bit Fields */
#define IOMUXC_PTA20_IBE_MASK                    0x1u
#define IOMUXC_PTA20_IBE_SHIFT                   0
#define IOMUXC_PTA20_OBE_MASK                    0x2u
#define IOMUXC_PTA20_OBE_SHIFT                   1
#define IOMUXC_PTA20_PUE_MASK                    0x4u
#define IOMUXC_PTA20_PUE_SHIFT                   2
#define IOMUXC_PTA20_PKE_MASK                    0x8u
#define IOMUXC_PTA20_PKE_SHIFT                   3
#define IOMUXC_PTA20_PUS_MASK                    0x30u
#define IOMUXC_PTA20_PUS_SHIFT                   4
#define IOMUXC_PTA20_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA20_PUS_SHIFT))&IOMUXC_PTA20_PUS_MASK)
#define IOMUXC_PTA20_DSE_MASK                    0x1C0u
#define IOMUXC_PTA20_DSE_SHIFT                   6
#define IOMUXC_PTA20_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA20_DSE_SHIFT))&IOMUXC_PTA20_DSE_MASK)
#define IOMUXC_PTA20_HYS_MASK                    0x200u
#define IOMUXC_PTA20_HYS_SHIFT                   9
#define IOMUXC_PTA20_ODE_MASK                    0x400u
#define IOMUXC_PTA20_ODE_SHIFT                   10
#define IOMUXC_PTA20_SRE_MASK                    0x800u
#define IOMUXC_PTA20_SRE_SHIFT                   11
#define IOMUXC_PTA20_SPEED_MASK                  0x3000u
#define IOMUXC_PTA20_SPEED_SHIFT                 12
#define IOMUXC_PTA20_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA20_SPEED_SHIFT))&IOMUXC_PTA20_SPEED_MASK)
#define IOMUXC_PTA20_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA20_MUX_MODE_SHIFT              20
#define IOMUXC_PTA20_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA20_MUX_MODE_SHIFT))&IOMUXC_PTA20_MUX_MODE_MASK)
/* PTA21 Bit Fields */
#define IOMUXC_PTA21_IBE_MASK                    0x1u
#define IOMUXC_PTA21_IBE_SHIFT                   0
#define IOMUXC_PTA21_OBE_MASK                    0x2u
#define IOMUXC_PTA21_OBE_SHIFT                   1
#define IOMUXC_PTA21_PUE_MASK                    0x4u
#define IOMUXC_PTA21_PUE_SHIFT                   2
#define IOMUXC_PTA21_PKE_MASK                    0x8u
#define IOMUXC_PTA21_PKE_SHIFT                   3
#define IOMUXC_PTA21_PUS_MASK                    0x30u
#define IOMUXC_PTA21_PUS_SHIFT                   4
#define IOMUXC_PTA21_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA21_PUS_SHIFT))&IOMUXC_PTA21_PUS_MASK)
#define IOMUXC_PTA21_DSE_MASK                    0x1C0u
#define IOMUXC_PTA21_DSE_SHIFT                   6
#define IOMUXC_PTA21_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA21_DSE_SHIFT))&IOMUXC_PTA21_DSE_MASK)
#define IOMUXC_PTA21_HYS_MASK                    0x200u
#define IOMUXC_PTA21_HYS_SHIFT                   9
#define IOMUXC_PTA21_ODE_MASK                    0x400u
#define IOMUXC_PTA21_ODE_SHIFT                   10
#define IOMUXC_PTA21_SRE_MASK                    0x800u
#define IOMUXC_PTA21_SRE_SHIFT                   11
#define IOMUXC_PTA21_SPEED_MASK                  0x3000u
#define IOMUXC_PTA21_SPEED_SHIFT                 12
#define IOMUXC_PTA21_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA21_SPEED_SHIFT))&IOMUXC_PTA21_SPEED_MASK)
#define IOMUXC_PTA21_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA21_MUX_MODE_SHIFT              20
#define IOMUXC_PTA21_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA21_MUX_MODE_SHIFT))&IOMUXC_PTA21_MUX_MODE_MASK)
/* PTA22 Bit Fields */
#define IOMUXC_PTA22_IBE_MASK                    0x1u
#define IOMUXC_PTA22_IBE_SHIFT                   0
#define IOMUXC_PTA22_OBE_MASK                    0x2u
#define IOMUXC_PTA22_OBE_SHIFT                   1
#define IOMUXC_PTA22_PUE_MASK                    0x4u
#define IOMUXC_PTA22_PUE_SHIFT                   2
#define IOMUXC_PTA22_PKE_MASK                    0x8u
#define IOMUXC_PTA22_PKE_SHIFT                   3
#define IOMUXC_PTA22_PUS_MASK                    0x30u
#define IOMUXC_PTA22_PUS_SHIFT                   4
#define IOMUXC_PTA22_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA22_PUS_SHIFT))&IOMUXC_PTA22_PUS_MASK)
#define IOMUXC_PTA22_DSE_MASK                    0x1C0u
#define IOMUXC_PTA22_DSE_SHIFT                   6
#define IOMUXC_PTA22_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA22_DSE_SHIFT))&IOMUXC_PTA22_DSE_MASK)
#define IOMUXC_PTA22_HYS_MASK                    0x200u
#define IOMUXC_PTA22_HYS_SHIFT                   9
#define IOMUXC_PTA22_ODE_MASK                    0x400u
#define IOMUXC_PTA22_ODE_SHIFT                   10
#define IOMUXC_PTA22_SRE_MASK                    0x800u
#define IOMUXC_PTA22_SRE_SHIFT                   11
#define IOMUXC_PTA22_SPEED_MASK                  0x3000u
#define IOMUXC_PTA22_SPEED_SHIFT                 12
#define IOMUXC_PTA22_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA22_SPEED_SHIFT))&IOMUXC_PTA22_SPEED_MASK)
#define IOMUXC_PTA22_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA22_MUX_MODE_SHIFT              20
#define IOMUXC_PTA22_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA22_MUX_MODE_SHIFT))&IOMUXC_PTA22_MUX_MODE_MASK)
/* PTA23 Bit Fields */
#define IOMUXC_PTA23_IBE_MASK                    0x1u
#define IOMUXC_PTA23_IBE_SHIFT                   0
#define IOMUXC_PTA23_OBE_MASK                    0x2u
#define IOMUXC_PTA23_OBE_SHIFT                   1
#define IOMUXC_PTA23_PUE_MASK                    0x4u
#define IOMUXC_PTA23_PUE_SHIFT                   2
#define IOMUXC_PTA23_PKE_MASK                    0x8u
#define IOMUXC_PTA23_PKE_SHIFT                   3
#define IOMUXC_PTA23_PUS_MASK                    0x30u
#define IOMUXC_PTA23_PUS_SHIFT                   4
#define IOMUXC_PTA23_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA23_PUS_SHIFT))&IOMUXC_PTA23_PUS_MASK)
#define IOMUXC_PTA23_DSE_MASK                    0x1C0u
#define IOMUXC_PTA23_DSE_SHIFT                   6
#define IOMUXC_PTA23_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA23_DSE_SHIFT))&IOMUXC_PTA23_DSE_MASK)
#define IOMUXC_PTA23_HYS_MASK                    0x200u
#define IOMUXC_PTA23_HYS_SHIFT                   9
#define IOMUXC_PTA23_ODE_MASK                    0x400u
#define IOMUXC_PTA23_ODE_SHIFT                   10
#define IOMUXC_PTA23_SRE_MASK                    0x800u
#define IOMUXC_PTA23_SRE_SHIFT                   11
#define IOMUXC_PTA23_SPEED_MASK                  0x3000u
#define IOMUXC_PTA23_SPEED_SHIFT                 12
#define IOMUXC_PTA23_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA23_SPEED_SHIFT))&IOMUXC_PTA23_SPEED_MASK)
#define IOMUXC_PTA23_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA23_MUX_MODE_SHIFT              20
#define IOMUXC_PTA23_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA23_MUX_MODE_SHIFT))&IOMUXC_PTA23_MUX_MODE_MASK)
/* PTA24 Bit Fields */
#define IOMUXC_PTA24_IBE_MASK                    0x1u
#define IOMUXC_PTA24_IBE_SHIFT                   0
#define IOMUXC_PTA24_OBE_MASK                    0x2u
#define IOMUXC_PTA24_OBE_SHIFT                   1
#define IOMUXC_PTA24_PUE_MASK                    0x4u
#define IOMUXC_PTA24_PUE_SHIFT                   2
#define IOMUXC_PTA24_PKE_MASK                    0x8u
#define IOMUXC_PTA24_PKE_SHIFT                   3
#define IOMUXC_PTA24_PUS_MASK                    0x30u
#define IOMUXC_PTA24_PUS_SHIFT                   4
#define IOMUXC_PTA24_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA24_PUS_SHIFT))&IOMUXC_PTA24_PUS_MASK)
#define IOMUXC_PTA24_DSE_MASK                    0x1C0u
#define IOMUXC_PTA24_DSE_SHIFT                   6
#define IOMUXC_PTA24_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA24_DSE_SHIFT))&IOMUXC_PTA24_DSE_MASK)
#define IOMUXC_PTA24_HYS_MASK                    0x200u
#define IOMUXC_PTA24_HYS_SHIFT                   9
#define IOMUXC_PTA24_ODE_MASK                    0x400u
#define IOMUXC_PTA24_ODE_SHIFT                   10
#define IOMUXC_PTA24_SRE_MASK                    0x800u
#define IOMUXC_PTA24_SRE_SHIFT                   11
#define IOMUXC_PTA24_SPEED_MASK                  0x3000u
#define IOMUXC_PTA24_SPEED_SHIFT                 12
#define IOMUXC_PTA24_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA24_SPEED_SHIFT))&IOMUXC_PTA24_SPEED_MASK)
#define IOMUXC_PTA24_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA24_MUX_MODE_SHIFT              20
#define IOMUXC_PTA24_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA24_MUX_MODE_SHIFT))&IOMUXC_PTA24_MUX_MODE_MASK)
/* PTA25 Bit Fields */
#define IOMUXC_PTA25_IBE_MASK                    0x1u
#define IOMUXC_PTA25_IBE_SHIFT                   0
#define IOMUXC_PTA25_OBE_MASK                    0x2u
#define IOMUXC_PTA25_OBE_SHIFT                   1
#define IOMUXC_PTA25_PUE_MASK                    0x4u
#define IOMUXC_PTA25_PUE_SHIFT                   2
#define IOMUXC_PTA25_PKE_MASK                    0x8u
#define IOMUXC_PTA25_PKE_SHIFT                   3
#define IOMUXC_PTA25_PUS_MASK                    0x30u
#define IOMUXC_PTA25_PUS_SHIFT                   4
#define IOMUXC_PTA25_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA25_PUS_SHIFT))&IOMUXC_PTA25_PUS_MASK)
#define IOMUXC_PTA25_DSE_MASK                    0x1C0u
#define IOMUXC_PTA25_DSE_SHIFT                   6
#define IOMUXC_PTA25_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA25_DSE_SHIFT))&IOMUXC_PTA25_DSE_MASK)
#define IOMUXC_PTA25_HYS_MASK                    0x200u
#define IOMUXC_PTA25_HYS_SHIFT                   9
#define IOMUXC_PTA25_ODE_MASK                    0x400u
#define IOMUXC_PTA25_ODE_SHIFT                   10
#define IOMUXC_PTA25_SRE_MASK                    0x800u
#define IOMUXC_PTA25_SRE_SHIFT                   11
#define IOMUXC_PTA25_SPEED_MASK                  0x3000u
#define IOMUXC_PTA25_SPEED_SHIFT                 12
#define IOMUXC_PTA25_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA25_SPEED_SHIFT))&IOMUXC_PTA25_SPEED_MASK)
#define IOMUXC_PTA25_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA25_MUX_MODE_SHIFT              20
#define IOMUXC_PTA25_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA25_MUX_MODE_SHIFT))&IOMUXC_PTA25_MUX_MODE_MASK)
/* PTA26 Bit Fields */
#define IOMUXC_PTA26_IBE_MASK                    0x1u
#define IOMUXC_PTA26_IBE_SHIFT                   0
#define IOMUXC_PTA26_OBE_MASK                    0x2u
#define IOMUXC_PTA26_OBE_SHIFT                   1
#define IOMUXC_PTA26_PUE_MASK                    0x4u
#define IOMUXC_PTA26_PUE_SHIFT                   2
#define IOMUXC_PTA26_PKE_MASK                    0x8u
#define IOMUXC_PTA26_PKE_SHIFT                   3
#define IOMUXC_PTA26_PUS_MASK                    0x30u
#define IOMUXC_PTA26_PUS_SHIFT                   4
#define IOMUXC_PTA26_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA26_PUS_SHIFT))&IOMUXC_PTA26_PUS_MASK)
#define IOMUXC_PTA26_DSE_MASK                    0x1C0u
#define IOMUXC_PTA26_DSE_SHIFT                   6
#define IOMUXC_PTA26_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA26_DSE_SHIFT))&IOMUXC_PTA26_DSE_MASK)
#define IOMUXC_PTA26_HYS_MASK                    0x200u
#define IOMUXC_PTA26_HYS_SHIFT                   9
#define IOMUXC_PTA26_ODE_MASK                    0x400u
#define IOMUXC_PTA26_ODE_SHIFT                   10
#define IOMUXC_PTA26_SRE_MASK                    0x800u
#define IOMUXC_PTA26_SRE_SHIFT                   11
#define IOMUXC_PTA26_SPEED_MASK                  0x3000u
#define IOMUXC_PTA26_SPEED_SHIFT                 12
#define IOMUXC_PTA26_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA26_SPEED_SHIFT))&IOMUXC_PTA26_SPEED_MASK)
#define IOMUXC_PTA26_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA26_MUX_MODE_SHIFT              20
#define IOMUXC_PTA26_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA26_MUX_MODE_SHIFT))&IOMUXC_PTA26_MUX_MODE_MASK)
/* PTA27 Bit Fields */
#define IOMUXC_PTA27_IBE_MASK                    0x1u
#define IOMUXC_PTA27_IBE_SHIFT                   0
#define IOMUXC_PTA27_OBE_MASK                    0x2u
#define IOMUXC_PTA27_OBE_SHIFT                   1
#define IOMUXC_PTA27_PUE_MASK                    0x4u
#define IOMUXC_PTA27_PUE_SHIFT                   2
#define IOMUXC_PTA27_PKE_MASK                    0x8u
#define IOMUXC_PTA27_PKE_SHIFT                   3
#define IOMUXC_PTA27_PUS_MASK                    0x30u
#define IOMUXC_PTA27_PUS_SHIFT                   4
#define IOMUXC_PTA27_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA27_PUS_SHIFT))&IOMUXC_PTA27_PUS_MASK)
#define IOMUXC_PTA27_DSE_MASK                    0x1C0u
#define IOMUXC_PTA27_DSE_SHIFT                   6
#define IOMUXC_PTA27_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA27_DSE_SHIFT))&IOMUXC_PTA27_DSE_MASK)
#define IOMUXC_PTA27_HYS_MASK                    0x200u
#define IOMUXC_PTA27_HYS_SHIFT                   9
#define IOMUXC_PTA27_ODE_MASK                    0x400u
#define IOMUXC_PTA27_ODE_SHIFT                   10
#define IOMUXC_PTA27_SRE_MASK                    0x800u
#define IOMUXC_PTA27_SRE_SHIFT                   11
#define IOMUXC_PTA27_SPEED_MASK                  0x3000u
#define IOMUXC_PTA27_SPEED_SHIFT                 12
#define IOMUXC_PTA27_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA27_SPEED_SHIFT))&IOMUXC_PTA27_SPEED_MASK)
#define IOMUXC_PTA27_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA27_MUX_MODE_SHIFT              20
#define IOMUXC_PTA27_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA27_MUX_MODE_SHIFT))&IOMUXC_PTA27_MUX_MODE_MASK)
/* PTA28 Bit Fields */
#define IOMUXC_PTA28_IBE_MASK                    0x1u
#define IOMUXC_PTA28_IBE_SHIFT                   0
#define IOMUXC_PTA28_OBE_MASK                    0x2u
#define IOMUXC_PTA28_OBE_SHIFT                   1
#define IOMUXC_PTA28_PUE_MASK                    0x4u
#define IOMUXC_PTA28_PUE_SHIFT                   2
#define IOMUXC_PTA28_PKE_MASK                    0x8u
#define IOMUXC_PTA28_PKE_SHIFT                   3
#define IOMUXC_PTA28_PUS_MASK                    0x30u
#define IOMUXC_PTA28_PUS_SHIFT                   4
#define IOMUXC_PTA28_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA28_PUS_SHIFT))&IOMUXC_PTA28_PUS_MASK)
#define IOMUXC_PTA28_DSE_MASK                    0x1C0u
#define IOMUXC_PTA28_DSE_SHIFT                   6
#define IOMUXC_PTA28_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA28_DSE_SHIFT))&IOMUXC_PTA28_DSE_MASK)
#define IOMUXC_PTA28_HYS_MASK                    0x200u
#define IOMUXC_PTA28_HYS_SHIFT                   9
#define IOMUXC_PTA28_ODE_MASK                    0x400u
#define IOMUXC_PTA28_ODE_SHIFT                   10
#define IOMUXC_PTA28_SRE_MASK                    0x800u
#define IOMUXC_PTA28_SRE_SHIFT                   11
#define IOMUXC_PTA28_SPEED_MASK                  0x3000u
#define IOMUXC_PTA28_SPEED_SHIFT                 12
#define IOMUXC_PTA28_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA28_SPEED_SHIFT))&IOMUXC_PTA28_SPEED_MASK)
#define IOMUXC_PTA28_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA28_MUX_MODE_SHIFT              20
#define IOMUXC_PTA28_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA28_MUX_MODE_SHIFT))&IOMUXC_PTA28_MUX_MODE_MASK)
/* PTA29 Bit Fields */
#define IOMUXC_PTA29_IBE_MASK                    0x1u
#define IOMUXC_PTA29_IBE_SHIFT                   0
#define IOMUXC_PTA29_OBE_MASK                    0x2u
#define IOMUXC_PTA29_OBE_SHIFT                   1
#define IOMUXC_PTA29_PUE_MASK                    0x4u
#define IOMUXC_PTA29_PUE_SHIFT                   2
#define IOMUXC_PTA29_PKE_MASK                    0x8u
#define IOMUXC_PTA29_PKE_SHIFT                   3
#define IOMUXC_PTA29_PUS_MASK                    0x30u
#define IOMUXC_PTA29_PUS_SHIFT                   4
#define IOMUXC_PTA29_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA29_PUS_SHIFT))&IOMUXC_PTA29_PUS_MASK)
#define IOMUXC_PTA29_DSE_MASK                    0x1C0u
#define IOMUXC_PTA29_DSE_SHIFT                   6
#define IOMUXC_PTA29_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA29_DSE_SHIFT))&IOMUXC_PTA29_DSE_MASK)
#define IOMUXC_PTA29_HYS_MASK                    0x200u
#define IOMUXC_PTA29_HYS_SHIFT                   9
#define IOMUXC_PTA29_ODE_MASK                    0x400u
#define IOMUXC_PTA29_ODE_SHIFT                   10
#define IOMUXC_PTA29_SRE_MASK                    0x800u
#define IOMUXC_PTA29_SRE_SHIFT                   11
#define IOMUXC_PTA29_SPEED_MASK                  0x3000u
#define IOMUXC_PTA29_SPEED_SHIFT                 12
#define IOMUXC_PTA29_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA29_SPEED_SHIFT))&IOMUXC_PTA29_SPEED_MASK)
#define IOMUXC_PTA29_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA29_MUX_MODE_SHIFT              20
#define IOMUXC_PTA29_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA29_MUX_MODE_SHIFT))&IOMUXC_PTA29_MUX_MODE_MASK)
/* PTA30 Bit Fields */
#define IOMUXC_PTA30_IBE_MASK                    0x1u
#define IOMUXC_PTA30_IBE_SHIFT                   0
#define IOMUXC_PTA30_OBE_MASK                    0x2u
#define IOMUXC_PTA30_OBE_SHIFT                   1
#define IOMUXC_PTA30_PUE_MASK                    0x4u
#define IOMUXC_PTA30_PUE_SHIFT                   2
#define IOMUXC_PTA30_PKE_MASK                    0x8u
#define IOMUXC_PTA30_PKE_SHIFT                   3
#define IOMUXC_PTA30_PUS_MASK                    0x30u
#define IOMUXC_PTA30_PUS_SHIFT                   4
#define IOMUXC_PTA30_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA30_PUS_SHIFT))&IOMUXC_PTA30_PUS_MASK)
#define IOMUXC_PTA30_DSE_MASK                    0x1C0u
#define IOMUXC_PTA30_DSE_SHIFT                   6
#define IOMUXC_PTA30_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA30_DSE_SHIFT))&IOMUXC_PTA30_DSE_MASK)
#define IOMUXC_PTA30_HYS_MASK                    0x200u
#define IOMUXC_PTA30_HYS_SHIFT                   9
#define IOMUXC_PTA30_ODE_MASK                    0x400u
#define IOMUXC_PTA30_ODE_SHIFT                   10
#define IOMUXC_PTA30_SRE_MASK                    0x800u
#define IOMUXC_PTA30_SRE_SHIFT                   11
#define IOMUXC_PTA30_SPEED_MASK                  0x3000u
#define IOMUXC_PTA30_SPEED_SHIFT                 12
#define IOMUXC_PTA30_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA30_SPEED_SHIFT))&IOMUXC_PTA30_SPEED_MASK)
#define IOMUXC_PTA30_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA30_MUX_MODE_SHIFT              20
#define IOMUXC_PTA30_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA30_MUX_MODE_SHIFT))&IOMUXC_PTA30_MUX_MODE_MASK)
/* PTA31 Bit Fields */
#define IOMUXC_PTA31_IBE_MASK                    0x1u
#define IOMUXC_PTA31_IBE_SHIFT                   0
#define IOMUXC_PTA31_OBE_MASK                    0x2u
#define IOMUXC_PTA31_OBE_SHIFT                   1
#define IOMUXC_PTA31_PUE_MASK                    0x4u
#define IOMUXC_PTA31_PUE_SHIFT                   2
#define IOMUXC_PTA31_PKE_MASK                    0x8u
#define IOMUXC_PTA31_PKE_SHIFT                   3
#define IOMUXC_PTA31_PUS_MASK                    0x30u
#define IOMUXC_PTA31_PUS_SHIFT                   4
#define IOMUXC_PTA31_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA31_PUS_SHIFT))&IOMUXC_PTA31_PUS_MASK)
#define IOMUXC_PTA31_DSE_MASK                    0x1C0u
#define IOMUXC_PTA31_DSE_SHIFT                   6
#define IOMUXC_PTA31_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA31_DSE_SHIFT))&IOMUXC_PTA31_DSE_MASK)
#define IOMUXC_PTA31_HYS_MASK                    0x200u
#define IOMUXC_PTA31_HYS_SHIFT                   9
#define IOMUXC_PTA31_ODE_MASK                    0x400u
#define IOMUXC_PTA31_ODE_SHIFT                   10
#define IOMUXC_PTA31_SRE_MASK                    0x800u
#define IOMUXC_PTA31_SRE_SHIFT                   11
#define IOMUXC_PTA31_SPEED_MASK                  0x3000u
#define IOMUXC_PTA31_SPEED_SHIFT                 12
#define IOMUXC_PTA31_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA31_SPEED_SHIFT))&IOMUXC_PTA31_SPEED_MASK)
#define IOMUXC_PTA31_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTA31_MUX_MODE_SHIFT              20
#define IOMUXC_PTA31_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA31_MUX_MODE_SHIFT))&IOMUXC_PTA31_MUX_MODE_MASK)
/* PTB0 Bit Fields */
#define IOMUXC_PTB0_IBE_MASK                     0x1u
#define IOMUXC_PTB0_IBE_SHIFT                    0
#define IOMUXC_PTB0_OBE_MASK                     0x2u
#define IOMUXC_PTB0_OBE_SHIFT                    1
#define IOMUXC_PTB0_PUE_MASK                     0x4u
#define IOMUXC_PTB0_PUE_SHIFT                    2
#define IOMUXC_PTB0_PKE_MASK                     0x8u
#define IOMUXC_PTB0_PKE_SHIFT                    3
#define IOMUXC_PTB0_PUS_MASK                     0x30u
#define IOMUXC_PTB0_PUS_SHIFT                    4
#define IOMUXC_PTB0_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB0_PUS_SHIFT))&IOMUXC_PTB0_PUS_MASK)
#define IOMUXC_PTB0_DSE_MASK                     0x1C0u
#define IOMUXC_PTB0_DSE_SHIFT                    6
#define IOMUXC_PTB0_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB0_DSE_SHIFT))&IOMUXC_PTB0_DSE_MASK)
#define IOMUXC_PTB0_HYS_MASK                     0x200u
#define IOMUXC_PTB0_HYS_SHIFT                    9
#define IOMUXC_PTB0_ODE_MASK                     0x400u
#define IOMUXC_PTB0_ODE_SHIFT                    10
#define IOMUXC_PTB0_SRE_MASK                     0x800u
#define IOMUXC_PTB0_SRE_SHIFT                    11
#define IOMUXC_PTB0_SPEED_MASK                   0x3000u
#define IOMUXC_PTB0_SPEED_SHIFT                  12
#define IOMUXC_PTB0_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB0_SPEED_SHIFT))&IOMUXC_PTB0_SPEED_MASK)
#define IOMUXC_PTB0_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB0_MUX_MODE_SHIFT               20
#define IOMUXC_PTB0_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB0_MUX_MODE_SHIFT))&IOMUXC_PTB0_MUX_MODE_MASK)
/* PTB1 Bit Fields */
#define IOMUXC_PTB1_IBE_MASK                     0x1u
#define IOMUXC_PTB1_IBE_SHIFT                    0
#define IOMUXC_PTB1_OBE_MASK                     0x2u
#define IOMUXC_PTB1_OBE_SHIFT                    1
#define IOMUXC_PTB1_PUE_MASK                     0x4u
#define IOMUXC_PTB1_PUE_SHIFT                    2
#define IOMUXC_PTB1_PKE_MASK                     0x8u
#define IOMUXC_PTB1_PKE_SHIFT                    3
#define IOMUXC_PTB1_PUS_MASK                     0x30u
#define IOMUXC_PTB1_PUS_SHIFT                    4
#define IOMUXC_PTB1_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB1_PUS_SHIFT))&IOMUXC_PTB1_PUS_MASK)
#define IOMUXC_PTB1_DSE_MASK                     0x1C0u
#define IOMUXC_PTB1_DSE_SHIFT                    6
#define IOMUXC_PTB1_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB1_DSE_SHIFT))&IOMUXC_PTB1_DSE_MASK)
#define IOMUXC_PTB1_HYS_MASK                     0x200u
#define IOMUXC_PTB1_HYS_SHIFT                    9
#define IOMUXC_PTB1_ODE_MASK                     0x400u
#define IOMUXC_PTB1_ODE_SHIFT                    10
#define IOMUXC_PTB1_SRE_MASK                     0x800u
#define IOMUXC_PTB1_SRE_SHIFT                    11
#define IOMUXC_PTB1_SPEED_MASK                   0x3000u
#define IOMUXC_PTB1_SPEED_SHIFT                  12
#define IOMUXC_PTB1_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB1_SPEED_SHIFT))&IOMUXC_PTB1_SPEED_MASK)
#define IOMUXC_PTB1_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB1_MUX_MODE_SHIFT               20
#define IOMUXC_PTB1_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB1_MUX_MODE_SHIFT))&IOMUXC_PTB1_MUX_MODE_MASK)
/* PTB2 Bit Fields */
#define IOMUXC_PTB2_IBE_MASK                     0x1u
#define IOMUXC_PTB2_IBE_SHIFT                    0
#define IOMUXC_PTB2_OBE_MASK                     0x2u
#define IOMUXC_PTB2_OBE_SHIFT                    1
#define IOMUXC_PTB2_PUE_MASK                     0x4u
#define IOMUXC_PTB2_PUE_SHIFT                    2
#define IOMUXC_PTB2_PKE_MASK                     0x8u
#define IOMUXC_PTB2_PKE_SHIFT                    3
#define IOMUXC_PTB2_PUS_MASK                     0x30u
#define IOMUXC_PTB2_PUS_SHIFT                    4
#define IOMUXC_PTB2_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB2_PUS_SHIFT))&IOMUXC_PTB2_PUS_MASK)
#define IOMUXC_PTB2_DSE_MASK                     0x1C0u
#define IOMUXC_PTB2_DSE_SHIFT                    6
#define IOMUXC_PTB2_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB2_DSE_SHIFT))&IOMUXC_PTB2_DSE_MASK)
#define IOMUXC_PTB2_HYS_MASK                     0x200u
#define IOMUXC_PTB2_HYS_SHIFT                    9
#define IOMUXC_PTB2_ODE_MASK                     0x400u
#define IOMUXC_PTB2_ODE_SHIFT                    10
#define IOMUXC_PTB2_SRE_MASK                     0x800u
#define IOMUXC_PTB2_SRE_SHIFT                    11
#define IOMUXC_PTB2_SPEED_MASK                   0x3000u
#define IOMUXC_PTB2_SPEED_SHIFT                  12
#define IOMUXC_PTB2_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB2_SPEED_SHIFT))&IOMUXC_PTB2_SPEED_MASK)
#define IOMUXC_PTB2_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB2_MUX_MODE_SHIFT               20
#define IOMUXC_PTB2_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB2_MUX_MODE_SHIFT))&IOMUXC_PTB2_MUX_MODE_MASK)
/* PTB3 Bit Fields */
#define IOMUXC_PTB3_IBE_MASK                     0x1u
#define IOMUXC_PTB3_IBE_SHIFT                    0
#define IOMUXC_PTB3_OBE_MASK                     0x2u
#define IOMUXC_PTB3_OBE_SHIFT                    1
#define IOMUXC_PTB3_PUE_MASK                     0x4u
#define IOMUXC_PTB3_PUE_SHIFT                    2
#define IOMUXC_PTB3_PKE_MASK                     0x8u
#define IOMUXC_PTB3_PKE_SHIFT                    3
#define IOMUXC_PTB3_PUS_MASK                     0x30u
#define IOMUXC_PTB3_PUS_SHIFT                    4
#define IOMUXC_PTB3_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB3_PUS_SHIFT))&IOMUXC_PTB3_PUS_MASK)
#define IOMUXC_PTB3_DSE_MASK                     0x1C0u
#define IOMUXC_PTB3_DSE_SHIFT                    6
#define IOMUXC_PTB3_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB3_DSE_SHIFT))&IOMUXC_PTB3_DSE_MASK)
#define IOMUXC_PTB3_HYS_MASK                     0x200u
#define IOMUXC_PTB3_HYS_SHIFT                    9
#define IOMUXC_PTB3_ODE_MASK                     0x400u
#define IOMUXC_PTB3_ODE_SHIFT                    10
#define IOMUXC_PTB3_SRE_MASK                     0x800u
#define IOMUXC_PTB3_SRE_SHIFT                    11
#define IOMUXC_PTB3_SPEED_MASK                   0x3000u
#define IOMUXC_PTB3_SPEED_SHIFT                  12
#define IOMUXC_PTB3_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB3_SPEED_SHIFT))&IOMUXC_PTB3_SPEED_MASK)
#define IOMUXC_PTB3_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB3_MUX_MODE_SHIFT               20
#define IOMUXC_PTB3_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB3_MUX_MODE_SHIFT))&IOMUXC_PTB3_MUX_MODE_MASK)
/* PTB4 Bit Fields */
#define IOMUXC_PTB4_IBE_MASK                     0x1u
#define IOMUXC_PTB4_IBE_SHIFT                    0
#define IOMUXC_PTB4_OBE_MASK                     0x2u
#define IOMUXC_PTB4_OBE_SHIFT                    1
#define IOMUXC_PTB4_PUE_MASK                     0x4u
#define IOMUXC_PTB4_PUE_SHIFT                    2
#define IOMUXC_PTB4_PKE_MASK                     0x8u
#define IOMUXC_PTB4_PKE_SHIFT                    3
#define IOMUXC_PTB4_PUS_MASK                     0x30u
#define IOMUXC_PTB4_PUS_SHIFT                    4
#define IOMUXC_PTB4_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB4_PUS_SHIFT))&IOMUXC_PTB4_PUS_MASK)
#define IOMUXC_PTB4_DSE_MASK                     0x1C0u
#define IOMUXC_PTB4_DSE_SHIFT                    6
#define IOMUXC_PTB4_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB4_DSE_SHIFT))&IOMUXC_PTB4_DSE_MASK)
#define IOMUXC_PTB4_HYS_MASK                     0x200u
#define IOMUXC_PTB4_HYS_SHIFT                    9
#define IOMUXC_PTB4_ODE_MASK                     0x400u
#define IOMUXC_PTB4_ODE_SHIFT                    10
#define IOMUXC_PTB4_SRE_MASK                     0x800u
#define IOMUXC_PTB4_SRE_SHIFT                    11
#define IOMUXC_PTB4_SPEED_MASK                   0x3000u
#define IOMUXC_PTB4_SPEED_SHIFT                  12
#define IOMUXC_PTB4_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB4_SPEED_SHIFT))&IOMUXC_PTB4_SPEED_MASK)
#define IOMUXC_PTB4_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB4_MUX_MODE_SHIFT               20
#define IOMUXC_PTB4_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB4_MUX_MODE_SHIFT))&IOMUXC_PTB4_MUX_MODE_MASK)
/* PTB5 Bit Fields */
#define IOMUXC_PTB5_IBE_MASK                     0x1u
#define IOMUXC_PTB5_IBE_SHIFT                    0
#define IOMUXC_PTB5_OBE_MASK                     0x2u
#define IOMUXC_PTB5_OBE_SHIFT                    1
#define IOMUXC_PTB5_PUE_MASK                     0x4u
#define IOMUXC_PTB5_PUE_SHIFT                    2
#define IOMUXC_PTB5_PKE_MASK                     0x8u
#define IOMUXC_PTB5_PKE_SHIFT                    3
#define IOMUXC_PTB5_PUS_MASK                     0x30u
#define IOMUXC_PTB5_PUS_SHIFT                    4
#define IOMUXC_PTB5_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB5_PUS_SHIFT))&IOMUXC_PTB5_PUS_MASK)
#define IOMUXC_PTB5_DSE_MASK                     0x1C0u
#define IOMUXC_PTB5_DSE_SHIFT                    6
#define IOMUXC_PTB5_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB5_DSE_SHIFT))&IOMUXC_PTB5_DSE_MASK)
#define IOMUXC_PTB5_HYS_MASK                     0x200u
#define IOMUXC_PTB5_HYS_SHIFT                    9
#define IOMUXC_PTB5_ODE_MASK                     0x400u
#define IOMUXC_PTB5_ODE_SHIFT                    10
#define IOMUXC_PTB5_SRE_MASK                     0x800u
#define IOMUXC_PTB5_SRE_SHIFT                    11
#define IOMUXC_PTB5_SPEED_MASK                   0x3000u
#define IOMUXC_PTB5_SPEED_SHIFT                  12
#define IOMUXC_PTB5_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB5_SPEED_SHIFT))&IOMUXC_PTB5_SPEED_MASK)
#define IOMUXC_PTB5_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB5_MUX_MODE_SHIFT               20
#define IOMUXC_PTB5_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB5_MUX_MODE_SHIFT))&IOMUXC_PTB5_MUX_MODE_MASK)
/* PTB6 Bit Fields */
#define IOMUXC_PTB6_IBE_MASK                     0x1u
#define IOMUXC_PTB6_IBE_SHIFT                    0
#define IOMUXC_PTB6_OBE_MASK                     0x2u
#define IOMUXC_PTB6_OBE_SHIFT                    1
#define IOMUXC_PTB6_PUE_MASK                     0x4u
#define IOMUXC_PTB6_PUE_SHIFT                    2
#define IOMUXC_PTB6_PKE_MASK                     0x8u
#define IOMUXC_PTB6_PKE_SHIFT                    3
#define IOMUXC_PTB6_PUS_MASK                     0x30u
#define IOMUXC_PTB6_PUS_SHIFT                    4
#define IOMUXC_PTB6_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB6_PUS_SHIFT))&IOMUXC_PTB6_PUS_MASK)
#define IOMUXC_PTB6_DSE_MASK                     0x1C0u
#define IOMUXC_PTB6_DSE_SHIFT                    6
#define IOMUXC_PTB6_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB6_DSE_SHIFT))&IOMUXC_PTB6_DSE_MASK)
#define IOMUXC_PTB6_HYS_MASK                     0x200u
#define IOMUXC_PTB6_HYS_SHIFT                    9
#define IOMUXC_PTB6_ODE_MASK                     0x400u
#define IOMUXC_PTB6_ODE_SHIFT                    10
#define IOMUXC_PTB6_SRE_MASK                     0x800u
#define IOMUXC_PTB6_SRE_SHIFT                    11
#define IOMUXC_PTB6_SPEED_MASK                   0x3000u
#define IOMUXC_PTB6_SPEED_SHIFT                  12
#define IOMUXC_PTB6_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB6_SPEED_SHIFT))&IOMUXC_PTB6_SPEED_MASK)
#define IOMUXC_PTB6_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB6_MUX_MODE_SHIFT               20
#define IOMUXC_PTB6_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB6_MUX_MODE_SHIFT))&IOMUXC_PTB6_MUX_MODE_MASK)
/* PTB7 Bit Fields */
#define IOMUXC_PTB7_IBE_MASK                     0x1u
#define IOMUXC_PTB7_IBE_SHIFT                    0
#define IOMUXC_PTB7_OBE_MASK                     0x2u
#define IOMUXC_PTB7_OBE_SHIFT                    1
#define IOMUXC_PTB7_PUE_MASK                     0x4u
#define IOMUXC_PTB7_PUE_SHIFT                    2
#define IOMUXC_PTB7_PKE_MASK                     0x8u
#define IOMUXC_PTB7_PKE_SHIFT                    3
#define IOMUXC_PTB7_PUS_MASK                     0x30u
#define IOMUXC_PTB7_PUS_SHIFT                    4
#define IOMUXC_PTB7_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB7_PUS_SHIFT))&IOMUXC_PTB7_PUS_MASK)
#define IOMUXC_PTB7_DSE_MASK                     0x1C0u
#define IOMUXC_PTB7_DSE_SHIFT                    6
#define IOMUXC_PTB7_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB7_DSE_SHIFT))&IOMUXC_PTB7_DSE_MASK)
#define IOMUXC_PTB7_HYS_MASK                     0x200u
#define IOMUXC_PTB7_HYS_SHIFT                    9
#define IOMUXC_PTB7_ODE_MASK                     0x400u
#define IOMUXC_PTB7_ODE_SHIFT                    10
#define IOMUXC_PTB7_SRE_MASK                     0x800u
#define IOMUXC_PTB7_SRE_SHIFT                    11
#define IOMUXC_PTB7_SPEED_MASK                   0x3000u
#define IOMUXC_PTB7_SPEED_SHIFT                  12
#define IOMUXC_PTB7_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB7_SPEED_SHIFT))&IOMUXC_PTB7_SPEED_MASK)
#define IOMUXC_PTB7_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB7_MUX_MODE_SHIFT               20
#define IOMUXC_PTB7_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB7_MUX_MODE_SHIFT))&IOMUXC_PTB7_MUX_MODE_MASK)
/* PTB8 Bit Fields */
#define IOMUXC_PTB8_IBE_MASK                     0x1u
#define IOMUXC_PTB8_IBE_SHIFT                    0
#define IOMUXC_PTB8_OBE_MASK                     0x2u
#define IOMUXC_PTB8_OBE_SHIFT                    1
#define IOMUXC_PTB8_PUE_MASK                     0x4u
#define IOMUXC_PTB8_PUE_SHIFT                    2
#define IOMUXC_PTB8_PKE_MASK                     0x8u
#define IOMUXC_PTB8_PKE_SHIFT                    3
#define IOMUXC_PTB8_PUS_MASK                     0x30u
#define IOMUXC_PTB8_PUS_SHIFT                    4
#define IOMUXC_PTB8_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB8_PUS_SHIFT))&IOMUXC_PTB8_PUS_MASK)
#define IOMUXC_PTB8_DSE_MASK                     0x1C0u
#define IOMUXC_PTB8_DSE_SHIFT                    6
#define IOMUXC_PTB8_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB8_DSE_SHIFT))&IOMUXC_PTB8_DSE_MASK)
#define IOMUXC_PTB8_HYS_MASK                     0x200u
#define IOMUXC_PTB8_HYS_SHIFT                    9
#define IOMUXC_PTB8_ODE_MASK                     0x400u
#define IOMUXC_PTB8_ODE_SHIFT                    10
#define IOMUXC_PTB8_SRE_MASK                     0x800u
#define IOMUXC_PTB8_SRE_SHIFT                    11
#define IOMUXC_PTB8_SPEED_MASK                   0x3000u
#define IOMUXC_PTB8_SPEED_SHIFT                  12
#define IOMUXC_PTB8_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB8_SPEED_SHIFT))&IOMUXC_PTB8_SPEED_MASK)
#define IOMUXC_PTB8_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB8_MUX_MODE_SHIFT               20
#define IOMUXC_PTB8_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB8_MUX_MODE_SHIFT))&IOMUXC_PTB8_MUX_MODE_MASK)
/* PTB9 Bit Fields */
#define IOMUXC_PTB9_IBE_MASK                     0x1u
#define IOMUXC_PTB9_IBE_SHIFT                    0
#define IOMUXC_PTB9_OBE_MASK                     0x2u
#define IOMUXC_PTB9_OBE_SHIFT                    1
#define IOMUXC_PTB9_PUE_MASK                     0x4u
#define IOMUXC_PTB9_PUE_SHIFT                    2
#define IOMUXC_PTB9_PKE_MASK                     0x8u
#define IOMUXC_PTB9_PKE_SHIFT                    3
#define IOMUXC_PTB9_PUS_MASK                     0x30u
#define IOMUXC_PTB9_PUS_SHIFT                    4
#define IOMUXC_PTB9_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB9_PUS_SHIFT))&IOMUXC_PTB9_PUS_MASK)
#define IOMUXC_PTB9_DSE_MASK                     0x1C0u
#define IOMUXC_PTB9_DSE_SHIFT                    6
#define IOMUXC_PTB9_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB9_DSE_SHIFT))&IOMUXC_PTB9_DSE_MASK)
#define IOMUXC_PTB9_HYS_MASK                     0x200u
#define IOMUXC_PTB9_HYS_SHIFT                    9
#define IOMUXC_PTB9_ODE_MASK                     0x400u
#define IOMUXC_PTB9_ODE_SHIFT                    10
#define IOMUXC_PTB9_SRE_MASK                     0x800u
#define IOMUXC_PTB9_SRE_SHIFT                    11
#define IOMUXC_PTB9_SPEED_MASK                   0x3000u
#define IOMUXC_PTB9_SPEED_SHIFT                  12
#define IOMUXC_PTB9_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB9_SPEED_SHIFT))&IOMUXC_PTB9_SPEED_MASK)
#define IOMUXC_PTB9_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTB9_MUX_MODE_SHIFT               20
#define IOMUXC_PTB9_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB9_MUX_MODE_SHIFT))&IOMUXC_PTB9_MUX_MODE_MASK)
/* PTB10 Bit Fields */
#define IOMUXC_PTB10_IBE_MASK                    0x1u
#define IOMUXC_PTB10_IBE_SHIFT                   0
#define IOMUXC_PTB10_OBE_MASK                    0x2u
#define IOMUXC_PTB10_OBE_SHIFT                   1
#define IOMUXC_PTB10_PUE_MASK                    0x4u
#define IOMUXC_PTB10_PUE_SHIFT                   2
#define IOMUXC_PTB10_PKE_MASK                    0x8u
#define IOMUXC_PTB10_PKE_SHIFT                   3
#define IOMUXC_PTB10_PUS_MASK                    0x30u
#define IOMUXC_PTB10_PUS_SHIFT                   4
#define IOMUXC_PTB10_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB10_PUS_SHIFT))&IOMUXC_PTB10_PUS_MASK)
#define IOMUXC_PTB10_DSE_MASK                    0x1C0u
#define IOMUXC_PTB10_DSE_SHIFT                   6
#define IOMUXC_PTB10_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB10_DSE_SHIFT))&IOMUXC_PTB10_DSE_MASK)
#define IOMUXC_PTB10_HYS_MASK                    0x200u
#define IOMUXC_PTB10_HYS_SHIFT                   9
#define IOMUXC_PTB10_ODE_MASK                    0x400u
#define IOMUXC_PTB10_ODE_SHIFT                   10
#define IOMUXC_PTB10_SRE_MASK                    0x800u
#define IOMUXC_PTB10_SRE_SHIFT                   11
#define IOMUXC_PTB10_SPEED_MASK                  0x3000u
#define IOMUXC_PTB10_SPEED_SHIFT                 12
#define IOMUXC_PTB10_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB10_SPEED_SHIFT))&IOMUXC_PTB10_SPEED_MASK)
#define IOMUXC_PTB10_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB10_MUX_MODE_SHIFT              20
#define IOMUXC_PTB10_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB10_MUX_MODE_SHIFT))&IOMUXC_PTB10_MUX_MODE_MASK)
/* PTB11 Bit Fields */
#define IOMUXC_PTB11_IBE_MASK                    0x1u
#define IOMUXC_PTB11_IBE_SHIFT                   0
#define IOMUXC_PTB11_OBE_MASK                    0x2u
#define IOMUXC_PTB11_OBE_SHIFT                   1
#define IOMUXC_PTB11_PUE_MASK                    0x4u
#define IOMUXC_PTB11_PUE_SHIFT                   2
#define IOMUXC_PTB11_PKE_MASK                    0x8u
#define IOMUXC_PTB11_PKE_SHIFT                   3
#define IOMUXC_PTB11_PUS_MASK                    0x30u
#define IOMUXC_PTB11_PUS_SHIFT                   4
#define IOMUXC_PTB11_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB11_PUS_SHIFT))&IOMUXC_PTB11_PUS_MASK)
#define IOMUXC_PTB11_DSE_MASK                    0x1C0u
#define IOMUXC_PTB11_DSE_SHIFT                   6
#define IOMUXC_PTB11_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB11_DSE_SHIFT))&IOMUXC_PTB11_DSE_MASK)
#define IOMUXC_PTB11_HYS_MASK                    0x200u
#define IOMUXC_PTB11_HYS_SHIFT                   9
#define IOMUXC_PTB11_ODE_MASK                    0x400u
#define IOMUXC_PTB11_ODE_SHIFT                   10
#define IOMUXC_PTB11_SRE_MASK                    0x800u
#define IOMUXC_PTB11_SRE_SHIFT                   11
#define IOMUXC_PTB11_SPEED_MASK                  0x3000u
#define IOMUXC_PTB11_SPEED_SHIFT                 12
#define IOMUXC_PTB11_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB11_SPEED_SHIFT))&IOMUXC_PTB11_SPEED_MASK)
#define IOMUXC_PTB11_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB11_MUX_MODE_SHIFT              20
#define IOMUXC_PTB11_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB11_MUX_MODE_SHIFT))&IOMUXC_PTB11_MUX_MODE_MASK)
/* PTB12 Bit Fields */
#define IOMUXC_PTB12_IBE_MASK                    0x1u
#define IOMUXC_PTB12_IBE_SHIFT                   0
#define IOMUXC_PTB12_OBE_MASK                    0x2u
#define IOMUXC_PTB12_OBE_SHIFT                   1
#define IOMUXC_PTB12_PUE_MASK                    0x4u
#define IOMUXC_PTB12_PUE_SHIFT                   2
#define IOMUXC_PTB12_PKE_MASK                    0x8u
#define IOMUXC_PTB12_PKE_SHIFT                   3
#define IOMUXC_PTB12_PUS_MASK                    0x30u
#define IOMUXC_PTB12_PUS_SHIFT                   4
#define IOMUXC_PTB12_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB12_PUS_SHIFT))&IOMUXC_PTB12_PUS_MASK)
#define IOMUXC_PTB12_DSE_MASK                    0x1C0u
#define IOMUXC_PTB12_DSE_SHIFT                   6
#define IOMUXC_PTB12_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB12_DSE_SHIFT))&IOMUXC_PTB12_DSE_MASK)
#define IOMUXC_PTB12_HYS_MASK                    0x200u
#define IOMUXC_PTB12_HYS_SHIFT                   9
#define IOMUXC_PTB12_ODE_MASK                    0x400u
#define IOMUXC_PTB12_ODE_SHIFT                   10
#define IOMUXC_PTB12_SRE_MASK                    0x800u
#define IOMUXC_PTB12_SRE_SHIFT                   11
#define IOMUXC_PTB12_SPEED_MASK                  0x3000u
#define IOMUXC_PTB12_SPEED_SHIFT                 12
#define IOMUXC_PTB12_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB12_SPEED_SHIFT))&IOMUXC_PTB12_SPEED_MASK)
#define IOMUXC_PTB12_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB12_MUX_MODE_SHIFT              20
#define IOMUXC_PTB12_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB12_MUX_MODE_SHIFT))&IOMUXC_PTB12_MUX_MODE_MASK)
/* PTB13 Bit Fields */
#define IOMUXC_PTB13_IBE_MASK                    0x1u
#define IOMUXC_PTB13_IBE_SHIFT                   0
#define IOMUXC_PTB13_OBE_MASK                    0x2u
#define IOMUXC_PTB13_OBE_SHIFT                   1
#define IOMUXC_PTB13_PUE_MASK                    0x4u
#define IOMUXC_PTB13_PUE_SHIFT                   2
#define IOMUXC_PTB13_PKE_MASK                    0x8u
#define IOMUXC_PTB13_PKE_SHIFT                   3
#define IOMUXC_PTB13_PUS_MASK                    0x30u
#define IOMUXC_PTB13_PUS_SHIFT                   4
#define IOMUXC_PTB13_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB13_PUS_SHIFT))&IOMUXC_PTB13_PUS_MASK)
#define IOMUXC_PTB13_DSE_MASK                    0x1C0u
#define IOMUXC_PTB13_DSE_SHIFT                   6
#define IOMUXC_PTB13_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB13_DSE_SHIFT))&IOMUXC_PTB13_DSE_MASK)
#define IOMUXC_PTB13_HYS_MASK                    0x200u
#define IOMUXC_PTB13_HYS_SHIFT                   9
#define IOMUXC_PTB13_ODE_MASK                    0x400u
#define IOMUXC_PTB13_ODE_SHIFT                   10
#define IOMUXC_PTB13_SRE_MASK                    0x800u
#define IOMUXC_PTB13_SRE_SHIFT                   11
#define IOMUXC_PTB13_SPEED_MASK                  0x3000u
#define IOMUXC_PTB13_SPEED_SHIFT                 12
#define IOMUXC_PTB13_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB13_SPEED_SHIFT))&IOMUXC_PTB13_SPEED_MASK)
#define IOMUXC_PTB13_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB13_MUX_MODE_SHIFT              20
#define IOMUXC_PTB13_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB13_MUX_MODE_SHIFT))&IOMUXC_PTB13_MUX_MODE_MASK)
/* PTB14 Bit Fields */
#define IOMUXC_PTB14_IBE_MASK                    0x1u
#define IOMUXC_PTB14_IBE_SHIFT                   0
#define IOMUXC_PTB14_OBE_MASK                    0x2u
#define IOMUXC_PTB14_OBE_SHIFT                   1
#define IOMUXC_PTB14_PUE_MASK                    0x4u
#define IOMUXC_PTB14_PUE_SHIFT                   2
#define IOMUXC_PTB14_PKE_MASK                    0x8u
#define IOMUXC_PTB14_PKE_SHIFT                   3
#define IOMUXC_PTB14_PUS_MASK                    0x30u
#define IOMUXC_PTB14_PUS_SHIFT                   4
#define IOMUXC_PTB14_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB14_PUS_SHIFT))&IOMUXC_PTB14_PUS_MASK)
#define IOMUXC_PTB14_DSE_MASK                    0x1C0u
#define IOMUXC_PTB14_DSE_SHIFT                   6
#define IOMUXC_PTB14_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB14_DSE_SHIFT))&IOMUXC_PTB14_DSE_MASK)
#define IOMUXC_PTB14_HYS_MASK                    0x200u
#define IOMUXC_PTB14_HYS_SHIFT                   9
#define IOMUXC_PTB14_ODE_MASK                    0x400u
#define IOMUXC_PTB14_ODE_SHIFT                   10
#define IOMUXC_PTB14_SRE_MASK                    0x800u
#define IOMUXC_PTB14_SRE_SHIFT                   11
#define IOMUXC_PTB14_SPEED_MASK                  0x3000u
#define IOMUXC_PTB14_SPEED_SHIFT                 12
#define IOMUXC_PTB14_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB14_SPEED_SHIFT))&IOMUXC_PTB14_SPEED_MASK)
#define IOMUXC_PTB14_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB14_MUX_MODE_SHIFT              20
#define IOMUXC_PTB14_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB14_MUX_MODE_SHIFT))&IOMUXC_PTB14_MUX_MODE_MASK)
/* PTB15 Bit Fields */
#define IOMUXC_PTB15_IBE_MASK                    0x1u
#define IOMUXC_PTB15_IBE_SHIFT                   0
#define IOMUXC_PTB15_OBE_MASK                    0x2u
#define IOMUXC_PTB15_OBE_SHIFT                   1
#define IOMUXC_PTB15_PUE_MASK                    0x4u
#define IOMUXC_PTB15_PUE_SHIFT                   2
#define IOMUXC_PTB15_PKE_MASK                    0x8u
#define IOMUXC_PTB15_PKE_SHIFT                   3
#define IOMUXC_PTB15_PUS_MASK                    0x30u
#define IOMUXC_PTB15_PUS_SHIFT                   4
#define IOMUXC_PTB15_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB15_PUS_SHIFT))&IOMUXC_PTB15_PUS_MASK)
#define IOMUXC_PTB15_DSE_MASK                    0x1C0u
#define IOMUXC_PTB15_DSE_SHIFT                   6
#define IOMUXC_PTB15_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB15_DSE_SHIFT))&IOMUXC_PTB15_DSE_MASK)
#define IOMUXC_PTB15_HYS_MASK                    0x200u
#define IOMUXC_PTB15_HYS_SHIFT                   9
#define IOMUXC_PTB15_ODE_MASK                    0x400u
#define IOMUXC_PTB15_ODE_SHIFT                   10
#define IOMUXC_PTB15_SRE_MASK                    0x800u
#define IOMUXC_PTB15_SRE_SHIFT                   11
#define IOMUXC_PTB15_SPEED_MASK                  0x3000u
#define IOMUXC_PTB15_SPEED_SHIFT                 12
#define IOMUXC_PTB15_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB15_SPEED_SHIFT))&IOMUXC_PTB15_SPEED_MASK)
#define IOMUXC_PTB15_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB15_MUX_MODE_SHIFT              20
#define IOMUXC_PTB15_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB15_MUX_MODE_SHIFT))&IOMUXC_PTB15_MUX_MODE_MASK)
/* PTB16 Bit Fields */
#define IOMUXC_PTB16_IBE_MASK                    0x1u
#define IOMUXC_PTB16_IBE_SHIFT                   0
#define IOMUXC_PTB16_OBE_MASK                    0x2u
#define IOMUXC_PTB16_OBE_SHIFT                   1
#define IOMUXC_PTB16_PUE_MASK                    0x4u
#define IOMUXC_PTB16_PUE_SHIFT                   2
#define IOMUXC_PTB16_PKE_MASK                    0x8u
#define IOMUXC_PTB16_PKE_SHIFT                   3
#define IOMUXC_PTB16_PUS_MASK                    0x30u
#define IOMUXC_PTB16_PUS_SHIFT                   4
#define IOMUXC_PTB16_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB16_PUS_SHIFT))&IOMUXC_PTB16_PUS_MASK)
#define IOMUXC_PTB16_DSE_MASK                    0x1C0u
#define IOMUXC_PTB16_DSE_SHIFT                   6
#define IOMUXC_PTB16_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB16_DSE_SHIFT))&IOMUXC_PTB16_DSE_MASK)
#define IOMUXC_PTB16_HYS_MASK                    0x200u
#define IOMUXC_PTB16_HYS_SHIFT                   9
#define IOMUXC_PTB16_ODE_MASK                    0x400u
#define IOMUXC_PTB16_ODE_SHIFT                   10
#define IOMUXC_PTB16_SRE_MASK                    0x800u
#define IOMUXC_PTB16_SRE_SHIFT                   11
#define IOMUXC_PTB16_SPEED_MASK                  0x3000u
#define IOMUXC_PTB16_SPEED_SHIFT                 12
#define IOMUXC_PTB16_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB16_SPEED_SHIFT))&IOMUXC_PTB16_SPEED_MASK)
#define IOMUXC_PTB16_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB16_MUX_MODE_SHIFT              20
#define IOMUXC_PTB16_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB16_MUX_MODE_SHIFT))&IOMUXC_PTB16_MUX_MODE_MASK)
/* PTB17 Bit Fields */
#define IOMUXC_PTB17_IBE_MASK                    0x1u
#define IOMUXC_PTB17_IBE_SHIFT                   0
#define IOMUXC_PTB17_OBE_MASK                    0x2u
#define IOMUXC_PTB17_OBE_SHIFT                   1
#define IOMUXC_PTB17_PUE_MASK                    0x4u
#define IOMUXC_PTB17_PUE_SHIFT                   2
#define IOMUXC_PTB17_PKE_MASK                    0x8u
#define IOMUXC_PTB17_PKE_SHIFT                   3
#define IOMUXC_PTB17_PUS_MASK                    0x30u
#define IOMUXC_PTB17_PUS_SHIFT                   4
#define IOMUXC_PTB17_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB17_PUS_SHIFT))&IOMUXC_PTB17_PUS_MASK)
#define IOMUXC_PTB17_DSE_MASK                    0x1C0u
#define IOMUXC_PTB17_DSE_SHIFT                   6
#define IOMUXC_PTB17_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB17_DSE_SHIFT))&IOMUXC_PTB17_DSE_MASK)
#define IOMUXC_PTB17_HYS_MASK                    0x200u
#define IOMUXC_PTB17_HYS_SHIFT                   9
#define IOMUXC_PTB17_ODE_MASK                    0x400u
#define IOMUXC_PTB17_ODE_SHIFT                   10
#define IOMUXC_PTB17_SRE_MASK                    0x800u
#define IOMUXC_PTB17_SRE_SHIFT                   11
#define IOMUXC_PTB17_SPEED_MASK                  0x3000u
#define IOMUXC_PTB17_SPEED_SHIFT                 12
#define IOMUXC_PTB17_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB17_SPEED_SHIFT))&IOMUXC_PTB17_SPEED_MASK)
#define IOMUXC_PTB17_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB17_MUX_MODE_SHIFT              20
#define IOMUXC_PTB17_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB17_MUX_MODE_SHIFT))&IOMUXC_PTB17_MUX_MODE_MASK)
/* PTB18 Bit Fields */
#define IOMUXC_PTB18_IBE_MASK                    0x1u
#define IOMUXC_PTB18_IBE_SHIFT                   0
#define IOMUXC_PTB18_OBE_MASK                    0x2u
#define IOMUXC_PTB18_OBE_SHIFT                   1
#define IOMUXC_PTB18_PUE_MASK                    0x4u
#define IOMUXC_PTB18_PUE_SHIFT                   2
#define IOMUXC_PTB18_PKE_MASK                    0x8u
#define IOMUXC_PTB18_PKE_SHIFT                   3
#define IOMUXC_PTB18_PUS_MASK                    0x30u
#define IOMUXC_PTB18_PUS_SHIFT                   4
#define IOMUXC_PTB18_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB18_PUS_SHIFT))&IOMUXC_PTB18_PUS_MASK)
#define IOMUXC_PTB18_DSE_MASK                    0x1C0u
#define IOMUXC_PTB18_DSE_SHIFT                   6
#define IOMUXC_PTB18_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB18_DSE_SHIFT))&IOMUXC_PTB18_DSE_MASK)
#define IOMUXC_PTB18_HYS_MASK                    0x200u
#define IOMUXC_PTB18_HYS_SHIFT                   9
#define IOMUXC_PTB18_ODE_MASK                    0x400u
#define IOMUXC_PTB18_ODE_SHIFT                   10
#define IOMUXC_PTB18_SRE_MASK                    0x800u
#define IOMUXC_PTB18_SRE_SHIFT                   11
#define IOMUXC_PTB18_SPEED_MASK                  0x3000u
#define IOMUXC_PTB18_SPEED_SHIFT                 12
#define IOMUXC_PTB18_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB18_SPEED_SHIFT))&IOMUXC_PTB18_SPEED_MASK)
#define IOMUXC_PTB18_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB18_MUX_MODE_SHIFT              20
#define IOMUXC_PTB18_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB18_MUX_MODE_SHIFT))&IOMUXC_PTB18_MUX_MODE_MASK)
/* PTB19 Bit Fields */
#define IOMUXC_PTB19_IBE_MASK                    0x1u
#define IOMUXC_PTB19_IBE_SHIFT                   0
#define IOMUXC_PTB19_OBE_MASK                    0x2u
#define IOMUXC_PTB19_OBE_SHIFT                   1
#define IOMUXC_PTB19_PUE_MASK                    0x4u
#define IOMUXC_PTB19_PUE_SHIFT                   2
#define IOMUXC_PTB19_PKE_MASK                    0x8u
#define IOMUXC_PTB19_PKE_SHIFT                   3
#define IOMUXC_PTB19_PUS_MASK                    0x30u
#define IOMUXC_PTB19_PUS_SHIFT                   4
#define IOMUXC_PTB19_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB19_PUS_SHIFT))&IOMUXC_PTB19_PUS_MASK)
#define IOMUXC_PTB19_DSE_MASK                    0x1C0u
#define IOMUXC_PTB19_DSE_SHIFT                   6
#define IOMUXC_PTB19_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB19_DSE_SHIFT))&IOMUXC_PTB19_DSE_MASK)
#define IOMUXC_PTB19_HYS_MASK                    0x200u
#define IOMUXC_PTB19_HYS_SHIFT                   9
#define IOMUXC_PTB19_ODE_MASK                    0x400u
#define IOMUXC_PTB19_ODE_SHIFT                   10
#define IOMUXC_PTB19_SRE_MASK                    0x800u
#define IOMUXC_PTB19_SRE_SHIFT                   11
#define IOMUXC_PTB19_SPEED_MASK                  0x3000u
#define IOMUXC_PTB19_SPEED_SHIFT                 12
#define IOMUXC_PTB19_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB19_SPEED_SHIFT))&IOMUXC_PTB19_SPEED_MASK)
#define IOMUXC_PTB19_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB19_MUX_MODE_SHIFT              20
#define IOMUXC_PTB19_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB19_MUX_MODE_SHIFT))&IOMUXC_PTB19_MUX_MODE_MASK)
/* PTB20 Bit Fields */
#define IOMUXC_PTB20_IBE_MASK                    0x1u
#define IOMUXC_PTB20_IBE_SHIFT                   0
#define IOMUXC_PTB20_OBE_MASK                    0x2u
#define IOMUXC_PTB20_OBE_SHIFT                   1
#define IOMUXC_PTB20_PUE_MASK                    0x4u
#define IOMUXC_PTB20_PUE_SHIFT                   2
#define IOMUXC_PTB20_PKE_MASK                    0x8u
#define IOMUXC_PTB20_PKE_SHIFT                   3
#define IOMUXC_PTB20_PUS_MASK                    0x30u
#define IOMUXC_PTB20_PUS_SHIFT                   4
#define IOMUXC_PTB20_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB20_PUS_SHIFT))&IOMUXC_PTB20_PUS_MASK)
#define IOMUXC_PTB20_DSE_MASK                    0x1C0u
#define IOMUXC_PTB20_DSE_SHIFT                   6
#define IOMUXC_PTB20_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB20_DSE_SHIFT))&IOMUXC_PTB20_DSE_MASK)
#define IOMUXC_PTB20_HYS_MASK                    0x200u
#define IOMUXC_PTB20_HYS_SHIFT                   9
#define IOMUXC_PTB20_ODE_MASK                    0x400u
#define IOMUXC_PTB20_ODE_SHIFT                   10
#define IOMUXC_PTB20_SRE_MASK                    0x800u
#define IOMUXC_PTB20_SRE_SHIFT                   11
#define IOMUXC_PTB20_SPEED_MASK                  0x3000u
#define IOMUXC_PTB20_SPEED_SHIFT                 12
#define IOMUXC_PTB20_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB20_SPEED_SHIFT))&IOMUXC_PTB20_SPEED_MASK)
#define IOMUXC_PTB20_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB20_MUX_MODE_SHIFT              20
#define IOMUXC_PTB20_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB20_MUX_MODE_SHIFT))&IOMUXC_PTB20_MUX_MODE_MASK)
/* PTB21 Bit Fields */
#define IOMUXC_PTB21_IBE_MASK                    0x1u
#define IOMUXC_PTB21_IBE_SHIFT                   0
#define IOMUXC_PTB21_OBE_MASK                    0x2u
#define IOMUXC_PTB21_OBE_SHIFT                   1
#define IOMUXC_PTB21_PUE_MASK                    0x4u
#define IOMUXC_PTB21_PUE_SHIFT                   2
#define IOMUXC_PTB21_PKE_MASK                    0x8u
#define IOMUXC_PTB21_PKE_SHIFT                   3
#define IOMUXC_PTB21_PUS_MASK                    0x30u
#define IOMUXC_PTB21_PUS_SHIFT                   4
#define IOMUXC_PTB21_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB21_PUS_SHIFT))&IOMUXC_PTB21_PUS_MASK)
#define IOMUXC_PTB21_DSE_MASK                    0x1C0u
#define IOMUXC_PTB21_DSE_SHIFT                   6
#define IOMUXC_PTB21_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB21_DSE_SHIFT))&IOMUXC_PTB21_DSE_MASK)
#define IOMUXC_PTB21_HYS_MASK                    0x200u
#define IOMUXC_PTB21_HYS_SHIFT                   9
#define IOMUXC_PTB21_ODE_MASK                    0x400u
#define IOMUXC_PTB21_ODE_SHIFT                   10
#define IOMUXC_PTB21_SRE_MASK                    0x800u
#define IOMUXC_PTB21_SRE_SHIFT                   11
#define IOMUXC_PTB21_SPEED_MASK                  0x3000u
#define IOMUXC_PTB21_SPEED_SHIFT                 12
#define IOMUXC_PTB21_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB21_SPEED_SHIFT))&IOMUXC_PTB21_SPEED_MASK)
#define IOMUXC_PTB21_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB21_MUX_MODE_SHIFT              20
#define IOMUXC_PTB21_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB21_MUX_MODE_SHIFT))&IOMUXC_PTB21_MUX_MODE_MASK)
/* PTB22 Bit Fields */
#define IOMUXC_PTB22_IBE_MASK                    0x1u
#define IOMUXC_PTB22_IBE_SHIFT                   0
#define IOMUXC_PTB22_OBE_MASK                    0x2u
#define IOMUXC_PTB22_OBE_SHIFT                   1
#define IOMUXC_PTB22_PUE_MASK                    0x4u
#define IOMUXC_PTB22_PUE_SHIFT                   2
#define IOMUXC_PTB22_PKE_MASK                    0x8u
#define IOMUXC_PTB22_PKE_SHIFT                   3
#define IOMUXC_PTB22_PUS_MASK                    0x30u
#define IOMUXC_PTB22_PUS_SHIFT                   4
#define IOMUXC_PTB22_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB22_PUS_SHIFT))&IOMUXC_PTB22_PUS_MASK)
#define IOMUXC_PTB22_DSE_MASK                    0x1C0u
#define IOMUXC_PTB22_DSE_SHIFT                   6
#define IOMUXC_PTB22_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB22_DSE_SHIFT))&IOMUXC_PTB22_DSE_MASK)
#define IOMUXC_PTB22_HYS_MASK                    0x200u
#define IOMUXC_PTB22_HYS_SHIFT                   9
#define IOMUXC_PTB22_ODE_MASK                    0x400u
#define IOMUXC_PTB22_ODE_SHIFT                   10
#define IOMUXC_PTB22_SRE_MASK                    0x800u
#define IOMUXC_PTB22_SRE_SHIFT                   11
#define IOMUXC_PTB22_SPEED_MASK                  0x3000u
#define IOMUXC_PTB22_SPEED_SHIFT                 12
#define IOMUXC_PTB22_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB22_SPEED_SHIFT))&IOMUXC_PTB22_SPEED_MASK)
#define IOMUXC_PTB22_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB22_MUX_MODE_SHIFT              20
#define IOMUXC_PTB22_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB22_MUX_MODE_SHIFT))&IOMUXC_PTB22_MUX_MODE_MASK)
/* PTC0 Bit Fields */
#define IOMUXC_PTC0_IBE_MASK                     0x1u
#define IOMUXC_PTC0_IBE_SHIFT                    0
#define IOMUXC_PTC0_OBE_MASK                     0x2u
#define IOMUXC_PTC0_OBE_SHIFT                    1
#define IOMUXC_PTC0_PUE_MASK                     0x4u
#define IOMUXC_PTC0_PUE_SHIFT                    2
#define IOMUXC_PTC0_PKE_MASK                     0x8u
#define IOMUXC_PTC0_PKE_SHIFT                    3
#define IOMUXC_PTC0_PUS_MASK                     0x30u
#define IOMUXC_PTC0_PUS_SHIFT                    4
#define IOMUXC_PTC0_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC0_PUS_SHIFT))&IOMUXC_PTC0_PUS_MASK)
#define IOMUXC_PTC0_DSE_MASK                     0x1C0u
#define IOMUXC_PTC0_DSE_SHIFT                    6
#define IOMUXC_PTC0_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC0_DSE_SHIFT))&IOMUXC_PTC0_DSE_MASK)
#define IOMUXC_PTC0_HYS_MASK                     0x200u
#define IOMUXC_PTC0_HYS_SHIFT                    9
#define IOMUXC_PTC0_ODE_MASK                     0x400u
#define IOMUXC_PTC0_ODE_SHIFT                    10
#define IOMUXC_PTC0_SRE_MASK                     0x800u
#define IOMUXC_PTC0_SRE_SHIFT                    11
#define IOMUXC_PTC0_SPEED_MASK                   0x3000u
#define IOMUXC_PTC0_SPEED_SHIFT                  12
#define IOMUXC_PTC0_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC0_SPEED_SHIFT))&IOMUXC_PTC0_SPEED_MASK)
#define IOMUXC_PTC0_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC0_MUX_MODE_SHIFT               20
#define IOMUXC_PTC0_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC0_MUX_MODE_SHIFT))&IOMUXC_PTC0_MUX_MODE_MASK)
/* PTC1 Bit Fields */
#define IOMUXC_PTC1_IBE_MASK                     0x1u
#define IOMUXC_PTC1_IBE_SHIFT                    0
#define IOMUXC_PTC1_OBE_MASK                     0x2u
#define IOMUXC_PTC1_OBE_SHIFT                    1
#define IOMUXC_PTC1_PUE_MASK                     0x4u
#define IOMUXC_PTC1_PUE_SHIFT                    2
#define IOMUXC_PTC1_PKE_MASK                     0x8u
#define IOMUXC_PTC1_PKE_SHIFT                    3
#define IOMUXC_PTC1_PUS_MASK                     0x30u
#define IOMUXC_PTC1_PUS_SHIFT                    4
#define IOMUXC_PTC1_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC1_PUS_SHIFT))&IOMUXC_PTC1_PUS_MASK)
#define IOMUXC_PTC1_DSE_MASK                     0x1C0u
#define IOMUXC_PTC1_DSE_SHIFT                    6
#define IOMUXC_PTC1_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC1_DSE_SHIFT))&IOMUXC_PTC1_DSE_MASK)
#define IOMUXC_PTC1_HYS_MASK                     0x200u
#define IOMUXC_PTC1_HYS_SHIFT                    9
#define IOMUXC_PTC1_ODE_MASK                     0x400u
#define IOMUXC_PTC1_ODE_SHIFT                    10
#define IOMUXC_PTC1_SRE_MASK                     0x800u
#define IOMUXC_PTC1_SRE_SHIFT                    11
#define IOMUXC_PTC1_SPEED_MASK                   0x3000u
#define IOMUXC_PTC1_SPEED_SHIFT                  12
#define IOMUXC_PTC1_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC1_SPEED_SHIFT))&IOMUXC_PTC1_SPEED_MASK)
#define IOMUXC_PTC1_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC1_MUX_MODE_SHIFT               20
#define IOMUXC_PTC1_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC1_MUX_MODE_SHIFT))&IOMUXC_PTC1_MUX_MODE_MASK)
/* PTC2 Bit Fields */
#define IOMUXC_PTC2_IBE_MASK                     0x1u
#define IOMUXC_PTC2_IBE_SHIFT                    0
#define IOMUXC_PTC2_OBE_MASK                     0x2u
#define IOMUXC_PTC2_OBE_SHIFT                    1
#define IOMUXC_PTC2_PUE_MASK                     0x4u
#define IOMUXC_PTC2_PUE_SHIFT                    2
#define IOMUXC_PTC2_PKE_MASK                     0x8u
#define IOMUXC_PTC2_PKE_SHIFT                    3
#define IOMUXC_PTC2_PUS_MASK                     0x30u
#define IOMUXC_PTC2_PUS_SHIFT                    4
#define IOMUXC_PTC2_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC2_PUS_SHIFT))&IOMUXC_PTC2_PUS_MASK)
#define IOMUXC_PTC2_DSE_MASK                     0x1C0u
#define IOMUXC_PTC2_DSE_SHIFT                    6
#define IOMUXC_PTC2_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC2_DSE_SHIFT))&IOMUXC_PTC2_DSE_MASK)
#define IOMUXC_PTC2_HYS_MASK                     0x200u
#define IOMUXC_PTC2_HYS_SHIFT                    9
#define IOMUXC_PTC2_ODE_MASK                     0x400u
#define IOMUXC_PTC2_ODE_SHIFT                    10
#define IOMUXC_PTC2_SRE_MASK                     0x800u
#define IOMUXC_PTC2_SRE_SHIFT                    11
#define IOMUXC_PTC2_SPEED_MASK                   0x3000u
#define IOMUXC_PTC2_SPEED_SHIFT                  12
#define IOMUXC_PTC2_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC2_SPEED_SHIFT))&IOMUXC_PTC2_SPEED_MASK)
#define IOMUXC_PTC2_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC2_MUX_MODE_SHIFT               20
#define IOMUXC_PTC2_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC2_MUX_MODE_SHIFT))&IOMUXC_PTC2_MUX_MODE_MASK)
/* PTC3 Bit Fields */
#define IOMUXC_PTC3_IBE_MASK                     0x1u
#define IOMUXC_PTC3_IBE_SHIFT                    0
#define IOMUXC_PTC3_OBE_MASK                     0x2u
#define IOMUXC_PTC3_OBE_SHIFT                    1
#define IOMUXC_PTC3_PUE_MASK                     0x4u
#define IOMUXC_PTC3_PUE_SHIFT                    2
#define IOMUXC_PTC3_PKE_MASK                     0x8u
#define IOMUXC_PTC3_PKE_SHIFT                    3
#define IOMUXC_PTC3_PUS_MASK                     0x30u
#define IOMUXC_PTC3_PUS_SHIFT                    4
#define IOMUXC_PTC3_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC3_PUS_SHIFT))&IOMUXC_PTC3_PUS_MASK)
#define IOMUXC_PTC3_DSE_MASK                     0x1C0u
#define IOMUXC_PTC3_DSE_SHIFT                    6
#define IOMUXC_PTC3_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC3_DSE_SHIFT))&IOMUXC_PTC3_DSE_MASK)
#define IOMUXC_PTC3_HYS_MASK                     0x200u
#define IOMUXC_PTC3_HYS_SHIFT                    9
#define IOMUXC_PTC3_ODE_MASK                     0x400u
#define IOMUXC_PTC3_ODE_SHIFT                    10
#define IOMUXC_PTC3_SRE_MASK                     0x800u
#define IOMUXC_PTC3_SRE_SHIFT                    11
#define IOMUXC_PTC3_SPEED_MASK                   0x3000u
#define IOMUXC_PTC3_SPEED_SHIFT                  12
#define IOMUXC_PTC3_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC3_SPEED_SHIFT))&IOMUXC_PTC3_SPEED_MASK)
#define IOMUXC_PTC3_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC3_MUX_MODE_SHIFT               20
#define IOMUXC_PTC3_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC3_MUX_MODE_SHIFT))&IOMUXC_PTC3_MUX_MODE_MASK)
/* PTC4 Bit Fields */
#define IOMUXC_PTC4_IBE_MASK                     0x1u
#define IOMUXC_PTC4_IBE_SHIFT                    0
#define IOMUXC_PTC4_OBE_MASK                     0x2u
#define IOMUXC_PTC4_OBE_SHIFT                    1
#define IOMUXC_PTC4_PUE_MASK                     0x4u
#define IOMUXC_PTC4_PUE_SHIFT                    2
#define IOMUXC_PTC4_PKE_MASK                     0x8u
#define IOMUXC_PTC4_PKE_SHIFT                    3
#define IOMUXC_PTC4_PUS_MASK                     0x30u
#define IOMUXC_PTC4_PUS_SHIFT                    4
#define IOMUXC_PTC4_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC4_PUS_SHIFT))&IOMUXC_PTC4_PUS_MASK)
#define IOMUXC_PTC4_DSE_MASK                     0x1C0u
#define IOMUXC_PTC4_DSE_SHIFT                    6
#define IOMUXC_PTC4_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC4_DSE_SHIFT))&IOMUXC_PTC4_DSE_MASK)
#define IOMUXC_PTC4_HYS_MASK                     0x200u
#define IOMUXC_PTC4_HYS_SHIFT                    9
#define IOMUXC_PTC4_ODE_MASK                     0x400u
#define IOMUXC_PTC4_ODE_SHIFT                    10
#define IOMUXC_PTC4_SRE_MASK                     0x800u
#define IOMUXC_PTC4_SRE_SHIFT                    11
#define IOMUXC_PTC4_SPEED_MASK                   0x3000u
#define IOMUXC_PTC4_SPEED_SHIFT                  12
#define IOMUXC_PTC4_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC4_SPEED_SHIFT))&IOMUXC_PTC4_SPEED_MASK)
#define IOMUXC_PTC4_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC4_MUX_MODE_SHIFT               20
#define IOMUXC_PTC4_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC4_MUX_MODE_SHIFT))&IOMUXC_PTC4_MUX_MODE_MASK)
/* PTC5 Bit Fields */
#define IOMUXC_PTC5_IBE_MASK                     0x1u
#define IOMUXC_PTC5_IBE_SHIFT                    0
#define IOMUXC_PTC5_OBE_MASK                     0x2u
#define IOMUXC_PTC5_OBE_SHIFT                    1
#define IOMUXC_PTC5_PUE_MASK                     0x4u
#define IOMUXC_PTC5_PUE_SHIFT                    2
#define IOMUXC_PTC5_PKE_MASK                     0x8u
#define IOMUXC_PTC5_PKE_SHIFT                    3
#define IOMUXC_PTC5_PUS_MASK                     0x30u
#define IOMUXC_PTC5_PUS_SHIFT                    4
#define IOMUXC_PTC5_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC5_PUS_SHIFT))&IOMUXC_PTC5_PUS_MASK)
#define IOMUXC_PTC5_DSE_MASK                     0x1C0u
#define IOMUXC_PTC5_DSE_SHIFT                    6
#define IOMUXC_PTC5_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC5_DSE_SHIFT))&IOMUXC_PTC5_DSE_MASK)
#define IOMUXC_PTC5_HYS_MASK                     0x200u
#define IOMUXC_PTC5_HYS_SHIFT                    9
#define IOMUXC_PTC5_ODE_MASK                     0x400u
#define IOMUXC_PTC5_ODE_SHIFT                    10
#define IOMUXC_PTC5_SRE_MASK                     0x800u
#define IOMUXC_PTC5_SRE_SHIFT                    11
#define IOMUXC_PTC5_SPEED_MASK                   0x3000u
#define IOMUXC_PTC5_SPEED_SHIFT                  12
#define IOMUXC_PTC5_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC5_SPEED_SHIFT))&IOMUXC_PTC5_SPEED_MASK)
#define IOMUXC_PTC5_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC5_MUX_MODE_SHIFT               20
#define IOMUXC_PTC5_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC5_MUX_MODE_SHIFT))&IOMUXC_PTC5_MUX_MODE_MASK)
/* PTC6 Bit Fields */
#define IOMUXC_PTC6_IBE_MASK                     0x1u
#define IOMUXC_PTC6_IBE_SHIFT                    0
#define IOMUXC_PTC6_OBE_MASK                     0x2u
#define IOMUXC_PTC6_OBE_SHIFT                    1
#define IOMUXC_PTC6_PUE_MASK                     0x4u
#define IOMUXC_PTC6_PUE_SHIFT                    2
#define IOMUXC_PTC6_PKE_MASK                     0x8u
#define IOMUXC_PTC6_PKE_SHIFT                    3
#define IOMUXC_PTC6_PUS_MASK                     0x30u
#define IOMUXC_PTC6_PUS_SHIFT                    4
#define IOMUXC_PTC6_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC6_PUS_SHIFT))&IOMUXC_PTC6_PUS_MASK)
#define IOMUXC_PTC6_DSE_MASK                     0x1C0u
#define IOMUXC_PTC6_DSE_SHIFT                    6
#define IOMUXC_PTC6_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC6_DSE_SHIFT))&IOMUXC_PTC6_DSE_MASK)
#define IOMUXC_PTC6_HYS_MASK                     0x200u
#define IOMUXC_PTC6_HYS_SHIFT                    9
#define IOMUXC_PTC6_ODE_MASK                     0x400u
#define IOMUXC_PTC6_ODE_SHIFT                    10
#define IOMUXC_PTC6_SRE_MASK                     0x800u
#define IOMUXC_PTC6_SRE_SHIFT                    11
#define IOMUXC_PTC6_SPEED_MASK                   0x3000u
#define IOMUXC_PTC6_SPEED_SHIFT                  12
#define IOMUXC_PTC6_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC6_SPEED_SHIFT))&IOMUXC_PTC6_SPEED_MASK)
#define IOMUXC_PTC6_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC6_MUX_MODE_SHIFT               20
#define IOMUXC_PTC6_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC6_MUX_MODE_SHIFT))&IOMUXC_PTC6_MUX_MODE_MASK)
/* PTC7 Bit Fields */
#define IOMUXC_PTC7_IBE_MASK                     0x1u
#define IOMUXC_PTC7_IBE_SHIFT                    0
#define IOMUXC_PTC7_OBE_MASK                     0x2u
#define IOMUXC_PTC7_OBE_SHIFT                    1
#define IOMUXC_PTC7_PUE_MASK                     0x4u
#define IOMUXC_PTC7_PUE_SHIFT                    2
#define IOMUXC_PTC7_PKE_MASK                     0x8u
#define IOMUXC_PTC7_PKE_SHIFT                    3
#define IOMUXC_PTC7_PUS_MASK                     0x30u
#define IOMUXC_PTC7_PUS_SHIFT                    4
#define IOMUXC_PTC7_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC7_PUS_SHIFT))&IOMUXC_PTC7_PUS_MASK)
#define IOMUXC_PTC7_DSE_MASK                     0x1C0u
#define IOMUXC_PTC7_DSE_SHIFT                    6
#define IOMUXC_PTC7_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC7_DSE_SHIFT))&IOMUXC_PTC7_DSE_MASK)
#define IOMUXC_PTC7_HYS_MASK                     0x200u
#define IOMUXC_PTC7_HYS_SHIFT                    9
#define IOMUXC_PTC7_ODE_MASK                     0x400u
#define IOMUXC_PTC7_ODE_SHIFT                    10
#define IOMUXC_PTC7_SRE_MASK                     0x800u
#define IOMUXC_PTC7_SRE_SHIFT                    11
#define IOMUXC_PTC7_SPEED_MASK                   0x3000u
#define IOMUXC_PTC7_SPEED_SHIFT                  12
#define IOMUXC_PTC7_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC7_SPEED_SHIFT))&IOMUXC_PTC7_SPEED_MASK)
#define IOMUXC_PTC7_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC7_MUX_MODE_SHIFT               20
#define IOMUXC_PTC7_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC7_MUX_MODE_SHIFT))&IOMUXC_PTC7_MUX_MODE_MASK)
/* PTC8 Bit Fields */
#define IOMUXC_PTC8_IBE_MASK                     0x1u
#define IOMUXC_PTC8_IBE_SHIFT                    0
#define IOMUXC_PTC8_OBE_MASK                     0x2u
#define IOMUXC_PTC8_OBE_SHIFT                    1
#define IOMUXC_PTC8_PUE_MASK                     0x4u
#define IOMUXC_PTC8_PUE_SHIFT                    2
#define IOMUXC_PTC8_PKE_MASK                     0x8u
#define IOMUXC_PTC8_PKE_SHIFT                    3
#define IOMUXC_PTC8_PUS_MASK                     0x30u
#define IOMUXC_PTC8_PUS_SHIFT                    4
#define IOMUXC_PTC8_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC8_PUS_SHIFT))&IOMUXC_PTC8_PUS_MASK)
#define IOMUXC_PTC8_DSE_MASK                     0x1C0u
#define IOMUXC_PTC8_DSE_SHIFT                    6
#define IOMUXC_PTC8_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC8_DSE_SHIFT))&IOMUXC_PTC8_DSE_MASK)
#define IOMUXC_PTC8_HYS_MASK                     0x200u
#define IOMUXC_PTC8_HYS_SHIFT                    9
#define IOMUXC_PTC8_ODE_MASK                     0x400u
#define IOMUXC_PTC8_ODE_SHIFT                    10
#define IOMUXC_PTC8_SRE_MASK                     0x800u
#define IOMUXC_PTC8_SRE_SHIFT                    11
#define IOMUXC_PTC8_SPEED_MASK                   0x3000u
#define IOMUXC_PTC8_SPEED_SHIFT                  12
#define IOMUXC_PTC8_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC8_SPEED_SHIFT))&IOMUXC_PTC8_SPEED_MASK)
#define IOMUXC_PTC8_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC8_MUX_MODE_SHIFT               20
#define IOMUXC_PTC8_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC8_MUX_MODE_SHIFT))&IOMUXC_PTC8_MUX_MODE_MASK)
/* PTC9 Bit Fields */
#define IOMUXC_PTC9_IBE_MASK                     0x1u
#define IOMUXC_PTC9_IBE_SHIFT                    0
#define IOMUXC_PTC9_OBE_MASK                     0x2u
#define IOMUXC_PTC9_OBE_SHIFT                    1
#define IOMUXC_PTC9_PUE_MASK                     0x4u
#define IOMUXC_PTC9_PUE_SHIFT                    2
#define IOMUXC_PTC9_PKE_MASK                     0x8u
#define IOMUXC_PTC9_PKE_SHIFT                    3
#define IOMUXC_PTC9_PUS_MASK                     0x30u
#define IOMUXC_PTC9_PUS_SHIFT                    4
#define IOMUXC_PTC9_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC9_PUS_SHIFT))&IOMUXC_PTC9_PUS_MASK)
#define IOMUXC_PTC9_DSE_MASK                     0x1C0u
#define IOMUXC_PTC9_DSE_SHIFT                    6
#define IOMUXC_PTC9_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC9_DSE_SHIFT))&IOMUXC_PTC9_DSE_MASK)
#define IOMUXC_PTC9_HYS_MASK                     0x200u
#define IOMUXC_PTC9_HYS_SHIFT                    9
#define IOMUXC_PTC9_ODE_MASK                     0x400u
#define IOMUXC_PTC9_ODE_SHIFT                    10
#define IOMUXC_PTC9_SRE_MASK                     0x800u
#define IOMUXC_PTC9_SRE_SHIFT                    11
#define IOMUXC_PTC9_SPEED_MASK                   0x3000u
#define IOMUXC_PTC9_SPEED_SHIFT                  12
#define IOMUXC_PTC9_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC9_SPEED_SHIFT))&IOMUXC_PTC9_SPEED_MASK)
#define IOMUXC_PTC9_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTC9_MUX_MODE_SHIFT               20
#define IOMUXC_PTC9_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC9_MUX_MODE_SHIFT))&IOMUXC_PTC9_MUX_MODE_MASK)
/* PTC10 Bit Fields */
#define IOMUXC_PTC10_IBE_MASK                    0x1u
#define IOMUXC_PTC10_IBE_SHIFT                   0
#define IOMUXC_PTC10_OBE_MASK                    0x2u
#define IOMUXC_PTC10_OBE_SHIFT                   1
#define IOMUXC_PTC10_PUE_MASK                    0x4u
#define IOMUXC_PTC10_PUE_SHIFT                   2
#define IOMUXC_PTC10_PKE_MASK                    0x8u
#define IOMUXC_PTC10_PKE_SHIFT                   3
#define IOMUXC_PTC10_PUS_MASK                    0x30u
#define IOMUXC_PTC10_PUS_SHIFT                   4
#define IOMUXC_PTC10_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC10_PUS_SHIFT))&IOMUXC_PTC10_PUS_MASK)
#define IOMUXC_PTC10_DSE_MASK                    0x1C0u
#define IOMUXC_PTC10_DSE_SHIFT                   6
#define IOMUXC_PTC10_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC10_DSE_SHIFT))&IOMUXC_PTC10_DSE_MASK)
#define IOMUXC_PTC10_HYS_MASK                    0x200u
#define IOMUXC_PTC10_HYS_SHIFT                   9
#define IOMUXC_PTC10_ODE_MASK                    0x400u
#define IOMUXC_PTC10_ODE_SHIFT                   10
#define IOMUXC_PTC10_SRE_MASK                    0x800u
#define IOMUXC_PTC10_SRE_SHIFT                   11
#define IOMUXC_PTC10_SPEED_MASK                  0x3000u
#define IOMUXC_PTC10_SPEED_SHIFT                 12
#define IOMUXC_PTC10_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC10_SPEED_SHIFT))&IOMUXC_PTC10_SPEED_MASK)
#define IOMUXC_PTC10_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC10_MUX_MODE_SHIFT              20
#define IOMUXC_PTC10_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC10_MUX_MODE_SHIFT))&IOMUXC_PTC10_MUX_MODE_MASK)
/* PTC11 Bit Fields */
#define IOMUXC_PTC11_IBE_MASK                    0x1u
#define IOMUXC_PTC11_IBE_SHIFT                   0
#define IOMUXC_PTC11_OBE_MASK                    0x2u
#define IOMUXC_PTC11_OBE_SHIFT                   1
#define IOMUXC_PTC11_PUE_MASK                    0x4u
#define IOMUXC_PTC11_PUE_SHIFT                   2
#define IOMUXC_PTC11_PKE_MASK                    0x8u
#define IOMUXC_PTC11_PKE_SHIFT                   3
#define IOMUXC_PTC11_PUS_MASK                    0x30u
#define IOMUXC_PTC11_PUS_SHIFT                   4
#define IOMUXC_PTC11_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC11_PUS_SHIFT))&IOMUXC_PTC11_PUS_MASK)
#define IOMUXC_PTC11_DSE_MASK                    0x1C0u
#define IOMUXC_PTC11_DSE_SHIFT                   6
#define IOMUXC_PTC11_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC11_DSE_SHIFT))&IOMUXC_PTC11_DSE_MASK)
#define IOMUXC_PTC11_HYS_MASK                    0x200u
#define IOMUXC_PTC11_HYS_SHIFT                   9
#define IOMUXC_PTC11_ODE_MASK                    0x400u
#define IOMUXC_PTC11_ODE_SHIFT                   10
#define IOMUXC_PTC11_SRE_MASK                    0x800u
#define IOMUXC_PTC11_SRE_SHIFT                   11
#define IOMUXC_PTC11_SPEED_MASK                  0x3000u
#define IOMUXC_PTC11_SPEED_SHIFT                 12
#define IOMUXC_PTC11_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC11_SPEED_SHIFT))&IOMUXC_PTC11_SPEED_MASK)
#define IOMUXC_PTC11_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC11_MUX_MODE_SHIFT              20
#define IOMUXC_PTC11_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC11_MUX_MODE_SHIFT))&IOMUXC_PTC11_MUX_MODE_MASK)
/* PTC12 Bit Fields */
#define IOMUXC_PTC12_IBE_MASK                    0x1u
#define IOMUXC_PTC12_IBE_SHIFT                   0
#define IOMUXC_PTC12_OBE_MASK                    0x2u
#define IOMUXC_PTC12_OBE_SHIFT                   1
#define IOMUXC_PTC12_PUE_MASK                    0x4u
#define IOMUXC_PTC12_PUE_SHIFT                   2
#define IOMUXC_PTC12_PKE_MASK                    0x8u
#define IOMUXC_PTC12_PKE_SHIFT                   3
#define IOMUXC_PTC12_PUS_MASK                    0x30u
#define IOMUXC_PTC12_PUS_SHIFT                   4
#define IOMUXC_PTC12_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC12_PUS_SHIFT))&IOMUXC_PTC12_PUS_MASK)
#define IOMUXC_PTC12_DSE_MASK                    0x1C0u
#define IOMUXC_PTC12_DSE_SHIFT                   6
#define IOMUXC_PTC12_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC12_DSE_SHIFT))&IOMUXC_PTC12_DSE_MASK)
#define IOMUXC_PTC12_HYS_MASK                    0x200u
#define IOMUXC_PTC12_HYS_SHIFT                   9
#define IOMUXC_PTC12_ODE_MASK                    0x400u
#define IOMUXC_PTC12_ODE_SHIFT                   10
#define IOMUXC_PTC12_SRE_MASK                    0x800u
#define IOMUXC_PTC12_SRE_SHIFT                   11
#define IOMUXC_PTC12_SPEED_MASK                  0x3000u
#define IOMUXC_PTC12_SPEED_SHIFT                 12
#define IOMUXC_PTC12_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC12_SPEED_SHIFT))&IOMUXC_PTC12_SPEED_MASK)
#define IOMUXC_PTC12_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC12_MUX_MODE_SHIFT              20
#define IOMUXC_PTC12_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC12_MUX_MODE_SHIFT))&IOMUXC_PTC12_MUX_MODE_MASK)
/* PTC13 Bit Fields */
#define IOMUXC_PTC13_IBE_MASK                    0x1u
#define IOMUXC_PTC13_IBE_SHIFT                   0
#define IOMUXC_PTC13_OBE_MASK                    0x2u
#define IOMUXC_PTC13_OBE_SHIFT                   1
#define IOMUXC_PTC13_PUE_MASK                    0x4u
#define IOMUXC_PTC13_PUE_SHIFT                   2
#define IOMUXC_PTC13_PKE_MASK                    0x8u
#define IOMUXC_PTC13_PKE_SHIFT                   3
#define IOMUXC_PTC13_PUS_MASK                    0x30u
#define IOMUXC_PTC13_PUS_SHIFT                   4
#define IOMUXC_PTC13_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC13_PUS_SHIFT))&IOMUXC_PTC13_PUS_MASK)
#define IOMUXC_PTC13_DSE_MASK                    0x1C0u
#define IOMUXC_PTC13_DSE_SHIFT                   6
#define IOMUXC_PTC13_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC13_DSE_SHIFT))&IOMUXC_PTC13_DSE_MASK)
#define IOMUXC_PTC13_HYS_MASK                    0x200u
#define IOMUXC_PTC13_HYS_SHIFT                   9
#define IOMUXC_PTC13_ODE_MASK                    0x400u
#define IOMUXC_PTC13_ODE_SHIFT                   10
#define IOMUXC_PTC13_SRE_MASK                    0x800u
#define IOMUXC_PTC13_SRE_SHIFT                   11
#define IOMUXC_PTC13_SPEED_MASK                  0x3000u
#define IOMUXC_PTC13_SPEED_SHIFT                 12
#define IOMUXC_PTC13_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC13_SPEED_SHIFT))&IOMUXC_PTC13_SPEED_MASK)
#define IOMUXC_PTC13_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC13_MUX_MODE_SHIFT              20
#define IOMUXC_PTC13_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC13_MUX_MODE_SHIFT))&IOMUXC_PTC13_MUX_MODE_MASK)
/* PTC14 Bit Fields */
#define IOMUXC_PTC14_IBE_MASK                    0x1u
#define IOMUXC_PTC14_IBE_SHIFT                   0
#define IOMUXC_PTC14_OBE_MASK                    0x2u
#define IOMUXC_PTC14_OBE_SHIFT                   1
#define IOMUXC_PTC14_PUE_MASK                    0x4u
#define IOMUXC_PTC14_PUE_SHIFT                   2
#define IOMUXC_PTC14_PKE_MASK                    0x8u
#define IOMUXC_PTC14_PKE_SHIFT                   3
#define IOMUXC_PTC14_PUS_MASK                    0x30u
#define IOMUXC_PTC14_PUS_SHIFT                   4
#define IOMUXC_PTC14_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC14_PUS_SHIFT))&IOMUXC_PTC14_PUS_MASK)
#define IOMUXC_PTC14_DSE_MASK                    0x1C0u
#define IOMUXC_PTC14_DSE_SHIFT                   6
#define IOMUXC_PTC14_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC14_DSE_SHIFT))&IOMUXC_PTC14_DSE_MASK)
#define IOMUXC_PTC14_HYS_MASK                    0x200u
#define IOMUXC_PTC14_HYS_SHIFT                   9
#define IOMUXC_PTC14_ODE_MASK                    0x400u
#define IOMUXC_PTC14_ODE_SHIFT                   10
#define IOMUXC_PTC14_SRE_MASK                    0x800u
#define IOMUXC_PTC14_SRE_SHIFT                   11
#define IOMUXC_PTC14_SPEED_MASK                  0x3000u
#define IOMUXC_PTC14_SPEED_SHIFT                 12
#define IOMUXC_PTC14_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC14_SPEED_SHIFT))&IOMUXC_PTC14_SPEED_MASK)
#define IOMUXC_PTC14_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC14_MUX_MODE_SHIFT              20
#define IOMUXC_PTC14_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC14_MUX_MODE_SHIFT))&IOMUXC_PTC14_MUX_MODE_MASK)
/* PTC15 Bit Fields */
#define IOMUXC_PTC15_IBE_MASK                    0x1u
#define IOMUXC_PTC15_IBE_SHIFT                   0
#define IOMUXC_PTC15_OBE_MASK                    0x2u
#define IOMUXC_PTC15_OBE_SHIFT                   1
#define IOMUXC_PTC15_PUE_MASK                    0x4u
#define IOMUXC_PTC15_PUE_SHIFT                   2
#define IOMUXC_PTC15_PKE_MASK                    0x8u
#define IOMUXC_PTC15_PKE_SHIFT                   3
#define IOMUXC_PTC15_PUS_MASK                    0x30u
#define IOMUXC_PTC15_PUS_SHIFT                   4
#define IOMUXC_PTC15_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC15_PUS_SHIFT))&IOMUXC_PTC15_PUS_MASK)
#define IOMUXC_PTC15_DSE_MASK                    0x1C0u
#define IOMUXC_PTC15_DSE_SHIFT                   6
#define IOMUXC_PTC15_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC15_DSE_SHIFT))&IOMUXC_PTC15_DSE_MASK)
#define IOMUXC_PTC15_HYS_MASK                    0x200u
#define IOMUXC_PTC15_HYS_SHIFT                   9
#define IOMUXC_PTC15_ODE_MASK                    0x400u
#define IOMUXC_PTC15_ODE_SHIFT                   10
#define IOMUXC_PTC15_SRE_MASK                    0x800u
#define IOMUXC_PTC15_SRE_SHIFT                   11
#define IOMUXC_PTC15_SPEED_MASK                  0x3000u
#define IOMUXC_PTC15_SPEED_SHIFT                 12
#define IOMUXC_PTC15_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC15_SPEED_SHIFT))&IOMUXC_PTC15_SPEED_MASK)
#define IOMUXC_PTC15_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC15_MUX_MODE_SHIFT              20
#define IOMUXC_PTC15_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC15_MUX_MODE_SHIFT))&IOMUXC_PTC15_MUX_MODE_MASK)
/* PTC16 Bit Fields */
#define IOMUXC_PTC16_IBE_MASK                    0x1u
#define IOMUXC_PTC16_IBE_SHIFT                   0
#define IOMUXC_PTC16_OBE_MASK                    0x2u
#define IOMUXC_PTC16_OBE_SHIFT                   1
#define IOMUXC_PTC16_PUE_MASK                    0x4u
#define IOMUXC_PTC16_PUE_SHIFT                   2
#define IOMUXC_PTC16_PKE_MASK                    0x8u
#define IOMUXC_PTC16_PKE_SHIFT                   3
#define IOMUXC_PTC16_PUS_MASK                    0x30u
#define IOMUXC_PTC16_PUS_SHIFT                   4
#define IOMUXC_PTC16_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC16_PUS_SHIFT))&IOMUXC_PTC16_PUS_MASK)
#define IOMUXC_PTC16_DSE_MASK                    0x1C0u
#define IOMUXC_PTC16_DSE_SHIFT                   6
#define IOMUXC_PTC16_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC16_DSE_SHIFT))&IOMUXC_PTC16_DSE_MASK)
#define IOMUXC_PTC16_HYS_MASK                    0x200u
#define IOMUXC_PTC16_HYS_SHIFT                   9
#define IOMUXC_PTC16_ODE_MASK                    0x400u
#define IOMUXC_PTC16_ODE_SHIFT                   10
#define IOMUXC_PTC16_SRE_MASK                    0x800u
#define IOMUXC_PTC16_SRE_SHIFT                   11
#define IOMUXC_PTC16_SPEED_MASK                  0x3000u
#define IOMUXC_PTC16_SPEED_SHIFT                 12
#define IOMUXC_PTC16_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC16_SPEED_SHIFT))&IOMUXC_PTC16_SPEED_MASK)
#define IOMUXC_PTC16_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC16_MUX_MODE_SHIFT              20
#define IOMUXC_PTC16_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC16_MUX_MODE_SHIFT))&IOMUXC_PTC16_MUX_MODE_MASK)
/* PTC17 Bit Fields */
#define IOMUXC_PTC17_IBE_MASK                    0x1u
#define IOMUXC_PTC17_IBE_SHIFT                   0
#define IOMUXC_PTC17_OBE_MASK                    0x2u
#define IOMUXC_PTC17_OBE_SHIFT                   1
#define IOMUXC_PTC17_PUE_MASK                    0x4u
#define IOMUXC_PTC17_PUE_SHIFT                   2
#define IOMUXC_PTC17_PKE_MASK                    0x8u
#define IOMUXC_PTC17_PKE_SHIFT                   3
#define IOMUXC_PTC17_PUS_MASK                    0x30u
#define IOMUXC_PTC17_PUS_SHIFT                   4
#define IOMUXC_PTC17_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC17_PUS_SHIFT))&IOMUXC_PTC17_PUS_MASK)
#define IOMUXC_PTC17_DSE_MASK                    0x1C0u
#define IOMUXC_PTC17_DSE_SHIFT                   6
#define IOMUXC_PTC17_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC17_DSE_SHIFT))&IOMUXC_PTC17_DSE_MASK)
#define IOMUXC_PTC17_HYS_MASK                    0x200u
#define IOMUXC_PTC17_HYS_SHIFT                   9
#define IOMUXC_PTC17_ODE_MASK                    0x400u
#define IOMUXC_PTC17_ODE_SHIFT                   10
#define IOMUXC_PTC17_SRE_MASK                    0x800u
#define IOMUXC_PTC17_SRE_SHIFT                   11
#define IOMUXC_PTC17_SPEED_MASK                  0x3000u
#define IOMUXC_PTC17_SPEED_SHIFT                 12
#define IOMUXC_PTC17_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC17_SPEED_SHIFT))&IOMUXC_PTC17_SPEED_MASK)
#define IOMUXC_PTC17_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC17_MUX_MODE_SHIFT              20
#define IOMUXC_PTC17_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC17_MUX_MODE_SHIFT))&IOMUXC_PTC17_MUX_MODE_MASK)
/* PTD31 Bit Fields */
#define IOMUXC_PTD31_IBE_MASK                    0x1u
#define IOMUXC_PTD31_IBE_SHIFT                   0
#define IOMUXC_PTD31_OBE_MASK                    0x2u
#define IOMUXC_PTD31_OBE_SHIFT                   1
#define IOMUXC_PTD31_PUE_MASK                    0x4u
#define IOMUXC_PTD31_PUE_SHIFT                   2
#define IOMUXC_PTD31_PKE_MASK                    0x8u
#define IOMUXC_PTD31_PKE_SHIFT                   3
#define IOMUXC_PTD31_PUS_MASK                    0x30u
#define IOMUXC_PTD31_PUS_SHIFT                   4
#define IOMUXC_PTD31_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD31_PUS_SHIFT))&IOMUXC_PTD31_PUS_MASK)
#define IOMUXC_PTD31_DSE_MASK                    0x1C0u
#define IOMUXC_PTD31_DSE_SHIFT                   6
#define IOMUXC_PTD31_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD31_DSE_SHIFT))&IOMUXC_PTD31_DSE_MASK)
#define IOMUXC_PTD31_HYS_MASK                    0x200u
#define IOMUXC_PTD31_HYS_SHIFT                   9
#define IOMUXC_PTD31_ODE_MASK                    0x400u
#define IOMUXC_PTD31_ODE_SHIFT                   10
#define IOMUXC_PTD31_SRE_MASK                    0x800u
#define IOMUXC_PTD31_SRE_SHIFT                   11
#define IOMUXC_PTD31_SPEED_MASK                  0x3000u
#define IOMUXC_PTD31_SPEED_SHIFT                 12
#define IOMUXC_PTD31_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD31_SPEED_SHIFT))&IOMUXC_PTD31_SPEED_MASK)
#define IOMUXC_PTD31_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD31_MUX_MODE_SHIFT              20
#define IOMUXC_PTD31_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD31_MUX_MODE_SHIFT))&IOMUXC_PTD31_MUX_MODE_MASK)
/* PTD30 Bit Fields */
#define IOMUXC_PTD30_IBE_MASK                    0x1u
#define IOMUXC_PTD30_IBE_SHIFT                   0
#define IOMUXC_PTD30_OBE_MASK                    0x2u
#define IOMUXC_PTD30_OBE_SHIFT                   1
#define IOMUXC_PTD30_PUE_MASK                    0x4u
#define IOMUXC_PTD30_PUE_SHIFT                   2
#define IOMUXC_PTD30_PKE_MASK                    0x8u
#define IOMUXC_PTD30_PKE_SHIFT                   3
#define IOMUXC_PTD30_PUS_MASK                    0x30u
#define IOMUXC_PTD30_PUS_SHIFT                   4
#define IOMUXC_PTD30_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD30_PUS_SHIFT))&IOMUXC_PTD30_PUS_MASK)
#define IOMUXC_PTD30_DSE_MASK                    0x1C0u
#define IOMUXC_PTD30_DSE_SHIFT                   6
#define IOMUXC_PTD30_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD30_DSE_SHIFT))&IOMUXC_PTD30_DSE_MASK)
#define IOMUXC_PTD30_HYS_MASK                    0x200u
#define IOMUXC_PTD30_HYS_SHIFT                   9
#define IOMUXC_PTD30_ODE_MASK                    0x400u
#define IOMUXC_PTD30_ODE_SHIFT                   10
#define IOMUXC_PTD30_SRE_MASK                    0x800u
#define IOMUXC_PTD30_SRE_SHIFT                   11
#define IOMUXC_PTD30_SPEED_MASK                  0x3000u
#define IOMUXC_PTD30_SPEED_SHIFT                 12
#define IOMUXC_PTD30_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD30_SPEED_SHIFT))&IOMUXC_PTD30_SPEED_MASK)
#define IOMUXC_PTD30_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD30_MUX_MODE_SHIFT              20
#define IOMUXC_PTD30_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD30_MUX_MODE_SHIFT))&IOMUXC_PTD30_MUX_MODE_MASK)
/* PTD29 Bit Fields */
#define IOMUXC_PTD29_IBE_MASK                    0x1u
#define IOMUXC_PTD29_IBE_SHIFT                   0
#define IOMUXC_PTD29_OBE_MASK                    0x2u
#define IOMUXC_PTD29_OBE_SHIFT                   1
#define IOMUXC_PTD29_PUE_MASK                    0x4u
#define IOMUXC_PTD29_PUE_SHIFT                   2
#define IOMUXC_PTD29_PKE_MASK                    0x8u
#define IOMUXC_PTD29_PKE_SHIFT                   3
#define IOMUXC_PTD29_PUS_MASK                    0x30u
#define IOMUXC_PTD29_PUS_SHIFT                   4
#define IOMUXC_PTD29_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD29_PUS_SHIFT))&IOMUXC_PTD29_PUS_MASK)
#define IOMUXC_PTD29_DSE_MASK                    0x1C0u
#define IOMUXC_PTD29_DSE_SHIFT                   6
#define IOMUXC_PTD29_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD29_DSE_SHIFT))&IOMUXC_PTD29_DSE_MASK)
#define IOMUXC_PTD29_HYS_MASK                    0x200u
#define IOMUXC_PTD29_HYS_SHIFT                   9
#define IOMUXC_PTD29_ODE_MASK                    0x400u
#define IOMUXC_PTD29_ODE_SHIFT                   10
#define IOMUXC_PTD29_SRE_MASK                    0x800u
#define IOMUXC_PTD29_SRE_SHIFT                   11
#define IOMUXC_PTD29_SPEED_MASK                  0x3000u
#define IOMUXC_PTD29_SPEED_SHIFT                 12
#define IOMUXC_PTD29_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD29_SPEED_SHIFT))&IOMUXC_PTD29_SPEED_MASK)
#define IOMUXC_PTD29_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD29_MUX_MODE_SHIFT              20
#define IOMUXC_PTD29_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD29_MUX_MODE_SHIFT))&IOMUXC_PTD29_MUX_MODE_MASK)
/* PTD28 Bit Fields */
#define IOMUXC_PTD28_IBE_MASK                    0x1u
#define IOMUXC_PTD28_IBE_SHIFT                   0
#define IOMUXC_PTD28_OBE_MASK                    0x2u
#define IOMUXC_PTD28_OBE_SHIFT                   1
#define IOMUXC_PTD28_PUE_MASK                    0x4u
#define IOMUXC_PTD28_PUE_SHIFT                   2
#define IOMUXC_PTD28_PKE_MASK                    0x8u
#define IOMUXC_PTD28_PKE_SHIFT                   3
#define IOMUXC_PTD28_PUS_MASK                    0x30u
#define IOMUXC_PTD28_PUS_SHIFT                   4
#define IOMUXC_PTD28_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD28_PUS_SHIFT))&IOMUXC_PTD28_PUS_MASK)
#define IOMUXC_PTD28_DSE_MASK                    0x1C0u
#define IOMUXC_PTD28_DSE_SHIFT                   6
#define IOMUXC_PTD28_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD28_DSE_SHIFT))&IOMUXC_PTD28_DSE_MASK)
#define IOMUXC_PTD28_HYS_MASK                    0x200u
#define IOMUXC_PTD28_HYS_SHIFT                   9
#define IOMUXC_PTD28_ODE_MASK                    0x400u
#define IOMUXC_PTD28_ODE_SHIFT                   10
#define IOMUXC_PTD28_SRE_MASK                    0x800u
#define IOMUXC_PTD28_SRE_SHIFT                   11
#define IOMUXC_PTD28_SPEED_MASK                  0x3000u
#define IOMUXC_PTD28_SPEED_SHIFT                 12
#define IOMUXC_PTD28_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD28_SPEED_SHIFT))&IOMUXC_PTD28_SPEED_MASK)
#define IOMUXC_PTD28_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD28_MUX_MODE_SHIFT              20
#define IOMUXC_PTD28_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD28_MUX_MODE_SHIFT))&IOMUXC_PTD28_MUX_MODE_MASK)
/* PTD27 Bit Fields */
#define IOMUXC_PTD27_IBE_MASK                    0x1u
#define IOMUXC_PTD27_IBE_SHIFT                   0
#define IOMUXC_PTD27_OBE_MASK                    0x2u
#define IOMUXC_PTD27_OBE_SHIFT                   1
#define IOMUXC_PTD27_PUE_MASK                    0x4u
#define IOMUXC_PTD27_PUE_SHIFT                   2
#define IOMUXC_PTD27_PKE_MASK                    0x8u
#define IOMUXC_PTD27_PKE_SHIFT                   3
#define IOMUXC_PTD27_PUS_MASK                    0x30u
#define IOMUXC_PTD27_PUS_SHIFT                   4
#define IOMUXC_PTD27_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD27_PUS_SHIFT))&IOMUXC_PTD27_PUS_MASK)
#define IOMUXC_PTD27_DSE_MASK                    0x1C0u
#define IOMUXC_PTD27_DSE_SHIFT                   6
#define IOMUXC_PTD27_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD27_DSE_SHIFT))&IOMUXC_PTD27_DSE_MASK)
#define IOMUXC_PTD27_HYS_MASK                    0x200u
#define IOMUXC_PTD27_HYS_SHIFT                   9
#define IOMUXC_PTD27_ODE_MASK                    0x400u
#define IOMUXC_PTD27_ODE_SHIFT                   10
#define IOMUXC_PTD27_SRE_MASK                    0x800u
#define IOMUXC_PTD27_SRE_SHIFT                   11
#define IOMUXC_PTD27_SPEED_MASK                  0x3000u
#define IOMUXC_PTD27_SPEED_SHIFT                 12
#define IOMUXC_PTD27_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD27_SPEED_SHIFT))&IOMUXC_PTD27_SPEED_MASK)
#define IOMUXC_PTD27_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD27_MUX_MODE_SHIFT              20
#define IOMUXC_PTD27_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD27_MUX_MODE_SHIFT))&IOMUXC_PTD27_MUX_MODE_MASK)
/* PTD26 Bit Fields */
#define IOMUXC_PTD26_IBE_MASK                    0x1u
#define IOMUXC_PTD26_IBE_SHIFT                   0
#define IOMUXC_PTD26_OBE_MASK                    0x2u
#define IOMUXC_PTD26_OBE_SHIFT                   1
#define IOMUXC_PTD26_PUE_MASK                    0x4u
#define IOMUXC_PTD26_PUE_SHIFT                   2
#define IOMUXC_PTD26_PKE_MASK                    0x8u
#define IOMUXC_PTD26_PKE_SHIFT                   3
#define IOMUXC_PTD26_PUS_MASK                    0x30u
#define IOMUXC_PTD26_PUS_SHIFT                   4
#define IOMUXC_PTD26_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD26_PUS_SHIFT))&IOMUXC_PTD26_PUS_MASK)
#define IOMUXC_PTD26_DSE_MASK                    0x1C0u
#define IOMUXC_PTD26_DSE_SHIFT                   6
#define IOMUXC_PTD26_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD26_DSE_SHIFT))&IOMUXC_PTD26_DSE_MASK)
#define IOMUXC_PTD26_HYS_MASK                    0x200u
#define IOMUXC_PTD26_HYS_SHIFT                   9
#define IOMUXC_PTD26_ODE_MASK                    0x400u
#define IOMUXC_PTD26_ODE_SHIFT                   10
#define IOMUXC_PTD26_SRE_MASK                    0x800u
#define IOMUXC_PTD26_SRE_SHIFT                   11
#define IOMUXC_PTD26_SPEED_MASK                  0x3000u
#define IOMUXC_PTD26_SPEED_SHIFT                 12
#define IOMUXC_PTD26_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD26_SPEED_SHIFT))&IOMUXC_PTD26_SPEED_MASK)
#define IOMUXC_PTD26_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD26_MUX_MODE_SHIFT              20
#define IOMUXC_PTD26_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD26_MUX_MODE_SHIFT))&IOMUXC_PTD26_MUX_MODE_MASK)
/* PTD25 Bit Fields */
#define IOMUXC_PTD25_IBE_MASK                    0x1u
#define IOMUXC_PTD25_IBE_SHIFT                   0
#define IOMUXC_PTD25_OBE_MASK                    0x2u
#define IOMUXC_PTD25_OBE_SHIFT                   1
#define IOMUXC_PTD25_PUE_MASK                    0x4u
#define IOMUXC_PTD25_PUE_SHIFT                   2
#define IOMUXC_PTD25_PKE_MASK                    0x8u
#define IOMUXC_PTD25_PKE_SHIFT                   3
#define IOMUXC_PTD25_PUS_MASK                    0x30u
#define IOMUXC_PTD25_PUS_SHIFT                   4
#define IOMUXC_PTD25_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD25_PUS_SHIFT))&IOMUXC_PTD25_PUS_MASK)
#define IOMUXC_PTD25_DSE_MASK                    0x1C0u
#define IOMUXC_PTD25_DSE_SHIFT                   6
#define IOMUXC_PTD25_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD25_DSE_SHIFT))&IOMUXC_PTD25_DSE_MASK)
#define IOMUXC_PTD25_HYS_MASK                    0x200u
#define IOMUXC_PTD25_HYS_SHIFT                   9
#define IOMUXC_PTD25_ODE_MASK                    0x400u
#define IOMUXC_PTD25_ODE_SHIFT                   10
#define IOMUXC_PTD25_SRE_MASK                    0x800u
#define IOMUXC_PTD25_SRE_SHIFT                   11
#define IOMUXC_PTD25_SPEED_MASK                  0x3000u
#define IOMUXC_PTD25_SPEED_SHIFT                 12
#define IOMUXC_PTD25_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD25_SPEED_SHIFT))&IOMUXC_PTD25_SPEED_MASK)
#define IOMUXC_PTD25_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD25_MUX_MODE_SHIFT              20
#define IOMUXC_PTD25_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD25_MUX_MODE_SHIFT))&IOMUXC_PTD25_MUX_MODE_MASK)
/* PTD24 Bit Fields */
#define IOMUXC_PTD24_IBE_MASK                    0x1u
#define IOMUXC_PTD24_IBE_SHIFT                   0
#define IOMUXC_PTD24_OBE_MASK                    0x2u
#define IOMUXC_PTD24_OBE_SHIFT                   1
#define IOMUXC_PTD24_PUE_MASK                    0x4u
#define IOMUXC_PTD24_PUE_SHIFT                   2
#define IOMUXC_PTD24_PKE_MASK                    0x8u
#define IOMUXC_PTD24_PKE_SHIFT                   3
#define IOMUXC_PTD24_PUS_MASK                    0x30u
#define IOMUXC_PTD24_PUS_SHIFT                   4
#define IOMUXC_PTD24_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD24_PUS_SHIFT))&IOMUXC_PTD24_PUS_MASK)
#define IOMUXC_PTD24_DSE_MASK                    0x1C0u
#define IOMUXC_PTD24_DSE_SHIFT                   6
#define IOMUXC_PTD24_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD24_DSE_SHIFT))&IOMUXC_PTD24_DSE_MASK)
#define IOMUXC_PTD24_HYS_MASK                    0x200u
#define IOMUXC_PTD24_HYS_SHIFT                   9
#define IOMUXC_PTD24_ODE_MASK                    0x400u
#define IOMUXC_PTD24_ODE_SHIFT                   10
#define IOMUXC_PTD24_SRE_MASK                    0x800u
#define IOMUXC_PTD24_SRE_SHIFT                   11
#define IOMUXC_PTD24_SPEED_MASK                  0x3000u
#define IOMUXC_PTD24_SPEED_SHIFT                 12
#define IOMUXC_PTD24_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD24_SPEED_SHIFT))&IOMUXC_PTD24_SPEED_MASK)
#define IOMUXC_PTD24_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD24_MUX_MODE_SHIFT              20
#define IOMUXC_PTD24_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD24_MUX_MODE_SHIFT))&IOMUXC_PTD24_MUX_MODE_MASK)
/* PTD23 Bit Fields */
#define IOMUXC_PTD23_IBE_MASK                    0x1u
#define IOMUXC_PTD23_IBE_SHIFT                   0
#define IOMUXC_PTD23_OBE_MASK                    0x2u
#define IOMUXC_PTD23_OBE_SHIFT                   1
#define IOMUXC_PTD23_PUE_MASK                    0x4u
#define IOMUXC_PTD23_PUE_SHIFT                   2
#define IOMUXC_PTD23_PKE_MASK                    0x8u
#define IOMUXC_PTD23_PKE_SHIFT                   3
#define IOMUXC_PTD23_PUS_MASK                    0x30u
#define IOMUXC_PTD23_PUS_SHIFT                   4
#define IOMUXC_PTD23_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD23_PUS_SHIFT))&IOMUXC_PTD23_PUS_MASK)
#define IOMUXC_PTD23_DSE_MASK                    0x1C0u
#define IOMUXC_PTD23_DSE_SHIFT                   6
#define IOMUXC_PTD23_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD23_DSE_SHIFT))&IOMUXC_PTD23_DSE_MASK)
#define IOMUXC_PTD23_HYS_MASK                    0x200u
#define IOMUXC_PTD23_HYS_SHIFT                   9
#define IOMUXC_PTD23_ODE_MASK                    0x400u
#define IOMUXC_PTD23_ODE_SHIFT                   10
#define IOMUXC_PTD23_SRE_MASK                    0x800u
#define IOMUXC_PTD23_SRE_SHIFT                   11
#define IOMUXC_PTD23_SPEED_MASK                  0x3000u
#define IOMUXC_PTD23_SPEED_SHIFT                 12
#define IOMUXC_PTD23_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD23_SPEED_SHIFT))&IOMUXC_PTD23_SPEED_MASK)
#define IOMUXC_PTD23_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD23_MUX_MODE_SHIFT              20
#define IOMUXC_PTD23_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD23_MUX_MODE_SHIFT))&IOMUXC_PTD23_MUX_MODE_MASK)
/* PTD22 Bit Fields */
#define IOMUXC_PTD22_IBE_MASK                    0x1u
#define IOMUXC_PTD22_IBE_SHIFT                   0
#define IOMUXC_PTD22_OBE_MASK                    0x2u
#define IOMUXC_PTD22_OBE_SHIFT                   1
#define IOMUXC_PTD22_PUE_MASK                    0x4u
#define IOMUXC_PTD22_PUE_SHIFT                   2
#define IOMUXC_PTD22_PKE_MASK                    0x8u
#define IOMUXC_PTD22_PKE_SHIFT                   3
#define IOMUXC_PTD22_PUS_MASK                    0x30u
#define IOMUXC_PTD22_PUS_SHIFT                   4
#define IOMUXC_PTD22_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD22_PUS_SHIFT))&IOMUXC_PTD22_PUS_MASK)
#define IOMUXC_PTD22_DSE_MASK                    0x1C0u
#define IOMUXC_PTD22_DSE_SHIFT                   6
#define IOMUXC_PTD22_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD22_DSE_SHIFT))&IOMUXC_PTD22_DSE_MASK)
#define IOMUXC_PTD22_HYS_MASK                    0x200u
#define IOMUXC_PTD22_HYS_SHIFT                   9
#define IOMUXC_PTD22_ODE_MASK                    0x400u
#define IOMUXC_PTD22_ODE_SHIFT                   10
#define IOMUXC_PTD22_SRE_MASK                    0x800u
#define IOMUXC_PTD22_SRE_SHIFT                   11
#define IOMUXC_PTD22_SPEED_MASK                  0x3000u
#define IOMUXC_PTD22_SPEED_SHIFT                 12
#define IOMUXC_PTD22_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD22_SPEED_SHIFT))&IOMUXC_PTD22_SPEED_MASK)
#define IOMUXC_PTD22_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD22_MUX_MODE_SHIFT              20
#define IOMUXC_PTD22_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD22_MUX_MODE_SHIFT))&IOMUXC_PTD22_MUX_MODE_MASK)
/* PTD21 Bit Fields */
#define IOMUXC_PTD21_IBE_MASK                    0x1u
#define IOMUXC_PTD21_IBE_SHIFT                   0
#define IOMUXC_PTD21_OBE_MASK                    0x2u
#define IOMUXC_PTD21_OBE_SHIFT                   1
#define IOMUXC_PTD21_PUE_MASK                    0x4u
#define IOMUXC_PTD21_PUE_SHIFT                   2
#define IOMUXC_PTD21_PKE_MASK                    0x8u
#define IOMUXC_PTD21_PKE_SHIFT                   3
#define IOMUXC_PTD21_PUS_MASK                    0x30u
#define IOMUXC_PTD21_PUS_SHIFT                   4
#define IOMUXC_PTD21_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD21_PUS_SHIFT))&IOMUXC_PTD21_PUS_MASK)
#define IOMUXC_PTD21_DSE_MASK                    0x1C0u
#define IOMUXC_PTD21_DSE_SHIFT                   6
#define IOMUXC_PTD21_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD21_DSE_SHIFT))&IOMUXC_PTD21_DSE_MASK)
#define IOMUXC_PTD21_HYS_MASK                    0x200u
#define IOMUXC_PTD21_HYS_SHIFT                   9
#define IOMUXC_PTD21_ODE_MASK                    0x400u
#define IOMUXC_PTD21_ODE_SHIFT                   10
#define IOMUXC_PTD21_SRE_MASK                    0x800u
#define IOMUXC_PTD21_SRE_SHIFT                   11
#define IOMUXC_PTD21_SPEED_MASK                  0x3000u
#define IOMUXC_PTD21_SPEED_SHIFT                 12
#define IOMUXC_PTD21_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD21_SPEED_SHIFT))&IOMUXC_PTD21_SPEED_MASK)
#define IOMUXC_PTD21_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD21_MUX_MODE_SHIFT              20
#define IOMUXC_PTD21_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD21_MUX_MODE_SHIFT))&IOMUXC_PTD21_MUX_MODE_MASK)
/* PTD20 Bit Fields */
#define IOMUXC_PTD20_IBE_MASK                    0x1u
#define IOMUXC_PTD20_IBE_SHIFT                   0
#define IOMUXC_PTD20_OBE_MASK                    0x2u
#define IOMUXC_PTD20_OBE_SHIFT                   1
#define IOMUXC_PTD20_PUE_MASK                    0x4u
#define IOMUXC_PTD20_PUE_SHIFT                   2
#define IOMUXC_PTD20_PKE_MASK                    0x8u
#define IOMUXC_PTD20_PKE_SHIFT                   3
#define IOMUXC_PTD20_PUS_MASK                    0x30u
#define IOMUXC_PTD20_PUS_SHIFT                   4
#define IOMUXC_PTD20_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD20_PUS_SHIFT))&IOMUXC_PTD20_PUS_MASK)
#define IOMUXC_PTD20_DSE_MASK                    0x1C0u
#define IOMUXC_PTD20_DSE_SHIFT                   6
#define IOMUXC_PTD20_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD20_DSE_SHIFT))&IOMUXC_PTD20_DSE_MASK)
#define IOMUXC_PTD20_HYS_MASK                    0x200u
#define IOMUXC_PTD20_HYS_SHIFT                   9
#define IOMUXC_PTD20_ODE_MASK                    0x400u
#define IOMUXC_PTD20_ODE_SHIFT                   10
#define IOMUXC_PTD20_SRE_MASK                    0x800u
#define IOMUXC_PTD20_SRE_SHIFT                   11
#define IOMUXC_PTD20_SPEED_MASK                  0x3000u
#define IOMUXC_PTD20_SPEED_SHIFT                 12
#define IOMUXC_PTD20_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD20_SPEED_SHIFT))&IOMUXC_PTD20_SPEED_MASK)
#define IOMUXC_PTD20_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD20_MUX_MODE_SHIFT              20
#define IOMUXC_PTD20_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD20_MUX_MODE_SHIFT))&IOMUXC_PTD20_MUX_MODE_MASK)
/* PTD19 Bit Fields */
#define IOMUXC_PTD19_IBE_MASK                    0x1u
#define IOMUXC_PTD19_IBE_SHIFT                   0
#define IOMUXC_PTD19_OBE_MASK                    0x2u
#define IOMUXC_PTD19_OBE_SHIFT                   1
#define IOMUXC_PTD19_PUE_MASK                    0x4u
#define IOMUXC_PTD19_PUE_SHIFT                   2
#define IOMUXC_PTD19_PKE_MASK                    0x8u
#define IOMUXC_PTD19_PKE_SHIFT                   3
#define IOMUXC_PTD19_PUS_MASK                    0x30u
#define IOMUXC_PTD19_PUS_SHIFT                   4
#define IOMUXC_PTD19_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD19_PUS_SHIFT))&IOMUXC_PTD19_PUS_MASK)
#define IOMUXC_PTD19_DSE_MASK                    0x1C0u
#define IOMUXC_PTD19_DSE_SHIFT                   6
#define IOMUXC_PTD19_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD19_DSE_SHIFT))&IOMUXC_PTD19_DSE_MASK)
#define IOMUXC_PTD19_HYS_MASK                    0x200u
#define IOMUXC_PTD19_HYS_SHIFT                   9
#define IOMUXC_PTD19_ODE_MASK                    0x400u
#define IOMUXC_PTD19_ODE_SHIFT                   10
#define IOMUXC_PTD19_SRE_MASK                    0x800u
#define IOMUXC_PTD19_SRE_SHIFT                   11
#define IOMUXC_PTD19_SPEED_MASK                  0x3000u
#define IOMUXC_PTD19_SPEED_SHIFT                 12
#define IOMUXC_PTD19_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD19_SPEED_SHIFT))&IOMUXC_PTD19_SPEED_MASK)
#define IOMUXC_PTD19_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD19_MUX_MODE_SHIFT              20
#define IOMUXC_PTD19_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD19_MUX_MODE_SHIFT))&IOMUXC_PTD19_MUX_MODE_MASK)
/* PTD18 Bit Fields */
#define IOMUXC_PTD18_IBE_MASK                    0x1u
#define IOMUXC_PTD18_IBE_SHIFT                   0
#define IOMUXC_PTD18_OBE_MASK                    0x2u
#define IOMUXC_PTD18_OBE_SHIFT                   1
#define IOMUXC_PTD18_PUE_MASK                    0x4u
#define IOMUXC_PTD18_PUE_SHIFT                   2
#define IOMUXC_PTD18_PKE_MASK                    0x8u
#define IOMUXC_PTD18_PKE_SHIFT                   3
#define IOMUXC_PTD18_PUS_MASK                    0x30u
#define IOMUXC_PTD18_PUS_SHIFT                   4
#define IOMUXC_PTD18_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD18_PUS_SHIFT))&IOMUXC_PTD18_PUS_MASK)
#define IOMUXC_PTD18_DSE_MASK                    0x1C0u
#define IOMUXC_PTD18_DSE_SHIFT                   6
#define IOMUXC_PTD18_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD18_DSE_SHIFT))&IOMUXC_PTD18_DSE_MASK)
#define IOMUXC_PTD18_HYS_MASK                    0x200u
#define IOMUXC_PTD18_HYS_SHIFT                   9
#define IOMUXC_PTD18_ODE_MASK                    0x400u
#define IOMUXC_PTD18_ODE_SHIFT                   10
#define IOMUXC_PTD18_SRE_MASK                    0x800u
#define IOMUXC_PTD18_SRE_SHIFT                   11
#define IOMUXC_PTD18_SPEED_MASK                  0x3000u
#define IOMUXC_PTD18_SPEED_SHIFT                 12
#define IOMUXC_PTD18_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD18_SPEED_SHIFT))&IOMUXC_PTD18_SPEED_MASK)
#define IOMUXC_PTD18_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD18_MUX_MODE_SHIFT              20
#define IOMUXC_PTD18_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD18_MUX_MODE_SHIFT))&IOMUXC_PTD18_MUX_MODE_MASK)
/* PTD17 Bit Fields */
#define IOMUXC_PTD17_IBE_MASK                    0x1u
#define IOMUXC_PTD17_IBE_SHIFT                   0
#define IOMUXC_PTD17_OBE_MASK                    0x2u
#define IOMUXC_PTD17_OBE_SHIFT                   1
#define IOMUXC_PTD17_PUE_MASK                    0x4u
#define IOMUXC_PTD17_PUE_SHIFT                   2
#define IOMUXC_PTD17_PKE_MASK                    0x8u
#define IOMUXC_PTD17_PKE_SHIFT                   3
#define IOMUXC_PTD17_PUS_MASK                    0x30u
#define IOMUXC_PTD17_PUS_SHIFT                   4
#define IOMUXC_PTD17_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD17_PUS_SHIFT))&IOMUXC_PTD17_PUS_MASK)
#define IOMUXC_PTD17_DSE_MASK                    0x1C0u
#define IOMUXC_PTD17_DSE_SHIFT                   6
#define IOMUXC_PTD17_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD17_DSE_SHIFT))&IOMUXC_PTD17_DSE_MASK)
#define IOMUXC_PTD17_HYS_MASK                    0x200u
#define IOMUXC_PTD17_HYS_SHIFT                   9
#define IOMUXC_PTD17_ODE_MASK                    0x400u
#define IOMUXC_PTD17_ODE_SHIFT                   10
#define IOMUXC_PTD17_SRE_MASK                    0x800u
#define IOMUXC_PTD17_SRE_SHIFT                   11
#define IOMUXC_PTD17_SPEED_MASK                  0x3000u
#define IOMUXC_PTD17_SPEED_SHIFT                 12
#define IOMUXC_PTD17_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD17_SPEED_SHIFT))&IOMUXC_PTD17_SPEED_MASK)
#define IOMUXC_PTD17_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD17_MUX_MODE_SHIFT              20
#define IOMUXC_PTD17_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD17_MUX_MODE_SHIFT))&IOMUXC_PTD17_MUX_MODE_MASK)
/* PTD16 Bit Fields */
#define IOMUXC_PTD16_IBE_MASK                    0x1u
#define IOMUXC_PTD16_IBE_SHIFT                   0
#define IOMUXC_PTD16_OBE_MASK                    0x2u
#define IOMUXC_PTD16_OBE_SHIFT                   1
#define IOMUXC_PTD16_PUE_MASK                    0x4u
#define IOMUXC_PTD16_PUE_SHIFT                   2
#define IOMUXC_PTD16_PKE_MASK                    0x8u
#define IOMUXC_PTD16_PKE_SHIFT                   3
#define IOMUXC_PTD16_PUS_MASK                    0x30u
#define IOMUXC_PTD16_PUS_SHIFT                   4
#define IOMUXC_PTD16_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD16_PUS_SHIFT))&IOMUXC_PTD16_PUS_MASK)
#define IOMUXC_PTD16_DSE_MASK                    0x1C0u
#define IOMUXC_PTD16_DSE_SHIFT                   6
#define IOMUXC_PTD16_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD16_DSE_SHIFT))&IOMUXC_PTD16_DSE_MASK)
#define IOMUXC_PTD16_HYS_MASK                    0x200u
#define IOMUXC_PTD16_HYS_SHIFT                   9
#define IOMUXC_PTD16_ODE_MASK                    0x400u
#define IOMUXC_PTD16_ODE_SHIFT                   10
#define IOMUXC_PTD16_SRE_MASK                    0x800u
#define IOMUXC_PTD16_SRE_SHIFT                   11
#define IOMUXC_PTD16_SPEED_MASK                  0x3000u
#define IOMUXC_PTD16_SPEED_SHIFT                 12
#define IOMUXC_PTD16_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD16_SPEED_SHIFT))&IOMUXC_PTD16_SPEED_MASK)
#define IOMUXC_PTD16_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD16_MUX_MODE_SHIFT              20
#define IOMUXC_PTD16_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD16_MUX_MODE_SHIFT))&IOMUXC_PTD16_MUX_MODE_MASK)
/* PTD0 Bit Fields */
#define IOMUXC_PTD0_IBE_MASK                     0x1u
#define IOMUXC_PTD0_IBE_SHIFT                    0
#define IOMUXC_PTD0_OBE_MASK                     0x2u
#define IOMUXC_PTD0_OBE_SHIFT                    1
#define IOMUXC_PTD0_PUE_MASK                     0x4u
#define IOMUXC_PTD0_PUE_SHIFT                    2
#define IOMUXC_PTD0_PKE_MASK                     0x8u
#define IOMUXC_PTD0_PKE_SHIFT                    3
#define IOMUXC_PTD0_PUS_MASK                     0x30u
#define IOMUXC_PTD0_PUS_SHIFT                    4
#define IOMUXC_PTD0_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD0_PUS_SHIFT))&IOMUXC_PTD0_PUS_MASK)
#define IOMUXC_PTD0_DSE_MASK                     0x1C0u
#define IOMUXC_PTD0_DSE_SHIFT                    6
#define IOMUXC_PTD0_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD0_DSE_SHIFT))&IOMUXC_PTD0_DSE_MASK)
#define IOMUXC_PTD0_HYS_MASK                     0x200u
#define IOMUXC_PTD0_HYS_SHIFT                    9
#define IOMUXC_PTD0_ODE_MASK                     0x400u
#define IOMUXC_PTD0_ODE_SHIFT                    10
#define IOMUXC_PTD0_SRE_MASK                     0x800u
#define IOMUXC_PTD0_SRE_SHIFT                    11
#define IOMUXC_PTD0_SPEED_MASK                   0x3000u
#define IOMUXC_PTD0_SPEED_SHIFT                  12
#define IOMUXC_PTD0_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD0_SPEED_SHIFT))&IOMUXC_PTD0_SPEED_MASK)
#define IOMUXC_PTD0_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD0_MUX_MODE_SHIFT               20
#define IOMUXC_PTD0_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD0_MUX_MODE_SHIFT))&IOMUXC_PTD0_MUX_MODE_MASK)
/* PTD1 Bit Fields */
#define IOMUXC_PTD1_IBE_MASK                     0x1u
#define IOMUXC_PTD1_IBE_SHIFT                    0
#define IOMUXC_PTD1_OBE_MASK                     0x2u
#define IOMUXC_PTD1_OBE_SHIFT                    1
#define IOMUXC_PTD1_PUE_MASK                     0x4u
#define IOMUXC_PTD1_PUE_SHIFT                    2
#define IOMUXC_PTD1_PKE_MASK                     0x8u
#define IOMUXC_PTD1_PKE_SHIFT                    3
#define IOMUXC_PTD1_PUS_MASK                     0x30u
#define IOMUXC_PTD1_PUS_SHIFT                    4
#define IOMUXC_PTD1_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD1_PUS_SHIFT))&IOMUXC_PTD1_PUS_MASK)
#define IOMUXC_PTD1_DSE_MASK                     0x1C0u
#define IOMUXC_PTD1_DSE_SHIFT                    6
#define IOMUXC_PTD1_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD1_DSE_SHIFT))&IOMUXC_PTD1_DSE_MASK)
#define IOMUXC_PTD1_HYS_MASK                     0x200u
#define IOMUXC_PTD1_HYS_SHIFT                    9
#define IOMUXC_PTD1_ODE_MASK                     0x400u
#define IOMUXC_PTD1_ODE_SHIFT                    10
#define IOMUXC_PTD1_SRE_MASK                     0x800u
#define IOMUXC_PTD1_SRE_SHIFT                    11
#define IOMUXC_PTD1_SPEED_MASK                   0x3000u
#define IOMUXC_PTD1_SPEED_SHIFT                  12
#define IOMUXC_PTD1_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD1_SPEED_SHIFT))&IOMUXC_PTD1_SPEED_MASK)
#define IOMUXC_PTD1_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD1_MUX_MODE_SHIFT               20
#define IOMUXC_PTD1_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD1_MUX_MODE_SHIFT))&IOMUXC_PTD1_MUX_MODE_MASK)
/* PTD2 Bit Fields */
#define IOMUXC_PTD2_IBE_MASK                     0x1u
#define IOMUXC_PTD2_IBE_SHIFT                    0
#define IOMUXC_PTD2_OBE_MASK                     0x2u
#define IOMUXC_PTD2_OBE_SHIFT                    1
#define IOMUXC_PTD2_PUE_MASK                     0x4u
#define IOMUXC_PTD2_PUE_SHIFT                    2
#define IOMUXC_PTD2_PKE_MASK                     0x8u
#define IOMUXC_PTD2_PKE_SHIFT                    3
#define IOMUXC_PTD2_PUS_MASK                     0x30u
#define IOMUXC_PTD2_PUS_SHIFT                    4
#define IOMUXC_PTD2_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD2_PUS_SHIFT))&IOMUXC_PTD2_PUS_MASK)
#define IOMUXC_PTD2_DSE_MASK                     0x1C0u
#define IOMUXC_PTD2_DSE_SHIFT                    6
#define IOMUXC_PTD2_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD2_DSE_SHIFT))&IOMUXC_PTD2_DSE_MASK)
#define IOMUXC_PTD2_HYS_MASK                     0x200u
#define IOMUXC_PTD2_HYS_SHIFT                    9
#define IOMUXC_PTD2_ODE_MASK                     0x400u
#define IOMUXC_PTD2_ODE_SHIFT                    10
#define IOMUXC_PTD2_SRE_MASK                     0x800u
#define IOMUXC_PTD2_SRE_SHIFT                    11
#define IOMUXC_PTD2_SPEED_MASK                   0x3000u
#define IOMUXC_PTD2_SPEED_SHIFT                  12
#define IOMUXC_PTD2_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD2_SPEED_SHIFT))&IOMUXC_PTD2_SPEED_MASK)
#define IOMUXC_PTD2_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD2_MUX_MODE_SHIFT               20
#define IOMUXC_PTD2_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD2_MUX_MODE_SHIFT))&IOMUXC_PTD2_MUX_MODE_MASK)
/* PTD3 Bit Fields */
#define IOMUXC_PTD3_IBE_MASK                     0x1u
#define IOMUXC_PTD3_IBE_SHIFT                    0
#define IOMUXC_PTD3_OBE_MASK                     0x2u
#define IOMUXC_PTD3_OBE_SHIFT                    1
#define IOMUXC_PTD3_PUE_MASK                     0x4u
#define IOMUXC_PTD3_PUE_SHIFT                    2
#define IOMUXC_PTD3_PKE_MASK                     0x8u
#define IOMUXC_PTD3_PKE_SHIFT                    3
#define IOMUXC_PTD3_PUS_MASK                     0x30u
#define IOMUXC_PTD3_PUS_SHIFT                    4
#define IOMUXC_PTD3_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD3_PUS_SHIFT))&IOMUXC_PTD3_PUS_MASK)
#define IOMUXC_PTD3_DSE_MASK                     0x1C0u
#define IOMUXC_PTD3_DSE_SHIFT                    6
#define IOMUXC_PTD3_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD3_DSE_SHIFT))&IOMUXC_PTD3_DSE_MASK)
#define IOMUXC_PTD3_HYS_MASK                     0x200u
#define IOMUXC_PTD3_HYS_SHIFT                    9
#define IOMUXC_PTD3_ODE_MASK                     0x400u
#define IOMUXC_PTD3_ODE_SHIFT                    10
#define IOMUXC_PTD3_SRE_MASK                     0x800u
#define IOMUXC_PTD3_SRE_SHIFT                    11
#define IOMUXC_PTD3_SPEED_MASK                   0x3000u
#define IOMUXC_PTD3_SPEED_SHIFT                  12
#define IOMUXC_PTD3_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD3_SPEED_SHIFT))&IOMUXC_PTD3_SPEED_MASK)
#define IOMUXC_PTD3_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD3_MUX_MODE_SHIFT               20
#define IOMUXC_PTD3_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD3_MUX_MODE_SHIFT))&IOMUXC_PTD3_MUX_MODE_MASK)
/* PTD4 Bit Fields */
#define IOMUXC_PTD4_IBE_MASK                     0x1u
#define IOMUXC_PTD4_IBE_SHIFT                    0
#define IOMUXC_PTD4_OBE_MASK                     0x2u
#define IOMUXC_PTD4_OBE_SHIFT                    1
#define IOMUXC_PTD4_PUE_MASK                     0x4u
#define IOMUXC_PTD4_PUE_SHIFT                    2
#define IOMUXC_PTD4_PKE_MASK                     0x8u
#define IOMUXC_PTD4_PKE_SHIFT                    3
#define IOMUXC_PTD4_PUS_MASK                     0x30u
#define IOMUXC_PTD4_PUS_SHIFT                    4
#define IOMUXC_PTD4_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD4_PUS_SHIFT))&IOMUXC_PTD4_PUS_MASK)
#define IOMUXC_PTD4_DSE_MASK                     0x1C0u
#define IOMUXC_PTD4_DSE_SHIFT                    6
#define IOMUXC_PTD4_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD4_DSE_SHIFT))&IOMUXC_PTD4_DSE_MASK)
#define IOMUXC_PTD4_HYS_MASK                     0x200u
#define IOMUXC_PTD4_HYS_SHIFT                    9
#define IOMUXC_PTD4_ODE_MASK                     0x400u
#define IOMUXC_PTD4_ODE_SHIFT                    10
#define IOMUXC_PTD4_SRE_MASK                     0x800u
#define IOMUXC_PTD4_SRE_SHIFT                    11
#define IOMUXC_PTD4_SPEED_MASK                   0x3000u
#define IOMUXC_PTD4_SPEED_SHIFT                  12
#define IOMUXC_PTD4_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD4_SPEED_SHIFT))&IOMUXC_PTD4_SPEED_MASK)
#define IOMUXC_PTD4_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD4_MUX_MODE_SHIFT               20
#define IOMUXC_PTD4_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD4_MUX_MODE_SHIFT))&IOMUXC_PTD4_MUX_MODE_MASK)
/* PTD5 Bit Fields */
#define IOMUXC_PTD5_IBE_MASK                     0x1u
#define IOMUXC_PTD5_IBE_SHIFT                    0
#define IOMUXC_PTD5_OBE_MASK                     0x2u
#define IOMUXC_PTD5_OBE_SHIFT                    1
#define IOMUXC_PTD5_PUE_MASK                     0x4u
#define IOMUXC_PTD5_PUE_SHIFT                    2
#define IOMUXC_PTD5_PKE_MASK                     0x8u
#define IOMUXC_PTD5_PKE_SHIFT                    3
#define IOMUXC_PTD5_PUS_MASK                     0x30u
#define IOMUXC_PTD5_PUS_SHIFT                    4
#define IOMUXC_PTD5_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD5_PUS_SHIFT))&IOMUXC_PTD5_PUS_MASK)
#define IOMUXC_PTD5_DSE_MASK                     0x1C0u
#define IOMUXC_PTD5_DSE_SHIFT                    6
#define IOMUXC_PTD5_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD5_DSE_SHIFT))&IOMUXC_PTD5_DSE_MASK)
#define IOMUXC_PTD5_HYS_MASK                     0x200u
#define IOMUXC_PTD5_HYS_SHIFT                    9
#define IOMUXC_PTD5_ODE_MASK                     0x400u
#define IOMUXC_PTD5_ODE_SHIFT                    10
#define IOMUXC_PTD5_SRE_MASK                     0x800u
#define IOMUXC_PTD5_SRE_SHIFT                    11
#define IOMUXC_PTD5_SPEED_MASK                   0x3000u
#define IOMUXC_PTD5_SPEED_SHIFT                  12
#define IOMUXC_PTD5_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD5_SPEED_SHIFT))&IOMUXC_PTD5_SPEED_MASK)
#define IOMUXC_PTD5_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD5_MUX_MODE_SHIFT               20
#define IOMUXC_PTD5_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD5_MUX_MODE_SHIFT))&IOMUXC_PTD5_MUX_MODE_MASK)
/* PTD6 Bit Fields */
#define IOMUXC_PTD6_IBE_MASK                     0x1u
#define IOMUXC_PTD6_IBE_SHIFT                    0
#define IOMUXC_PTD6_OBE_MASK                     0x2u
#define IOMUXC_PTD6_OBE_SHIFT                    1
#define IOMUXC_PTD6_PUE_MASK                     0x4u
#define IOMUXC_PTD6_PUE_SHIFT                    2
#define IOMUXC_PTD6_PKE_MASK                     0x8u
#define IOMUXC_PTD6_PKE_SHIFT                    3
#define IOMUXC_PTD6_PUS_MASK                     0x30u
#define IOMUXC_PTD6_PUS_SHIFT                    4
#define IOMUXC_PTD6_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD6_PUS_SHIFT))&IOMUXC_PTD6_PUS_MASK)
#define IOMUXC_PTD6_DSE_MASK                     0x1C0u
#define IOMUXC_PTD6_DSE_SHIFT                    6
#define IOMUXC_PTD6_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD6_DSE_SHIFT))&IOMUXC_PTD6_DSE_MASK)
#define IOMUXC_PTD6_HYS_MASK                     0x200u
#define IOMUXC_PTD6_HYS_SHIFT                    9
#define IOMUXC_PTD6_ODE_MASK                     0x400u
#define IOMUXC_PTD6_ODE_SHIFT                    10
#define IOMUXC_PTD6_SRE_MASK                     0x800u
#define IOMUXC_PTD6_SRE_SHIFT                    11
#define IOMUXC_PTD6_SPEED_MASK                   0x3000u
#define IOMUXC_PTD6_SPEED_SHIFT                  12
#define IOMUXC_PTD6_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD6_SPEED_SHIFT))&IOMUXC_PTD6_SPEED_MASK)
#define IOMUXC_PTD6_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD6_MUX_MODE_SHIFT               20
#define IOMUXC_PTD6_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD6_MUX_MODE_SHIFT))&IOMUXC_PTD6_MUX_MODE_MASK)
/* PTD7 Bit Fields */
#define IOMUXC_PTD7_IBE_MASK                     0x1u
#define IOMUXC_PTD7_IBE_SHIFT                    0
#define IOMUXC_PTD7_OBE_MASK                     0x2u
#define IOMUXC_PTD7_OBE_SHIFT                    1
#define IOMUXC_PTD7_PUE_MASK                     0x4u
#define IOMUXC_PTD7_PUE_SHIFT                    2
#define IOMUXC_PTD7_PKE_MASK                     0x8u
#define IOMUXC_PTD7_PKE_SHIFT                    3
#define IOMUXC_PTD7_PUS_MASK                     0x30u
#define IOMUXC_PTD7_PUS_SHIFT                    4
#define IOMUXC_PTD7_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD7_PUS_SHIFT))&IOMUXC_PTD7_PUS_MASK)
#define IOMUXC_PTD7_DSE_MASK                     0x1C0u
#define IOMUXC_PTD7_DSE_SHIFT                    6
#define IOMUXC_PTD7_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD7_DSE_SHIFT))&IOMUXC_PTD7_DSE_MASK)
#define IOMUXC_PTD7_HYS_MASK                     0x200u
#define IOMUXC_PTD7_HYS_SHIFT                    9
#define IOMUXC_PTD7_ODE_MASK                     0x400u
#define IOMUXC_PTD7_ODE_SHIFT                    10
#define IOMUXC_PTD7_SRE_MASK                     0x800u
#define IOMUXC_PTD7_SRE_SHIFT                    11
#define IOMUXC_PTD7_SPEED_MASK                   0x3000u
#define IOMUXC_PTD7_SPEED_SHIFT                  12
#define IOMUXC_PTD7_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD7_SPEED_SHIFT))&IOMUXC_PTD7_SPEED_MASK)
#define IOMUXC_PTD7_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD7_MUX_MODE_SHIFT               20
#define IOMUXC_PTD7_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD7_MUX_MODE_SHIFT))&IOMUXC_PTD7_MUX_MODE_MASK)
/* PTD8 Bit Fields */
#define IOMUXC_PTD8_IBE_MASK                     0x1u
#define IOMUXC_PTD8_IBE_SHIFT                    0
#define IOMUXC_PTD8_OBE_MASK                     0x2u
#define IOMUXC_PTD8_OBE_SHIFT                    1
#define IOMUXC_PTD8_PUE_MASK                     0x4u
#define IOMUXC_PTD8_PUE_SHIFT                    2
#define IOMUXC_PTD8_PKE_MASK                     0x8u
#define IOMUXC_PTD8_PKE_SHIFT                    3
#define IOMUXC_PTD8_PUS_MASK                     0x30u
#define IOMUXC_PTD8_PUS_SHIFT                    4
#define IOMUXC_PTD8_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD8_PUS_SHIFT))&IOMUXC_PTD8_PUS_MASK)
#define IOMUXC_PTD8_DSE_MASK                     0x1C0u
#define IOMUXC_PTD8_DSE_SHIFT                    6
#define IOMUXC_PTD8_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD8_DSE_SHIFT))&IOMUXC_PTD8_DSE_MASK)
#define IOMUXC_PTD8_HYS_MASK                     0x200u
#define IOMUXC_PTD8_HYS_SHIFT                    9
#define IOMUXC_PTD8_ODE_MASK                     0x400u
#define IOMUXC_PTD8_ODE_SHIFT                    10
#define IOMUXC_PTD8_SRE_MASK                     0x800u
#define IOMUXC_PTD8_SRE_SHIFT                    11
#define IOMUXC_PTD8_SPEED_MASK                   0x3000u
#define IOMUXC_PTD8_SPEED_SHIFT                  12
#define IOMUXC_PTD8_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD8_SPEED_SHIFT))&IOMUXC_PTD8_SPEED_MASK)
#define IOMUXC_PTD8_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD8_MUX_MODE_SHIFT               20
#define IOMUXC_PTD8_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD8_MUX_MODE_SHIFT))&IOMUXC_PTD8_MUX_MODE_MASK)
/* PTD9 Bit Fields */
#define IOMUXC_PTD9_IBE_MASK                     0x1u
#define IOMUXC_PTD9_IBE_SHIFT                    0
#define IOMUXC_PTD9_OBE_MASK                     0x2u
#define IOMUXC_PTD9_OBE_SHIFT                    1
#define IOMUXC_PTD9_PUE_MASK                     0x4u
#define IOMUXC_PTD9_PUE_SHIFT                    2
#define IOMUXC_PTD9_PKE_MASK                     0x8u
#define IOMUXC_PTD9_PKE_SHIFT                    3
#define IOMUXC_PTD9_PUS_MASK                     0x30u
#define IOMUXC_PTD9_PUS_SHIFT                    4
#define IOMUXC_PTD9_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD9_PUS_SHIFT))&IOMUXC_PTD9_PUS_MASK)
#define IOMUXC_PTD9_DSE_MASK                     0x1C0u
#define IOMUXC_PTD9_DSE_SHIFT                    6
#define IOMUXC_PTD9_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD9_DSE_SHIFT))&IOMUXC_PTD9_DSE_MASK)
#define IOMUXC_PTD9_HYS_MASK                     0x200u
#define IOMUXC_PTD9_HYS_SHIFT                    9
#define IOMUXC_PTD9_ODE_MASK                     0x400u
#define IOMUXC_PTD9_ODE_SHIFT                    10
#define IOMUXC_PTD9_SRE_MASK                     0x800u
#define IOMUXC_PTD9_SRE_SHIFT                    11
#define IOMUXC_PTD9_SPEED_MASK                   0x3000u
#define IOMUXC_PTD9_SPEED_SHIFT                  12
#define IOMUXC_PTD9_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD9_SPEED_SHIFT))&IOMUXC_PTD9_SPEED_MASK)
#define IOMUXC_PTD9_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTD9_MUX_MODE_SHIFT               20
#define IOMUXC_PTD9_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD9_MUX_MODE_SHIFT))&IOMUXC_PTD9_MUX_MODE_MASK)
/* PTD10 Bit Fields */
#define IOMUXC_PTD10_IBE_MASK                    0x1u
#define IOMUXC_PTD10_IBE_SHIFT                   0
#define IOMUXC_PTD10_OBE_MASK                    0x2u
#define IOMUXC_PTD10_OBE_SHIFT                   1
#define IOMUXC_PTD10_PUE_MASK                    0x4u
#define IOMUXC_PTD10_PUE_SHIFT                   2
#define IOMUXC_PTD10_PKE_MASK                    0x8u
#define IOMUXC_PTD10_PKE_SHIFT                   3
#define IOMUXC_PTD10_PUS_MASK                    0x30u
#define IOMUXC_PTD10_PUS_SHIFT                   4
#define IOMUXC_PTD10_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD10_PUS_SHIFT))&IOMUXC_PTD10_PUS_MASK)
#define IOMUXC_PTD10_DSE_MASK                    0x1C0u
#define IOMUXC_PTD10_DSE_SHIFT                   6
#define IOMUXC_PTD10_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD10_DSE_SHIFT))&IOMUXC_PTD10_DSE_MASK)
#define IOMUXC_PTD10_HYS_MASK                    0x200u
#define IOMUXC_PTD10_HYS_SHIFT                   9
#define IOMUXC_PTD10_ODE_MASK                    0x400u
#define IOMUXC_PTD10_ODE_SHIFT                   10
#define IOMUXC_PTD10_SRE_MASK                    0x800u
#define IOMUXC_PTD10_SRE_SHIFT                   11
#define IOMUXC_PTD10_SPEED_MASK                  0x3000u
#define IOMUXC_PTD10_SPEED_SHIFT                 12
#define IOMUXC_PTD10_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD10_SPEED_SHIFT))&IOMUXC_PTD10_SPEED_MASK)
#define IOMUXC_PTD10_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD10_MUX_MODE_SHIFT              20
#define IOMUXC_PTD10_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD10_MUX_MODE_SHIFT))&IOMUXC_PTD10_MUX_MODE_MASK)
/* PTD11 Bit Fields */
#define IOMUXC_PTD11_IBE_MASK                    0x1u
#define IOMUXC_PTD11_IBE_SHIFT                   0
#define IOMUXC_PTD11_OBE_MASK                    0x2u
#define IOMUXC_PTD11_OBE_SHIFT                   1
#define IOMUXC_PTD11_PUE_MASK                    0x4u
#define IOMUXC_PTD11_PUE_SHIFT                   2
#define IOMUXC_PTD11_PKE_MASK                    0x8u
#define IOMUXC_PTD11_PKE_SHIFT                   3
#define IOMUXC_PTD11_PUS_MASK                    0x30u
#define IOMUXC_PTD11_PUS_SHIFT                   4
#define IOMUXC_PTD11_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD11_PUS_SHIFT))&IOMUXC_PTD11_PUS_MASK)
#define IOMUXC_PTD11_DSE_MASK                    0x1C0u
#define IOMUXC_PTD11_DSE_SHIFT                   6
#define IOMUXC_PTD11_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD11_DSE_SHIFT))&IOMUXC_PTD11_DSE_MASK)
#define IOMUXC_PTD11_HYS_MASK                    0x200u
#define IOMUXC_PTD11_HYS_SHIFT                   9
#define IOMUXC_PTD11_ODE_MASK                    0x400u
#define IOMUXC_PTD11_ODE_SHIFT                   10
#define IOMUXC_PTD11_SRE_MASK                    0x800u
#define IOMUXC_PTD11_SRE_SHIFT                   11
#define IOMUXC_PTD11_SPEED_MASK                  0x3000u
#define IOMUXC_PTD11_SPEED_SHIFT                 12
#define IOMUXC_PTD11_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD11_SPEED_SHIFT))&IOMUXC_PTD11_SPEED_MASK)
#define IOMUXC_PTD11_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD11_MUX_MODE_SHIFT              20
#define IOMUXC_PTD11_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD11_MUX_MODE_SHIFT))&IOMUXC_PTD11_MUX_MODE_MASK)
/* PTD12 Bit Fields */
#define IOMUXC_PTD12_IBE_MASK                    0x1u
#define IOMUXC_PTD12_IBE_SHIFT                   0
#define IOMUXC_PTD12_OBE_MASK                    0x2u
#define IOMUXC_PTD12_OBE_SHIFT                   1
#define IOMUXC_PTD12_PUE_MASK                    0x4u
#define IOMUXC_PTD12_PUE_SHIFT                   2
#define IOMUXC_PTD12_PKE_MASK                    0x8u
#define IOMUXC_PTD12_PKE_SHIFT                   3
#define IOMUXC_PTD12_PUS_MASK                    0x30u
#define IOMUXC_PTD12_PUS_SHIFT                   4
#define IOMUXC_PTD12_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD12_PUS_SHIFT))&IOMUXC_PTD12_PUS_MASK)
#define IOMUXC_PTD12_DSE_MASK                    0x1C0u
#define IOMUXC_PTD12_DSE_SHIFT                   6
#define IOMUXC_PTD12_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD12_DSE_SHIFT))&IOMUXC_PTD12_DSE_MASK)
#define IOMUXC_PTD12_HYS_MASK                    0x200u
#define IOMUXC_PTD12_HYS_SHIFT                   9
#define IOMUXC_PTD12_ODE_MASK                    0x400u
#define IOMUXC_PTD12_ODE_SHIFT                   10
#define IOMUXC_PTD12_SRE_MASK                    0x800u
#define IOMUXC_PTD12_SRE_SHIFT                   11
#define IOMUXC_PTD12_SPEED_MASK                  0x3000u
#define IOMUXC_PTD12_SPEED_SHIFT                 12
#define IOMUXC_PTD12_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD12_SPEED_SHIFT))&IOMUXC_PTD12_SPEED_MASK)
#define IOMUXC_PTD12_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD12_MUX_MODE_SHIFT              20
#define IOMUXC_PTD12_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD12_MUX_MODE_SHIFT))&IOMUXC_PTD12_MUX_MODE_MASK)
/* PTD13 Bit Fields */
#define IOMUXC_PTD13_IBE_MASK                    0x1u
#define IOMUXC_PTD13_IBE_SHIFT                   0
#define IOMUXC_PTD13_OBE_MASK                    0x2u
#define IOMUXC_PTD13_OBE_SHIFT                   1
#define IOMUXC_PTD13_PUE_MASK                    0x4u
#define IOMUXC_PTD13_PUE_SHIFT                   2
#define IOMUXC_PTD13_PKE_MASK                    0x8u
#define IOMUXC_PTD13_PKE_SHIFT                   3
#define IOMUXC_PTD13_PUS_MASK                    0x30u
#define IOMUXC_PTD13_PUS_SHIFT                   4
#define IOMUXC_PTD13_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD13_PUS_SHIFT))&IOMUXC_PTD13_PUS_MASK)
#define IOMUXC_PTD13_DSE_MASK                    0x1C0u
#define IOMUXC_PTD13_DSE_SHIFT                   6
#define IOMUXC_PTD13_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD13_DSE_SHIFT))&IOMUXC_PTD13_DSE_MASK)
#define IOMUXC_PTD13_HYS_MASK                    0x200u
#define IOMUXC_PTD13_HYS_SHIFT                   9
#define IOMUXC_PTD13_ODE_MASK                    0x400u
#define IOMUXC_PTD13_ODE_SHIFT                   10
#define IOMUXC_PTD13_SRE_MASK                    0x800u
#define IOMUXC_PTD13_SRE_SHIFT                   11
#define IOMUXC_PTD13_SPEED_MASK                  0x3000u
#define IOMUXC_PTD13_SPEED_SHIFT                 12
#define IOMUXC_PTD13_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD13_SPEED_SHIFT))&IOMUXC_PTD13_SPEED_MASK)
#define IOMUXC_PTD13_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTD13_MUX_MODE_SHIFT              20
#define IOMUXC_PTD13_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTD13_MUX_MODE_SHIFT))&IOMUXC_PTD13_MUX_MODE_MASK)
/* PTB23 Bit Fields */
#define IOMUXC_PTB23_IBE_MASK                    0x1u
#define IOMUXC_PTB23_IBE_SHIFT                   0
#define IOMUXC_PTB23_OBE_MASK                    0x2u
#define IOMUXC_PTB23_OBE_SHIFT                   1
#define IOMUXC_PTB23_PUE_MASK                    0x4u
#define IOMUXC_PTB23_PUE_SHIFT                   2
#define IOMUXC_PTB23_PKE_MASK                    0x8u
#define IOMUXC_PTB23_PKE_SHIFT                   3
#define IOMUXC_PTB23_PUS_MASK                    0x30u
#define IOMUXC_PTB23_PUS_SHIFT                   4
#define IOMUXC_PTB23_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB23_PUS_SHIFT))&IOMUXC_PTB23_PUS_MASK)
#define IOMUXC_PTB23_DSE_MASK                    0x1C0u
#define IOMUXC_PTB23_DSE_SHIFT                   6
#define IOMUXC_PTB23_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB23_DSE_SHIFT))&IOMUXC_PTB23_DSE_MASK)
#define IOMUXC_PTB23_HYS_MASK                    0x200u
#define IOMUXC_PTB23_HYS_SHIFT                   9
#define IOMUXC_PTB23_ODE_MASK                    0x400u
#define IOMUXC_PTB23_ODE_SHIFT                   10
#define IOMUXC_PTB23_SRE_MASK                    0x800u
#define IOMUXC_PTB23_SRE_SHIFT                   11
#define IOMUXC_PTB23_SPEED_MASK                  0x3000u
#define IOMUXC_PTB23_SPEED_SHIFT                 12
#define IOMUXC_PTB23_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB23_SPEED_SHIFT))&IOMUXC_PTB23_SPEED_MASK)
#define IOMUXC_PTB23_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB23_MUX_MODE_SHIFT              20
#define IOMUXC_PTB23_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB23_MUX_MODE_SHIFT))&IOMUXC_PTB23_MUX_MODE_MASK)
/* PTB24 Bit Fields */
#define IOMUXC_PTB24_IBE_MASK                    0x1u
#define IOMUXC_PTB24_IBE_SHIFT                   0
#define IOMUXC_PTB24_OBE_MASK                    0x2u
#define IOMUXC_PTB24_OBE_SHIFT                   1
#define IOMUXC_PTB24_PUE_MASK                    0x4u
#define IOMUXC_PTB24_PUE_SHIFT                   2
#define IOMUXC_PTB24_PKE_MASK                    0x8u
#define IOMUXC_PTB24_PKE_SHIFT                   3
#define IOMUXC_PTB24_PUS_MASK                    0x30u
#define IOMUXC_PTB24_PUS_SHIFT                   4
#define IOMUXC_PTB24_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB24_PUS_SHIFT))&IOMUXC_PTB24_PUS_MASK)
#define IOMUXC_PTB24_DSE_MASK                    0x1C0u
#define IOMUXC_PTB24_DSE_SHIFT                   6
#define IOMUXC_PTB24_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB24_DSE_SHIFT))&IOMUXC_PTB24_DSE_MASK)
#define IOMUXC_PTB24_HYS_MASK                    0x200u
#define IOMUXC_PTB24_HYS_SHIFT                   9
#define IOMUXC_PTB24_ODE_MASK                    0x400u
#define IOMUXC_PTB24_ODE_SHIFT                   10
#define IOMUXC_PTB24_SRE_MASK                    0x800u
#define IOMUXC_PTB24_SRE_SHIFT                   11
#define IOMUXC_PTB24_SPEED_MASK                  0x3000u
#define IOMUXC_PTB24_SPEED_SHIFT                 12
#define IOMUXC_PTB24_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB24_SPEED_SHIFT))&IOMUXC_PTB24_SPEED_MASK)
#define IOMUXC_PTB24_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB24_MUX_MODE_SHIFT              20
#define IOMUXC_PTB24_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB24_MUX_MODE_SHIFT))&IOMUXC_PTB24_MUX_MODE_MASK)
/* PTB25 Bit Fields */
#define IOMUXC_PTB25_IBE_MASK                    0x1u
#define IOMUXC_PTB25_IBE_SHIFT                   0
#define IOMUXC_PTB25_OBE_MASK                    0x2u
#define IOMUXC_PTB25_OBE_SHIFT                   1
#define IOMUXC_PTB25_PUE_MASK                    0x4u
#define IOMUXC_PTB25_PUE_SHIFT                   2
#define IOMUXC_PTB25_PKE_MASK                    0x8u
#define IOMUXC_PTB25_PKE_SHIFT                   3
#define IOMUXC_PTB25_PUS_MASK                    0x30u
#define IOMUXC_PTB25_PUS_SHIFT                   4
#define IOMUXC_PTB25_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB25_PUS_SHIFT))&IOMUXC_PTB25_PUS_MASK)
#define IOMUXC_PTB25_DSE_MASK                    0x1C0u
#define IOMUXC_PTB25_DSE_SHIFT                   6
#define IOMUXC_PTB25_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB25_DSE_SHIFT))&IOMUXC_PTB25_DSE_MASK)
#define IOMUXC_PTB25_HYS_MASK                    0x200u
#define IOMUXC_PTB25_HYS_SHIFT                   9
#define IOMUXC_PTB25_ODE_MASK                    0x400u
#define IOMUXC_PTB25_ODE_SHIFT                   10
#define IOMUXC_PTB25_SRE_MASK                    0x800u
#define IOMUXC_PTB25_SRE_SHIFT                   11
#define IOMUXC_PTB25_SPEED_MASK                  0x3000u
#define IOMUXC_PTB25_SPEED_SHIFT                 12
#define IOMUXC_PTB25_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB25_SPEED_SHIFT))&IOMUXC_PTB25_SPEED_MASK)
#define IOMUXC_PTB25_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB25_MUX_MODE_SHIFT              20
#define IOMUXC_PTB25_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB25_MUX_MODE_SHIFT))&IOMUXC_PTB25_MUX_MODE_MASK)
/* PTB26 Bit Fields */
#define IOMUXC_PTB26_IBE_MASK                    0x1u
#define IOMUXC_PTB26_IBE_SHIFT                   0
#define IOMUXC_PTB26_OBE_MASK                    0x2u
#define IOMUXC_PTB26_OBE_SHIFT                   1
#define IOMUXC_PTB26_PUE_MASK                    0x4u
#define IOMUXC_PTB26_PUE_SHIFT                   2
#define IOMUXC_PTB26_PKE_MASK                    0x8u
#define IOMUXC_PTB26_PKE_SHIFT                   3
#define IOMUXC_PTB26_PUS_MASK                    0x30u
#define IOMUXC_PTB26_PUS_SHIFT                   4
#define IOMUXC_PTB26_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB26_PUS_SHIFT))&IOMUXC_PTB26_PUS_MASK)
#define IOMUXC_PTB26_DSE_MASK                    0x1C0u
#define IOMUXC_PTB26_DSE_SHIFT                   6
#define IOMUXC_PTB26_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB26_DSE_SHIFT))&IOMUXC_PTB26_DSE_MASK)
#define IOMUXC_PTB26_HYS_MASK                    0x200u
#define IOMUXC_PTB26_HYS_SHIFT                   9
#define IOMUXC_PTB26_ODE_MASK                    0x400u
#define IOMUXC_PTB26_ODE_SHIFT                   10
#define IOMUXC_PTB26_SRE_MASK                    0x800u
#define IOMUXC_PTB26_SRE_SHIFT                   11
#define IOMUXC_PTB26_SPEED_MASK                  0x3000u
#define IOMUXC_PTB26_SPEED_SHIFT                 12
#define IOMUXC_PTB26_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB26_SPEED_SHIFT))&IOMUXC_PTB26_SPEED_MASK)
#define IOMUXC_PTB26_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB26_MUX_MODE_SHIFT              20
#define IOMUXC_PTB26_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB26_MUX_MODE_SHIFT))&IOMUXC_PTB26_MUX_MODE_MASK)
/* PTB27 Bit Fields */
#define IOMUXC_PTB27_IBE_MASK                    0x1u
#define IOMUXC_PTB27_IBE_SHIFT                   0
#define IOMUXC_PTB27_OBE_MASK                    0x2u
#define IOMUXC_PTB27_OBE_SHIFT                   1
#define IOMUXC_PTB27_PUE_MASK                    0x4u
#define IOMUXC_PTB27_PUE_SHIFT                   2
#define IOMUXC_PTB27_PKE_MASK                    0x8u
#define IOMUXC_PTB27_PKE_SHIFT                   3
#define IOMUXC_PTB27_PUS_MASK                    0x30u
#define IOMUXC_PTB27_PUS_SHIFT                   4
#define IOMUXC_PTB27_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB27_PUS_SHIFT))&IOMUXC_PTB27_PUS_MASK)
#define IOMUXC_PTB27_DSE_MASK                    0x1C0u
#define IOMUXC_PTB27_DSE_SHIFT                   6
#define IOMUXC_PTB27_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB27_DSE_SHIFT))&IOMUXC_PTB27_DSE_MASK)
#define IOMUXC_PTB27_HYS_MASK                    0x200u
#define IOMUXC_PTB27_HYS_SHIFT                   9
#define IOMUXC_PTB27_ODE_MASK                    0x400u
#define IOMUXC_PTB27_ODE_SHIFT                   10
#define IOMUXC_PTB27_SRE_MASK                    0x800u
#define IOMUXC_PTB27_SRE_SHIFT                   11
#define IOMUXC_PTB27_SPEED_MASK                  0x3000u
#define IOMUXC_PTB27_SPEED_SHIFT                 12
#define IOMUXC_PTB27_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB27_SPEED_SHIFT))&IOMUXC_PTB27_SPEED_MASK)
#define IOMUXC_PTB27_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB27_MUX_MODE_SHIFT              20
#define IOMUXC_PTB27_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB27_MUX_MODE_SHIFT))&IOMUXC_PTB27_MUX_MODE_MASK)
/* PTB28 Bit Fields */
#define IOMUXC_PTB28_IBE_MASK                    0x1u
#define IOMUXC_PTB28_IBE_SHIFT                   0
#define IOMUXC_PTB28_OBE_MASK                    0x2u
#define IOMUXC_PTB28_OBE_SHIFT                   1
#define IOMUXC_PTB28_PUE_MASK                    0x4u
#define IOMUXC_PTB28_PUE_SHIFT                   2
#define IOMUXC_PTB28_PKE_MASK                    0x8u
#define IOMUXC_PTB28_PKE_SHIFT                   3
#define IOMUXC_PTB28_PUS_MASK                    0x30u
#define IOMUXC_PTB28_PUS_SHIFT                   4
#define IOMUXC_PTB28_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB28_PUS_SHIFT))&IOMUXC_PTB28_PUS_MASK)
#define IOMUXC_PTB28_DSE_MASK                    0x1C0u
#define IOMUXC_PTB28_DSE_SHIFT                   6
#define IOMUXC_PTB28_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB28_DSE_SHIFT))&IOMUXC_PTB28_DSE_MASK)
#define IOMUXC_PTB28_HYS_MASK                    0x200u
#define IOMUXC_PTB28_HYS_SHIFT                   9
#define IOMUXC_PTB28_ODE_MASK                    0x400u
#define IOMUXC_PTB28_ODE_SHIFT                   10
#define IOMUXC_PTB28_SRE_MASK                    0x800u
#define IOMUXC_PTB28_SRE_SHIFT                   11
#define IOMUXC_PTB28_SPEED_MASK                  0x3000u
#define IOMUXC_PTB28_SPEED_SHIFT                 12
#define IOMUXC_PTB28_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB28_SPEED_SHIFT))&IOMUXC_PTB28_SPEED_MASK)
#define IOMUXC_PTB28_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTB28_MUX_MODE_SHIFT              20
#define IOMUXC_PTB28_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTB28_MUX_MODE_SHIFT))&IOMUXC_PTB28_MUX_MODE_MASK)
/* PTC26 Bit Fields */
#define IOMUXC_PTC26_IBE_MASK                    0x1u
#define IOMUXC_PTC26_IBE_SHIFT                   0
#define IOMUXC_PTC26_OBE_MASK                    0x2u
#define IOMUXC_PTC26_OBE_SHIFT                   1
#define IOMUXC_PTC26_PUE_MASK                    0x4u
#define IOMUXC_PTC26_PUE_SHIFT                   2
#define IOMUXC_PTC26_PKE_MASK                    0x8u
#define IOMUXC_PTC26_PKE_SHIFT                   3
#define IOMUXC_PTC26_PUS_MASK                    0x30u
#define IOMUXC_PTC26_PUS_SHIFT                   4
#define IOMUXC_PTC26_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC26_PUS_SHIFT))&IOMUXC_PTC26_PUS_MASK)
#define IOMUXC_PTC26_DSE_MASK                    0x1C0u
#define IOMUXC_PTC26_DSE_SHIFT                   6
#define IOMUXC_PTC26_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC26_DSE_SHIFT))&IOMUXC_PTC26_DSE_MASK)
#define IOMUXC_PTC26_HYS_MASK                    0x200u
#define IOMUXC_PTC26_HYS_SHIFT                   9
#define IOMUXC_PTC26_ODE_MASK                    0x400u
#define IOMUXC_PTC26_ODE_SHIFT                   10
#define IOMUXC_PTC26_SRE_MASK                    0x800u
#define IOMUXC_PTC26_SRE_SHIFT                   11
#define IOMUXC_PTC26_SPEED_MASK                  0x3000u
#define IOMUXC_PTC26_SPEED_SHIFT                 12
#define IOMUXC_PTC26_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC26_SPEED_SHIFT))&IOMUXC_PTC26_SPEED_MASK)
#define IOMUXC_PTC26_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC26_MUX_MODE_SHIFT              20
#define IOMUXC_PTC26_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC26_MUX_MODE_SHIFT))&IOMUXC_PTC26_MUX_MODE_MASK)
/* PTC27 Bit Fields */
#define IOMUXC_PTC27_IBE_MASK                    0x1u
#define IOMUXC_PTC27_IBE_SHIFT                   0
#define IOMUXC_PTC27_OBE_MASK                    0x2u
#define IOMUXC_PTC27_OBE_SHIFT                   1
#define IOMUXC_PTC27_PUE_MASK                    0x4u
#define IOMUXC_PTC27_PUE_SHIFT                   2
#define IOMUXC_PTC27_PKE_MASK                    0x8u
#define IOMUXC_PTC27_PKE_SHIFT                   3
#define IOMUXC_PTC27_PUS_MASK                    0x30u
#define IOMUXC_PTC27_PUS_SHIFT                   4
#define IOMUXC_PTC27_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC27_PUS_SHIFT))&IOMUXC_PTC27_PUS_MASK)
#define IOMUXC_PTC27_DSE_MASK                    0x1C0u
#define IOMUXC_PTC27_DSE_SHIFT                   6
#define IOMUXC_PTC27_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC27_DSE_SHIFT))&IOMUXC_PTC27_DSE_MASK)
#define IOMUXC_PTC27_HYS_MASK                    0x200u
#define IOMUXC_PTC27_HYS_SHIFT                   9
#define IOMUXC_PTC27_ODE_MASK                    0x400u
#define IOMUXC_PTC27_ODE_SHIFT                   10
#define IOMUXC_PTC27_SRE_MASK                    0x800u
#define IOMUXC_PTC27_SRE_SHIFT                   11
#define IOMUXC_PTC27_SPEED_MASK                  0x3000u
#define IOMUXC_PTC27_SPEED_SHIFT                 12
#define IOMUXC_PTC27_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC27_SPEED_SHIFT))&IOMUXC_PTC27_SPEED_MASK)
#define IOMUXC_PTC27_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC27_MUX_MODE_SHIFT              20
#define IOMUXC_PTC27_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC27_MUX_MODE_SHIFT))&IOMUXC_PTC27_MUX_MODE_MASK)
/* PTC28 Bit Fields */
#define IOMUXC_PTC28_IBE_MASK                    0x1u
#define IOMUXC_PTC28_IBE_SHIFT                   0
#define IOMUXC_PTC28_OBE_MASK                    0x2u
#define IOMUXC_PTC28_OBE_SHIFT                   1
#define IOMUXC_PTC28_PUE_MASK                    0x4u
#define IOMUXC_PTC28_PUE_SHIFT                   2
#define IOMUXC_PTC28_PKE_MASK                    0x8u
#define IOMUXC_PTC28_PKE_SHIFT                   3
#define IOMUXC_PTC28_PUS_MASK                    0x30u
#define IOMUXC_PTC28_PUS_SHIFT                   4
#define IOMUXC_PTC28_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC28_PUS_SHIFT))&IOMUXC_PTC28_PUS_MASK)
#define IOMUXC_PTC28_DSE_MASK                    0x1C0u
#define IOMUXC_PTC28_DSE_SHIFT                   6
#define IOMUXC_PTC28_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC28_DSE_SHIFT))&IOMUXC_PTC28_DSE_MASK)
#define IOMUXC_PTC28_HYS_MASK                    0x200u
#define IOMUXC_PTC28_HYS_SHIFT                   9
#define IOMUXC_PTC28_ODE_MASK                    0x400u
#define IOMUXC_PTC28_ODE_SHIFT                   10
#define IOMUXC_PTC28_SRE_MASK                    0x800u
#define IOMUXC_PTC28_SRE_SHIFT                   11
#define IOMUXC_PTC28_SPEED_MASK                  0x3000u
#define IOMUXC_PTC28_SPEED_SHIFT                 12
#define IOMUXC_PTC28_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC28_SPEED_SHIFT))&IOMUXC_PTC28_SPEED_MASK)
#define IOMUXC_PTC28_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC28_MUX_MODE_SHIFT              20
#define IOMUXC_PTC28_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC28_MUX_MODE_SHIFT))&IOMUXC_PTC28_MUX_MODE_MASK)
/* PTC29 Bit Fields */
#define IOMUXC_PTC29_IBE_MASK                    0x1u
#define IOMUXC_PTC29_IBE_SHIFT                   0
#define IOMUXC_PTC29_OBE_MASK                    0x2u
#define IOMUXC_PTC29_OBE_SHIFT                   1
#define IOMUXC_PTC29_PUE_MASK                    0x4u
#define IOMUXC_PTC29_PUE_SHIFT                   2
#define IOMUXC_PTC29_PKE_MASK                    0x8u
#define IOMUXC_PTC29_PKE_SHIFT                   3
#define IOMUXC_PTC29_PUS_MASK                    0x30u
#define IOMUXC_PTC29_PUS_SHIFT                   4
#define IOMUXC_PTC29_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC29_PUS_SHIFT))&IOMUXC_PTC29_PUS_MASK)
#define IOMUXC_PTC29_DSE_MASK                    0x1C0u
#define IOMUXC_PTC29_DSE_SHIFT                   6
#define IOMUXC_PTC29_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC29_DSE_SHIFT))&IOMUXC_PTC29_DSE_MASK)
#define IOMUXC_PTC29_HYS_MASK                    0x200u
#define IOMUXC_PTC29_HYS_SHIFT                   9
#define IOMUXC_PTC29_ODE_MASK                    0x400u
#define IOMUXC_PTC29_ODE_SHIFT                   10
#define IOMUXC_PTC29_SRE_MASK                    0x800u
#define IOMUXC_PTC29_SRE_SHIFT                   11
#define IOMUXC_PTC29_SPEED_MASK                  0x3000u
#define IOMUXC_PTC29_SPEED_SHIFT                 12
#define IOMUXC_PTC29_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC29_SPEED_SHIFT))&IOMUXC_PTC29_SPEED_MASK)
#define IOMUXC_PTC29_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC29_MUX_MODE_SHIFT              20
#define IOMUXC_PTC29_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC29_MUX_MODE_SHIFT))&IOMUXC_PTC29_MUX_MODE_MASK)
/* PTC30 Bit Fields */
#define IOMUXC_PTC30_IBE_MASK                    0x1u
#define IOMUXC_PTC30_IBE_SHIFT                   0
#define IOMUXC_PTC30_OBE_MASK                    0x2u
#define IOMUXC_PTC30_OBE_SHIFT                   1
#define IOMUXC_PTC30_PUE_MASK                    0x4u
#define IOMUXC_PTC30_PUE_SHIFT                   2
#define IOMUXC_PTC30_PKE_MASK                    0x8u
#define IOMUXC_PTC30_PKE_SHIFT                   3
#define IOMUXC_PTC30_PUS_MASK                    0x30u
#define IOMUXC_PTC30_PUS_SHIFT                   4
#define IOMUXC_PTC30_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC30_PUS_SHIFT))&IOMUXC_PTC30_PUS_MASK)
#define IOMUXC_PTC30_DSE_MASK                    0x1C0u
#define IOMUXC_PTC30_DSE_SHIFT                   6
#define IOMUXC_PTC30_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC30_DSE_SHIFT))&IOMUXC_PTC30_DSE_MASK)
#define IOMUXC_PTC30_HYS_MASK                    0x200u
#define IOMUXC_PTC30_HYS_SHIFT                   9
#define IOMUXC_PTC30_ODE_MASK                    0x400u
#define IOMUXC_PTC30_ODE_SHIFT                   10
#define IOMUXC_PTC30_SRE_MASK                    0x800u
#define IOMUXC_PTC30_SRE_SHIFT                   11
#define IOMUXC_PTC30_SPEED_MASK                  0x3000u
#define IOMUXC_PTC30_SPEED_SHIFT                 12
#define IOMUXC_PTC30_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC30_SPEED_SHIFT))&IOMUXC_PTC30_SPEED_MASK)
#define IOMUXC_PTC30_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC30_MUX_MODE_SHIFT              20
#define IOMUXC_PTC30_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC30_MUX_MODE_SHIFT))&IOMUXC_PTC30_MUX_MODE_MASK)
/* PTC31 Bit Fields */
#define IOMUXC_PTC31_IBE_MASK                    0x1u
#define IOMUXC_PTC31_IBE_SHIFT                   0
#define IOMUXC_PTC31_OBE_MASK                    0x2u
#define IOMUXC_PTC31_OBE_SHIFT                   1
#define IOMUXC_PTC31_PUE_MASK                    0x4u
#define IOMUXC_PTC31_PUE_SHIFT                   2
#define IOMUXC_PTC31_PKE_MASK                    0x8u
#define IOMUXC_PTC31_PKE_SHIFT                   3
#define IOMUXC_PTC31_PUS_MASK                    0x30u
#define IOMUXC_PTC31_PUS_SHIFT                   4
#define IOMUXC_PTC31_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC31_PUS_SHIFT))&IOMUXC_PTC31_PUS_MASK)
#define IOMUXC_PTC31_DSE_MASK                    0x1C0u
#define IOMUXC_PTC31_DSE_SHIFT                   6
#define IOMUXC_PTC31_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC31_DSE_SHIFT))&IOMUXC_PTC31_DSE_MASK)
#define IOMUXC_PTC31_HYS_MASK                    0x200u
#define IOMUXC_PTC31_HYS_SHIFT                   9
#define IOMUXC_PTC31_ODE_MASK                    0x400u
#define IOMUXC_PTC31_ODE_SHIFT                   10
#define IOMUXC_PTC31_SRE_MASK                    0x800u
#define IOMUXC_PTC31_SRE_SHIFT                   11
#define IOMUXC_PTC31_SPEED_MASK                  0x3000u
#define IOMUXC_PTC31_SPEED_SHIFT                 12
#define IOMUXC_PTC31_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC31_SPEED_SHIFT))&IOMUXC_PTC31_SPEED_MASK)
#define IOMUXC_PTC31_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTC31_MUX_MODE_SHIFT              20
#define IOMUXC_PTC31_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTC31_MUX_MODE_SHIFT))&IOMUXC_PTC31_MUX_MODE_MASK)
/* PTE0 Bit Fields */
#define IOMUXC_PTE0_IBE_MASK                     0x1u
#define IOMUXC_PTE0_IBE_SHIFT                    0
#define IOMUXC_PTE0_OBE_MASK                     0x2u
#define IOMUXC_PTE0_OBE_SHIFT                    1
#define IOMUXC_PTE0_PUE_MASK                     0x4u
#define IOMUXC_PTE0_PUE_SHIFT                    2
#define IOMUXC_PTE0_PKE_MASK                     0x8u
#define IOMUXC_PTE0_PKE_SHIFT                    3
#define IOMUXC_PTE0_PUS_MASK                     0x30u
#define IOMUXC_PTE0_PUS_SHIFT                    4
#define IOMUXC_PTE0_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE0_PUS_SHIFT))&IOMUXC_PTE0_PUS_MASK)
#define IOMUXC_PTE0_DSE_MASK                     0x1C0u
#define IOMUXC_PTE0_DSE_SHIFT                    6
#define IOMUXC_PTE0_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE0_DSE_SHIFT))&IOMUXC_PTE0_DSE_MASK)
#define IOMUXC_PTE0_HYS_MASK                     0x200u
#define IOMUXC_PTE0_HYS_SHIFT                    9
#define IOMUXC_PTE0_ODE_MASK                     0x400u
#define IOMUXC_PTE0_ODE_SHIFT                    10
#define IOMUXC_PTE0_SRE_MASK                     0x800u
#define IOMUXC_PTE0_SRE_SHIFT                    11
#define IOMUXC_PTE0_SPEED_MASK                   0x3000u
#define IOMUXC_PTE0_SPEED_SHIFT                  12
#define IOMUXC_PTE0_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE0_SPEED_SHIFT))&IOMUXC_PTE0_SPEED_MASK)
#define IOMUXC_PTE0_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE0_MUX_MODE_SHIFT               20
#define IOMUXC_PTE0_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE0_MUX_MODE_SHIFT))&IOMUXC_PTE0_MUX_MODE_MASK)
/* PTE1 Bit Fields */
#define IOMUXC_PTE1_IBE_MASK                     0x1u
#define IOMUXC_PTE1_IBE_SHIFT                    0
#define IOMUXC_PTE1_OBE_MASK                     0x2u
#define IOMUXC_PTE1_OBE_SHIFT                    1
#define IOMUXC_PTE1_PUE_MASK                     0x4u
#define IOMUXC_PTE1_PUE_SHIFT                    2
#define IOMUXC_PTE1_PKE_MASK                     0x8u
#define IOMUXC_PTE1_PKE_SHIFT                    3
#define IOMUXC_PTE1_PUS_MASK                     0x30u
#define IOMUXC_PTE1_PUS_SHIFT                    4
#define IOMUXC_PTE1_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE1_PUS_SHIFT))&IOMUXC_PTE1_PUS_MASK)
#define IOMUXC_PTE1_DSE_MASK                     0x1C0u
#define IOMUXC_PTE1_DSE_SHIFT                    6
#define IOMUXC_PTE1_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE1_DSE_SHIFT))&IOMUXC_PTE1_DSE_MASK)
#define IOMUXC_PTE1_HYS_MASK                     0x200u
#define IOMUXC_PTE1_HYS_SHIFT                    9
#define IOMUXC_PTE1_ODE_MASK                     0x400u
#define IOMUXC_PTE1_ODE_SHIFT                    10
#define IOMUXC_PTE1_SRE_MASK                     0x800u
#define IOMUXC_PTE1_SRE_SHIFT                    11
#define IOMUXC_PTE1_SPEED_MASK                   0x3000u
#define IOMUXC_PTE1_SPEED_SHIFT                  12
#define IOMUXC_PTE1_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE1_SPEED_SHIFT))&IOMUXC_PTE1_SPEED_MASK)
#define IOMUXC_PTE1_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE1_MUX_MODE_SHIFT               20
#define IOMUXC_PTE1_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE1_MUX_MODE_SHIFT))&IOMUXC_PTE1_MUX_MODE_MASK)
/* PTE2 Bit Fields */
#define IOMUXC_PTE2_IBE_MASK                     0x1u
#define IOMUXC_PTE2_IBE_SHIFT                    0
#define IOMUXC_PTE2_OBE_MASK                     0x2u
#define IOMUXC_PTE2_OBE_SHIFT                    1
#define IOMUXC_PTE2_PUE_MASK                     0x4u
#define IOMUXC_PTE2_PUE_SHIFT                    2
#define IOMUXC_PTE2_PKE_MASK                     0x8u
#define IOMUXC_PTE2_PKE_SHIFT                    3
#define IOMUXC_PTE2_PUS_MASK                     0x30u
#define IOMUXC_PTE2_PUS_SHIFT                    4
#define IOMUXC_PTE2_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE2_PUS_SHIFT))&IOMUXC_PTE2_PUS_MASK)
#define IOMUXC_PTE2_DSE_MASK                     0x1C0u
#define IOMUXC_PTE2_DSE_SHIFT                    6
#define IOMUXC_PTE2_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE2_DSE_SHIFT))&IOMUXC_PTE2_DSE_MASK)
#define IOMUXC_PTE2_HYS_MASK                     0x200u
#define IOMUXC_PTE2_HYS_SHIFT                    9
#define IOMUXC_PTE2_ODE_MASK                     0x400u
#define IOMUXC_PTE2_ODE_SHIFT                    10
#define IOMUXC_PTE2_SRE_MASK                     0x800u
#define IOMUXC_PTE2_SRE_SHIFT                    11
#define IOMUXC_PTE2_SPEED_MASK                   0x3000u
#define IOMUXC_PTE2_SPEED_SHIFT                  12
#define IOMUXC_PTE2_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE2_SPEED_SHIFT))&IOMUXC_PTE2_SPEED_MASK)
#define IOMUXC_PTE2_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE2_MUX_MODE_SHIFT               20
#define IOMUXC_PTE2_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE2_MUX_MODE_SHIFT))&IOMUXC_PTE2_MUX_MODE_MASK)
/* PTE3 Bit Fields */
#define IOMUXC_PTE3_IBE_MASK                     0x1u
#define IOMUXC_PTE3_IBE_SHIFT                    0
#define IOMUXC_PTE3_OBE_MASK                     0x2u
#define IOMUXC_PTE3_OBE_SHIFT                    1
#define IOMUXC_PTE3_PUE_MASK                     0x4u
#define IOMUXC_PTE3_PUE_SHIFT                    2
#define IOMUXC_PTE3_PKE_MASK                     0x8u
#define IOMUXC_PTE3_PKE_SHIFT                    3
#define IOMUXC_PTE3_PUS_MASK                     0x30u
#define IOMUXC_PTE3_PUS_SHIFT                    4
#define IOMUXC_PTE3_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE3_PUS_SHIFT))&IOMUXC_PTE3_PUS_MASK)
#define IOMUXC_PTE3_DSE_MASK                     0x1C0u
#define IOMUXC_PTE3_DSE_SHIFT                    6
#define IOMUXC_PTE3_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE3_DSE_SHIFT))&IOMUXC_PTE3_DSE_MASK)
#define IOMUXC_PTE3_HYS_MASK                     0x200u
#define IOMUXC_PTE3_HYS_SHIFT                    9
#define IOMUXC_PTE3_ODE_MASK                     0x400u
#define IOMUXC_PTE3_ODE_SHIFT                    10
#define IOMUXC_PTE3_SRE_MASK                     0x800u
#define IOMUXC_PTE3_SRE_SHIFT                    11
#define IOMUXC_PTE3_SPEED_MASK                   0x3000u
#define IOMUXC_PTE3_SPEED_SHIFT                  12
#define IOMUXC_PTE3_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE3_SPEED_SHIFT))&IOMUXC_PTE3_SPEED_MASK)
#define IOMUXC_PTE3_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE3_MUX_MODE_SHIFT               20
#define IOMUXC_PTE3_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE3_MUX_MODE_SHIFT))&IOMUXC_PTE3_MUX_MODE_MASK)
/* PTE4 Bit Fields */
#define IOMUXC_PTE4_IBE_MASK                     0x1u
#define IOMUXC_PTE4_IBE_SHIFT                    0
#define IOMUXC_PTE4_OBE_MASK                     0x2u
#define IOMUXC_PTE4_OBE_SHIFT                    1
#define IOMUXC_PTE4_PUE_MASK                     0x4u
#define IOMUXC_PTE4_PUE_SHIFT                    2
#define IOMUXC_PTE4_PKE_MASK                     0x8u
#define IOMUXC_PTE4_PKE_SHIFT                    3
#define IOMUXC_PTE4_PUS_MASK                     0x30u
#define IOMUXC_PTE4_PUS_SHIFT                    4
#define IOMUXC_PTE4_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE4_PUS_SHIFT))&IOMUXC_PTE4_PUS_MASK)
#define IOMUXC_PTE4_DSE_MASK                     0x1C0u
#define IOMUXC_PTE4_DSE_SHIFT                    6
#define IOMUXC_PTE4_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE4_DSE_SHIFT))&IOMUXC_PTE4_DSE_MASK)
#define IOMUXC_PTE4_HYS_MASK                     0x200u
#define IOMUXC_PTE4_HYS_SHIFT                    9
#define IOMUXC_PTE4_ODE_MASK                     0x400u
#define IOMUXC_PTE4_ODE_SHIFT                    10
#define IOMUXC_PTE4_SRE_MASK                     0x800u
#define IOMUXC_PTE4_SRE_SHIFT                    11
#define IOMUXC_PTE4_SPEED_MASK                   0x3000u
#define IOMUXC_PTE4_SPEED_SHIFT                  12
#define IOMUXC_PTE4_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE4_SPEED_SHIFT))&IOMUXC_PTE4_SPEED_MASK)
#define IOMUXC_PTE4_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE4_MUX_MODE_SHIFT               20
#define IOMUXC_PTE4_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE4_MUX_MODE_SHIFT))&IOMUXC_PTE4_MUX_MODE_MASK)
/* PTE5 Bit Fields */
#define IOMUXC_PTE5_IBE_MASK                     0x1u
#define IOMUXC_PTE5_IBE_SHIFT                    0
#define IOMUXC_PTE5_OBE_MASK                     0x2u
#define IOMUXC_PTE5_OBE_SHIFT                    1
#define IOMUXC_PTE5_PUE_MASK                     0x4u
#define IOMUXC_PTE5_PUE_SHIFT                    2
#define IOMUXC_PTE5_PKE_MASK                     0x8u
#define IOMUXC_PTE5_PKE_SHIFT                    3
#define IOMUXC_PTE5_PUS_MASK                     0x30u
#define IOMUXC_PTE5_PUS_SHIFT                    4
#define IOMUXC_PTE5_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE5_PUS_SHIFT))&IOMUXC_PTE5_PUS_MASK)
#define IOMUXC_PTE5_DSE_MASK                     0x1C0u
#define IOMUXC_PTE5_DSE_SHIFT                    6
#define IOMUXC_PTE5_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE5_DSE_SHIFT))&IOMUXC_PTE5_DSE_MASK)
#define IOMUXC_PTE5_HYS_MASK                     0x200u
#define IOMUXC_PTE5_HYS_SHIFT                    9
#define IOMUXC_PTE5_ODE_MASK                     0x400u
#define IOMUXC_PTE5_ODE_SHIFT                    10
#define IOMUXC_PTE5_SRE_MASK                     0x800u
#define IOMUXC_PTE5_SRE_SHIFT                    11
#define IOMUXC_PTE5_SPEED_MASK                   0x3000u
#define IOMUXC_PTE5_SPEED_SHIFT                  12
#define IOMUXC_PTE5_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE5_SPEED_SHIFT))&IOMUXC_PTE5_SPEED_MASK)
#define IOMUXC_PTE5_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE5_MUX_MODE_SHIFT               20
#define IOMUXC_PTE5_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE5_MUX_MODE_SHIFT))&IOMUXC_PTE5_MUX_MODE_MASK)
/* PTE6 Bit Fields */
#define IOMUXC_PTE6_IBE_MASK                     0x1u
#define IOMUXC_PTE6_IBE_SHIFT                    0
#define IOMUXC_PTE6_OBE_MASK                     0x2u
#define IOMUXC_PTE6_OBE_SHIFT                    1
#define IOMUXC_PTE6_PUE_MASK                     0x4u
#define IOMUXC_PTE6_PUE_SHIFT                    2
#define IOMUXC_PTE6_PKE_MASK                     0x8u
#define IOMUXC_PTE6_PKE_SHIFT                    3
#define IOMUXC_PTE6_PUS_MASK                     0x30u
#define IOMUXC_PTE6_PUS_SHIFT                    4
#define IOMUXC_PTE6_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE6_PUS_SHIFT))&IOMUXC_PTE6_PUS_MASK)
#define IOMUXC_PTE6_DSE_MASK                     0x1C0u
#define IOMUXC_PTE6_DSE_SHIFT                    6
#define IOMUXC_PTE6_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE6_DSE_SHIFT))&IOMUXC_PTE6_DSE_MASK)
#define IOMUXC_PTE6_HYS_MASK                     0x200u
#define IOMUXC_PTE6_HYS_SHIFT                    9
#define IOMUXC_PTE6_ODE_MASK                     0x400u
#define IOMUXC_PTE6_ODE_SHIFT                    10
#define IOMUXC_PTE6_SRE_MASK                     0x800u
#define IOMUXC_PTE6_SRE_SHIFT                    11
#define IOMUXC_PTE6_SPEED_MASK                   0x3000u
#define IOMUXC_PTE6_SPEED_SHIFT                  12
#define IOMUXC_PTE6_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE6_SPEED_SHIFT))&IOMUXC_PTE6_SPEED_MASK)
#define IOMUXC_PTE6_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE6_MUX_MODE_SHIFT               20
#define IOMUXC_PTE6_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE6_MUX_MODE_SHIFT))&IOMUXC_PTE6_MUX_MODE_MASK)
/* PTE7 Bit Fields */
#define IOMUXC_PTE7_IBE_MASK                     0x1u
#define IOMUXC_PTE7_IBE_SHIFT                    0
#define IOMUXC_PTE7_OBE_MASK                     0x2u
#define IOMUXC_PTE7_OBE_SHIFT                    1
#define IOMUXC_PTE7_PUE_MASK                     0x4u
#define IOMUXC_PTE7_PUE_SHIFT                    2
#define IOMUXC_PTE7_PKE_MASK                     0x8u
#define IOMUXC_PTE7_PKE_SHIFT                    3
#define IOMUXC_PTE7_PUS_MASK                     0x30u
#define IOMUXC_PTE7_PUS_SHIFT                    4
#define IOMUXC_PTE7_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE7_PUS_SHIFT))&IOMUXC_PTE7_PUS_MASK)
#define IOMUXC_PTE7_DSE_MASK                     0x1C0u
#define IOMUXC_PTE7_DSE_SHIFT                    6
#define IOMUXC_PTE7_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE7_DSE_SHIFT))&IOMUXC_PTE7_DSE_MASK)
#define IOMUXC_PTE7_HYS_MASK                     0x200u
#define IOMUXC_PTE7_HYS_SHIFT                    9
#define IOMUXC_PTE7_ODE_MASK                     0x400u
#define IOMUXC_PTE7_ODE_SHIFT                    10
#define IOMUXC_PTE7_SRE_MASK                     0x800u
#define IOMUXC_PTE7_SRE_SHIFT                    11
#define IOMUXC_PTE7_SPEED_MASK                   0x3000u
#define IOMUXC_PTE7_SPEED_SHIFT                  12
#define IOMUXC_PTE7_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE7_SPEED_SHIFT))&IOMUXC_PTE7_SPEED_MASK)
#define IOMUXC_PTE7_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE7_MUX_MODE_SHIFT               20
#define IOMUXC_PTE7_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE7_MUX_MODE_SHIFT))&IOMUXC_PTE7_MUX_MODE_MASK)
/* PTE8 Bit Fields */
#define IOMUXC_PTE8_IBE_MASK                     0x1u
#define IOMUXC_PTE8_IBE_SHIFT                    0
#define IOMUXC_PTE8_OBE_MASK                     0x2u
#define IOMUXC_PTE8_OBE_SHIFT                    1
#define IOMUXC_PTE8_PUE_MASK                     0x4u
#define IOMUXC_PTE8_PUE_SHIFT                    2
#define IOMUXC_PTE8_PKE_MASK                     0x8u
#define IOMUXC_PTE8_PKE_SHIFT                    3
#define IOMUXC_PTE8_PUS_MASK                     0x30u
#define IOMUXC_PTE8_PUS_SHIFT                    4
#define IOMUXC_PTE8_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE8_PUS_SHIFT))&IOMUXC_PTE8_PUS_MASK)
#define IOMUXC_PTE8_DSE_MASK                     0x1C0u
#define IOMUXC_PTE8_DSE_SHIFT                    6
#define IOMUXC_PTE8_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE8_DSE_SHIFT))&IOMUXC_PTE8_DSE_MASK)
#define IOMUXC_PTE8_HYS_MASK                     0x200u
#define IOMUXC_PTE8_HYS_SHIFT                    9
#define IOMUXC_PTE8_ODE_MASK                     0x400u
#define IOMUXC_PTE8_ODE_SHIFT                    10
#define IOMUXC_PTE8_SRE_MASK                     0x800u
#define IOMUXC_PTE8_SRE_SHIFT                    11
#define IOMUXC_PTE8_SPEED_MASK                   0x3000u
#define IOMUXC_PTE8_SPEED_SHIFT                  12
#define IOMUXC_PTE8_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE8_SPEED_SHIFT))&IOMUXC_PTE8_SPEED_MASK)
#define IOMUXC_PTE8_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE8_MUX_MODE_SHIFT               20
#define IOMUXC_PTE8_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE8_MUX_MODE_SHIFT))&IOMUXC_PTE8_MUX_MODE_MASK)
/* PTE9 Bit Fields */
#define IOMUXC_PTE9_IBE_MASK                     0x1u
#define IOMUXC_PTE9_IBE_SHIFT                    0
#define IOMUXC_PTE9_OBE_MASK                     0x2u
#define IOMUXC_PTE9_OBE_SHIFT                    1
#define IOMUXC_PTE9_PUE_MASK                     0x4u
#define IOMUXC_PTE9_PUE_SHIFT                    2
#define IOMUXC_PTE9_PKE_MASK                     0x8u
#define IOMUXC_PTE9_PKE_SHIFT                    3
#define IOMUXC_PTE9_PUS_MASK                     0x30u
#define IOMUXC_PTE9_PUS_SHIFT                    4
#define IOMUXC_PTE9_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE9_PUS_SHIFT))&IOMUXC_PTE9_PUS_MASK)
#define IOMUXC_PTE9_DSE_MASK                     0x1C0u
#define IOMUXC_PTE9_DSE_SHIFT                    6
#define IOMUXC_PTE9_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE9_DSE_SHIFT))&IOMUXC_PTE9_DSE_MASK)
#define IOMUXC_PTE9_HYS_MASK                     0x200u
#define IOMUXC_PTE9_HYS_SHIFT                    9
#define IOMUXC_PTE9_ODE_MASK                     0x400u
#define IOMUXC_PTE9_ODE_SHIFT                    10
#define IOMUXC_PTE9_SRE_MASK                     0x800u
#define IOMUXC_PTE9_SRE_SHIFT                    11
#define IOMUXC_PTE9_SPEED_MASK                   0x3000u
#define IOMUXC_PTE9_SPEED_SHIFT                  12
#define IOMUXC_PTE9_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE9_SPEED_SHIFT))&IOMUXC_PTE9_SPEED_MASK)
#define IOMUXC_PTE9_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTE9_MUX_MODE_SHIFT               20
#define IOMUXC_PTE9_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE9_MUX_MODE_SHIFT))&IOMUXC_PTE9_MUX_MODE_MASK)
/* PTE10 Bit Fields */
#define IOMUXC_PTE10_IBE_MASK                    0x1u
#define IOMUXC_PTE10_IBE_SHIFT                   0
#define IOMUXC_PTE10_OBE_MASK                    0x2u
#define IOMUXC_PTE10_OBE_SHIFT                   1
#define IOMUXC_PTE10_PUE_MASK                    0x4u
#define IOMUXC_PTE10_PUE_SHIFT                   2
#define IOMUXC_PTE10_PKE_MASK                    0x8u
#define IOMUXC_PTE10_PKE_SHIFT                   3
#define IOMUXC_PTE10_PUS_MASK                    0x30u
#define IOMUXC_PTE10_PUS_SHIFT                   4
#define IOMUXC_PTE10_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE10_PUS_SHIFT))&IOMUXC_PTE10_PUS_MASK)
#define IOMUXC_PTE10_DSE_MASK                    0x1C0u
#define IOMUXC_PTE10_DSE_SHIFT                   6
#define IOMUXC_PTE10_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE10_DSE_SHIFT))&IOMUXC_PTE10_DSE_MASK)
#define IOMUXC_PTE10_HYS_MASK                    0x200u
#define IOMUXC_PTE10_HYS_SHIFT                   9
#define IOMUXC_PTE10_ODE_MASK                    0x400u
#define IOMUXC_PTE10_ODE_SHIFT                   10
#define IOMUXC_PTE10_SRE_MASK                    0x800u
#define IOMUXC_PTE10_SRE_SHIFT                   11
#define IOMUXC_PTE10_SPEED_MASK                  0x3000u
#define IOMUXC_PTE10_SPEED_SHIFT                 12
#define IOMUXC_PTE10_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE10_SPEED_SHIFT))&IOMUXC_PTE10_SPEED_MASK)
#define IOMUXC_PTE10_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE10_MUX_MODE_SHIFT              20
#define IOMUXC_PTE10_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE10_MUX_MODE_SHIFT))&IOMUXC_PTE10_MUX_MODE_MASK)
/* PTE11 Bit Fields */
#define IOMUXC_PTE11_IBE_MASK                    0x1u
#define IOMUXC_PTE11_IBE_SHIFT                   0
#define IOMUXC_PTE11_OBE_MASK                    0x2u
#define IOMUXC_PTE11_OBE_SHIFT                   1
#define IOMUXC_PTE11_PUE_MASK                    0x4u
#define IOMUXC_PTE11_PUE_SHIFT                   2
#define IOMUXC_PTE11_PKE_MASK                    0x8u
#define IOMUXC_PTE11_PKE_SHIFT                   3
#define IOMUXC_PTE11_PUS_MASK                    0x30u
#define IOMUXC_PTE11_PUS_SHIFT                   4
#define IOMUXC_PTE11_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE11_PUS_SHIFT))&IOMUXC_PTE11_PUS_MASK)
#define IOMUXC_PTE11_DSE_MASK                    0x1C0u
#define IOMUXC_PTE11_DSE_SHIFT                   6
#define IOMUXC_PTE11_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE11_DSE_SHIFT))&IOMUXC_PTE11_DSE_MASK)
#define IOMUXC_PTE11_HYS_MASK                    0x200u
#define IOMUXC_PTE11_HYS_SHIFT                   9
#define IOMUXC_PTE11_ODE_MASK                    0x400u
#define IOMUXC_PTE11_ODE_SHIFT                   10
#define IOMUXC_PTE11_SRE_MASK                    0x800u
#define IOMUXC_PTE11_SRE_SHIFT                   11
#define IOMUXC_PTE11_SPEED_MASK                  0x3000u
#define IOMUXC_PTE11_SPEED_SHIFT                 12
#define IOMUXC_PTE11_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE11_SPEED_SHIFT))&IOMUXC_PTE11_SPEED_MASK)
#define IOMUXC_PTE11_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE11_MUX_MODE_SHIFT              20
#define IOMUXC_PTE11_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE11_MUX_MODE_SHIFT))&IOMUXC_PTE11_MUX_MODE_MASK)
/* PTE12 Bit Fields */
#define IOMUXC_PTE12_IBE_MASK                    0x1u
#define IOMUXC_PTE12_IBE_SHIFT                   0
#define IOMUXC_PTE12_OBE_MASK                    0x2u
#define IOMUXC_PTE12_OBE_SHIFT                   1
#define IOMUXC_PTE12_PUE_MASK                    0x4u
#define IOMUXC_PTE12_PUE_SHIFT                   2
#define IOMUXC_PTE12_PKE_MASK                    0x8u
#define IOMUXC_PTE12_PKE_SHIFT                   3
#define IOMUXC_PTE12_PUS_MASK                    0x30u
#define IOMUXC_PTE12_PUS_SHIFT                   4
#define IOMUXC_PTE12_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE12_PUS_SHIFT))&IOMUXC_PTE12_PUS_MASK)
#define IOMUXC_PTE12_DSE_MASK                    0x1C0u
#define IOMUXC_PTE12_DSE_SHIFT                   6
#define IOMUXC_PTE12_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE12_DSE_SHIFT))&IOMUXC_PTE12_DSE_MASK)
#define IOMUXC_PTE12_HYS_MASK                    0x200u
#define IOMUXC_PTE12_HYS_SHIFT                   9
#define IOMUXC_PTE12_ODE_MASK                    0x400u
#define IOMUXC_PTE12_ODE_SHIFT                   10
#define IOMUXC_PTE12_SRE_MASK                    0x800u
#define IOMUXC_PTE12_SRE_SHIFT                   11
#define IOMUXC_PTE12_SPEED_MASK                  0x3000u
#define IOMUXC_PTE12_SPEED_SHIFT                 12
#define IOMUXC_PTE12_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE12_SPEED_SHIFT))&IOMUXC_PTE12_SPEED_MASK)
#define IOMUXC_PTE12_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE12_MUX_MODE_SHIFT              20
#define IOMUXC_PTE12_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE12_MUX_MODE_SHIFT))&IOMUXC_PTE12_MUX_MODE_MASK)
/* PTE13 Bit Fields */
#define IOMUXC_PTE13_IBE_MASK                    0x1u
#define IOMUXC_PTE13_IBE_SHIFT                   0
#define IOMUXC_PTE13_OBE_MASK                    0x2u
#define IOMUXC_PTE13_OBE_SHIFT                   1
#define IOMUXC_PTE13_PUE_MASK                    0x4u
#define IOMUXC_PTE13_PUE_SHIFT                   2
#define IOMUXC_PTE13_PKE_MASK                    0x8u
#define IOMUXC_PTE13_PKE_SHIFT                   3
#define IOMUXC_PTE13_PUS_MASK                    0x30u
#define IOMUXC_PTE13_PUS_SHIFT                   4
#define IOMUXC_PTE13_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE13_PUS_SHIFT))&IOMUXC_PTE13_PUS_MASK)
#define IOMUXC_PTE13_DSE_MASK                    0x1C0u
#define IOMUXC_PTE13_DSE_SHIFT                   6
#define IOMUXC_PTE13_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE13_DSE_SHIFT))&IOMUXC_PTE13_DSE_MASK)
#define IOMUXC_PTE13_HYS_MASK                    0x200u
#define IOMUXC_PTE13_HYS_SHIFT                   9
#define IOMUXC_PTE13_ODE_MASK                    0x400u
#define IOMUXC_PTE13_ODE_SHIFT                   10
#define IOMUXC_PTE13_SRE_MASK                    0x800u
#define IOMUXC_PTE13_SRE_SHIFT                   11
#define IOMUXC_PTE13_SPEED_MASK                  0x3000u
#define IOMUXC_PTE13_SPEED_SHIFT                 12
#define IOMUXC_PTE13_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE13_SPEED_SHIFT))&IOMUXC_PTE13_SPEED_MASK)
#define IOMUXC_PTE13_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE13_MUX_MODE_SHIFT              20
#define IOMUXC_PTE13_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE13_MUX_MODE_SHIFT))&IOMUXC_PTE13_MUX_MODE_MASK)
/* PTE14 Bit Fields */
#define IOMUXC_PTE14_IBE_MASK                    0x1u
#define IOMUXC_PTE14_IBE_SHIFT                   0
#define IOMUXC_PTE14_OBE_MASK                    0x2u
#define IOMUXC_PTE14_OBE_SHIFT                   1
#define IOMUXC_PTE14_PUE_MASK                    0x4u
#define IOMUXC_PTE14_PUE_SHIFT                   2
#define IOMUXC_PTE14_PKE_MASK                    0x8u
#define IOMUXC_PTE14_PKE_SHIFT                   3
#define IOMUXC_PTE14_PUS_MASK                    0x30u
#define IOMUXC_PTE14_PUS_SHIFT                   4
#define IOMUXC_PTE14_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE14_PUS_SHIFT))&IOMUXC_PTE14_PUS_MASK)
#define IOMUXC_PTE14_DSE_MASK                    0x1C0u
#define IOMUXC_PTE14_DSE_SHIFT                   6
#define IOMUXC_PTE14_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE14_DSE_SHIFT))&IOMUXC_PTE14_DSE_MASK)
#define IOMUXC_PTE14_HYS_MASK                    0x200u
#define IOMUXC_PTE14_HYS_SHIFT                   9
#define IOMUXC_PTE14_ODE_MASK                    0x400u
#define IOMUXC_PTE14_ODE_SHIFT                   10
#define IOMUXC_PTE14_SRE_MASK                    0x800u
#define IOMUXC_PTE14_SRE_SHIFT                   11
#define IOMUXC_PTE14_SPEED_MASK                  0x3000u
#define IOMUXC_PTE14_SPEED_SHIFT                 12
#define IOMUXC_PTE14_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE14_SPEED_SHIFT))&IOMUXC_PTE14_SPEED_MASK)
#define IOMUXC_PTE14_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE14_MUX_MODE_SHIFT              20
#define IOMUXC_PTE14_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE14_MUX_MODE_SHIFT))&IOMUXC_PTE14_MUX_MODE_MASK)
/* PTE15 Bit Fields */
#define IOMUXC_PTE15_IBE_MASK                    0x1u
#define IOMUXC_PTE15_IBE_SHIFT                   0
#define IOMUXC_PTE15_OBE_MASK                    0x2u
#define IOMUXC_PTE15_OBE_SHIFT                   1
#define IOMUXC_PTE15_PUE_MASK                    0x4u
#define IOMUXC_PTE15_PUE_SHIFT                   2
#define IOMUXC_PTE15_PKE_MASK                    0x8u
#define IOMUXC_PTE15_PKE_SHIFT                   3
#define IOMUXC_PTE15_PUS_MASK                    0x30u
#define IOMUXC_PTE15_PUS_SHIFT                   4
#define IOMUXC_PTE15_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE15_PUS_SHIFT))&IOMUXC_PTE15_PUS_MASK)
#define IOMUXC_PTE15_DSE_MASK                    0x1C0u
#define IOMUXC_PTE15_DSE_SHIFT                   6
#define IOMUXC_PTE15_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE15_DSE_SHIFT))&IOMUXC_PTE15_DSE_MASK)
#define IOMUXC_PTE15_HYS_MASK                    0x200u
#define IOMUXC_PTE15_HYS_SHIFT                   9
#define IOMUXC_PTE15_ODE_MASK                    0x400u
#define IOMUXC_PTE15_ODE_SHIFT                   10
#define IOMUXC_PTE15_SRE_MASK                    0x800u
#define IOMUXC_PTE15_SRE_SHIFT                   11
#define IOMUXC_PTE15_SPEED_MASK                  0x3000u
#define IOMUXC_PTE15_SPEED_SHIFT                 12
#define IOMUXC_PTE15_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE15_SPEED_SHIFT))&IOMUXC_PTE15_SPEED_MASK)
#define IOMUXC_PTE15_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE15_MUX_MODE_SHIFT              20
#define IOMUXC_PTE15_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE15_MUX_MODE_SHIFT))&IOMUXC_PTE15_MUX_MODE_MASK)
/* PTE16 Bit Fields */
#define IOMUXC_PTE16_IBE_MASK                    0x1u
#define IOMUXC_PTE16_IBE_SHIFT                   0
#define IOMUXC_PTE16_OBE_MASK                    0x2u
#define IOMUXC_PTE16_OBE_SHIFT                   1
#define IOMUXC_PTE16_PUE_MASK                    0x4u
#define IOMUXC_PTE16_PUE_SHIFT                   2
#define IOMUXC_PTE16_PKE_MASK                    0x8u
#define IOMUXC_PTE16_PKE_SHIFT                   3
#define IOMUXC_PTE16_PUS_MASK                    0x30u
#define IOMUXC_PTE16_PUS_SHIFT                   4
#define IOMUXC_PTE16_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE16_PUS_SHIFT))&IOMUXC_PTE16_PUS_MASK)
#define IOMUXC_PTE16_DSE_MASK                    0x1C0u
#define IOMUXC_PTE16_DSE_SHIFT                   6
#define IOMUXC_PTE16_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE16_DSE_SHIFT))&IOMUXC_PTE16_DSE_MASK)
#define IOMUXC_PTE16_HYS_MASK                    0x200u
#define IOMUXC_PTE16_HYS_SHIFT                   9
#define IOMUXC_PTE16_ODE_MASK                    0x400u
#define IOMUXC_PTE16_ODE_SHIFT                   10
#define IOMUXC_PTE16_SRE_MASK                    0x800u
#define IOMUXC_PTE16_SRE_SHIFT                   11
#define IOMUXC_PTE16_SPEED_MASK                  0x3000u
#define IOMUXC_PTE16_SPEED_SHIFT                 12
#define IOMUXC_PTE16_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE16_SPEED_SHIFT))&IOMUXC_PTE16_SPEED_MASK)
#define IOMUXC_PTE16_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE16_MUX_MODE_SHIFT              20
#define IOMUXC_PTE16_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE16_MUX_MODE_SHIFT))&IOMUXC_PTE16_MUX_MODE_MASK)
/* PTE17 Bit Fields */
#define IOMUXC_PTE17_IBE_MASK                    0x1u
#define IOMUXC_PTE17_IBE_SHIFT                   0
#define IOMUXC_PTE17_OBE_MASK                    0x2u
#define IOMUXC_PTE17_OBE_SHIFT                   1
#define IOMUXC_PTE17_PUE_MASK                    0x4u
#define IOMUXC_PTE17_PUE_SHIFT                   2
#define IOMUXC_PTE17_PKE_MASK                    0x8u
#define IOMUXC_PTE17_PKE_SHIFT                   3
#define IOMUXC_PTE17_PUS_MASK                    0x30u
#define IOMUXC_PTE17_PUS_SHIFT                   4
#define IOMUXC_PTE17_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE17_PUS_SHIFT))&IOMUXC_PTE17_PUS_MASK)
#define IOMUXC_PTE17_DSE_MASK                    0x1C0u
#define IOMUXC_PTE17_DSE_SHIFT                   6
#define IOMUXC_PTE17_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE17_DSE_SHIFT))&IOMUXC_PTE17_DSE_MASK)
#define IOMUXC_PTE17_HYS_MASK                    0x200u
#define IOMUXC_PTE17_HYS_SHIFT                   9
#define IOMUXC_PTE17_ODE_MASK                    0x400u
#define IOMUXC_PTE17_ODE_SHIFT                   10
#define IOMUXC_PTE17_SRE_MASK                    0x800u
#define IOMUXC_PTE17_SRE_SHIFT                   11
#define IOMUXC_PTE17_SPEED_MASK                  0x3000u
#define IOMUXC_PTE17_SPEED_SHIFT                 12
#define IOMUXC_PTE17_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE17_SPEED_SHIFT))&IOMUXC_PTE17_SPEED_MASK)
#define IOMUXC_PTE17_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE17_MUX_MODE_SHIFT              20
#define IOMUXC_PTE17_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE17_MUX_MODE_SHIFT))&IOMUXC_PTE17_MUX_MODE_MASK)
/* PTE18 Bit Fields */
#define IOMUXC_PTE18_IBE_MASK                    0x1u
#define IOMUXC_PTE18_IBE_SHIFT                   0
#define IOMUXC_PTE18_OBE_MASK                    0x2u
#define IOMUXC_PTE18_OBE_SHIFT                   1
#define IOMUXC_PTE18_PUE_MASK                    0x4u
#define IOMUXC_PTE18_PUE_SHIFT                   2
#define IOMUXC_PTE18_PKE_MASK                    0x8u
#define IOMUXC_PTE18_PKE_SHIFT                   3
#define IOMUXC_PTE18_PUS_MASK                    0x30u
#define IOMUXC_PTE18_PUS_SHIFT                   4
#define IOMUXC_PTE18_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE18_PUS_SHIFT))&IOMUXC_PTE18_PUS_MASK)
#define IOMUXC_PTE18_DSE_MASK                    0x1C0u
#define IOMUXC_PTE18_DSE_SHIFT                   6
#define IOMUXC_PTE18_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE18_DSE_SHIFT))&IOMUXC_PTE18_DSE_MASK)
#define IOMUXC_PTE18_HYS_MASK                    0x200u
#define IOMUXC_PTE18_HYS_SHIFT                   9
#define IOMUXC_PTE18_ODE_MASK                    0x400u
#define IOMUXC_PTE18_ODE_SHIFT                   10
#define IOMUXC_PTE18_SRE_MASK                    0x800u
#define IOMUXC_PTE18_SRE_SHIFT                   11
#define IOMUXC_PTE18_SPEED_MASK                  0x3000u
#define IOMUXC_PTE18_SPEED_SHIFT                 12
#define IOMUXC_PTE18_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE18_SPEED_SHIFT))&IOMUXC_PTE18_SPEED_MASK)
#define IOMUXC_PTE18_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE18_MUX_MODE_SHIFT              20
#define IOMUXC_PTE18_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE18_MUX_MODE_SHIFT))&IOMUXC_PTE18_MUX_MODE_MASK)
/* PTE19 Bit Fields */
#define IOMUXC_PTE19_IBE_MASK                    0x1u
#define IOMUXC_PTE19_IBE_SHIFT                   0
#define IOMUXC_PTE19_OBE_MASK                    0x2u
#define IOMUXC_PTE19_OBE_SHIFT                   1
#define IOMUXC_PTE19_PUE_MASK                    0x4u
#define IOMUXC_PTE19_PUE_SHIFT                   2
#define IOMUXC_PTE19_PKE_MASK                    0x8u
#define IOMUXC_PTE19_PKE_SHIFT                   3
#define IOMUXC_PTE19_PUS_MASK                    0x30u
#define IOMUXC_PTE19_PUS_SHIFT                   4
#define IOMUXC_PTE19_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE19_PUS_SHIFT))&IOMUXC_PTE19_PUS_MASK)
#define IOMUXC_PTE19_DSE_MASK                    0x1C0u
#define IOMUXC_PTE19_DSE_SHIFT                   6
#define IOMUXC_PTE19_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE19_DSE_SHIFT))&IOMUXC_PTE19_DSE_MASK)
#define IOMUXC_PTE19_HYS_MASK                    0x200u
#define IOMUXC_PTE19_HYS_SHIFT                   9
#define IOMUXC_PTE19_ODE_MASK                    0x400u
#define IOMUXC_PTE19_ODE_SHIFT                   10
#define IOMUXC_PTE19_SRE_MASK                    0x800u
#define IOMUXC_PTE19_SRE_SHIFT                   11
#define IOMUXC_PTE19_SPEED_MASK                  0x3000u
#define IOMUXC_PTE19_SPEED_SHIFT                 12
#define IOMUXC_PTE19_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE19_SPEED_SHIFT))&IOMUXC_PTE19_SPEED_MASK)
#define IOMUXC_PTE19_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE19_MUX_MODE_SHIFT              20
#define IOMUXC_PTE19_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE19_MUX_MODE_SHIFT))&IOMUXC_PTE19_MUX_MODE_MASK)
/* PTE20 Bit Fields */
#define IOMUXC_PTE20_IBE_MASK                    0x1u
#define IOMUXC_PTE20_IBE_SHIFT                   0
#define IOMUXC_PTE20_OBE_MASK                    0x2u
#define IOMUXC_PTE20_OBE_SHIFT                   1
#define IOMUXC_PTE20_PUE_MASK                    0x4u
#define IOMUXC_PTE20_PUE_SHIFT                   2
#define IOMUXC_PTE20_PKE_MASK                    0x8u
#define IOMUXC_PTE20_PKE_SHIFT                   3
#define IOMUXC_PTE20_PUS_MASK                    0x30u
#define IOMUXC_PTE20_PUS_SHIFT                   4
#define IOMUXC_PTE20_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE20_PUS_SHIFT))&IOMUXC_PTE20_PUS_MASK)
#define IOMUXC_PTE20_DSE_MASK                    0x1C0u
#define IOMUXC_PTE20_DSE_SHIFT                   6
#define IOMUXC_PTE20_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE20_DSE_SHIFT))&IOMUXC_PTE20_DSE_MASK)
#define IOMUXC_PTE20_HYS_MASK                    0x200u
#define IOMUXC_PTE20_HYS_SHIFT                   9
#define IOMUXC_PTE20_ODE_MASK                    0x400u
#define IOMUXC_PTE20_ODE_SHIFT                   10
#define IOMUXC_PTE20_SRE_MASK                    0x800u
#define IOMUXC_PTE20_SRE_SHIFT                   11
#define IOMUXC_PTE20_SPEED_MASK                  0x3000u
#define IOMUXC_PTE20_SPEED_SHIFT                 12
#define IOMUXC_PTE20_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE20_SPEED_SHIFT))&IOMUXC_PTE20_SPEED_MASK)
#define IOMUXC_PTE20_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE20_MUX_MODE_SHIFT              20
#define IOMUXC_PTE20_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE20_MUX_MODE_SHIFT))&IOMUXC_PTE20_MUX_MODE_MASK)
/* PTE21 Bit Fields */
#define IOMUXC_PTE21_IBE_MASK                    0x1u
#define IOMUXC_PTE21_IBE_SHIFT                   0
#define IOMUXC_PTE21_OBE_MASK                    0x2u
#define IOMUXC_PTE21_OBE_SHIFT                   1
#define IOMUXC_PTE21_PUE_MASK                    0x4u
#define IOMUXC_PTE21_PUE_SHIFT                   2
#define IOMUXC_PTE21_PKE_MASK                    0x8u
#define IOMUXC_PTE21_PKE_SHIFT                   3
#define IOMUXC_PTE21_PUS_MASK                    0x30u
#define IOMUXC_PTE21_PUS_SHIFT                   4
#define IOMUXC_PTE21_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE21_PUS_SHIFT))&IOMUXC_PTE21_PUS_MASK)
#define IOMUXC_PTE21_DSE_MASK                    0x1C0u
#define IOMUXC_PTE21_DSE_SHIFT                   6
#define IOMUXC_PTE21_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE21_DSE_SHIFT))&IOMUXC_PTE21_DSE_MASK)
#define IOMUXC_PTE21_HYS_MASK                    0x200u
#define IOMUXC_PTE21_HYS_SHIFT                   9
#define IOMUXC_PTE21_ODE_MASK                    0x400u
#define IOMUXC_PTE21_ODE_SHIFT                   10
#define IOMUXC_PTE21_SRE_MASK                    0x800u
#define IOMUXC_PTE21_SRE_SHIFT                   11
#define IOMUXC_PTE21_SPEED_MASK                  0x3000u
#define IOMUXC_PTE21_SPEED_SHIFT                 12
#define IOMUXC_PTE21_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE21_SPEED_SHIFT))&IOMUXC_PTE21_SPEED_MASK)
#define IOMUXC_PTE21_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE21_MUX_MODE_SHIFT              20
#define IOMUXC_PTE21_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE21_MUX_MODE_SHIFT))&IOMUXC_PTE21_MUX_MODE_MASK)
/* PTE22 Bit Fields */
#define IOMUXC_PTE22_IBE_MASK                    0x1u
#define IOMUXC_PTE22_IBE_SHIFT                   0
#define IOMUXC_PTE22_OBE_MASK                    0x2u
#define IOMUXC_PTE22_OBE_SHIFT                   1
#define IOMUXC_PTE22_PUE_MASK                    0x4u
#define IOMUXC_PTE22_PUE_SHIFT                   2
#define IOMUXC_PTE22_PKE_MASK                    0x8u
#define IOMUXC_PTE22_PKE_SHIFT                   3
#define IOMUXC_PTE22_PUS_MASK                    0x30u
#define IOMUXC_PTE22_PUS_SHIFT                   4
#define IOMUXC_PTE22_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE22_PUS_SHIFT))&IOMUXC_PTE22_PUS_MASK)
#define IOMUXC_PTE22_DSE_MASK                    0x1C0u
#define IOMUXC_PTE22_DSE_SHIFT                   6
#define IOMUXC_PTE22_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE22_DSE_SHIFT))&IOMUXC_PTE22_DSE_MASK)
#define IOMUXC_PTE22_HYS_MASK                    0x200u
#define IOMUXC_PTE22_HYS_SHIFT                   9
#define IOMUXC_PTE22_ODE_MASK                    0x400u
#define IOMUXC_PTE22_ODE_SHIFT                   10
#define IOMUXC_PTE22_SRE_MASK                    0x800u
#define IOMUXC_PTE22_SRE_SHIFT                   11
#define IOMUXC_PTE22_SPEED_MASK                  0x3000u
#define IOMUXC_PTE22_SPEED_SHIFT                 12
#define IOMUXC_PTE22_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE22_SPEED_SHIFT))&IOMUXC_PTE22_SPEED_MASK)
#define IOMUXC_PTE22_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE22_MUX_MODE_SHIFT              20
#define IOMUXC_PTE22_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE22_MUX_MODE_SHIFT))&IOMUXC_PTE22_MUX_MODE_MASK)
/* PTE23 Bit Fields */
#define IOMUXC_PTE23_IBE_MASK                    0x1u
#define IOMUXC_PTE23_IBE_SHIFT                   0
#define IOMUXC_PTE23_OBE_MASK                    0x2u
#define IOMUXC_PTE23_OBE_SHIFT                   1
#define IOMUXC_PTE23_PUE_MASK                    0x4u
#define IOMUXC_PTE23_PUE_SHIFT                   2
#define IOMUXC_PTE23_PKE_MASK                    0x8u
#define IOMUXC_PTE23_PKE_SHIFT                   3
#define IOMUXC_PTE23_PUS_MASK                    0x30u
#define IOMUXC_PTE23_PUS_SHIFT                   4
#define IOMUXC_PTE23_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE23_PUS_SHIFT))&IOMUXC_PTE23_PUS_MASK)
#define IOMUXC_PTE23_DSE_MASK                    0x1C0u
#define IOMUXC_PTE23_DSE_SHIFT                   6
#define IOMUXC_PTE23_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE23_DSE_SHIFT))&IOMUXC_PTE23_DSE_MASK)
#define IOMUXC_PTE23_HYS_MASK                    0x200u
#define IOMUXC_PTE23_HYS_SHIFT                   9
#define IOMUXC_PTE23_ODE_MASK                    0x400u
#define IOMUXC_PTE23_ODE_SHIFT                   10
#define IOMUXC_PTE23_SRE_MASK                    0x800u
#define IOMUXC_PTE23_SRE_SHIFT                   11
#define IOMUXC_PTE23_SPEED_MASK                  0x3000u
#define IOMUXC_PTE23_SPEED_SHIFT                 12
#define IOMUXC_PTE23_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE23_SPEED_SHIFT))&IOMUXC_PTE23_SPEED_MASK)
#define IOMUXC_PTE23_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE23_MUX_MODE_SHIFT              20
#define IOMUXC_PTE23_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE23_MUX_MODE_SHIFT))&IOMUXC_PTE23_MUX_MODE_MASK)
/* PTE24 Bit Fields */
#define IOMUXC_PTE24_IBE_MASK                    0x1u
#define IOMUXC_PTE24_IBE_SHIFT                   0
#define IOMUXC_PTE24_OBE_MASK                    0x2u
#define IOMUXC_PTE24_OBE_SHIFT                   1
#define IOMUXC_PTE24_PUE_MASK                    0x4u
#define IOMUXC_PTE24_PUE_SHIFT                   2
#define IOMUXC_PTE24_PKE_MASK                    0x8u
#define IOMUXC_PTE24_PKE_SHIFT                   3
#define IOMUXC_PTE24_PUS_MASK                    0x30u
#define IOMUXC_PTE24_PUS_SHIFT                   4
#define IOMUXC_PTE24_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE24_PUS_SHIFT))&IOMUXC_PTE24_PUS_MASK)
#define IOMUXC_PTE24_DSE_MASK                    0x1C0u
#define IOMUXC_PTE24_DSE_SHIFT                   6
#define IOMUXC_PTE24_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE24_DSE_SHIFT))&IOMUXC_PTE24_DSE_MASK)
#define IOMUXC_PTE24_HYS_MASK                    0x200u
#define IOMUXC_PTE24_HYS_SHIFT                   9
#define IOMUXC_PTE24_ODE_MASK                    0x400u
#define IOMUXC_PTE24_ODE_SHIFT                   10
#define IOMUXC_PTE24_SRE_MASK                    0x800u
#define IOMUXC_PTE24_SRE_SHIFT                   11
#define IOMUXC_PTE24_SPEED_MASK                  0x3000u
#define IOMUXC_PTE24_SPEED_SHIFT                 12
#define IOMUXC_PTE24_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE24_SPEED_SHIFT))&IOMUXC_PTE24_SPEED_MASK)
#define IOMUXC_PTE24_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE24_MUX_MODE_SHIFT              20
#define IOMUXC_PTE24_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE24_MUX_MODE_SHIFT))&IOMUXC_PTE24_MUX_MODE_MASK)
/* PTE25 Bit Fields */
#define IOMUXC_PTE25_IBE_MASK                    0x1u
#define IOMUXC_PTE25_IBE_SHIFT                   0
#define IOMUXC_PTE25_OBE_MASK                    0x2u
#define IOMUXC_PTE25_OBE_SHIFT                   1
#define IOMUXC_PTE25_PUE_MASK                    0x4u
#define IOMUXC_PTE25_PUE_SHIFT                   2
#define IOMUXC_PTE25_PKE_MASK                    0x8u
#define IOMUXC_PTE25_PKE_SHIFT                   3
#define IOMUXC_PTE25_PUS_MASK                    0x30u
#define IOMUXC_PTE25_PUS_SHIFT                   4
#define IOMUXC_PTE25_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE25_PUS_SHIFT))&IOMUXC_PTE25_PUS_MASK)
#define IOMUXC_PTE25_DSE_MASK                    0x1C0u
#define IOMUXC_PTE25_DSE_SHIFT                   6
#define IOMUXC_PTE25_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE25_DSE_SHIFT))&IOMUXC_PTE25_DSE_MASK)
#define IOMUXC_PTE25_HYS_MASK                    0x200u
#define IOMUXC_PTE25_HYS_SHIFT                   9
#define IOMUXC_PTE25_ODE_MASK                    0x400u
#define IOMUXC_PTE25_ODE_SHIFT                   10
#define IOMUXC_PTE25_SRE_MASK                    0x800u
#define IOMUXC_PTE25_SRE_SHIFT                   11
#define IOMUXC_PTE25_SPEED_MASK                  0x3000u
#define IOMUXC_PTE25_SPEED_SHIFT                 12
#define IOMUXC_PTE25_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE25_SPEED_SHIFT))&IOMUXC_PTE25_SPEED_MASK)
#define IOMUXC_PTE25_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE25_MUX_MODE_SHIFT              20
#define IOMUXC_PTE25_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE25_MUX_MODE_SHIFT))&IOMUXC_PTE25_MUX_MODE_MASK)
/* PTE26 Bit Fields */
#define IOMUXC_PTE26_IBE_MASK                    0x1u
#define IOMUXC_PTE26_IBE_SHIFT                   0
#define IOMUXC_PTE26_OBE_MASK                    0x2u
#define IOMUXC_PTE26_OBE_SHIFT                   1
#define IOMUXC_PTE26_PUE_MASK                    0x4u
#define IOMUXC_PTE26_PUE_SHIFT                   2
#define IOMUXC_PTE26_PKE_MASK                    0x8u
#define IOMUXC_PTE26_PKE_SHIFT                   3
#define IOMUXC_PTE26_PUS_MASK                    0x30u
#define IOMUXC_PTE26_PUS_SHIFT                   4
#define IOMUXC_PTE26_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE26_PUS_SHIFT))&IOMUXC_PTE26_PUS_MASK)
#define IOMUXC_PTE26_DSE_MASK                    0x1C0u
#define IOMUXC_PTE26_DSE_SHIFT                   6
#define IOMUXC_PTE26_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE26_DSE_SHIFT))&IOMUXC_PTE26_DSE_MASK)
#define IOMUXC_PTE26_HYS_MASK                    0x200u
#define IOMUXC_PTE26_HYS_SHIFT                   9
#define IOMUXC_PTE26_ODE_MASK                    0x400u
#define IOMUXC_PTE26_ODE_SHIFT                   10
#define IOMUXC_PTE26_SRE_MASK                    0x800u
#define IOMUXC_PTE26_SRE_SHIFT                   11
#define IOMUXC_PTE26_SPEED_MASK                  0x3000u
#define IOMUXC_PTE26_SPEED_SHIFT                 12
#define IOMUXC_PTE26_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE26_SPEED_SHIFT))&IOMUXC_PTE26_SPEED_MASK)
#define IOMUXC_PTE26_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE26_MUX_MODE_SHIFT              20
#define IOMUXC_PTE26_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE26_MUX_MODE_SHIFT))&IOMUXC_PTE26_MUX_MODE_MASK)
/* PTE27 Bit Fields */
#define IOMUXC_PTE27_IBE_MASK                    0x1u
#define IOMUXC_PTE27_IBE_SHIFT                   0
#define IOMUXC_PTE27_OBE_MASK                    0x2u
#define IOMUXC_PTE27_OBE_SHIFT                   1
#define IOMUXC_PTE27_PUE_MASK                    0x4u
#define IOMUXC_PTE27_PUE_SHIFT                   2
#define IOMUXC_PTE27_PKE_MASK                    0x8u
#define IOMUXC_PTE27_PKE_SHIFT                   3
#define IOMUXC_PTE27_PUS_MASK                    0x30u
#define IOMUXC_PTE27_PUS_SHIFT                   4
#define IOMUXC_PTE27_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE27_PUS_SHIFT))&IOMUXC_PTE27_PUS_MASK)
#define IOMUXC_PTE27_DSE_MASK                    0x1C0u
#define IOMUXC_PTE27_DSE_SHIFT                   6
#define IOMUXC_PTE27_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE27_DSE_SHIFT))&IOMUXC_PTE27_DSE_MASK)
#define IOMUXC_PTE27_HYS_MASK                    0x200u
#define IOMUXC_PTE27_HYS_SHIFT                   9
#define IOMUXC_PTE27_ODE_MASK                    0x400u
#define IOMUXC_PTE27_ODE_SHIFT                   10
#define IOMUXC_PTE27_SRE_MASK                    0x800u
#define IOMUXC_PTE27_SRE_SHIFT                   11
#define IOMUXC_PTE27_SPEED_MASK                  0x3000u
#define IOMUXC_PTE27_SPEED_SHIFT                 12
#define IOMUXC_PTE27_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE27_SPEED_SHIFT))&IOMUXC_PTE27_SPEED_MASK)
#define IOMUXC_PTE27_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE27_MUX_MODE_SHIFT              20
#define IOMUXC_PTE27_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE27_MUX_MODE_SHIFT))&IOMUXC_PTE27_MUX_MODE_MASK)
/* PTE28 Bit Fields */
#define IOMUXC_PTE28_IBE_MASK                    0x1u
#define IOMUXC_PTE28_IBE_SHIFT                   0
#define IOMUXC_PTE28_OBE_MASK                    0x2u
#define IOMUXC_PTE28_OBE_SHIFT                   1
#define IOMUXC_PTE28_PUE_MASK                    0x4u
#define IOMUXC_PTE28_PUE_SHIFT                   2
#define IOMUXC_PTE28_PKE_MASK                    0x8u
#define IOMUXC_PTE28_PKE_SHIFT                   3
#define IOMUXC_PTE28_PUS_MASK                    0x30u
#define IOMUXC_PTE28_PUS_SHIFT                   4
#define IOMUXC_PTE28_PUS(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE28_PUS_SHIFT))&IOMUXC_PTE28_PUS_MASK)
#define IOMUXC_PTE28_DSE_MASK                    0x1C0u
#define IOMUXC_PTE28_DSE_SHIFT                   6
#define IOMUXC_PTE28_DSE(x)                      (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE28_DSE_SHIFT))&IOMUXC_PTE28_DSE_MASK)
#define IOMUXC_PTE28_HYS_MASK                    0x200u
#define IOMUXC_PTE28_HYS_SHIFT                   9
#define IOMUXC_PTE28_ODE_MASK                    0x400u
#define IOMUXC_PTE28_ODE_SHIFT                   10
#define IOMUXC_PTE28_SRE_MASK                    0x800u
#define IOMUXC_PTE28_SRE_SHIFT                   11
#define IOMUXC_PTE28_SPEED_MASK                  0x3000u
#define IOMUXC_PTE28_SPEED_SHIFT                 12
#define IOMUXC_PTE28_SPEED(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE28_SPEED_SHIFT))&IOMUXC_PTE28_SPEED_MASK)
#define IOMUXC_PTE28_MUX_MODE_MASK               0x700000u
#define IOMUXC_PTE28_MUX_MODE_SHIFT              20
#define IOMUXC_PTE28_MUX_MODE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTE28_MUX_MODE_SHIFT))&IOMUXC_PTE28_MUX_MODE_MASK)
/* PTA7 Bit Fields */
#define IOMUXC_PTA7_IBE_MASK                     0x1u
#define IOMUXC_PTA7_IBE_SHIFT                    0
#define IOMUXC_PTA7_OBE_MASK                     0x2u
#define IOMUXC_PTA7_OBE_SHIFT                    1
#define IOMUXC_PTA7_PUE_MASK                     0x4u
#define IOMUXC_PTA7_PUE_SHIFT                    2
#define IOMUXC_PTA7_PKE_MASK                     0x8u
#define IOMUXC_PTA7_PKE_SHIFT                    3
#define IOMUXC_PTA7_PUS_MASK                     0x30u
#define IOMUXC_PTA7_PUS_SHIFT                    4
#define IOMUXC_PTA7_PUS(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA7_PUS_SHIFT))&IOMUXC_PTA7_PUS_MASK)
#define IOMUXC_PTA7_DSE_MASK                     0x1C0u
#define IOMUXC_PTA7_DSE_SHIFT                    6
#define IOMUXC_PTA7_DSE(x)                       (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA7_DSE_SHIFT))&IOMUXC_PTA7_DSE_MASK)
#define IOMUXC_PTA7_HYS_MASK                     0x200u
#define IOMUXC_PTA7_HYS_SHIFT                    9
#define IOMUXC_PTA7_ODE_MASK                     0x400u
#define IOMUXC_PTA7_ODE_SHIFT                    10
#define IOMUXC_PTA7_SRE_MASK                     0x800u
#define IOMUXC_PTA7_SRE_SHIFT                    11
#define IOMUXC_PTA7_SPEED_MASK                   0x3000u
#define IOMUXC_PTA7_SPEED_SHIFT                  12
#define IOMUXC_PTA7_SPEED(x)                     (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA7_SPEED_SHIFT))&IOMUXC_PTA7_SPEED_MASK)
#define IOMUXC_PTA7_MUX_MODE_MASK                0x700000u
#define IOMUXC_PTA7_MUX_MODE_SHIFT               20
#define IOMUXC_PTA7_MUX_MODE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_PTA7_MUX_MODE_SHIFT))&IOMUXC_PTA7_MUX_MODE_MASK)
/* DDR_RESETB Bit Fields */
#define IOMUXC_DDR_RESETB_PUE_MASK               0x4u
#define IOMUXC_DDR_RESETB_PUE_SHIFT              2
#define IOMUXC_DDR_RESETB_PKE_MASK               0x8u
#define IOMUXC_DDR_RESETB_PKE_SHIFT              3
#define IOMUXC_DDR_RESETB_PUS_MASK               0x30u
#define IOMUXC_DDR_RESETB_PUS_SHIFT              4
#define IOMUXC_DDR_RESETB_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_RESETB_PUS_SHIFT))&IOMUXC_DDR_RESETB_PUS_MASK)
#define IOMUXC_DDR_RESETB_DSE_MASK               0x1C0u
#define IOMUXC_DDR_RESETB_DSE_SHIFT              6
#define IOMUXC_DDR_RESETB_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_RESETB_DSE_SHIFT))&IOMUXC_DDR_RESETB_DSE_MASK)
#define IOMUXC_DDR_RESETB_HYS_MASK               0x200u
#define IOMUXC_DDR_RESETB_HYS_SHIFT              9
#define IOMUXC_DDR_RESETB_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_RESETB_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_RESETB_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_RESETB_DDR_TRIM_SHIFT))&IOMUXC_DDR_RESETB_DDR_TRIM_MASK)
#define IOMUXC_DDR_RESETB_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_RESETB_DDR_INPUT_SHIFT        16
/* DDR_A_15 Bit Fields */
#define IOMUXC_DDR_A_15_PUE_MASK                 0x4u
#define IOMUXC_DDR_A_15_PUE_SHIFT                2
#define IOMUXC_DDR_A_15_PKE_MASK                 0x8u
#define IOMUXC_DDR_A_15_PKE_SHIFT                3
#define IOMUXC_DDR_A_15_PUS_MASK                 0x30u
#define IOMUXC_DDR_A_15_PUS_SHIFT                4
#define IOMUXC_DDR_A_15_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_15_PUS_SHIFT))&IOMUXC_DDR_A_15_PUS_MASK)
#define IOMUXC_DDR_A_15_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_A_15_DSE_SHIFT                6
#define IOMUXC_DDR_A_15_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_15_DSE_SHIFT))&IOMUXC_DDR_A_15_DSE_MASK)
#define IOMUXC_DDR_A_15_HYS_MASK                 0x200u
#define IOMUXC_DDR_A_15_HYS_SHIFT                9
#define IOMUXC_DDR_A_15_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_A_15_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_A_15_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_15_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_15_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_15_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_A_15_DDR_INPUT_SHIFT          16
/* DDR_A_14 Bit Fields */
#define IOMUXC_DDR_A_14_PUE_MASK                 0x4u
#define IOMUXC_DDR_A_14_PUE_SHIFT                2
#define IOMUXC_DDR_A_14_PKE_MASK                 0x8u
#define IOMUXC_DDR_A_14_PKE_SHIFT                3
#define IOMUXC_DDR_A_14_PUS_MASK                 0x30u
#define IOMUXC_DDR_A_14_PUS_SHIFT                4
#define IOMUXC_DDR_A_14_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_14_PUS_SHIFT))&IOMUXC_DDR_A_14_PUS_MASK)
#define IOMUXC_DDR_A_14_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_A_14_DSE_SHIFT                6
#define IOMUXC_DDR_A_14_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_14_DSE_SHIFT))&IOMUXC_DDR_A_14_DSE_MASK)
#define IOMUXC_DDR_A_14_HYS_MASK                 0x200u
#define IOMUXC_DDR_A_14_HYS_SHIFT                9
#define IOMUXC_DDR_A_14_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_A_14_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_A_14_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_14_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_14_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_14_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_A_14_DDR_INPUT_SHIFT          16
/* DDR_A_13 Bit Fields */
#define IOMUXC_DDR_A_13_PUE_MASK                 0x4u
#define IOMUXC_DDR_A_13_PUE_SHIFT                2
#define IOMUXC_DDR_A_13_PKE_MASK                 0x8u
#define IOMUXC_DDR_A_13_PKE_SHIFT                3
#define IOMUXC_DDR_A_13_PUS_MASK                 0x30u
#define IOMUXC_DDR_A_13_PUS_SHIFT                4
#define IOMUXC_DDR_A_13_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_13_PUS_SHIFT))&IOMUXC_DDR_A_13_PUS_MASK)
#define IOMUXC_DDR_A_13_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_A_13_DSE_SHIFT                6
#define IOMUXC_DDR_A_13_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_13_DSE_SHIFT))&IOMUXC_DDR_A_13_DSE_MASK)
#define IOMUXC_DDR_A_13_HYS_MASK                 0x200u
#define IOMUXC_DDR_A_13_HYS_SHIFT                9
#define IOMUXC_DDR_A_13_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_A_13_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_A_13_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_13_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_13_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_13_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_A_13_DDR_INPUT_SHIFT          16
/* DDR_A_12 Bit Fields */
#define IOMUXC_DDR_A_12_PUE_MASK                 0x4u
#define IOMUXC_DDR_A_12_PUE_SHIFT                2
#define IOMUXC_DDR_A_12_PKE_MASK                 0x8u
#define IOMUXC_DDR_A_12_PKE_SHIFT                3
#define IOMUXC_DDR_A_12_PUS_MASK                 0x30u
#define IOMUXC_DDR_A_12_PUS_SHIFT                4
#define IOMUXC_DDR_A_12_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_12_PUS_SHIFT))&IOMUXC_DDR_A_12_PUS_MASK)
#define IOMUXC_DDR_A_12_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_A_12_DSE_SHIFT                6
#define IOMUXC_DDR_A_12_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_12_DSE_SHIFT))&IOMUXC_DDR_A_12_DSE_MASK)
#define IOMUXC_DDR_A_12_HYS_MASK                 0x200u
#define IOMUXC_DDR_A_12_HYS_SHIFT                9
#define IOMUXC_DDR_A_12_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_A_12_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_A_12_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_12_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_12_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_12_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_A_12_DDR_INPUT_SHIFT          16
/* DDR_A_11 Bit Fields */
#define IOMUXC_DDR_A_11_PUE_MASK                 0x4u
#define IOMUXC_DDR_A_11_PUE_SHIFT                2
#define IOMUXC_DDR_A_11_PKE_MASK                 0x8u
#define IOMUXC_DDR_A_11_PKE_SHIFT                3
#define IOMUXC_DDR_A_11_PUS_MASK                 0x30u
#define IOMUXC_DDR_A_11_PUS_SHIFT                4
#define IOMUXC_DDR_A_11_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_11_PUS_SHIFT))&IOMUXC_DDR_A_11_PUS_MASK)
#define IOMUXC_DDR_A_11_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_A_11_DSE_SHIFT                6
#define IOMUXC_DDR_A_11_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_11_DSE_SHIFT))&IOMUXC_DDR_A_11_DSE_MASK)
#define IOMUXC_DDR_A_11_HYS_MASK                 0x200u
#define IOMUXC_DDR_A_11_HYS_SHIFT                9
#define IOMUXC_DDR_A_11_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_A_11_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_A_11_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_11_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_11_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_11_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_A_11_DDR_INPUT_SHIFT          16
/* DDR_A_10 Bit Fields */
#define IOMUXC_DDR_A_10_PUE_MASK                 0x4u
#define IOMUXC_DDR_A_10_PUE_SHIFT                2
#define IOMUXC_DDR_A_10_PKE_MASK                 0x8u
#define IOMUXC_DDR_A_10_PKE_SHIFT                3
#define IOMUXC_DDR_A_10_PUS_MASK                 0x30u
#define IOMUXC_DDR_A_10_PUS_SHIFT                4
#define IOMUXC_DDR_A_10_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_10_PUS_SHIFT))&IOMUXC_DDR_A_10_PUS_MASK)
#define IOMUXC_DDR_A_10_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_A_10_DSE_SHIFT                6
#define IOMUXC_DDR_A_10_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_10_DSE_SHIFT))&IOMUXC_DDR_A_10_DSE_MASK)
#define IOMUXC_DDR_A_10_HYS_MASK                 0x200u
#define IOMUXC_DDR_A_10_HYS_SHIFT                9
#define IOMUXC_DDR_A_10_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_A_10_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_A_10_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_10_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_10_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_10_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_A_10_DDR_INPUT_SHIFT          16
/* DDR_A_9 Bit Fields */
#define IOMUXC_DDR_A_9_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_9_PUE_SHIFT                 2
#define IOMUXC_DDR_A_9_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_9_PKE_SHIFT                 3
#define IOMUXC_DDR_A_9_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_9_PUS_SHIFT                 4
#define IOMUXC_DDR_A_9_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_9_PUS_SHIFT))&IOMUXC_DDR_A_9_PUS_MASK)
#define IOMUXC_DDR_A_9_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_9_DSE_SHIFT                 6
#define IOMUXC_DDR_A_9_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_9_DSE_SHIFT))&IOMUXC_DDR_A_9_DSE_MASK)
#define IOMUXC_DDR_A_9_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_9_HYS_SHIFT                 9
#define IOMUXC_DDR_A_9_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_9_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_9_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_9_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_9_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_9_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_9_DDR_INPUT_SHIFT           16
/* DDR_A_8 Bit Fields */
#define IOMUXC_DDR_A_8_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_8_PUE_SHIFT                 2
#define IOMUXC_DDR_A_8_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_8_PKE_SHIFT                 3
#define IOMUXC_DDR_A_8_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_8_PUS_SHIFT                 4
#define IOMUXC_DDR_A_8_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_8_PUS_SHIFT))&IOMUXC_DDR_A_8_PUS_MASK)
#define IOMUXC_DDR_A_8_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_8_DSE_SHIFT                 6
#define IOMUXC_DDR_A_8_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_8_DSE_SHIFT))&IOMUXC_DDR_A_8_DSE_MASK)
#define IOMUXC_DDR_A_8_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_8_HYS_SHIFT                 9
#define IOMUXC_DDR_A_8_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_8_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_8_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_8_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_8_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_8_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_8_DDR_INPUT_SHIFT           16
/* DDR_A_7 Bit Fields */
#define IOMUXC_DDR_A_7_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_7_PUE_SHIFT                 2
#define IOMUXC_DDR_A_7_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_7_PKE_SHIFT                 3
#define IOMUXC_DDR_A_7_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_7_PUS_SHIFT                 4
#define IOMUXC_DDR_A_7_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_7_PUS_SHIFT))&IOMUXC_DDR_A_7_PUS_MASK)
#define IOMUXC_DDR_A_7_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_7_DSE_SHIFT                 6
#define IOMUXC_DDR_A_7_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_7_DSE_SHIFT))&IOMUXC_DDR_A_7_DSE_MASK)
#define IOMUXC_DDR_A_7_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_7_HYS_SHIFT                 9
#define IOMUXC_DDR_A_7_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_7_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_7_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_7_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_7_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_7_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_7_DDR_INPUT_SHIFT           16
/* DDR_A_6 Bit Fields */
#define IOMUXC_DDR_A_6_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_6_PUE_SHIFT                 2
#define IOMUXC_DDR_A_6_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_6_PKE_SHIFT                 3
#define IOMUXC_DDR_A_6_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_6_PUS_SHIFT                 4
#define IOMUXC_DDR_A_6_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_6_PUS_SHIFT))&IOMUXC_DDR_A_6_PUS_MASK)
#define IOMUXC_DDR_A_6_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_6_DSE_SHIFT                 6
#define IOMUXC_DDR_A_6_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_6_DSE_SHIFT))&IOMUXC_DDR_A_6_DSE_MASK)
#define IOMUXC_DDR_A_6_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_6_HYS_SHIFT                 9
#define IOMUXC_DDR_A_6_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_6_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_6_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_6_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_6_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_6_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_6_DDR_INPUT_SHIFT           16
/* DDR_A_5 Bit Fields */
#define IOMUXC_DDR_A_5_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_5_PUE_SHIFT                 2
#define IOMUXC_DDR_A_5_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_5_PKE_SHIFT                 3
#define IOMUXC_DDR_A_5_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_5_PUS_SHIFT                 4
#define IOMUXC_DDR_A_5_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_5_PUS_SHIFT))&IOMUXC_DDR_A_5_PUS_MASK)
#define IOMUXC_DDR_A_5_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_5_DSE_SHIFT                 6
#define IOMUXC_DDR_A_5_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_5_DSE_SHIFT))&IOMUXC_DDR_A_5_DSE_MASK)
#define IOMUXC_DDR_A_5_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_5_HYS_SHIFT                 9
#define IOMUXC_DDR_A_5_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_5_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_5_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_5_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_5_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_5_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_5_DDR_INPUT_SHIFT           16
/* DDR_A_4 Bit Fields */
#define IOMUXC_DDR_A_4_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_4_PUE_SHIFT                 2
#define IOMUXC_DDR_A_4_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_4_PKE_SHIFT                 3
#define IOMUXC_DDR_A_4_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_4_PUS_SHIFT                 4
#define IOMUXC_DDR_A_4_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_4_PUS_SHIFT))&IOMUXC_DDR_A_4_PUS_MASK)
#define IOMUXC_DDR_A_4_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_4_DSE_SHIFT                 6
#define IOMUXC_DDR_A_4_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_4_DSE_SHIFT))&IOMUXC_DDR_A_4_DSE_MASK)
#define IOMUXC_DDR_A_4_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_4_HYS_SHIFT                 9
#define IOMUXC_DDR_A_4_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_4_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_4_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_4_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_4_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_4_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_4_DDR_INPUT_SHIFT           16
/* DDR_A_3 Bit Fields */
#define IOMUXC_DDR_A_3_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_3_PUE_SHIFT                 2
#define IOMUXC_DDR_A_3_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_3_PKE_SHIFT                 3
#define IOMUXC_DDR_A_3_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_3_PUS_SHIFT                 4
#define IOMUXC_DDR_A_3_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_3_PUS_SHIFT))&IOMUXC_DDR_A_3_PUS_MASK)
#define IOMUXC_DDR_A_3_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_3_DSE_SHIFT                 6
#define IOMUXC_DDR_A_3_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_3_DSE_SHIFT))&IOMUXC_DDR_A_3_DSE_MASK)
#define IOMUXC_DDR_A_3_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_3_HYS_SHIFT                 9
#define IOMUXC_DDR_A_3_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_3_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_3_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_3_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_3_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_3_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_3_DDR_INPUT_SHIFT           16
/* DDR_A_2 Bit Fields */
#define IOMUXC_DDR_A_2_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_2_PUE_SHIFT                 2
#define IOMUXC_DDR_A_2_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_2_PKE_SHIFT                 3
#define IOMUXC_DDR_A_2_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_2_PUS_SHIFT                 4
#define IOMUXC_DDR_A_2_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_2_PUS_SHIFT))&IOMUXC_DDR_A_2_PUS_MASK)
#define IOMUXC_DDR_A_2_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_2_DSE_SHIFT                 6
#define IOMUXC_DDR_A_2_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_2_DSE_SHIFT))&IOMUXC_DDR_A_2_DSE_MASK)
#define IOMUXC_DDR_A_2_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_2_HYS_SHIFT                 9
#define IOMUXC_DDR_A_2_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_2_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_2_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_2_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_2_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_2_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_2_DDR_INPUT_SHIFT           16
/* DDR_A_1 Bit Fields */
#define IOMUXC_DDR_A_1_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_1_PUE_SHIFT                 2
#define IOMUXC_DDR_A_1_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_1_PKE_SHIFT                 3
#define IOMUXC_DDR_A_1_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_1_PUS_SHIFT                 4
#define IOMUXC_DDR_A_1_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_1_PUS_SHIFT))&IOMUXC_DDR_A_1_PUS_MASK)
#define IOMUXC_DDR_A_1_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_1_DSE_SHIFT                 6
#define IOMUXC_DDR_A_1_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_1_DSE_SHIFT))&IOMUXC_DDR_A_1_DSE_MASK)
#define IOMUXC_DDR_A_1_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_1_HYS_SHIFT                 9
#define IOMUXC_DDR_A_1_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_1_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_1_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_1_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_1_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_1_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_1_DDR_INPUT_SHIFT           16
/* DDR_A_0 Bit Fields */
#define IOMUXC_DDR_A_0_PUE_MASK                  0x4u
#define IOMUXC_DDR_A_0_PUE_SHIFT                 2
#define IOMUXC_DDR_A_0_PKE_MASK                  0x8u
#define IOMUXC_DDR_A_0_PKE_SHIFT                 3
#define IOMUXC_DDR_A_0_PUS_MASK                  0x30u
#define IOMUXC_DDR_A_0_PUS_SHIFT                 4
#define IOMUXC_DDR_A_0_PUS(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_0_PUS_SHIFT))&IOMUXC_DDR_A_0_PUS_MASK)
#define IOMUXC_DDR_A_0_DSE_MASK                  0x1C0u
#define IOMUXC_DDR_A_0_DSE_SHIFT                 6
#define IOMUXC_DDR_A_0_DSE(x)                    (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_0_DSE_SHIFT))&IOMUXC_DDR_A_0_DSE_MASK)
#define IOMUXC_DDR_A_0_HYS_MASK                  0x200u
#define IOMUXC_DDR_A_0_HYS_SHIFT                 9
#define IOMUXC_DDR_A_0_DDR_TRIM_MASK             0xC000u
#define IOMUXC_DDR_A_0_DDR_TRIM_SHIFT            14
#define IOMUXC_DDR_A_0_DDR_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_A_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_A_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_A_0_DDR_INPUT_MASK            0x10000u
#define IOMUXC_DDR_A_0_DDR_INPUT_SHIFT           16
/* DDR_BA_2 Bit Fields */
#define IOMUXC_DDR_BA_2_PUE_MASK                 0x4u
#define IOMUXC_DDR_BA_2_PUE_SHIFT                2
#define IOMUXC_DDR_BA_2_PKE_MASK                 0x8u
#define IOMUXC_DDR_BA_2_PKE_SHIFT                3
#define IOMUXC_DDR_BA_2_PUS_MASK                 0x30u
#define IOMUXC_DDR_BA_2_PUS_SHIFT                4
#define IOMUXC_DDR_BA_2_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_2_PUS_SHIFT))&IOMUXC_DDR_BA_2_PUS_MASK)
#define IOMUXC_DDR_BA_2_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_BA_2_DSE_SHIFT                6
#define IOMUXC_DDR_BA_2_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_2_DSE_SHIFT))&IOMUXC_DDR_BA_2_DSE_MASK)
#define IOMUXC_DDR_BA_2_HYS_MASK                 0x200u
#define IOMUXC_DDR_BA_2_HYS_SHIFT                9
#define IOMUXC_DDR_BA_2_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_BA_2_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_BA_2_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_2_DDR_TRIM_SHIFT))&IOMUXC_DDR_BA_2_DDR_TRIM_MASK)
#define IOMUXC_DDR_BA_2_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_BA_2_DDR_INPUT_SHIFT          16
/* DDR_BA_1 Bit Fields */
#define IOMUXC_DDR_BA_1_PUE_MASK                 0x4u
#define IOMUXC_DDR_BA_1_PUE_SHIFT                2
#define IOMUXC_DDR_BA_1_PKE_MASK                 0x8u
#define IOMUXC_DDR_BA_1_PKE_SHIFT                3
#define IOMUXC_DDR_BA_1_PUS_MASK                 0x30u
#define IOMUXC_DDR_BA_1_PUS_SHIFT                4
#define IOMUXC_DDR_BA_1_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_1_PUS_SHIFT))&IOMUXC_DDR_BA_1_PUS_MASK)
#define IOMUXC_DDR_BA_1_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_BA_1_DSE_SHIFT                6
#define IOMUXC_DDR_BA_1_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_1_DSE_SHIFT))&IOMUXC_DDR_BA_1_DSE_MASK)
#define IOMUXC_DDR_BA_1_HYS_MASK                 0x200u
#define IOMUXC_DDR_BA_1_HYS_SHIFT                9
#define IOMUXC_DDR_BA_1_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_BA_1_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_BA_1_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_1_DDR_TRIM_SHIFT))&IOMUXC_DDR_BA_1_DDR_TRIM_MASK)
#define IOMUXC_DDR_BA_1_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_BA_1_DDR_INPUT_SHIFT          16
/* DDR_BA_0 Bit Fields */
#define IOMUXC_DDR_BA_0_PUE_MASK                 0x4u
#define IOMUXC_DDR_BA_0_PUE_SHIFT                2
#define IOMUXC_DDR_BA_0_PKE_MASK                 0x8u
#define IOMUXC_DDR_BA_0_PKE_SHIFT                3
#define IOMUXC_DDR_BA_0_PUS_MASK                 0x30u
#define IOMUXC_DDR_BA_0_PUS_SHIFT                4
#define IOMUXC_DDR_BA_0_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_0_PUS_SHIFT))&IOMUXC_DDR_BA_0_PUS_MASK)
#define IOMUXC_DDR_BA_0_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_BA_0_DSE_SHIFT                6
#define IOMUXC_DDR_BA_0_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_0_DSE_SHIFT))&IOMUXC_DDR_BA_0_DSE_MASK)
#define IOMUXC_DDR_BA_0_HYS_MASK                 0x200u
#define IOMUXC_DDR_BA_0_HYS_SHIFT                9
#define IOMUXC_DDR_BA_0_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_BA_0_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_BA_0_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_BA_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_BA_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_BA_0_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_BA_0_DDR_INPUT_SHIFT          16
/* DDR_CAS_B Bit Fields */
#define IOMUXC_DDR_CAS_B_PUE_MASK                0x4u
#define IOMUXC_DDR_CAS_B_PUE_SHIFT               2
#define IOMUXC_DDR_CAS_B_PKE_MASK                0x8u
#define IOMUXC_DDR_CAS_B_PKE_SHIFT               3
#define IOMUXC_DDR_CAS_B_PUS_MASK                0x30u
#define IOMUXC_DDR_CAS_B_PUS_SHIFT               4
#define IOMUXC_DDR_CAS_B_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CAS_B_PUS_SHIFT))&IOMUXC_DDR_CAS_B_PUS_MASK)
#define IOMUXC_DDR_CAS_B_DSE_MASK                0x1C0u
#define IOMUXC_DDR_CAS_B_DSE_SHIFT               6
#define IOMUXC_DDR_CAS_B_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CAS_B_DSE_SHIFT))&IOMUXC_DDR_CAS_B_DSE_MASK)
#define IOMUXC_DDR_CAS_B_HYS_MASK                0x200u
#define IOMUXC_DDR_CAS_B_HYS_SHIFT               9
#define IOMUXC_DDR_CAS_B_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_CAS_B_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_CAS_B_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CAS_B_DDR_TRIM_SHIFT))&IOMUXC_DDR_CAS_B_DDR_TRIM_MASK)
#define IOMUXC_DDR_CAS_B_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_CAS_B_DDR_INPUT_SHIFT         16
/* DDR_CKE_0 Bit Fields */
#define IOMUXC_DDR_CKE_0_PUE_MASK                0x4u
#define IOMUXC_DDR_CKE_0_PUE_SHIFT               2
#define IOMUXC_DDR_CKE_0_PKE_MASK                0x8u
#define IOMUXC_DDR_CKE_0_PKE_SHIFT               3
#define IOMUXC_DDR_CKE_0_PUS_MASK                0x30u
#define IOMUXC_DDR_CKE_0_PUS_SHIFT               4
#define IOMUXC_DDR_CKE_0_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CKE_0_PUS_SHIFT))&IOMUXC_DDR_CKE_0_PUS_MASK)
#define IOMUXC_DDR_CKE_0_DSE_MASK                0x1C0u
#define IOMUXC_DDR_CKE_0_DSE_SHIFT               6
#define IOMUXC_DDR_CKE_0_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CKE_0_DSE_SHIFT))&IOMUXC_DDR_CKE_0_DSE_MASK)
#define IOMUXC_DDR_CKE_0_HYS_MASK                0x200u
#define IOMUXC_DDR_CKE_0_HYS_SHIFT               9
#define IOMUXC_DDR_CKE_0_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_CKE_0_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_CKE_0_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CKE_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_CKE_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_CKE_0_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_CKE_0_DDR_INPUT_SHIFT         16
/* DDR_CLK_0 Bit Fields */
#define IOMUXC_DDR_CLK_0_PUE_MASK                0x4u
#define IOMUXC_DDR_CLK_0_PUE_SHIFT               2
#define IOMUXC_DDR_CLK_0_PKE_MASK                0x8u
#define IOMUXC_DDR_CLK_0_PKE_SHIFT               3
#define IOMUXC_DDR_CLK_0_PUS_MASK                0x30u
#define IOMUXC_DDR_CLK_0_PUS_SHIFT               4
#define IOMUXC_DDR_CLK_0_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CLK_0_PUS_SHIFT))&IOMUXC_DDR_CLK_0_PUS_MASK)
#define IOMUXC_DDR_CLK_0_DSE_MASK                0x1C0u
#define IOMUXC_DDR_CLK_0_DSE_SHIFT               6
#define IOMUXC_DDR_CLK_0_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CLK_0_DSE_SHIFT))&IOMUXC_DDR_CLK_0_DSE_MASK)
#define IOMUXC_DDR_CLK_0_HYS_MASK                0x200u
#define IOMUXC_DDR_CLK_0_HYS_SHIFT               9
#define IOMUXC_DDR_CLK_0_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_CLK_0_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_CLK_0_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CLK_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_CLK_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_CLK_0_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_CLK_0_DDR_INPUT_SHIFT         16
/* DDR_CS_B_0 Bit Fields */
#define IOMUXC_DDR_CS_B_0_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_B_0_PUE_SHIFT              2
#define IOMUXC_DDR_CS_B_0_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_B_0_PKE_SHIFT              3
#define IOMUXC_DDR_CS_B_0_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_B_0_PUS_SHIFT              4
#define IOMUXC_DDR_CS_B_0_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_B_0_PUS_SHIFT))&IOMUXC_DDR_CS_B_0_PUS_MASK)
#define IOMUXC_DDR_CS_B_0_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_B_0_DSE_SHIFT              6
#define IOMUXC_DDR_CS_B_0_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_B_0_DSE_SHIFT))&IOMUXC_DDR_CS_B_0_DSE_MASK)
#define IOMUXC_DDR_CS_B_0_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_B_0_HYS_SHIFT              9
#define IOMUXC_DDR_CS_B_0_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_B_0_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_B_0_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_B_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_B_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_B_0_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_B_0_DDR_INPUT_SHIFT        16
/* DDR_CS_D_15 Bit Fields */
#define IOMUXC_DDR_CS_D_15_PUE_MASK              0x4u
#define IOMUXC_DDR_CS_D_15_PUE_SHIFT             2
#define IOMUXC_DDR_CS_D_15_PKE_MASK              0x8u
#define IOMUXC_DDR_CS_D_15_PKE_SHIFT             3
#define IOMUXC_DDR_CS_D_15_PUS_MASK              0x30u
#define IOMUXC_DDR_CS_D_15_PUS_SHIFT             4
#define IOMUXC_DDR_CS_D_15_PUS(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_15_PUS_SHIFT))&IOMUXC_DDR_CS_D_15_PUS_MASK)
#define IOMUXC_DDR_CS_D_15_DSE_MASK              0x1C0u
#define IOMUXC_DDR_CS_D_15_DSE_SHIFT             6
#define IOMUXC_DDR_CS_D_15_DSE(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_15_DSE_SHIFT))&IOMUXC_DDR_CS_D_15_DSE_MASK)
#define IOMUXC_DDR_CS_D_15_HYS_MASK              0x200u
#define IOMUXC_DDR_CS_D_15_HYS_SHIFT             9
#define IOMUXC_DDR_CS_D_15_DDR_TRIM_MASK         0xC000u
#define IOMUXC_DDR_CS_D_15_DDR_TRIM_SHIFT        14
#define IOMUXC_DDR_CS_D_15_DDR_TRIM(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_15_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_15_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_15_DDR_INPUT_MASK        0x10000u
#define IOMUXC_DDR_CS_D_15_DDR_INPUT_SHIFT       16
/* DDR_CS_D_14 Bit Fields */
#define IOMUXC_DDR_CS_D_14_PUE_MASK              0x4u
#define IOMUXC_DDR_CS_D_14_PUE_SHIFT             2
#define IOMUXC_DDR_CS_D_14_PKE_MASK              0x8u
#define IOMUXC_DDR_CS_D_14_PKE_SHIFT             3
#define IOMUXC_DDR_CS_D_14_PUS_MASK              0x30u
#define IOMUXC_DDR_CS_D_14_PUS_SHIFT             4
#define IOMUXC_DDR_CS_D_14_PUS(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_14_PUS_SHIFT))&IOMUXC_DDR_CS_D_14_PUS_MASK)
#define IOMUXC_DDR_CS_D_14_DSE_MASK              0x1C0u
#define IOMUXC_DDR_CS_D_14_DSE_SHIFT             6
#define IOMUXC_DDR_CS_D_14_DSE(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_14_DSE_SHIFT))&IOMUXC_DDR_CS_D_14_DSE_MASK)
#define IOMUXC_DDR_CS_D_14_HYS_MASK              0x200u
#define IOMUXC_DDR_CS_D_14_HYS_SHIFT             9
#define IOMUXC_DDR_CS_D_14_DDR_TRIM_MASK         0xC000u
#define IOMUXC_DDR_CS_D_14_DDR_TRIM_SHIFT        14
#define IOMUXC_DDR_CS_D_14_DDR_TRIM(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_14_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_14_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_14_DDR_INPUT_MASK        0x10000u
#define IOMUXC_DDR_CS_D_14_DDR_INPUT_SHIFT       16
/* DDR_CS_D_13 Bit Fields */
#define IOMUXC_DDR_CS_D_13_PUE_MASK              0x4u
#define IOMUXC_DDR_CS_D_13_PUE_SHIFT             2
#define IOMUXC_DDR_CS_D_13_PKE_MASK              0x8u
#define IOMUXC_DDR_CS_D_13_PKE_SHIFT             3
#define IOMUXC_DDR_CS_D_13_PUS_MASK              0x30u
#define IOMUXC_DDR_CS_D_13_PUS_SHIFT             4
#define IOMUXC_DDR_CS_D_13_PUS(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_13_PUS_SHIFT))&IOMUXC_DDR_CS_D_13_PUS_MASK)
#define IOMUXC_DDR_CS_D_13_DSE_MASK              0x1C0u
#define IOMUXC_DDR_CS_D_13_DSE_SHIFT             6
#define IOMUXC_DDR_CS_D_13_DSE(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_13_DSE_SHIFT))&IOMUXC_DDR_CS_D_13_DSE_MASK)
#define IOMUXC_DDR_CS_D_13_HYS_MASK              0x200u
#define IOMUXC_DDR_CS_D_13_HYS_SHIFT             9
#define IOMUXC_DDR_CS_D_13_DDR_TRIM_MASK         0xC000u
#define IOMUXC_DDR_CS_D_13_DDR_TRIM_SHIFT        14
#define IOMUXC_DDR_CS_D_13_DDR_TRIM(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_13_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_13_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_13_DDR_INPUT_MASK        0x10000u
#define IOMUXC_DDR_CS_D_13_DDR_INPUT_SHIFT       16
/* DDR_CS_D_12 Bit Fields */
#define IOMUXC_DDR_CS_D_12_PUE_MASK              0x4u
#define IOMUXC_DDR_CS_D_12_PUE_SHIFT             2
#define IOMUXC_DDR_CS_D_12_PKE_MASK              0x8u
#define IOMUXC_DDR_CS_D_12_PKE_SHIFT             3
#define IOMUXC_DDR_CS_D_12_PUS_MASK              0x30u
#define IOMUXC_DDR_CS_D_12_PUS_SHIFT             4
#define IOMUXC_DDR_CS_D_12_PUS(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_12_PUS_SHIFT))&IOMUXC_DDR_CS_D_12_PUS_MASK)
#define IOMUXC_DDR_CS_D_12_DSE_MASK              0x1C0u
#define IOMUXC_DDR_CS_D_12_DSE_SHIFT             6
#define IOMUXC_DDR_CS_D_12_DSE(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_12_DSE_SHIFT))&IOMUXC_DDR_CS_D_12_DSE_MASK)
#define IOMUXC_DDR_CS_D_12_HYS_MASK              0x200u
#define IOMUXC_DDR_CS_D_12_HYS_SHIFT             9
#define IOMUXC_DDR_CS_D_12_DDR_TRIM_MASK         0xC000u
#define IOMUXC_DDR_CS_D_12_DDR_TRIM_SHIFT        14
#define IOMUXC_DDR_CS_D_12_DDR_TRIM(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_12_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_12_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_12_DDR_INPUT_MASK        0x10000u
#define IOMUXC_DDR_CS_D_12_DDR_INPUT_SHIFT       16
/* DDR_CS_D_11 Bit Fields */
#define IOMUXC_DDR_CS_D_11_PUE_MASK              0x4u
#define IOMUXC_DDR_CS_D_11_PUE_SHIFT             2
#define IOMUXC_DDR_CS_D_11_PKE_MASK              0x8u
#define IOMUXC_DDR_CS_D_11_PKE_SHIFT             3
#define IOMUXC_DDR_CS_D_11_PUS_MASK              0x30u
#define IOMUXC_DDR_CS_D_11_PUS_SHIFT             4
#define IOMUXC_DDR_CS_D_11_PUS(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_11_PUS_SHIFT))&IOMUXC_DDR_CS_D_11_PUS_MASK)
#define IOMUXC_DDR_CS_D_11_DSE_MASK              0x1C0u
#define IOMUXC_DDR_CS_D_11_DSE_SHIFT             6
#define IOMUXC_DDR_CS_D_11_DSE(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_11_DSE_SHIFT))&IOMUXC_DDR_CS_D_11_DSE_MASK)
#define IOMUXC_DDR_CS_D_11_HYS_MASK              0x200u
#define IOMUXC_DDR_CS_D_11_HYS_SHIFT             9
#define IOMUXC_DDR_CS_D_11_DDR_TRIM_MASK         0xC000u
#define IOMUXC_DDR_CS_D_11_DDR_TRIM_SHIFT        14
#define IOMUXC_DDR_CS_D_11_DDR_TRIM(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_11_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_11_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_11_DDR_INPUT_MASK        0x10000u
#define IOMUXC_DDR_CS_D_11_DDR_INPUT_SHIFT       16
/* DDR_CS_D_10 Bit Fields */
#define IOMUXC_DDR_CS_D_10_PUE_MASK              0x4u
#define IOMUXC_DDR_CS_D_10_PUE_SHIFT             2
#define IOMUXC_DDR_CS_D_10_PKE_MASK              0x8u
#define IOMUXC_DDR_CS_D_10_PKE_SHIFT             3
#define IOMUXC_DDR_CS_D_10_PUS_MASK              0x30u
#define IOMUXC_DDR_CS_D_10_PUS_SHIFT             4
#define IOMUXC_DDR_CS_D_10_PUS(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_10_PUS_SHIFT))&IOMUXC_DDR_CS_D_10_PUS_MASK)
#define IOMUXC_DDR_CS_D_10_DSE_MASK              0x1C0u
#define IOMUXC_DDR_CS_D_10_DSE_SHIFT             6
#define IOMUXC_DDR_CS_D_10_DSE(x)                (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_10_DSE_SHIFT))&IOMUXC_DDR_CS_D_10_DSE_MASK)
#define IOMUXC_DDR_CS_D_10_HYS_MASK              0x200u
#define IOMUXC_DDR_CS_D_10_HYS_SHIFT             9
#define IOMUXC_DDR_CS_D_10_DDR_TRIM_MASK         0xC000u
#define IOMUXC_DDR_CS_D_10_DDR_TRIM_SHIFT        14
#define IOMUXC_DDR_CS_D_10_DDR_TRIM(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_10_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_10_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_10_DDR_INPUT_MASK        0x10000u
#define IOMUXC_DDR_CS_D_10_DDR_INPUT_SHIFT       16
/* DDR_CS_D_9 Bit Fields */
#define IOMUXC_DDR_CS_D_9_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_9_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_9_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_9_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_9_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_9_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_9_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_9_PUS_SHIFT))&IOMUXC_DDR_CS_D_9_PUS_MASK)
#define IOMUXC_DDR_CS_D_9_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_9_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_9_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_9_DSE_SHIFT))&IOMUXC_DDR_CS_D_9_DSE_MASK)
#define IOMUXC_DDR_CS_D_9_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_9_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_9_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_9_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_9_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_9_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_9_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_9_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_9_DDR_INPUT_SHIFT        16
/* DDR_CS_D_8 Bit Fields */
#define IOMUXC_DDR_CS_D_8_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_8_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_8_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_8_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_8_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_8_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_8_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_8_PUS_SHIFT))&IOMUXC_DDR_CS_D_8_PUS_MASK)
#define IOMUXC_DDR_CS_D_8_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_8_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_8_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_8_DSE_SHIFT))&IOMUXC_DDR_CS_D_8_DSE_MASK)
#define IOMUXC_DDR_CS_D_8_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_8_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_8_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_8_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_8_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_8_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_8_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_8_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_8_DDR_INPUT_SHIFT        16
/* DDR_CS_D_7 Bit Fields */
#define IOMUXC_DDR_CS_D_7_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_7_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_7_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_7_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_7_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_7_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_7_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_7_PUS_SHIFT))&IOMUXC_DDR_CS_D_7_PUS_MASK)
#define IOMUXC_DDR_CS_D_7_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_7_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_7_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_7_DSE_SHIFT))&IOMUXC_DDR_CS_D_7_DSE_MASK)
#define IOMUXC_DDR_CS_D_7_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_7_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_7_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_7_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_7_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_7_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_7_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_7_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_7_DDR_INPUT_SHIFT        16
/* DDR_CS_D_6 Bit Fields */
#define IOMUXC_DDR_CS_D_6_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_6_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_6_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_6_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_6_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_6_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_6_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_6_PUS_SHIFT))&IOMUXC_DDR_CS_D_6_PUS_MASK)
#define IOMUXC_DDR_CS_D_6_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_6_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_6_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_6_DSE_SHIFT))&IOMUXC_DDR_CS_D_6_DSE_MASK)
#define IOMUXC_DDR_CS_D_6_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_6_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_6_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_6_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_6_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_6_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_6_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_6_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_6_DDR_INPUT_SHIFT        16
/* DDR_CS_D_5 Bit Fields */
#define IOMUXC_DDR_CS_D_5_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_5_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_5_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_5_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_5_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_5_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_5_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_5_PUS_SHIFT))&IOMUXC_DDR_CS_D_5_PUS_MASK)
#define IOMUXC_DDR_CS_D_5_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_5_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_5_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_5_DSE_SHIFT))&IOMUXC_DDR_CS_D_5_DSE_MASK)
#define IOMUXC_DDR_CS_D_5_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_5_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_5_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_5_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_5_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_5_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_5_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_5_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_5_DDR_INPUT_SHIFT        16
/* DDR_CS_D_4 Bit Fields */
#define IOMUXC_DDR_CS_D_4_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_4_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_4_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_4_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_4_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_4_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_4_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_4_PUS_SHIFT))&IOMUXC_DDR_CS_D_4_PUS_MASK)
#define IOMUXC_DDR_CS_D_4_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_4_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_4_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_4_DSE_SHIFT))&IOMUXC_DDR_CS_D_4_DSE_MASK)
#define IOMUXC_DDR_CS_D_4_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_4_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_4_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_4_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_4_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_4_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_4_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_4_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_4_DDR_INPUT_SHIFT        16
/* DDR_CS_D_3 Bit Fields */
#define IOMUXC_DDR_CS_D_3_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_3_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_3_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_3_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_3_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_3_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_3_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_3_PUS_SHIFT))&IOMUXC_DDR_CS_D_3_PUS_MASK)
#define IOMUXC_DDR_CS_D_3_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_3_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_3_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_3_DSE_SHIFT))&IOMUXC_DDR_CS_D_3_DSE_MASK)
#define IOMUXC_DDR_CS_D_3_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_3_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_3_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_3_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_3_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_3_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_3_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_3_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_3_DDR_INPUT_SHIFT        16
/* DDR_CS_D_2 Bit Fields */
#define IOMUXC_DDR_CS_D_2_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_2_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_2_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_2_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_2_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_2_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_2_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_2_PUS_SHIFT))&IOMUXC_DDR_CS_D_2_PUS_MASK)
#define IOMUXC_DDR_CS_D_2_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_2_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_2_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_2_DSE_SHIFT))&IOMUXC_DDR_CS_D_2_DSE_MASK)
#define IOMUXC_DDR_CS_D_2_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_2_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_2_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_2_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_2_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_2_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_2_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_2_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_2_DDR_INPUT_SHIFT        16
/* DDR_CS_D_1 Bit Fields */
#define IOMUXC_DDR_CS_D_1_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_1_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_1_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_1_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_1_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_1_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_1_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_1_PUS_SHIFT))&IOMUXC_DDR_CS_D_1_PUS_MASK)
#define IOMUXC_DDR_CS_D_1_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_1_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_1_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_1_DSE_SHIFT))&IOMUXC_DDR_CS_D_1_DSE_MASK)
#define IOMUXC_DDR_CS_D_1_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_1_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_1_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_1_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_1_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_1_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_1_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_1_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_1_DDR_INPUT_SHIFT        16
/* DDR_CS_D_0 Bit Fields */
#define IOMUXC_DDR_CS_D_0_PUE_MASK               0x4u
#define IOMUXC_DDR_CS_D_0_PUE_SHIFT              2
#define IOMUXC_DDR_CS_D_0_PKE_MASK               0x8u
#define IOMUXC_DDR_CS_D_0_PKE_SHIFT              3
#define IOMUXC_DDR_CS_D_0_PUS_MASK               0x30u
#define IOMUXC_DDR_CS_D_0_PUS_SHIFT              4
#define IOMUXC_DDR_CS_D_0_PUS(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_0_PUS_SHIFT))&IOMUXC_DDR_CS_D_0_PUS_MASK)
#define IOMUXC_DDR_CS_D_0_DSE_MASK               0x1C0u
#define IOMUXC_DDR_CS_D_0_DSE_SHIFT              6
#define IOMUXC_DDR_CS_D_0_DSE(x)                 (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_0_DSE_SHIFT))&IOMUXC_DDR_CS_D_0_DSE_MASK)
#define IOMUXC_DDR_CS_D_0_HYS_MASK               0x200u
#define IOMUXC_DDR_CS_D_0_HYS_SHIFT              9
#define IOMUXC_DDR_CS_D_0_DDR_TRIM_MASK          0xC000u
#define IOMUXC_DDR_CS_D_0_DDR_TRIM_SHIFT         14
#define IOMUXC_DDR_CS_D_0_DDR_TRIM(x)            (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_CS_D_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_CS_D_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_CS_D_0_DDR_INPUT_MASK         0x10000u
#define IOMUXC_DDR_CS_D_0_DDR_INPUT_SHIFT        16
/* DDR_DQM_1 Bit Fields */
#define IOMUXC_DDR_DQM_1_PUE_MASK                0x4u
#define IOMUXC_DDR_DQM_1_PUE_SHIFT               2
#define IOMUXC_DDR_DQM_1_PKE_MASK                0x8u
#define IOMUXC_DDR_DQM_1_PKE_SHIFT               3
#define IOMUXC_DDR_DQM_1_PUS_MASK                0x30u
#define IOMUXC_DDR_DQM_1_PUS_SHIFT               4
#define IOMUXC_DDR_DQM_1_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQM_1_PUS_SHIFT))&IOMUXC_DDR_DQM_1_PUS_MASK)
#define IOMUXC_DDR_DQM_1_DSE_MASK                0x1C0u
#define IOMUXC_DDR_DQM_1_DSE_SHIFT               6
#define IOMUXC_DDR_DQM_1_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQM_1_DSE_SHIFT))&IOMUXC_DDR_DQM_1_DSE_MASK)
#define IOMUXC_DDR_DQM_1_HYS_MASK                0x200u
#define IOMUXC_DDR_DQM_1_HYS_SHIFT               9
#define IOMUXC_DDR_DQM_1_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_DQM_1_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_DQM_1_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQM_1_DDR_TRIM_SHIFT))&IOMUXC_DDR_DQM_1_DDR_TRIM_MASK)
#define IOMUXC_DDR_DQM_1_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_DQM_1_DDR_INPUT_SHIFT         16
/* DDR_DQM_0 Bit Fields */
#define IOMUXC_DDR_DQM_0_PUE_MASK                0x4u
#define IOMUXC_DDR_DQM_0_PUE_SHIFT               2
#define IOMUXC_DDR_DQM_0_PKE_MASK                0x8u
#define IOMUXC_DDR_DQM_0_PKE_SHIFT               3
#define IOMUXC_DDR_DQM_0_PUS_MASK                0x30u
#define IOMUXC_DDR_DQM_0_PUS_SHIFT               4
#define IOMUXC_DDR_DQM_0_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQM_0_PUS_SHIFT))&IOMUXC_DDR_DQM_0_PUS_MASK)
#define IOMUXC_DDR_DQM_0_DSE_MASK                0x1C0u
#define IOMUXC_DDR_DQM_0_DSE_SHIFT               6
#define IOMUXC_DDR_DQM_0_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQM_0_DSE_SHIFT))&IOMUXC_DDR_DQM_0_DSE_MASK)
#define IOMUXC_DDR_DQM_0_HYS_MASK                0x200u
#define IOMUXC_DDR_DQM_0_HYS_SHIFT               9
#define IOMUXC_DDR_DQM_0_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_DQM_0_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_DQM_0_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQM_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_DQM_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_DQM_0_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_DQM_0_DDR_INPUT_SHIFT         16
/* DDR_DQS_1 Bit Fields */
#define IOMUXC_DDR_DQS_1_PUE_MASK                0x4u
#define IOMUXC_DDR_DQS_1_PUE_SHIFT               2
#define IOMUXC_DDR_DQS_1_PKE_MASK                0x8u
#define IOMUXC_DDR_DQS_1_PKE_SHIFT               3
#define IOMUXC_DDR_DQS_1_PUS_MASK                0x30u
#define IOMUXC_DDR_DQS_1_PUS_SHIFT               4
#define IOMUXC_DDR_DQS_1_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQS_1_PUS_SHIFT))&IOMUXC_DDR_DQS_1_PUS_MASK)
#define IOMUXC_DDR_DQS_1_DSE_MASK                0x1C0u
#define IOMUXC_DDR_DQS_1_DSE_SHIFT               6
#define IOMUXC_DDR_DQS_1_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQS_1_DSE_SHIFT))&IOMUXC_DDR_DQS_1_DSE_MASK)
#define IOMUXC_DDR_DQS_1_HYS_MASK                0x200u
#define IOMUXC_DDR_DQS_1_HYS_SHIFT               9
#define IOMUXC_DDR_DQS_1_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_DQS_1_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_DQS_1_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQS_1_DDR_TRIM_SHIFT))&IOMUXC_DDR_DQS_1_DDR_TRIM_MASK)
#define IOMUXC_DDR_DQS_1_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_DQS_1_DDR_INPUT_SHIFT         16
/* DDR_DQS_0 Bit Fields */
#define IOMUXC_DDR_DQS_0_PUE_MASK                0x4u
#define IOMUXC_DDR_DQS_0_PUE_SHIFT               2
#define IOMUXC_DDR_DQS_0_PKE_MASK                0x8u
#define IOMUXC_DDR_DQS_0_PKE_SHIFT               3
#define IOMUXC_DDR_DQS_0_PUS_MASK                0x30u
#define IOMUXC_DDR_DQS_0_PUS_SHIFT               4
#define IOMUXC_DDR_DQS_0_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQS_0_PUS_SHIFT))&IOMUXC_DDR_DQS_0_PUS_MASK)
#define IOMUXC_DDR_DQS_0_DSE_MASK                0x1C0u
#define IOMUXC_DDR_DQS_0_DSE_SHIFT               6
#define IOMUXC_DDR_DQS_0_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQS_0_DSE_SHIFT))&IOMUXC_DDR_DQS_0_DSE_MASK)
#define IOMUXC_DDR_DQS_0_HYS_MASK                0x200u
#define IOMUXC_DDR_DQS_0_HYS_SHIFT               9
#define IOMUXC_DDR_DQS_0_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_DQS_0_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_DQS_0_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_DQS_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_DQS_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_DQS_0_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_DQS_0_DDR_INPUT_SHIFT         16
/* DDR_RAS_B Bit Fields */
#define IOMUXC_DDR_RAS_B_PUE_MASK                0x4u
#define IOMUXC_DDR_RAS_B_PUE_SHIFT               2
#define IOMUXC_DDR_RAS_B_PKE_MASK                0x8u
#define IOMUXC_DDR_RAS_B_PKE_SHIFT               3
#define IOMUXC_DDR_RAS_B_PUS_MASK                0x30u
#define IOMUXC_DDR_RAS_B_PUS_SHIFT               4
#define IOMUXC_DDR_RAS_B_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_RAS_B_PUS_SHIFT))&IOMUXC_DDR_RAS_B_PUS_MASK)
#define IOMUXC_DDR_RAS_B_DSE_MASK                0x1C0u
#define IOMUXC_DDR_RAS_B_DSE_SHIFT               6
#define IOMUXC_DDR_RAS_B_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_RAS_B_DSE_SHIFT))&IOMUXC_DDR_RAS_B_DSE_MASK)
#define IOMUXC_DDR_RAS_B_HYS_MASK                0x200u
#define IOMUXC_DDR_RAS_B_HYS_SHIFT               9
#define IOMUXC_DDR_RAS_B_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_RAS_B_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_RAS_B_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_RAS_B_DDR_TRIM_SHIFT))&IOMUXC_DDR_RAS_B_DDR_TRIM_MASK)
#define IOMUXC_DDR_RAS_B_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_RAS_B_DDR_INPUT_SHIFT         16
/* DDR_WE_B Bit Fields */
#define IOMUXC_DDR_WE_B_PUE_MASK                 0x4u
#define IOMUXC_DDR_WE_B_PUE_SHIFT                2
#define IOMUXC_DDR_WE_B_PKE_MASK                 0x8u
#define IOMUXC_DDR_WE_B_PKE_SHIFT                3
#define IOMUXC_DDR_WE_B_PUS_MASK                 0x30u
#define IOMUXC_DDR_WE_B_PUS_SHIFT                4
#define IOMUXC_DDR_WE_B_PUS(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_WE_B_PUS_SHIFT))&IOMUXC_DDR_WE_B_PUS_MASK)
#define IOMUXC_DDR_WE_B_DSE_MASK                 0x1C0u
#define IOMUXC_DDR_WE_B_DSE_SHIFT                6
#define IOMUXC_DDR_WE_B_DSE(x)                   (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_WE_B_DSE_SHIFT))&IOMUXC_DDR_WE_B_DSE_MASK)
#define IOMUXC_DDR_WE_B_HYS_MASK                 0x200u
#define IOMUXC_DDR_WE_B_HYS_SHIFT                9
#define IOMUXC_DDR_WE_B_DDR_TRIM_MASK            0xC000u
#define IOMUXC_DDR_WE_B_DDR_TRIM_SHIFT           14
#define IOMUXC_DDR_WE_B_DDR_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_WE_B_DDR_TRIM_SHIFT))&IOMUXC_DDR_WE_B_DDR_TRIM_MASK)
#define IOMUXC_DDR_WE_B_DDR_INPUT_MASK           0x10000u
#define IOMUXC_DDR_WE_B_DDR_INPUT_SHIFT          16
/* DDR_ODT_0 Bit Fields */
#define IOMUXC_DDR_ODT_0_PUE_MASK                0x4u
#define IOMUXC_DDR_ODT_0_PUE_SHIFT               2
#define IOMUXC_DDR_ODT_0_PKE_MASK                0x8u
#define IOMUXC_DDR_ODT_0_PKE_SHIFT               3
#define IOMUXC_DDR_ODT_0_PUS_MASK                0x30u
#define IOMUXC_DDR_ODT_0_PUS_SHIFT               4
#define IOMUXC_DDR_ODT_0_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_ODT_0_PUS_SHIFT))&IOMUXC_DDR_ODT_0_PUS_MASK)
#define IOMUXC_DDR_ODT_0_DSE_MASK                0x1C0u
#define IOMUXC_DDR_ODT_0_DSE_SHIFT               6
#define IOMUXC_DDR_ODT_0_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_ODT_0_DSE_SHIFT))&IOMUXC_DDR_ODT_0_DSE_MASK)
#define IOMUXC_DDR_ODT_0_HYS_MASK                0x200u
#define IOMUXC_DDR_ODT_0_HYS_SHIFT               9
#define IOMUXC_DDR_ODT_0_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_ODT_0_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_ODT_0_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_ODT_0_DDR_TRIM_SHIFT))&IOMUXC_DDR_ODT_0_DDR_TRIM_MASK)
#define IOMUXC_DDR_ODT_0_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_ODT_0_DDR_INPUT_SHIFT         16
/* DDR_ODT_1 Bit Fields */
#define IOMUXC_DDR_ODT_1_PUE_MASK                0x4u
#define IOMUXC_DDR_ODT_1_PUE_SHIFT               2
#define IOMUXC_DDR_ODT_1_PKE_MASK                0x8u
#define IOMUXC_DDR_ODT_1_PKE_SHIFT               3
#define IOMUXC_DDR_ODT_1_PUS_MASK                0x30u
#define IOMUXC_DDR_ODT_1_PUS_SHIFT               4
#define IOMUXC_DDR_ODT_1_PUS(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_ODT_1_PUS_SHIFT))&IOMUXC_DDR_ODT_1_PUS_MASK)
#define IOMUXC_DDR_ODT_1_DSE_MASK                0x1C0u
#define IOMUXC_DDR_ODT_1_DSE_SHIFT               6
#define IOMUXC_DDR_ODT_1_DSE(x)                  (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_ODT_1_DSE_SHIFT))&IOMUXC_DDR_ODT_1_DSE_MASK)
#define IOMUXC_DDR_ODT_1_HYS_MASK                0x200u
#define IOMUXC_DDR_ODT_1_HYS_SHIFT               9
#define IOMUXC_DDR_ODT_1_DDR_TRIM_MASK           0xC000u
#define IOMUXC_DDR_ODT_1_DDR_TRIM_SHIFT          14
#define IOMUXC_DDR_ODT_1_DDR_TRIM(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DDR_ODT_1_DDR_TRIM_SHIFT))&IOMUXC_DDR_ODT_1_DDR_TRIM_MASK)
#define IOMUXC_DDR_ODT_1_DDR_INPUT_MASK          0x10000u
#define IOMUXC_DDR_ODT_1_DDR_INPUT_SHIFT         16
/* DUMMY_DDRBYTE1 Bit Fields */
#define IOMUXC_DUMMY_DDRBYTE1_PUE_MASK           0x4u
#define IOMUXC_DUMMY_DDRBYTE1_PUE_SHIFT          2
#define IOMUXC_DUMMY_DDRBYTE1_PKE_MASK           0x8u
#define IOMUXC_DUMMY_DDRBYTE1_PKE_SHIFT          3
#define IOMUXC_DUMMY_DDRBYTE1_PUS_MASK           0x30u
#define IOMUXC_DUMMY_DDRBYTE1_PUS_SHIFT          4
#define IOMUXC_DUMMY_DDRBYTE1_PUS(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_DDRBYTE1_PUS_SHIFT))&IOMUXC_DUMMY_DDRBYTE1_PUS_MASK)
#define IOMUXC_DUMMY_DDRBYTE1_DSE_MASK           0x1C0u
#define IOMUXC_DUMMY_DDRBYTE1_DSE_SHIFT          6
#define IOMUXC_DUMMY_DDRBYTE1_DSE(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_DDRBYTE1_DSE_SHIFT))&IOMUXC_DUMMY_DDRBYTE1_DSE_MASK)
#define IOMUXC_DUMMY_DDRBYTE1_HYS_MASK           0x200u
#define IOMUXC_DUMMY_DDRBYTE1_HYS_SHIFT          9
#define IOMUXC_DUMMY_DDRBYTE1_DDR_TRIM_MASK      0xC000u
#define IOMUXC_DUMMY_DDRBYTE1_DDR_TRIM_SHIFT     14
#define IOMUXC_DUMMY_DDRBYTE1_DDR_TRIM(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_DDRBYTE1_DDR_TRIM_SHIFT))&IOMUXC_DUMMY_DDRBYTE1_DDR_TRIM_MASK)
#define IOMUXC_DUMMY_DDRBYTE1_DDR_INPUT_MASK     0x10000u
#define IOMUXC_DUMMY_DDRBYTE1_DDR_INPUT_SHIFT    16
/* DUMMY_DDRBYTE2 Bit Fields */
#define IOMUXC_DUMMY_DDRBYTE2_PUE_MASK           0x4u
#define IOMUXC_DUMMY_DDRBYTE2_PUE_SHIFT          2
#define IOMUXC_DUMMY_DDRBYTE2_PKE_MASK           0x8u
#define IOMUXC_DUMMY_DDRBYTE2_PKE_SHIFT          3
#define IOMUXC_DUMMY_DDRBYTE2_PUS_MASK           0x30u
#define IOMUXC_DUMMY_DDRBYTE2_PUS_SHIFT          4
#define IOMUXC_DUMMY_DDRBYTE2_PUS(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_DDRBYTE2_PUS_SHIFT))&IOMUXC_DUMMY_DDRBYTE2_PUS_MASK)
#define IOMUXC_DUMMY_DDRBYTE2_DSE_MASK           0x1C0u
#define IOMUXC_DUMMY_DDRBYTE2_DSE_SHIFT          6
#define IOMUXC_DUMMY_DDRBYTE2_DSE(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_DDRBYTE2_DSE_SHIFT))&IOMUXC_DUMMY_DDRBYTE2_DSE_MASK)
#define IOMUXC_DUMMY_DDRBYTE2_HYS_MASK           0x200u
#define IOMUXC_DUMMY_DDRBYTE2_HYS_SHIFT          9
#define IOMUXC_DUMMY_DDRBYTE2_DDR_TRIM_MASK      0xC000u
#define IOMUXC_DUMMY_DDRBYTE2_DDR_TRIM_SHIFT     14
#define IOMUXC_DUMMY_DDRBYTE2_DDR_TRIM(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_DDRBYTE2_DDR_TRIM_SHIFT))&IOMUXC_DUMMY_DDRBYTE2_DDR_TRIM_MASK)
#define IOMUXC_DUMMY_DDRBYTE2_DDR_INPUT_MASK     0x10000u
#define IOMUXC_DUMMY_DDRBYTE2_DDR_INPUT_SHIFT    16
/* DUMMY_QUADSPI0 Bit Fields */
#define IOMUXC_DUMMY_QUADSPI0_IBE_MASK           0x1u
#define IOMUXC_DUMMY_QUADSPI0_IBE_SHIFT          0
#define IOMUXC_DUMMY_QUADSPI0_OBE_MASK           0x2u
#define IOMUXC_DUMMY_QUADSPI0_OBE_SHIFT          1
#define IOMUXC_DUMMY_QUADSPI0_PUE_MASK           0x4u
#define IOMUXC_DUMMY_QUADSPI0_PUE_SHIFT          2
#define IOMUXC_DUMMY_QUADSPI0_PKE_MASK           0x8u
#define IOMUXC_DUMMY_QUADSPI0_PKE_SHIFT          3
#define IOMUXC_DUMMY_QUADSPI0_PUS_MASK           0x30u
#define IOMUXC_DUMMY_QUADSPI0_PUS_SHIFT          4
#define IOMUXC_DUMMY_QUADSPI0_PUS(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_QUADSPI0_PUS_SHIFT))&IOMUXC_DUMMY_QUADSPI0_PUS_MASK)
#define IOMUXC_DUMMY_QUADSPI0_DSE_MASK           0x1C0u
#define IOMUXC_DUMMY_QUADSPI0_DSE_SHIFT          6
#define IOMUXC_DUMMY_QUADSPI0_DSE(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_QUADSPI0_DSE_SHIFT))&IOMUXC_DUMMY_QUADSPI0_DSE_MASK)
#define IOMUXC_DUMMY_QUADSPI0_HYS_MASK           0x200u
#define IOMUXC_DUMMY_QUADSPI0_HYS_SHIFT          9
#define IOMUXC_DUMMY_QUADSPI0_ODE_MASK           0x400u
#define IOMUXC_DUMMY_QUADSPI0_ODE_SHIFT          10
#define IOMUXC_DUMMY_QUADSPI0_SRE_MASK           0x800u
#define IOMUXC_DUMMY_QUADSPI0_SRE_SHIFT          11
#define IOMUXC_DUMMY_QUADSPI0_SPEED_MASK         0x3000u
#define IOMUXC_DUMMY_QUADSPI0_SPEED_SHIFT        12
#define IOMUXC_DUMMY_QUADSPI0_SPEED(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_QUADSPI0_SPEED_SHIFT))&IOMUXC_DUMMY_QUADSPI0_SPEED_MASK)
/* DUMMY_QUADSPI1 Bit Fields */
#define IOMUXC_DUMMY_QUADSPI1_IBE_MASK           0x1u
#define IOMUXC_DUMMY_QUADSPI1_IBE_SHIFT          0
#define IOMUXC_DUMMY_QUADSPI1_OBE_MASK           0x2u
#define IOMUXC_DUMMY_QUADSPI1_OBE_SHIFT          1
#define IOMUXC_DUMMY_QUADSPI1_PUE_MASK           0x4u
#define IOMUXC_DUMMY_QUADSPI1_PUE_SHIFT          2
#define IOMUXC_DUMMY_QUADSPI1_PKE_MASK           0x8u
#define IOMUXC_DUMMY_QUADSPI1_PKE_SHIFT          3
#define IOMUXC_DUMMY_QUADSPI1_PUS_MASK           0x30u
#define IOMUXC_DUMMY_QUADSPI1_PUS_SHIFT          4
#define IOMUXC_DUMMY_QUADSPI1_PUS(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_QUADSPI1_PUS_SHIFT))&IOMUXC_DUMMY_QUADSPI1_PUS_MASK)
#define IOMUXC_DUMMY_QUADSPI1_DSE_MASK           0x1C0u
#define IOMUXC_DUMMY_QUADSPI1_DSE_SHIFT          6
#define IOMUXC_DUMMY_QUADSPI1_DSE(x)             (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_QUADSPI1_DSE_SHIFT))&IOMUXC_DUMMY_QUADSPI1_DSE_MASK)
#define IOMUXC_DUMMY_QUADSPI1_HYS_MASK           0x200u
#define IOMUXC_DUMMY_QUADSPI1_HYS_SHIFT          9
#define IOMUXC_DUMMY_QUADSPI1_ODE_MASK           0x400u
#define IOMUXC_DUMMY_QUADSPI1_ODE_SHIFT          10
#define IOMUXC_DUMMY_QUADSPI1_SRE_MASK           0x800u
#define IOMUXC_DUMMY_QUADSPI1_SRE_SHIFT          11
#define IOMUXC_DUMMY_QUADSPI1_SPEED_MASK         0x3000u
#define IOMUXC_DUMMY_QUADSPI1_SPEED_SHIFT        12
#define IOMUXC_DUMMY_QUADSPI1_SPEED(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_DUMMY_QUADSPI1_SPEED_SHIFT))&IOMUXC_DUMMY_QUADSPI1_SPEED_MASK)
/* CCM_AUD_EXT_CLK_SELECT_INPUT Bit Fields */
#define IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY_MASK)
/* CCM_ENET_EXT_CLK_SELECT_INPUT Bit Fields */
#define IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_CCM_ENET_EXT_CLK_SELECT_INPUT_DAISY_SHIFT 0
/* CCM_ENET_TS_CLK_SELECT_INPUT Bit Fields */
#define IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_CCM_ENET_TS_CLK_SELECT_INPUT_DAISY_SHIFT 0
/* DSPI1_IPP_IND_SCK_SELECT_INPUT Bit Fields */
#define IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_DSPI1_IPP_IND_SCK_SELECT_INPUT_DAISY_SHIFT 0
/* DSPI1_IPP_IND_SIN_SELECT_INPUT Bit Fields */
#define IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_DSPI1_IPP_IND_SIN_SELECT_INPUT_DAISY_SHIFT 0
/* DSPI1_IPP_IND_SS_B_SELECT_INPUT Bit Fields */
#define IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_DSPI1_IPP_IND_SS_B_SELECT_INPUT_DAISY_SHIFT 0
/* ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT Bit Fields */
#define IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_0_SELECT_INPUT_DAISY_SHIFT 0
/* ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT Bit Fields */
#define IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ENET_SWIAHB_IPP_IND_MAC0_TIMER_1_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_FST_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SCKT_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SDO0_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SDO1_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_SHIFT 0
/* ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT Bit Fields */
#define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT 0
/* FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT Bit Fields */
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_0_SELECT_INPUT_DAISY_SHIFT 0
/* FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT Bit Fields */
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_CH_1_SELECT_INPUT_DAISY_SHIFT 0
/* FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT Bit Fields */
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHA_SELECT_INPUT_DAISY_SHIFT 0
/* FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT Bit Fields */
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_FLEXTIMER1_IPP_IND_FTM_PHB_SELECT_INPUT_DAISY_SHIFT 0
/* I2C0_IPP_SCL_IND_SELECT_INPUT Bit Fields */
#define IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C0_IPP_SCL_IND_SELECT_INPUT_DAISY_MASK)
/* I2C0_IPP_SDA_IND_SELECT_INPUT Bit Fields */
#define IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C0_IPP_SDA_IND_SELECT_INPUT_DAISY_MASK)
/* I2C1_IPP_SCL_IND_SELECT_INPUT Bit Fields */
#define IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C1_IPP_SCL_IND_SELECT_INPUT_DAISY_MASK)
/* I2C1_IPP_SDA_IND_SELECT_INPUT Bit Fields */
#define IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C1_IPP_SDA_IND_SELECT_INPUT_DAISY_MASK)
/* I2C2_IPP_SCL_IND_SELECT_INPUT Bit Fields */
#define IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_I2C2_IPP_SCL_IND_SELECT_INPUT_DAISY_SHIFT 0
/* I2C2_IPP_SDA_IND_SELECT_INPUT Bit Fields */
#define IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_I2C2_IPP_SDA_IND_SELECT_INPUT_DAISY_SHIFT 0
/* MLB_TOP_MLBCLK_IN_SELECT_INPUT Bit Fields */
#define IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_MLB_TOP_MLBCLK_IN_SELECT_INPUT_DAISY_SHIFT 0
/* MLB_TOP_MLBDAT_IN_SELECT_INPUT Bit Fields */
#define IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_MLB_TOP_MLBDAT_IN_SELECT_INPUT_DAISY_SHIFT 0
/* MLB_TOP_MLBSIG_IN_SELECT_INPUT Bit Fields */
#define IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_MLB_TOP_MLBSIG_IN_SELECT_INPUT_DAISY_SHIFT 0
/* SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT Bit Fields */
#define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_SHIFT 0
/* SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT Bit Fields */
#define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_MASK)
/* SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT Bit Fields */
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI2_IPP_IND_SAI_RXDATA_0_SELECT_INPUT_DAISY_MASK)
/* SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT Bit Fields */
#define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_MASK)
/* SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT Bit Fields */
#define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_SHIFT 0
/* SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT Bit Fields */
#define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_SHIFT 0
/* SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SCI_FLX1_IPP_IND_CTS_B_SELECT_INPUT_DAISY_MASK)
/* SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SCI_FLX1_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_MASK)
/* SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SCI_FLX1_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_MASK)
/* SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SCI_FLX2_IPP_IND_CTS_B_SELECT_INPUT_DAISY_SHIFT 0
/* SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SCI_FLX2_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_MASK)
/* SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SCI_FLX2_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_MASK)
/* SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SCI_FLX3_IPP_IND_SCI_RX_SELECT_INPUT_DAISY_SHIFT 0
/* SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT Bit Fields */
#define IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SCI_FLX3_IPP_IND_SCI_TX_SELECT_INPUT_DAISY_SHIFT 0
/* SRC_IPP_BOOT_CFG_18_SELECT_INPUT Bit Fields */
#define IOMUXC_SRC_IPP_BOOT_CFG_18_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SRC_IPP_BOOT_CFG_18_SELECT_INPUT_DAISY_SHIFT 0
/* SRC_IPP_BOOT_CFG_19_SELECT_INPUT Bit Fields */
#define IOMUXC_SRC_IPP_BOOT_CFG_19_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SRC_IPP_BOOT_CFG_19_SELECT_INPUT_DAISY_SHIFT 0
/* SRC_IPP_BOOT_CFG_20_SELECT_INPUT Bit Fields */
#define IOMUXC_SRC_IPP_BOOT_CFG_20_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_SRC_IPP_BOOT_CFG_20_SELECT_INPUT_DAISY_SHIFT 0
/* VIDEO_IN0_IPP_IND_DE_SELECT_INPUT Bit Fields */
#define IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_DAISY_MASK 0x3u
#define IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_DAISY_SHIFT 0
#define IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_VIDEO_IN0_IPP_IND_DE_SELECT_INPUT_DAISY_MASK)
/* VIDEO_IN0_IPP_IND_FID_SELECT_INPUT Bit Fields */
#define IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_VIDEO_IN0_IPP_IND_FID_SELECT_INPUT_DAISY_SHIFT 0
/* VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT Bit Fields */
#define IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT_DAISY_MASK 0x1u
#define IOMUXC_VIDEO_IN0_IPP_IND_PIX_CLK_SELECT_INPUT_DAISY_SHIFT 0

/**
 * @}
 */ /* end of group IOMUXC_Register_Masks */


/* IOMUXC - Peripheral instance base addresses */
/** Peripheral IOMUXC base address */
#define IOMUXC_BASE                              (0x40048000u)
/** Peripheral IOMUXC base pointer */
#define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
/** Array initializer of IOMUXC peripheral base pointers */
#define IOMUXC_BASES                             { IOMUXC }

/**
 * @}
 */ /* end of group IOMUXC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LCD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
 * @{
 */

/** LCD - Register Layout Typedef */
typedef struct {
  __IO uint32_t LCDCR;                             /**< LCD Control Register, offset: 0x0 */
  __IO uint32_t LCDPCR;                            /**< LCD Prescaler Control Register, offset: 0x4 */
  __IO uint32_t LCDCCR;                            /**< LCD Contrast Control Register, offset: 0x8 */
       uint8_t RESERVED_0[4];
  __IO uint32_t ENFPR[2];                          /**< LCD Frontplane Enable Register 0..LCD Frontplane Enable Register 1, array offset: 0x10, array step: 0x4 */
       uint8_t RESERVED_1[8];
  __IO uint32_t Location[16];                      /**< LCDRAM, array offset: 0x20, array step: 0x4 */
} LCD_Type;

/* ----------------------------------------------------------------------------
   -- LCD Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup LCD_Register_Masks LCD Register Masks
 * @{
 */

/* LCDCR Bit Fields */
#define LCD_LCDCR_LCDBPS_MASK                    0x7u
#define LCD_LCDCR_LCDBPS_SHIFT                   0
#define LCD_LCDCR_LCDBPS(x)                      (((uint32_t)(((uint32_t)(x))<<LCD_LCDCR_LCDBPS_SHIFT))&LCD_LCDCR_LCDBPS_MASK)
#define LCD_LCDCR_LCDBPA_MASK                    0x30u
#define LCD_LCDCR_LCDBPA_SHIFT                   4
#define LCD_LCDCR_LCDBPA(x)                      (((uint32_t)(((uint32_t)(x))<<LCD_LCDCR_LCDBPA_SHIFT))&LCD_LCDCR_LCDBPA_MASK)
#define LCD_LCDCR_NOF_MASK                       0xFF00u
#define LCD_LCDCR_NOF_SHIFT                      8
#define LCD_LCDCR_NOF(x)                         (((uint32_t)(((uint32_t)(x))<<LCD_LCDCR_NOF_SHIFT))&LCD_LCDCR_NOF_MASK)
#define LCD_LCDCR_EOF_MASK                       0x10000u
#define LCD_LCDCR_EOF_SHIFT                      16
#define LCD_LCDCR_LCDINT_MASK                    0x20000u
#define LCD_LCDCR_LCDINT_SHIFT                   17
#define LCD_LCDCR_LCDOCS_MASK                    0x40000u
#define LCD_LCDCR_LCDOCS_SHIFT                   18
#define LCD_LCDCR_BSTAO_MASK                     0x80000u
#define LCD_LCDCR_BSTAO_SHIFT                    19
#define LCD_LCDCR_BSTSEL_MASK                    0x100000u
#define LCD_LCDCR_BSTSEL_SHIFT                   20
#define LCD_LCDCR_BSTEN_MASK                     0x200000u
#define LCD_LCDCR_BSTEN_SHIFT                    21
#define LCD_LCDCR_PWR_MASK                       0xC00000u
#define LCD_LCDCR_PWR_SHIFT                      22
#define LCD_LCDCR_PWR(x)                         (((uint32_t)(((uint32_t)(x))<<LCD_LCDCR_PWR_SHIFT))&LCD_LCDCR_PWR_MASK)
#define LCD_LCDCR_VLCDS_MASK                     0x1000000u
#define LCD_LCDCR_VLCDS_SHIFT                    24
#define LCD_LCDCR_BIAS_MASK                      0x2000000u
#define LCD_LCDCR_BIAS_SHIFT                     25
#define LCD_LCDCR_DUTY_MASK                      0x1C000000u
#define LCD_LCDCR_DUTY_SHIFT                     26
#define LCD_LCDCR_DUTY(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_LCDCR_DUTY_SHIFT))&LCD_LCDCR_DUTY_MASK)
#define LCD_LCDCR_LCDRCS_MASK                    0x20000000u
#define LCD_LCDCR_LCDRCS_SHIFT                   29
#define LCD_LCDCR_LCDRST_MASK                    0x40000000u
#define LCD_LCDCR_LCDRST_SHIFT                   30
#define LCD_LCDCR_LCDEN_MASK                     0x80000000u
#define LCD_LCDCR_LCDEN_SHIFT                    31
/* LCDPCR Bit Fields */
#define LCD_LCDPCR_LCLK_MASK                     0xF000000u
#define LCD_LCDPCR_LCLK_SHIFT                    24
#define LCD_LCDPCR_LCLK(x)                       (((uint32_t)(((uint32_t)(x))<<LCD_LCDPCR_LCLK_SHIFT))&LCD_LCDPCR_LCLK_MASK)
/* LCDCCR Bit Fields */
#define LCD_LCDCCR_LCC_MASK                      0x7FF0000u
#define LCD_LCDCCR_LCC_SHIFT                     16
#define LCD_LCDCCR_LCC(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_LCDCCR_LCC_SHIFT))&LCD_LCDCCR_LCC_MASK)
#define LCD_LCDCCR_CCEN_MASK                     0x80000000u
#define LCD_LCDCCR_CCEN_SHIFT                    31
/* ENFPR Bit Fields */
#define LCD_ENFPR_ENFP_MASK                      0xFFFFFFFFu
#define LCD_ENFPR_ENFP_SHIFT                     0
#define LCD_ENFPR_ENFP(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_ENFPR_ENFP_SHIFT))&LCD_ENFPR_ENFP_MASK)
/* Location Bit Fields */
#define LCD_Location_FP3_BP_MASK                 0xFFu
#define LCD_Location_FP3_BP_SHIFT                0
#define LCD_Location_FP3_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP3_BP_SHIFT))&LCD_Location_FP3_BP_MASK)
#define LCD_Location_FP63_BP_MASK                0xFFu
#define LCD_Location_FP63_BP_SHIFT               0
#define LCD_Location_FP63_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP63_BP_SHIFT))&LCD_Location_FP63_BP_MASK)
#define LCD_Location_FP59_BP_MASK                0xFFu
#define LCD_Location_FP59_BP_SHIFT               0
#define LCD_Location_FP59_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP59_BP_SHIFT))&LCD_Location_FP59_BP_MASK)
#define LCD_Location_FP55_BP_MASK                0xFFu
#define LCD_Location_FP55_BP_SHIFT               0
#define LCD_Location_FP55_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP55_BP_SHIFT))&LCD_Location_FP55_BP_MASK)
#define LCD_Location_FP7_BP_MASK                 0xFFu
#define LCD_Location_FP7_BP_SHIFT                0
#define LCD_Location_FP7_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP7_BP_SHIFT))&LCD_Location_FP7_BP_MASK)
#define LCD_Location_FP51_BP_MASK                0xFFu
#define LCD_Location_FP51_BP_SHIFT               0
#define LCD_Location_FP51_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP51_BP_SHIFT))&LCD_Location_FP51_BP_MASK)
#define LCD_Location_FP47_BP_MASK                0xFFu
#define LCD_Location_FP47_BP_SHIFT               0
#define LCD_Location_FP47_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP47_BP_SHIFT))&LCD_Location_FP47_BP_MASK)
#define LCD_Location_FP43_BP_MASK                0xFFu
#define LCD_Location_FP43_BP_SHIFT               0
#define LCD_Location_FP43_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP43_BP_SHIFT))&LCD_Location_FP43_BP_MASK)
#define LCD_Location_FP11_BP_MASK                0xFFu
#define LCD_Location_FP11_BP_SHIFT               0
#define LCD_Location_FP11_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP11_BP_SHIFT))&LCD_Location_FP11_BP_MASK)
#define LCD_Location_FP39_BP_MASK                0xFFu
#define LCD_Location_FP39_BP_SHIFT               0
#define LCD_Location_FP39_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP39_BP_SHIFT))&LCD_Location_FP39_BP_MASK)
#define LCD_Location_FP35_BP_MASK                0xFFu
#define LCD_Location_FP35_BP_SHIFT               0
#define LCD_Location_FP35_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP35_BP_SHIFT))&LCD_Location_FP35_BP_MASK)
#define LCD_Location_FP31_BP_MASK                0xFFu
#define LCD_Location_FP31_BP_SHIFT               0
#define LCD_Location_FP31_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP31_BP_SHIFT))&LCD_Location_FP31_BP_MASK)
#define LCD_Location_FP15_BP_MASK                0xFFu
#define LCD_Location_FP15_BP_SHIFT               0
#define LCD_Location_FP15_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP15_BP_SHIFT))&LCD_Location_FP15_BP_MASK)
#define LCD_Location_FP27_BP_MASK                0xFFu
#define LCD_Location_FP27_BP_SHIFT               0
#define LCD_Location_FP27_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP27_BP_SHIFT))&LCD_Location_FP27_BP_MASK)
#define LCD_Location_FP23_BP_MASK                0xFFu
#define LCD_Location_FP23_BP_SHIFT               0
#define LCD_Location_FP23_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP23_BP_SHIFT))&LCD_Location_FP23_BP_MASK)
#define LCD_Location_FP19_BP_MASK                0xFFu
#define LCD_Location_FP19_BP_SHIFT               0
#define LCD_Location_FP19_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP19_BP_SHIFT))&LCD_Location_FP19_BP_MASK)
#define LCD_Location_FP6_BP_MASK                 0xFF00u
#define LCD_Location_FP6_BP_SHIFT                8
#define LCD_Location_FP6_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP6_BP_SHIFT))&LCD_Location_FP6_BP_MASK)
#define LCD_Location_FP50_BP_MASK                0xFF00u
#define LCD_Location_FP50_BP_SHIFT               8
#define LCD_Location_FP50_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP50_BP_SHIFT))&LCD_Location_FP50_BP_MASK)
#define LCD_Location_FP46_BP_MASK                0xFF00u
#define LCD_Location_FP46_BP_SHIFT               8
#define LCD_Location_FP46_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP46_BP_SHIFT))&LCD_Location_FP46_BP_MASK)
#define LCD_Location_FP62_BP_MASK                0xFF00u
#define LCD_Location_FP62_BP_SHIFT               8
#define LCD_Location_FP62_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP62_BP_SHIFT))&LCD_Location_FP62_BP_MASK)
#define LCD_Location_FP26_BP_MASK                0xFF00u
#define LCD_Location_FP26_BP_SHIFT               8
#define LCD_Location_FP26_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP26_BP_SHIFT))&LCD_Location_FP26_BP_MASK)
#define LCD_Location_FP18_BP_MASK                0xFF00u
#define LCD_Location_FP18_BP_SHIFT               8
#define LCD_Location_FP18_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP18_BP_SHIFT))&LCD_Location_FP18_BP_MASK)
#define LCD_Location_FP42_BP_MASK                0xFF00u
#define LCD_Location_FP42_BP_SHIFT               8
#define LCD_Location_FP42_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP42_BP_SHIFT))&LCD_Location_FP42_BP_MASK)
#define LCD_Location_FP14_BP_MASK                0xFF00u
#define LCD_Location_FP14_BP_SHIFT               8
#define LCD_Location_FP14_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP14_BP_SHIFT))&LCD_Location_FP14_BP_MASK)
#define LCD_Location_FP58_BP_MASK                0xFF00u
#define LCD_Location_FP58_BP_SHIFT               8
#define LCD_Location_FP58_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP58_BP_SHIFT))&LCD_Location_FP58_BP_MASK)
#define LCD_Location_FP54_BP_MASK                0xFF00u
#define LCD_Location_FP54_BP_SHIFT               8
#define LCD_Location_FP54_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP54_BP_SHIFT))&LCD_Location_FP54_BP_MASK)
#define LCD_Location_FP38_BP_MASK                0xFF00u
#define LCD_Location_FP38_BP_SHIFT               8
#define LCD_Location_FP38_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP38_BP_SHIFT))&LCD_Location_FP38_BP_MASK)
#define LCD_Location_FP10_BP_MASK                0xFF00u
#define LCD_Location_FP10_BP_SHIFT               8
#define LCD_Location_FP10_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP10_BP_SHIFT))&LCD_Location_FP10_BP_MASK)
#define LCD_Location_FP2_BP_MASK                 0xFF00u
#define LCD_Location_FP2_BP_SHIFT                8
#define LCD_Location_FP2_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP2_BP_SHIFT))&LCD_Location_FP2_BP_MASK)
#define LCD_Location_FP30_BP_MASK                0xFF00u
#define LCD_Location_FP30_BP_SHIFT               8
#define LCD_Location_FP30_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP30_BP_SHIFT))&LCD_Location_FP30_BP_MASK)
#define LCD_Location_FP34_BP_MASK                0xFF00u
#define LCD_Location_FP34_BP_SHIFT               8
#define LCD_Location_FP34_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP34_BP_SHIFT))&LCD_Location_FP34_BP_MASK)
#define LCD_Location_FP22_BP_MASK                0xFF00u
#define LCD_Location_FP22_BP_SHIFT               8
#define LCD_Location_FP22_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP22_BP_SHIFT))&LCD_Location_FP22_BP_MASK)
#define LCD_Location_FP25_BP_MASK                0xFF0000u
#define LCD_Location_FP25_BP_SHIFT               16
#define LCD_Location_FP25_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP25_BP_SHIFT))&LCD_Location_FP25_BP_MASK)
#define LCD_Location_FP45_BP_MASK                0xFF0000u
#define LCD_Location_FP45_BP_SHIFT               16
#define LCD_Location_FP45_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP45_BP_SHIFT))&LCD_Location_FP45_BP_MASK)
#define LCD_Location_FP5_BP_MASK                 0xFF0000u
#define LCD_Location_FP5_BP_SHIFT                16
#define LCD_Location_FP5_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP5_BP_SHIFT))&LCD_Location_FP5_BP_MASK)
#define LCD_Location_FP41_BP_MASK                0xFF0000u
#define LCD_Location_FP41_BP_SHIFT               16
#define LCD_Location_FP41_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP41_BP_SHIFT))&LCD_Location_FP41_BP_MASK)
#define LCD_Location_FP17_BP_MASK                0xFF0000u
#define LCD_Location_FP17_BP_SHIFT               16
#define LCD_Location_FP17_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP17_BP_SHIFT))&LCD_Location_FP17_BP_MASK)
#define LCD_Location_FP37_BP_MASK                0xFF0000u
#define LCD_Location_FP37_BP_SHIFT               16
#define LCD_Location_FP37_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP37_BP_SHIFT))&LCD_Location_FP37_BP_MASK)
#define LCD_Location_FP21_BP_MASK                0xFF0000u
#define LCD_Location_FP21_BP_SHIFT               16
#define LCD_Location_FP21_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP21_BP_SHIFT))&LCD_Location_FP21_BP_MASK)
#define LCD_Location_FP33_BP_MASK                0xFF0000u
#define LCD_Location_FP33_BP_SHIFT               16
#define LCD_Location_FP33_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP33_BP_SHIFT))&LCD_Location_FP33_BP_MASK)
#define LCD_Location_FP49_BP_MASK                0xFF0000u
#define LCD_Location_FP49_BP_SHIFT               16
#define LCD_Location_FP49_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP49_BP_SHIFT))&LCD_Location_FP49_BP_MASK)
#define LCD_Location_FP13_BP_MASK                0xFF0000u
#define LCD_Location_FP13_BP_SHIFT               16
#define LCD_Location_FP13_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP13_BP_SHIFT))&LCD_Location_FP13_BP_MASK)
#define LCD_Location_FP53_BP_MASK                0xFF0000u
#define LCD_Location_FP53_BP_SHIFT               16
#define LCD_Location_FP53_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP53_BP_SHIFT))&LCD_Location_FP53_BP_MASK)
#define LCD_Location_FP1_BP_MASK                 0xFF0000u
#define LCD_Location_FP1_BP_SHIFT                16
#define LCD_Location_FP1_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP1_BP_SHIFT))&LCD_Location_FP1_BP_MASK)
#define LCD_Location_FP57_BP_MASK                0xFF0000u
#define LCD_Location_FP57_BP_SHIFT               16
#define LCD_Location_FP57_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP57_BP_SHIFT))&LCD_Location_FP57_BP_MASK)
#define LCD_Location_FP29_BP_MASK                0xFF0000u
#define LCD_Location_FP29_BP_SHIFT               16
#define LCD_Location_FP29_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP29_BP_SHIFT))&LCD_Location_FP29_BP_MASK)
#define LCD_Location_FP61_BP_MASK                0xFF0000u
#define LCD_Location_FP61_BP_SHIFT               16
#define LCD_Location_FP61_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP61_BP_SHIFT))&LCD_Location_FP61_BP_MASK)
#define LCD_Location_FP9_BP_MASK                 0xFF0000u
#define LCD_Location_FP9_BP_SHIFT                16
#define LCD_Location_FP9_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP9_BP_SHIFT))&LCD_Location_FP9_BP_MASK)
#define LCD_Location_FP60_BP_MASK                0xFF000000u
#define LCD_Location_FP60_BP_SHIFT               24
#define LCD_Location_FP60_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP60_BP_SHIFT))&LCD_Location_FP60_BP_MASK)
#define LCD_Location_FP56_BP_MASK                0xFF000000u
#define LCD_Location_FP56_BP_SHIFT               24
#define LCD_Location_FP56_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP56_BP_SHIFT))&LCD_Location_FP56_BP_MASK)
#define LCD_Location_FP52_BP_MASK                0xFF000000u
#define LCD_Location_FP52_BP_SHIFT               24
#define LCD_Location_FP52_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP52_BP_SHIFT))&LCD_Location_FP52_BP_MASK)
#define LCD_Location_FP0_BP_MASK                 0xFF000000u
#define LCD_Location_FP0_BP_SHIFT                24
#define LCD_Location_FP0_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP0_BP_SHIFT))&LCD_Location_FP0_BP_MASK)
#define LCD_Location_FP48_BP_MASK                0xFF000000u
#define LCD_Location_FP48_BP_SHIFT               24
#define LCD_Location_FP48_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP48_BP_SHIFT))&LCD_Location_FP48_BP_MASK)
#define LCD_Location_FP44_BP_MASK                0xFF000000u
#define LCD_Location_FP44_BP_SHIFT               24
#define LCD_Location_FP44_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP44_BP_SHIFT))&LCD_Location_FP44_BP_MASK)
#define LCD_Location_FP40_BP_MASK                0xFF000000u
#define LCD_Location_FP40_BP_SHIFT               24
#define LCD_Location_FP40_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP40_BP_SHIFT))&LCD_Location_FP40_BP_MASK)
#define LCD_Location_FP4_BP_MASK                 0xFF000000u
#define LCD_Location_FP4_BP_SHIFT                24
#define LCD_Location_FP4_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP4_BP_SHIFT))&LCD_Location_FP4_BP_MASK)
#define LCD_Location_FP36_BP_MASK                0xFF000000u
#define LCD_Location_FP36_BP_SHIFT               24
#define LCD_Location_FP36_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP36_BP_SHIFT))&LCD_Location_FP36_BP_MASK)
#define LCD_Location_FP32_BP_MASK                0xFF000000u
#define LCD_Location_FP32_BP_SHIFT               24
#define LCD_Location_FP32_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP32_BP_SHIFT))&LCD_Location_FP32_BP_MASK)
#define LCD_Location_FP28_BP_MASK                0xFF000000u
#define LCD_Location_FP28_BP_SHIFT               24
#define LCD_Location_FP28_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP28_BP_SHIFT))&LCD_Location_FP28_BP_MASK)
#define LCD_Location_FP8_BP_MASK                 0xFF000000u
#define LCD_Location_FP8_BP_SHIFT                24
#define LCD_Location_FP8_BP(x)                   (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP8_BP_SHIFT))&LCD_Location_FP8_BP_MASK)
#define LCD_Location_FP24_BP_MASK                0xFF000000u
#define LCD_Location_FP24_BP_SHIFT               24
#define LCD_Location_FP24_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP24_BP_SHIFT))&LCD_Location_FP24_BP_MASK)
#define LCD_Location_FP20_BP_MASK                0xFF000000u
#define LCD_Location_FP20_BP_SHIFT               24
#define LCD_Location_FP20_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP20_BP_SHIFT))&LCD_Location_FP20_BP_MASK)
#define LCD_Location_FP16_BP_MASK                0xFF000000u
#define LCD_Location_FP16_BP_SHIFT               24
#define LCD_Location_FP16_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP16_BP_SHIFT))&LCD_Location_FP16_BP_MASK)
#define LCD_Location_FP12_BP_MASK                0xFF000000u
#define LCD_Location_FP12_BP_SHIFT               24
#define LCD_Location_FP12_BP(x)                  (((uint32_t)(((uint32_t)(x))<<LCD_Location_FP12_BP_SHIFT))&LCD_Location_FP12_BP_MASK)

/**
 * @}
 */ /* end of group LCD_Register_Masks */


/* LCD - Peripheral instance base addresses */
/** Peripheral LCD base address */
#define LCD_BASE                                 (0x400BE000u)
/** Peripheral LCD base pointer */
#define LCD                                      ((LCD_Type *)LCD_BASE)
/** Array initializer of LCD peripheral base pointers */
#define LCD_BASES                                { LCD }

/**
 * @}
 */ /* end of group LCD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LMEM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
 * @{
 */

/** LMEM - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCCCR;                             /**< Cache control register, offset: 0x0 */
  __IO uint32_t PCCLCR;                            /**< Cache line control register, offset: 0x4 */
  __IO uint32_t PCCSAR;                            /**< Cache search address register, offset: 0x8 */
  __IO uint32_t PCCCVR;                            /**< Cache read/write value register, offset: 0xC */
       uint8_t RESERVED_0[2032];
  __IO uint32_t PSCCR;                             /**< Cache control register, offset: 0x800 */
  __IO uint32_t PSCLCR;                            /**< Cache line control register, offset: 0x804 */
  __IO uint32_t PSCSAR;                            /**< Cache search address register, offset: 0x808 */
  __IO uint32_t PSCCVR;                            /**< Cache read/write value register, offset: 0x80C */
} LMEM_Type;

/* ----------------------------------------------------------------------------
   -- LMEM Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup LMEM_Register_Masks LMEM Register Masks
 * @{
 */

/* PCCCR Bit Fields */
#define LMEM_PCCCR_ENCACHE_MASK                  0x1u
#define LMEM_PCCCR_ENCACHE_SHIFT                 0
#define LMEM_PCCCR_ENWRBUF_MASK                  0x2u
#define LMEM_PCCCR_ENWRBUF_SHIFT                 1
#define LMEM_PCCCR_INVW0_MASK                    0x1000000u
#define LMEM_PCCCR_INVW0_SHIFT                   24
#define LMEM_PCCCR_PUSHW0_MASK                   0x2000000u
#define LMEM_PCCCR_PUSHW0_SHIFT                  25
#define LMEM_PCCCR_INVW1_MASK                    0x4000000u
#define LMEM_PCCCR_INVW1_SHIFT                   26
#define LMEM_PCCCR_PUSHW1_MASK                   0x8000000u
#define LMEM_PCCCR_PUSHW1_SHIFT                  27
#define LMEM_PCCCR_GO_MASK                       0x80000000u
#define LMEM_PCCCR_GO_SHIFT                      31
/* PCCLCR Bit Fields */
#define LMEM_PCCLCR_LGO_MASK                     0x1u
#define LMEM_PCCLCR_LGO_SHIFT                    0
#define LMEM_PCCLCR_CACHEADDR_MASK               0x1FFCu
#define LMEM_PCCLCR_CACHEADDR_SHIFT              2
#define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
#define LMEM_PCCLCR_WSEL_MASK                    0x4000u
#define LMEM_PCCLCR_WSEL_SHIFT                   14
#define LMEM_PCCLCR_TDSEL_MASK                   0x10000u
#define LMEM_PCCLCR_TDSEL_SHIFT                  16
#define LMEM_PCCLCR_LCIVB_MASK                   0x100000u
#define LMEM_PCCLCR_LCIVB_SHIFT                  20
#define LMEM_PCCLCR_LCIMB_MASK                   0x200000u
#define LMEM_PCCLCR_LCIMB_SHIFT                  21
#define LMEM_PCCLCR_LCWAY_MASK                   0x400000u
#define LMEM_PCCLCR_LCWAY_SHIFT                  22
#define LMEM_PCCLCR_LCMD_MASK                    0x3000000u
#define LMEM_PCCLCR_LCMD_SHIFT                   24
#define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
#define LMEM_PCCLCR_LADSEL_MASK                  0x4000000u
#define LMEM_PCCLCR_LADSEL_SHIFT                 26
#define LMEM_PCCLCR_LACC_MASK                    0x8000000u
#define LMEM_PCCLCR_LACC_SHIFT                   27
/* PCCSAR Bit Fields */
#define LMEM_PCCSAR_LGO_MASK                     0x1u
#define LMEM_PCCSAR_LGO_SHIFT                    0
#define LMEM_PCCSAR_PHYADDR_MASK                 0xFFFFFFFCu
#define LMEM_PCCSAR_PHYADDR_SHIFT                2
#define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
/* PCCCVR Bit Fields */
#define LMEM_PCCCVR_DATA_MASK                    0xFFFFFFFFu
#define LMEM_PCCCVR_DATA_SHIFT                   0
#define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
/* PSCCR Bit Fields */
#define LMEM_PSCCR_ENCACHE_MASK                  0x1u
#define LMEM_PSCCR_ENCACHE_SHIFT                 0
#define LMEM_PSCCR_ENWRBUF_MASK                  0x2u
#define LMEM_PSCCR_ENWRBUF_SHIFT                 1
#define LMEM_PSCCR_INVW0_MASK                    0x1000000u
#define LMEM_PSCCR_INVW0_SHIFT                   24
#define LMEM_PSCCR_PUSHW0_MASK                   0x2000000u
#define LMEM_PSCCR_PUSHW0_SHIFT                  25
#define LMEM_PSCCR_INVW1_MASK                    0x4000000u
#define LMEM_PSCCR_INVW1_SHIFT                   26
#define LMEM_PSCCR_PUSHW1_MASK                   0x8000000u
#define LMEM_PSCCR_PUSHW1_SHIFT                  27
#define LMEM_PSCCR_GO_MASK                       0x80000000u
#define LMEM_PSCCR_GO_SHIFT                      31
/* PSCLCR Bit Fields */
#define LMEM_PSCLCR_LGO_MASK                     0x1u
#define LMEM_PSCLCR_LGO_SHIFT                    0
#define LMEM_PSCLCR_CACHEADDR_MASK               0x1FFCu
#define LMEM_PSCLCR_CACHEADDR_SHIFT              2
#define LMEM_PSCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_CACHEADDR_SHIFT))&LMEM_PSCLCR_CACHEADDR_MASK)
#define LMEM_PSCLCR_WSEL_MASK                    0x4000u
#define LMEM_PSCLCR_WSEL_SHIFT                   14
#define LMEM_PSCLCR_TDSEL_MASK                   0x10000u
#define LMEM_PSCLCR_TDSEL_SHIFT                  16
#define LMEM_PSCLCR_LCIVB_MASK                   0x100000u
#define LMEM_PSCLCR_LCIVB_SHIFT                  20
#define LMEM_PSCLCR_LCIMB_MASK                   0x200000u
#define LMEM_PSCLCR_LCIMB_SHIFT                  21
#define LMEM_PSCLCR_LCWAY_MASK                   0x400000u
#define LMEM_PSCLCR_LCWAY_SHIFT                  22
#define LMEM_PSCLCR_LCMD_MASK                    0x3000000u
#define LMEM_PSCLCR_LCMD_SHIFT                   24
#define LMEM_PSCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_LCMD_SHIFT))&LMEM_PSCLCR_LCMD_MASK)
#define LMEM_PSCLCR_LADSEL_MASK                  0x4000000u
#define LMEM_PSCLCR_LADSEL_SHIFT                 26
#define LMEM_PSCLCR_LACC_MASK                    0x8000000u
#define LMEM_PSCLCR_LACC_SHIFT                   27
/* PSCSAR Bit Fields */
#define LMEM_PSCSAR_LGO_MASK                     0x1u
#define LMEM_PSCSAR_LGO_SHIFT                    0
#define LMEM_PSCSAR_PHYADDR_MASK                 0xFFFFFFFCu
#define LMEM_PSCSAR_PHYADDR_SHIFT                2
#define LMEM_PSCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x))<<LMEM_PSCSAR_PHYADDR_SHIFT))&LMEM_PSCSAR_PHYADDR_MASK)
/* PSCCVR Bit Fields */
#define LMEM_PSCCVR_DATA_MASK                    0xFFFFFFFFu
#define LMEM_PSCCVR_DATA_SHIFT                   0
#define LMEM_PSCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x))<<LMEM_PSCCVR_DATA_SHIFT))&LMEM_PSCCVR_DATA_MASK)

/**
 * @}
 */ /* end of group LMEM_Register_Masks */


/* LMEM - Peripheral instance base addresses */
/** Peripheral LMEM base address */
#define LMEM_BASE                                (0xE0082000u)
/** Peripheral LMEM base pointer */
#define LMEM                                     ((LMEM_Type *)LMEM_BASE)
/** Array initializer of LMEM peripheral base pointers */
#define LMEM_BASES                               { LMEM }

/**
 * @}
 */ /* end of group LMEM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LPTMR Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
 * @{
 */

/** LPTMR - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
  __I  uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
} LPTMR_Type;

/* ----------------------------------------------------------------------------
   -- LPTMR Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
 * @{
 */

/* CSR Bit Fields */
#define LPTMR_CSR_TEN_MASK                       0x1u
#define LPTMR_CSR_TEN_SHIFT                      0
#define LPTMR_CSR_TMS_MASK                       0x2u
#define LPTMR_CSR_TMS_SHIFT                      1
#define LPTMR_CSR_TFC_MASK                       0x4u
#define LPTMR_CSR_TFC_SHIFT                      2
#define LPTMR_CSR_TPP_MASK                       0x8u
#define LPTMR_CSR_TPP_SHIFT                      3
#define LPTMR_CSR_TPS_MASK                       0x30u
#define LPTMR_CSR_TPS_SHIFT                      4
#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
#define LPTMR_CSR_TIE_MASK                       0x40u
#define LPTMR_CSR_TIE_SHIFT                      6
#define LPTMR_CSR_TCF_MASK                       0x80u
#define LPTMR_CSR_TCF_SHIFT                      7
/* PSR Bit Fields */
#define LPTMR_PSR_PCS_MASK                       0x3u
#define LPTMR_PSR_PCS_SHIFT                      0
#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
#define LPTMR_PSR_PBYP_MASK                      0x4u
#define LPTMR_PSR_PBYP_SHIFT                     2
#define LPTMR_PSR_PRESCALE_MASK                  0x78u
#define LPTMR_PSR_PRESCALE_SHIFT                 3
#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
/* CMR Bit Fields */
#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
#define LPTMR_CMR_COMPARE_SHIFT                  0
#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
/* CNR Bit Fields */
#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
#define LPTMR_CNR_COUNTER_SHIFT                  0
#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)

/**
 * @}
 */ /* end of group LPTMR_Register_Masks */


/* LPTMR - Peripheral instance base addresses */
/** Peripheral LPTMR0 base address */
#define LPTMR0_BASE                              (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
/** Array initializer of LPTMR peripheral base pointers */
#define LPTMR_BASES                              { LPTMR0 }

/**
 * @}
 */ /* end of group LPTMR_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
 * @{
 */

/** MCM - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[8];
  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
       uint8_t RESERVED_1[16];
  __I  uint32_t FATR;                              /**< Fault attributes register, offset: 0x24 */
  __I  uint32_t FDR;                               /**< Fault data register, offset: 0x28 */
} MCM_Type;

/* ----------------------------------------------------------------------------
   -- MCM Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup MCM_Register_Masks MCM Register Masks
 * @{
 */

/* PLASC Bit Fields */
#define MCM_PLASC_ASC_MASK                       0xFFu
#define MCM_PLASC_ASC_SHIFT                      0
#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
/* PLAMC Bit Fields */
#define MCM_PLAMC_AMC_MASK                       0xFFu
#define MCM_PLAMC_AMC_SHIFT                      0
#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
/* CR Bit Fields */
#define MCM_CR_DDRSIZE_MASK                      0x300000u
#define MCM_CR_DDRSIZE_SHIFT                     20
#define MCM_CR_DDRSIZE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_DDRSIZE_SHIFT))&MCM_CR_DDRSIZE_MASK)
#define MCM_CR_SRAMUAP_MASK                      0x3000000u
#define MCM_CR_SRAMUAP_SHIFT                     24
#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
#define MCM_CR_SRAMUWP_MASK                      0x4000000u
#define MCM_CR_SRAMUWP_SHIFT                     26
#define MCM_CR_SRAMLAP_MASK                      0x30000000u
#define MCM_CR_SRAMLAP_SHIFT                     28
#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
#define MCM_CR_SRAMLWP_MASK                      0x40000000u
#define MCM_CR_SRAMLWP_SHIFT                     30
/* ISCR Bit Fields */
#define MCM_ISCR_IRQ_MASK                        0x2u
#define MCM_ISCR_IRQ_SHIFT                       1
#define MCM_ISCR_NMI_MASK                        0x4u
#define MCM_ISCR_NMI_SHIFT                       2
#define MCM_ISCR_DHREQ_MASK                      0x8u
#define MCM_ISCR_DHREQ_SHIFT                     3
#define MCM_ISCR_CWBER_MASK                      0x10u
#define MCM_ISCR_CWBER_SHIFT                     4
#define MCM_ISCR_FIOC_MASK                       0x100u
#define MCM_ISCR_FIOC_SHIFT                      8
#define MCM_ISCR_FDZC_MASK                       0x200u
#define MCM_ISCR_FDZC_SHIFT                      9
#define MCM_ISCR_FOFC_MASK                       0x400u
#define MCM_ISCR_FOFC_SHIFT                      10
#define MCM_ISCR_FUFC_MASK                       0x800u
#define MCM_ISCR_FUFC_SHIFT                      11
#define MCM_ISCR_FIXC_MASK                       0x1000u
#define MCM_ISCR_FIXC_SHIFT                      12
#define MCM_ISCR_FIDC_MASK                       0x8000u
#define MCM_ISCR_FIDC_SHIFT                      15
#define MCM_ISCR_CWBEE_MASK                      0x100000u
#define MCM_ISCR_CWBEE_SHIFT                     20
#define MCM_ISCR_FIOCE_MASK                      0x1000000u
#define MCM_ISCR_FIOCE_SHIFT                     24
#define MCM_ISCR_FDZCE_MASK                      0x2000000u
#define MCM_ISCR_FDZCE_SHIFT                     25
#define MCM_ISCR_FOFCE_MASK                      0x4000000u
#define MCM_ISCR_FOFCE_SHIFT                     26
#define MCM_ISCR_FUFCE_MASK                      0x8000000u
#define MCM_ISCR_FUFCE_SHIFT                     27
#define MCM_ISCR_FIXCE_MASK                      0x10000000u
#define MCM_ISCR_FIXCE_SHIFT                     28
#define MCM_ISCR_FIDCE_MASK                      0x80000000u
#define MCM_ISCR_FIDCE_SHIFT                     31
/* FATR Bit Fields */
#define MCM_FATR_BEDA_MASK                       0x1u
#define MCM_FATR_BEDA_SHIFT                      0
#define MCM_FATR_BEMD_MASK                       0x2u
#define MCM_FATR_BEMD_SHIFT                      1
#define MCM_FATR_BESZ_MASK                       0x30u
#define MCM_FATR_BESZ_SHIFT                      4
#define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BESZ_SHIFT))&MCM_FATR_BESZ_MASK)
#define MCM_FATR_BEWT_MASK                       0x80u
#define MCM_FATR_BEWT_SHIFT                      7
#define MCM_FATR_BEMN_MASK                       0xF00u
#define MCM_FATR_BEMN_SHIFT                      8
#define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BEMN_SHIFT))&MCM_FATR_BEMN_MASK)
#define MCM_FATR_BEOVR_MASK                      0x80000000u
#define MCM_FATR_BEOVR_SHIFT                     31
/* FDR Bit Fields */
#define MCM_FDR_DATA_MASK                        0xFFFFFFFFu
#define MCM_FDR_DATA_SHIFT                       0
#define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_FDR_DATA_SHIFT))&MCM_FDR_DATA_MASK)

/**
 * @}
 */ /* end of group MCM_Register_Masks */


/* MCM - Peripheral instance base addresses */
/** Peripheral MCM base address */
#define MCM_BASE                                 (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM                                      ((MCM_Type *)MCM_BASE)
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASES                                { MCM }

/**
 * @}
 */ /* end of group MCM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MLB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup MLB_Peripheral_Access_Layer MLB Peripheral Access Layer
 * @{
 */

/** MLB - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[1677606912];
  __IO uint32_t DCCR;                              /**< Device Control Configuration Register, offset: 0x63FE4000 */
  __IO uint32_t SSCR;                              /**< System Status Configuration Register, offset: 0x63FE4004 */
  __I  uint32_t SDCR;                              /**< System Data Configuration Register, offset: 0x63FE4008 */
  __IO uint32_t SMCR;                              /**< System Mask Configuration Register, offset: 0x63FE400C */
       uint8_t RESERVED_1[12];
  __I  uint32_t VCCR;                              /**< Version Control Configuration Register, offset: 0x63FE401C */
  __I  uint32_t SBCR;                              /**< Synchronous Base Address Configuration Register, offset: 0x63FE4020 */
  __I  uint32_t ABCR;                              /**< Asynchronous Base Address Configuration Register, offset: 0x63FE4024 */
  __I  uint32_t CBCR;                              /**< Control Base Address Configuration Register, offset: 0x63FE4028 */
  __I  uint32_t IBCR;                              /**< Isochronous Base Address Configuration Register, offset: 0x63FE402C */
  __I  uint32_t CICR;                              /**< Channel Interrupt Configuration Register, offset: 0x63FE4030 */
       uint8_t RESERVED_2[12];
  __IO uint32_t CECR0;                             /**< Channel n Entry Configuration Register, offset: 0x63FE4040 */
  __IO uint32_t CSCR0;                             /**< Channel n Status Configuration Register, offset: 0x63FE4044 */
  __I  uint32_t CCBCR0;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4048 */
  __IO uint32_t CNBCR0;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE404C */
  __IO uint32_t CECR1;                             /**< Channel n Entry Configuration Register, offset: 0x63FE4050 */
  __IO uint32_t CSCR1;                             /**< Channel n Status Configuration Register, offset: 0x63FE4054 */
  __I  uint32_t CCBCR1;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4058 */
  __IO uint32_t CNBCR1;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE405C */
  __IO uint32_t CECR2;                             /**< Channel n Entry Configuration Register, offset: 0x63FE4060 */
  __IO uint32_t CSCR2;                             /**< Channel n Status Configuration Register, offset: 0x63FE4064 */
  __I  uint32_t CCBCR2;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4068 */
  __IO uint32_t CNBCR2;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE406C */
  __IO uint32_t CECR3;                             /**< Channel n Entry Configuration Register, offset: 0x63FE4070 */
  __IO uint32_t CSCR3;                             /**< Channel n Status Configuration Register, offset: 0x63FE4074 */
  __I  uint32_t CCBCR3;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4078 */
  __IO uint32_t CNBCR3;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE407C */
  __IO uint32_t CECR4;                             /**< Channel n Entry Configuration Register, offset: 0x63FE4080 */
  __IO uint32_t CSCR4;                             /**< Channel n Status Configuration Register, offset: 0x63FE4084 */
  __I  uint32_t CCBCR4;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4088 */
  __IO uint32_t CNBCR4;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE408C */
  __IO uint32_t CECR5;                             /**< Channel n Entry Configuration Register, offset: 0x63FE4090 */
  __IO uint32_t CSCR5;                             /**< Channel n Status Configuration Register, offset: 0x63FE4094 */
  __I  uint32_t CCBCR5;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4098 */
  __IO uint32_t CNBCR5;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE409C */
  __IO uint32_t CECR6;                             /**< Channel n Entry Configuration Register, offset: 0x63FE40A0 */
  __IO uint32_t CSCR6;                             /**< Channel n Status Configuration Register, offset: 0x63FE40A4 */
  __I  uint32_t CCBCR6;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE40A8 */
  __IO uint32_t CNBCR6;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE40AC */
  __IO uint32_t CECR7;                             /**< Channel n Entry Configuration Register, offset: 0x63FE40B0 */
  __IO uint32_t CSCR7;                             /**< Channel n Status Configuration Register, offset: 0x63FE40B4 */
  __I  uint32_t CCBCR7;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE40B8 */
  __IO uint32_t CNBCR7;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE40BC */
  __IO uint32_t CECR8;                             /**< Channel n Entry Configuration Register, offset: 0x63FE40C0 */
  __IO uint32_t CSCR8;                             /**< Channel n Status Configuration Register, offset: 0x63FE40C4 */
  __I  uint32_t CCBCR8;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE40C8 */
  __IO uint32_t CNBCR8;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE40CC */
  __IO uint32_t CECR9;                             /**< Channel n Entry Configuration Register, offset: 0x63FE40D0 */
  __IO uint32_t CSCR9;                             /**< Channel n Status Configuration Register, offset: 0x63FE40D4 */
  __I  uint32_t CCBCR9;                            /**< Channel n Current Buffer Configuration Register, offset: 0x63FE40D8 */
  __IO uint32_t CNBCR9;                            /**< Channel n Next Buffer Configuration Register, offset: 0x63FE40DC */
  __IO uint32_t CECR10;                            /**< Channel n Entry Configuration Register, offset: 0x63FE40E0 */
  __IO uint32_t CSCR10;                            /**< Channel n Status Configuration Register, offset: 0x63FE40E4 */
  __I  uint32_t CCBCR10;                           /**< Channel n Current Buffer Configuration Register, offset: 0x63FE40E8 */
  __IO uint32_t CNBCR10;                           /**< Channel n Next Buffer Configuration Register, offset: 0x63FE40EC */
  __IO uint32_t CECR11;                            /**< Channel n Entry Configuration Register, offset: 0x63FE40F0 */
  __IO uint32_t CSCR11;                            /**< Channel n Status Configuration Register, offset: 0x63FE40F4 */
  __I  uint32_t CCBCR11;                           /**< Channel n Current Buffer Configuration Register, offset: 0x63FE40F8 */
  __IO uint32_t CNBCR11;                           /**< Channel n Next Buffer Configuration Register, offset: 0x63FE40FC */
  __IO uint32_t CECR12;                            /**< Channel n Entry Configuration Register, offset: 0x63FE4100 */
  __IO uint32_t CSCR12;                            /**< Channel n Status Configuration Register, offset: 0x63FE4104 */
  __I  uint32_t CCBCR12;                           /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4108 */
  __IO uint32_t CNBCR12;                           /**< Channel n Next Buffer Configuration Register, offset: 0x63FE410C */
  __IO uint32_t CECR13;                            /**< Channel n Entry Configuration Register, offset: 0x63FE4110 */
  __IO uint32_t CSCR13;                            /**< Channel n Status Configuration Register, offset: 0x63FE4114 */
  __I  uint32_t CCBCR13;                           /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4118 */
  __IO uint32_t CNBCR13;                           /**< Channel n Next Buffer Configuration Register, offset: 0x63FE411C */
  __IO uint32_t CECR14;                            /**< Channel n Entry Configuration Register, offset: 0x63FE4120 */
  __IO uint32_t CSCR14;                            /**< Channel n Status Configuration Register, offset: 0x63FE4124 */
  __I  uint32_t CCBCR14;                           /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4128 */
  __IO uint32_t CNBCR14;                           /**< Channel n Next Buffer Configuration Register, offset: 0x63FE412C */
  __IO uint32_t CECR15;                            /**< Channel n Entry Configuration Register, offset: 0x63FE4130 */
  __IO uint32_t CSCR15;                            /**< Channel n Status Configuration Register, offset: 0x63FE4134 */
  __I  uint32_t CCBCR15;                           /**< Channel n Current Buffer Configuration Register, offset: 0x63FE4138 */
  __IO uint32_t CNBCR15;                           /**< Channel n Next Buffer Configuration Register, offset: 0x63FE413C */
       uint8_t RESERVED_3[320];
  __IO uint32_t LCBCR0;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE4280 */
  __IO uint32_t LCBCR1;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE4284 */
  __IO uint32_t LCBCR2;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE4288 */
  __IO uint32_t LCBCR3;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE428C */
  __IO uint32_t LCBCR4;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE4290 */
  __IO uint32_t LCBCR5;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE4294 */
  __IO uint32_t LCBCR6;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE4298 */
  __IO uint32_t LCBCR7;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE429C */
  __IO uint32_t LCBCR8;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42A0 */
  __IO uint32_t LCBCR9;                            /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42A4 */
  __IO uint32_t LCBCR10;                           /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42A8 */
  __IO uint32_t LCBCR11;                           /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42AC */
  __IO uint32_t LCBCR12;                           /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42B0 */
  __IO uint32_t LCBCR13;                           /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42B4 */
  __IO uint32_t LCBCR14;                           /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42B8 */
  __IO uint32_t LCBCR15;                           /**< Local Channel n Buffer Configuration Register, offset: 0x63FE42BC */
} MLB_Type;

/* ----------------------------------------------------------------------------
   -- MLB Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup MLB_Register_Masks MLB Register Masks
 * @{
 */

/* DCCR Bit Fields */
#define MLB_DCCR_MDA_MASK                        0xFFu
#define MLB_DCCR_MDA_SHIFT                       0
#define MLB_DCCR_MDA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_DCCR_MDA_SHIFT))&MLB_DCCR_MDA_MASK)
#define MLB_DCCR_MRS_MASK                        0x800000u
#define MLB_DCCR_MRS_SHIFT                       23
#define MLB_DCCR_MHRE_MASK                       0x1000000u
#define MLB_DCCR_MHRE_SHIFT                      24
#define MLB_DCCR_MLE_MASK                        0x2000000u
#define MLB_DCCR_MLE_SHIFT                       25
#define MLB_DCCR_MLK_MASK                        0x4000000u
#define MLB_DCCR_MLK_SHIFT                       26
#define MLB_DCCR_MCS_MASK                        0x30000000u
#define MLB_DCCR_MCS_SHIFT                       28
#define MLB_DCCR_MCS(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_DCCR_MCS_SHIFT))&MLB_DCCR_MCS_MASK)
#define MLB_DCCR_LBM_MASK                        0x40000000u
#define MLB_DCCR_LBM_SHIFT                       30
#define MLB_DCCR_MDE_MASK                        0x80000000u
#define MLB_DCCR_MDE_SHIFT                       31
/* SSCR Bit Fields */
#define MLB_SSCR_SDR_MASK                        0x1u
#define MLB_SSCR_SDR_SHIFT                       0
#define MLB_SSCR_SDNL_MASK                       0x2u
#define MLB_SSCR_SDNL_SHIFT                      1
#define MLB_SSCR_SDNU_MASK                       0x4u
#define MLB_SSCR_SDNU_SHIFT                      2
#define MLB_SSCR_SDCS_MASK                       0x8u
#define MLB_SSCR_SDCS_SHIFT                      3
#define MLB_SSCR_SDSC_MASK                       0x10u
#define MLB_SSCR_SDSC_SHIFT                      4
#define MLB_SSCR_SDML_MASK                       0x20u
#define MLB_SSCR_SDML_SHIFT                      5
#define MLB_SSCR_SDMU_MASK                       0x40u
#define MLB_SSCR_SDMU_SHIFT                      6
#define MLB_SSCR_SSRE_MASK                       0x80u
#define MLB_SSCR_SSRE_SHIFT                      7
/* SDCR Bit Fields */
#define MLB_SDCR_MSD_MASK                        0xFFFFFFFFu
#define MLB_SDCR_MSD_SHIFT                       0
#define MLB_SDCR_MSD(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_SDCR_MSD_SHIFT))&MLB_SDCR_MSD_MASK)
/* SMCR Bit Fields */
#define MLB_SMCR_SMR_MASK                        0x1u
#define MLB_SMCR_SMR_SHIFT                       0
#define MLB_SMCR_SMNL_MASK                       0x2u
#define MLB_SMCR_SMNL_SHIFT                      1
#define MLB_SMCR_SMNU_MASK                       0x4u
#define MLB_SMCR_SMNU_SHIFT                      2
#define MLB_SMCR_SMCS_MASK                       0x8u
#define MLB_SMCR_SMCS_SHIFT                      3
#define MLB_SMCR_SMSC_MASK                       0x10u
#define MLB_SMCR_SMSC_SHIFT                      4
#define MLB_SMCR_SMML_MASK                       0x20u
#define MLB_SMCR_SMML_SHIFT                      5
#define MLB_SMCR_SMMU_MASK                       0x40u
#define MLB_SMCR_SMMU_SHIFT                      6
/* VCCR Bit Fields */
#define MLB_VCCR_MMI_MASK                        0xFFu
#define MLB_VCCR_MMI_SHIFT                       0
#define MLB_VCCR_MMI(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_VCCR_MMI_SHIFT))&MLB_VCCR_MMI_MASK)
#define MLB_VCCR_MMA_MASK                        0xFF00u
#define MLB_VCCR_MMA_SHIFT                       8
#define MLB_VCCR_MMA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_VCCR_MMA_SHIFT))&MLB_VCCR_MMA_MASK)
#define MLB_VCCR_UMI_MASK                        0xFF0000u
#define MLB_VCCR_UMI_SHIFT                       16
#define MLB_VCCR_UMI(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_VCCR_UMI_SHIFT))&MLB_VCCR_UMI_MASK)
#define MLB_VCCR_UMA_MASK                        0xFF000000u
#define MLB_VCCR_UMA_SHIFT                       24
#define MLB_VCCR_UMA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_VCCR_UMA_SHIFT))&MLB_VCCR_UMA_MASK)
/* SBCR Bit Fields */
#define MLB_SBCR_STBA_MASK                       0xFFFFu
#define MLB_SBCR_STBA_SHIFT                      0
#define MLB_SBCR_STBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_SBCR_STBA_SHIFT))&MLB_SBCR_STBA_MASK)
#define MLB_SBCR_SRBA_MASK                       0xFFFF0000u
#define MLB_SBCR_SRBA_SHIFT                      16
#define MLB_SBCR_SRBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_SBCR_SRBA_SHIFT))&MLB_SBCR_SRBA_MASK)
/* ABCR Bit Fields */
#define MLB_ABCR_ATBA_MASK                       0xFFFFu
#define MLB_ABCR_ATBA_SHIFT                      0
#define MLB_ABCR_ATBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_ABCR_ATBA_SHIFT))&MLB_ABCR_ATBA_MASK)
#define MLB_ABCR_ARBA_MASK                       0xFFFF0000u
#define MLB_ABCR_ARBA_SHIFT                      16
#define MLB_ABCR_ARBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_ABCR_ARBA_SHIFT))&MLB_ABCR_ARBA_MASK)
/* CBCR Bit Fields */
#define MLB_CBCR_CTBA_MASK                       0xFFFFu
#define MLB_CBCR_CTBA_SHIFT                      0
#define MLB_CBCR_CTBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CBCR_CTBA_SHIFT))&MLB_CBCR_CTBA_MASK)
#define MLB_CBCR_CRBA_MASK                       0xFFFF0000u
#define MLB_CBCR_CRBA_SHIFT                      16
#define MLB_CBCR_CRBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CBCR_CRBA_SHIFT))&MLB_CBCR_CRBA_MASK)
/* IBCR Bit Fields */
#define MLB_IBCR_ITBA_MASK                       0xFFFFu
#define MLB_IBCR_ITBA_SHIFT                      0
#define MLB_IBCR_ITBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_IBCR_ITBA_SHIFT))&MLB_IBCR_ITBA_MASK)
#define MLB_IBCR_IRBA_MASK                       0xFFFF0000u
#define MLB_IBCR_IRBA_SHIFT                      16
#define MLB_IBCR_IRBA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_IBCR_IRBA_SHIFT))&MLB_IBCR_IRBA_MASK)
/* CICR Bit Fields */
#define MLB_CICR_CSU_MASK                        0xFFFFu
#define MLB_CICR_CSU_SHIFT                       0
#define MLB_CICR_CSU(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CICR_CSU_SHIFT))&MLB_CICR_CSU_MASK)
/* CECR0 Bit Fields */
#define MLB_CECR0_CA_MASK                        0xFFu
#define MLB_CECR0_CA_SHIFT                       0
#define MLB_CECR0_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR0_CA_SHIFT))&MLB_CECR0_CA_MASK)
#define MLB_CECR0_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR0_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR0_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR0_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR0_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR0_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR0_Rsvd_IPL_SHIFT                 13
#define MLB_CECR0_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR0_Rsvd_IPL_SHIFT))&MLB_CECR0_Rsvd_IPL_MASK)
#define MLB_CECR0_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR0_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR0_MPE_MASK                       0x10000u
#define MLB_CECR0_MPE_SHIFT                      16
#define MLB_CECR0_MDB_MASK                       0x20000u
#define MLB_CECR0_MDB_SHIFT                      17
#define MLB_CECR0_MBD_MASK                       0x40000u
#define MLB_CECR0_MBD_SHIFT                      18
#define MLB_CECR0_MBS_MASK                       0x80000u
#define MLB_CECR0_MBS_SHIFT                      19
#define MLB_CECR0_MBE_MASK                       0x100000u
#define MLB_CECR0_MBE_SHIFT                      20
#define MLB_CECR0_MLFS_MASK                      0x400000u
#define MLB_CECR0_MLFS_SHIFT                     22
#define MLB_CECR0_MDS_MASK                       0x6000000u
#define MLB_CECR0_MDS_SHIFT                      25
#define MLB_CECR0_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR0_MDS_SHIFT))&MLB_CECR0_MDS_MASK)
#define MLB_CECR0_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR0_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR0_CT_MASK                        0x30000000u
#define MLB_CECR0_CT_SHIFT                       28
#define MLB_CECR0_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR0_CT_SHIFT))&MLB_CECR0_CT_MASK)
#define MLB_CECR0_TR_MASK                        0x40000000u
#define MLB_CECR0_TR_SHIFT                       30
#define MLB_CECR0_CE_MASK                        0x80000000u
#define MLB_CECR0_CE_SHIFT                       31
/* CSCR0 Bit Fields */
#define MLB_CSCR0_CBPE_MASK                      0x1u
#define MLB_CSCR0_CBPE_SHIFT                     0
#define MLB_CSCR0_CBDB_MASK                      0x2u
#define MLB_CSCR0_CBDB_SHIFT                     1
#define MLB_CSCR0_CBD_MASK                       0x4u
#define MLB_CSCR0_CBD_SHIFT                      2
#define MLB_CSCR0_CBS_MASK                       0x8u
#define MLB_CSCR0_CBS_SHIFT                      3
#define MLB_CSCR0_BE_MASK                        0x10u
#define MLB_CSCR0_BE_SHIFT                       4
#define MLB_CSCR0_ABE_MASK                       0x20u
#define MLB_CSCR0_ABE_SHIFT                      5
#define MLB_CSCR0_LFS_MASK                       0x40u
#define MLB_CSCR0_LFS_SHIFT                      6
#define MLB_CSCR0_PBPE_MASK                      0x100u
#define MLB_CSCR0_PBPE_SHIFT                     8
#define MLB_CSCR0_PBDB_MASK                      0x200u
#define MLB_CSCR0_PBDB_SHIFT                     9
#define MLB_CSCR0_PBD_MASK                       0x400u
#define MLB_CSCR0_PBD_SHIFT                      10
#define MLB_CSCR0_PBS_MASK                       0x800u
#define MLB_CSCR0_PBS_SHIFT                      11
#define MLB_CSCR0_RDY_MASK                       0x10000u
#define MLB_CSCR0_RDY_SHIFT                      16
#define MLB_CSCR0_GIRB_MASK                      0x20000u
#define MLB_CSCR0_GIRB_SHIFT                     17
#define MLB_CSCR0_IVB_MASK                       0xC0000u
#define MLB_CSCR0_IVB_SHIFT                      18
#define MLB_CSCR0_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR0_IVB_SHIFT))&MLB_CSCR0_IVB_MASK)
#define MLB_CSCR0_BF_MASK                        0x40000000u
#define MLB_CSCR0_BF_SHIFT                       30
#define MLB_CSCR0_BM_MASK                        0x80000000u
#define MLB_CSCR0_BM_SHIFT                       31
/* CCBCR0 Bit Fields */
#define MLB_CCBCR0_BFA0_MASK                     0x3u
#define MLB_CCBCR0_BFA0_SHIFT                    0
#define MLB_CCBCR0_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR0_BFA0_SHIFT))&MLB_CCBCR0_BFA0_MASK)
#define MLB_CCBCR0_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR0_BFA1_SHIFT                    2
#define MLB_CCBCR0_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR0_BFA1_SHIFT))&MLB_CCBCR0_BFA1_MASK)
#define MLB_CCBCR0_BCA0_MASK                     0x30000u
#define MLB_CCBCR0_BCA0_SHIFT                    16
#define MLB_CCBCR0_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR0_BCA0_SHIFT))&MLB_CCBCR0_BCA0_MASK)
#define MLB_CCBCR0_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR0_BCA1_SHIFT                    18
#define MLB_CCBCR0_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR0_BCA1_SHIFT))&MLB_CCBCR0_BCA1_MASK)
/* CNBCR0 Bit Fields */
#define MLB_CNBCR0_BEA_MASK                      0xFFFFu
#define MLB_CNBCR0_BEA_SHIFT                     0
#define MLB_CNBCR0_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR0_BEA_SHIFT))&MLB_CNBCR0_BEA_MASK)
#define MLB_CNBCR0_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR0_BSA_SHIFT                     16
#define MLB_CNBCR0_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR0_BSA_SHIFT))&MLB_CNBCR0_BSA_MASK)
/* CECR1 Bit Fields */
#define MLB_CECR1_CA_MASK                        0xFFu
#define MLB_CECR1_CA_SHIFT                       0
#define MLB_CECR1_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR1_CA_SHIFT))&MLB_CECR1_CA_MASK)
#define MLB_CECR1_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR1_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR1_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR1_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR1_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR1_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR1_Rsvd_IPL_SHIFT                 13
#define MLB_CECR1_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR1_Rsvd_IPL_SHIFT))&MLB_CECR1_Rsvd_IPL_MASK)
#define MLB_CECR1_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR1_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR1_MPE_MASK                       0x10000u
#define MLB_CECR1_MPE_SHIFT                      16
#define MLB_CECR1_MDB_MASK                       0x20000u
#define MLB_CECR1_MDB_SHIFT                      17
#define MLB_CECR1_MBD_MASK                       0x40000u
#define MLB_CECR1_MBD_SHIFT                      18
#define MLB_CECR1_MBS_MASK                       0x80000u
#define MLB_CECR1_MBS_SHIFT                      19
#define MLB_CECR1_MBE_MASK                       0x100000u
#define MLB_CECR1_MBE_SHIFT                      20
#define MLB_CECR1_MLFS_MASK                      0x400000u
#define MLB_CECR1_MLFS_SHIFT                     22
#define MLB_CECR1_MDS_MASK                       0x6000000u
#define MLB_CECR1_MDS_SHIFT                      25
#define MLB_CECR1_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR1_MDS_SHIFT))&MLB_CECR1_MDS_MASK)
#define MLB_CECR1_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR1_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR1_CT_MASK                        0x30000000u
#define MLB_CECR1_CT_SHIFT                       28
#define MLB_CECR1_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR1_CT_SHIFT))&MLB_CECR1_CT_MASK)
#define MLB_CECR1_TR_MASK                        0x40000000u
#define MLB_CECR1_TR_SHIFT                       30
#define MLB_CECR1_CE_MASK                        0x80000000u
#define MLB_CECR1_CE_SHIFT                       31
/* CSCR1 Bit Fields */
#define MLB_CSCR1_CBPE_MASK                      0x1u
#define MLB_CSCR1_CBPE_SHIFT                     0
#define MLB_CSCR1_CBDB_MASK                      0x2u
#define MLB_CSCR1_CBDB_SHIFT                     1
#define MLB_CSCR1_CBD_MASK                       0x4u
#define MLB_CSCR1_CBD_SHIFT                      2
#define MLB_CSCR1_CBS_MASK                       0x8u
#define MLB_CSCR1_CBS_SHIFT                      3
#define MLB_CSCR1_BE_MASK                        0x10u
#define MLB_CSCR1_BE_SHIFT                       4
#define MLB_CSCR1_ABE_MASK                       0x20u
#define MLB_CSCR1_ABE_SHIFT                      5
#define MLB_CSCR1_LFS_MASK                       0x40u
#define MLB_CSCR1_LFS_SHIFT                      6
#define MLB_CSCR1_PBPE_MASK                      0x100u
#define MLB_CSCR1_PBPE_SHIFT                     8
#define MLB_CSCR1_PBDB_MASK                      0x200u
#define MLB_CSCR1_PBDB_SHIFT                     9
#define MLB_CSCR1_PBD_MASK                       0x400u
#define MLB_CSCR1_PBD_SHIFT                      10
#define MLB_CSCR1_PBS_MASK                       0x800u
#define MLB_CSCR1_PBS_SHIFT                      11
#define MLB_CSCR1_RDY_MASK                       0x10000u
#define MLB_CSCR1_RDY_SHIFT                      16
#define MLB_CSCR1_GIRB_MASK                      0x20000u
#define MLB_CSCR1_GIRB_SHIFT                     17
#define MLB_CSCR1_IVB_MASK                       0xC0000u
#define MLB_CSCR1_IVB_SHIFT                      18
#define MLB_CSCR1_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR1_IVB_SHIFT))&MLB_CSCR1_IVB_MASK)
#define MLB_CSCR1_BF_MASK                        0x40000000u
#define MLB_CSCR1_BF_SHIFT                       30
#define MLB_CSCR1_BM_MASK                        0x80000000u
#define MLB_CSCR1_BM_SHIFT                       31
/* CCBCR1 Bit Fields */
#define MLB_CCBCR1_BFA0_MASK                     0x3u
#define MLB_CCBCR1_BFA0_SHIFT                    0
#define MLB_CCBCR1_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR1_BFA0_SHIFT))&MLB_CCBCR1_BFA0_MASK)
#define MLB_CCBCR1_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR1_BFA1_SHIFT                    2
#define MLB_CCBCR1_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR1_BFA1_SHIFT))&MLB_CCBCR1_BFA1_MASK)
#define MLB_CCBCR1_BCA0_MASK                     0x30000u
#define MLB_CCBCR1_BCA0_SHIFT                    16
#define MLB_CCBCR1_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR1_BCA0_SHIFT))&MLB_CCBCR1_BCA0_MASK)
#define MLB_CCBCR1_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR1_BCA1_SHIFT                    18
#define MLB_CCBCR1_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR1_BCA1_SHIFT))&MLB_CCBCR1_BCA1_MASK)
/* CNBCR1 Bit Fields */
#define MLB_CNBCR1_BEA_MASK                      0xFFFFu
#define MLB_CNBCR1_BEA_SHIFT                     0
#define MLB_CNBCR1_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR1_BEA_SHIFT))&MLB_CNBCR1_BEA_MASK)
#define MLB_CNBCR1_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR1_BSA_SHIFT                     16
#define MLB_CNBCR1_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR1_BSA_SHIFT))&MLB_CNBCR1_BSA_MASK)
/* CECR2 Bit Fields */
#define MLB_CECR2_CA_MASK                        0xFFu
#define MLB_CECR2_CA_SHIFT                       0
#define MLB_CECR2_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR2_CA_SHIFT))&MLB_CECR2_CA_MASK)
#define MLB_CECR2_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR2_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR2_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR2_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR2_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR2_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR2_Rsvd_IPL_SHIFT                 13
#define MLB_CECR2_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR2_Rsvd_IPL_SHIFT))&MLB_CECR2_Rsvd_IPL_MASK)
#define MLB_CECR2_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR2_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR2_MPE_MASK                       0x10000u
#define MLB_CECR2_MPE_SHIFT                      16
#define MLB_CECR2_MDB_MASK                       0x20000u
#define MLB_CECR2_MDB_SHIFT                      17
#define MLB_CECR2_MBD_MASK                       0x40000u
#define MLB_CECR2_MBD_SHIFT                      18
#define MLB_CECR2_MBS_MASK                       0x80000u
#define MLB_CECR2_MBS_SHIFT                      19
#define MLB_CECR2_MBE_MASK                       0x100000u
#define MLB_CECR2_MBE_SHIFT                      20
#define MLB_CECR2_MLFS_MASK                      0x400000u
#define MLB_CECR2_MLFS_SHIFT                     22
#define MLB_CECR2_MDS_MASK                       0x6000000u
#define MLB_CECR2_MDS_SHIFT                      25
#define MLB_CECR2_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR2_MDS_SHIFT))&MLB_CECR2_MDS_MASK)
#define MLB_CECR2_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR2_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR2_CT_MASK                        0x30000000u
#define MLB_CECR2_CT_SHIFT                       28
#define MLB_CECR2_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR2_CT_SHIFT))&MLB_CECR2_CT_MASK)
#define MLB_CECR2_TR_MASK                        0x40000000u
#define MLB_CECR2_TR_SHIFT                       30
#define MLB_CECR2_CE_MASK                        0x80000000u
#define MLB_CECR2_CE_SHIFT                       31
/* CSCR2 Bit Fields */
#define MLB_CSCR2_CBPE_MASK                      0x1u
#define MLB_CSCR2_CBPE_SHIFT                     0
#define MLB_CSCR2_CBDB_MASK                      0x2u
#define MLB_CSCR2_CBDB_SHIFT                     1
#define MLB_CSCR2_CBD_MASK                       0x4u
#define MLB_CSCR2_CBD_SHIFT                      2
#define MLB_CSCR2_CBS_MASK                       0x8u
#define MLB_CSCR2_CBS_SHIFT                      3
#define MLB_CSCR2_BE_MASK                        0x10u
#define MLB_CSCR2_BE_SHIFT                       4
#define MLB_CSCR2_ABE_MASK                       0x20u
#define MLB_CSCR2_ABE_SHIFT                      5
#define MLB_CSCR2_LFS_MASK                       0x40u
#define MLB_CSCR2_LFS_SHIFT                      6
#define MLB_CSCR2_PBPE_MASK                      0x100u
#define MLB_CSCR2_PBPE_SHIFT                     8
#define MLB_CSCR2_PBDB_MASK                      0x200u
#define MLB_CSCR2_PBDB_SHIFT                     9
#define MLB_CSCR2_PBD_MASK                       0x400u
#define MLB_CSCR2_PBD_SHIFT                      10
#define MLB_CSCR2_PBS_MASK                       0x800u
#define MLB_CSCR2_PBS_SHIFT                      11
#define MLB_CSCR2_RDY_MASK                       0x10000u
#define MLB_CSCR2_RDY_SHIFT                      16
#define MLB_CSCR2_GIRB_MASK                      0x20000u
#define MLB_CSCR2_GIRB_SHIFT                     17
#define MLB_CSCR2_IVB_MASK                       0xC0000u
#define MLB_CSCR2_IVB_SHIFT                      18
#define MLB_CSCR2_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR2_IVB_SHIFT))&MLB_CSCR2_IVB_MASK)
#define MLB_CSCR2_BF_MASK                        0x40000000u
#define MLB_CSCR2_BF_SHIFT                       30
#define MLB_CSCR2_BM_MASK                        0x80000000u
#define MLB_CSCR2_BM_SHIFT                       31
/* CCBCR2 Bit Fields */
#define MLB_CCBCR2_BFA0_MASK                     0x3u
#define MLB_CCBCR2_BFA0_SHIFT                    0
#define MLB_CCBCR2_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR2_BFA0_SHIFT))&MLB_CCBCR2_BFA0_MASK)
#define MLB_CCBCR2_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR2_BFA1_SHIFT                    2
#define MLB_CCBCR2_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR2_BFA1_SHIFT))&MLB_CCBCR2_BFA1_MASK)
#define MLB_CCBCR2_BCA0_MASK                     0x30000u
#define MLB_CCBCR2_BCA0_SHIFT                    16
#define MLB_CCBCR2_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR2_BCA0_SHIFT))&MLB_CCBCR2_BCA0_MASK)
#define MLB_CCBCR2_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR2_BCA1_SHIFT                    18
#define MLB_CCBCR2_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR2_BCA1_SHIFT))&MLB_CCBCR2_BCA1_MASK)
/* CNBCR2 Bit Fields */
#define MLB_CNBCR2_BEA_MASK                      0xFFFFu
#define MLB_CNBCR2_BEA_SHIFT                     0
#define MLB_CNBCR2_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR2_BEA_SHIFT))&MLB_CNBCR2_BEA_MASK)
#define MLB_CNBCR2_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR2_BSA_SHIFT                     16
#define MLB_CNBCR2_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR2_BSA_SHIFT))&MLB_CNBCR2_BSA_MASK)
/* CECR3 Bit Fields */
#define MLB_CECR3_CA_MASK                        0xFFu
#define MLB_CECR3_CA_SHIFT                       0
#define MLB_CECR3_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR3_CA_SHIFT))&MLB_CECR3_CA_MASK)
#define MLB_CECR3_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR3_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR3_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR3_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR3_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR3_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR3_Rsvd_IPL_SHIFT                 13
#define MLB_CECR3_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR3_Rsvd_IPL_SHIFT))&MLB_CECR3_Rsvd_IPL_MASK)
#define MLB_CECR3_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR3_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR3_MPE_MASK                       0x10000u
#define MLB_CECR3_MPE_SHIFT                      16
#define MLB_CECR3_MDB_MASK                       0x20000u
#define MLB_CECR3_MDB_SHIFT                      17
#define MLB_CECR3_MBD_MASK                       0x40000u
#define MLB_CECR3_MBD_SHIFT                      18
#define MLB_CECR3_MBS_MASK                       0x80000u
#define MLB_CECR3_MBS_SHIFT                      19
#define MLB_CECR3_MBE_MASK                       0x100000u
#define MLB_CECR3_MBE_SHIFT                      20
#define MLB_CECR3_MLFS_MASK                      0x400000u
#define MLB_CECR3_MLFS_SHIFT                     22
#define MLB_CECR3_MDS_MASK                       0x6000000u
#define MLB_CECR3_MDS_SHIFT                      25
#define MLB_CECR3_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR3_MDS_SHIFT))&MLB_CECR3_MDS_MASK)
#define MLB_CECR3_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR3_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR3_CT_MASK                        0x30000000u
#define MLB_CECR3_CT_SHIFT                       28
#define MLB_CECR3_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR3_CT_SHIFT))&MLB_CECR3_CT_MASK)
#define MLB_CECR3_TR_MASK                        0x40000000u
#define MLB_CECR3_TR_SHIFT                       30
#define MLB_CECR3_CE_MASK                        0x80000000u
#define MLB_CECR3_CE_SHIFT                       31
/* CSCR3 Bit Fields */
#define MLB_CSCR3_CBPE_MASK                      0x1u
#define MLB_CSCR3_CBPE_SHIFT                     0
#define MLB_CSCR3_CBDB_MASK                      0x2u
#define MLB_CSCR3_CBDB_SHIFT                     1
#define MLB_CSCR3_CBD_MASK                       0x4u
#define MLB_CSCR3_CBD_SHIFT                      2
#define MLB_CSCR3_CBS_MASK                       0x8u
#define MLB_CSCR3_CBS_SHIFT                      3
#define MLB_CSCR3_BE_MASK                        0x10u
#define MLB_CSCR3_BE_SHIFT                       4
#define MLB_CSCR3_ABE_MASK                       0x20u
#define MLB_CSCR3_ABE_SHIFT                      5
#define MLB_CSCR3_LFS_MASK                       0x40u
#define MLB_CSCR3_LFS_SHIFT                      6
#define MLB_CSCR3_PBPE_MASK                      0x100u
#define MLB_CSCR3_PBPE_SHIFT                     8
#define MLB_CSCR3_PBDB_MASK                      0x200u
#define MLB_CSCR3_PBDB_SHIFT                     9
#define MLB_CSCR3_PBD_MASK                       0x400u
#define MLB_CSCR3_PBD_SHIFT                      10
#define MLB_CSCR3_PBS_MASK                       0x800u
#define MLB_CSCR3_PBS_SHIFT                      11
#define MLB_CSCR3_RDY_MASK                       0x10000u
#define MLB_CSCR3_RDY_SHIFT                      16
#define MLB_CSCR3_GIRB_MASK                      0x20000u
#define MLB_CSCR3_GIRB_SHIFT                     17
#define MLB_CSCR3_IVB_MASK                       0xC0000u
#define MLB_CSCR3_IVB_SHIFT                      18
#define MLB_CSCR3_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR3_IVB_SHIFT))&MLB_CSCR3_IVB_MASK)
#define MLB_CSCR3_BF_MASK                        0x40000000u
#define MLB_CSCR3_BF_SHIFT                       30
#define MLB_CSCR3_BM_MASK                        0x80000000u
#define MLB_CSCR3_BM_SHIFT                       31
/* CCBCR3 Bit Fields */
#define MLB_CCBCR3_BFA0_MASK                     0x3u
#define MLB_CCBCR3_BFA0_SHIFT                    0
#define MLB_CCBCR3_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR3_BFA0_SHIFT))&MLB_CCBCR3_BFA0_MASK)
#define MLB_CCBCR3_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR3_BFA1_SHIFT                    2
#define MLB_CCBCR3_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR3_BFA1_SHIFT))&MLB_CCBCR3_BFA1_MASK)
#define MLB_CCBCR3_BCA0_MASK                     0x30000u
#define MLB_CCBCR3_BCA0_SHIFT                    16
#define MLB_CCBCR3_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR3_BCA0_SHIFT))&MLB_CCBCR3_BCA0_MASK)
#define MLB_CCBCR3_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR3_BCA1_SHIFT                    18
#define MLB_CCBCR3_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR3_BCA1_SHIFT))&MLB_CCBCR3_BCA1_MASK)
/* CNBCR3 Bit Fields */
#define MLB_CNBCR3_BEA_MASK                      0xFFFFu
#define MLB_CNBCR3_BEA_SHIFT                     0
#define MLB_CNBCR3_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR3_BEA_SHIFT))&MLB_CNBCR3_BEA_MASK)
#define MLB_CNBCR3_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR3_BSA_SHIFT                     16
#define MLB_CNBCR3_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR3_BSA_SHIFT))&MLB_CNBCR3_BSA_MASK)
/* CECR4 Bit Fields */
#define MLB_CECR4_CA_MASK                        0xFFu
#define MLB_CECR4_CA_SHIFT                       0
#define MLB_CECR4_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR4_CA_SHIFT))&MLB_CECR4_CA_MASK)
#define MLB_CECR4_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR4_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR4_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR4_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR4_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR4_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR4_Rsvd_IPL_SHIFT                 13
#define MLB_CECR4_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR4_Rsvd_IPL_SHIFT))&MLB_CECR4_Rsvd_IPL_MASK)
#define MLB_CECR4_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR4_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR4_MPE_MASK                       0x10000u
#define MLB_CECR4_MPE_SHIFT                      16
#define MLB_CECR4_MDB_MASK                       0x20000u
#define MLB_CECR4_MDB_SHIFT                      17
#define MLB_CECR4_MBD_MASK                       0x40000u
#define MLB_CECR4_MBD_SHIFT                      18
#define MLB_CECR4_MBS_MASK                       0x80000u
#define MLB_CECR4_MBS_SHIFT                      19
#define MLB_CECR4_MBE_MASK                       0x100000u
#define MLB_CECR4_MBE_SHIFT                      20
#define MLB_CECR4_MLFS_MASK                      0x400000u
#define MLB_CECR4_MLFS_SHIFT                     22
#define MLB_CECR4_MDS_MASK                       0x6000000u
#define MLB_CECR4_MDS_SHIFT                      25
#define MLB_CECR4_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR4_MDS_SHIFT))&MLB_CECR4_MDS_MASK)
#define MLB_CECR4_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR4_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR4_CT_MASK                        0x30000000u
#define MLB_CECR4_CT_SHIFT                       28
#define MLB_CECR4_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR4_CT_SHIFT))&MLB_CECR4_CT_MASK)
#define MLB_CECR4_TR_MASK                        0x40000000u
#define MLB_CECR4_TR_SHIFT                       30
#define MLB_CECR4_CE_MASK                        0x80000000u
#define MLB_CECR4_CE_SHIFT                       31
/* CSCR4 Bit Fields */
#define MLB_CSCR4_CBPE_MASK                      0x1u
#define MLB_CSCR4_CBPE_SHIFT                     0
#define MLB_CSCR4_CBDB_MASK                      0x2u
#define MLB_CSCR4_CBDB_SHIFT                     1
#define MLB_CSCR4_CBD_MASK                       0x4u
#define MLB_CSCR4_CBD_SHIFT                      2
#define MLB_CSCR4_CBS_MASK                       0x8u
#define MLB_CSCR4_CBS_SHIFT                      3
#define MLB_CSCR4_BE_MASK                        0x10u
#define MLB_CSCR4_BE_SHIFT                       4
#define MLB_CSCR4_ABE_MASK                       0x20u
#define MLB_CSCR4_ABE_SHIFT                      5
#define MLB_CSCR4_LFS_MASK                       0x40u
#define MLB_CSCR4_LFS_SHIFT                      6
#define MLB_CSCR4_PBPE_MASK                      0x100u
#define MLB_CSCR4_PBPE_SHIFT                     8
#define MLB_CSCR4_PBDB_MASK                      0x200u
#define MLB_CSCR4_PBDB_SHIFT                     9
#define MLB_CSCR4_PBD_MASK                       0x400u
#define MLB_CSCR4_PBD_SHIFT                      10
#define MLB_CSCR4_PBS_MASK                       0x800u
#define MLB_CSCR4_PBS_SHIFT                      11
#define MLB_CSCR4_RDY_MASK                       0x10000u
#define MLB_CSCR4_RDY_SHIFT                      16
#define MLB_CSCR4_GIRB_MASK                      0x20000u
#define MLB_CSCR4_GIRB_SHIFT                     17
#define MLB_CSCR4_IVB_MASK                       0xC0000u
#define MLB_CSCR4_IVB_SHIFT                      18
#define MLB_CSCR4_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR4_IVB_SHIFT))&MLB_CSCR4_IVB_MASK)
#define MLB_CSCR4_BF_MASK                        0x40000000u
#define MLB_CSCR4_BF_SHIFT                       30
#define MLB_CSCR4_BM_MASK                        0x80000000u
#define MLB_CSCR4_BM_SHIFT                       31
/* CCBCR4 Bit Fields */
#define MLB_CCBCR4_BFA0_MASK                     0x3u
#define MLB_CCBCR4_BFA0_SHIFT                    0
#define MLB_CCBCR4_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR4_BFA0_SHIFT))&MLB_CCBCR4_BFA0_MASK)
#define MLB_CCBCR4_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR4_BFA1_SHIFT                    2
#define MLB_CCBCR4_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR4_BFA1_SHIFT))&MLB_CCBCR4_BFA1_MASK)
#define MLB_CCBCR4_BCA0_MASK                     0x30000u
#define MLB_CCBCR4_BCA0_SHIFT                    16
#define MLB_CCBCR4_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR4_BCA0_SHIFT))&MLB_CCBCR4_BCA0_MASK)
#define MLB_CCBCR4_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR4_BCA1_SHIFT                    18
#define MLB_CCBCR4_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR4_BCA1_SHIFT))&MLB_CCBCR4_BCA1_MASK)
/* CNBCR4 Bit Fields */
#define MLB_CNBCR4_BEA_MASK                      0xFFFFu
#define MLB_CNBCR4_BEA_SHIFT                     0
#define MLB_CNBCR4_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR4_BEA_SHIFT))&MLB_CNBCR4_BEA_MASK)
#define MLB_CNBCR4_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR4_BSA_SHIFT                     16
#define MLB_CNBCR4_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR4_BSA_SHIFT))&MLB_CNBCR4_BSA_MASK)
/* CECR5 Bit Fields */
#define MLB_CECR5_CA_MASK                        0xFFu
#define MLB_CECR5_CA_SHIFT                       0
#define MLB_CECR5_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR5_CA_SHIFT))&MLB_CECR5_CA_MASK)
#define MLB_CECR5_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR5_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR5_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR5_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR5_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR5_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR5_Rsvd_IPL_SHIFT                 13
#define MLB_CECR5_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR5_Rsvd_IPL_SHIFT))&MLB_CECR5_Rsvd_IPL_MASK)
#define MLB_CECR5_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR5_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR5_MPE_MASK                       0x10000u
#define MLB_CECR5_MPE_SHIFT                      16
#define MLB_CECR5_MDB_MASK                       0x20000u
#define MLB_CECR5_MDB_SHIFT                      17
#define MLB_CECR5_MBD_MASK                       0x40000u
#define MLB_CECR5_MBD_SHIFT                      18
#define MLB_CECR5_MBS_MASK                       0x80000u
#define MLB_CECR5_MBS_SHIFT                      19
#define MLB_CECR5_MBE_MASK                       0x100000u
#define MLB_CECR5_MBE_SHIFT                      20
#define MLB_CECR5_MLFS_MASK                      0x400000u
#define MLB_CECR5_MLFS_SHIFT                     22
#define MLB_CECR5_MDS_MASK                       0x6000000u
#define MLB_CECR5_MDS_SHIFT                      25
#define MLB_CECR5_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR5_MDS_SHIFT))&MLB_CECR5_MDS_MASK)
#define MLB_CECR5_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR5_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR5_CT_MASK                        0x30000000u
#define MLB_CECR5_CT_SHIFT                       28
#define MLB_CECR5_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR5_CT_SHIFT))&MLB_CECR5_CT_MASK)
#define MLB_CECR5_TR_MASK                        0x40000000u
#define MLB_CECR5_TR_SHIFT                       30
#define MLB_CECR5_CE_MASK                        0x80000000u
#define MLB_CECR5_CE_SHIFT                       31
/* CSCR5 Bit Fields */
#define MLB_CSCR5_CBPE_MASK                      0x1u
#define MLB_CSCR5_CBPE_SHIFT                     0
#define MLB_CSCR5_CBDB_MASK                      0x2u
#define MLB_CSCR5_CBDB_SHIFT                     1
#define MLB_CSCR5_CBD_MASK                       0x4u
#define MLB_CSCR5_CBD_SHIFT                      2
#define MLB_CSCR5_CBS_MASK                       0x8u
#define MLB_CSCR5_CBS_SHIFT                      3
#define MLB_CSCR5_BE_MASK                        0x10u
#define MLB_CSCR5_BE_SHIFT                       4
#define MLB_CSCR5_ABE_MASK                       0x20u
#define MLB_CSCR5_ABE_SHIFT                      5
#define MLB_CSCR5_LFS_MASK                       0x40u
#define MLB_CSCR5_LFS_SHIFT                      6
#define MLB_CSCR5_PBPE_MASK                      0x100u
#define MLB_CSCR5_PBPE_SHIFT                     8
#define MLB_CSCR5_PBDB_MASK                      0x200u
#define MLB_CSCR5_PBDB_SHIFT                     9
#define MLB_CSCR5_PBD_MASK                       0x400u
#define MLB_CSCR5_PBD_SHIFT                      10
#define MLB_CSCR5_PBS_MASK                       0x800u
#define MLB_CSCR5_PBS_SHIFT                      11
#define MLB_CSCR5_RDY_MASK                       0x10000u
#define MLB_CSCR5_RDY_SHIFT                      16
#define MLB_CSCR5_GIRB_MASK                      0x20000u
#define MLB_CSCR5_GIRB_SHIFT                     17
#define MLB_CSCR5_IVB_MASK                       0xC0000u
#define MLB_CSCR5_IVB_SHIFT                      18
#define MLB_CSCR5_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR5_IVB_SHIFT))&MLB_CSCR5_IVB_MASK)
#define MLB_CSCR5_BF_MASK                        0x40000000u
#define MLB_CSCR5_BF_SHIFT                       30
#define MLB_CSCR5_BM_MASK                        0x80000000u
#define MLB_CSCR5_BM_SHIFT                       31
/* CCBCR5 Bit Fields */
#define MLB_CCBCR5_BFA0_MASK                     0x3u
#define MLB_CCBCR5_BFA0_SHIFT                    0
#define MLB_CCBCR5_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR5_BFA0_SHIFT))&MLB_CCBCR5_BFA0_MASK)
#define MLB_CCBCR5_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR5_BFA1_SHIFT                    2
#define MLB_CCBCR5_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR5_BFA1_SHIFT))&MLB_CCBCR5_BFA1_MASK)
#define MLB_CCBCR5_BCA0_MASK                     0x30000u
#define MLB_CCBCR5_BCA0_SHIFT                    16
#define MLB_CCBCR5_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR5_BCA0_SHIFT))&MLB_CCBCR5_BCA0_MASK)
#define MLB_CCBCR5_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR5_BCA1_SHIFT                    18
#define MLB_CCBCR5_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR5_BCA1_SHIFT))&MLB_CCBCR5_BCA1_MASK)
/* CNBCR5 Bit Fields */
#define MLB_CNBCR5_BEA_MASK                      0xFFFFu
#define MLB_CNBCR5_BEA_SHIFT                     0
#define MLB_CNBCR5_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR5_BEA_SHIFT))&MLB_CNBCR5_BEA_MASK)
#define MLB_CNBCR5_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR5_BSA_SHIFT                     16
#define MLB_CNBCR5_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR5_BSA_SHIFT))&MLB_CNBCR5_BSA_MASK)
/* CECR6 Bit Fields */
#define MLB_CECR6_CA_MASK                        0xFFu
#define MLB_CECR6_CA_SHIFT                       0
#define MLB_CECR6_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR6_CA_SHIFT))&MLB_CECR6_CA_MASK)
#define MLB_CECR6_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR6_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR6_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR6_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR6_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR6_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR6_Rsvd_IPL_SHIFT                 13
#define MLB_CECR6_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR6_Rsvd_IPL_SHIFT))&MLB_CECR6_Rsvd_IPL_MASK)
#define MLB_CECR6_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR6_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR6_MPE_MASK                       0x10000u
#define MLB_CECR6_MPE_SHIFT                      16
#define MLB_CECR6_MDB_MASK                       0x20000u
#define MLB_CECR6_MDB_SHIFT                      17
#define MLB_CECR6_MBD_MASK                       0x40000u
#define MLB_CECR6_MBD_SHIFT                      18
#define MLB_CECR6_MBS_MASK                       0x80000u
#define MLB_CECR6_MBS_SHIFT                      19
#define MLB_CECR6_MBE_MASK                       0x100000u
#define MLB_CECR6_MBE_SHIFT                      20
#define MLB_CECR6_MLFS_MASK                      0x400000u
#define MLB_CECR6_MLFS_SHIFT                     22
#define MLB_CECR6_MDS_MASK                       0x6000000u
#define MLB_CECR6_MDS_SHIFT                      25
#define MLB_CECR6_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR6_MDS_SHIFT))&MLB_CECR6_MDS_MASK)
#define MLB_CECR6_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR6_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR6_CT_MASK                        0x30000000u
#define MLB_CECR6_CT_SHIFT                       28
#define MLB_CECR6_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR6_CT_SHIFT))&MLB_CECR6_CT_MASK)
#define MLB_CECR6_TR_MASK                        0x40000000u
#define MLB_CECR6_TR_SHIFT                       30
#define MLB_CECR6_CE_MASK                        0x80000000u
#define MLB_CECR6_CE_SHIFT                       31
/* CSCR6 Bit Fields */
#define MLB_CSCR6_CBPE_MASK                      0x1u
#define MLB_CSCR6_CBPE_SHIFT                     0
#define MLB_CSCR6_CBDB_MASK                      0x2u
#define MLB_CSCR6_CBDB_SHIFT                     1
#define MLB_CSCR6_CBD_MASK                       0x4u
#define MLB_CSCR6_CBD_SHIFT                      2
#define MLB_CSCR6_CBS_MASK                       0x8u
#define MLB_CSCR6_CBS_SHIFT                      3
#define MLB_CSCR6_BE_MASK                        0x10u
#define MLB_CSCR6_BE_SHIFT                       4
#define MLB_CSCR6_ABE_MASK                       0x20u
#define MLB_CSCR6_ABE_SHIFT                      5
#define MLB_CSCR6_LFS_MASK                       0x40u
#define MLB_CSCR6_LFS_SHIFT                      6
#define MLB_CSCR6_PBPE_MASK                      0x100u
#define MLB_CSCR6_PBPE_SHIFT                     8
#define MLB_CSCR6_PBDB_MASK                      0x200u
#define MLB_CSCR6_PBDB_SHIFT                     9
#define MLB_CSCR6_PBD_MASK                       0x400u
#define MLB_CSCR6_PBD_SHIFT                      10
#define MLB_CSCR6_PBS_MASK                       0x800u
#define MLB_CSCR6_PBS_SHIFT                      11
#define MLB_CSCR6_RDY_MASK                       0x10000u
#define MLB_CSCR6_RDY_SHIFT                      16
#define MLB_CSCR6_GIRB_MASK                      0x20000u
#define MLB_CSCR6_GIRB_SHIFT                     17
#define MLB_CSCR6_IVB_MASK                       0xC0000u
#define MLB_CSCR6_IVB_SHIFT                      18
#define MLB_CSCR6_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR6_IVB_SHIFT))&MLB_CSCR6_IVB_MASK)
#define MLB_CSCR6_BF_MASK                        0x40000000u
#define MLB_CSCR6_BF_SHIFT                       30
#define MLB_CSCR6_BM_MASK                        0x80000000u
#define MLB_CSCR6_BM_SHIFT                       31
/* CCBCR6 Bit Fields */
#define MLB_CCBCR6_BFA0_MASK                     0x3u
#define MLB_CCBCR6_BFA0_SHIFT                    0
#define MLB_CCBCR6_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR6_BFA0_SHIFT))&MLB_CCBCR6_BFA0_MASK)
#define MLB_CCBCR6_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR6_BFA1_SHIFT                    2
#define MLB_CCBCR6_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR6_BFA1_SHIFT))&MLB_CCBCR6_BFA1_MASK)
#define MLB_CCBCR6_BCA0_MASK                     0x30000u
#define MLB_CCBCR6_BCA0_SHIFT                    16
#define MLB_CCBCR6_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR6_BCA0_SHIFT))&MLB_CCBCR6_BCA0_MASK)
#define MLB_CCBCR6_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR6_BCA1_SHIFT                    18
#define MLB_CCBCR6_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR6_BCA1_SHIFT))&MLB_CCBCR6_BCA1_MASK)
/* CNBCR6 Bit Fields */
#define MLB_CNBCR6_BEA_MASK                      0xFFFFu
#define MLB_CNBCR6_BEA_SHIFT                     0
#define MLB_CNBCR6_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR6_BEA_SHIFT))&MLB_CNBCR6_BEA_MASK)
#define MLB_CNBCR6_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR6_BSA_SHIFT                     16
#define MLB_CNBCR6_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR6_BSA_SHIFT))&MLB_CNBCR6_BSA_MASK)
/* CECR7 Bit Fields */
#define MLB_CECR7_CA_MASK                        0xFFu
#define MLB_CECR7_CA_SHIFT                       0
#define MLB_CECR7_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR7_CA_SHIFT))&MLB_CECR7_CA_MASK)
#define MLB_CECR7_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR7_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR7_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR7_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR7_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR7_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR7_Rsvd_IPL_SHIFT                 13
#define MLB_CECR7_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR7_Rsvd_IPL_SHIFT))&MLB_CECR7_Rsvd_IPL_MASK)
#define MLB_CECR7_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR7_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR7_MPE_MASK                       0x10000u
#define MLB_CECR7_MPE_SHIFT                      16
#define MLB_CECR7_MDB_MASK                       0x20000u
#define MLB_CECR7_MDB_SHIFT                      17
#define MLB_CECR7_MBD_MASK                       0x40000u
#define MLB_CECR7_MBD_SHIFT                      18
#define MLB_CECR7_MBS_MASK                       0x80000u
#define MLB_CECR7_MBS_SHIFT                      19
#define MLB_CECR7_MBE_MASK                       0x100000u
#define MLB_CECR7_MBE_SHIFT                      20
#define MLB_CECR7_MLFS_MASK                      0x400000u
#define MLB_CECR7_MLFS_SHIFT                     22
#define MLB_CECR7_MDS_MASK                       0x6000000u
#define MLB_CECR7_MDS_SHIFT                      25
#define MLB_CECR7_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR7_MDS_SHIFT))&MLB_CECR7_MDS_MASK)
#define MLB_CECR7_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR7_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR7_CT_MASK                        0x30000000u
#define MLB_CECR7_CT_SHIFT                       28
#define MLB_CECR7_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR7_CT_SHIFT))&MLB_CECR7_CT_MASK)
#define MLB_CECR7_TR_MASK                        0x40000000u
#define MLB_CECR7_TR_SHIFT                       30
#define MLB_CECR7_CE_MASK                        0x80000000u
#define MLB_CECR7_CE_SHIFT                       31
/* CSCR7 Bit Fields */
#define MLB_CSCR7_CBPE_MASK                      0x1u
#define MLB_CSCR7_CBPE_SHIFT                     0
#define MLB_CSCR7_CBDB_MASK                      0x2u
#define MLB_CSCR7_CBDB_SHIFT                     1
#define MLB_CSCR7_CBD_MASK                       0x4u
#define MLB_CSCR7_CBD_SHIFT                      2
#define MLB_CSCR7_CBS_MASK                       0x8u
#define MLB_CSCR7_CBS_SHIFT                      3
#define MLB_CSCR7_BE_MASK                        0x10u
#define MLB_CSCR7_BE_SHIFT                       4
#define MLB_CSCR7_ABE_MASK                       0x20u
#define MLB_CSCR7_ABE_SHIFT                      5
#define MLB_CSCR7_LFS_MASK                       0x40u
#define MLB_CSCR7_LFS_SHIFT                      6
#define MLB_CSCR7_PBPE_MASK                      0x100u
#define MLB_CSCR7_PBPE_SHIFT                     8
#define MLB_CSCR7_PBDB_MASK                      0x200u
#define MLB_CSCR7_PBDB_SHIFT                     9
#define MLB_CSCR7_PBD_MASK                       0x400u
#define MLB_CSCR7_PBD_SHIFT                      10
#define MLB_CSCR7_PBS_MASK                       0x800u
#define MLB_CSCR7_PBS_SHIFT                      11
#define MLB_CSCR7_RDY_MASK                       0x10000u
#define MLB_CSCR7_RDY_SHIFT                      16
#define MLB_CSCR7_GIRB_MASK                      0x20000u
#define MLB_CSCR7_GIRB_SHIFT                     17
#define MLB_CSCR7_IVB_MASK                       0xC0000u
#define MLB_CSCR7_IVB_SHIFT                      18
#define MLB_CSCR7_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR7_IVB_SHIFT))&MLB_CSCR7_IVB_MASK)
#define MLB_CSCR7_BF_MASK                        0x40000000u
#define MLB_CSCR7_BF_SHIFT                       30
#define MLB_CSCR7_BM_MASK                        0x80000000u
#define MLB_CSCR7_BM_SHIFT                       31
/* CCBCR7 Bit Fields */
#define MLB_CCBCR7_BFA0_MASK                     0x3u
#define MLB_CCBCR7_BFA0_SHIFT                    0
#define MLB_CCBCR7_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR7_BFA0_SHIFT))&MLB_CCBCR7_BFA0_MASK)
#define MLB_CCBCR7_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR7_BFA1_SHIFT                    2
#define MLB_CCBCR7_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR7_BFA1_SHIFT))&MLB_CCBCR7_BFA1_MASK)
#define MLB_CCBCR7_BCA0_MASK                     0x30000u
#define MLB_CCBCR7_BCA0_SHIFT                    16
#define MLB_CCBCR7_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR7_BCA0_SHIFT))&MLB_CCBCR7_BCA0_MASK)
#define MLB_CCBCR7_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR7_BCA1_SHIFT                    18
#define MLB_CCBCR7_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR7_BCA1_SHIFT))&MLB_CCBCR7_BCA1_MASK)
/* CNBCR7 Bit Fields */
#define MLB_CNBCR7_BEA_MASK                      0xFFFFu
#define MLB_CNBCR7_BEA_SHIFT                     0
#define MLB_CNBCR7_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR7_BEA_SHIFT))&MLB_CNBCR7_BEA_MASK)
#define MLB_CNBCR7_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR7_BSA_SHIFT                     16
#define MLB_CNBCR7_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR7_BSA_SHIFT))&MLB_CNBCR7_BSA_MASK)
/* CECR8 Bit Fields */
#define MLB_CECR8_CA_MASK                        0xFFu
#define MLB_CECR8_CA_SHIFT                       0
#define MLB_CECR8_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR8_CA_SHIFT))&MLB_CECR8_CA_MASK)
#define MLB_CECR8_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR8_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR8_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR8_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR8_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR8_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR8_Rsvd_IPL_SHIFT                 13
#define MLB_CECR8_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR8_Rsvd_IPL_SHIFT))&MLB_CECR8_Rsvd_IPL_MASK)
#define MLB_CECR8_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR8_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR8_MPE_MASK                       0x10000u
#define MLB_CECR8_MPE_SHIFT                      16
#define MLB_CECR8_MDB_MASK                       0x20000u
#define MLB_CECR8_MDB_SHIFT                      17
#define MLB_CECR8_MBD_MASK                       0x40000u
#define MLB_CECR8_MBD_SHIFT                      18
#define MLB_CECR8_MBS_MASK                       0x80000u
#define MLB_CECR8_MBS_SHIFT                      19
#define MLB_CECR8_MBE_MASK                       0x100000u
#define MLB_CECR8_MBE_SHIFT                      20
#define MLB_CECR8_MLFS_MASK                      0x400000u
#define MLB_CECR8_MLFS_SHIFT                     22
#define MLB_CECR8_MDS_MASK                       0x6000000u
#define MLB_CECR8_MDS_SHIFT                      25
#define MLB_CECR8_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR8_MDS_SHIFT))&MLB_CECR8_MDS_MASK)
#define MLB_CECR8_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR8_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR8_CT_MASK                        0x30000000u
#define MLB_CECR8_CT_SHIFT                       28
#define MLB_CECR8_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR8_CT_SHIFT))&MLB_CECR8_CT_MASK)
#define MLB_CECR8_TR_MASK                        0x40000000u
#define MLB_CECR8_TR_SHIFT                       30
#define MLB_CECR8_CE_MASK                        0x80000000u
#define MLB_CECR8_CE_SHIFT                       31
/* CSCR8 Bit Fields */
#define MLB_CSCR8_CBPE_MASK                      0x1u
#define MLB_CSCR8_CBPE_SHIFT                     0
#define MLB_CSCR8_CBDB_MASK                      0x2u
#define MLB_CSCR8_CBDB_SHIFT                     1
#define MLB_CSCR8_CBD_MASK                       0x4u
#define MLB_CSCR8_CBD_SHIFT                      2
#define MLB_CSCR8_CBS_MASK                       0x8u
#define MLB_CSCR8_CBS_SHIFT                      3
#define MLB_CSCR8_BE_MASK                        0x10u
#define MLB_CSCR8_BE_SHIFT                       4
#define MLB_CSCR8_ABE_MASK                       0x20u
#define MLB_CSCR8_ABE_SHIFT                      5
#define MLB_CSCR8_LFS_MASK                       0x40u
#define MLB_CSCR8_LFS_SHIFT                      6
#define MLB_CSCR8_PBPE_MASK                      0x100u
#define MLB_CSCR8_PBPE_SHIFT                     8
#define MLB_CSCR8_PBDB_MASK                      0x200u
#define MLB_CSCR8_PBDB_SHIFT                     9
#define MLB_CSCR8_PBD_MASK                       0x400u
#define MLB_CSCR8_PBD_SHIFT                      10
#define MLB_CSCR8_PBS_MASK                       0x800u
#define MLB_CSCR8_PBS_SHIFT                      11
#define MLB_CSCR8_RDY_MASK                       0x10000u
#define MLB_CSCR8_RDY_SHIFT                      16
#define MLB_CSCR8_GIRB_MASK                      0x20000u
#define MLB_CSCR8_GIRB_SHIFT                     17
#define MLB_CSCR8_IVB_MASK                       0xC0000u
#define MLB_CSCR8_IVB_SHIFT                      18
#define MLB_CSCR8_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR8_IVB_SHIFT))&MLB_CSCR8_IVB_MASK)
#define MLB_CSCR8_BF_MASK                        0x40000000u
#define MLB_CSCR8_BF_SHIFT                       30
#define MLB_CSCR8_BM_MASK                        0x80000000u
#define MLB_CSCR8_BM_SHIFT                       31
/* CCBCR8 Bit Fields */
#define MLB_CCBCR8_BFA0_MASK                     0x3u
#define MLB_CCBCR8_BFA0_SHIFT                    0
#define MLB_CCBCR8_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR8_BFA0_SHIFT))&MLB_CCBCR8_BFA0_MASK)
#define MLB_CCBCR8_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR8_BFA1_SHIFT                    2
#define MLB_CCBCR8_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR8_BFA1_SHIFT))&MLB_CCBCR8_BFA1_MASK)
#define MLB_CCBCR8_BCA0_MASK                     0x30000u
#define MLB_CCBCR8_BCA0_SHIFT                    16
#define MLB_CCBCR8_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR8_BCA0_SHIFT))&MLB_CCBCR8_BCA0_MASK)
#define MLB_CCBCR8_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR8_BCA1_SHIFT                    18
#define MLB_CCBCR8_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR8_BCA1_SHIFT))&MLB_CCBCR8_BCA1_MASK)
/* CNBCR8 Bit Fields */
#define MLB_CNBCR8_BEA_MASK                      0xFFFFu
#define MLB_CNBCR8_BEA_SHIFT                     0
#define MLB_CNBCR8_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR8_BEA_SHIFT))&MLB_CNBCR8_BEA_MASK)
#define MLB_CNBCR8_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR8_BSA_SHIFT                     16
#define MLB_CNBCR8_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR8_BSA_SHIFT))&MLB_CNBCR8_BSA_MASK)
/* CECR9 Bit Fields */
#define MLB_CECR9_CA_MASK                        0xFFu
#define MLB_CECR9_CA_SHIFT                       0
#define MLB_CECR9_CA(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR9_CA_SHIFT))&MLB_CECR9_CA_MASK)
#define MLB_CECR9_Rsvd_FSPC_IPL_MASK             0x1F00u
#define MLB_CECR9_Rsvd_FSPC_IPL_SHIFT            8
#define MLB_CECR9_Rsvd_FSPC_IPL(x)               (((uint32_t)(((uint32_t)(x))<<MLB_CECR9_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR9_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR9_Rsvd_IPL_MASK                  0x6000u
#define MLB_CECR9_Rsvd_IPL_SHIFT                 13
#define MLB_CECR9_Rsvd_IPL(x)                    (((uint32_t)(((uint32_t)(x))<<MLB_CECR9_Rsvd_IPL_SHIFT))&MLB_CECR9_Rsvd_IPL_MASK)
#define MLB_CECR9_Rsvd_FSCD_IPL_MASK             0x8000u
#define MLB_CECR9_Rsvd_FSCD_IPL_SHIFT            15
#define MLB_CECR9_MPE_MASK                       0x10000u
#define MLB_CECR9_MPE_SHIFT                      16
#define MLB_CECR9_MDB_MASK                       0x20000u
#define MLB_CECR9_MDB_SHIFT                      17
#define MLB_CECR9_MBD_MASK                       0x40000u
#define MLB_CECR9_MBD_SHIFT                      18
#define MLB_CECR9_MBS_MASK                       0x80000u
#define MLB_CECR9_MBS_SHIFT                      19
#define MLB_CECR9_MBE_MASK                       0x100000u
#define MLB_CECR9_MBE_SHIFT                      20
#define MLB_CECR9_MLFS_MASK                      0x400000u
#define MLB_CECR9_MLFS_SHIFT                     22
#define MLB_CECR9_MDS_MASK                       0x6000000u
#define MLB_CECR9_MDS_SHIFT                      25
#define MLB_CECR9_MDS(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR9_MDS_SHIFT))&MLB_CECR9_MDS_MASK)
#define MLB_CECR9_Rsvd_FSE_FCE_MASK              0x8000000u
#define MLB_CECR9_Rsvd_FSE_FCE_SHIFT             27
#define MLB_CECR9_CT_MASK                        0x30000000u
#define MLB_CECR9_CT_SHIFT                       28
#define MLB_CECR9_CT(x)                          (((uint32_t)(((uint32_t)(x))<<MLB_CECR9_CT_SHIFT))&MLB_CECR9_CT_MASK)
#define MLB_CECR9_TR_MASK                        0x40000000u
#define MLB_CECR9_TR_SHIFT                       30
#define MLB_CECR9_CE_MASK                        0x80000000u
#define MLB_CECR9_CE_SHIFT                       31
/* CSCR9 Bit Fields */
#define MLB_CSCR9_CBPE_MASK                      0x1u
#define MLB_CSCR9_CBPE_SHIFT                     0
#define MLB_CSCR9_CBDB_MASK                      0x2u
#define MLB_CSCR9_CBDB_SHIFT                     1
#define MLB_CSCR9_CBD_MASK                       0x4u
#define MLB_CSCR9_CBD_SHIFT                      2
#define MLB_CSCR9_CBS_MASK                       0x8u
#define MLB_CSCR9_CBS_SHIFT                      3
#define MLB_CSCR9_BE_MASK                        0x10u
#define MLB_CSCR9_BE_SHIFT                       4
#define MLB_CSCR9_ABE_MASK                       0x20u
#define MLB_CSCR9_ABE_SHIFT                      5
#define MLB_CSCR9_LFS_MASK                       0x40u
#define MLB_CSCR9_LFS_SHIFT                      6
#define MLB_CSCR9_PBPE_MASK                      0x100u
#define MLB_CSCR9_PBPE_SHIFT                     8
#define MLB_CSCR9_PBDB_MASK                      0x200u
#define MLB_CSCR9_PBDB_SHIFT                     9
#define MLB_CSCR9_PBD_MASK                       0x400u
#define MLB_CSCR9_PBD_SHIFT                      10
#define MLB_CSCR9_PBS_MASK                       0x800u
#define MLB_CSCR9_PBS_SHIFT                      11
#define MLB_CSCR9_RDY_MASK                       0x10000u
#define MLB_CSCR9_RDY_SHIFT                      16
#define MLB_CSCR9_GIRB_MASK                      0x20000u
#define MLB_CSCR9_GIRB_SHIFT                     17
#define MLB_CSCR9_IVB_MASK                       0xC0000u
#define MLB_CSCR9_IVB_SHIFT                      18
#define MLB_CSCR9_IVB(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CSCR9_IVB_SHIFT))&MLB_CSCR9_IVB_MASK)
#define MLB_CSCR9_BF_MASK                        0x40000000u
#define MLB_CSCR9_BF_SHIFT                       30
#define MLB_CSCR9_BM_MASK                        0x80000000u
#define MLB_CSCR9_BM_SHIFT                       31
/* CCBCR9 Bit Fields */
#define MLB_CCBCR9_BFA0_MASK                     0x3u
#define MLB_CCBCR9_BFA0_SHIFT                    0
#define MLB_CCBCR9_BFA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR9_BFA0_SHIFT))&MLB_CCBCR9_BFA0_MASK)
#define MLB_CCBCR9_BFA1_MASK                     0xFFFCu
#define MLB_CCBCR9_BFA1_SHIFT                    2
#define MLB_CCBCR9_BFA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR9_BFA1_SHIFT))&MLB_CCBCR9_BFA1_MASK)
#define MLB_CCBCR9_BCA0_MASK                     0x30000u
#define MLB_CCBCR9_BCA0_SHIFT                    16
#define MLB_CCBCR9_BCA0(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR9_BCA0_SHIFT))&MLB_CCBCR9_BCA0_MASK)
#define MLB_CCBCR9_BCA1_MASK                     0xFFFC0000u
#define MLB_CCBCR9_BCA1_SHIFT                    18
#define MLB_CCBCR9_BCA1(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR9_BCA1_SHIFT))&MLB_CCBCR9_BCA1_MASK)
/* CNBCR9 Bit Fields */
#define MLB_CNBCR9_BEA_MASK                      0xFFFFu
#define MLB_CNBCR9_BEA_SHIFT                     0
#define MLB_CNBCR9_BEA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR9_BEA_SHIFT))&MLB_CNBCR9_BEA_MASK)
#define MLB_CNBCR9_BSA_MASK                      0xFFFF0000u
#define MLB_CNBCR9_BSA_SHIFT                     16
#define MLB_CNBCR9_BSA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR9_BSA_SHIFT))&MLB_CNBCR9_BSA_MASK)
/* CECR10 Bit Fields */
#define MLB_CECR10_CA_MASK                       0xFFu
#define MLB_CECR10_CA_SHIFT                      0
#define MLB_CECR10_CA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR10_CA_SHIFT))&MLB_CECR10_CA_MASK)
#define MLB_CECR10_Rsvd_FSPC_IPL_MASK            0x1F00u
#define MLB_CECR10_Rsvd_FSPC_IPL_SHIFT           8
#define MLB_CECR10_Rsvd_FSPC_IPL(x)              (((uint32_t)(((uint32_t)(x))<<MLB_CECR10_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR10_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR10_Rsvd_IPL_MASK                 0x6000u
#define MLB_CECR10_Rsvd_IPL_SHIFT                13
#define MLB_CECR10_Rsvd_IPL(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_CECR10_Rsvd_IPL_SHIFT))&MLB_CECR10_Rsvd_IPL_MASK)
#define MLB_CECR10_Rsvd_FSCD_IPL_MASK            0x8000u
#define MLB_CECR10_Rsvd_FSCD_IPL_SHIFT           15
#define MLB_CECR10_MPE_MASK                      0x10000u
#define MLB_CECR10_MPE_SHIFT                     16
#define MLB_CECR10_MDB_MASK                      0x20000u
#define MLB_CECR10_MDB_SHIFT                     17
#define MLB_CECR10_MBD_MASK                      0x40000u
#define MLB_CECR10_MBD_SHIFT                     18
#define MLB_CECR10_MBS_MASK                      0x80000u
#define MLB_CECR10_MBS_SHIFT                     19
#define MLB_CECR10_MBE_MASK                      0x100000u
#define MLB_CECR10_MBE_SHIFT                     20
#define MLB_CECR10_MLFS_MASK                     0x400000u
#define MLB_CECR10_MLFS_SHIFT                    22
#define MLB_CECR10_MDS_MASK                      0x6000000u
#define MLB_CECR10_MDS_SHIFT                     25
#define MLB_CECR10_MDS(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CECR10_MDS_SHIFT))&MLB_CECR10_MDS_MASK)
#define MLB_CECR10_Rsvd_FSE_FCE_MASK             0x8000000u
#define MLB_CECR10_Rsvd_FSE_FCE_SHIFT            27
#define MLB_CECR10_CT_MASK                       0x30000000u
#define MLB_CECR10_CT_SHIFT                      28
#define MLB_CECR10_CT(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR10_CT_SHIFT))&MLB_CECR10_CT_MASK)
#define MLB_CECR10_TR_MASK                       0x40000000u
#define MLB_CECR10_TR_SHIFT                      30
#define MLB_CECR10_CE_MASK                       0x80000000u
#define MLB_CECR10_CE_SHIFT                      31
/* CSCR10 Bit Fields */
#define MLB_CSCR10_CBPE_MASK                     0x1u
#define MLB_CSCR10_CBPE_SHIFT                    0
#define MLB_CSCR10_CBDB_MASK                     0x2u
#define MLB_CSCR10_CBDB_SHIFT                    1
#define MLB_CSCR10_CBD_MASK                      0x4u
#define MLB_CSCR10_CBD_SHIFT                     2
#define MLB_CSCR10_CBS_MASK                      0x8u
#define MLB_CSCR10_CBS_SHIFT                     3
#define MLB_CSCR10_BE_MASK                       0x10u
#define MLB_CSCR10_BE_SHIFT                      4
#define MLB_CSCR10_ABE_MASK                      0x20u
#define MLB_CSCR10_ABE_SHIFT                     5
#define MLB_CSCR10_LFS_MASK                      0x40u
#define MLB_CSCR10_LFS_SHIFT                     6
#define MLB_CSCR10_PBPE_MASK                     0x100u
#define MLB_CSCR10_PBPE_SHIFT                    8
#define MLB_CSCR10_PBDB_MASK                     0x200u
#define MLB_CSCR10_PBDB_SHIFT                    9
#define MLB_CSCR10_PBD_MASK                      0x400u
#define MLB_CSCR10_PBD_SHIFT                     10
#define MLB_CSCR10_PBS_MASK                      0x800u
#define MLB_CSCR10_PBS_SHIFT                     11
#define MLB_CSCR10_RDY_MASK                      0x10000u
#define MLB_CSCR10_RDY_SHIFT                     16
#define MLB_CSCR10_GIRB_MASK                     0x20000u
#define MLB_CSCR10_GIRB_SHIFT                    17
#define MLB_CSCR10_IVB_MASK                      0xC0000u
#define MLB_CSCR10_IVB_SHIFT                     18
#define MLB_CSCR10_IVB(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CSCR10_IVB_SHIFT))&MLB_CSCR10_IVB_MASK)
#define MLB_CSCR10_BF_MASK                       0x40000000u
#define MLB_CSCR10_BF_SHIFT                      30
#define MLB_CSCR10_BM_MASK                       0x80000000u
#define MLB_CSCR10_BM_SHIFT                      31
/* CCBCR10 Bit Fields */
#define MLB_CCBCR10_BFA0_MASK                    0x3u
#define MLB_CCBCR10_BFA0_SHIFT                   0
#define MLB_CCBCR10_BFA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR10_BFA0_SHIFT))&MLB_CCBCR10_BFA0_MASK)
#define MLB_CCBCR10_BFA1_MASK                    0xFFFCu
#define MLB_CCBCR10_BFA1_SHIFT                   2
#define MLB_CCBCR10_BFA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR10_BFA1_SHIFT))&MLB_CCBCR10_BFA1_MASK)
#define MLB_CCBCR10_BCA0_MASK                    0x30000u
#define MLB_CCBCR10_BCA0_SHIFT                   16
#define MLB_CCBCR10_BCA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR10_BCA0_SHIFT))&MLB_CCBCR10_BCA0_MASK)
#define MLB_CCBCR10_BCA1_MASK                    0xFFFC0000u
#define MLB_CCBCR10_BCA1_SHIFT                   18
#define MLB_CCBCR10_BCA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR10_BCA1_SHIFT))&MLB_CCBCR10_BCA1_MASK)
/* CNBCR10 Bit Fields */
#define MLB_CNBCR10_BEA_MASK                     0xFFFFu
#define MLB_CNBCR10_BEA_SHIFT                    0
#define MLB_CNBCR10_BEA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR10_BEA_SHIFT))&MLB_CNBCR10_BEA_MASK)
#define MLB_CNBCR10_BSA_MASK                     0xFFFF0000u
#define MLB_CNBCR10_BSA_SHIFT                    16
#define MLB_CNBCR10_BSA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR10_BSA_SHIFT))&MLB_CNBCR10_BSA_MASK)
/* CECR11 Bit Fields */
#define MLB_CECR11_CA_MASK                       0xFFu
#define MLB_CECR11_CA_SHIFT                      0
#define MLB_CECR11_CA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR11_CA_SHIFT))&MLB_CECR11_CA_MASK)
#define MLB_CECR11_Rsvd_FSPC_IPL_MASK            0x1F00u
#define MLB_CECR11_Rsvd_FSPC_IPL_SHIFT           8
#define MLB_CECR11_Rsvd_FSPC_IPL(x)              (((uint32_t)(((uint32_t)(x))<<MLB_CECR11_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR11_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR11_Rsvd_IPL_MASK                 0x6000u
#define MLB_CECR11_Rsvd_IPL_SHIFT                13
#define MLB_CECR11_Rsvd_IPL(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_CECR11_Rsvd_IPL_SHIFT))&MLB_CECR11_Rsvd_IPL_MASK)
#define MLB_CECR11_Rsvd_FSCD_IPL_MASK            0x8000u
#define MLB_CECR11_Rsvd_FSCD_IPL_SHIFT           15
#define MLB_CECR11_MPE_MASK                      0x10000u
#define MLB_CECR11_MPE_SHIFT                     16
#define MLB_CECR11_MDB_MASK                      0x20000u
#define MLB_CECR11_MDB_SHIFT                     17
#define MLB_CECR11_MBD_MASK                      0x40000u
#define MLB_CECR11_MBD_SHIFT                     18
#define MLB_CECR11_MBS_MASK                      0x80000u
#define MLB_CECR11_MBS_SHIFT                     19
#define MLB_CECR11_MBE_MASK                      0x100000u
#define MLB_CECR11_MBE_SHIFT                     20
#define MLB_CECR11_MLFS_MASK                     0x400000u
#define MLB_CECR11_MLFS_SHIFT                    22
#define MLB_CECR11_MDS_MASK                      0x6000000u
#define MLB_CECR11_MDS_SHIFT                     25
#define MLB_CECR11_MDS(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CECR11_MDS_SHIFT))&MLB_CECR11_MDS_MASK)
#define MLB_CECR11_Rsvd_FSE_FCE_MASK             0x8000000u
#define MLB_CECR11_Rsvd_FSE_FCE_SHIFT            27
#define MLB_CECR11_CT_MASK                       0x30000000u
#define MLB_CECR11_CT_SHIFT                      28
#define MLB_CECR11_CT(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR11_CT_SHIFT))&MLB_CECR11_CT_MASK)
#define MLB_CECR11_TR_MASK                       0x40000000u
#define MLB_CECR11_TR_SHIFT                      30
#define MLB_CECR11_CE_MASK                       0x80000000u
#define MLB_CECR11_CE_SHIFT                      31
/* CSCR11 Bit Fields */
#define MLB_CSCR11_CBPE_MASK                     0x1u
#define MLB_CSCR11_CBPE_SHIFT                    0
#define MLB_CSCR11_CBDB_MASK                     0x2u
#define MLB_CSCR11_CBDB_SHIFT                    1
#define MLB_CSCR11_CBD_MASK                      0x4u
#define MLB_CSCR11_CBD_SHIFT                     2
#define MLB_CSCR11_CBS_MASK                      0x8u
#define MLB_CSCR11_CBS_SHIFT                     3
#define MLB_CSCR11_BE_MASK                       0x10u
#define MLB_CSCR11_BE_SHIFT                      4
#define MLB_CSCR11_ABE_MASK                      0x20u
#define MLB_CSCR11_ABE_SHIFT                     5
#define MLB_CSCR11_LFS_MASK                      0x40u
#define MLB_CSCR11_LFS_SHIFT                     6
#define MLB_CSCR11_PBPE_MASK                     0x100u
#define MLB_CSCR11_PBPE_SHIFT                    8
#define MLB_CSCR11_PBDB_MASK                     0x200u
#define MLB_CSCR11_PBDB_SHIFT                    9
#define MLB_CSCR11_PBD_MASK                      0x400u
#define MLB_CSCR11_PBD_SHIFT                     10
#define MLB_CSCR11_PBS_MASK                      0x800u
#define MLB_CSCR11_PBS_SHIFT                     11
#define MLB_CSCR11_RDY_MASK                      0x10000u
#define MLB_CSCR11_RDY_SHIFT                     16
#define MLB_CSCR11_GIRB_MASK                     0x20000u
#define MLB_CSCR11_GIRB_SHIFT                    17
#define MLB_CSCR11_IVB_MASK                      0xC0000u
#define MLB_CSCR11_IVB_SHIFT                     18
#define MLB_CSCR11_IVB(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CSCR11_IVB_SHIFT))&MLB_CSCR11_IVB_MASK)
#define MLB_CSCR11_BF_MASK                       0x40000000u
#define MLB_CSCR11_BF_SHIFT                      30
#define MLB_CSCR11_BM_MASK                       0x80000000u
#define MLB_CSCR11_BM_SHIFT                      31
/* CCBCR11 Bit Fields */
#define MLB_CCBCR11_BFA0_MASK                    0x3u
#define MLB_CCBCR11_BFA0_SHIFT                   0
#define MLB_CCBCR11_BFA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR11_BFA0_SHIFT))&MLB_CCBCR11_BFA0_MASK)
#define MLB_CCBCR11_BFA1_MASK                    0xFFFCu
#define MLB_CCBCR11_BFA1_SHIFT                   2
#define MLB_CCBCR11_BFA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR11_BFA1_SHIFT))&MLB_CCBCR11_BFA1_MASK)
#define MLB_CCBCR11_BCA0_MASK                    0x30000u
#define MLB_CCBCR11_BCA0_SHIFT                   16
#define MLB_CCBCR11_BCA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR11_BCA0_SHIFT))&MLB_CCBCR11_BCA0_MASK)
#define MLB_CCBCR11_BCA1_MASK                    0xFFFC0000u
#define MLB_CCBCR11_BCA1_SHIFT                   18
#define MLB_CCBCR11_BCA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR11_BCA1_SHIFT))&MLB_CCBCR11_BCA1_MASK)
/* CNBCR11 Bit Fields */
#define MLB_CNBCR11_BEA_MASK                     0xFFFFu
#define MLB_CNBCR11_BEA_SHIFT                    0
#define MLB_CNBCR11_BEA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR11_BEA_SHIFT))&MLB_CNBCR11_BEA_MASK)
#define MLB_CNBCR11_BSA_MASK                     0xFFFF0000u
#define MLB_CNBCR11_BSA_SHIFT                    16
#define MLB_CNBCR11_BSA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR11_BSA_SHIFT))&MLB_CNBCR11_BSA_MASK)
/* CECR12 Bit Fields */
#define MLB_CECR12_CA_MASK                       0xFFu
#define MLB_CECR12_CA_SHIFT                      0
#define MLB_CECR12_CA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR12_CA_SHIFT))&MLB_CECR12_CA_MASK)
#define MLB_CECR12_Rsvd_FSPC_IPL_MASK            0x1F00u
#define MLB_CECR12_Rsvd_FSPC_IPL_SHIFT           8
#define MLB_CECR12_Rsvd_FSPC_IPL(x)              (((uint32_t)(((uint32_t)(x))<<MLB_CECR12_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR12_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR12_Rsvd_IPL_MASK                 0x6000u
#define MLB_CECR12_Rsvd_IPL_SHIFT                13
#define MLB_CECR12_Rsvd_IPL(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_CECR12_Rsvd_IPL_SHIFT))&MLB_CECR12_Rsvd_IPL_MASK)
#define MLB_CECR12_Rsvd_FSCD_IPL_MASK            0x8000u
#define MLB_CECR12_Rsvd_FSCD_IPL_SHIFT           15
#define MLB_CECR12_MPE_MASK                      0x10000u
#define MLB_CECR12_MPE_SHIFT                     16
#define MLB_CECR12_MDB_MASK                      0x20000u
#define MLB_CECR12_MDB_SHIFT                     17
#define MLB_CECR12_MBD_MASK                      0x40000u
#define MLB_CECR12_MBD_SHIFT                     18
#define MLB_CECR12_MBS_MASK                      0x80000u
#define MLB_CECR12_MBS_SHIFT                     19
#define MLB_CECR12_MBE_MASK                      0x100000u
#define MLB_CECR12_MBE_SHIFT                     20
#define MLB_CECR12_MLFS_MASK                     0x400000u
#define MLB_CECR12_MLFS_SHIFT                    22
#define MLB_CECR12_MDS_MASK                      0x6000000u
#define MLB_CECR12_MDS_SHIFT                     25
#define MLB_CECR12_MDS(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CECR12_MDS_SHIFT))&MLB_CECR12_MDS_MASK)
#define MLB_CECR12_Rsvd_FSE_FCE_MASK             0x8000000u
#define MLB_CECR12_Rsvd_FSE_FCE_SHIFT            27
#define MLB_CECR12_CT_MASK                       0x30000000u
#define MLB_CECR12_CT_SHIFT                      28
#define MLB_CECR12_CT(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR12_CT_SHIFT))&MLB_CECR12_CT_MASK)
#define MLB_CECR12_TR_MASK                       0x40000000u
#define MLB_CECR12_TR_SHIFT                      30
#define MLB_CECR12_CE_MASK                       0x80000000u
#define MLB_CECR12_CE_SHIFT                      31
/* CSCR12 Bit Fields */
#define MLB_CSCR12_CBPE_MASK                     0x1u
#define MLB_CSCR12_CBPE_SHIFT                    0
#define MLB_CSCR12_CBDB_MASK                     0x2u
#define MLB_CSCR12_CBDB_SHIFT                    1
#define MLB_CSCR12_CBD_MASK                      0x4u
#define MLB_CSCR12_CBD_SHIFT                     2
#define MLB_CSCR12_CBS_MASK                      0x8u
#define MLB_CSCR12_CBS_SHIFT                     3
#define MLB_CSCR12_BE_MASK                       0x10u
#define MLB_CSCR12_BE_SHIFT                      4
#define MLB_CSCR12_ABE_MASK                      0x20u
#define MLB_CSCR12_ABE_SHIFT                     5
#define MLB_CSCR12_LFS_MASK                      0x40u
#define MLB_CSCR12_LFS_SHIFT                     6
#define MLB_CSCR12_PBPE_MASK                     0x100u
#define MLB_CSCR12_PBPE_SHIFT                    8
#define MLB_CSCR12_PBDB_MASK                     0x200u
#define MLB_CSCR12_PBDB_SHIFT                    9
#define MLB_CSCR12_PBD_MASK                      0x400u
#define MLB_CSCR12_PBD_SHIFT                     10
#define MLB_CSCR12_PBS_MASK                      0x800u
#define MLB_CSCR12_PBS_SHIFT                     11
#define MLB_CSCR12_RDY_MASK                      0x10000u
#define MLB_CSCR12_RDY_SHIFT                     16
#define MLB_CSCR12_GIRB_MASK                     0x20000u
#define MLB_CSCR12_GIRB_SHIFT                    17
#define MLB_CSCR12_IVB_MASK                      0xC0000u
#define MLB_CSCR12_IVB_SHIFT                     18
#define MLB_CSCR12_IVB(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CSCR12_IVB_SHIFT))&MLB_CSCR12_IVB_MASK)
#define MLB_CSCR12_BF_MASK                       0x40000000u
#define MLB_CSCR12_BF_SHIFT                      30
#define MLB_CSCR12_BM_MASK                       0x80000000u
#define MLB_CSCR12_BM_SHIFT                      31
/* CCBCR12 Bit Fields */
#define MLB_CCBCR12_BFA0_MASK                    0x3u
#define MLB_CCBCR12_BFA0_SHIFT                   0
#define MLB_CCBCR12_BFA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR12_BFA0_SHIFT))&MLB_CCBCR12_BFA0_MASK)
#define MLB_CCBCR12_BFA1_MASK                    0xFFFCu
#define MLB_CCBCR12_BFA1_SHIFT                   2
#define MLB_CCBCR12_BFA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR12_BFA1_SHIFT))&MLB_CCBCR12_BFA1_MASK)
#define MLB_CCBCR12_BCA0_MASK                    0x30000u
#define MLB_CCBCR12_BCA0_SHIFT                   16
#define MLB_CCBCR12_BCA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR12_BCA0_SHIFT))&MLB_CCBCR12_BCA0_MASK)
#define MLB_CCBCR12_BCA1_MASK                    0xFFFC0000u
#define MLB_CCBCR12_BCA1_SHIFT                   18
#define MLB_CCBCR12_BCA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR12_BCA1_SHIFT))&MLB_CCBCR12_BCA1_MASK)
/* CNBCR12 Bit Fields */
#define MLB_CNBCR12_BEA_MASK                     0xFFFFu
#define MLB_CNBCR12_BEA_SHIFT                    0
#define MLB_CNBCR12_BEA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR12_BEA_SHIFT))&MLB_CNBCR12_BEA_MASK)
#define MLB_CNBCR12_BSA_MASK                     0xFFFF0000u
#define MLB_CNBCR12_BSA_SHIFT                    16
#define MLB_CNBCR12_BSA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR12_BSA_SHIFT))&MLB_CNBCR12_BSA_MASK)
/* CECR13 Bit Fields */
#define MLB_CECR13_CA_MASK                       0xFFu
#define MLB_CECR13_CA_SHIFT                      0
#define MLB_CECR13_CA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR13_CA_SHIFT))&MLB_CECR13_CA_MASK)
#define MLB_CECR13_Rsvd_FSPC_IPL_MASK            0x1F00u
#define MLB_CECR13_Rsvd_FSPC_IPL_SHIFT           8
#define MLB_CECR13_Rsvd_FSPC_IPL(x)              (((uint32_t)(((uint32_t)(x))<<MLB_CECR13_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR13_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR13_Rsvd_IPL_MASK                 0x6000u
#define MLB_CECR13_Rsvd_IPL_SHIFT                13
#define MLB_CECR13_Rsvd_IPL(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_CECR13_Rsvd_IPL_SHIFT))&MLB_CECR13_Rsvd_IPL_MASK)
#define MLB_CECR13_Rsvd_FSCD_IPL_MASK            0x8000u
#define MLB_CECR13_Rsvd_FSCD_IPL_SHIFT           15
#define MLB_CECR13_MPE_MASK                      0x10000u
#define MLB_CECR13_MPE_SHIFT                     16
#define MLB_CECR13_MDB_MASK                      0x20000u
#define MLB_CECR13_MDB_SHIFT                     17
#define MLB_CECR13_MBD_MASK                      0x40000u
#define MLB_CECR13_MBD_SHIFT                     18
#define MLB_CECR13_MBS_MASK                      0x80000u
#define MLB_CECR13_MBS_SHIFT                     19
#define MLB_CECR13_MBE_MASK                      0x100000u
#define MLB_CECR13_MBE_SHIFT                     20
#define MLB_CECR13_MLFS_MASK                     0x400000u
#define MLB_CECR13_MLFS_SHIFT                    22
#define MLB_CECR13_MDS_MASK                      0x6000000u
#define MLB_CECR13_MDS_SHIFT                     25
#define MLB_CECR13_MDS(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CECR13_MDS_SHIFT))&MLB_CECR13_MDS_MASK)
#define MLB_CECR13_Rsvd_FSE_FCE_MASK             0x8000000u
#define MLB_CECR13_Rsvd_FSE_FCE_SHIFT            27
#define MLB_CECR13_CT_MASK                       0x30000000u
#define MLB_CECR13_CT_SHIFT                      28
#define MLB_CECR13_CT(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR13_CT_SHIFT))&MLB_CECR13_CT_MASK)
#define MLB_CECR13_TR_MASK                       0x40000000u
#define MLB_CECR13_TR_SHIFT                      30
#define MLB_CECR13_CE_MASK                       0x80000000u
#define MLB_CECR13_CE_SHIFT                      31
/* CSCR13 Bit Fields */
#define MLB_CSCR13_CBPE_MASK                     0x1u
#define MLB_CSCR13_CBPE_SHIFT                    0
#define MLB_CSCR13_CBDB_MASK                     0x2u
#define MLB_CSCR13_CBDB_SHIFT                    1
#define MLB_CSCR13_CBD_MASK                      0x4u
#define MLB_CSCR13_CBD_SHIFT                     2
#define MLB_CSCR13_CBS_MASK                      0x8u
#define MLB_CSCR13_CBS_SHIFT                     3
#define MLB_CSCR13_BE_MASK                       0x10u
#define MLB_CSCR13_BE_SHIFT                      4
#define MLB_CSCR13_ABE_MASK                      0x20u
#define MLB_CSCR13_ABE_SHIFT                     5
#define MLB_CSCR13_LFS_MASK                      0x40u
#define MLB_CSCR13_LFS_SHIFT                     6
#define MLB_CSCR13_PBPE_MASK                     0x100u
#define MLB_CSCR13_PBPE_SHIFT                    8
#define MLB_CSCR13_PBDB_MASK                     0x200u
#define MLB_CSCR13_PBDB_SHIFT                    9
#define MLB_CSCR13_PBD_MASK                      0x400u
#define MLB_CSCR13_PBD_SHIFT                     10
#define MLB_CSCR13_PBS_MASK                      0x800u
#define MLB_CSCR13_PBS_SHIFT                     11
#define MLB_CSCR13_RDY_MASK                      0x10000u
#define MLB_CSCR13_RDY_SHIFT                     16
#define MLB_CSCR13_GIRB_MASK                     0x20000u
#define MLB_CSCR13_GIRB_SHIFT                    17
#define MLB_CSCR13_IVB_MASK                      0xC0000u
#define MLB_CSCR13_IVB_SHIFT                     18
#define MLB_CSCR13_IVB(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CSCR13_IVB_SHIFT))&MLB_CSCR13_IVB_MASK)
#define MLB_CSCR13_BF_MASK                       0x40000000u
#define MLB_CSCR13_BF_SHIFT                      30
#define MLB_CSCR13_BM_MASK                       0x80000000u
#define MLB_CSCR13_BM_SHIFT                      31
/* CCBCR13 Bit Fields */
#define MLB_CCBCR13_BFA0_MASK                    0x3u
#define MLB_CCBCR13_BFA0_SHIFT                   0
#define MLB_CCBCR13_BFA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR13_BFA0_SHIFT))&MLB_CCBCR13_BFA0_MASK)
#define MLB_CCBCR13_BFA1_MASK                    0xFFFCu
#define MLB_CCBCR13_BFA1_SHIFT                   2
#define MLB_CCBCR13_BFA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR13_BFA1_SHIFT))&MLB_CCBCR13_BFA1_MASK)
#define MLB_CCBCR13_BCA0_MASK                    0x30000u
#define MLB_CCBCR13_BCA0_SHIFT                   16
#define MLB_CCBCR13_BCA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR13_BCA0_SHIFT))&MLB_CCBCR13_BCA0_MASK)
#define MLB_CCBCR13_BCA1_MASK                    0xFFFC0000u
#define MLB_CCBCR13_BCA1_SHIFT                   18
#define MLB_CCBCR13_BCA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR13_BCA1_SHIFT))&MLB_CCBCR13_BCA1_MASK)
/* CNBCR13 Bit Fields */
#define MLB_CNBCR13_BEA_MASK                     0xFFFFu
#define MLB_CNBCR13_BEA_SHIFT                    0
#define MLB_CNBCR13_BEA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR13_BEA_SHIFT))&MLB_CNBCR13_BEA_MASK)
#define MLB_CNBCR13_BSA_MASK                     0xFFFF0000u
#define MLB_CNBCR13_BSA_SHIFT                    16
#define MLB_CNBCR13_BSA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR13_BSA_SHIFT))&MLB_CNBCR13_BSA_MASK)
/* CECR14 Bit Fields */
#define MLB_CECR14_CA_MASK                       0xFFu
#define MLB_CECR14_CA_SHIFT                      0
#define MLB_CECR14_CA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR14_CA_SHIFT))&MLB_CECR14_CA_MASK)
#define MLB_CECR14_Rsvd_FSPC_IPL_MASK            0x1F00u
#define MLB_CECR14_Rsvd_FSPC_IPL_SHIFT           8
#define MLB_CECR14_Rsvd_FSPC_IPL(x)              (((uint32_t)(((uint32_t)(x))<<MLB_CECR14_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR14_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR14_Rsvd_IPL_MASK                 0x6000u
#define MLB_CECR14_Rsvd_IPL_SHIFT                13
#define MLB_CECR14_Rsvd_IPL(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_CECR14_Rsvd_IPL_SHIFT))&MLB_CECR14_Rsvd_IPL_MASK)
#define MLB_CECR14_Rsvd_FSCD_IPL_MASK            0x8000u
#define MLB_CECR14_Rsvd_FSCD_IPL_SHIFT           15
#define MLB_CECR14_MPE_MASK                      0x10000u
#define MLB_CECR14_MPE_SHIFT                     16
#define MLB_CECR14_MDB_MASK                      0x20000u
#define MLB_CECR14_MDB_SHIFT                     17
#define MLB_CECR14_MBD_MASK                      0x40000u
#define MLB_CECR14_MBD_SHIFT                     18
#define MLB_CECR14_MBS_MASK                      0x80000u
#define MLB_CECR14_MBS_SHIFT                     19
#define MLB_CECR14_MBE_MASK                      0x100000u
#define MLB_CECR14_MBE_SHIFT                     20
#define MLB_CECR14_MLFS_MASK                     0x400000u
#define MLB_CECR14_MLFS_SHIFT                    22
#define MLB_CECR14_MDS_MASK                      0x6000000u
#define MLB_CECR14_MDS_SHIFT                     25
#define MLB_CECR14_MDS(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CECR14_MDS_SHIFT))&MLB_CECR14_MDS_MASK)
#define MLB_CECR14_Rsvd_FSE_FCE_MASK             0x8000000u
#define MLB_CECR14_Rsvd_FSE_FCE_SHIFT            27
#define MLB_CECR14_CT_MASK                       0x30000000u
#define MLB_CECR14_CT_SHIFT                      28
#define MLB_CECR14_CT(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR14_CT_SHIFT))&MLB_CECR14_CT_MASK)
#define MLB_CECR14_TR_MASK                       0x40000000u
#define MLB_CECR14_TR_SHIFT                      30
#define MLB_CECR14_CE_MASK                       0x80000000u
#define MLB_CECR14_CE_SHIFT                      31
/* CSCR14 Bit Fields */
#define MLB_CSCR14_CBPE_MASK                     0x1u
#define MLB_CSCR14_CBPE_SHIFT                    0
#define MLB_CSCR14_CBDB_MASK                     0x2u
#define MLB_CSCR14_CBDB_SHIFT                    1
#define MLB_CSCR14_CBD_MASK                      0x4u
#define MLB_CSCR14_CBD_SHIFT                     2
#define MLB_CSCR14_CBS_MASK                      0x8u
#define MLB_CSCR14_CBS_SHIFT                     3
#define MLB_CSCR14_BE_MASK                       0x10u
#define MLB_CSCR14_BE_SHIFT                      4
#define MLB_CSCR14_ABE_MASK                      0x20u
#define MLB_CSCR14_ABE_SHIFT                     5
#define MLB_CSCR14_LFS_MASK                      0x40u
#define MLB_CSCR14_LFS_SHIFT                     6
#define MLB_CSCR14_PBPE_MASK                     0x100u
#define MLB_CSCR14_PBPE_SHIFT                    8
#define MLB_CSCR14_PBDB_MASK                     0x200u
#define MLB_CSCR14_PBDB_SHIFT                    9
#define MLB_CSCR14_PBD_MASK                      0x400u
#define MLB_CSCR14_PBD_SHIFT                     10
#define MLB_CSCR14_PBS_MASK                      0x800u
#define MLB_CSCR14_PBS_SHIFT                     11
#define MLB_CSCR14_RDY_MASK                      0x10000u
#define MLB_CSCR14_RDY_SHIFT                     16
#define MLB_CSCR14_GIRB_MASK                     0x20000u
#define MLB_CSCR14_GIRB_SHIFT                    17
#define MLB_CSCR14_IVB_MASK                      0xC0000u
#define MLB_CSCR14_IVB_SHIFT                     18
#define MLB_CSCR14_IVB(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CSCR14_IVB_SHIFT))&MLB_CSCR14_IVB_MASK)
#define MLB_CSCR14_BF_MASK                       0x40000000u
#define MLB_CSCR14_BF_SHIFT                      30
#define MLB_CSCR14_BM_MASK                       0x80000000u
#define MLB_CSCR14_BM_SHIFT                      31
/* CCBCR14 Bit Fields */
#define MLB_CCBCR14_BFA0_MASK                    0x3u
#define MLB_CCBCR14_BFA0_SHIFT                   0
#define MLB_CCBCR14_BFA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR14_BFA0_SHIFT))&MLB_CCBCR14_BFA0_MASK)
#define MLB_CCBCR14_BFA1_MASK                    0xFFFCu
#define MLB_CCBCR14_BFA1_SHIFT                   2
#define MLB_CCBCR14_BFA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR14_BFA1_SHIFT))&MLB_CCBCR14_BFA1_MASK)
#define MLB_CCBCR14_BCA0_MASK                    0x30000u
#define MLB_CCBCR14_BCA0_SHIFT                   16
#define MLB_CCBCR14_BCA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR14_BCA0_SHIFT))&MLB_CCBCR14_BCA0_MASK)
#define MLB_CCBCR14_BCA1_MASK                    0xFFFC0000u
#define MLB_CCBCR14_BCA1_SHIFT                   18
#define MLB_CCBCR14_BCA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR14_BCA1_SHIFT))&MLB_CCBCR14_BCA1_MASK)
/* CNBCR14 Bit Fields */
#define MLB_CNBCR14_BEA_MASK                     0xFFFFu
#define MLB_CNBCR14_BEA_SHIFT                    0
#define MLB_CNBCR14_BEA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR14_BEA_SHIFT))&MLB_CNBCR14_BEA_MASK)
#define MLB_CNBCR14_BSA_MASK                     0xFFFF0000u
#define MLB_CNBCR14_BSA_SHIFT                    16
#define MLB_CNBCR14_BSA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR14_BSA_SHIFT))&MLB_CNBCR14_BSA_MASK)
/* CECR15 Bit Fields */
#define MLB_CECR15_CA_MASK                       0xFFu
#define MLB_CECR15_CA_SHIFT                      0
#define MLB_CECR15_CA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR15_CA_SHIFT))&MLB_CECR15_CA_MASK)
#define MLB_CECR15_Rsvd_FSPC_IPL_MASK            0x1F00u
#define MLB_CECR15_Rsvd_FSPC_IPL_SHIFT           8
#define MLB_CECR15_Rsvd_FSPC_IPL(x)              (((uint32_t)(((uint32_t)(x))<<MLB_CECR15_Rsvd_FSPC_IPL_SHIFT))&MLB_CECR15_Rsvd_FSPC_IPL_MASK)
#define MLB_CECR15_Rsvd_IPL_MASK                 0x6000u
#define MLB_CECR15_Rsvd_IPL_SHIFT                13
#define MLB_CECR15_Rsvd_IPL(x)                   (((uint32_t)(((uint32_t)(x))<<MLB_CECR15_Rsvd_IPL_SHIFT))&MLB_CECR15_Rsvd_IPL_MASK)
#define MLB_CECR15_Rsvd_FSCD_IPL_MASK            0x8000u
#define MLB_CECR15_Rsvd_FSCD_IPL_SHIFT           15
#define MLB_CECR15_MPE_MASK                      0x10000u
#define MLB_CECR15_MPE_SHIFT                     16
#define MLB_CECR15_MDB_MASK                      0x20000u
#define MLB_CECR15_MDB_SHIFT                     17
#define MLB_CECR15_MBD_MASK                      0x40000u
#define MLB_CECR15_MBD_SHIFT                     18
#define MLB_CECR15_MBS_MASK                      0x80000u
#define MLB_CECR15_MBS_SHIFT                     19
#define MLB_CECR15_MBE_MASK                      0x100000u
#define MLB_CECR15_MBE_SHIFT                     20
#define MLB_CECR15_MLFS_MASK                     0x400000u
#define MLB_CECR15_MLFS_SHIFT                    22
#define MLB_CECR15_MDS_MASK                      0x6000000u
#define MLB_CECR15_MDS_SHIFT                     25
#define MLB_CECR15_MDS(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CECR15_MDS_SHIFT))&MLB_CECR15_MDS_MASK)
#define MLB_CECR15_Rsvd_FSE_FCE_MASK             0x8000000u
#define MLB_CECR15_Rsvd_FSE_FCE_SHIFT            27
#define MLB_CECR15_CT_MASK                       0x30000000u
#define MLB_CECR15_CT_SHIFT                      28
#define MLB_CECR15_CT(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_CECR15_CT_SHIFT))&MLB_CECR15_CT_MASK)
#define MLB_CECR15_TR_MASK                       0x40000000u
#define MLB_CECR15_TR_SHIFT                      30
#define MLB_CECR15_CE_MASK                       0x80000000u
#define MLB_CECR15_CE_SHIFT                      31
/* CSCR15 Bit Fields */
#define MLB_CSCR15_CBPE_MASK                     0x1u
#define MLB_CSCR15_CBPE_SHIFT                    0
#define MLB_CSCR15_CBDB_MASK                     0x2u
#define MLB_CSCR15_CBDB_SHIFT                    1
#define MLB_CSCR15_CBD_MASK                      0x4u
#define MLB_CSCR15_CBD_SHIFT                     2
#define MLB_CSCR15_CBS_MASK                      0x8u
#define MLB_CSCR15_CBS_SHIFT                     3
#define MLB_CSCR15_BE_MASK                       0x10u
#define MLB_CSCR15_BE_SHIFT                      4
#define MLB_CSCR15_ABE_MASK                      0x20u
#define MLB_CSCR15_ABE_SHIFT                     5
#define MLB_CSCR15_LFS_MASK                      0x40u
#define MLB_CSCR15_LFS_SHIFT                     6
#define MLB_CSCR15_PBPE_MASK                     0x100u
#define MLB_CSCR15_PBPE_SHIFT                    8
#define MLB_CSCR15_PBDB_MASK                     0x200u
#define MLB_CSCR15_PBDB_SHIFT                    9
#define MLB_CSCR15_PBD_MASK                      0x400u
#define MLB_CSCR15_PBD_SHIFT                     10
#define MLB_CSCR15_PBS_MASK                      0x800u
#define MLB_CSCR15_PBS_SHIFT                     11
#define MLB_CSCR15_RDY_MASK                      0x10000u
#define MLB_CSCR15_RDY_SHIFT                     16
#define MLB_CSCR15_GIRB_MASK                     0x20000u
#define MLB_CSCR15_GIRB_SHIFT                    17
#define MLB_CSCR15_IVB_MASK                      0xC0000u
#define MLB_CSCR15_IVB_SHIFT                     18
#define MLB_CSCR15_IVB(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_CSCR15_IVB_SHIFT))&MLB_CSCR15_IVB_MASK)
#define MLB_CSCR15_BF_MASK                       0x40000000u
#define MLB_CSCR15_BF_SHIFT                      30
#define MLB_CSCR15_BM_MASK                       0x80000000u
#define MLB_CSCR15_BM_SHIFT                      31
/* CCBCR15 Bit Fields */
#define MLB_CCBCR15_BFA0_MASK                    0x3u
#define MLB_CCBCR15_BFA0_SHIFT                   0
#define MLB_CCBCR15_BFA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR15_BFA0_SHIFT))&MLB_CCBCR15_BFA0_MASK)
#define MLB_CCBCR15_BFA1_MASK                    0xFFFCu
#define MLB_CCBCR15_BFA1_SHIFT                   2
#define MLB_CCBCR15_BFA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR15_BFA1_SHIFT))&MLB_CCBCR15_BFA1_MASK)
#define MLB_CCBCR15_BCA0_MASK                    0x30000u
#define MLB_CCBCR15_BCA0_SHIFT                   16
#define MLB_CCBCR15_BCA0(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR15_BCA0_SHIFT))&MLB_CCBCR15_BCA0_MASK)
#define MLB_CCBCR15_BCA1_MASK                    0xFFFC0000u
#define MLB_CCBCR15_BCA1_SHIFT                   18
#define MLB_CCBCR15_BCA1(x)                      (((uint32_t)(((uint32_t)(x))<<MLB_CCBCR15_BCA1_SHIFT))&MLB_CCBCR15_BCA1_MASK)
/* CNBCR15 Bit Fields */
#define MLB_CNBCR15_BEA_MASK                     0xFFFFu
#define MLB_CNBCR15_BEA_SHIFT                    0
#define MLB_CNBCR15_BEA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR15_BEA_SHIFT))&MLB_CNBCR15_BEA_MASK)
#define MLB_CNBCR15_BSA_MASK                     0xFFFF0000u
#define MLB_CNBCR15_BSA_SHIFT                    16
#define MLB_CNBCR15_BSA(x)                       (((uint32_t)(((uint32_t)(x))<<MLB_CNBCR15_BSA_SHIFT))&MLB_CNBCR15_BSA_MASK)
/* LCBCR0 Bit Fields */
#define MLB_LCBCR0_SA_MASK                       0x1FFu
#define MLB_LCBCR0_SA_SHIFT                      0
#define MLB_LCBCR0_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR0_SA_SHIFT))&MLB_LCBCR0_SA_MASK)
#define MLB_LCBCR0_BD_MASK                       0xFE000u
#define MLB_LCBCR0_BD_SHIFT                      13
#define MLB_LCBCR0_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR0_BD_SHIFT))&MLB_LCBCR0_BD_MASK)
#define MLB_LCBCR0_TH_MASK                       0x3FC00000u
#define MLB_LCBCR0_TH_SHIFT                      22
#define MLB_LCBCR0_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR0_TH_SHIFT))&MLB_LCBCR0_TH_MASK)
/* LCBCR1 Bit Fields */
#define MLB_LCBCR1_SA_MASK                       0x1FFu
#define MLB_LCBCR1_SA_SHIFT                      0
#define MLB_LCBCR1_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR1_SA_SHIFT))&MLB_LCBCR1_SA_MASK)
#define MLB_LCBCR1_BD_MASK                       0xFE000u
#define MLB_LCBCR1_BD_SHIFT                      13
#define MLB_LCBCR1_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR1_BD_SHIFT))&MLB_LCBCR1_BD_MASK)
#define MLB_LCBCR1_TH_MASK                       0x3FC00000u
#define MLB_LCBCR1_TH_SHIFT                      22
#define MLB_LCBCR1_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR1_TH_SHIFT))&MLB_LCBCR1_TH_MASK)
/* LCBCR2 Bit Fields */
#define MLB_LCBCR2_SA_MASK                       0x1FFu
#define MLB_LCBCR2_SA_SHIFT                      0
#define MLB_LCBCR2_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR2_SA_SHIFT))&MLB_LCBCR2_SA_MASK)
#define MLB_LCBCR2_BD_MASK                       0xFE000u
#define MLB_LCBCR2_BD_SHIFT                      13
#define MLB_LCBCR2_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR2_BD_SHIFT))&MLB_LCBCR2_BD_MASK)
#define MLB_LCBCR2_TH_MASK                       0x3FC00000u
#define MLB_LCBCR2_TH_SHIFT                      22
#define MLB_LCBCR2_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR2_TH_SHIFT))&MLB_LCBCR2_TH_MASK)
/* LCBCR3 Bit Fields */
#define MLB_LCBCR3_SA_MASK                       0x1FFu
#define MLB_LCBCR3_SA_SHIFT                      0
#define MLB_LCBCR3_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR3_SA_SHIFT))&MLB_LCBCR3_SA_MASK)
#define MLB_LCBCR3_BD_MASK                       0xFE000u
#define MLB_LCBCR3_BD_SHIFT                      13
#define MLB_LCBCR3_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR3_BD_SHIFT))&MLB_LCBCR3_BD_MASK)
#define MLB_LCBCR3_TH_MASK                       0x3FC00000u
#define MLB_LCBCR3_TH_SHIFT                      22
#define MLB_LCBCR3_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR3_TH_SHIFT))&MLB_LCBCR3_TH_MASK)
/* LCBCR4 Bit Fields */
#define MLB_LCBCR4_SA_MASK                       0x1FFu
#define MLB_LCBCR4_SA_SHIFT                      0
#define MLB_LCBCR4_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR4_SA_SHIFT))&MLB_LCBCR4_SA_MASK)
#define MLB_LCBCR4_BD_MASK                       0xFE000u
#define MLB_LCBCR4_BD_SHIFT                      13
#define MLB_LCBCR4_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR4_BD_SHIFT))&MLB_LCBCR4_BD_MASK)
#define MLB_LCBCR4_TH_MASK                       0x3FC00000u
#define MLB_LCBCR4_TH_SHIFT                      22
#define MLB_LCBCR4_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR4_TH_SHIFT))&MLB_LCBCR4_TH_MASK)
/* LCBCR5 Bit Fields */
#define MLB_LCBCR5_SA_MASK                       0x1FFu
#define MLB_LCBCR5_SA_SHIFT                      0
#define MLB_LCBCR5_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR5_SA_SHIFT))&MLB_LCBCR5_SA_MASK)
#define MLB_LCBCR5_BD_MASK                       0xFE000u
#define MLB_LCBCR5_BD_SHIFT                      13
#define MLB_LCBCR5_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR5_BD_SHIFT))&MLB_LCBCR5_BD_MASK)
#define MLB_LCBCR5_TH_MASK                       0x3FC00000u
#define MLB_LCBCR5_TH_SHIFT                      22
#define MLB_LCBCR5_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR5_TH_SHIFT))&MLB_LCBCR5_TH_MASK)
/* LCBCR6 Bit Fields */
#define MLB_LCBCR6_SA_MASK                       0x1FFu
#define MLB_LCBCR6_SA_SHIFT                      0
#define MLB_LCBCR6_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR6_SA_SHIFT))&MLB_LCBCR6_SA_MASK)
#define MLB_LCBCR6_BD_MASK                       0xFE000u
#define MLB_LCBCR6_BD_SHIFT                      13
#define MLB_LCBCR6_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR6_BD_SHIFT))&MLB_LCBCR6_BD_MASK)
#define MLB_LCBCR6_TH_MASK                       0x3FC00000u
#define MLB_LCBCR6_TH_SHIFT                      22
#define MLB_LCBCR6_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR6_TH_SHIFT))&MLB_LCBCR6_TH_MASK)
/* LCBCR7 Bit Fields */
#define MLB_LCBCR7_SA_MASK                       0x1FFu
#define MLB_LCBCR7_SA_SHIFT                      0
#define MLB_LCBCR7_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR7_SA_SHIFT))&MLB_LCBCR7_SA_MASK)
#define MLB_LCBCR7_BD_MASK                       0xFE000u
#define MLB_LCBCR7_BD_SHIFT                      13
#define MLB_LCBCR7_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR7_BD_SHIFT))&MLB_LCBCR7_BD_MASK)
#define MLB_LCBCR7_TH_MASK                       0x3FC00000u
#define MLB_LCBCR7_TH_SHIFT                      22
#define MLB_LCBCR7_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR7_TH_SHIFT))&MLB_LCBCR7_TH_MASK)
/* LCBCR8 Bit Fields */
#define MLB_LCBCR8_SA_MASK                       0x1FFu
#define MLB_LCBCR8_SA_SHIFT                      0
#define MLB_LCBCR8_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR8_SA_SHIFT))&MLB_LCBCR8_SA_MASK)
#define MLB_LCBCR8_BD_MASK                       0xFE000u
#define MLB_LCBCR8_BD_SHIFT                      13
#define MLB_LCBCR8_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR8_BD_SHIFT))&MLB_LCBCR8_BD_MASK)
#define MLB_LCBCR8_TH_MASK                       0x3FC00000u
#define MLB_LCBCR8_TH_SHIFT                      22
#define MLB_LCBCR8_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR8_TH_SHIFT))&MLB_LCBCR8_TH_MASK)
/* LCBCR9 Bit Fields */
#define MLB_LCBCR9_SA_MASK                       0x1FFu
#define MLB_LCBCR9_SA_SHIFT                      0
#define MLB_LCBCR9_SA(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR9_SA_SHIFT))&MLB_LCBCR9_SA_MASK)
#define MLB_LCBCR9_BD_MASK                       0xFE000u
#define MLB_LCBCR9_BD_SHIFT                      13
#define MLB_LCBCR9_BD(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR9_BD_SHIFT))&MLB_LCBCR9_BD_MASK)
#define MLB_LCBCR9_TH_MASK                       0x3FC00000u
#define MLB_LCBCR9_TH_SHIFT                      22
#define MLB_LCBCR9_TH(x)                         (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR9_TH_SHIFT))&MLB_LCBCR9_TH_MASK)
/* LCBCR10 Bit Fields */
#define MLB_LCBCR10_SA_MASK                      0x1FFu
#define MLB_LCBCR10_SA_SHIFT                     0
#define MLB_LCBCR10_SA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR10_SA_SHIFT))&MLB_LCBCR10_SA_MASK)
#define MLB_LCBCR10_BD_MASK                      0xFE000u
#define MLB_LCBCR10_BD_SHIFT                     13
#define MLB_LCBCR10_BD(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR10_BD_SHIFT))&MLB_LCBCR10_BD_MASK)
#define MLB_LCBCR10_TH_MASK                      0x3FC00000u
#define MLB_LCBCR10_TH_SHIFT                     22
#define MLB_LCBCR10_TH(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR10_TH_SHIFT))&MLB_LCBCR10_TH_MASK)
/* LCBCR11 Bit Fields */
#define MLB_LCBCR11_SA_MASK                      0x1FFu
#define MLB_LCBCR11_SA_SHIFT                     0
#define MLB_LCBCR11_SA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR11_SA_SHIFT))&MLB_LCBCR11_SA_MASK)
#define MLB_LCBCR11_BD_MASK                      0xFE000u
#define MLB_LCBCR11_BD_SHIFT                     13
#define MLB_LCBCR11_BD(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR11_BD_SHIFT))&MLB_LCBCR11_BD_MASK)
#define MLB_LCBCR11_TH_MASK                      0x3FC00000u
#define MLB_LCBCR11_TH_SHIFT                     22
#define MLB_LCBCR11_TH(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR11_TH_SHIFT))&MLB_LCBCR11_TH_MASK)
/* LCBCR12 Bit Fields */
#define MLB_LCBCR12_SA_MASK                      0x1FFu
#define MLB_LCBCR12_SA_SHIFT                     0
#define MLB_LCBCR12_SA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR12_SA_SHIFT))&MLB_LCBCR12_SA_MASK)
#define MLB_LCBCR12_BD_MASK                      0xFE000u
#define MLB_LCBCR12_BD_SHIFT                     13
#define MLB_LCBCR12_BD(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR12_BD_SHIFT))&MLB_LCBCR12_BD_MASK)
#define MLB_LCBCR12_TH_MASK                      0x3FC00000u
#define MLB_LCBCR12_TH_SHIFT                     22
#define MLB_LCBCR12_TH(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR12_TH_SHIFT))&MLB_LCBCR12_TH_MASK)
/* LCBCR13 Bit Fields */
#define MLB_LCBCR13_SA_MASK                      0x1FFu
#define MLB_LCBCR13_SA_SHIFT                     0
#define MLB_LCBCR13_SA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR13_SA_SHIFT))&MLB_LCBCR13_SA_MASK)
#define MLB_LCBCR13_BD_MASK                      0xFE000u
#define MLB_LCBCR13_BD_SHIFT                     13
#define MLB_LCBCR13_BD(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR13_BD_SHIFT))&MLB_LCBCR13_BD_MASK)
#define MLB_LCBCR13_TH_MASK                      0x3FC00000u
#define MLB_LCBCR13_TH_SHIFT                     22
#define MLB_LCBCR13_TH(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR13_TH_SHIFT))&MLB_LCBCR13_TH_MASK)
/* LCBCR14 Bit Fields */
#define MLB_LCBCR14_SA_MASK                      0x1FFu
#define MLB_LCBCR14_SA_SHIFT                     0
#define MLB_LCBCR14_SA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR14_SA_SHIFT))&MLB_LCBCR14_SA_MASK)
#define MLB_LCBCR14_BD_MASK                      0xFE000u
#define MLB_LCBCR14_BD_SHIFT                     13
#define MLB_LCBCR14_BD(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR14_BD_SHIFT))&MLB_LCBCR14_BD_MASK)
#define MLB_LCBCR14_TH_MASK                      0x3FC00000u
#define MLB_LCBCR14_TH_SHIFT                     22
#define MLB_LCBCR14_TH(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR14_TH_SHIFT))&MLB_LCBCR14_TH_MASK)
/* LCBCR15 Bit Fields */
#define MLB_LCBCR15_SA_MASK                      0x1FFu
#define MLB_LCBCR15_SA_SHIFT                     0
#define MLB_LCBCR15_SA(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR15_SA_SHIFT))&MLB_LCBCR15_SA_MASK)
#define MLB_LCBCR15_BD_MASK                      0xFE000u
#define MLB_LCBCR15_BD_SHIFT                     13
#define MLB_LCBCR15_BD(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR15_BD_SHIFT))&MLB_LCBCR15_BD_MASK)
#define MLB_LCBCR15_TH_MASK                      0x3FC00000u
#define MLB_LCBCR15_TH_SHIFT                     22
#define MLB_LCBCR15_TH(x)                        (((uint32_t)(((uint32_t)(x))<<MLB_LCBCR15_TH_SHIFT))&MLB_LCBCR15_TH_MASK)

/**
 * @}
 */ /* end of group MLB_Register_Masks */


/* MLB - Peripheral instance base addresses */
/** Peripheral MLB base address */
#define MLB_BASE                                 (0x40043000u)
/** Peripheral MLB base pointer */
#define MLB                                      ((MLB_Type *)MLB_BASE)
/** Array initializer of MLB peripheral base pointers */
#define MLB_BASES                                { MLB }

/**
 * @}
 */ /* end of group MLB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MSCM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer
 * @{
 */

/** MSCM - Register Layout Typedef */
typedef struct {
  __I  uint32_t CPxTYPE;                           /**< Processor X Type Register, offset: 0x0 */
  __I  uint32_t CPxNUM;                            /**< Processor X Number Register, offset: 0x4 */
  __I  uint32_t CPxMASTER;                         /**< Processor X Master Register, offset: 0x8 */
  __I  uint32_t CPxCOUNT;                          /**< Processor X Count Register, offset: 0xC */
  __I  uint32_t CPxCFG[4];                         /**< Processor X Configuration Register, array offset: 0x10, array step: 0x4 */
  __I  uint32_t CP0TYPE;                           /**< Processor 0 Type Register, offset: 0x20 */
  __I  uint32_t CP0NUM;                            /**< Processor 0 Number Register, offset: 0x24 */
  __I  uint32_t CP0MASTER;                         /**< Processor 0 Master Register, offset: 0x28 */
  __I  uint32_t CP0COUNT;                          /**< Processor 0 Count Register, offset: 0x2C */
  __I  uint32_t CP0CFG[4];                         /**< Processor 0 Configuration Register, array offset: 0x30, array step: 0x4 */
  __I  uint32_t CP1TYPE;                           /**< Processor 1 Type Register, offset: 0x40 */
  __I  uint32_t CP1NUM;                            /**< Processor 1 Number Register, offset: 0x44 */
  __I  uint32_t CP1MASTER;                         /**< Processor 1 Master Register, offset: 0x48 */
  __I  uint32_t CP1COUNT;                          /**< Processor 1 Count Register, offset: 0x4C */
  __I  uint32_t CP1CFG[4];                         /**< Processor 1 Configuration Register, array offset: 0x50, array step: 0x4 */
       uint8_t RESERVED_0[1952];
  __IO uint32_t IRCP0IR;                           /**< Interrupt Router CP0 Interrupt Register, offset: 0x800 */
  __IO uint32_t IRCP1IR;                           /**< Interrupt Router CP1 Interrupt Register, offset: 0x804 */
       uint8_t RESERVED_1[24];
  __O  uint32_t IRCPGIR;                           /**< Interrupt Router CPU Generate Interrupt Register, offset: 0x820 */
       uint8_t RESERVED_2[92];
  __IO uint16_t IRSPRC[112];                       /**< Interrupt Router Shared Peripheral Routing Control Register n, array offset: 0x880, array step: 0x2 */
       uint8_t RESERVED_3[672];
  __IO uint32_t TZENR;                             /**< ACTZS TrustZone Enable Register, offset: 0xC00 */
  __I  uint32_t TZIR;                              /**< ACTZS TrustZone Interrupt Register, offset: 0xC04 */
       uint8_t RESERVED_4[8];
  __IO uint32_t CSLIER;                            /**< ACTZS CSLn Interrupt Enable Register, offset: 0xC10 */
  __IO uint32_t CSLIR;                             /**< ACTZS CSLn Interrupt Register, offset: 0xC14 */
  __I  uint32_t CSOVR;                             /**< ACTZS CSLn Interrupt Overrun Register, offset: 0xC18 */
       uint8_t RESERVED_5[228];
  struct {                                         /* offset: 0xD00, array step: 0x10 */
    __I  uint32_t CSFAR;                             /**< ACTZS CSLn Fail Status Address (Low) Register, array offset: 0xD00, array step: 0x10 */
         uint8_t RESERVED_0[4];
    __I  uint32_t CSFCR;                             /**< ACTZS CSLn Fail Status Control Register, array offset: 0xD08, array step: 0x10 */
    __I  uint32_t CSFIR;                             /**< ACTZS CSLn Fail Status Master ID Register, array offset: 0xD0C, array step: 0x10 */
  } CSFCAP[14];
} MSCM_Type;

/* ----------------------------------------------------------------------------
   -- MSCM Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup MSCM_Register_Masks MSCM Register Masks
 * @{
 */

/* CPxTYPE Bit Fields */
#define MSCM_CPxTYPE_rYpZ_MASK                   0xFFu
#define MSCM_CPxTYPE_rYpZ_SHIFT                  0
#define MSCM_CPxTYPE_rYpZ(x)                     (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_rYpZ_SHIFT))&MSCM_CPxTYPE_rYpZ_MASK)
#define MSCM_CPxTYPE_Personality_MASK            0xFFFFFF00u
#define MSCM_CPxTYPE_Personality_SHIFT           8
#define MSCM_CPxTYPE_Personality(x)              (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_Personality_SHIFT))&MSCM_CPxTYPE_Personality_MASK)
/* CPxNUM Bit Fields */
#define MSCM_CPxNUM_CPN_MASK                     0x1u
#define MSCM_CPxNUM_CPN_SHIFT                    0
/* CPxMASTER Bit Fields */
#define MSCM_CPxMASTER_PPN_MASK                  0x1Fu
#define MSCM_CPxMASTER_PPN_SHIFT                 0
#define MSCM_CPxMASTER_PPN(x)                    (((uint32_t)(((uint32_t)(x))<<MSCM_CPxMASTER_PPN_SHIFT))&MSCM_CPxMASTER_PPN_MASK)
/* CPxCOUNT Bit Fields */
#define MSCM_CPxCOUNT_PCNT_MASK                  0x1u
#define MSCM_CPxCOUNT_PCNT_SHIFT                 0
/* CPxCFG Bit Fields */
#define MSCM_CPxCFG_DCWY_MASK                    0xFFu
#define MSCM_CPxCFG_DCWY_SHIFT                   0
#define MSCM_CPxCFG_DCWY(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_DCWY_SHIFT))&MSCM_CPxCFG_DCWY_MASK)
#define MSCM_CPxCFG_DCSZ_MASK                    0xFF00u
#define MSCM_CPxCFG_DCSZ_SHIFT                   8
#define MSCM_CPxCFG_DCSZ(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_DCSZ_SHIFT))&MSCM_CPxCFG_DCSZ_MASK)
#define MSCM_CPxCFG_ICWY_MASK                    0xFF0000u
#define MSCM_CPxCFG_ICWY_SHIFT                   16
#define MSCM_CPxCFG_ICWY(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_ICWY_SHIFT))&MSCM_CPxCFG_ICWY_MASK)
#define MSCM_CPxCFG_ICSZ_MASK                    0xFF000000u
#define MSCM_CPxCFG_ICSZ_SHIFT                   24
#define MSCM_CPxCFG_ICSZ(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG_ICSZ_SHIFT))&MSCM_CPxCFG_ICSZ_MASK)
/* CP0TYPE Bit Fields */
#define MSCM_CP0TYPE_rYpZ_MASK                   0xFFu
#define MSCM_CP0TYPE_rYpZ_SHIFT                  0
#define MSCM_CP0TYPE_rYpZ(x)                     (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_rYpZ_SHIFT))&MSCM_CP0TYPE_rYpZ_MASK)
#define MSCM_CP0TYPE_Personality_MASK            0xFFFFFF00u
#define MSCM_CP0TYPE_Personality_SHIFT           8
#define MSCM_CP0TYPE_Personality(x)              (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_Personality_SHIFT))&MSCM_CP0TYPE_Personality_MASK)
/* CP0NUM Bit Fields */
#define MSCM_CP0NUM_CPN_MASK                     0x1u
#define MSCM_CP0NUM_CPN_SHIFT                    0
/* CP0MASTER Bit Fields */
#define MSCM_CP0MASTER_PPN_MASK                  0x1Fu
#define MSCM_CP0MASTER_PPN_SHIFT                 0
#define MSCM_CP0MASTER_PPN(x)                    (((uint32_t)(((uint32_t)(x))<<MSCM_CP0MASTER_PPN_SHIFT))&MSCM_CP0MASTER_PPN_MASK)
/* CP0COUNT Bit Fields */
#define MSCM_CP0COUNT_PCNT_MASK                  0x1u
#define MSCM_CP0COUNT_PCNT_SHIFT                 0
/* CP0CFG Bit Fields */
#define MSCM_CP0CFG_DCWY_MASK                    0xFFu
#define MSCM_CP0CFG_DCWY_SHIFT                   0
#define MSCM_CP0CFG_DCWY(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_DCWY_SHIFT))&MSCM_CP0CFG_DCWY_MASK)
#define MSCM_CP0CFG_DCSZ_MASK                    0xFF00u
#define MSCM_CP0CFG_DCSZ_SHIFT                   8
#define MSCM_CP0CFG_DCSZ(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_DCSZ_SHIFT))&MSCM_CP0CFG_DCSZ_MASK)
#define MSCM_CP0CFG_ICWY_MASK                    0xFF0000u
#define MSCM_CP0CFG_ICWY_SHIFT                   16
#define MSCM_CP0CFG_ICWY(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_ICWY_SHIFT))&MSCM_CP0CFG_ICWY_MASK)
#define MSCM_CP0CFG_ICSZ_MASK                    0xFF000000u
#define MSCM_CP0CFG_ICSZ_SHIFT                   24
#define MSCM_CP0CFG_ICSZ(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG_ICSZ_SHIFT))&MSCM_CP0CFG_ICSZ_MASK)
/* CP1TYPE Bit Fields */
#define MSCM_CP1TYPE_rYpZ_MASK                   0xFFu
#define MSCM_CP1TYPE_rYpZ_SHIFT                  0
#define MSCM_CP1TYPE_rYpZ(x)                     (((uint32_t)(((uint32_t)(x))<<MSCM_CP1TYPE_rYpZ_SHIFT))&MSCM_CP1TYPE_rYpZ_MASK)
#define MSCM_CP1TYPE_Personality_MASK            0xFFFFFF00u
#define MSCM_CP1TYPE_Personality_SHIFT           8
#define MSCM_CP1TYPE_Personality(x)              (((uint32_t)(((uint32_t)(x))<<MSCM_CP1TYPE_Personality_SHIFT))&MSCM_CP1TYPE_Personality_MASK)
/* CP1NUM Bit Fields */
#define MSCM_CP1NUM_CPN_MASK                     0x1u
#define MSCM_CP1NUM_CPN_SHIFT                    0
/* CP1MASTER Bit Fields */
#define MSCM_CP1MASTER_PPN_MASK                  0x1Fu
#define MSCM_CP1MASTER_PPN_SHIFT                 0
#define MSCM_CP1MASTER_PPN(x)                    (((uint32_t)(((uint32_t)(x))<<MSCM_CP1MASTER_PPN_SHIFT))&MSCM_CP1MASTER_PPN_MASK)
/* CP1COUNT Bit Fields */
#define MSCM_CP1COUNT_PCNT_MASK                  0x1u
#define MSCM_CP1COUNT_PCNT_SHIFT                 0
/* CP1CFG Bit Fields */
#define MSCM_CP1CFG_DCWY_MASK                    0xFFu
#define MSCM_CP1CFG_DCWY_SHIFT                   0
#define MSCM_CP1CFG_DCWY(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP1CFG_DCWY_SHIFT))&MSCM_CP1CFG_DCWY_MASK)
#define MSCM_CP1CFG_DCSZ_MASK                    0xFF00u
#define MSCM_CP1CFG_DCSZ_SHIFT                   8
#define MSCM_CP1CFG_DCSZ(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP1CFG_DCSZ_SHIFT))&MSCM_CP1CFG_DCSZ_MASK)
#define MSCM_CP1CFG_ICWY_MASK                    0xFF0000u
#define MSCM_CP1CFG_ICWY_SHIFT                   16
#define MSCM_CP1CFG_ICWY(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP1CFG_ICWY_SHIFT))&MSCM_CP1CFG_ICWY_MASK)
#define MSCM_CP1CFG_ICSZ_MASK                    0xFF000000u
#define MSCM_CP1CFG_ICSZ_SHIFT                   24
#define MSCM_CP1CFG_ICSZ(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_CP1CFG_ICSZ_SHIFT))&MSCM_CP1CFG_ICSZ_MASK)
/* IRCP0IR Bit Fields */
#define MSCM_IRCP0IR_INT0_MASK                   0x1u
#define MSCM_IRCP0IR_INT0_SHIFT                  0
#define MSCM_IRCP0IR_INT1_MASK                   0x2u
#define MSCM_IRCP0IR_INT1_SHIFT                  1
#define MSCM_IRCP0IR_INT2_MASK                   0x4u
#define MSCM_IRCP0IR_INT2_SHIFT                  2
#define MSCM_IRCP0IR_INT3_MASK                   0x8u
#define MSCM_IRCP0IR_INT3_SHIFT                  3
/* IRCP1IR Bit Fields */
#define MSCM_IRCP1IR_INT0_MASK                   0x1u
#define MSCM_IRCP1IR_INT0_SHIFT                  0
#define MSCM_IRCP1IR_INT1_MASK                   0x2u
#define MSCM_IRCP1IR_INT1_SHIFT                  1
#define MSCM_IRCP1IR_INT2_MASK                   0x4u
#define MSCM_IRCP1IR_INT2_SHIFT                  2
#define MSCM_IRCP1IR_INT3_MASK                   0x8u
#define MSCM_IRCP1IR_INT3_SHIFT                  3
/* IRCPGIR Bit Fields */
#define MSCM_IRCPGIR_INTID_MASK                  0x3u
#define MSCM_IRCPGIR_INTID_SHIFT                 0
#define MSCM_IRCPGIR_INTID(x)                    (((uint32_t)(((uint32_t)(x))<<MSCM_IRCPGIR_INTID_SHIFT))&MSCM_IRCPGIR_INTID_MASK)
#define MSCM_IRCPGIR_CPUTL_MASK                  0x30000u
#define MSCM_IRCPGIR_CPUTL_SHIFT                 16
#define MSCM_IRCPGIR_CPUTL(x)                    (((uint32_t)(((uint32_t)(x))<<MSCM_IRCPGIR_CPUTL_SHIFT))&MSCM_IRCPGIR_CPUTL_MASK)
#define MSCM_IRCPGIR_TLF_MASK                    0x3000000u
#define MSCM_IRCPGIR_TLF_SHIFT                   24
#define MSCM_IRCPGIR_TLF(x)                      (((uint32_t)(((uint32_t)(x))<<MSCM_IRCPGIR_TLF_SHIFT))&MSCM_IRCPGIR_TLF_MASK)
/* IRSPRC Bit Fields */
#define MSCM_IRSPRC_CP0En_MASK                   0x1u
#define MSCM_IRSPRC_CP0En_SHIFT                  0
#define MSCM_IRSPRC_CP1En_MASK                   0x2u
#define MSCM_IRSPRC_CP1En_SHIFT                  1
#define MSCM_IRSPRC_RO_MASK                      0x8000u
#define MSCM_IRSPRC_RO_SHIFT                     15
/* TZENR Bit Fields */
#define MSCM_TZENR_TZEN1_MASK                    0x2u
#define MSCM_TZENR_TZEN1_SHIFT                   1
#define MSCM_TZENR_TZEN3_MASK                    0x8u
#define MSCM_TZENR_TZEN3_SHIFT                   3
#define MSCM_TZENR_TZEN4_MASK                    0x10u
#define MSCM_TZENR_TZEN4_SHIFT                   4
#define MSCM_TZENR_TZEN5_MASK                    0x20u
#define MSCM_TZENR_TZEN5_SHIFT                   5
#define MSCM_TZENR_TZEN6_MASK                    0x40u
#define MSCM_TZENR_TZEN6_SHIFT                   6
#define MSCM_TZENR_TZEN7_MASK                    0x80u
#define MSCM_TZENR_TZEN7_SHIFT                   7
#define MSCM_TZENR_TZEN9_MASK                    0x200u
#define MSCM_TZENR_TZEN9_SHIFT                   9
#define MSCM_TZENR_TZEN11_MASK                   0x800u
#define MSCM_TZENR_TZEN11_SHIFT                  11
#define MSCM_TZENR_SBL_MASK                      0x10000000u
#define MSCM_TZENR_SBL_SHIFT                     28
#define MSCM_TZENR_RO_MASK                       0x80000000u
#define MSCM_TZENR_RO_SHIFT                      31
/* TZIR Bit Fields */
#define MSCM_TZIR_TZINT1_MASK                    0x2u
#define MSCM_TZIR_TZINT1_SHIFT                   1
#define MSCM_TZIR_TZINT3_MASK                    0x8u
#define MSCM_TZIR_TZINT3_SHIFT                   3
#define MSCM_TZIR_TZINT4_MASK                    0x10u
#define MSCM_TZIR_TZINT4_SHIFT                   4
#define MSCM_TZIR_TZINT5_MASK                    0x20u
#define MSCM_TZIR_TZINT5_SHIFT                   5
#define MSCM_TZIR_TZINT6_MASK                    0x40u
#define MSCM_TZIR_TZINT6_SHIFT                   6
#define MSCM_TZIR_TZINT7_MASK                    0x80u
#define MSCM_TZIR_TZINT7_SHIFT                   7
#define MSCM_TZIR_TZINT9_MASK                    0x200u
#define MSCM_TZIR_TZINT9_SHIFT                   9
#define MSCM_TZIR_TZINT11_MASK                   0x800u
#define MSCM_TZIR_TZINT11_SHIFT                  11
/* CSLIER Bit Fields */
#define MSCM_CSLIER_CIE0_MASK                    0x1u
#define MSCM_CSLIER_CIE0_SHIFT                   0
#define MSCM_CSLIER_CIE1_MASK                    0x2u
#define MSCM_CSLIER_CIE1_SHIFT                   1
#define MSCM_CSLIER_CIE2_MASK                    0x4u
#define MSCM_CSLIER_CIE2_SHIFT                   2
#define MSCM_CSLIER_CIE3_MASK                    0x8u
#define MSCM_CSLIER_CIE3_SHIFT                   3
#define MSCM_CSLIER_CIE4_MASK                    0x10u
#define MSCM_CSLIER_CIE4_SHIFT                   4
#define MSCM_CSLIER_CIE8_MASK                    0x100u
#define MSCM_CSLIER_CIE8_SHIFT                   8
#define MSCM_CSLIER_CIE9_MASK                    0x200u
#define MSCM_CSLIER_CIE9_SHIFT                   9
#define MSCM_CSLIER_CIE10_MASK                   0x400u
#define MSCM_CSLIER_CIE10_SHIFT                  10
#define MSCM_CSLIER_CIE12_MASK                   0x1000u
#define MSCM_CSLIER_CIE12_SHIFT                  12
#define MSCM_CSLIER_CIE13_MASK                   0x2000u
#define MSCM_CSLIER_CIE13_SHIFT                  13
#define MSCM_CSLIER_RO_MASK                      0x80000000u
#define MSCM_CSLIER_RO_SHIFT                     31
/* CSLIR Bit Fields */
#define MSCM_CSLIR_INT0_MASK                     0x1u
#define MSCM_CSLIR_INT0_SHIFT                    0
#define MSCM_CSLIR_INT1_MASK                     0x2u
#define MSCM_CSLIR_INT1_SHIFT                    1
#define MSCM_CSLIR_INT2_MASK                     0x4u
#define MSCM_CSLIR_INT2_SHIFT                    2
#define MSCM_CSLIR_INT3_MASK                     0x8u
#define MSCM_CSLIR_INT3_SHIFT                    3
#define MSCM_CSLIR_INT4_MASK                     0x10u
#define MSCM_CSLIR_INT4_SHIFT                    4
#define MSCM_CSLIR_INT8_MASK                     0x100u
#define MSCM_CSLIR_INT8_SHIFT                    8
#define MSCM_CSLIR_INT9_MASK                     0x200u
#define MSCM_CSLIR_INT9_SHIFT                    9
#define MSCM_CSLIR_INT10_MASK                    0x400u
#define MSCM_CSLIR_INT10_SHIFT                   10
#define MSCM_CSLIR_INT12_MASK                    0x1000u
#define MSCM_CSLIR_INT12_SHIFT                   12
#define MSCM_CSLIR_INT13_MASK                    0x2000u
#define MSCM_CSLIR_INT13_SHIFT                   13
/* CSOVR Bit Fields */
#define MSCM_CSOVR_OVR0_MASK                     0x1u
#define MSCM_CSOVR_OVR0_SHIFT                    0
#define MSCM_CSOVR_OVR1_MASK                     0x2u
#define MSCM_CSOVR_OVR1_SHIFT                    1
#define MSCM_CSOVR_OVR2_MASK                     0x4u
#define MSCM_CSOVR_OVR2_SHIFT                    2
#define MSCM_CSOVR_OVR3_MASK                     0x8u
#define MSCM_CSOVR_OVR3_SHIFT                    3
#define MSCM_CSOVR_OVR4_MASK                     0x10u
#define MSCM_CSOVR_OVR4_SHIFT                    4
#define MSCM_CSOVR_OVR8_MASK                     0x100u
#define MSCM_CSOVR_OVR8_SHIFT                    8
#define MSCM_CSOVR_OVR9_MASK                     0x200u
#define MSCM_CSOVR_OVR9_SHIFT                    9
#define MSCM_CSOVR_OVR10_MASK                    0x400u
#define MSCM_CSOVR_OVR10_SHIFT                   10
#define MSCM_CSOVR_OVR12_MASK                    0x1000u
#define MSCM_CSOVR_OVR12_SHIFT                   12
#define MSCM_CSOVR_OVR13_MASK                    0x2000u
#define MSCM_CSOVR_OVR13_SHIFT                   13
/* CSFAR Bit Fields */
#define MSCM_CSFAR_FAD_MASK                      0xFFFFFFFFu
#define MSCM_CSFAR_FAD_SHIFT                     0
#define MSCM_CSFAR_FAD(x)                        (((uint32_t)(((uint32_t)(x))<<MSCM_CSFAR_FAD_SHIFT))&MSCM_CSFAR_FAD_MASK)
/* CSFCR Bit Fields */
#define MSCM_CSFCR_FPR_MASK                      0x100000u
#define MSCM_CSFCR_FPR_SHIFT                     20
#define MSCM_CSFCR_FNS_MASK                      0x200000u
#define MSCM_CSFCR_FNS_SHIFT                     21
#define MSCM_CSFCR_FWT_MASK                      0x1000000u
#define MSCM_CSFCR_FWT_SHIFT                     24
/* CSFIR Bit Fields */
#define MSCM_CSFIR_FMID_MASK                     0x1Fu
#define MSCM_CSFIR_FMID_SHIFT                    0
#define MSCM_CSFIR_FMID(x)                       (((uint32_t)(((uint32_t)(x))<<MSCM_CSFIR_FMID_SHIFT))&MSCM_CSFIR_FMID_MASK)

/**
 * @}
 */ /* end of group MSCM_Register_Masks */


/* MSCM - Peripheral instance base addresses */
/** Peripheral MSCM base address */
#define MSCM_BASE                                (0x40001000u)
/** Peripheral MSCM base pointer */
#define MSCM                                     ((MSCM_Type *)MSCM_BASE)
/** Array initializer of MSCM peripheral base pointers */
#define MSCM_BASES                               { MSCM }

/**
 * @}
 */ /* end of group MSCM_Peripheral_Access_Layer */

/* SYSTEM CONTROLLER RAM BASE*/ 

#define OCRAM_BASE		(0x40001400u)

/* ----------------------------------------------------------------------------
   -- NFC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup NFC_Peripheral_Access_Layer NFC Peripheral Access Layer
 * @{
 */

/** NFC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16128];
  __IO uint32_t CMD1;                              /**< Flash command 1, offset: 0x3F00 */
  __IO uint32_t CMD2;                              /**< Flash command 2, offset: 0x3F04 */
  __IO uint32_t CAR;                               /**< Column address, offset: 0x3F08 */
  __IO uint32_t RAR;                               /**< Row address, offset: 0x3F0C */
  __IO uint32_t RPT;                               /**< Flash command repeat, offset: 0x3F10 */
  __IO uint32_t RAI;                               /**< Row address increment, offset: 0x3F14 */
  __I  uint32_t SR1;                               /**< Flash status 1, offset: 0x3F18 */
  __I  uint32_t SR2;                               /**< Flash status 2, offset: 0x3F1C */
  __IO uint32_t DMA_CH1;                           /**< DMA channel 1 address, offset: 0x3F20 */
  __IO uint32_t DMACFG;                            /**< DMA configuration, offset: 0x3F24 */
  __IO uint32_t SWAP;                              /**< Cach swap, offset: 0x3F28 */
  __IO uint32_t SECSZ;                             /**< Sector size, offset: 0x3F2C */
  __IO uint32_t CFG;                               /**< Flash configuration, offset: 0x3F30 */
  __IO uint32_t DMA_CH2;                           /**< DMA channel 2 address, offset: 0x3F34 */
  __IO uint32_t ISR;                               /**< Interrupt status, offset: 0x3F38 */
} NFC_Type;

/* ----------------------------------------------------------------------------
   -- NFC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup NFC_Register_Masks NFC Register Masks
 * @{
 */

/* CMD1 Bit Fields */
#define NFC_CMD1_BYTE3_MASK                      0xFF0000u
#define NFC_CMD1_BYTE3_SHIFT                     16
#define NFC_CMD1_BYTE3(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_CMD1_BYTE3_SHIFT))&NFC_CMD1_BYTE3_MASK)
#define NFC_CMD1_BYTE2_MASK                      0xFF000000u
#define NFC_CMD1_BYTE2_SHIFT                     24
#define NFC_CMD1_BYTE2(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_CMD1_BYTE2_SHIFT))&NFC_CMD1_BYTE2_MASK)
/* CMD2 Bit Fields */
#define NFC_CMD2_BUSY_START_MASK                 0x1u
#define NFC_CMD2_BUSY_START_SHIFT                0
#define NFC_CMD2_BUFNO_MASK                      0x6u
#define NFC_CMD2_BUFNO_SHIFT                     1
#define NFC_CMD2_BUFNO(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_CMD2_BUFNO_SHIFT))&NFC_CMD2_BUFNO_MASK)
#define NFC_CMD2_CODE_MASK                       0xFFFF00u
#define NFC_CMD2_CODE_SHIFT                      8
#define NFC_CMD2_CODE(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_CMD2_CODE_SHIFT))&NFC_CMD2_CODE_MASK)
#define NFC_CMD2_BYTE1_MASK                      0xFF000000u
#define NFC_CMD2_BYTE1_SHIFT                     24
#define NFC_CMD2_BYTE1(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_CMD2_BYTE1_SHIFT))&NFC_CMD2_BYTE1_MASK)
/* CAR Bit Fields */
#define NFC_CAR_BYTE1_MASK                       0xFFu
#define NFC_CAR_BYTE1_SHIFT                      0
#define NFC_CAR_BYTE1(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_CAR_BYTE1_SHIFT))&NFC_CAR_BYTE1_MASK)
#define NFC_CAR_BYTE2_MASK                       0xFF00u
#define NFC_CAR_BYTE2_SHIFT                      8
#define NFC_CAR_BYTE2(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_CAR_BYTE2_SHIFT))&NFC_CAR_BYTE2_MASK)
/* RAR Bit Fields */
#define NFC_RAR_BYTE1_MASK                       0xFFu
#define NFC_RAR_BYTE1_SHIFT                      0
#define NFC_RAR_BYTE1(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_RAR_BYTE1_SHIFT))&NFC_RAR_BYTE1_MASK)
#define NFC_RAR_BYTE2_MASK                       0xFF00u
#define NFC_RAR_BYTE2_SHIFT                      8
#define NFC_RAR_BYTE2(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_RAR_BYTE2_SHIFT))&NFC_RAR_BYTE2_MASK)
#define NFC_RAR_BYTE3_MASK                       0xFF0000u
#define NFC_RAR_BYTE3_SHIFT                      16
#define NFC_RAR_BYTE3(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_RAR_BYTE3_SHIFT))&NFC_RAR_BYTE3_MASK)
#define NFC_RAR_CS0_MASK                         0x1000000u
#define NFC_RAR_CS0_SHIFT                        24
#define NFC_RAR_CS1_MASK                         0x2000000u
#define NFC_RAR_CS1_SHIFT                        25
#define NFC_RAR_RB0_MASK                         0x10000000u
#define NFC_RAR_RB0_SHIFT                        28
/* RPT Bit Fields */
#define NFC_RPT_COUNT_MASK                       0xFFFFu
#define NFC_RPT_COUNT_SHIFT                      0
#define NFC_RPT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_RPT_COUNT_SHIFT))&NFC_RPT_COUNT_MASK)
/* RAI Bit Fields */
#define NFC_RAI_INC1_MASK                        0xFFu
#define NFC_RAI_INC1_SHIFT                       0
#define NFC_RAI_INC1(x)                          (((uint32_t)(((uint32_t)(x))<<NFC_RAI_INC1_SHIFT))&NFC_RAI_INC1_MASK)
#define NFC_RAI_INC2_MASK                        0xFF00u
#define NFC_RAI_INC2_SHIFT                       8
#define NFC_RAI_INC2(x)                          (((uint32_t)(((uint32_t)(x))<<NFC_RAI_INC2_SHIFT))&NFC_RAI_INC2_MASK)
#define NFC_RAI_INC3_MASK                        0xFF0000u
#define NFC_RAI_INC3_SHIFT                       16
#define NFC_RAI_INC3(x)                          (((uint32_t)(((uint32_t)(x))<<NFC_RAI_INC3_SHIFT))&NFC_RAI_INC3_MASK)
/* SR1 Bit Fields */
#define NFC_SR1_ID4_MASK                         0xFFu
#define NFC_SR1_ID4_SHIFT                        0
#define NFC_SR1_ID4(x)                           (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID4_SHIFT))&NFC_SR1_ID4_MASK)
#define NFC_SR1_ID3_MASK                         0xFF00u
#define NFC_SR1_ID3_SHIFT                        8
#define NFC_SR1_ID3(x)                           (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID3_SHIFT))&NFC_SR1_ID3_MASK)
#define NFC_SR1_ID2_MASK                         0xFF0000u
#define NFC_SR1_ID2_SHIFT                        16
#define NFC_SR1_ID2(x)                           (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID2_SHIFT))&NFC_SR1_ID2_MASK)
#define NFC_SR1_ID1_MASK                         0xFF000000u
#define NFC_SR1_ID1_SHIFT                        24
#define NFC_SR1_ID1(x)                           (((uint32_t)(((uint32_t)(x))<<NFC_SR1_ID1_SHIFT))&NFC_SR1_ID1_MASK)
/* SR2 Bit Fields */
#define NFC_SR2_STATUS1_MASK                     0xFFu
#define NFC_SR2_STATUS1_SHIFT                    0
#define NFC_SR2_STATUS1(x)                       (((uint32_t)(((uint32_t)(x))<<NFC_SR2_STATUS1_SHIFT))&NFC_SR2_STATUS1_MASK)
#define NFC_SR2_ID5_MASK                         0xFF000000u
#define NFC_SR2_ID5_SHIFT                        24
#define NFC_SR2_ID5(x)                           (((uint32_t)(((uint32_t)(x))<<NFC_SR2_ID5_SHIFT))&NFC_SR2_ID5_MASK)
/* DMA_CH1 Bit Fields */
#define NFC_DMA_CH1_ADDRESS_MASK                 0xFFFFFFFFu
#define NFC_DMA_CH1_ADDRESS_SHIFT                0
#define NFC_DMA_CH1_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x))<<NFC_DMA_CH1_ADDRESS_SHIFT))&NFC_DMA_CH1_ADDRESS_MASK)
/* DMACFG Bit Fields */
#define NFC_DMACFG_ACT2_MASK                     0x1u
#define NFC_DMACFG_ACT2_SHIFT                    0
#define NFC_DMACFG_ACT1_MASK                     0x2u
#define NFC_DMACFG_ACT1_SHIFT                    1
#define NFC_DMACFG_OFFSET2_MASK                  0x1E00u
#define NFC_DMACFG_OFFSET2_SHIFT                 9
#define NFC_DMACFG_OFFSET2(x)                    (((uint32_t)(((uint32_t)(x))<<NFC_DMACFG_OFFSET2_SHIFT))&NFC_DMACFG_OFFSET2_MASK)
#define NFC_DMACFG_COUNT2_MASK                   0xFE000u
#define NFC_DMACFG_COUNT2_SHIFT                  13
#define NFC_DMACFG_COUNT2(x)                     (((uint32_t)(((uint32_t)(x))<<NFC_DMACFG_COUNT2_SHIFT))&NFC_DMACFG_COUNT2_MASK)
#define NFC_DMACFG_COUNT1_MASK                   0xFFF00000u
#define NFC_DMACFG_COUNT1_SHIFT                  20
#define NFC_DMACFG_COUNT1(x)                     (((uint32_t)(((uint32_t)(x))<<NFC_DMACFG_COUNT1_SHIFT))&NFC_DMACFG_COUNT1_MASK)
/* SWAP Bit Fields */
#define NFC_SWAP_ADDR2_MASK                      0xFFEu
#define NFC_SWAP_ADDR2_SHIFT                     1
#define NFC_SWAP_ADDR2(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_SWAP_ADDR2_SHIFT))&NFC_SWAP_ADDR2_MASK)
#define NFC_SWAP_ADDR1_MASK                      0xFFE0000u
#define NFC_SWAP_ADDR1_SHIFT                     17
#define NFC_SWAP_ADDR1(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_SWAP_ADDR1_SHIFT))&NFC_SWAP_ADDR1_MASK)
/* SECSZ Bit Fields */
#define NFC_SECSZ_SIZE_MASK                      0x1FFFu
#define NFC_SECSZ_SIZE_SHIFT                     0
#define NFC_SECSZ_SIZE(x)                        (((uint32_t)(((uint32_t)(x))<<NFC_SECSZ_SIZE_SHIFT))&NFC_SECSZ_SIZE_MASK)
/* CFG Bit Fields */
#define NFC_CFG_PAGECNT_MASK                     0xFu
#define NFC_CFG_PAGECNT_SHIFT                    0
#define NFC_CFG_PAGECNT(x)                       (((uint32_t)(((uint32_t)(x))<<NFC_CFG_PAGECNT_SHIFT))&NFC_CFG_PAGECNT_MASK)
#define NFC_CFG_AIBN_MASK                        0x10u
#define NFC_CFG_AIBN_SHIFT                       4
#define NFC_CFG_AIAD_MASK                        0x20u
#define NFC_CFG_AIAD_SHIFT                       5
#define NFC_CFG_BTMD_MASK                        0x40u
#define NFC_CFG_BTMD_SHIFT                       6
#define NFC_CFG_BITWIDTH_MASK                    0x80u
#define NFC_CFG_BITWIDTH_SHIFT                   7
#define NFC_CFG_TIMEOUT_MASK                     0x1F00u
#define NFC_CFG_TIMEOUT_SHIFT                    8
#define NFC_CFG_TIMEOUT(x)                       (((uint32_t)(((uint32_t)(x))<<NFC_CFG_TIMEOUT_SHIFT))&NFC_CFG_TIMEOUT_MASK)
#define NFC_CFG_IDCNT_MASK                       0xE000u
#define NFC_CFG_IDCNT_SHIFT                      13
#define NFC_CFG_IDCNT(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_CFG_IDCNT_SHIFT))&NFC_CFG_IDCNT_MASK)
#define NFC_CFG_FAST_MASK                        0x10000u
#define NFC_CFG_FAST_SHIFT                       16
#define NFC_CFG_ECCMODE_MASK                     0xE0000u
#define NFC_CFG_ECCMODE_SHIFT                    17
#define NFC_CFG_ECCMODE(x)                       (((uint32_t)(((uint32_t)(x))<<NFC_CFG_ECCMODE_SHIFT))&NFC_CFG_ECCMODE_MASK)
#define NFC_CFG_DMAREQ_MASK                      0x100000u
#define NFC_CFG_DMAREQ_SHIFT                     20
#define NFC_CFG_ECCSRAM_MASK                     0x200000u
#define NFC_CFG_ECCSRAM_SHIFT                    21
#define NFC_CFG_ECCAD_MASK                       0x7FC00000u
#define NFC_CFG_ECCAD_SHIFT                      22
#define NFC_CFG_ECCAD(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_CFG_ECCAD_SHIFT))&NFC_CFG_ECCAD_MASK)
#define NFC_CFG_STOPWERR_MASK                    0x80000000u
#define NFC_CFG_STOPWERR_SHIFT                   31
/* DMA_CH2 Bit Fields */
#define NFC_DMA_CH2_ADDRESS_MASK                 0xFFFFFFFFu
#define NFC_DMA_CH2_ADDRESS_SHIFT                0
#define NFC_DMA_CH2_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x))<<NFC_DMA_CH2_ADDRESS_SHIFT))&NFC_DMA_CH2_ADDRESS_MASK)
/* ISR Bit Fields */
#define NFC_ISR_DMABN_MASK                       0x3u
#define NFC_ISR_DMABN_SHIFT                      0
#define NFC_ISR_DMABN(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_ISR_DMABN_SHIFT))&NFC_ISR_DMABN_MASK)
#define NFC_ISR_ECCBN_MASK                       0xCu
#define NFC_ISR_ECCBN_SHIFT                      2
#define NFC_ISR_ECCBN(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_ISR_ECCBN_SHIFT))&NFC_ISR_ECCBN_MASK)
#define NFC_ISR_RESBN_MASK                       0x30u
#define NFC_ISR_RESBN_SHIFT                      4
#define NFC_ISR_RESBN(x)                         (((uint32_t)(((uint32_t)(x))<<NFC_ISR_RESBN_SHIFT))&NFC_ISR_RESBN_MASK)
#define NFC_ISR_IDLECLR_MASK                     0x20000u
#define NFC_ISR_IDLECLR_SHIFT                    17
#define NFC_ISR_DONECLR_MASK                     0x40000u
#define NFC_ISR_DONECLR_SHIFT                    18
#define NFC_ISR_WERRCLR_MASK                     0x80000u
#define NFC_ISR_WERRCLR_SHIFT                    19
#define NFC_ISR_IDLEEN_MASK                      0x100000u
#define NFC_ISR_IDLEEN_SHIFT                     20
#define NFC_ISR_DONEEN_MASK                      0x200000u
#define NFC_ISR_DONEEN_SHIFT                     21
#define NFC_ISR_WERREN_MASK                      0x400000u
#define NFC_ISR_WERREN_SHIFT                     22
#define NFC_ISR_DMABUSY_MASK                     0x800000u
#define NFC_ISR_DMABUSY_SHIFT                    23
#define NFC_ISR_ECCBUSY_MASK                     0x1000000u
#define NFC_ISR_ECCBUSY_SHIFT                    24
#define NFC_ISR_RESBUSY_MASK                     0x2000000u
#define NFC_ISR_RESBUSY_SHIFT                    25
#define NFC_ISR_CMDBUSY_MASK                     0x4000000u
#define NFC_ISR_CMDBUSY_SHIFT                    26
#define NFC_ISR_WERRNS_MASK                      0x8000000u
#define NFC_ISR_WERRNS_SHIFT                     27
#define NFC_ISR_IDLE_MASK                        0x20000000u
#define NFC_ISR_IDLE_SHIFT                       29
#define NFC_ISR_DONE_MASK                        0x40000000u
#define NFC_ISR_DONE_SHIFT                       30
#define NFC_ISR_WERR_MASK                        0x80000000u
#define NFC_ISR_WERR_SHIFT                       31

/**
 * @}
 */ /* end of group NFC_Register_Masks */


/* NFC - Peripheral instance base addresses */
/** Peripheral NFC base address */
#define NFC_BASE                                 (0x400E0000u)
/** Peripheral NFC base pointer */
#define NFC                                      ((NFC_Type *)NFC_BASE)
/** Array initializer of NFC peripheral base pointers */
#define NFC_BASES                                { NFC }

/**
 * @}
 */ /* end of group NFC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OCOTP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
 * @{
 */

/** OCOTP - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< OTP Controller Control Register, offset: 0x0 */
  __IO uint32_t CTRL_SET;                          /**< OTP Controller Control Register, offset: 0x4 */
  __IO uint32_t CTRL_CLR;                          /**< OTP Controller Control Register, offset: 0x8 */
  __IO uint32_t CTRL_TOG;                          /**< OTP Controller Control Register, offset: 0xC */
  __IO uint32_t TIMING;                            /**< OTP Controller Timing Register, offset: 0x10 */
       uint8_t RESERVED_0[12];
  __IO uint32_t DATA;                              /**< OTP Controller Write Data Register, offset: 0x20 */
       uint8_t RESERVED_1[12];
  __IO uint32_t READ_CTRL;                         /**< OTP Controller Read Control Register, offset: 0x30 */
       uint8_t RESERVED_2[12];
  __IO uint32_t READ_FUSE_DATA;                    /**< OTP Controller Read Data Register, offset: 0x40 */
       uint8_t RESERVED_3[28];
  __IO uint32_t SCS;                               /**< Software Controllable Set Register, offset: 0x60 */
  __IO uint32_t SCS_SET;                           /**< Software Controllable Set Register, offset: 0x64 */
  __IO uint32_t SCS_CLR;                           /**< Software Controllable Set Register, offset: 0x68 */
  __IO uint32_t SCS_TOG;                           /**< Software Controllable Set Register, offset: 0x6C */
  __IO uint32_t CRC_ADDR;                          /**< OTP Controller CRC address, offset: 0x70 */
       uint8_t RESERVED_4[12];
  __IO uint32_t CRC_VALUE;                         /**< OTP Controller CRC Value Register, offset: 0x80 */
       uint8_t RESERVED_5[12];
  __I  uint32_t VERSION;                           /**< OTP Controller Version Register, offset: 0x90 */
       uint8_t RESERVED_6[876];
  __IO uint32_t LOCK;                              /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
       uint8_t RESERVED_7[12];
  __IO uint32_t CFG0;                              /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */
       uint8_t RESERVED_8[12];
  __IO uint32_t CFG1;                              /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */
       uint8_t RESERVED_9[44];
  __IO uint32_t CFG4;                              /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */
       uint8_t RESERVED_10[12];
  __IO uint32_t CFG5;                              /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */
       uint8_t RESERVED_11[28];
  __IO uint32_t MEM0;                              /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */
       uint8_t RESERVED_12[12];
  __IO uint32_t MEM1;                              /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */
       uint8_t RESERVED_13[12];
  __IO uint32_t MEM2;                              /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */
       uint8_t RESERVED_14[12];
  __IO uint32_t MEM3;                              /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */
       uint8_t RESERVED_15[12];
  __IO uint32_t MEM4;                              /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */
       uint8_t RESERVED_16[12];
  __IO uint32_t ANA0;                              /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */
       uint8_t RESERVED_17[12];
  __IO uint32_t ANA1;                              /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */
       uint8_t RESERVED_18[12];
  __IO uint32_t ANA2;                              /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */
       uint8_t RESERVED_19[12];
  __IO uint32_t OTPMK0;                            /**< Shadow Register for OTP Bank2 Word0 (OTPMK and CRYPTO Key), offset: 0x500 */
       uint8_t RESERVED_20[12];
  __IO uint32_t OTPMK1;                            /**< Shadow Register for OTP Bank2 Word1 (OTPMK and CRYPTO Key), offset: 0x510 */
       uint8_t RESERVED_21[12];
  __IO uint32_t OTPMK2;                            /**< Shadow Register for OTP Bank2 Word2 (OTPMK and CRYPTO Key), offset: 0x520 */
       uint8_t RESERVED_22[12];
  __IO uint32_t OTPMK3;                            /**< Shadow Register for OTP Bank2 Word3 (OTPMK and CRYPTO Key), offset: 0x530 */
       uint8_t RESERVED_23[12];
  __IO uint32_t OTPMK4;                            /**< Shadow Register for OTP Bank2 Word4 (OTPMK Key), offset: 0x540 */
       uint8_t RESERVED_24[12];
  __IO uint32_t OTPMK5;                            /**< Shadow Register for OTP Bank2 Word5 (OTPMK Key), offset: 0x550 */
       uint8_t RESERVED_25[12];
  __IO uint32_t OTPMK6;                            /**< Shadow Register for OTP Bank2 Word6 (OTPMK Key), offset: 0x560 */
       uint8_t RESERVED_26[12];
  __IO uint32_t OTPMK7;                            /**< Shadow Register for OTP Bank2 Word7 (OTPMK Key), offset: 0x570 */
       uint8_t RESERVED_27[12];
  __IO uint32_t SRK0;                              /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */
       uint8_t RESERVED_28[12];
  __IO uint32_t SRK1;                              /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */
       uint8_t RESERVED_29[12];
  __IO uint32_t SRK2;                              /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */
       uint8_t RESERVED_30[12];
  __IO uint32_t SRK3;                              /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */
       uint8_t RESERVED_31[12];
  __IO uint32_t SRK4;                              /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */
       uint8_t RESERVED_32[12];
  __IO uint32_t SRK5;                              /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */
       uint8_t RESERVED_33[12];
  __IO uint32_t SRK6;                              /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */
       uint8_t RESERVED_34[12];
  __IO uint32_t SRK7;                              /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */
       uint8_t RESERVED_35[12];
  __IO uint32_t RESP0;                             /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */
       uint8_t RESERVED_36[12];
  __IO uint32_t HSJC_RESP1;                        /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */
       uint8_t RESERVED_37[12];
  __IO uint32_t MAC0;                              /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */
       uint8_t RESERVED_38[12];
  __IO uint32_t MAC1;                              /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */
       uint8_t RESERVED_39[12];
  __IO uint32_t MAC2;                              /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */
       uint8_t RESERVED_40[12];
  __IO uint32_t MAC3;                              /**< Value of OTP Bank4 Word5 (MAC Address), offset: 0x650 */
       uint8_t RESERVED_41[12];
  __IO uint32_t GP1;                               /**< Value of OTP Bank4 Word6 (HW Capabilities), offset: 0x660 */
       uint8_t RESERVED_42[12];
  __IO uint32_t GP2;                               /**< Value of OTP Bank4 Word7 (HW Capabilities), offset: 0x670 */
       uint8_t RESERVED_43[12];
  __IO uint32_t CSU_ALARM;                         /**< Value of OTP Bank5 Word0, offset: 0x680 */
       uint8_t RESERVED_44[108];
  __IO uint32_t SRK_REVOKE;                        /**< Value of OTP Bank5 Word7 (HW Capabilities), offset: 0x6F0 */
       uint8_t RESERVED_45[396];
  __I  uint32_t TFUSE0;                            /**< Value of OTP Bank7 Word0 (Configuration and Manufacturing Info.), offset: 0x880 */
       uint8_t RESERVED_46[12];
  __I  uint32_t TFUSE1;                            /**< Value of OTP Bank7 Word1 (Configuration and Manufacturing Info.), offset: 0x890 */
       uint8_t RESERVED_47[12];
  __I  uint32_t VDD_TRIM;                          /**< Value of OTP Bank7 Word2 (Configuration and Manufacturing Info.), offset: 0x8A0 */
       uint8_t RESERVED_48[12];
  __I  uint32_t PMUR;                              /**< Value of OTP Bank7 Word3 (Configuration and Manufacturing Info.), offset: 0x8B0 */
       uint8_t RESERVED_49[12];
  __I  uint32_t PMU;                               /**< Value of OTP Bank7 Word4 (Configuration and Manufacturing Info.), offset: 0x8C0 */
       uint8_t RESERVED_50[12];
  __IO uint32_t RNG;                               /**< Value of OTP Bank7 Word5 (Memory Related Info.), offset: 0x8D0 */
       uint8_t RESERVED_51[12];
  __IO uint32_t VTD_TRIM;                          /**< Value of OTP Bank7 Word6 (Memory Related Info.), offset: 0x8E0 */
       uint8_t RESERVED_52[12];
  __IO uint32_t VTMON;                             /**< Value of OTP Bank7 Word7 (Memory Related Info.), offset: 0x8F0 */
       uint8_t RESERVED_53[908];
  __IO uint32_t CRC0;                              /**< Value of OTP Bank15 Word0, offset: 0xC80 */
       uint8_t RESERVED_54[12];
  __IO uint32_t CRC1;                              /**< Value of OTP Bank15 Word1, offset: 0xC90 */
       uint8_t RESERVED_55[12];
  __IO uint32_t CRC2;                              /**< Value of OTP Bank15 Word2, offset: 0xCA0 */
       uint8_t RESERVED_56[12];
  __IO uint32_t CRC3;                              /**< Value of OTP Bank15 Word3, offset: 0xCB0 */
       uint8_t RESERVED_57[12];
  __IO uint32_t CRC4;                              /**< Value of OTP Bank15 Word4, offset: 0xCC0 */
       uint8_t RESERVED_58[12];
  __IO uint32_t CRC5;                              /**< Value of OTP Bank15 Word5, offset: 0xCD0 */
       uint8_t RESERVED_59[12];
  __IO uint32_t CRC6;                              /**< Value of OTP Bank15 Word6, offset: 0xCE0 */
       uint8_t RESERVED_60[12];
  __IO uint32_t CRC7;                              /**< Value of OTP Bank15 Word7, offset: 0xCF0 */
} OCOTP_Type;

/* ----------------------------------------------------------------------------
   -- OCOTP Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
 * @{
 */

/* CTRL Bit Fields */
#define OCOTP_CTRL_ADDR_MASK                     0x7Fu
#define OCOTP_CTRL_ADDR_SHIFT                    0
#define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_ADDR_SHIFT))&OCOTP_CTRL_ADDR_MASK)
#define OCOTP_CTRL_BUSY_MASK                     0x100u
#define OCOTP_CTRL_BUSY_SHIFT                    8
#define OCOTP_CTRL_ERROR_MASK                    0x200u
#define OCOTP_CTRL_ERROR_SHIFT                   9
#define OCOTP_CTRL_RELOAD_SHADOWS_MASK           0x400u
#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          10
#define OCOTP_CTRL_CRC_TEST_MASK                 0x800u
#define OCOTP_CTRL_CRC_TEST_SHIFT                11
#define OCOTP_CTRL_CRC_FAIL_MASK                 0x1000u
#define OCOTP_CTRL_CRC_FAIL_SHIFT                12
#define OCOTP_CTRL_WR_UNLOCK_MASK                0xFFFF0000u
#define OCOTP_CTRL_WR_UNLOCK_SHIFT               16
#define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_WR_UNLOCK_SHIFT))&OCOTP_CTRL_WR_UNLOCK_MASK)
/* CTRL_SET Bit Fields */
#define OCOTP_CTRL_SET_ADDR_MASK                 0x7Fu
#define OCOTP_CTRL_SET_ADDR_SHIFT                0
#define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_ADDR_SHIFT))&OCOTP_CTRL_SET_ADDR_MASK)
#define OCOTP_CTRL_SET_BUSY_MASK                 0x100u
#define OCOTP_CTRL_SET_BUSY_SHIFT                8
#define OCOTP_CTRL_SET_ERROR_MASK                0x200u
#define OCOTP_CTRL_SET_ERROR_SHIFT               9
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       0x400u
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      10
#define OCOTP_CTRL_SET_CRC_TEST_MASK             0x800u
#define OCOTP_CTRL_SET_CRC_TEST_SHIFT            11
#define OCOTP_CTRL_SET_CRC_FAIL_MASK             0x1000u
#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT            12
#define OCOTP_CTRL_SET_WR_UNLOCK_MASK            0xFFFF0000u
#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           16
#define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_WR_UNLOCK_SHIFT))&OCOTP_CTRL_SET_WR_UNLOCK_MASK)
/* CTRL_CLR Bit Fields */
#define OCOTP_CTRL_CLR_ADDR_MASK                 0x7Fu
#define OCOTP_CTRL_CLR_ADDR_SHIFT                0
#define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_ADDR_SHIFT))&OCOTP_CTRL_CLR_ADDR_MASK)
#define OCOTP_CTRL_CLR_BUSY_MASK                 0x100u
#define OCOTP_CTRL_CLR_BUSY_SHIFT                8
#define OCOTP_CTRL_CLR_ERROR_MASK                0x200u
#define OCOTP_CTRL_CLR_ERROR_SHIFT               9
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       0x400u
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      10
#define OCOTP_CTRL_CLR_CRC_TEST_MASK             0x800u
#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT            11
#define OCOTP_CTRL_CLR_CRC_FAIL_MASK             0x1000u
#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT            12
#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            0xFFFF0000u
#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           16
#define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT))&OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
/* CTRL_TOG Bit Fields */
#define OCOTP_CTRL_TOG_ADDR_MASK                 0x7Fu
#define OCOTP_CTRL_TOG_ADDR_SHIFT                0
#define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_ADDR_SHIFT))&OCOTP_CTRL_TOG_ADDR_MASK)
#define OCOTP_CTRL_TOG_BUSY_MASK                 0x100u
#define OCOTP_CTRL_TOG_BUSY_SHIFT                8
#define OCOTP_CTRL_TOG_ERROR_MASK                0x200u
#define OCOTP_CTRL_TOG_ERROR_SHIFT               9
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       0x400u
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      10
#define OCOTP_CTRL_TOG_CRC_TEST_MASK             0x800u
#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT            11
#define OCOTP_CTRL_TOG_CRC_FAIL_MASK             0x1000u
#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT            12
#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            0xFFFF0000u
#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           16
#define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT))&OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
/* TIMING Bit Fields */
#define OCOTP_TIMING_STROBE_PROG_MASK            0xFFFu
#define OCOTP_TIMING_STROBE_PROG_SHIFT           0
#define OCOTP_TIMING_STROBE_PROG(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_STROBE_PROG_SHIFT))&OCOTP_TIMING_STROBE_PROG_MASK)
#define OCOTP_TIMING_RELAX_MASK                  0xF000u
#define OCOTP_TIMING_RELAX_SHIFT                 12
#define OCOTP_TIMING_RELAX(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_RELAX_SHIFT))&OCOTP_TIMING_RELAX_MASK)
#define OCOTP_TIMING_STROBE_READ_MASK            0x3F0000u
#define OCOTP_TIMING_STROBE_READ_SHIFT           16
#define OCOTP_TIMING_STROBE_READ(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_STROBE_READ_SHIFT))&OCOTP_TIMING_STROBE_READ_MASK)
#define OCOTP_TIMING_WAIT_MASK                   0xFC00000u
#define OCOTP_TIMING_WAIT_SHIFT                  22
#define OCOTP_TIMING_WAIT(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_WAIT_SHIFT))&OCOTP_TIMING_WAIT_MASK)
/* DATA Bit Fields */
#define OCOTP_DATA_DATA_MASK                     0xFFFFFFFFu
#define OCOTP_DATA_DATA_SHIFT                    0
#define OCOTP_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA_DATA_SHIFT))&OCOTP_DATA_DATA_MASK)
/* READ_CTRL Bit Fields */
#define OCOTP_READ_CTRL_READ_FUSE_MASK           0x1u
#define OCOTP_READ_CTRL_READ_FUSE_SHIFT          0
/* READ_FUSE_DATA Bit Fields */
#define OCOTP_READ_FUSE_DATA_DATA_MASK           0xFFFFFFFFu
#define OCOTP_READ_FUSE_DATA_DATA_SHIFT          0
#define OCOTP_READ_FUSE_DATA_DATA(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA_DATA_SHIFT))&OCOTP_READ_FUSE_DATA_DATA_MASK)
/* SCS Bit Fields */
#define OCOTP_SCS_HAB_JDE_MASK                   0x1u
#define OCOTP_SCS_HAB_JDE_SHIFT                  0
#define OCOTP_SCS_SPARE_MASK                     0x7FFFFFFEu
#define OCOTP_SCS_SPARE_SHIFT                    1
#define OCOTP_SCS_SPARE(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SPARE_SHIFT))&OCOTP_SCS_SPARE_MASK)
#define OCOTP_SCS_LOCK_MASK                      0x80000000u
#define OCOTP_SCS_LOCK_SHIFT                     31
/* SCS_SET Bit Fields */
#define OCOTP_SCS_SET_HAB_JDE_MASK               0x1u
#define OCOTP_SCS_SET_HAB_JDE_SHIFT              0
#define OCOTP_SCS_SET_SPARE_MASK                 0x7FFFFFFEu
#define OCOTP_SCS_SET_SPARE_SHIFT                1
#define OCOTP_SCS_SET_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SET_SPARE_SHIFT))&OCOTP_SCS_SET_SPARE_MASK)
#define OCOTP_SCS_SET_LOCK_MASK                  0x80000000u
#define OCOTP_SCS_SET_LOCK_SHIFT                 31
/* SCS_CLR Bit Fields */
#define OCOTP_SCS_CLR_HAB_JDE_MASK               0x1u
#define OCOTP_SCS_CLR_HAB_JDE_SHIFT              0
#define OCOTP_SCS_CLR_SPARE_MASK                 0x7FFFFFFEu
#define OCOTP_SCS_CLR_SPARE_SHIFT                1
#define OCOTP_SCS_CLR_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_CLR_SPARE_SHIFT))&OCOTP_SCS_CLR_SPARE_MASK)
#define OCOTP_SCS_CLR_LOCK_MASK                  0x80000000u
#define OCOTP_SCS_CLR_LOCK_SHIFT                 31
/* SCS_TOG Bit Fields */
#define OCOTP_SCS_TOG_HAB_JDE_MASK               0x1u
#define OCOTP_SCS_TOG_HAB_JDE_SHIFT              0
#define OCOTP_SCS_TOG_SPARE_MASK                 0x7FFFFFFEu
#define OCOTP_SCS_TOG_SPARE_SHIFT                1
#define OCOTP_SCS_TOG_SPARE(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_TOG_SPARE_SHIFT))&OCOTP_SCS_TOG_SPARE_MASK)
#define OCOTP_SCS_TOG_LOCK_MASK                  0x80000000u
#define OCOTP_SCS_TOG_LOCK_SHIFT                 31
/* CRC_ADDR Bit Fields */
#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK      0xFFu
#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT     0
#define OCOTP_CRC_ADDR_DATA_START_ADDR(x)        (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT))&OCOTP_CRC_ADDR_DATA_START_ADDR_MASK)
#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK        0xFF00u
#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT       8
#define OCOTP_CRC_ADDR_DATA_END_ADDR(x)          (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT))&OCOTP_CRC_ADDR_DATA_END_ADDR_MASK)
#define OCOTP_CRC_ADDR_CRC_ADDR_MASK             0x70000u
#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT            16
#define OCOTP_CRC_ADDR_CRC_ADDR(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_CRC_ADDR_SHIFT))&OCOTP_CRC_ADDR_CRC_ADDR_MASK)
/* CRC_VALUE Bit Fields */
#define OCOTP_CRC_VALUE_DATA_MASK                0xFFFFFFFFu
#define OCOTP_CRC_VALUE_DATA_SHIFT               0
#define OCOTP_CRC_VALUE_DATA(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_VALUE_DATA_SHIFT))&OCOTP_CRC_VALUE_DATA_MASK)
/* VERSION Bit Fields */
#define OCOTP_VERSION_STEP_MASK                  0xFFFFu
#define OCOTP_VERSION_STEP_SHIFT                 0
#define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_STEP_SHIFT))&OCOTP_VERSION_STEP_MASK)
#define OCOTP_VERSION_MINOR_MASK                 0xFF0000u
#define OCOTP_VERSION_MINOR_SHIFT                16
#define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MINOR_SHIFT))&OCOTP_VERSION_MINOR_MASK)
#define OCOTP_VERSION_MAJOR_MASK                 0xFF000000u
#define OCOTP_VERSION_MAJOR_SHIFT                24
#define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MAJOR_SHIFT))&OCOTP_VERSION_MAJOR_MASK)
/* LOCK Bit Fields */
#define OCOTP_LOCK_TESTER_LOCK_MASK              0x3u
#define OCOTP_LOCK_TESTER_LOCK_SHIFT             0
#define OCOTP_LOCK_TESTER_LOCK(x)                (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_TESTER_LOCK_SHIFT))&OCOTP_LOCK_TESTER_LOCK_MASK)
#define OCOTP_LOCK_BOOT_CFG_LOCK_MASK            0xCu
#define OCOTP_LOCK_BOOT_CFG_LOCK_SHIFT           2
#define OCOTP_LOCK_BOOT_CFG_LOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_BOOT_CFG_LOCK_SHIFT))&OCOTP_LOCK_BOOT_CFG_LOCK_MASK)
#define OCOTP_LOCK_MEM_TRIM_LOCK_MASK            0x30u
#define OCOTP_LOCK_MEM_TRIM_LOCK_SHIFT           4
#define OCOTP_LOCK_MEM_TRIM_LOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MEM_TRIM_LOCK_SHIFT))&OCOTP_LOCK_MEM_TRIM_LOCK_MASK)
#define OCOTP_LOCK_SJC_RESP_LOCK_MASK            0x40u
#define OCOTP_LOCK_SJC_RESP_LOCK_SHIFT           6
#define OCOTP_LOCK_MAC_ADDR_LOCK_MASK            0x300u
#define OCOTP_LOCK_MAC_ADDR_LOCK_SHIFT           8
#define OCOTP_LOCK_MAC_ADDR_LOCK(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MAC_ADDR_LOCK_SHIFT))&OCOTP_LOCK_MAC_ADDR_LOCK_MASK)
#define OCOTP_LOCK_GP1_LOCK_MASK                 0xC00u
#define OCOTP_LOCK_GP1_LOCK_SHIFT                10
#define OCOTP_LOCK_GP1_LOCK(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP1_LOCK_SHIFT))&OCOTP_LOCK_GP1_LOCK_MASK)
#define OCOTP_LOCK_GP2_LOCK_MASK                 0x3000u
#define OCOTP_LOCK_GP2_LOCK_SHIFT                12
#define OCOTP_LOCK_GP2_LOCK(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP2_LOCK_SHIFT))&OCOTP_LOCK_GP2_LOCK_MASK)
#define OCOTP_LOCK_SRK_LOCK_MASK                 0x4000u
#define OCOTP_LOCK_SRK_LOCK_SHIFT                14
#define OCOTP_LOCK_OTPMK_LOCK_MASK               0x20000u
#define OCOTP_LOCK_OTPMK_LOCK_SHIFT              17
#define OCOTP_LOCK_ANALOG_LOCK_MASK              0xC0000u
#define OCOTP_LOCK_ANALOG_LOCK_SHIFT             18
#define OCOTP_LOCK_ANALOG_LOCK(x)                (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_ANALOG_LOCK_SHIFT))&OCOTP_LOCK_ANALOG_LOCK_MASK)
#define OCOTP_LOCK_PMU_LOCK_MASK                 0x300000u
#define OCOTP_LOCK_PMU_LOCK_SHIFT                20
#define OCOTP_LOCK_PMU_LOCK(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_PMU_LOCK_SHIFT))&OCOTP_LOCK_PMU_LOCK_MASK)
#define OCOTP_LOCK_MISC_CONF_LOCK_MASK           0x400000u
#define OCOTP_LOCK_MISC_CONF_LOCK_SHIFT          22
#define OCOTP_LOCK_CRC_GP_LO_LOCK_MASK           0xC000000u
#define OCOTP_LOCK_CRC_GP_LO_LOCK_SHIFT          26
#define OCOTP_LOCK_CRC_GP_LO_LOCK(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_CRC_GP_LO_LOCK_SHIFT))&OCOTP_LOCK_CRC_GP_LO_LOCK_MASK)
#define OCOTP_LOCK_CRC_GP_HI_LOCK_MASK           0x30000000u
#define OCOTP_LOCK_CRC_GP_HI_LOCK_SHIFT          28
#define OCOTP_LOCK_CRC_GP_HI_LOCK(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_CRC_GP_HI_LOCK_SHIFT))&OCOTP_LOCK_CRC_GP_HI_LOCK_MASK)
/* CFG0 Bit Fields */
#define OCOTP_CFG0_SJC_CHALL_MASK                0xFFFFFFFFu
#define OCOTP_CFG0_SJC_CHALL_SHIFT               0
#define OCOTP_CFG0_SJC_CHALL(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG0_SJC_CHALL_SHIFT))&OCOTP_CFG0_SJC_CHALL_MASK)
/* CFG1 Bit Fields */
#define OCOTP_CFG1_SJC_CHALL_MASK                0xFFFFFFFFu
#define OCOTP_CFG1_SJC_CHALL_SHIFT               0
#define OCOTP_CFG1_SJC_CHALL(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG1_SJC_CHALL_SHIFT))&OCOTP_CFG1_SJC_CHALL_MASK)
/* CFG4 Bit Fields */
#define OCOTP_CFG4_BOOT_CFG1_MASK                0xFFu
#define OCOTP_CFG4_BOOT_CFG1_SHIFT               0
#define OCOTP_CFG4_BOOT_CFG1(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG4_BOOT_CFG1_SHIFT))&OCOTP_CFG4_BOOT_CFG1_MASK)
#define OCOTP_CFG4_BOOT_CFG2_MASK                0xFF00u
#define OCOTP_CFG4_BOOT_CFG2_SHIFT               8
#define OCOTP_CFG4_BOOT_CFG2(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG4_BOOT_CFG2_SHIFT))&OCOTP_CFG4_BOOT_CFG2_MASK)
#define OCOTP_CFG4_BOOT_CFG3_MASK                0xFF0000u
#define OCOTP_CFG4_BOOT_CFG3_SHIFT               16
#define OCOTP_CFG4_BOOT_CFG3(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG4_BOOT_CFG3_SHIFT))&OCOTP_CFG4_BOOT_CFG3_MASK)
#define OCOTP_CFG4_BOOT_CFG4_MASK                0xFF000000u
#define OCOTP_CFG4_BOOT_CFG4_SHIFT               24
#define OCOTP_CFG4_BOOT_CFG4(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG4_BOOT_CFG4_SHIFT))&OCOTP_CFG4_BOOT_CFG4_MASK)
/* CFG5 Bit Fields */
#define OCOTP_CFG5_SEC_CONFIG_MASK               0x2u
#define OCOTP_CFG5_SEC_CONFIG_SHIFT              1
#define OCOTP_CFG5_DIR_BT_DIS_MASK               0x8u
#define OCOTP_CFG5_DIR_BT_DIS_SHIFT              3
#define OCOTP_CFG5_BT_FUSE_SEL_MASK              0x10u
#define OCOTP_CFG5_BT_FUSE_SEL_SHIFT             4
#define OCOTP_CFG5_CSU_ALARM_DISABLE_MASK        0x80000u
#define OCOTP_CFG5_CSU_ALARM_DISABLE_SHIFT       19
#define OCOTP_CFG5_SJC_DISABLE_MASK              0x100000u
#define OCOTP_CFG5_SJC_DISABLE_SHIFT             20
#define OCOTP_CFG5_WDOG_ENABLE_MASK              0x200000u
#define OCOTP_CFG5_WDOG_ENABLE_SHIFT             21
#define OCOTP_CFG5_JTAG_SMODE_MASK               0xC00000u
#define OCOTP_CFG5_JTAG_SMODE_SHIFT              22
#define OCOTP_CFG5_JTAG_SMODE(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG5_JTAG_SMODE_SHIFT))&OCOTP_CFG5_JTAG_SMODE_MASK)
#define OCOTP_CFG5_KTE_MASK                      0x4000000u
#define OCOTP_CFG5_KTE_SHIFT                     26
#define OCOTP_CFG5_JTAG_HEO_MASK                 0x8000000u
#define OCOTP_CFG5_JTAG_HEO_SHIFT                27
/* MEM0 Bit Fields */
#define OCOTP_MEM0_IRC_128K_TRIM_MASK            0xFFFFu
#define OCOTP_MEM0_IRC_128K_TRIM_SHIFT           0
#define OCOTP_MEM0_IRC_128K_TRIM(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM0_IRC_128K_TRIM_SHIFT))&OCOTP_MEM0_IRC_128K_TRIM_MASK)
#define OCOTP_MEM0_IRC_24M_TRIM_MASK             0xFFFF0000u
#define OCOTP_MEM0_IRC_24M_TRIM_SHIFT            16
#define OCOTP_MEM0_IRC_24M_TRIM(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM0_IRC_24M_TRIM_SHIFT))&OCOTP_MEM0_IRC_24M_TRIM_MASK)
/* MEM1 Bit Fields */
#define OCOTP_MEM1_PTC_VER_MASK                  0x7u
#define OCOTP_MEM1_PTC_VER_SHIFT                 0
#define OCOTP_MEM1_PTC_VER(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_PTC_VER_SHIFT))&OCOTP_MEM1_PTC_VER_MASK)
#define OCOTP_MEM1_LVDS_BG_V_MASK                0x38u
#define OCOTP_MEM1_LVDS_BG_V_SHIFT               3
#define OCOTP_MEM1_LVDS_BG_V(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_LVDS_BG_V_SHIFT))&OCOTP_MEM1_LVDS_BG_V_MASK)
#define OCOTP_MEM1_DVFS_DELAY_ADJUST_MASK        0xFF00u
#define OCOTP_MEM1_DVFS_DELAY_ADJUST_SHIFT       8
#define OCOTP_MEM1_DVFS_DELAY_ADJUST(x)          (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_DVFS_DELAY_ADJUST_SHIFT))&OCOTP_MEM1_DVFS_DELAY_ADJUST_MASK)
#define OCOTP_MEM1_L1I_TCS1_MASK                 0x70000u
#define OCOTP_MEM1_L1I_TCS1_SHIFT                16
#define OCOTP_MEM1_L1I_TCS1(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_L1I_TCS1_SHIFT))&OCOTP_MEM1_L1I_TCS1_MASK)
#define OCOTP_MEM1_L1D_TCH_MASK                  0x380000u
#define OCOTP_MEM1_L1D_TCH_SHIFT                 19
#define OCOTP_MEM1_L1D_TCH(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_L1D_TCH_SHIFT))&OCOTP_MEM1_L1D_TCH_MASK)
#define OCOTP_MEM1_L1I_TCS2_MASK                 0x7000000u
#define OCOTP_MEM1_L1I_TCS2_SHIFT                24
#define OCOTP_MEM1_L1I_TCS2(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_L1I_TCS2_SHIFT))&OCOTP_MEM1_L1I_TCS2_MASK)
#define OCOTP_MEM1_L1I_TCH_MASK                  0x38000000u
#define OCOTP_MEM1_L1I_TCH_SHIFT                 27
#define OCOTP_MEM1_L1I_TCH(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_L1I_TCH_SHIFT))&OCOTP_MEM1_L1I_TCH_MASK)
#define OCOTP_MEM1_TLB_TC_MASK                   0xC0000000u
#define OCOTP_MEM1_TLB_TC_SHIFT                  30
#define OCOTP_MEM1_TLB_TC(x)                     (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_TLB_TC_SHIFT))&OCOTP_MEM1_TLB_TC_MASK)
/* MEM2 Bit Fields */
#define OCOTP_MEM2_MANU2_MASK                    0xFFu
#define OCOTP_MEM2_MANU2_SHIFT                   0
#define OCOTP_MEM2_MANU2(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM2_MANU2_SHIFT))&OCOTP_MEM2_MANU2_MASK)
#define OCOTP_MEM2_SMS_MASK                      0xFFFFFF00u
#define OCOTP_MEM2_SMS_SHIFT                     8
#define OCOTP_MEM2_SMS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM2_SMS_SHIFT))&OCOTP_MEM2_SMS_MASK)
/* MEM3 Bit Fields */
#define OCOTP_MEM3_SMS_MASK                      0xFFFFFFFFu
#define OCOTP_MEM3_SMS_SHIFT                     0
#define OCOTP_MEM3_SMS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM3_SMS_SHIFT))&OCOTP_MEM3_SMS_MASK)
/* MEM4 Bit Fields */
#define OCOTP_MEM4_SMS_MASK                      0xFFFFFFFFu
#define OCOTP_MEM4_SMS_SHIFT                     0
#define OCOTP_MEM4_SMS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM4_SMS_SHIFT))&OCOTP_MEM4_SMS_MASK)
/* ANA0 Bit Fields */
#define OCOTP_ANA0_REFTOP_VBGADJ_MASK            0x7u
#define OCOTP_ANA0_REFTOP_VBGADJ_SHIFT           0
#define OCOTP_ANA0_REFTOP_VBGADJ(x)              (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_REFTOP_VBGADJ_SHIFT))&OCOTP_ANA0_REFTOP_VBGADJ_MASK)
#define OCOTP_ANA0_REFTOP_BIAS_TST_MASK          0x18u
#define OCOTP_ANA0_REFTOP_BIAS_TST_SHIFT         3
#define OCOTP_ANA0_REFTOP_BIAS_TST(x)            (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_REFTOP_BIAS_TST_SHIFT))&OCOTP_ANA0_REFTOP_BIAS_TST_MASK)
#define OCOTP_ANA0_1P1_REG_OUT_TRG_MASK          0x1F00u
#define OCOTP_ANA0_1P1_REG_OUT_TRG_SHIFT         8
#define OCOTP_ANA0_1P1_REG_OUT_TRG(x)            (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_1P1_REG_OUT_TRG_SHIFT))&OCOTP_ANA0_1P1_REG_OUT_TRG_MASK)
#define OCOTP_ANA0_2P5_REG_OUT_TRG_MASK          0x1F0000u
#define OCOTP_ANA0_2P5_REG_OUT_TRG_SHIFT         16
#define OCOTP_ANA0_2P5_REG_OUT_TRG(x)            (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_2P5_REG_OUT_TRG_SHIFT))&OCOTP_ANA0_2P5_REG_OUT_TRG_MASK)
#define OCOTP_ANA0_3P_REG_OUT_TRG_MASK           0x1F000000u
#define OCOTP_ANA0_3P_REG_OUT_TRG_SHIFT          24
#define OCOTP_ANA0_3P_REG_OUT_TRG(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_3P_REG_OUT_TRG_SHIFT))&OCOTP_ANA0_3P_REG_OUT_TRG_MASK)
/* ANA1 Bit Fields */
#define OCOTP_ANA1_ANALOG_TEMP_SENSE_MASK        0xFFFFFFFFu
#define OCOTP_ANA1_ANALOG_TEMP_SENSE_SHIFT       0
#define OCOTP_ANA1_ANALOG_TEMP_SENSE(x)          (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA1_ANALOG_TEMP_SENSE_SHIFT))&OCOTP_ANA1_ANALOG_TEMP_SENSE_MASK)
/* ANA2 Bit Fields */
#define OCOTP_ANA2_USB_VID_MASK                  0xFFFFu
#define OCOTP_ANA2_USB_VID_SHIFT                 0
#define OCOTP_ANA2_USB_VID(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA2_USB_VID_SHIFT))&OCOTP_ANA2_USB_VID_MASK)
#define OCOTP_ANA2_USB0_PID_MASK                 0xFFFF0000u
#define OCOTP_ANA2_USB0_PID_SHIFT                16
#define OCOTP_ANA2_USB0_PID(x)                   (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA2_USB0_PID_SHIFT))&OCOTP_ANA2_USB0_PID_MASK)
/* OTPMK0 Bit Fields */
#define OCOTP_OTPMK0_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK0_OTPMK_SHIFT                 0
#define OCOTP_OTPMK0_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK0_OTPMK_SHIFT))&OCOTP_OTPMK0_OTPMK_MASK)
/* OTPMK1 Bit Fields */
#define OCOTP_OTPMK1_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK1_OTPMK_SHIFT                 0
#define OCOTP_OTPMK1_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK1_OTPMK_SHIFT))&OCOTP_OTPMK1_OTPMK_MASK)
/* OTPMK2 Bit Fields */
#define OCOTP_OTPMK2_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK2_OTPMK_SHIFT                 0
#define OCOTP_OTPMK2_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK2_OTPMK_SHIFT))&OCOTP_OTPMK2_OTPMK_MASK)
/* OTPMK3 Bit Fields */
#define OCOTP_OTPMK3_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK3_OTPMK_SHIFT                 0
#define OCOTP_OTPMK3_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK3_OTPMK_SHIFT))&OCOTP_OTPMK3_OTPMK_MASK)
/* OTPMK4 Bit Fields */
#define OCOTP_OTPMK4_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK4_OTPMK_SHIFT                 0
#define OCOTP_OTPMK4_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK4_OTPMK_SHIFT))&OCOTP_OTPMK4_OTPMK_MASK)
/* OTPMK5 Bit Fields */
#define OCOTP_OTPMK5_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK5_OTPMK_SHIFT                 0
#define OCOTP_OTPMK5_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK5_OTPMK_SHIFT))&OCOTP_OTPMK5_OTPMK_MASK)
/* OTPMK6 Bit Fields */
#define OCOTP_OTPMK6_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK6_OTPMK_SHIFT                 0
#define OCOTP_OTPMK6_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK6_OTPMK_SHIFT))&OCOTP_OTPMK6_OTPMK_MASK)
/* OTPMK7 Bit Fields */
#define OCOTP_OTPMK7_OTPMK_MASK                  0xFFFFFFFFu
#define OCOTP_OTPMK7_OTPMK_SHIFT                 0
#define OCOTP_OTPMK7_OTPMK(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK7_OTPMK_SHIFT))&OCOTP_OTPMK7_OTPMK_MASK)
/* SRK0 Bit Fields */
#define OCOTP_SRK0_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK0_BITS_SHIFT                    0
#define OCOTP_SRK0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK0_BITS_SHIFT))&OCOTP_SRK0_BITS_MASK)
/* SRK1 Bit Fields */
#define OCOTP_SRK1_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK1_BITS_SHIFT                    0
#define OCOTP_SRK1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK1_BITS_SHIFT))&OCOTP_SRK1_BITS_MASK)
/* SRK2 Bit Fields */
#define OCOTP_SRK2_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK2_BITS_SHIFT                    0
#define OCOTP_SRK2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK2_BITS_SHIFT))&OCOTP_SRK2_BITS_MASK)
/* SRK3 Bit Fields */
#define OCOTP_SRK3_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK3_BITS_SHIFT                    0
#define OCOTP_SRK3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK3_BITS_SHIFT))&OCOTP_SRK3_BITS_MASK)
/* SRK4 Bit Fields */
#define OCOTP_SRK4_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK4_BITS_SHIFT                    0
#define OCOTP_SRK4_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK4_BITS_SHIFT))&OCOTP_SRK4_BITS_MASK)
/* SRK5 Bit Fields */
#define OCOTP_SRK5_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK5_BITS_SHIFT                    0
#define OCOTP_SRK5_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK5_BITS_SHIFT))&OCOTP_SRK5_BITS_MASK)
/* SRK6 Bit Fields */
#define OCOTP_SRK6_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK6_BITS_SHIFT                    0
#define OCOTP_SRK6_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK6_BITS_SHIFT))&OCOTP_SRK6_BITS_MASK)
/* SRK7 Bit Fields */
#define OCOTP_SRK7_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_SRK7_BITS_SHIFT                    0
#define OCOTP_SRK7_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK7_BITS_SHIFT))&OCOTP_SRK7_BITS_MASK)
/* RESP0 Bit Fields */
#define OCOTP_RESP0_BITS_MASK                    0xFFFFFFFFu
#define OCOTP_RESP0_BITS_SHIFT                   0
#define OCOTP_RESP0_BITS(x)                      (((uint32_t)(((uint32_t)(x))<<OCOTP_RESP0_BITS_SHIFT))&OCOTP_RESP0_BITS_MASK)
/* HSJC_RESP1 Bit Fields */
#define OCOTP_HSJC_RESP1_BITS_MASK               0xFFFFFFFFu
#define OCOTP_HSJC_RESP1_BITS_SHIFT              0
#define OCOTP_HSJC_RESP1_BITS(x)                 (((uint32_t)(((uint32_t)(x))<<OCOTP_HSJC_RESP1_BITS_SHIFT))&OCOTP_HSJC_RESP1_BITS_MASK)
/* MAC0 Bit Fields */
#define OCOTP_MAC0_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_MAC0_BITS_SHIFT                    0
#define OCOTP_MAC0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC0_BITS_SHIFT))&OCOTP_MAC0_BITS_MASK)
/* MAC1 Bit Fields */
#define OCOTP_MAC1_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_MAC1_BITS_SHIFT                    0
#define OCOTP_MAC1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC1_BITS_SHIFT))&OCOTP_MAC1_BITS_MASK)
/* MAC2 Bit Fields */
#define OCOTP_MAC2_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_MAC2_BITS_SHIFT                    0
#define OCOTP_MAC2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC2_BITS_SHIFT))&OCOTP_MAC2_BITS_MASK)
/* MAC3 Bit Fields */
#define OCOTP_MAC3_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_MAC3_BITS_SHIFT                    0
#define OCOTP_MAC3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC3_BITS_SHIFT))&OCOTP_MAC3_BITS_MASK)
/* GP1 Bit Fields */
#define OCOTP_GP1_BITS_MASK                      0xFFFFFFFFu
#define OCOTP_GP1_BITS_SHIFT                     0
#define OCOTP_GP1_BITS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_GP1_BITS_SHIFT))&OCOTP_GP1_BITS_MASK)
/* GP2 Bit Fields */
#define OCOTP_GP2_BITS_MASK                      0xFFFFFFFFu
#define OCOTP_GP2_BITS_SHIFT                     0
#define OCOTP_GP2_BITS(x)                        (((uint32_t)(((uint32_t)(x))<<OCOTP_GP2_BITS_SHIFT))&OCOTP_GP2_BITS_MASK)
/* CSU_ALARM Bit Fields */
#define OCOTP_CSU_ALARM_ALARM_DIS_MASK           0x3u
#define OCOTP_CSU_ALARM_ALARM_DIS_SHIFT          0
#define OCOTP_CSU_ALARM_ALARM_DIS(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_CSU_ALARM_ALARM_DIS_SHIFT))&OCOTP_CSU_ALARM_ALARM_DIS_MASK)
#define OCOTP_CSU_ALARM_ALARM_OUT_MASK           0xCu
#define OCOTP_CSU_ALARM_ALARM_OUT_SHIFT          2
#define OCOTP_CSU_ALARM_ALARM_OUT(x)             (((uint32_t)(((uint32_t)(x))<<OCOTP_CSU_ALARM_ALARM_OUT_SHIFT))&OCOTP_CSU_ALARM_ALARM_OUT_MASK)
#define OCOTP_CSU_ALARM_COUNTER_ALARM_MASK       0x10u
#define OCOTP_CSU_ALARM_COUNTER_ALARM_SHIFT      4
/* SRK_REVOKE Bit Fields */
#define OCOTP_SRK_REVOKE_MC_ERA_MASK             0xFF00u
#define OCOTP_SRK_REVOKE_MC_ERA_SHIFT            8
#define OCOTP_SRK_REVOKE_MC_ERA(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK_REVOKE_MC_ERA_SHIFT))&OCOTP_SRK_REVOKE_MC_ERA_MASK)
#define OCOTP_SRK_REVOKE_AP_BI_VER_MASK          0xFFFF0000u
#define OCOTP_SRK_REVOKE_AP_BI_VER_SHIFT         16
#define OCOTP_SRK_REVOKE_AP_BI_VER(x)            (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK_REVOKE_AP_BI_VER_SHIFT))&OCOTP_SRK_REVOKE_AP_BI_VER_MASK)
/* RNG Bit Fields */
#define OCOTP_RNG_VADC_BANDGAP_MASK              0xFu
#define OCOTP_RNG_VADC_BANDGAP_SHIFT             0
#define OCOTP_RNG_VADC_BANDGAP(x)                (((uint32_t)(((uint32_t)(x))<<OCOTP_RNG_VADC_BANDGAP_SHIFT))&OCOTP_RNG_VADC_BANDGAP_MASK)
#define OCOTP_RNG_ADC0_CAL_MASK                  0xF00u
#define OCOTP_RNG_ADC0_CAL_SHIFT                 8
#define OCOTP_RNG_ADC0_CAL(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_RNG_ADC0_CAL_SHIFT))&OCOTP_RNG_ADC0_CAL_MASK)
#define OCOTP_RNG_ADC1_CAL_MASK                  0xF000u
#define OCOTP_RNG_ADC1_CAL_SHIFT                 12
#define OCOTP_RNG_ADC1_CAL(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_RNG_ADC1_CAL_SHIFT))&OCOTP_RNG_ADC1_CAL_MASK)
#define OCOTP_RNG_RNG_TRIM_MASK                  0xFF000000u
#define OCOTP_RNG_RNG_TRIM_SHIFT                 24
#define OCOTP_RNG_RNG_TRIM(x)                    (((uint32_t)(((uint32_t)(x))<<OCOTP_RNG_RNG_TRIM_SHIFT))&OCOTP_RNG_RNG_TRIM_MASK)
/* VTD_TRIM Bit Fields */
#define OCOTP_VTD_TRIM_VOLTAGE_MON_TRIM_MASK     0x3FFu
#define OCOTP_VTD_TRIM_VOLTAGE_MON_TRIM_SHIFT    0
#define OCOTP_VTD_TRIM_VOLTAGE_MON_TRIM(x)       (((uint32_t)(((uint32_t)(x))<<OCOTP_VTD_TRIM_VOLTAGE_MON_TRIM_SHIFT))&OCOTP_VTD_TRIM_VOLTAGE_MON_TRIM_MASK)
#define OCOTP_VTD_TRIM_TEMP_MON_TRIM_MASK        0xFFC00u
#define OCOTP_VTD_TRIM_TEMP_MON_TRIM_SHIFT       10
#define OCOTP_VTD_TRIM_TEMP_MON_TRIM(x)          (((uint32_t)(((uint32_t)(x))<<OCOTP_VTD_TRIM_TEMP_MON_TRIM_SHIFT))&OCOTP_VTD_TRIM_TEMP_MON_TRIM_MASK)
#define OCOTP_VTD_TRIM_DRYICE_BGR_TRIM_MASK      0x3F000000u
#define OCOTP_VTD_TRIM_DRYICE_BGR_TRIM_SHIFT     24
#define OCOTP_VTD_TRIM_DRYICE_BGR_TRIM(x)        (((uint32_t)(((uint32_t)(x))<<OCOTP_VTD_TRIM_DRYICE_BGR_TRIM_SHIFT))&OCOTP_VTD_TRIM_DRYICE_BGR_TRIM_MASK)
#define OCOTP_VTD_TRIM_VOLT_MON_DIS_MASK         0x40000000u
#define OCOTP_VTD_TRIM_VOLT_MON_DIS_SHIFT        30
#define OCOTP_VTD_TRIM_TEMP_MON_DIS_MASK         0x80000000u
#define OCOTP_VTD_TRIM_TEMP_MON_DIS_SHIFT        31
/* VTMON Bit Fields */
#define OCOTP_VTMON_DRYICE_PROG_MASK             0x3Fu
#define OCOTP_VTMON_DRYICE_PROG_SHIFT            0
#define OCOTP_VTMON_DRYICE_PROG(x)               (((uint32_t)(((uint32_t)(x))<<OCOTP_VTMON_DRYICE_PROG_SHIFT))&OCOTP_VTMON_DRYICE_PROG_MASK)
#define OCOTP_VTMON_USB1_PID_MASK                0xFFFF0000u
#define OCOTP_VTMON_USB1_PID_SHIFT               16
#define OCOTP_VTMON_USB1_PID(x)                  (((uint32_t)(((uint32_t)(x))<<OCOTP_VTMON_USB1_PID_SHIFT))&OCOTP_VTMON_USB1_PID_MASK)
/* CRC0 Bit Fields */
#define OCOTP_CRC0_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC0_BITS_SHIFT                    0
#define OCOTP_CRC0_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC0_BITS_SHIFT))&OCOTP_CRC0_BITS_MASK)
/* CRC1 Bit Fields */
#define OCOTP_CRC1_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC1_BITS_SHIFT                    0
#define OCOTP_CRC1_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC1_BITS_SHIFT))&OCOTP_CRC1_BITS_MASK)
/* CRC2 Bit Fields */
#define OCOTP_CRC2_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC2_BITS_SHIFT                    0
#define OCOTP_CRC2_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC2_BITS_SHIFT))&OCOTP_CRC2_BITS_MASK)
/* CRC3 Bit Fields */
#define OCOTP_CRC3_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC3_BITS_SHIFT                    0
#define OCOTP_CRC3_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC3_BITS_SHIFT))&OCOTP_CRC3_BITS_MASK)
/* CRC4 Bit Fields */
#define OCOTP_CRC4_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC4_BITS_SHIFT                    0
#define OCOTP_CRC4_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC4_BITS_SHIFT))&OCOTP_CRC4_BITS_MASK)
/* CRC5 Bit Fields */
#define OCOTP_CRC5_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC5_BITS_SHIFT                    0
#define OCOTP_CRC5_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC5_BITS_SHIFT))&OCOTP_CRC5_BITS_MASK)
/* CRC6 Bit Fields */
#define OCOTP_CRC6_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC6_BITS_SHIFT                    0
#define OCOTP_CRC6_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC6_BITS_SHIFT))&OCOTP_CRC6_BITS_MASK)
/* CRC7 Bit Fields */
#define OCOTP_CRC7_BITS_MASK                     0xFFFFFFFFu
#define OCOTP_CRC7_BITS_SHIFT                    0
#define OCOTP_CRC7_BITS(x)                       (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC7_BITS_SHIFT))&OCOTP_CRC7_BITS_MASK)

/**
 * @}
 */ /* end of group OCOTP_Register_Masks */


/* OCOTP - Peripheral instance base addresses */
/** Peripheral OCOTP base address */
#define OCOTP_BASE                               (0x400A5000u)
/** Peripheral OCOTP base pointer */
#define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
/** Array initializer of OCOTP peripheral base pointers */
#define OCOTP_BASES                              { OCOTP }

/**
 * @}
 */ /* end of group OCOTP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PDB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
 * @{
 */

/** PDB - Register Layout Typedef */
typedef struct {
  __IO uint32_t SC;                                /**< Status and Control Register, offset: 0x0 */
  __IO uint32_t MOD;                               /**< Modulus Register, offset: 0x4 */
  __I  uint32_t CNT;                               /**< Counter Register, offset: 0x8 */
  __IO uint32_t IDLY;                              /**< Interrupt Delay Register, offset: 0xC */
  struct {                                         /* offset: 0x10, array step: 0x28 */
    __IO uint32_t C1;                                /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
    __IO uint32_t S;                                 /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */
    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
         uint8_t RESERVED_0[24];
  } CH[2];
       uint8_t RESERVED_0[240];
  __IO uint32_t DACINTC[2];                        /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x4 */
  __IO uint32_t DACINT[2];                         /**< DAC Interval n Register, array offset: 0x154, array step: 0x4 */
} PDB_Type;

/* ----------------------------------------------------------------------------
   -- PDB Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup PDB_Register_Masks PDB Register Masks
 * @{
 */

/* SC Bit Fields */
#define PDB_SC_LDOK_MASK                         0x1u
#define PDB_SC_LDOK_SHIFT                        0
#define PDB_SC_CONT_MASK                         0x2u
#define PDB_SC_CONT_SHIFT                        1
#define PDB_SC_MULT_MASK                         0xCu
#define PDB_SC_MULT_SHIFT                        2
#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
#define PDB_SC_PDBIE_MASK                        0x20u
#define PDB_SC_PDBIE_SHIFT                       5
#define PDB_SC_PDBIF_MASK                        0x40u
#define PDB_SC_PDBIF_SHIFT                       6
#define PDB_SC_PDBEN_MASK                        0x80u
#define PDB_SC_PDBEN_SHIFT                       7
#define PDB_SC_TRGSEL_MASK                       0xF00u
#define PDB_SC_TRGSEL_SHIFT                      8
#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
#define PDB_SC_PRESCALER_MASK                    0x7000u
#define PDB_SC_PRESCALER_SHIFT                   12
#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
#define PDB_SC_DMAEN_MASK                        0x8000u
#define PDB_SC_DMAEN_SHIFT                       15
#define PDB_SC_SWTRIG_MASK                       0x10000u
#define PDB_SC_SWTRIG_SHIFT                      16
#define PDB_SC_PDBEIE_MASK                       0x20000u
#define PDB_SC_PDBEIE_SHIFT                      17
#define PDB_SC_LDMOD_MASK                        0xC0000u
#define PDB_SC_LDMOD_SHIFT                       18
#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
/* MOD Bit Fields */
#define PDB_MOD_MOD_MASK                         0xFFFFu
#define PDB_MOD_MOD_SHIFT                        0
#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
/* CNT Bit Fields */
#define PDB_CNT_CNT_MASK                         0xFFFFu
#define PDB_CNT_CNT_SHIFT                        0
#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
/* IDLY Bit Fields */
#define PDB_IDLY_IDLY_MASK                       0xFFFFu
#define PDB_IDLY_IDLY_SHIFT                      0
#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
/* C1 Bit Fields */
#define PDB_C1_EN_MASK                           0xFFu
#define PDB_C1_EN_SHIFT                          0
#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
#define PDB_C1_TOS_MASK                          0xFF00u
#define PDB_C1_TOS_SHIFT                         8
#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
#define PDB_C1_BB_MASK                           0xFF0000u
#define PDB_C1_BB_SHIFT                          16
#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
/* S Bit Fields */
#define PDB_S_ERR_MASK                           0xFFu
#define PDB_S_ERR_SHIFT                          0
#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
#define PDB_S_CF_MASK                            0xFF0000u
#define PDB_S_CF_SHIFT                           16
#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
/* DLY Bit Fields */
#define PDB_DLY_DLY_MASK                         0xFFFFu
#define PDB_DLY_DLY_SHIFT                        0
#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
/* DACINTC Bit Fields */
#define PDB_DACINTC_TOE_MASK                     0x1u
#define PDB_DACINTC_TOE_SHIFT                    0
#define PDB_DACINTC_EXT_MASK                     0x2u
#define PDB_DACINTC_EXT_SHIFT                    1
/* DACINT Bit Fields */
#define PDB_DACINT_INT_MASK                      0xFFFFu
#define PDB_DACINT_INT_SHIFT                     0
#define PDB_DACINT_INT(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_DACINT_INT_SHIFT))&PDB_DACINT_INT_MASK)

/**
 * @}
 */ /* end of group PDB_Register_Masks */


/* PDB - Peripheral instance base addresses */
/** Peripheral PDB base address */
#define PDB_BASE                                 (0x40036000u)
/** Peripheral PDB base pointer */
#define PDB                                      ((PDB_Type *)PDB_BASE)
/** Array initializer of PDB peripheral base pointers */
#define PDB_BASES                                { PDB }

/**
 * @}
 */ /* end of group PDB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PIT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
 * @{
 */

/** PIT - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
       uint8_t RESERVED_0[220];
  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
       uint8_t RESERVED_1[24];
  struct {                                         /* offset: 0x100, array step: 0x10 */
    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
  } CHANNEL[8];
} PIT_Type;

/* ----------------------------------------------------------------------------
   -- PIT Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup PIT_Register_Masks PIT Register Masks
 * @{
 */

/* MCR Bit Fields */
#define PIT_MCR_FRZ_MASK                         0x1u
#define PIT_MCR_FRZ_SHIFT                        0
#define PIT_MCR_MDIS_MASK                        0x2u
#define PIT_MCR_MDIS_SHIFT                       1
/* LTMR64H Bit Fields */
#define PIT_LTMR64H_LTH_MASK                     0xFFFFFFFFu
#define PIT_LTMR64H_LTH_SHIFT                    0
#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
/* LTMR64L Bit Fields */
#define PIT_LTMR64L_LTL_MASK                     0xFFFFFFFFu
#define PIT_LTMR64L_LTL_SHIFT                    0
#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
/* LDVAL Bit Fields */
#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
#define PIT_LDVAL_TSV_SHIFT                      0
#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
/* CVAL Bit Fields */
#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
#define PIT_CVAL_TVL_SHIFT                       0
#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
/* TCTRL Bit Fields */
#define PIT_TCTRL_TEN_MASK                       0x1u
#define PIT_TCTRL_TEN_SHIFT                      0
#define PIT_TCTRL_TIE_MASK                       0x2u
#define PIT_TCTRL_TIE_SHIFT                      1
#define PIT_TCTRL_CHN_MASK                       0x4u
#define PIT_TCTRL_CHN_SHIFT                      2
/* TFLG Bit Fields */
#define PIT_TFLG_TIF_MASK                        0x1u
#define PIT_TFLG_TIF_SHIFT                       0

/**
 * @}
 */ /* end of group PIT_Register_Masks */


/* PIT - Peripheral instance base addresses */
/** Peripheral PIT base address */
#define PIT_BASE                                 (0x40037000u)
/** Peripheral PIT base pointer */
#define PIT                                      ((PIT_Type *)PIT_BASE)
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASES                                { PIT }

/**
 * @}
 */ /* end of group PIT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PORT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
 * @{
 */

/** PORT - Register Layout Typedef */
typedef struct {
  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[32];
  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
       uint8_t RESERVED_1[28];
  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
} PORT_Type;

/* ----------------------------------------------------------------------------
   -- PORT Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup PORT_Register_Masks PORT Register Masks
 * @{
 */

/* PCR Bit Fields */
#define PORT_PCR_IRQC_MASK                       0xF0000u
#define PORT_PCR_IRQC_SHIFT                      16
#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define PORT_PCR_ISF_MASK                        0x1000000u
#define PORT_PCR_ISF_SHIFT                       24
/* ISFR Bit Fields */
#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
#define PORT_ISFR_ISF_SHIFT                      0
#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
/* DFER Bit Fields */
#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
#define PORT_DFER_DFE_SHIFT                      0
#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
/* DFCR Bit Fields */
#define PORT_DFCR_CS_MASK                        0x1u
#define PORT_DFCR_CS_SHIFT                       0
/* DFWR Bit Fields */
#define PORT_DFWR_FILT_MASK                      0x1Fu
#define PORT_DFWR_FILT_SHIFT                     0
#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)

/**
 * @}
 */ /* end of group PORT_Register_Masks */


/* PORT - Peripheral instance base addresses */
/** Peripheral PORT0 base address */
#define PORT0_BASE                               (0x40049000u)
/** Peripheral PORT0 base pointer */
#define PORT0                                    ((PORT_Type *)PORT0_BASE)
/** Peripheral PORT1 base address */
#define PORT1_BASE                               (0x4004A000u)
/** Peripheral PORT1 base pointer */
#define PORT1                                    ((PORT_Type *)PORT1_BASE)
/** Peripheral PORT2 base address */
#define PORT2_BASE                               (0x4004B000u)
/** Peripheral PORT2 base pointer */
#define PORT2                                    ((PORT_Type *)PORT2_BASE)
/** Peripheral PORT3 base address */
#define PORT3_BASE                               (0x4004C000u)
/** Peripheral PORT3 base pointer */
#define PORT3                                    ((PORT_Type *)PORT3_BASE)
/** Peripheral PORT4 base address */
#define PORT4_BASE                               (0x4004D000u)
/** Peripheral PORT4 base pointer */
#define PORT4                                    ((PORT_Type *)PORT4_BASE)
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASES                               { PORT0, PORT1, PORT2, PORT3, PORT4 }

/**
 * @}
 */ /* end of group PORT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- QuadSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
 * @{
 */

/** QuadSPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t IPCR;                              /**< IP Configuration Register, offset: 0x8 */
  __IO uint32_t FLSHCR;                            /**< Flash Configuration Register, offset: 0xC */
  __IO uint32_t BUF0CR;                            /**< Buffer0 Configuration Register, offset: 0x10 */
  __IO uint32_t BUF1CR;                            /**< Buffer1 Configuration Register, offset: 0x14 */
  __IO uint32_t BUF2CR;                            /**< Buffer2 Configuration Register, offset: 0x18 */
  __IO uint32_t BUF3CR;                            /**< Buffer3 Configuration Register, offset: 0x1C */
  __IO uint32_t BFGENCR;                           /**< Buffer Generic Configuration Register, offset: 0x20 */
  __IO uint32_t SOCCR;                             /**< SOC Configuration Register, offset: 0x24 */
       uint8_t RESERVED_1[8];
  __IO uint32_t BUF0IND;                           /**< Buffer0 Top Index Register, offset: 0x30 */
  __IO uint32_t BUF1IND;                           /**< Buffer1 Top Index Register, offset: 0x34 */
  __IO uint32_t BUF2IND;                           /**< Buffer2 Top Index Register, offset: 0x38 */
       uint8_t RESERVED_2[196];
  __IO uint32_t SFAR;                              /**< Serial Flash Address Register, offset: 0x100 */
       uint8_t RESERVED_3[4];
  __IO uint32_t SMPR;                              /**< Sampling Register, offset: 0x108 */
  __I  uint32_t RBSR;                              /**< RX Buffer Status Register, offset: 0x10C */
  __IO uint32_t RBCT;                              /**< RX Buffer Control Register, offset: 0x110 */
       uint8_t RESERVED_4[60];
  __I  uint32_t TBSR;                              /**< TX Buffer Status Register, offset: 0x150 */
  __IO uint32_t TBDR;                              /**< TX Buffer Data Register, offset: 0x154 */
       uint8_t RESERVED_5[4];
  __I  uint32_t SR;                                /**< Status Register, offset: 0x15C */
  __IO uint32_t FR;                                /**< Flag Register, offset: 0x160 */
  __IO uint32_t RSER;                              /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
  __I  uint32_t SPNDST;                            /**< Sequence Suspend Status Register, offset: 0x168 */
  __IO uint32_t SPTRCLR;                           /**< Sequence Pointer Clear Register, offset: 0x16C */
       uint8_t RESERVED_6[16];
  __IO uint32_t SFA1AD;                            /**< Serial Flash A1 Top Address, offset: 0x180 */
  __IO uint32_t SFA2AD;                            /**< Serial Flash A2 Top Address, offset: 0x184 */
  __IO uint32_t SFB1AD;                            /**< Serial Flash B1Top Address, offset: 0x188 */
  __IO uint32_t SFB2AD;                            /**< Serial Flash B2Top Address, offset: 0x18C */
       uint8_t RESERVED_7[112];
  __IO uint32_t RBDR[32];                              /**< RX Buffer Data Register, offset: 0x200 */
       uint8_t RESERVED_8[128];
  __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x300 */
  __IO uint32_t LCKCR;                             /**< LUT Lock Configuration Register, offset: 0x304 */
       uint8_t RESERVED_9[8];
  __IO uint32_t LUT[64];                           /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
} QuadSPI_Type;

/* ----------------------------------------------------------------------------
   -- QuadSPI Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
 * @{
 */

/* MCR Bit Fields */
#define QuadSPI_MCR_SWRSTSD_MASK                 0x1u
#define QuadSPI_MCR_SWRSTSD_SHIFT                0
#define QuadSPI_MCR_SWRSTHD_MASK                 0x2u
#define QuadSPI_MCR_SWRSTHD_SHIFT                1
#define QuadSPI_MCR_DQS_EN_MASK                  0x40u
#define QuadSPI_MCR_DQS_EN_SHIFT                 6
#define QuadSPI_MCR_DDR_EN_MASK                  0x80u
#define QuadSPI_MCR_DDR_EN_SHIFT                 7
#define QuadSPI_MCR_CLR_RXF_MASK                 0x400u
#define QuadSPI_MCR_CLR_RXF_SHIFT                10
#define QuadSPI_MCR_CLR_TXF_MASK                 0x800u
#define QuadSPI_MCR_CLR_TXF_SHIFT                11
#define QuadSPI_MCR_MDIS_MASK                    0x4000u
#define QuadSPI_MCR_MDIS_SHIFT                   14
#define QuadSPI_MCR_DOZE_MASK                    0x8000u
#define QuadSPI_MCR_DOZE_SHIFT                   15
/* IPCR Bit Fields */
#define QuadSPI_IPCR_IDATSZ_MASK                 0xFFFFu
#define QuadSPI_IPCR_IDATSZ_SHIFT                0
#define QuadSPI_IPCR_IDATSZ(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_IDATSZ_SHIFT))&QuadSPI_IPCR_IDATSZ_MASK)
#define QuadSPI_IPCR_PAR_EN_MASK                 0x10000u
#define QuadSPI_IPCR_PAR_EN_SHIFT                16
#define QuadSPI_IPCR_SEQID_MASK                  0xF000000u
#define QuadSPI_IPCR_SEQID_SHIFT                 24
#define QuadSPI_IPCR_SEQID(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK)
/* FLSHCR Bit Fields */
#define QuadSPI_FLSHCR_TCSS_MASK                 0xFu
#define QuadSPI_FLSHCR_TCSS_SHIFT                0
#define QuadSPI_FLSHCR_TCSS(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSS_SHIFT))&QuadSPI_FLSHCR_TCSS_MASK)
#define QuadSPI_FLSHCR_TCSH_MASK                 0xF00u
#define QuadSPI_FLSHCR_TCSH_SHIFT                8
#define QuadSPI_FLSHCR_TCSH(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK)
/* BUF0CR Bit Fields */
#define QuadSPI_BUF0CR_MSTRID_MASK               0xFu
#define QuadSPI_BUF0CR_MSTRID_SHIFT              0
#define QuadSPI_BUF0CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_MSTRID_SHIFT))&QuadSPI_BUF0CR_MSTRID_MASK)
#define QuadSPI_BUF0CR_ADATSZ_MASK               0xFF00u
#define QuadSPI_BUF0CR_ADATSZ_SHIFT              8
#define QuadSPI_BUF0CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_ADATSZ_SHIFT))&QuadSPI_BUF0CR_ADATSZ_MASK)
#define QuadSPI_BUF0CR_HP_EN_MASK                0x80000000u
#define QuadSPI_BUF0CR_HP_EN_SHIFT               31
/* BUF1CR Bit Fields */
#define QuadSPI_BUF1CR_MSTRID_MASK               0xFu
#define QuadSPI_BUF1CR_MSTRID_SHIFT              0
#define QuadSPI_BUF1CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_MSTRID_SHIFT))&QuadSPI_BUF1CR_MSTRID_MASK)
#define QuadSPI_BUF1CR_ADATSZ_MASK               0xFF00u
#define QuadSPI_BUF1CR_ADATSZ_SHIFT              8
#define QuadSPI_BUF1CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_ADATSZ_SHIFT))&QuadSPI_BUF1CR_ADATSZ_MASK)
/* BUF2CR Bit Fields */
#define QuadSPI_BUF2CR_MSTRID_MASK               0xFu
#define QuadSPI_BUF2CR_MSTRID_SHIFT              0
#define QuadSPI_BUF2CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_MSTRID_SHIFT))&QuadSPI_BUF2CR_MSTRID_MASK)
#define QuadSPI_BUF2CR_ADATSZ_MASK               0xFF00u
#define QuadSPI_BUF2CR_ADATSZ_SHIFT              8
#define QuadSPI_BUF2CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_ADATSZ_SHIFT))&QuadSPI_BUF2CR_ADATSZ_MASK)
/* BUF3CR Bit Fields */
#define QuadSPI_BUF3CR_MSTRID_MASK               0xFu
#define QuadSPI_BUF3CR_MSTRID_SHIFT              0
#define QuadSPI_BUF3CR_MSTRID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_MSTRID_SHIFT))&QuadSPI_BUF3CR_MSTRID_MASK)
#define QuadSPI_BUF3CR_ADATSZ_MASK               0xFF00u
#define QuadSPI_BUF3CR_ADATSZ_SHIFT              8
#define QuadSPI_BUF3CR_ADATSZ(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ADATSZ_SHIFT))&QuadSPI_BUF3CR_ADATSZ_MASK)
#define QuadSPI_BUF3CR_ALLMST_MASK               0x80000000u
#define QuadSPI_BUF3CR_ALLMST_SHIFT              31
/* BFGENCR Bit Fields */
#define QuadSPI_BFGENCR_SEQID_MASK               0xF000u
#define QuadSPI_BFGENCR_SEQID_SHIFT              12
#define QuadSPI_BFGENCR_SEQID(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_BFGENCR_SEQID_SHIFT))&QuadSPI_BFGENCR_SEQID_MASK)
#define QuadSPI_BFGENCR_PAR_EN_MASK              0x10000u
#define QuadSPI_BFGENCR_PAR_EN_SHIFT             16
/* SOCCR Bit Fields */
#define QuadSPI_SOCCR_SOCCFG_MASK                0xFFu
#define QuadSPI_SOCCR_SOCCFG_SHIFT               0
#define QuadSPI_SOCCR_SOCCFG(x)                  (((uint32_t)(((uint32_t)(x))<<QuadSPI_SOCCR_SOCCFG_SHIFT))&QuadSPI_SOCCR_SOCCFG_MASK)
/* BUF0IND Bit Fields */
#define QuadSPI_BUF0IND_TPINDX0_MASK             0xFFFFFFF8u
#define QuadSPI_BUF0IND_TPINDX0_SHIFT            3
#define QuadSPI_BUF0IND_TPINDX0(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0IND_TPINDX0_SHIFT))&QuadSPI_BUF0IND_TPINDX0_MASK)
/* BUF1IND Bit Fields */
#define QuadSPI_BUF1IND_TPINDX1_MASK             0xFFFFFFF8u
#define QuadSPI_BUF1IND_TPINDX1_SHIFT            3
#define QuadSPI_BUF1IND_TPINDX1(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1IND_TPINDX1_SHIFT))&QuadSPI_BUF1IND_TPINDX1_MASK)
/* BUF2IND Bit Fields */
#define QuadSPI_BUF2IND_TPINDX2_MASK             0xFFFFFFF8u
#define QuadSPI_BUF2IND_TPINDX2_SHIFT            3
#define QuadSPI_BUF2IND_TPINDX2(x)               (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK)
/* SFAR Bit Fields */
#define QuadSPI_SFAR_SFADR_MASK                  0xFFFFFFFFu
#define QuadSPI_SFAR_SFADR_SHIFT                 0
#define QuadSPI_SFAR_SFADR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK)
/* SMPR Bit Fields */
#define QuadSPI_SMPR_HSENA_MASK                  0x1u
#define QuadSPI_SMPR_HSENA_SHIFT                 0
#define QuadSPI_SMPR_HSPHS_MASK                  0x2u
#define QuadSPI_SMPR_HSPHS_SHIFT                 1
#define QuadSPI_SMPR_HSDLY_MASK                  0x4u
#define QuadSPI_SMPR_HSDLY_SHIFT                 2
#define QuadSPI_SMPR_FSPHS_MASK                  0x20u
#define QuadSPI_SMPR_FSPHS_SHIFT                 5
#define QuadSPI_SMPR_FSDLY_MASK                  0x40u
#define QuadSPI_SMPR_FSDLY_SHIFT                 6
#define QuadSPI_SMPR_DDRSMP_MASK                 0x70000u
#define QuadSPI_SMPR_DDRSMP_SHIFT                16
#define QuadSPI_SMPR_DDRSMP(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_DDRSMP_SHIFT))&QuadSPI_SMPR_DDRSMP_MASK)
/* RBSR Bit Fields */
#define QuadSPI_RBSR_RDBFL_MASK                  0x3F00u
#define QuadSPI_RBSR_RDBFL_SHIFT                 8
#define QuadSPI_RBSR_RDBFL(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDBFL_SHIFT))&QuadSPI_RBSR_RDBFL_MASK)
#define QuadSPI_RBSR_RDCTR_MASK                  0xFFFF0000u
#define QuadSPI_RBSR_RDCTR_SHIFT                 16
#define QuadSPI_RBSR_RDCTR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDCTR_SHIFT))&QuadSPI_RBSR_RDCTR_MASK)
/* RBCT Bit Fields */
#define QuadSPI_RBCT_WMRK_MASK                   0x1Fu
#define QuadSPI_RBCT_WMRK_SHIFT                  0
#define QuadSPI_RBCT_WMRK(x)                     (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_WMRK_SHIFT))&QuadSPI_RBCT_WMRK_MASK)
#define QuadSPI_RBCT_RXBRD_MASK                  0x100u
#define QuadSPI_RBCT_RXBRD_SHIFT                 8
/* TBSR Bit Fields */
#define QuadSPI_TBSR_TRBFL_MASK                  0x1F00u
#define QuadSPI_TBSR_TRBFL_SHIFT                 8
#define QuadSPI_TBSR_TRBFL(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK)
#define QuadSPI_TBSR_TRCTR_MASK                  0xFFFF0000u
#define QuadSPI_TBSR_TRCTR_SHIFT                 16
#define QuadSPI_TBSR_TRCTR(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRCTR_SHIFT))&QuadSPI_TBSR_TRCTR_MASK)
/* TBDR Bit Fields */
#define QuadSPI_TBDR_TXDATA_MASK                 0xFFFFFFFFu
#define QuadSPI_TBDR_TXDATA_SHIFT                0
#define QuadSPI_TBDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBDR_TXDATA_SHIFT))&QuadSPI_TBDR_TXDATA_MASK)
/* SR Bit Fields */
#define QuadSPI_SR_BUSY_MASK                     0x1u
#define QuadSPI_SR_BUSY_SHIFT                    0
#define QuadSPI_SR_IP_ACC_MASK                   0x2u
#define QuadSPI_SR_IP_ACC_SHIFT                  1
#define QuadSPI_SR_AHB_ACC_MASK                  0x4u
#define QuadSPI_SR_AHB_ACC_SHIFT                 2
#define QuadSPI_SR_AHBGNT_MASK                   0x20u
#define QuadSPI_SR_AHBGNT_SHIFT                  5
#define QuadSPI_SR_AHBTRN_MASK                   0x40u
#define QuadSPI_SR_AHBTRN_SHIFT                  6
#define QuadSPI_SR_AHB0NE_MASK                   0x80u
#define QuadSPI_SR_AHB0NE_SHIFT                  7
#define QuadSPI_SR_AHB1NE_MASK                   0x100u
#define QuadSPI_SR_AHB1NE_SHIFT                  8
#define QuadSPI_SR_AHB2NE_MASK                   0x200u
#define QuadSPI_SR_AHB2NE_SHIFT                  9
#define QuadSPI_SR_AHB3NE_MASK                   0x400u
#define QuadSPI_SR_AHB3NE_SHIFT                  10
#define QuadSPI_SR_AHB0FUL_MASK                  0x800u
#define QuadSPI_SR_AHB0FUL_SHIFT                 11
#define QuadSPI_SR_AHB1FUL_MASK                  0x1000u
#define QuadSPI_SR_AHB1FUL_SHIFT                 12
#define QuadSPI_SR_AHB2FUL_MASK                  0x2000u
#define QuadSPI_SR_AHB2FUL_SHIFT                 13
#define QuadSPI_SR_AHB3FUL_MASK                  0x4000u
#define QuadSPI_SR_AHB3FUL_SHIFT                 14
#define QuadSPI_SR_RXWE_MASK                     0x10000u
#define QuadSPI_SR_RXWE_SHIFT                    16
#define QuadSPI_SR_RXFULL_MASK                   0x80000u
#define QuadSPI_SR_RXFULL_SHIFT                  19
#define QuadSPI_SR_RXDMA_MASK                    0x800000u
#define QuadSPI_SR_RXDMA_SHIFT                   23
#define QuadSPI_SR_TXNE_MASK                     0x1000000u
#define QuadSPI_SR_TXNE_SHIFT                    24
#define QuadSPI_SR_TXFULL_MASK                   0x8000000u
#define QuadSPI_SR_TXFULL_SHIFT                  27
#define QuadSPI_SR_DLPSMP_MASK                   0xE0000000u
#define QuadSPI_SR_DLPSMP_SHIFT                  29
#define QuadSPI_SR_DLPSMP(x)                     (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK)
/* FR Bit Fields */
#define QuadSPI_FR_TFF_MASK                      0x1u
#define QuadSPI_FR_TFF_SHIFT                     0
#define QuadSPI_FR_IPGEF_MASK                    0x10u
#define QuadSPI_FR_IPGEF_SHIFT                   4
#define QuadSPI_FR_IPIEF_MASK                    0x40u
#define QuadSPI_FR_IPIEF_SHIFT                   6
#define QuadSPI_FR_IPAEF_MASK                    0x80u
#define QuadSPI_FR_IPAEF_SHIFT                   7
#define QuadSPI_FR_IUEF_MASK                     0x800u
#define QuadSPI_FR_IUEF_SHIFT                    11
#define QuadSPI_FR_ABOF_MASK                     0x1000u
#define QuadSPI_FR_ABOF_SHIFT                    12
#define QuadSPI_FR_ABSEF_MASK                    0x8000u
#define QuadSPI_FR_ABSEF_SHIFT                   15
#define QuadSPI_FR_RBDF_MASK                     0x10000u
#define QuadSPI_FR_RBDF_SHIFT                    16
#define QuadSPI_FR_RBOF_MASK                     0x20000u
#define QuadSPI_FR_RBOF_SHIFT                    17
#define QuadSPI_FR_ILLINE_MASK                   0x800000u
#define QuadSPI_FR_ILLINE_SHIFT                  23
#define QuadSPI_FR_TBUF_MASK                     0x4000000u
#define QuadSPI_FR_TBUF_SHIFT                    26
#define QuadSPI_FR_TBFF_MASK                     0x8000000u
#define QuadSPI_FR_TBFF_SHIFT                    27
#define QuadSPI_FR_DLPFF_MASK                    0x80000000u
#define QuadSPI_FR_DLPFF_SHIFT                   31
/* RSER Bit Fields */
#define QuadSPI_RSER_TFIE_MASK                   0x1u
#define QuadSPI_RSER_TFIE_SHIFT                  0
#define QuadSPI_RSER_IPGEIE_MASK                 0x10u
#define QuadSPI_RSER_IPGEIE_SHIFT                4
#define QuadSPI_RSER_IPIEIE_MASK                 0x40u
#define QuadSPI_RSER_IPIEIE_SHIFT                6
#define QuadSPI_RSER_IPAEIE_MASK                 0x80u
#define QuadSPI_RSER_IPAEIE_SHIFT                7
#define QuadSPI_RSER_IUEIE_MASK                  0x800u
#define QuadSPI_RSER_IUEIE_SHIFT                 11
#define QuadSPI_RSER_ABOIE_MASK                  0x1000u
#define QuadSPI_RSER_ABOIE_SHIFT                 12
#define QuadSPI_RSER_ABSEIE_MASK                 0x8000u
#define QuadSPI_RSER_ABSEIE_SHIFT                15
#define QuadSPI_RSER_RBDIE_MASK                  0x10000u
#define QuadSPI_RSER_RBDIE_SHIFT                 16
#define QuadSPI_RSER_RBOIE_MASK                  0x20000u
#define QuadSPI_RSER_RBOIE_SHIFT                 17
#define QuadSPI_RSER_RBDDE_MASK                  0x200000u
#define QuadSPI_RSER_RBDDE_SHIFT                 21
#define QuadSPI_RSER_ILLINIE_MASK                0x800000u
#define QuadSPI_RSER_ILLINIE_SHIFT               23
#define QuadSPI_RSER_TBUIE_MASK                  0x4000000u
#define QuadSPI_RSER_TBUIE_SHIFT                 26
#define QuadSPI_RSER_TBFIE_MASK                  0x8000000u
#define QuadSPI_RSER_TBFIE_SHIFT                 27
#define QuadSPI_RSER_DLPFIE_MASK                 0x80000000u
#define QuadSPI_RSER_DLPFIE_SHIFT                31
/* SPNDST Bit Fields */
#define QuadSPI_SPNDST_SUSPND_MASK               0x1u
#define QuadSPI_SPNDST_SUSPND_SHIFT              0
#define QuadSPI_SPNDST_SPDBUF_MASK               0xC0u
#define QuadSPI_SPNDST_SPDBUF_SHIFT              6
#define QuadSPI_SPNDST_SPDBUF(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SPDBUF_SHIFT))&QuadSPI_SPNDST_SPDBUF_MASK)
#define QuadSPI_SPNDST_DATLFT_MASK               0xFE00u
#define QuadSPI_SPNDST_DATLFT_SHIFT              9
#define QuadSPI_SPNDST_DATLFT(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_DATLFT_SHIFT))&QuadSPI_SPNDST_DATLFT_MASK)
/* SPTRCLR Bit Fields */
#define QuadSPI_SPTRCLR_BFPTRC_MASK              0x1u
#define QuadSPI_SPTRCLR_BFPTRC_SHIFT             0
#define QuadSPI_SPTRCLR_IPPTRC_MASK              0x100u
#define QuadSPI_SPTRCLR_IPPTRC_SHIFT             8
/* SFA1AD Bit Fields */
#define QuadSPI_SFA1AD_TPADA1_MASK               0xFFFFFC00u
#define QuadSPI_SFA1AD_TPADA1_SHIFT              10
#define QuadSPI_SFA1AD_TPADA1(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA1AD_TPADA1_SHIFT))&QuadSPI_SFA1AD_TPADA1_MASK)
/* SFA2AD Bit Fields */
#define QuadSPI_SFA2AD_TPADA2_MASK               0xFFFFFC00u
#define QuadSPI_SFA2AD_TPADA2_SHIFT              10
#define QuadSPI_SFA2AD_TPADA2(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA2AD_TPADA2_SHIFT))&QuadSPI_SFA2AD_TPADA2_MASK)
/* SFB1AD Bit Fields */
#define QuadSPI_SFB1AD_TPADB1_MASK               0xFFFFFC00u
#define QuadSPI_SFB1AD_TPADB1_SHIFT              10
#define QuadSPI_SFB1AD_TPADB1(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB1AD_TPADB1_SHIFT))&QuadSPI_SFB1AD_TPADB1_MASK)
/* SFB2AD Bit Fields */
#define QuadSPI_SFB2AD_TPADB2_MASK               0xFFFFFC00u
#define QuadSPI_SFB2AD_TPADB2_SHIFT              10
#define QuadSPI_SFB2AD_TPADB2(x)                 (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB2AD_TPADB2_SHIFT))&QuadSPI_SFB2AD_TPADB2_MASK)
/* RBDR Bit Fields */
#define QuadSPI_RBDR_RXDATA_MASK                 0xFFFFFFFFu
#define QuadSPI_RBDR_RXDATA_SHIFT                0
#define QuadSPI_RBDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBDR_RXDATA_SHIFT))&QuadSPI_RBDR_RXDATA_MASK)
/* LUTKEY Bit Fields */
#define QuadSPI_LUTKEY_KEY_MASK                  0xFFFFFFFFu
#define QuadSPI_LUTKEY_KEY_SHIFT                 0
#define QuadSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUTKEY_KEY_SHIFT))&QuadSPI_LUTKEY_KEY_MASK)
/* LCKCR Bit Fields */
#define QuadSPI_LCKCR_LOCK_MASK                  0x1u
#define QuadSPI_LCKCR_LOCK_SHIFT                 0
#define QuadSPI_LCKCR_UNLOCK_MASK                0x2u
#define QuadSPI_LCKCR_UNLOCK_SHIFT               1
/* LUT Bit Fields */
#define QuadSPI_LUT_OPRND0_MASK                  0xFFu
#define QuadSPI_LUT_OPRND0_SHIFT                 0
#define QuadSPI_LUT_OPRND0(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND0_SHIFT))&QuadSPI_LUT_OPRND0_MASK)
#define QuadSPI_LUT_PAD0_MASK                    0x300u
#define QuadSPI_LUT_PAD0_SHIFT                   8
#define QuadSPI_LUT_PAD0(x)                      (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD0_SHIFT))&QuadSPI_LUT_PAD0_MASK)
#define QuadSPI_LUT_INSTR0_MASK                  0xFC00u
#define QuadSPI_LUT_INSTR0_SHIFT                 10
#define QuadSPI_LUT_INSTR0(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR0_SHIFT))&QuadSPI_LUT_INSTR0_MASK)
#define QuadSPI_LUT_OPRND1_MASK                  0xFF0000u
#define QuadSPI_LUT_OPRND1_SHIFT                 16
#define QuadSPI_LUT_OPRND1(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND1_SHIFT))&QuadSPI_LUT_OPRND1_MASK)
#define QuadSPI_LUT_PAD1_MASK                    0x3000000u
#define QuadSPI_LUT_PAD1_SHIFT                   24
#define QuadSPI_LUT_PAD1(x)                      (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD1_SHIFT))&QuadSPI_LUT_PAD1_MASK)
#define QuadSPI_LUT_INSTR1_MASK                  0xFC000000u
#define QuadSPI_LUT_INSTR1_SHIFT                 26
#define QuadSPI_LUT_INSTR1(x)                    (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR1_SHIFT))&QuadSPI_LUT_INSTR1_MASK)

/**
 * @}
 */ /* end of group QuadSPI_Register_Masks */


/* QuadSPI - Peripheral instance base addresses */
/** Peripheral QuadSPI0 base address */
#define QuadSPI0_BASE                            (0x40044000u)
/** Peripheral QuadSPI0 base pointer */
#define QuadSPI0                                 ((QuadSPI_Type *)QuadSPI0_BASE)
/** Peripheral QuadSPI1 base address */
#define QuadSPI1_BASE                            (0x400C4000u)
/** Peripheral QuadSPI1 base pointer */
#define QuadSPI1                                 ((QuadSPI_Type *)QuadSPI1_BASE)
/** Array initializer of QuadSPI peripheral base pointers */
#define QuadSPI_BASES                            { QuadSPI0, QuadSPI1 }

/**
 * @}
 */ /* end of group QuadSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RLE_DEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup RLE_DEC_Peripheral_Access_Layer RLE_DEC Peripheral Access Layer
 * @{
 */

/** RLE_DEC - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
  __IO uint32_t ICR;                               /**< Image Configuration Register, offset: 0x4 */
  __IO uint32_t CISR;                              /**< Compressed Image Size Register, offset: 0x8 */
  __IO uint32_t DICR;                              /**< Decompressed Image Co-ordinates register, offset: 0xC */
  __IO uint32_t SR;                                /**< Status Register, offset: 0x10 */
  __IO uint32_t ISR;                               /**< Interrupt Request Status Register, offset: 0x14 */
  __IO uint32_t RIER;                              /**< Interrupt Request Enable Register, offset: 0x18 */
  __IO uint32_t SPCR;                              /**< Start Pixel Co-ordinate Register of Image, offset: 0x1C */
  __IO uint32_t EPCR;                              /**< End Pixel Co-ordinate Register of Image, offset: 0x20 */
} RLE_DEC_Type;

/* ----------------------------------------------------------------------------
   -- RLE_DEC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup RLE_DEC_Register_Masks RLE_DEC Register Masks
 * @{
 */

/* MCR Bit Fields */
#define RLE_DEC_MCR_MDIS_MASK                    0x1u
#define RLE_DEC_MCR_MDIS_SHIFT                   0
#define RLE_DEC_MCR_TXFFEN_MASK                  0x4u
#define RLE_DEC_MCR_TXFFEN_SHIFT                 2
#define RLE_DEC_MCR_GRLE_EN_MASK                 0x8u
#define RLE_DEC_MCR_GRLE_EN_SHIFT                3
#define RLE_DEC_MCR_TX_FIFO_THRESHOLD_MASK       0xFF0000u
#define RLE_DEC_MCR_TX_FIFO_THRESHOLD_SHIFT      16
#define RLE_DEC_MCR_TX_FIFO_THRESHOLD(x)         (((uint32_t)(((uint32_t)(x))<<RLE_DEC_MCR_TX_FIFO_THRESHOLD_SHIFT))&RLE_DEC_MCR_TX_FIFO_THRESHOLD_MASK)
#define RLE_DEC_MCR_RX_FIFO_THRESHOLD_MASK       0xFF000000u
#define RLE_DEC_MCR_RX_FIFO_THRESHOLD_SHIFT      24
#define RLE_DEC_MCR_RX_FIFO_THRESHOLD(x)         (((uint32_t)(((uint32_t)(x))<<RLE_DEC_MCR_RX_FIFO_THRESHOLD_SHIFT))&RLE_DEC_MCR_RX_FIFO_THRESHOLD_MASK)
/* ICR Bit Fields */
#define RLE_DEC_ICR_WIDTH_MASK                   0x3u
#define RLE_DEC_ICR_WIDTH_SHIFT                  0
#define RLE_DEC_ICR_WIDTH(x)                     (((uint32_t)(((uint32_t)(x))<<RLE_DEC_ICR_WIDTH_SHIFT))&RLE_DEC_ICR_WIDTH_MASK)
/* CISR Bit Fields */
#define RLE_DEC_CISR_SIZE_MASK                   0xFFFFFFFFu
#define RLE_DEC_CISR_SIZE_SHIFT                  0
#define RLE_DEC_CISR_SIZE(x)                     (((uint32_t)(((uint32_t)(x))<<RLE_DEC_CISR_SIZE_SHIFT))&RLE_DEC_CISR_SIZE_MASK)
/* DICR Bit Fields */
#define RLE_DEC_DICR_Y_MASK                      0xFFFFu
#define RLE_DEC_DICR_Y_SHIFT                     0
#define RLE_DEC_DICR_Y(x)                        (((uint32_t)(((uint32_t)(x))<<RLE_DEC_DICR_Y_SHIFT))&RLE_DEC_DICR_Y_MASK)
#define RLE_DEC_DICR_X_MASK                      0xFFFF0000u
#define RLE_DEC_DICR_X_SHIFT                     16
#define RLE_DEC_DICR_X(x)                        (((uint32_t)(((uint32_t)(x))<<RLE_DEC_DICR_X_SHIFT))&RLE_DEC_DICR_X_MASK)
/* SR Bit Fields */
#define RLE_DEC_SR_TXFILL_MASK                   0xFFu
#define RLE_DEC_SR_TXFILL_SHIFT                  0
#define RLE_DEC_SR_TXFILL(x)                     (((uint32_t)(((uint32_t)(x))<<RLE_DEC_SR_TXFILL_SHIFT))&RLE_DEC_SR_TXFILL_MASK)
#define RLE_DEC_SR_RXFREE_MASK                   0xFF00u
#define RLE_DEC_SR_RXFREE_SHIFT                  8
#define RLE_DEC_SR_RXFREE(x)                     (((uint32_t)(((uint32_t)(x))<<RLE_DEC_SR_RXFREE_SHIFT))&RLE_DEC_SR_RXFREE_MASK)
/* ISR Bit Fields */
#define RLE_DEC_ISR_TXEIF_MASK                   0x1u
#define RLE_DEC_ISR_TXEIF_SHIFT                  0
#define RLE_DEC_ISR_RXEIF_MASK                   0x2u
#define RLE_DEC_ISR_RXEIF_SHIFT                  1
#define RLE_DEC_ISR_TXFIF_MASK                   0x4u
#define RLE_DEC_ISR_TXFIF_SHIFT                  2
#define RLE_DEC_ISR_RXFIF_MASK                   0x8u
#define RLE_DEC_ISR_RXFIF_SHIFT                  3
#define RLE_DEC_ISR_TXUIF_MASK                   0x10u
#define RLE_DEC_ISR_TXUIF_SHIFT                  4
#define RLE_DEC_ISR_RXUIF_MASK                   0x20u
#define RLE_DEC_ISR_RXUIF_SHIFT                  5
#define RLE_DEC_ISR_TXDIF_MASK                   0x40u
#define RLE_DEC_ISR_TXDIF_SHIFT                  6
#define RLE_DEC_ISR_RXDIF_MASK                   0x80u
#define RLE_DEC_ISR_RXDIF_SHIFT                  7
/* RIER Bit Fields */
#define RLE_DEC_RIER_TXEIE_MASK                  0x1u
#define RLE_DEC_RIER_TXEIE_SHIFT                 0
#define RLE_DEC_RIER_RXEIE_MASK                  0x2u
#define RLE_DEC_RIER_RXEIE_SHIFT                 1
#define RLE_DEC_RIER_TXFIE_MASK                  0x4u
#define RLE_DEC_RIER_TXFIE_SHIFT                 2
#define RLE_DEC_RIER_RXFIE_MASK                  0x8u
#define RLE_DEC_RIER_RXFIE_SHIFT                 3
#define RLE_DEC_RIER_TXUIE_MASK                  0x10u
#define RLE_DEC_RIER_TXUIE_SHIFT                 4
#define RLE_DEC_RIER_RXUIE_MASK                  0x20u
#define RLE_DEC_RIER_RXUIE_SHIFT                 5
#define RLE_DEC_RIER_TXDIE_MASK                  0x40u
#define RLE_DEC_RIER_TXDIE_SHIFT                 6
#define RLE_DEC_RIER_RXDIE_MASK                  0x80u
#define RLE_DEC_RIER_RXDIE_SHIFT                 7
/* SPCR Bit Fields */
#define RLE_DEC_SPCR_Y_MASK                      0xFFFFu
#define RLE_DEC_SPCR_Y_SHIFT                     0
#define RLE_DEC_SPCR_Y(x)                        (((uint32_t)(((uint32_t)(x))<<RLE_DEC_SPCR_Y_SHIFT))&RLE_DEC_SPCR_Y_MASK)
#define RLE_DEC_SPCR_X_MASK                      0xFFFF0000u
#define RLE_DEC_SPCR_X_SHIFT                     16
#define RLE_DEC_SPCR_X(x)                        (((uint32_t)(((uint32_t)(x))<<RLE_DEC_SPCR_X_SHIFT))&RLE_DEC_SPCR_X_MASK)
/* EPCR Bit Fields */
#define RLE_DEC_EPCR_Y_MASK                      0xFFFFu
#define RLE_DEC_EPCR_Y_SHIFT                     0
#define RLE_DEC_EPCR_Y(x)                        (((uint32_t)(((uint32_t)(x))<<RLE_DEC_EPCR_Y_SHIFT))&RLE_DEC_EPCR_Y_MASK)
#define RLE_DEC_EPCR_X_MASK                      0xFFFF0000u
#define RLE_DEC_EPCR_X_SHIFT                     16
#define RLE_DEC_EPCR_X(x)                        (((uint32_t)(((uint32_t)(x))<<RLE_DEC_EPCR_X_SHIFT))&RLE_DEC_EPCR_X_MASK)

/**
 * @}
 */ /* end of group RLE_DEC_Register_Masks */


/* RLE_DEC - Peripheral instance base addresses */
/** Peripheral RLE_DEC base address */
#define RLE_DEC_BASE                             (0x40042000u)
/** Peripheral RLE_DEC base pointer */
#define RLE_DEC                                  ((RLE_DEC_Type *)RLE_DEC_BASE)
/** Array initializer of RLE_DEC peripheral base pointers */
#define RLE_DEC_BASES                            { RLE_DEC }

/**
 * @}
 */ /* end of group RLE_DEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCSC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SCSC_Peripheral_Access_Layer SCSC Peripheral Access Layer
 * @{
 */

/** SCSC - Register Layout Typedef */
typedef struct {
  __IO uint32_t SIRC_CTR;                          /**< SIRC Control Register, offset: 0x0 */
  __IO uint32_t SOSC_CTR;                          /**< SOSC Control, offset: 0x4 */
  __IO uint32_t LFSR_CTR;                          /**< LFSR Control Register, offset: 0x8 */
} SCSC_Type;

/* ----------------------------------------------------------------------------
   -- SCSC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SCSC_Register_Masks SCSC Register Masks
 * @{
 */

/* SIRC_CTR Bit Fields */
#define SCSC_SIRC_CTR_SIRC_EN_MASK               0x1u
#define SCSC_SIRC_CTR_SIRC_EN_SHIFT              0
#define SCSC_SIRC_CTR_SIRC_EN_ON_FAIL_MASK       0x10u
#define SCSC_SIRC_CTR_SIRC_EN_ON_FAIL_SHIFT      4
#define SCSC_SIRC_CTR_SIRC_DIV_MASK              0x7F00u
#define SCSC_SIRC_CTR_SIRC_DIV_SHIFT             8
#define SCSC_SIRC_CTR_SIRC_DIV(x)                (((uint32_t)(((uint32_t)(x))<<SCSC_SIRC_CTR_SIRC_DIV_SHIFT))&SCSC_SIRC_CTR_SIRC_DIV_MASK)
#define SCSC_SIRC_CTR_Reseved_MASK               0xFFFF8000u
#define SCSC_SIRC_CTR_Reseved_SHIFT              15
#define SCSC_SIRC_CTR_Reseved(x)                 (((uint32_t)(((uint32_t)(x))<<SCSC_SIRC_CTR_Reseved_SHIFT))&SCSC_SIRC_CTR_Reseved_MASK)
/* SOSC_CTR Bit Fields */
#define SCSC_SOSC_CTR_SOSC_EN_MASK               0x1u
#define SCSC_SOSC_CTR_SOSC_EN_SHIFT              0
#define SCSC_SOSC_CTR_SOSC_BYPASS_MASK           0x10u
#define SCSC_SOSC_CTR_SOSC_BYPASS_SHIFT          4
/* LFSR_CTR Bit Fields */
#define SCSC_LFSR_CTR_TAMPER0_INV_MASK           0x10u
#define SCSC_LFSR_CTR_TAMPER0_INV_SHIFT          4
#define SCSC_LFSR_CTR_TAMPER1_INV_MASK           0x20u
#define SCSC_LFSR_CTR_TAMPER1_INV_SHIFT          5
#define SCSC_LFSR_CTR_TAMPER2_INV_MASK           0x40u
#define SCSC_LFSR_CTR_TAMPER2_INV_SHIFT          6
#define SCSC_LFSR_CTR_TAMPER3_INV_MASK           0x80u
#define SCSC_LFSR_CTR_TAMPER3_INV_SHIFT          7
#define SCSC_LFSR_CTR_TAMPER4_INV_MASK           0x100u
#define SCSC_LFSR_CTR_TAMPER4_INV_SHIFT          8
#define SCSC_LFSR_CTR_TAMPER5_INV_MASK           0x200u
#define SCSC_LFSR_CTR_TAMPER5_INV_SHIFT          9
#define SCSC_LFSR_CTR_ACTIVE_SEL_2_3_MASK        0x400u
#define SCSC_LFSR_CTR_ACTIVE_SEL_2_3_SHIFT       10
#define SCSC_LFSR_CTR_ACTIVE_SEL_4_5_MASK        0x800u
#define SCSC_LFSR_CTR_ACTIVE_SEL_4_5_SHIFT       11
#define SCSC_LFSR_CTR_LFSR0_SEED_MASK            0x1000u
#define SCSC_LFSR_CTR_LFSR0_SEED_SHIFT           12
#define SCSC_LFSR_CTR_LFSR1_SEED_MASK            0x2000u
#define SCSC_LFSR_CTR_LFSR1_SEED_SHIFT           13
#define SCSC_LFSR_CTR_EN_TZASC_VIO_MASK          0x4000u
#define SCSC_LFSR_CTR_EN_TZASC_VIO_SHIFT         14
#define SCSC_LFSR_CTR_POLY_LFSR_MASK             0xFFFF0000u
#define SCSC_LFSR_CTR_POLY_LFSR_SHIFT            16
#define SCSC_LFSR_CTR_POLY_LFSR(x)               (((uint32_t)(((uint32_t)(x))<<SCSC_LFSR_CTR_POLY_LFSR_SHIFT))&SCSC_LFSR_CTR_POLY_LFSR_MASK)

/**
 * @}
 */ /* end of group SCSC_Register_Masks */


/* SCSC - Peripheral instance base addresses */
/** Peripheral SCSC base address */
#define SCSC_BASE                                (0x40052000u)
/** Peripheral SCSC base pointer */
#define SCSC                                     ((SCSC_Type *)SCSC_BASE)
/** Array initializer of SCSC peripheral base pointers */
#define SCSC_BASES                               { SCSC }

/**
 * @}
 */ /* end of group SCSC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SDHC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
 * @{
 */

/** SDHC - Register Layout Typedef */
typedef struct {
  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
  __IO uint32_t WML;                               /**< Watermark Level register, offset: 0x44 */
       uint8_t RESERVED_0[8];
  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
       uint8_t RESERVED_1[100];
  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
       uint8_t RESERVED_2[52];
  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
} SDHC_Type;

/* ----------------------------------------------------------------------------
   -- SDHC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SDHC_Register_Masks SDHC Register Masks
 * @{
 */

/* DSADDR Bit Fields */
#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
#define SDHC_DSADDR_DSADDR_SHIFT                 2
#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
/* BLKATTR Bit Fields */
#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
#define SDHC_BLKATTR_BLKCNT_SHIFT                16
#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
/* CMDARG Bit Fields */
#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
#define SDHC_CMDARG_CMDARG_SHIFT                 0
#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
/* XFERTYP Bit Fields */
#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
#define SDHC_XFERTYP_DMAEN_SHIFT                 0
#define SDHC_XFERTYP_BCEN_MASK                   0x2u
#define SDHC_XFERTYP_BCEN_SHIFT                  1
#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
#define SDHC_XFERTYP_AC12EN_SHIFT                2
#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
#define SDHC_XFERTYP_DTDSEL_SHIFT                4
#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
#define SDHC_XFERTYP_MSBSEL_SHIFT                5
#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
#define SDHC_XFERTYP_RSPTYP_SHIFT                16
#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
#define SDHC_XFERTYP_CCCEN_SHIFT                 19
#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
#define SDHC_XFERTYP_CICEN_SHIFT                 20
#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
#define SDHC_XFERTYP_DPSEL_SHIFT                 21
#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
#define SDHC_XFERTYP_CMDTYP_SHIFT                22
#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
#define SDHC_XFERTYP_CMDINX_SHIFT                24
#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
/* CMDRSP Bit Fields */
#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
/* DATPORT Bit Fields */
#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
#define SDHC_DATPORT_DATCONT_SHIFT               0
#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
/* PRSSTAT Bit Fields */
#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
#define SDHC_PRSSTAT_CIHB_SHIFT                  0
#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
#define SDHC_PRSSTAT_DLA_MASK                    0x4u
#define SDHC_PRSSTAT_DLA_SHIFT                   2
#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
#define SDHC_PRSSTAT_PEROFF_SHIFT                6
#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
#define SDHC_PRSSTAT_WTA_MASK                    0x100u
#define SDHC_PRSSTAT_WTA_SHIFT                   8
#define SDHC_PRSSTAT_RTA_MASK                    0x200u
#define SDHC_PRSSTAT_RTA_SHIFT                   9
#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
#define SDHC_PRSSTAT_BWEN_SHIFT                  10
#define SDHC_PRSSTAT_BREN_MASK                   0x800u
#define SDHC_PRSSTAT_BREN_SHIFT                  11
#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
#define SDHC_PRSSTAT_CINS_SHIFT                  16
#define SDHC_PRSSTAT_CDPL_MASK                   0x40000u
#define SDHC_PRSSTAT_CDPL_SHIFT                  18
#define SDHC_PRSSTAT_WPSPL_MASK                  0x80000u
#define SDHC_PRSSTAT_WPSPL_SHIFT                 19
#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
#define SDHC_PRSSTAT_CLSL_SHIFT                  23
#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
#define SDHC_PRSSTAT_DLSL_SHIFT                  24
#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
/* PROCTL Bit Fields */
#define SDHC_PROCTL_LCTL_MASK                    0x1u
#define SDHC_PROCTL_LCTL_SHIFT                   0
#define SDHC_PROCTL_DTW_MASK                     0x6u
#define SDHC_PROCTL_DTW_SHIFT                    1
#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
#define SDHC_PROCTL_D3CD_MASK                    0x8u
#define SDHC_PROCTL_D3CD_SHIFT                   3
#define SDHC_PROCTL_EMODE_MASK                   0x30u
#define SDHC_PROCTL_EMODE_SHIFT                  4
#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
#define SDHC_PROCTL_CDTL_MASK                    0x40u
#define SDHC_PROCTL_CDTL_SHIFT                   6
#define SDHC_PROCTL_CDSS_MASK                    0x80u
#define SDHC_PROCTL_CDSS_SHIFT                   7
#define SDHC_PROCTL_DMAS_MASK                    0x300u
#define SDHC_PROCTL_DMAS_SHIFT                   8
#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
#define SDHC_PROCTL_SABGREQ_SHIFT                16
#define SDHC_PROCTL_CREQ_MASK                    0x20000u
#define SDHC_PROCTL_CREQ_SHIFT                   17
#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
#define SDHC_PROCTL_RWCTL_SHIFT                  18
#define SDHC_PROCTL_IABG_MASK                    0x80000u
#define SDHC_PROCTL_IABG_SHIFT                   19
#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
#define SDHC_PROCTL_WECINT_SHIFT                 24
#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
#define SDHC_PROCTL_WECINS_SHIFT                 25
#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
#define SDHC_PROCTL_WECRM_SHIFT                  26
/* SYSCTL Bit Fields */
#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
#define SDHC_SYSCTL_IPGEN_SHIFT                  0
#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
#define SDHC_SYSCTL_HCKEN_SHIFT                  1
#define SDHC_SYSCTL_PEREN_MASK                   0x4u
#define SDHC_SYSCTL_PEREN_SHIFT                  2
#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
#define SDHC_SYSCTL_DVS_MASK                     0xF0u
#define SDHC_SYSCTL_DVS_SHIFT                    4
#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
#define SDHC_SYSCTL_DTOCV_SHIFT                  16
#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
#define SDHC_SYSCTL_RSTA_SHIFT                   24
#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
#define SDHC_SYSCTL_RSTC_SHIFT                   25
#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
#define SDHC_SYSCTL_RSTD_SHIFT                   26
#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
#define SDHC_SYSCTL_INITA_SHIFT                  27
/* IRQSTAT Bit Fields */
#define SDHC_IRQSTAT_CC_MASK                     0x1u
#define SDHC_IRQSTAT_CC_SHIFT                    0
#define SDHC_IRQSTAT_TC_MASK                     0x2u
#define SDHC_IRQSTAT_TC_SHIFT                    1
#define SDHC_IRQSTAT_BGE_MASK                    0x4u
#define SDHC_IRQSTAT_BGE_SHIFT                   2
#define SDHC_IRQSTAT_DINT_MASK                   0x8u
#define SDHC_IRQSTAT_DINT_SHIFT                  3
#define SDHC_IRQSTAT_BWR_MASK                    0x10u
#define SDHC_IRQSTAT_BWR_SHIFT                   4
#define SDHC_IRQSTAT_BRR_MASK                    0x20u
#define SDHC_IRQSTAT_BRR_SHIFT                   5
#define SDHC_IRQSTAT_CINS_MASK                   0x40u
#define SDHC_IRQSTAT_CINS_SHIFT                  6
#define SDHC_IRQSTAT_CRM_MASK                    0x80u
#define SDHC_IRQSTAT_CRM_SHIFT                   7
#define SDHC_IRQSTAT_CINT_MASK                   0x100u
#define SDHC_IRQSTAT_CINT_SHIFT                  8
#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
#define SDHC_IRQSTAT_CTOE_SHIFT                  16
#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
#define SDHC_IRQSTAT_CCE_SHIFT                   17
#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
#define SDHC_IRQSTAT_CEBE_SHIFT                  18
#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
#define SDHC_IRQSTAT_CIE_SHIFT                   19
#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
#define SDHC_IRQSTAT_DTOE_SHIFT                  20
#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
#define SDHC_IRQSTAT_DCE_SHIFT                   21
#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
#define SDHC_IRQSTAT_DEBE_SHIFT                  22
#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
#define SDHC_IRQSTAT_AC12E_SHIFT                 24
#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
#define SDHC_IRQSTAT_DMAE_SHIFT                  28
/* IRQSTATEN Bit Fields */
#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
/* IRQSIGEN Bit Fields */
#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
/* AC12ERR Bit Fields */
#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
#define SDHC_AC12ERR_AC12NE_SHIFT                0
#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
#define SDHC_AC12ERR_AC12TOE_SHIFT               1
#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
#define SDHC_AC12ERR_AC12EBE_SHIFT               2
#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
#define SDHC_AC12ERR_AC12CE_SHIFT                3
#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
#define SDHC_AC12ERR_AC12IE_SHIFT                4
#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
/* HTCAPBLT Bit Fields */
#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
#define SDHC_HTCAPBLT_MBL_SHIFT                  16
#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
#define SDHC_HTCAPBLT_HSS_SHIFT                  21
#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
#define SDHC_HTCAPBLT_SRS_SHIFT                  23
#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
#define SDHC_HTCAPBLT_VS33_SHIFT                 24
/* WML Bit Fields */
#define SDHC_WML_RDWML_MASK                      0xFFu
#define SDHC_WML_RDWML_SHIFT                     0
#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
#define SDHC_WML_RDBRSTLEN_MASK                  0x1F00u
#define SDHC_WML_RDBRSTLEN_SHIFT                 8
#define SDHC_WML_RDBRSTLEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDBRSTLEN_SHIFT))&SDHC_WML_RDBRSTLEN_MASK)
#define SDHC_WML_WRWML_MASK                      0xFF0000u
#define SDHC_WML_WRWML_SHIFT                     16
#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
#define SDHC_WML_WRBRSTLEN_MASK                  0x1F000000u
#define SDHC_WML_WRBRSTLEN_SHIFT                 24
#define SDHC_WML_WRBRSTLEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRBRSTLEN_SHIFT))&SDHC_WML_WRBRSTLEN_MASK)
/* FEVT Bit Fields */
#define SDHC_FEVT_AC12NE_MASK                    0x1u
#define SDHC_FEVT_AC12NE_SHIFT                   0
#define SDHC_FEVT_AC12TOE_MASK                   0x2u
#define SDHC_FEVT_AC12TOE_SHIFT                  1
#define SDHC_FEVT_AC12CE_MASK                    0x4u
#define SDHC_FEVT_AC12CE_SHIFT                   2
#define SDHC_FEVT_AC12EBE_MASK                   0x8u
#define SDHC_FEVT_AC12EBE_SHIFT                  3
#define SDHC_FEVT_AC12IE_MASK                    0x10u
#define SDHC_FEVT_AC12IE_SHIFT                   4
#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
#define SDHC_FEVT_CNIBAC12E_SHIFT                7
#define SDHC_FEVT_CTOE_MASK                      0x10000u
#define SDHC_FEVT_CTOE_SHIFT                     16
#define SDHC_FEVT_CCE_MASK                       0x20000u
#define SDHC_FEVT_CCE_SHIFT                      17
#define SDHC_FEVT_CEBE_MASK                      0x40000u
#define SDHC_FEVT_CEBE_SHIFT                     18
#define SDHC_FEVT_CIE_MASK                       0x80000u
#define SDHC_FEVT_CIE_SHIFT                      19
#define SDHC_FEVT_DTOE_MASK                      0x100000u
#define SDHC_FEVT_DTOE_SHIFT                     20
#define SDHC_FEVT_DCE_MASK                       0x200000u
#define SDHC_FEVT_DCE_SHIFT                      21
#define SDHC_FEVT_DEBE_MASK                      0x400000u
#define SDHC_FEVT_DEBE_SHIFT                     22
#define SDHC_FEVT_AC12E_MASK                     0x1000000u
#define SDHC_FEVT_AC12E_SHIFT                    24
#define SDHC_FEVT_DMAE_MASK                      0x10000000u
#define SDHC_FEVT_DMAE_SHIFT                     28
#define SDHC_FEVT_CINT_MASK                      0x80000000u
#define SDHC_FEVT_CINT_SHIFT                     31
/* ADMAES Bit Fields */
#define SDHC_ADMAES_ADMAES_MASK                  0x3u
#define SDHC_ADMAES_ADMAES_SHIFT                 0
#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
#define SDHC_ADMAES_ADMALME_MASK                 0x4u
#define SDHC_ADMAES_ADMALME_SHIFT                2
#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
#define SDHC_ADMAES_ADMADCE_SHIFT                3
/* ADSADDR Bit Fields */
#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
#define SDHC_ADSADDR_ADSADDR_SHIFT               2
#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
/* VENDOR Bit Fields */
#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
#define SDHC_VENDOR_EXBLKNU_SHIFT                1
#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
#define SDHC_VENDOR_INTSTVAL_SHIFT               16
#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
/* MMCBOOT Bit Fields */
#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
/* HOSTVER Bit Fields */
#define SDHC_HOSTVER_SVN_MASK                    0xFFu
#define SDHC_HOSTVER_SVN_SHIFT                   0
#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
#define SDHC_HOSTVER_VVN_SHIFT                   8
#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)

/**
 * @}
 */ /* end of group SDHC_Register_Masks */


/* SDHC - Peripheral instance base addresses */
/** Peripheral SDHC0 base address */
#define SDHC0_BASE                               (0x400B1000u)
/** Peripheral SDHC0 base pointer */
#define SDHC0                                    ((SDHC_Type *)SDHC0_BASE)
/** Peripheral SDHC1 base address */
#define SDHC1_BASE                               (0x400B2000u)
/** Peripheral SDHC1 base pointer */
#define SDHC1                                    ((SDHC_Type *)SDHC1_BASE)
/** Array initializer of SDHC peripheral base pointers */
#define SDHC_BASES                               { SDHC0, SDHC1 }

/**
 * @}
 */ /* end of group SDHC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SEMA4 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
 * @{
 */

/** SEMA4 - Register Layout Typedef */
typedef struct {
#if 1
	__IO uint8_t GATE[16];							/* Much easier to use in code - match EAR3 MQX release header*/
#else
	/* original implementation */
  __IO uint8_t Gate00;                             /**< Semaphores Gate 0 Register, offset: 0x0 */
  __IO uint8_t Gate01;                             /**< Semaphores Gate 1 Register, offset: 0x1 */
  __IO uint8_t Gate02;                             /**< Semaphores Gate 2 Register, offset: 0x2 */
  __IO uint8_t Gate03;                             /**< Semaphores Gate 3 Register, offset: 0x3 */
  __IO uint8_t Gate04;                             /**< Semaphores Gate 4 Register, offset: 0x4 */
  __IO uint8_t Gate05;                             /**< Semaphores Gate 5 Register, offset: 0x5 */
  __IO uint8_t Gate06;                             /**< Semaphores Gate 6 Register, offset: 0x6 */
  __IO uint8_t Gate07;                             /**< Semaphores Gate 7 Register, offset: 0x7 */
  __IO uint8_t Gate08;                             /**< Semaphores Gate 8 Register, offset: 0x8 */
  __IO uint8_t Gate09;                             /**< Semaphores Gate 9 Register, offset: 0x9 */
  __IO uint8_t Gate10;                             /**< Semaphores Gate 10 Register, offset: 0xA */
  __IO uint8_t Gate11;                             /**< Semaphores Gate 11 Register, offset: 0xB */
  __IO uint8_t Gate12;                             /**< Semaphores Gate 12 Register, offset: 0xC */
  __IO uint8_t Gate13;                             /**< Semaphores Gate 13 Register, offset: 0xD */
  __IO uint8_t Gate14;                             /**< Semaphores Gate 14 Register, offset: 0xE */
  __IO uint8_t Gate15;                             /**< Semaphores Gate 15 Register, offset: 0xF */
#endif
       uint8_t RESERVED_0[48];	/** this is 50 in MQX EAR3 release ?? **/
  __IO uint16_t CP0INE;                            /**< Semaphores Processor n IRQ Notification Enable, offset: 0x40 */
       uint8_t RESERVED_1[6];
  __IO uint16_t CP1INE;                            /**< Semaphores Processor n IRQ Notification Enable, offset: 0x48 */
       uint8_t RESERVED_2[54];
  __IO uint16_t CP0NTF;                            /**< Semaphores Processor n IRQ Notification, offset: 0x80 */
       uint8_t RESERVED_3[6];
  __IO uint16_t CP1NTF;                            /**< Semaphores Processor n IRQ Notification, offset: 0x88 */
       uint8_t RESERVED_4[118];
  __IO uint16_t RSTGT;                             /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
       uint8_t RESERVED_5[2];
  __IO uint16_t RSTNTF;                            /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
} SEMA4_Type;

/* ----------------------------------------------------------------------------
   -- SEMA4 Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
 * @{
 */

/* Gate00 Bit Fields */
#define SEMA4_Gate00_GTFSM_MASK                  0x3u
#define SEMA4_Gate00_GTFSM_SHIFT                 0
#define SEMA4_Gate00_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate00_GTFSM_SHIFT))&SEMA4_Gate00_GTFSM_MASK)
/* Gate01 Bit Fields */
#define SEMA4_Gate01_GTFSM_MASK                  0x3u
#define SEMA4_Gate01_GTFSM_SHIFT                 0
#define SEMA4_Gate01_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate01_GTFSM_SHIFT))&SEMA4_Gate01_GTFSM_MASK)
/* Gate02 Bit Fields */
#define SEMA4_Gate02_GTFSM_MASK                  0x3u
#define SEMA4_Gate02_GTFSM_SHIFT                 0
#define SEMA4_Gate02_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate02_GTFSM_SHIFT))&SEMA4_Gate02_GTFSM_MASK)
/* Gate03 Bit Fields */
#define SEMA4_Gate03_GTFSM_MASK                  0x3u
#define SEMA4_Gate03_GTFSM_SHIFT                 0
#define SEMA4_Gate03_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate03_GTFSM_SHIFT))&SEMA4_Gate03_GTFSM_MASK)
/* Gate04 Bit Fields */
#define SEMA4_Gate04_GTFSM_MASK                  0x3u
#define SEMA4_Gate04_GTFSM_SHIFT                 0
#define SEMA4_Gate04_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate04_GTFSM_SHIFT))&SEMA4_Gate04_GTFSM_MASK)
/* Gate05 Bit Fields */
#define SEMA4_Gate05_GTFSM_MASK                  0x3u
#define SEMA4_Gate05_GTFSM_SHIFT                 0
#define SEMA4_Gate05_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate05_GTFSM_SHIFT))&SEMA4_Gate05_GTFSM_MASK)
/* Gate06 Bit Fields */
#define SEMA4_Gate06_GTFSM_MASK                  0x3u
#define SEMA4_Gate06_GTFSM_SHIFT                 0
#define SEMA4_Gate06_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate06_GTFSM_SHIFT))&SEMA4_Gate06_GTFSM_MASK)
/* Gate07 Bit Fields */
#define SEMA4_Gate07_GTFSM_MASK                  0x3u
#define SEMA4_Gate07_GTFSM_SHIFT                 0
#define SEMA4_Gate07_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate07_GTFSM_SHIFT))&SEMA4_Gate07_GTFSM_MASK)
/* Gate08 Bit Fields */
#define SEMA4_Gate08_GTFSM_MASK                  0x3u
#define SEMA4_Gate08_GTFSM_SHIFT                 0
#define SEMA4_Gate08_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate08_GTFSM_SHIFT))&SEMA4_Gate08_GTFSM_MASK)
/* Gate09 Bit Fields */
#define SEMA4_Gate09_GTFSM_MASK                  0x3u
#define SEMA4_Gate09_GTFSM_SHIFT                 0
#define SEMA4_Gate09_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate09_GTFSM_SHIFT))&SEMA4_Gate09_GTFSM_MASK)
/* Gate10 Bit Fields */
#define SEMA4_Gate10_GTFSM_MASK                  0x3u
#define SEMA4_Gate10_GTFSM_SHIFT                 0
#define SEMA4_Gate10_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate10_GTFSM_SHIFT))&SEMA4_Gate10_GTFSM_MASK)
/* Gate11 Bit Fields */
#define SEMA4_Gate11_GTFSM_MASK                  0x3u
#define SEMA4_Gate11_GTFSM_SHIFT                 0
#define SEMA4_Gate11_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate11_GTFSM_SHIFT))&SEMA4_Gate11_GTFSM_MASK)
/* Gate12 Bit Fields */
#define SEMA4_Gate12_GTFSM_MASK                  0x3u
#define SEMA4_Gate12_GTFSM_SHIFT                 0
#define SEMA4_Gate12_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate12_GTFSM_SHIFT))&SEMA4_Gate12_GTFSM_MASK)
/* Gate13 Bit Fields */
#define SEMA4_Gate13_GTFSM_MASK                  0x3u
#define SEMA4_Gate13_GTFSM_SHIFT                 0
#define SEMA4_Gate13_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate13_GTFSM_SHIFT))&SEMA4_Gate13_GTFSM_MASK)
/* Gate14 Bit Fields */
#define SEMA4_Gate14_GTFSM_MASK                  0x3u
#define SEMA4_Gate14_GTFSM_SHIFT                 0
#define SEMA4_Gate14_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate14_GTFSM_SHIFT))&SEMA4_Gate14_GTFSM_MASK)
/* Gate15 Bit Fields */
#define SEMA4_Gate15_GTFSM_MASK                  0x3u
#define SEMA4_Gate15_GTFSM_SHIFT                 0
#define SEMA4_Gate15_GTFSM(x)                    (((uint8_t)(((uint8_t)(x))<<SEMA4_Gate15_GTFSM_SHIFT))&SEMA4_Gate15_GTFSM_MASK)
/* CP0INE Bit Fields */
#define SEMA4_CP0INE_INE15_MASK                  0x1u
#define SEMA4_CP0INE_INE15_SHIFT                 0
#define SEMA4_CP0INE_INE14_MASK                  0x2u
#define SEMA4_CP0INE_INE14_SHIFT                 1
#define SEMA4_CP0INE_INE13_MASK                  0x4u
#define SEMA4_CP0INE_INE13_SHIFT                 2
#define SEMA4_CP0INE_INE12_MASK                  0x8u
#define SEMA4_CP0INE_INE12_SHIFT                 3
#define SEMA4_CP0INE_INE11_MASK                  0x10u
#define SEMA4_CP0INE_INE11_SHIFT                 4
#define SEMA4_CP0INE_INE10_MASK                  0x20u
#define SEMA4_CP0INE_INE10_SHIFT                 5
#define SEMA4_CP0INE_INE9_MASK                   0x40u
#define SEMA4_CP0INE_INE9_SHIFT                  6
#define SEMA4_CP0INE_INE8_MASK                   0x80u
#define SEMA4_CP0INE_INE8_SHIFT                  7
#define SEMA4_CP0INE_INE7_MASK                   0x100u
#define SEMA4_CP0INE_INE7_SHIFT                  8
#define SEMA4_CP0INE_INE6_MASK                   0x200u
#define SEMA4_CP0INE_INE6_SHIFT                  9
#define SEMA4_CP0INE_INE5_MASK                   0x400u
#define SEMA4_CP0INE_INE5_SHIFT                  10
#define SEMA4_CP0INE_INE4_MASK                   0x800u
#define SEMA4_CP0INE_INE4_SHIFT                  11
#define SEMA4_CP0INE_INE3_MASK                   0x1000u
#define SEMA4_CP0INE_INE3_SHIFT                  12
#define SEMA4_CP0INE_INE2_MASK                   0x2000u
#define SEMA4_CP0INE_INE2_SHIFT                  13
#define SEMA4_CP0INE_INE1_MASK                   0x4000u
#define SEMA4_CP0INE_INE1_SHIFT                  14
#define SEMA4_CP0INE_INE0_MASK                   0x8000u
#define SEMA4_CP0INE_INE0_SHIFT                  15
/* CP1INE Bit Fields */
#define SEMA4_CP1INE_INE15_MASK                  0x1u
#define SEMA4_CP1INE_INE15_SHIFT                 0
#define SEMA4_CP1INE_INE14_MASK                  0x2u
#define SEMA4_CP1INE_INE14_SHIFT                 1
#define SEMA4_CP1INE_INE13_MASK                  0x4u
#define SEMA4_CP1INE_INE13_SHIFT                 2
#define SEMA4_CP1INE_INE12_MASK                  0x8u
#define SEMA4_CP1INE_INE12_SHIFT                 3
#define SEMA4_CP1INE_INE11_MASK                  0x10u
#define SEMA4_CP1INE_INE11_SHIFT                 4
#define SEMA4_CP1INE_INE10_MASK                  0x20u
#define SEMA4_CP1INE_INE10_SHIFT                 5
#define SEMA4_CP1INE_INE9_MASK                   0x40u
#define SEMA4_CP1INE_INE9_SHIFT                  6
#define SEMA4_CP1INE_INE8_MASK                   0x80u
#define SEMA4_CP1INE_INE8_SHIFT                  7
#define SEMA4_CP1INE_INE7_MASK                   0x100u
#define SEMA4_CP1INE_INE7_SHIFT                  8
#define SEMA4_CP1INE_INE6_MASK                   0x200u
#define SEMA4_CP1INE_INE6_SHIFT                  9
#define SEMA4_CP1INE_INE5_MASK                   0x400u
#define SEMA4_CP1INE_INE5_SHIFT                  10
#define SEMA4_CP1INE_INE4_MASK                   0x800u
#define SEMA4_CP1INE_INE4_SHIFT                  11
#define SEMA4_CP1INE_INE3_MASK                   0x1000u
#define SEMA4_CP1INE_INE3_SHIFT                  12
#define SEMA4_CP1INE_INE2_MASK                   0x2000u
#define SEMA4_CP1INE_INE2_SHIFT                  13
#define SEMA4_CP1INE_INE1_MASK                   0x4000u
#define SEMA4_CP1INE_INE1_SHIFT                  14
#define SEMA4_CP1INE_INE0_MASK                   0x8000u
#define SEMA4_CP1INE_INE0_SHIFT                  15
/* CP0NTF Bit Fields */
#define SEMA4_CP0NTF_GNn_MASK                    0xFFFFu
#define SEMA4_CP0NTF_GNn_SHIFT                   0
#define SEMA4_CP0NTF_GNn(x)                      (((uint16_t)(((uint16_t)(x))<<SEMA4_CP0NTF_GNn_SHIFT))&SEMA4_CP0NTF_GNn_MASK)
/* CP1NTF Bit Fields */
#define SEMA4_CP1NTF_GNn_MASK                    0xFFFFu
#define SEMA4_CP1NTF_GNn_SHIFT                   0
#define SEMA4_CP1NTF_GNn(x)                      (((uint16_t)(((uint16_t)(x))<<SEMA4_CP1NTF_GNn_SHIFT))&SEMA4_CP1NTF_GNn_MASK)
/* RSTGT Bit Fields */
#define SEMA4_RSTGT_RSTGTN_MASK                  0xFFu
#define SEMA4_RSTGT_RSTGTN_SHIFT                 0
#define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGTN_SHIFT))&SEMA4_RSTGT_RSTGTN_MASK)
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    0xFF00u
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   8
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT))&SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
/* RSTNTF Bit Fields */
#define SEMA4_RSTNTF_RSTNTN_MASK                 0xFFu
#define SEMA4_RSTNTF_RSTNTN_SHIFT                0
#define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNTN_SHIFT))&SEMA4_RSTNTF_RSTNTN_MASK)
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   0xFF00u
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  8
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT))&SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)

/**
 * @}
 */ /* end of group SEMA4_Register_Masks */


/* SEMA4 - Peripheral instance base addresses */
/** Peripheral SEMA4 base address */
#define SEMA4_BASE                               (0x4001D000u)
/** Peripheral SEMA4 base pointer */
#define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
/** Array initializer of SEMA4 peripheral base pointers */
#define SEMA4_BASES                              { SEMA4 }

/**
 * @}
 */ /* end of group SEMA4_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SNVS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
 * @{
 */

/** SNVS - Register Layout Typedef */
typedef struct {
  __IO uint32_t HPLR;                              /**< SNVS_HP Lock Register, offset: 0x0 */
  __IO uint32_t HPCOMR;                            /**< SNVS_HP Command Register, offset: 0x4 */
  __IO uint32_t HPCR;                              /**< SNVS_HP Control Register, offset: 0x8 */
  __IO uint32_t HPSICR;                            /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
  __IO uint32_t HPSVCR;                            /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
  __IO uint32_t HPSR;                              /**< SNVS_HP Status Register, offset: 0x14 */
  __IO uint32_t HPSVSR;                            /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
  __IO uint32_t HPHACIVR;                          /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
  __IO uint32_t HPHACR;                            /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
  __IO uint32_t HPRTCMR;                           /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
  __IO uint32_t HPRTCLR;                           /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
  __IO uint32_t HPTAMR;                            /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
  __IO uint32_t HPTALR;                            /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
  __IO uint32_t LPLR;                              /**< SNVS_LP Lock Register, offset: 0x34 */
  __IO uint32_t LPCR;                              /**< SNVS_LP Control Register, offset: 0x38 */
  __IO uint32_t LPMKCR;                            /**< SNVS_LP Master Key Control Register, offset: 0x3C */
  __IO uint32_t LPSVCR;                            /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
  __IO uint32_t LPTGFCR;                           /**< SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44 */
  __IO uint32_t LPTDCR;                            /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */
  __IO uint32_t LPSR;                              /**< SNVS_LP Status Register, offset: 0x4C */
  __IO uint32_t LPSRTCMR;                          /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
  __IO uint32_t LPSRTCLR;                          /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
  __IO uint32_t LPTAR;                             /**< SNVS_LP Time Alarm Register, offset: 0x58 */
  __IO uint32_t LPSMCMR;                           /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
  __IO uint32_t LPSMCLR;                           /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
  __IO uint32_t LPPGDR;                            /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
  __IO uint32_t LPGPR;                             /**< SNVS_LP General Purpose Register, offset: 0x68 */
  __IO uint32_t LPZMKR[8];                         /**< SNVS_LP Zeroizable Master Key Register n, array offset: 0x6C, array step: 0x4 */
       uint8_t RESERVED_0[2924];
  __I  uint32_t HPVIDR1;                           /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
  __I  uint32_t HPVIDR2;                           /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
} SNVS_Type;

/* ----------------------------------------------------------------------------
   -- SNVS Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SNVS_Register_Masks SNVS Register Masks
 * @{
 */

/* HPLR Bit Fields */
#define SNVS_HPLR_ZMK_WSL_MASK                   0x1u
#define SNVS_HPLR_ZMK_WSL_SHIFT                  0
#define SNVS_HPLR_ZMK_RSL_MASK                   0x2u
#define SNVS_HPLR_ZMK_RSL_SHIFT                  1
#define SNVS_HPLR_SRTC_SL_MASK                   0x4u
#define SNVS_HPLR_SRTC_SL_SHIFT                  2
#define SNVS_HPLR_LPCALB_SL_MASK                 0x8u
#define SNVS_HPLR_LPCALB_SL_SHIFT                3
#define SNVS_HPLR_MC_SL_MASK                     0x10u
#define SNVS_HPLR_MC_SL_SHIFT                    4
#define SNVS_HPLR_GPR_SL_MASK                    0x20u
#define SNVS_HPLR_GPR_SL_SHIFT                   5
#define SNVS_HPLR_LPSVCR_SL_MASK                 0x40u
#define SNVS_HPLR_LPSVCR_SL_SHIFT                6
#define SNVS_HPLR_LPTGFCR_SL_MASK                0x80u
#define SNVS_HPLR_LPTGFCR_SL_SHIFT               7
#define SNVS_HPLR_LPTDCR_SL_MASK                 0x100u
#define SNVS_HPLR_LPTDCR_SL_SHIFT                8
#define SNVS_HPLR_MKS_SL_MASK                    0x200u
#define SNVS_HPLR_MKS_SL_SHIFT                   9
#define SNVS_HPLR_HPSVCR_L_MASK                  0x10000u
#define SNVS_HPLR_HPSVCR_L_SHIFT                 16
#define SNVS_HPLR_HPSICR_L_MASK                  0x20000u
#define SNVS_HPLR_HPSICR_L_SHIFT                 17
#define SNVS_HPLR_HAC_L_MASK                     0x40000u
#define SNVS_HPLR_HAC_L_SHIFT                    18
/* HPCOMR Bit Fields */
#define SNVS_HPCOMR_SSM_ST_MASK                  0x1u
#define SNVS_HPCOMR_SSM_ST_SHIFT                 0
#define SNVS_HPCOMR_SSM_ST_DIS_MASK              0x2u
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT             1
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK            0x4u
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT           2
#define SNVS_HPCOMR_LP_SWR_MASK                  0x10u
#define SNVS_HPCOMR_LP_SWR_SHIFT                 4
#define SNVS_HPCOMR_LP_SWR_DIS_MASK              0x20u
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             5
#define SNVS_HPCOMR_SW_SV_MASK                   0x100u
#define SNVS_HPCOMR_SW_SV_SHIFT                  8
#define SNVS_HPCOMR_SW_FSV_MASK                  0x200u
#define SNVS_HPCOMR_SW_FSV_SHIFT                 9
#define SNVS_HPCOMR_SW_LPSV_MASK                 0x400u
#define SNVS_HPCOMR_SW_LPSV_SHIFT                10
#define SNVS_HPCOMR_PROG_ZMK_MASK                0x1000u
#define SNVS_HPCOMR_PROG_ZMK_SHIFT               12
#define SNVS_HPCOMR_MKS_EN_MASK                  0x2000u
#define SNVS_HPCOMR_MKS_EN_SHIFT                 13
#define SNVS_HPCOMR_HAC_EN_MASK                  0x10000u
#define SNVS_HPCOMR_HAC_EN_SHIFT                 16
#define SNVS_HPCOMR_HAC_LOAD_MASK                0x20000u
#define SNVS_HPCOMR_HAC_LOAD_SHIFT               17
#define SNVS_HPCOMR_HAC_CLEAR_MASK               0x40000u
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT              18
#define SNVS_HPCOMR_HAC_STOP_MASK                0x80000u
#define SNVS_HPCOMR_HAC_STOP_SHIFT               19
#define SNVS_HPCOMR_NPSWA_EN_MASK                0x80000000u
#define SNVS_HPCOMR_NPSWA_EN_SHIFT               31
/* HPCR Bit Fields */
#define SNVS_HPCR_RTC_EN_MASK                    0x1u
#define SNVS_HPCR_RTC_EN_SHIFT                   0
#define SNVS_HPCR_HPTA_EN_MASK                   0x2u
#define SNVS_HPCR_HPTA_EN_SHIFT                  1
#define SNVS_HPCR_PI_EN_MASK                     0x8u
#define SNVS_HPCR_PI_EN_SHIFT                    3
#define SNVS_HPCR_PI_FREQ_MASK                   0xF0u
#define SNVS_HPCR_PI_FREQ_SHIFT                  4
#define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_PI_FREQ_SHIFT))&SNVS_HPCR_PI_FREQ_MASK)
#define SNVS_HPCR_HPCALB_EN_MASK                 0x100u
#define SNVS_HPCR_HPCALB_EN_SHIFT                8
#define SNVS_HPCR_HPCALB_VAL_MASK                0x7C00u
#define SNVS_HPCR_HPCALB_VAL_SHIFT               10
#define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_HPCALB_VAL_SHIFT))&SNVS_HPCR_HPCALB_VAL_MASK)
#define SNVS_HPCR_HP_TS_MASK                     0x10000u
#define SNVS_HPCR_HP_TS_SHIFT                    16
/* HPSICR Bit Fields */
#define SNVS_HPSICR_SVI_EN0_MASK                 0x1u
#define SNVS_HPSICR_SVI_EN0_SHIFT                0
#define SNVS_HPSICR_SVI_EN1_MASK                 0x2u
#define SNVS_HPSICR_SVI_EN1_SHIFT                1
#define SNVS_HPSICR_SVI_EN2_MASK                 0x4u
#define SNVS_HPSICR_SVI_EN2_SHIFT                2
#define SNVS_HPSICR_SVI_EN3_MASK                 0x8u
#define SNVS_HPSICR_SVI_EN3_SHIFT                3
#define SNVS_HPSICR_SVI_EN4_MASK                 0x10u
#define SNVS_HPSICR_SVI_EN4_SHIFT                4
#define SNVS_HPSICR_SVI_EN5_MASK                 0x20u
#define SNVS_HPSICR_SVI_EN5_SHIFT                5
#define SNVS_HPSICR_LPSVI_EN_MASK                0x80000000u
#define SNVS_HPSICR_LPSVI_EN_SHIFT               31
/* HPSVCR Bit Fields */
#define SNVS_HPSVCR_SV_CFG0_MASK                 0x1u
#define SNVS_HPSVCR_SV_CFG0_SHIFT                0
#define SNVS_HPSVCR_SV_CFG1_MASK                 0x2u
#define SNVS_HPSVCR_SV_CFG1_SHIFT                1
#define SNVS_HPSVCR_SV_CFG2_MASK                 0x4u
#define SNVS_HPSVCR_SV_CFG2_SHIFT                2
#define SNVS_HPSVCR_SV_CFG3_MASK                 0x8u
#define SNVS_HPSVCR_SV_CFG3_SHIFT                3
#define SNVS_HPSVCR_SV_CFG4_MASK                 0x10u
#define SNVS_HPSVCR_SV_CFG4_SHIFT                4
#define SNVS_HPSVCR_SV_CFG5_MASK                 0x60u
#define SNVS_HPSVCR_SV_CFG5_SHIFT                5
#define SNVS_HPSVCR_SV_CFG5(x)                   (((uint32_t)(((uint32_t)(x))<<SNVS_HPSVCR_SV_CFG5_SHIFT))&SNVS_HPSVCR_SV_CFG5_MASK)
#define SNVS_HPSVCR_LPSV_CFG_MASK                0xC0000000u
#define SNVS_HPSVCR_LPSV_CFG_SHIFT               30
#define SNVS_HPSVCR_LPSV_CFG(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPSVCR_LPSV_CFG_SHIFT))&SNVS_HPSVCR_LPSV_CFG_MASK)
/* HPSR Bit Fields */
#define SNVS_HPSR_HPTA_MASK                      0x1u
#define SNVS_HPSR_HPTA_SHIFT                     0
#define SNVS_HPSR_PI_MASK                        0x2u
#define SNVS_HPSR_PI_SHIFT                       1
#define SNVS_HPSR_LPDIS_MASK                     0x10u
#define SNVS_HPSR_LPDIS_SHIFT                    4
#define SNVS_HPSR_SSM_ST_MASK                    0xF00u
#define SNVS_HPSR_SSM_ST_SHIFT                   8
#define SNVS_HPSR_SSM_ST(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPSR_SSM_ST_SHIFT))&SNVS_HPSR_SSM_ST_MASK)
#define SNVS_HPSR_SYS_SECURITY_CFG_MASK          0x7000u
#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT         12
#define SNVS_HPSR_SYS_SECURITY_CFG(x)            (((uint32_t)(((uint32_t)(x))<<SNVS_HPSR_SYS_SECURITY_CFG_SHIFT))&SNVS_HPSR_SYS_SECURITY_CFG_MASK)
#define SNVS_HPSR_SYS_SECURE_BOOT_MASK           0x8000u
#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT          15
#define SNVS_HPSR_OTPMK_SYNDROME_MASK            0x1FF0000u
#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT           16
#define SNVS_HPSR_OTPMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_HPSR_OTPMK_SYNDROME_SHIFT))&SNVS_HPSR_OTPMK_SYNDROME_MASK)
#define SNVS_HPSR_OTPMK_ZERO_MASK                0x8000000u
#define SNVS_HPSR_OTPMK_ZERO_SHIFT               27
#define SNVS_HPSR_ZMK_ZERO_MASK                  0x80000000u
#define SNVS_HPSR_ZMK_ZERO_SHIFT                 31
/* HPSVSR Bit Fields */
#define SNVS_HPSVSR_SEC_VIO0_MASK                0x1u
#define SNVS_HPSVSR_SEC_VIO0_SHIFT               0
#define SNVS_HPSVSR_SEC_VIO1_MASK                0x2u
#define SNVS_HPSVSR_SEC_VIO1_SHIFT               1
#define SNVS_HPSVSR_SEC_VIO2_MASK                0x4u
#define SNVS_HPSVSR_SEC_VIO2_SHIFT               2
#define SNVS_HPSVSR_SEC_VIO3_MASK                0x8u
#define SNVS_HPSVSR_SEC_VIO3_SHIFT               3
#define SNVS_HPSVSR_SEC_VIO4_MASK                0x10u
#define SNVS_HPSVSR_SEC_VIO4_SHIFT               4
#define SNVS_HPSVSR_SEC_VIO5_MASK                0x20u
#define SNVS_HPSVSR_SEC_VIO5_SHIFT               5
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK            0x1FF0000u
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT           16
#define SNVS_HPSVSR_ZMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_HPSVSR_ZMK_SYNDROME_SHIFT))&SNVS_HPSVSR_ZMK_SYNDROME_MASK)
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK            0x8000000u
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT           27
/* HPHACIVR Bit Fields */
#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK        0xFFFFFFFFu
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT       0
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x)          (((uint32_t)(((uint32_t)(x))<<SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT))&SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
/* HPHACR Bit Fields */
#define SNVS_HPHACR_HAC_COUNTER_MASK             0xFFFFFFFFu
#define SNVS_HPHACR_HAC_COUNTER_SHIFT            0
#define SNVS_HPHACR_HAC_COUNTER(x)               (((uint32_t)(((uint32_t)(x))<<SNVS_HPHACR_HAC_COUNTER_SHIFT))&SNVS_HPHACR_HAC_COUNTER_MASK)
/* HPRTCMR Bit Fields */
#define SNVS_HPRTCMR_RTC_MASK                    0x7FFFu
#define SNVS_HPRTCMR_RTC_SHIFT                   0
#define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCMR_RTC_SHIFT))&SNVS_HPRTCMR_RTC_MASK)
/* HPRTCLR Bit Fields */
#define SNVS_HPRTCLR_RTC_MASK                    0xFFFFFFFFu
#define SNVS_HPRTCLR_RTC_SHIFT                   0
#define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCLR_RTC_SHIFT))&SNVS_HPRTCLR_RTC_MASK)
/* HPTAMR Bit Fields */
#define SNVS_HPTAMR_HPTA_MASK                    0x7FFFu
#define SNVS_HPTAMR_HPTA_SHIFT                   0
#define SNVS_HPTAMR_HPTA(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPTAMR_HPTA_SHIFT))&SNVS_HPTAMR_HPTA_MASK)
/* HPTALR Bit Fields */
#define SNVS_HPTALR_HPTA_MASK                    0xFFFFFFFFu
#define SNVS_HPTALR_HPTA_SHIFT                   0
#define SNVS_HPTALR_HPTA(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_HPTALR_HPTA_SHIFT))&SNVS_HPTALR_HPTA_MASK)
/* LPLR Bit Fields */
#define SNVS_LPLR_ZMK_WHL_MASK                   0x1u
#define SNVS_LPLR_ZMK_WHL_SHIFT                  0
#define SNVS_LPLR_ZMK_RHL_MASK                   0x2u
#define SNVS_LPLR_ZMK_RHL_SHIFT                  1
#define SNVS_LPLR_SRTC_HL_MASK                   0x4u
#define SNVS_LPLR_SRTC_HL_SHIFT                  2
#define SNVS_LPLR_LPCALB_HL_MASK                 0x8u
#define SNVS_LPLR_LPCALB_HL_SHIFT                3
#define SNVS_LPLR_MC_HL_MASK                     0x10u
#define SNVS_LPLR_MC_HL_SHIFT                    4
#define SNVS_LPLR_GPR_HL_MASK                    0x20u
#define SNVS_LPLR_GPR_HL_SHIFT                   5
#define SNVS_LPLR_LPSVCR_HL_MASK                 0x40u
#define SNVS_LPLR_LPSVCR_HL_SHIFT                6
#define SNVS_LPLR_LPTGFCR_HL_MASK                0x80u
#define SNVS_LPLR_LPTGFCR_HL_SHIFT               7
#define SNVS_LPLR_LPTDCR_HL_MASK                 0x100u
#define SNVS_LPLR_LPTDCR_HL_SHIFT                8
#define SNVS_LPLR_MKS_HL_MASK                    0x200u
#define SNVS_LPLR_MKS_HL_SHIFT                   9
/* LPCR Bit Fields */
#define SNVS_LPCR_SRTC_ENV_MASK                  0x1u
#define SNVS_LPCR_SRTC_ENV_SHIFT                 0
#define SNVS_LPCR_LPTA_EN_MASK                   0x2u
#define SNVS_LPCR_LPTA_EN_SHIFT                  1
#define SNVS_LPCR_MC_ENV_MASK                    0x4u
#define SNVS_LPCR_MC_ENV_SHIFT                   2
#define SNVS_LPCR_LPWUI_EN_MASK                  0x8u
#define SNVS_LPCR_LPWUI_EN_SHIFT                 3
#define SNVS_LPCR_SRTC_INV_EN_MASK               0x10u
#define SNVS_LPCR_SRTC_INV_EN_SHIFT              4
#define SNVS_LPCR_DP_EN_MASK                     0x20u
#define SNVS_LPCR_DP_EN_SHIFT                    5
#define SNVS_LPCR_TOP_MASK                       0x40u
#define SNVS_LPCR_TOP_SHIFT                      6
#define SNVS_LPCR_LPCALB_EN_MASK                 0x100u
#define SNVS_LPCR_LPCALB_EN_SHIFT                8
#define SNVS_LPCR_LPCALB_VAL_MASK                0x7C00u
#define SNVS_LPCR_LPCALB_VAL_SHIFT               10
#define SNVS_LPCR_LPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_LPCALB_VAL_SHIFT))&SNVS_LPCR_LPCALB_VAL_MASK)
/* LPMKCR Bit Fields */
#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK          0x3u
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT         0
#define SNVS_LPMKCR_MASTER_KEY_SEL(x)            (((uint32_t)(((uint32_t)(x))<<SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT))&SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
#define SNVS_LPMKCR_ZMK_HWP_MASK                 0x4u
#define SNVS_LPMKCR_ZMK_HWP_SHIFT                2
#define SNVS_LPMKCR_ZMK_VAL_MASK                 0x8u
#define SNVS_LPMKCR_ZMK_VAL_SHIFT                3
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK              0x10u
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT             4
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK           0xFF80u
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT          7
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x)             (((uint32_t)(((uint32_t)(x))<<SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT))&SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
/* LPSVCR Bit Fields */
#define SNVS_LPSVCR_SV_EN0_MASK                  0x1u
#define SNVS_LPSVCR_SV_EN0_SHIFT                 0
#define SNVS_LPSVCR_SV_EN1_MASK                  0x2u
#define SNVS_LPSVCR_SV_EN1_SHIFT                 1
#define SNVS_LPSVCR_SV_EN2_MASK                  0x4u
#define SNVS_LPSVCR_SV_EN2_SHIFT                 2
#define SNVS_LPSVCR_SV_EN3_MASK                  0x8u
#define SNVS_LPSVCR_SV_EN3_SHIFT                 3
#define SNVS_LPSVCR_SV_EN4_MASK                  0x10u
#define SNVS_LPSVCR_SV_EN4_SHIFT                 4
#define SNVS_LPSVCR_SV_EN5_MASK                  0x20u
#define SNVS_LPSVCR_SV_EN5_SHIFT                 5
/* LPTGFCR Bit Fields */
#define SNVS_LPTGFCR_WMTGF_MASK                  0x1Fu
#define SNVS_LPTGFCR_WMTGF_SHIFT                 0
#define SNVS_LPTGFCR_WMTGF(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPTGFCR_WMTGF_SHIFT))&SNVS_LPTGFCR_WMTGF_MASK)
#define SNVS_LPTGFCR_WMTGF_EN_MASK               0x80u
#define SNVS_LPTGFCR_WMTGF_EN_SHIFT              7
#define SNVS_LPTGFCR_ETGF1_MASK                  0x1F0000u
#define SNVS_LPTGFCR_ETGF1_SHIFT                 16
#define SNVS_LPTGFCR_ETGF1(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPTGFCR_ETGF1_SHIFT))&SNVS_LPTGFCR_ETGF1_MASK)
#define SNVS_LPTGFCR_ETGF1_EN_MASK               0x800000u
#define SNVS_LPTGFCR_ETGF1_EN_SHIFT              23
#define SNVS_LPTGFCR_ETGF2_MASK                  0x1F000000u
#define SNVS_LPTGFCR_ETGF2_SHIFT                 24
#define SNVS_LPTGFCR_ETGF2(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPTGFCR_ETGF2_SHIFT))&SNVS_LPTGFCR_ETGF2_MASK)
#define SNVS_LPTGFCR_ETGF2_EN_MASK               0x80000000u
#define SNVS_LPTGFCR_ETGF2_EN_SHIFT              31
/* LPTDCR Bit Fields */
#define SNVS_LPTDCR_SRTCR_EN_MASK                0x2u
#define SNVS_LPTDCR_SRTCR_EN_SHIFT               1
#define SNVS_LPTDCR_MCR_EN_MASK                  0x4u
#define SNVS_LPTDCR_MCR_EN_SHIFT                 2
#define SNVS_LPTDCR_CT_EN_MASK                   0x10u
#define SNVS_LPTDCR_CT_EN_SHIFT                  4
#define SNVS_LPTDCR_TT_EN_MASK                   0x20u
#define SNVS_LPTDCR_TT_EN_SHIFT                  5
#define SNVS_LPTDCR_VT_EN_MASK                   0x40u
#define SNVS_LPTDCR_VT_EN_SHIFT                  6
#define SNVS_LPTDCR_WMT1_EN_MASK                 0x80u
#define SNVS_LPTDCR_WMT1_EN_SHIFT                7
#define SNVS_LPTDCR_WMT2_EN_MASK                 0x100u
#define SNVS_LPTDCR_WMT2_EN_SHIFT                8
#define SNVS_LPTDCR_ET1_EN_MASK                  0x200u
#define SNVS_LPTDCR_ET1_EN_SHIFT                 9
#define SNVS_LPTDCR_ET2_EN_MASK                  0x400u
#define SNVS_LPTDCR_ET2_EN_SHIFT                 10
#define SNVS_LPTDCR_PFD_OBSERV_MASK              0x4000u
#define SNVS_LPTDCR_PFD_OBSERV_SHIFT             14
#define SNVS_LPTDCR_POR_OBSERV_MASK              0x8000u
#define SNVS_LPTDCR_POR_OBSERV_SHIFT             15
#define SNVS_LPTDCR_LTDC_MASK                    0x70000u
#define SNVS_LPTDCR_LTDC_SHIFT                   16
#define SNVS_LPTDCR_LTDC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_LPTDCR_LTDC_SHIFT))&SNVS_LPTDCR_LTDC_MASK)
#define SNVS_LPTDCR_HTDC_MASK                    0x700000u
#define SNVS_LPTDCR_HTDC_SHIFT                   20
#define SNVS_LPTDCR_HTDC(x)                      (((uint32_t)(((uint32_t)(x))<<SNVS_LPTDCR_HTDC_SHIFT))&SNVS_LPTDCR_HTDC_MASK)
#define SNVS_LPTDCR_VRC_MASK                     0x7000000u
#define SNVS_LPTDCR_VRC_SHIFT                    24
#define SNVS_LPTDCR_VRC(x)                       (((uint32_t)(((uint32_t)(x))<<SNVS_LPTDCR_VRC_SHIFT))&SNVS_LPTDCR_VRC_MASK)
#define SNVS_LPTDCR_OSCB_MASK                    0x10000000u
#define SNVS_LPTDCR_OSCB_SHIFT                   28
/* LPSR Bit Fields */
#define SNVS_LPSR_LPTA_MASK                      0x1u
#define SNVS_LPSR_LPTA_SHIFT                     0
#define SNVS_LPSR_SRTCR_MASK                     0x2u
#define SNVS_LPSR_SRTCR_SHIFT                    1
#define SNVS_LPSR_MCR_MASK                       0x4u
#define SNVS_LPSR_MCR_SHIFT                      2
#define SNVS_LPSR_PGD_MASK                       0x8u
#define SNVS_LPSR_PGD_SHIFT                      3
#define SNVS_LPSR_CTD_MASK                       0x10u
#define SNVS_LPSR_CTD_SHIFT                      4
#define SNVS_LPSR_TTD_MASK                       0x20u
#define SNVS_LPSR_TTD_SHIFT                      5
#define SNVS_LPSR_VTD_MASK                       0x40u
#define SNVS_LPSR_VTD_SHIFT                      6
#define SNVS_LPSR_WMT1D_MASK                     0x80u
#define SNVS_LPSR_WMT1D_SHIFT                    7
#define SNVS_LPSR_WMT2D_MASK                     0x100u
#define SNVS_LPSR_WMT2D_SHIFT                    8
#define SNVS_LPSR_ET1D_MASK                      0x200u
#define SNVS_LPSR_ET1D_SHIFT                     9
#define SNVS_LPSR_ET2D_MASK                      0x400u
#define SNVS_LPSR_ET2D_SHIFT                     10
#define SNVS_LPSR_ESVD_MASK                      0x10000u
#define SNVS_LPSR_ESVD_SHIFT                     16
#define SNVS_LPSR_EO_MASK                        0x20000u
#define SNVS_LPSR_EO_SHIFT                       17
#define SNVS_LPSR_SPO_MASK                       0x40000u
#define SNVS_LPSR_SPO_SHIFT                      18
#define SNVS_LPSR_SED_MASK                       0x100000u
#define SNVS_LPSR_SED_SHIFT                      20
#define SNVS_LPSR_LPNS_MASK                      0x40000000u
#define SNVS_LPSR_LPNS_SHIFT                     30
#define SNVS_LPSR_LPS_MASK                       0x80000000u
#define SNVS_LPSR_LPS_SHIFT                      31
/* LPSRTCMR Bit Fields */
#define SNVS_LPSRTCMR_SRTC_MASK                  0x7FFFu
#define SNVS_LPSRTCMR_SRTC_SHIFT                 0
#define SNVS_LPSRTCMR_SRTC(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPSRTCMR_SRTC_SHIFT))&SNVS_LPSRTCMR_SRTC_MASK)
/* LPSRTCLR Bit Fields */
#define SNVS_LPSRTCLR_SRTC_MASK                  0xFFFFFFFFu
#define SNVS_LPSRTCLR_SRTC_SHIFT                 0
#define SNVS_LPSRTCLR_SRTC(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_LPSRTCLR_SRTC_SHIFT))&SNVS_LPSRTCLR_SRTC_MASK)
/* LPTAR Bit Fields */
#define SNVS_LPTAR_LPTA_MASK                     0xFFFFFFFFu
#define SNVS_LPTAR_LPTA_SHIFT                    0
#define SNVS_LPTAR_LPTA(x)                       (((uint32_t)(((uint32_t)(x))<<SNVS_LPTAR_LPTA_SHIFT))&SNVS_LPTAR_LPTA_MASK)
/* LPSMCMR Bit Fields */
#define SNVS_LPSMCMR_MON_COUNTER_MASK            0xFFFFu
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT           0
#define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MON_COUNTER_SHIFT))&SNVS_LPSMCMR_MON_COUNTER_MASK)
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK            0xFFFF0000u
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           16
#define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MC_ERA_BITS_SHIFT))&SNVS_LPSMCMR_MC_ERA_BITS_MASK)
/* LPSMCLR Bit Fields */
#define SNVS_LPSMCLR_MON_COUNTER_MASK            0xFFFFFFFFu
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT           0
#define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCLR_MON_COUNTER_SHIFT))&SNVS_LPSMCLR_MON_COUNTER_MASK)
/* LPPGDR Bit Fields */
#define SNVS_LPPGDR_PGD_MASK                     0xFFFFFFFFu
#define SNVS_LPPGDR_PGD_SHIFT                    0
#define SNVS_LPPGDR_PGD(x)                       (((uint32_t)(((uint32_t)(x))<<SNVS_LPPGDR_PGD_SHIFT))&SNVS_LPPGDR_PGD_MASK)
/* LPGPR Bit Fields */
#define SNVS_LPGPR_GPR_MASK                      0xFFFFFFFFu
#define SNVS_LPGPR_GPR_SHIFT                     0
#define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x))<<SNVS_LPGPR_GPR_SHIFT))&SNVS_LPGPR_GPR_MASK)
/* LPZMKR Bit Fields */
#define SNVS_LPZMKR_ZMK_MASK                     0xFFFFFFFFu
#define SNVS_LPZMKR_ZMK_SHIFT                    0
#define SNVS_LPZMKR_ZMK(x)                       (((uint32_t)(((uint32_t)(x))<<SNVS_LPZMKR_ZMK_SHIFT))&SNVS_LPZMKR_ZMK_MASK)
/* HPVIDR1 Bit Fields */
#define SNVS_HPVIDR1_MINOR_REV_MASK              0xFFu
#define SNVS_HPVIDR1_MINOR_REV_SHIFT             0
#define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MINOR_REV_SHIFT))&SNVS_HPVIDR1_MINOR_REV_MASK)
#define SNVS_HPVIDR1_MAJOR_REV_MASK              0xFF00u
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT             8
#define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MAJOR_REV_SHIFT))&SNVS_HPVIDR1_MAJOR_REV_MASK)
#define SNVS_HPVIDR1_IP_ID_MASK                  0xFFFF0000u
#define SNVS_HPVIDR1_IP_ID_SHIFT                 16
#define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_IP_ID_SHIFT))&SNVS_HPVIDR1_IP_ID_MASK)
/* HPVIDR2 Bit Fields */
#define SNVS_HPVIDR2_CONFIG_OPT_MASK             0xFFu
#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT            0
#define SNVS_HPVIDR2_CONFIG_OPT(x)               (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_CONFIG_OPT_SHIFT))&SNVS_HPVIDR2_CONFIG_OPT_MASK)
#define SNVS_HPVIDR2_ECO_REV_MASK                0xFF00u
#define SNVS_HPVIDR2_ECO_REV_SHIFT               8
#define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_ECO_REV_SHIFT))&SNVS_HPVIDR2_ECO_REV_MASK)
#define SNVS_HPVIDR2_INTG_OPT_MASK               0xFF0000u
#define SNVS_HPVIDR2_INTG_OPT_SHIFT              16
#define SNVS_HPVIDR2_INTG_OPT(x)                 (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_INTG_OPT_SHIFT))&SNVS_HPVIDR2_INTG_OPT_MASK)

/**
 * @}
 */ /* end of group SNVS_Register_Masks */


/* SNVS - Peripheral instance base addresses */
/** Peripheral SNVS base address */
#define SNVS_BASE                                (0u)
/** Peripheral SNVS base pointer */
#define SNVS                                     ((SNVS_Type *)SNVS_BASE)
/** Array initializer of SNVS peripheral base pointers */
#define SNVS_BASES                               { SNVS }

/**
 * @}
 */ /* end of group SNVS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPDIF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
 * @{
 */

/** SPDIF - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
  __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
  __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
  __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
  union {                                          /* offset: 0x10 */
    __IO uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
    __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
  };
  __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
  __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
  __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
  __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
  __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
  __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
  __IO uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
  __IO uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
  __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
  __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
       uint8_t RESERVED_0[8];
  __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
       uint8_t RESERVED_1[8];
  __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
} SPDIF_Type;

/* ----------------------------------------------------------------------------
   -- SPDIF Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
 * @{
 */

/* SCR Bit Fields */
#define SPDIF_SCR_USrc_Sel_MASK                  0x3u
#define SPDIF_SCR_USrc_Sel_SHIFT                 0
#define SPDIF_SCR_USrc_Sel(x)                    (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_USrc_Sel_SHIFT))&SPDIF_SCR_USrc_Sel_MASK)
#define SPDIF_SCR_TxSel_MASK                     0x1Cu
#define SPDIF_SCR_TxSel_SHIFT                    2
#define SPDIF_SCR_TxSel(x)                       (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxSel_SHIFT))&SPDIF_SCR_TxSel_MASK)
#define SPDIF_SCR_ValCtrl_MASK                   0x20u
#define SPDIF_SCR_ValCtrl_SHIFT                  5
#define SPDIF_SCR_DMA_TX_En_MASK                 0x100u
#define SPDIF_SCR_DMA_TX_En_SHIFT                8
#define SPDIF_SCR_DMA_Rx_En_MASK                 0x200u
#define SPDIF_SCR_DMA_Rx_En_SHIFT                9
#define SPDIF_SCR_TxFIFO_Ctrl_MASK               0xC00u
#define SPDIF_SCR_TxFIFO_Ctrl_SHIFT              10
#define SPDIF_SCR_TxFIFO_Ctrl(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxFIFO_Ctrl_SHIFT))&SPDIF_SCR_TxFIFO_Ctrl_MASK)
#define SPDIF_SCR_Soft_Reset_MASK                0x1000u
#define SPDIF_SCR_Soft_Reset_SHIFT               12
#define SPDIF_SCR_Low_Power_MASK                 0x2000u
#define SPDIF_SCR_Low_Power_SHIFT                13
#define SPDIF_SCR_TxFIFOEmpty_Sel_MASK           0x18000u
#define SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT          15
#define SPDIF_SCR_TxFIFOEmpty_Sel(x)             (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT))&SPDIF_SCR_TxFIFOEmpty_Sel_MASK)
#define SPDIF_SCR_TxAutoSync_MASK                0x20000u
#define SPDIF_SCR_TxAutoSync_SHIFT               17
#define SPDIF_SCR_RxAutoSync_MASK                0x40000u
#define SPDIF_SCR_RxAutoSync_SHIFT               18
#define SPDIF_SCR_RxFIFOFull_Sel_MASK            0x180000u
#define SPDIF_SCR_RxFIFOFull_Sel_SHIFT           19
#define SPDIF_SCR_RxFIFOFull_Sel(x)              (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_RxFIFOFull_Sel_SHIFT))&SPDIF_SCR_RxFIFOFull_Sel_MASK)
#define SPDIF_SCR_RxFIFO_Rst_MASK                0x200000u
#define SPDIF_SCR_RxFIFO_Rst_SHIFT               21
#define SPDIF_SCR_RxFIFO_En_MASK                 0x400000u
#define SPDIF_SCR_RxFIFO_En_SHIFT                22
#define SPDIF_SCR_RxFIFO_Ctrl_MASK               0x800000u
#define SPDIF_SCR_RxFIFO_Ctrl_SHIFT              23
/* SRCD Bit Fields */
#define SPDIF_SRCD_USyncMode_MASK                0x2u
#define SPDIF_SRCD_USyncMode_SHIFT               1
/* SRPC Bit Fields */
#define SPDIF_SRPC_GainSel_MASK                  0x38u
#define SPDIF_SRPC_GainSel_SHIFT                 3
#define SPDIF_SRPC_GainSel(x)                    (((uint32_t)(((uint32_t)(x))<<SPDIF_SRPC_GainSel_SHIFT))&SPDIF_SRPC_GainSel_MASK)
#define SPDIF_SRPC_LOCK_MASK                     0x40u
#define SPDIF_SRPC_LOCK_SHIFT                    6
#define SPDIF_SRPC_ClkSrc_Sel_MASK               0x780u
#define SPDIF_SRPC_ClkSrc_Sel_SHIFT              7
#define SPDIF_SRPC_ClkSrc_Sel(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_SRPC_ClkSrc_Sel_SHIFT))&SPDIF_SRPC_ClkSrc_Sel_MASK)
/* SIE Bit Fields */
#define SPDIF_SIE_RxFIFOFul_MASK                 0x1u
#define SPDIF_SIE_RxFIFOFul_SHIFT                0
#define SPDIF_SIE_TxEm_MASK                      0x2u
#define SPDIF_SIE_TxEm_SHIFT                     1
#define SPDIF_SIE_LockLoss_MASK                  0x4u
#define SPDIF_SIE_LockLoss_SHIFT                 2
#define SPDIF_SIE_RxFIFOResyn_MASK               0x8u
#define SPDIF_SIE_RxFIFOResyn_SHIFT              3
#define SPDIF_SIE_RxFIFOUnOv_MASK                0x10u
#define SPDIF_SIE_RxFIFOUnOv_SHIFT               4
#define SPDIF_SIE_UQErr_MASK                     0x20u
#define SPDIF_SIE_UQErr_SHIFT                    5
#define SPDIF_SIE_UQSync_MASK                    0x40u
#define SPDIF_SIE_UQSync_SHIFT                   6
#define SPDIF_SIE_QRxOv_MASK                     0x80u
#define SPDIF_SIE_QRxOv_SHIFT                    7
#define SPDIF_SIE_QRxFul_MASK                    0x100u
#define SPDIF_SIE_QRxFul_SHIFT                   8
#define SPDIF_SIE_URxOv_MASK                     0x200u
#define SPDIF_SIE_URxOv_SHIFT                    9
#define SPDIF_SIE_URxFul_MASK                    0x400u
#define SPDIF_SIE_URxFul_SHIFT                   10
#define SPDIF_SIE_BitErr_MASK                    0x4000u
#define SPDIF_SIE_BitErr_SHIFT                   14
#define SPDIF_SIE_SymErr_MASK                    0x8000u
#define SPDIF_SIE_SymErr_SHIFT                   15
#define SPDIF_SIE_ValNoGood_MASK                 0x10000u
#define SPDIF_SIE_ValNoGood_SHIFT                16
#define SPDIF_SIE_CNew_MASK                      0x20000u
#define SPDIF_SIE_CNew_SHIFT                     17
#define SPDIF_SIE_TxResyn_MASK                   0x40000u
#define SPDIF_SIE_TxResyn_SHIFT                  18
#define SPDIF_SIE_TxUnOv_MASK                    0x80000u
#define SPDIF_SIE_TxUnOv_SHIFT                   19
#define SPDIF_SIE_Lock_MASK                      0x100000u
#define SPDIF_SIE_Lock_SHIFT                     20
/* SIC Bit Fields */
#define SPDIF_SIC_LockLoss_MASK                  0x4u
#define SPDIF_SIC_LockLoss_SHIFT                 2
#define SPDIF_SIC_RxFIFOResyn_MASK               0x8u
#define SPDIF_SIC_RxFIFOResyn_SHIFT              3
#define SPDIF_SIC_RxFIFOUnOv_MASK                0x10u
#define SPDIF_SIC_RxFIFOUnOv_SHIFT               4
#define SPDIF_SIC_UQErr_MASK                     0x20u
#define SPDIF_SIC_UQErr_SHIFT                    5
#define SPDIF_SIC_UQSync_MASK                    0x40u
#define SPDIF_SIC_UQSync_SHIFT                   6
#define SPDIF_SIC_QRxOv_MASK                     0x80u
#define SPDIF_SIC_QRxOv_SHIFT                    7
#define SPDIF_SIC_URxOv_MASK                     0x200u
#define SPDIF_SIC_URxOv_SHIFT                    9
#define SPDIF_SIC_BitErr_MASK                    0x4000u
#define SPDIF_SIC_BitErr_SHIFT                   14
#define SPDIF_SIC_SymErr_MASK                    0x8000u
#define SPDIF_SIC_SymErr_SHIFT                   15
#define SPDIF_SIC_ValNoGood_MASK                 0x10000u
#define SPDIF_SIC_ValNoGood_SHIFT                16
#define SPDIF_SIC_CNew_MASK                      0x20000u
#define SPDIF_SIC_CNew_SHIFT                     17
#define SPDIF_SIC_TxResyn_MASK                   0x40000u
#define SPDIF_SIC_TxResyn_SHIFT                  18
#define SPDIF_SIC_TxUnOv_MASK                    0x80000u
#define SPDIF_SIC_TxUnOv_SHIFT                   19
#define SPDIF_SIC_Lock_MASK                      0x100000u
#define SPDIF_SIC_Lock_SHIFT                     20
/* SIS Bit Fields */
#define SPDIF_SIS_RxFIFOFul_MASK                 0x1u
#define SPDIF_SIS_RxFIFOFul_SHIFT                0
#define SPDIF_SIS_TxFIFOEmpty_MASK               0x2u
#define SPDIF_SIS_TxFIFOEmpty_SHIFT              1
#define SPDIF_SIS_LockLoss_MASK                  0x4u
#define SPDIF_SIS_LockLoss_SHIFT                 2
#define SPDIF_SIS_RxFIFOResyn_MASK               0x8u
#define SPDIF_SIS_RxFIFOResyn_SHIFT              3
#define SPDIF_SIS_RxFIFOUnOv_MASK                0x10u
#define SPDIF_SIS_RxFIFOUnOv_SHIFT               4
#define SPDIF_SIS_UQErr_MASK                     0x20u
#define SPDIF_SIS_UQErr_SHIFT                    5
#define SPDIF_SIS_UQSync_MASK                    0x40u
#define SPDIF_SIS_UQSync_SHIFT                   6
#define SPDIF_SIS_QRxOv_MASK                     0x80u
#define SPDIF_SIS_QRxOv_SHIFT                    7
#define SPDIF_SIS_URxOv_MASK                     0x200u
#define SPDIF_SIS_URxOv_SHIFT                    9
#define SPDIF_SIS_BitErr_MASK                    0x4000u
#define SPDIF_SIS_BitErr_SHIFT                   14
#define SPDIF_SIS_SymErr_MASK                    0x8000u
#define SPDIF_SIS_SymErr_SHIFT                   15
#define SPDIF_SIS_ValNoGood_MASK                 0x10000u
#define SPDIF_SIS_ValNoGood_SHIFT                16
#define SPDIF_SIS_CNew_MASK                      0x20000u
#define SPDIF_SIS_CNew_SHIFT                     17
#define SPDIF_SIS_TxResyn_MASK                   0x40000u
#define SPDIF_SIS_TxResyn_SHIFT                  18
#define SPDIF_SIS_TxUnOv_MASK                    0x80000u
#define SPDIF_SIS_TxUnOv_SHIFT                   19
#define SPDIF_SIS_Lock_MASK                      0x100000u
#define SPDIF_SIS_Lock_SHIFT                     20
/* SRL Bit Fields */
#define SPDIF_SRL_RxDataLeft_MASK                0xFFFFFFu
#define SPDIF_SRL_RxDataLeft_SHIFT               0
#define SPDIF_SRL_RxDataLeft(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_SRL_RxDataLeft_SHIFT))&SPDIF_SRL_RxDataLeft_MASK)
/* SRR Bit Fields */
#define SPDIF_SRR_RxDataRight_MASK               0xFFFFFFu
#define SPDIF_SRR_RxDataRight_SHIFT              0
#define SPDIF_SRR_RxDataRight(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_SRR_RxDataRight_SHIFT))&SPDIF_SRR_RxDataRight_MASK)
/* SRCSH Bit Fields */
#define SPDIF_SRCSH_RxCChannel_h_MASK            0xFFFFFFu
#define SPDIF_SRCSH_RxCChannel_h_SHIFT           0
#define SPDIF_SRCSH_RxCChannel_h(x)              (((uint32_t)(((uint32_t)(x))<<SPDIF_SRCSH_RxCChannel_h_SHIFT))&SPDIF_SRCSH_RxCChannel_h_MASK)
/* SRCSL Bit Fields */
#define SPDIF_SRCSL_RxCChannel_l_MASK            0xFFFFFFu
#define SPDIF_SRCSL_RxCChannel_l_SHIFT           0
#define SPDIF_SRCSL_RxCChannel_l(x)              (((uint32_t)(((uint32_t)(x))<<SPDIF_SRCSL_RxCChannel_l_SHIFT))&SPDIF_SRCSL_RxCChannel_l_MASK)
/* SRU Bit Fields */
#define SPDIF_SRU_RxUChannel_MASK                0xFFFFFFu
#define SPDIF_SRU_RxUChannel_SHIFT               0
#define SPDIF_SRU_RxUChannel(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_SRU_RxUChannel_SHIFT))&SPDIF_SRU_RxUChannel_MASK)
/* SRQ Bit Fields */
#define SPDIF_SRQ_RxQChannel_MASK                0xFFFFFFu
#define SPDIF_SRQ_RxQChannel_SHIFT               0
#define SPDIF_SRQ_RxQChannel(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_SRQ_RxQChannel_SHIFT))&SPDIF_SRQ_RxQChannel_MASK)
/* STL Bit Fields */
#define SPDIF_STL_TxDataLeft_MASK                0xFFFFFFu
#define SPDIF_STL_TxDataLeft_SHIFT               0
#define SPDIF_STL_TxDataLeft(x)                  (((uint32_t)(((uint32_t)(x))<<SPDIF_STL_TxDataLeft_SHIFT))&SPDIF_STL_TxDataLeft_MASK)
/* STR Bit Fields */
#define SPDIF_STR_TxDataRight_MASK               0xFFFFFFu
#define SPDIF_STR_TxDataRight_SHIFT              0
#define SPDIF_STR_TxDataRight(x)                 (((uint32_t)(((uint32_t)(x))<<SPDIF_STR_TxDataRight_SHIFT))&SPDIF_STR_TxDataRight_MASK)
/* STCSCH Bit Fields */
#define SPDIF_STCSCH_TxCChannelCons_h_MASK       0xFFFFFFu
#define SPDIF_STCSCH_TxCChannelCons_h_SHIFT      0
#define SPDIF_STCSCH_TxCChannelCons_h(x)         (((uint32_t)(((uint32_t)(x))<<SPDIF_STCSCH_TxCChannelCons_h_SHIFT))&SPDIF_STCSCH_TxCChannelCons_h_MASK)
/* STCSCL Bit Fields */
#define SPDIF_STCSCL_TxCChannelCons_l_MASK       0xFFFFFFu
#define SPDIF_STCSCL_TxCChannelCons_l_SHIFT      0
#define SPDIF_STCSCL_TxCChannelCons_l(x)         (((uint32_t)(((uint32_t)(x))<<SPDIF_STCSCL_TxCChannelCons_l_SHIFT))&SPDIF_STCSCL_TxCChannelCons_l_MASK)
/* SRFM Bit Fields */
#define SPDIF_SRFM_FreqMeas_MASK                 0xFFFFFFu
#define SPDIF_SRFM_FreqMeas_SHIFT                0
#define SPDIF_SRFM_FreqMeas(x)                   (((uint32_t)(((uint32_t)(x))<<SPDIF_SRFM_FreqMeas_SHIFT))&SPDIF_SRFM_FreqMeas_MASK)
/* STC Bit Fields */
#define SPDIF_STC_TxClk_DF_MASK                  0x7Fu
#define SPDIF_STC_TxClk_DF_SHIFT                 0
#define SPDIF_STC_TxClk_DF(x)                    (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_TxClk_DF_SHIFT))&SPDIF_STC_TxClk_DF_MASK)
#define SPDIF_STC_tx_all_clk_en_MASK             0x80u
#define SPDIF_STC_tx_all_clk_en_SHIFT            7
#define SPDIF_STC_TxClk_Source_MASK              0x700u
#define SPDIF_STC_TxClk_Source_SHIFT             8
#define SPDIF_STC_TxClk_Source(x)                (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_TxClk_Source_SHIFT))&SPDIF_STC_TxClk_Source_MASK)
#define SPDIF_STC_SYSCLK_DF_MASK                 0xFF800u
#define SPDIF_STC_SYSCLK_DF_SHIFT                11
#define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_SYSCLK_DF_SHIFT))&SPDIF_STC_SYSCLK_DF_MASK)

/**
 * @}
 */ /* end of group SPDIF_Register_Masks */


/* SPDIF - Peripheral instance base addresses */
/** Peripheral SPDIF base address */
#define SPDIF_BASE                               (0x40061000u)
/** Peripheral SPDIF base pointer */
#define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
/** Array initializer of SPDIF peripheral base pointers */
#define SPDIF_BASES                              { SPDIF }

/**
 * @}
 */ /* end of group SPDIF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
 * @{
 */

/** SPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
  union {                                          /* offset: 0xC */
    __IO uint32_t CTAR[4];                           /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
  };
       uint8_t RESERVED_1[16];
  __IO uint32_t SR;                                /**< DSPI Status Register, offset: 0x2C */
  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
  union {                                          /* offset: 0x34 */
    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
  };
  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
  __I  uint32_t TXFR0;                             /**< DSPI Transmit FIFO Registers, offset: 0x3C */
  __I  uint32_t TXFR1;                             /**< DSPI Transmit FIFO Registers, offset: 0x40 */
  __I  uint32_t TXFR2;                             /**< DSPI Transmit FIFO Registers, offset: 0x44 */
  __I  uint32_t TXFR3;                             /**< DSPI Transmit FIFO Registers, offset: 0x48 */
       uint8_t RESERVED_2[48];
  __I  uint32_t RXFR0;                             /**< DSPI Receive FIFO Registers, offset: 0x7C */
  __I  uint32_t RXFR1;                             /**< DSPI Receive FIFO Registers, offset: 0x80 */
  __I  uint32_t RXFR2;                             /**< DSPI Receive FIFO Registers, offset: 0x84 */
  __I  uint32_t RXFR3;                             /**< DSPI Receive FIFO Registers, offset: 0x88 */
} SPI_Type;

/* ----------------------------------------------------------------------------
   -- SPI Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SPI_Register_Masks SPI Register Masks
 * @{
 */

/* MCR Bit Fields */
#define SPI_MCR_HALT_MASK                        0x1u
#define SPI_MCR_HALT_SHIFT                       0
#define SPI_MCR_PES_MASK                         0x2u
#define SPI_MCR_PES_SHIFT                        1
#define SPI_MCR_FCPCS_MASK                       0x4u
#define SPI_MCR_FCPCS_SHIFT                      2
#define SPI_MCR_SMPL_PT_MASK                     0x300u
#define SPI_MCR_SMPL_PT_SHIFT                    8
#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
#define SPI_MCR_CLR_RXF_MASK                     0x400u
#define SPI_MCR_CLR_RXF_SHIFT                    10
#define SPI_MCR_CLR_TXF_MASK                     0x800u
#define SPI_MCR_CLR_TXF_SHIFT                    11
#define SPI_MCR_DIS_RXF_MASK                     0x1000u
#define SPI_MCR_DIS_RXF_SHIFT                    12
#define SPI_MCR_DIS_TXF_MASK                     0x2000u
#define SPI_MCR_DIS_TXF_SHIFT                    13
#define SPI_MCR_MDIS_MASK                        0x4000u
#define SPI_MCR_MDIS_SHIFT                       14
#define SPI_MCR_PCSIS_MASK                       0x3F0000u
#define SPI_MCR_PCSIS_SHIFT                      16
#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
#define SPI_MCR_ROOE_MASK                        0x1000000u
#define SPI_MCR_ROOE_SHIFT                       24
#define SPI_MCR_PCSSE_MASK                       0x2000000u
#define SPI_MCR_PCSSE_SHIFT                      25
#define SPI_MCR_MTFE_MASK                        0x4000000u
#define SPI_MCR_MTFE_SHIFT                       26
#define SPI_MCR_FRZ_MASK                         0x8000000u
#define SPI_MCR_FRZ_SHIFT                        27
#define SPI_MCR_DCONF_MASK                       0x30000000u
#define SPI_MCR_DCONF_SHIFT                      28
#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
#define SPI_MCR_CONT_SCKE_SHIFT                  30
#define SPI_MCR_MSTR_MASK                        0x80000000u
#define SPI_MCR_MSTR_SHIFT                       31
/* TCR Bit Fields */
#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
#define SPI_TCR_SPI_TCNT_SHIFT                   16
#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
/* CTAR Bit Fields */
#define SPI_CTAR_BR_MASK                         0xFu
#define SPI_CTAR_BR_SHIFT                        0
#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
#define SPI_CTAR_DT_MASK                         0xF0u
#define SPI_CTAR_DT_SHIFT                        4
#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
#define SPI_CTAR_ASC_MASK                        0xF00u
#define SPI_CTAR_ASC_SHIFT                       8
#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
#define SPI_CTAR_CSSCK_MASK                      0xF000u
#define SPI_CTAR_CSSCK_SHIFT                     12
#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
#define SPI_CTAR_PBR_MASK                        0x30000u
#define SPI_CTAR_PBR_SHIFT                       16
#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
#define SPI_CTAR_PDT_MASK                        0xC0000u
#define SPI_CTAR_PDT_SHIFT                       18
#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
#define SPI_CTAR_PASC_MASK                       0x300000u
#define SPI_CTAR_PASC_SHIFT                      20
#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
#define SPI_CTAR_PCSSCK_SHIFT                    22
#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
#define SPI_CTAR_LSBFE_MASK                      0x1000000u
#define SPI_CTAR_LSBFE_SHIFT                     24
#define SPI_CTAR_CPHA_MASK                       0x2000000u
#define SPI_CTAR_CPHA_SHIFT                      25
#define SPI_CTAR_CPOL_MASK                       0x4000000u
#define SPI_CTAR_CPOL_SHIFT                      26
#define SPI_CTAR_FMSZ_MASK                       0x78000000u
#define SPI_CTAR_FMSZ_SHIFT                      27
#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
#define SPI_CTAR_DBR_MASK                        0x80000000u
#define SPI_CTAR_DBR_SHIFT                       31
/* CTAR_SLAVE Bit Fields */
#define SPI_CTAR_SLAVE_PP_MASK                   0x800000u
#define SPI_CTAR_SLAVE_PP_SHIFT                  23
#define SPI_CTAR_SLAVE_PE_MASK                   0x1000000u
#define SPI_CTAR_SLAVE_PE_SHIFT                  24
#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
/* SR Bit Fields */
#define SPI_SR_POPNXTPTR_MASK                    0xFu
#define SPI_SR_POPNXTPTR_SHIFT                   0
#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
#define SPI_SR_RXCTR_MASK                        0xF0u
#define SPI_SR_RXCTR_SHIFT                       4
#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
#define SPI_SR_TXNXTPTR_MASK                     0xF00u
#define SPI_SR_TXNXTPTR_SHIFT                    8
#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
#define SPI_SR_TXCTR_MASK                        0xF000u
#define SPI_SR_TXCTR_SHIFT                       12
#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
#define SPI_SR_RFDF_MASK                         0x20000u
#define SPI_SR_RFDF_SHIFT                        17
#define SPI_SR_RFOF_MASK                         0x80000u
#define SPI_SR_RFOF_SHIFT                        19
#define SPI_SR_SPEF_MASK                         0x200000u
#define SPI_SR_SPEF_SHIFT                        21
#define SPI_SR_TFFF_MASK                         0x2000000u
#define SPI_SR_TFFF_SHIFT                        25
#define SPI_SR_TFUF_MASK                         0x8000000u
#define SPI_SR_TFUF_SHIFT                        27
#define SPI_SR_EOQF_MASK                         0x10000000u
#define SPI_SR_EOQF_SHIFT                        28
#define SPI_SR_TXRXS_MASK                        0x40000000u
#define SPI_SR_TXRXS_SHIFT                       30
#define SPI_SR_TCF_MASK                          0x80000000u
#define SPI_SR_TCF_SHIFT                         31
/* RSER Bit Fields */
#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
#define SPI_RSER_RFDF_DIRS_SHIFT                 16
#define SPI_RSER_RFDF_RE_MASK                    0x20000u
#define SPI_RSER_RFDF_RE_SHIFT                   17
#define SPI_RSER_RFOF_RE_MASK                    0x80000u
#define SPI_RSER_RFOF_RE_SHIFT                   19
#define SPI_RSER_SPEF_RE_MASK                    0x200000u
#define SPI_RSER_SPEF_RE_SHIFT                   21
#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
#define SPI_RSER_TFFF_DIRS_SHIFT                 24
#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
#define SPI_RSER_TFFF_RE_SHIFT                   25
#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
#define SPI_RSER_TFUF_RE_SHIFT                   27
#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
#define SPI_RSER_EOQF_RE_SHIFT                   28
#define SPI_RSER_TCF_RE_MASK                     0x80000000u
#define SPI_RSER_TCF_RE_SHIFT                    31
/* PUSHR Bit Fields */
#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
#define SPI_PUSHR_TXDATA_SHIFT                   0
#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
#define SPI_PUSHR_PCS_MASK                       0x3F0000u
#define SPI_PUSHR_PCS_SHIFT                      16
#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
#define SPI_PUSHR_PP_MCSC_MASK                   0x1000000u
#define SPI_PUSHR_PP_MCSC_SHIFT                  24
#define SPI_PUSHR_PE_MASC_MASK                   0x2000000u
#define SPI_PUSHR_PE_MASC_SHIFT                  25
#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
#define SPI_PUSHR_CTCNT_SHIFT                    26
#define SPI_PUSHR_EOQ_MASK                       0x8000000u
#define SPI_PUSHR_EOQ_SHIFT                      27
#define SPI_PUSHR_CTAS_MASK                      0x70000000u
#define SPI_PUSHR_CTAS_SHIFT                     28
#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
#define SPI_PUSHR_CONT_MASK                      0x80000000u
#define SPI_PUSHR_CONT_SHIFT                     31
/* PUSHR_SLAVE Bit Fields */
#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFu
#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
/* POPR Bit Fields */
#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
#define SPI_POPR_RXDATA_SHIFT                    0
#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
/* TXFR0 Bit Fields */
#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
#define SPI_TXFR0_TXDATA_SHIFT                   0
#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
/* TXFR1 Bit Fields */
#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
#define SPI_TXFR1_TXDATA_SHIFT                   0
#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
/* TXFR2 Bit Fields */
#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
#define SPI_TXFR2_TXDATA_SHIFT                   0
#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
/* TXFR3 Bit Fields */
#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
#define SPI_TXFR3_TXDATA_SHIFT                   0
#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
/* RXFR0 Bit Fields */
#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
#define SPI_RXFR0_RXDATA_SHIFT                   0
#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
/* RXFR1 Bit Fields */
#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
#define SPI_RXFR1_RXDATA_SHIFT                   0
#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
/* RXFR2 Bit Fields */
#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
#define SPI_RXFR2_RXDATA_SHIFT                   0
#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
/* RXFR3 Bit Fields */
#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
#define SPI_RXFR3_RXDATA_SHIFT                   0
#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)

/**
 * @}
 */ /* end of group SPI_Register_Masks */


/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base address */
#define SPI0_BASE                                (0x4002C000u)
/** Peripheral SPI0 base pointer */
#define SPI0                                     ((SPI_Type *)SPI0_BASE)
/** Peripheral SPI1 base address */
#define SPI1_BASE                                (0x4002D000u)
/** Peripheral SPI1 base pointer */
#define SPI1                                     ((SPI_Type *)SPI1_BASE)
/** Peripheral SPI2 base address */
#define SPI2_BASE                                (0x400AC000u)
/** Peripheral SPI2 base pointer */
#define SPI2                                     ((SPI_Type *)SPI2_BASE)
/** Peripheral SPI3 base address */
#define SPI3_BASE                                (0x400AD000u)
/** Peripheral SPI3 base pointer */
#define SPI3                                     ((SPI_Type *)SPI3_BASE)
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASES                                { SPI0, SPI1, SPI2, SPI3 }

/**
 * @}
 */ /* end of group SPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
 * @{
 */

/** SRC - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCR;                               /**< SRC Control Register, offset: 0x0 */
  __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x4 */
  __IO uint32_t SRSR;                              /**< SRC Status Register, offset: 0x8 */
  __IO uint32_t SECR;                              /**< , offset: 0xC */
  __I  uint32_t GPSR;                              /**< General purpose Status register., offset: 0x10 */
  __IO uint32_t SICR;                              /**< SRC Reset Interrupt Configuration Register, offset: 0x14 */
  __IO uint32_t SIMR;                              /**< SRC Interrupt Masking Register, offset: 0x18 */
  __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0x1C */
  __IO uint32_t GPR[5];                            /**< General Purpose Register, array offset: 0x20, array step: 0x4 */
  __IO uint32_t HAB[6];                            /**< HAB, array offset: 0x34, array step: 0x4 */
  __IO uint32_t MISC0;                             /**< MISC0, offset: 0x4C */
  __IO uint32_t MISC1;                             /**< MISC1, offset: 0x50 */
  __IO uint32_t MISC2;                             /**< MISC2, offset: 0x54 */
  __IO uint32_t MISC3;                             /**< MISC3, offset: 0x58 */
} SRC_Type;

/* ----------------------------------------------------------------------------
   -- SRC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup SRC_Register_Masks SRC Register Masks
 * @{
 */

/* SCR Bit Fields */
#define SRC_SCR_CA5_WDGRST_MASK_MASK             0xFu
#define SRC_SCR_CA5_WDGRST_MASK_SHIFT            0
#define SRC_SCR_CA5_WDGRST_MASK(x)               (((uint32_t)(((uint32_t)(x))<<SRC_SCR_CA5_WDGRST_MASK_SHIFT))&SRC_SCR_CA5_WDGRST_MASK_MASK)
#define SRC_SCR_CM4_WDGRST_MASK_MASK             0x780u
#define SRC_SCR_CM4_WDGRST_MASK_SHIFT            7
#define SRC_SCR_CM4_WDGRST_MASK(x)               (((uint32_t)(((uint32_t)(x))<<SRC_SCR_CM4_WDGRST_MASK_SHIFT))&SRC_SCR_CM4_WDGRST_MASK_MASK)
#define SRC_SCR_SW_RST_MASK                      0x1000u
#define SRC_SCR_SW_RST_SHIFT                     12
/* SBMR1 Bit Fields */
#define SRC_SBMR1_BOOT_CFG1_MASK                 0xFFu
#define SRC_SBMR1_BOOT_CFG1_SHIFT                0
#define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG1_SHIFT))&SRC_SBMR1_BOOT_CFG1_MASK)
#define SRC_SBMR1_BOOT_CFG2_MASK                 0xFF00u
#define SRC_SBMR1_BOOT_CFG2_SHIFT                8
#define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG2_SHIFT))&SRC_SBMR1_BOOT_CFG2_MASK)
#define SRC_SBMR1_BOOT_CFG3_MASK                 0xFF0000u
#define SRC_SBMR1_BOOT_CFG3_SHIFT                16
#define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG3_SHIFT))&SRC_SBMR1_BOOT_CFG3_MASK)
#define SRC_SBMR1_BOOT_CFG4_MASK                 0xFF000000u
#define SRC_SBMR1_BOOT_CFG4_SHIFT                24
#define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG4_SHIFT))&SRC_SBMR1_BOOT_CFG4_MASK)
/* SRSR Bit Fields */
#define SRC_SRSR_POR_RST_MASK                    0x1u
#define SRC_SRSR_POR_RST_SHIFT                   0
#define SRC_SRSR_CA5_WDG_RST_MASK                0x2u
#define SRC_SRSR_CA5_WDG_RST_SHIFT               1
#define SRC_SRSR_WDOG_RST_MASK                   0x18u
#define SRC_SRSR_WDOG_RST_SHIFT                  3
#define SRC_SRSR_WDOG_RST(x)                     (((uint32_t)(((uint32_t)(x))<<SRC_SRSR_WDOG_RST_SHIFT))&SRC_SRSR_WDOG_RST_MASK)
#define SRC_SRSR_JTAG_RST_MASK                   0x20u
#define SRC_SRSR_JTAG_RST_SHIFT                  5
#define SRC_SRSR_RESETB_MASK                     0x80u
#define SRC_SRSR_RESETB_SHIFT                    7
#define SRC_SRSR_POR1P2_MASK                     0x100u
#define SRC_SRSR_POR1P2_SHIFT                    8
#define SRC_SRSR_HP_LVD_MASK                     0x200u
#define SRC_SRSR_HP_LVD_SHIFT                    9
#define SRC_SRSR_ULP_LVD_MASK                    0x400u
#define SRC_SRSR_ULP_LVD_SHIFT                   10
#define SRC_SRSR_LVD_P3P_MASK                    0x800u
#define SRC_SRSR_LVD_P3P_SHIFT                   11
#define SRC_SRSR_LP_LVD_MASK                     0x1000u
#define SRC_SRSR_LP_LVD_SHIFT                    12
#define SRC_SRSR_MDM_SYS_RST_MASK                0x10000u
#define SRC_SRSR_MDM_SYS_RST_SHIFT               16
#define SRC_SRSR_SNVS_HARD_RST_MASK              0x20000u
#define SRC_SRSR_SNVS_HARD_RST_SHIFT             17
#define SRC_SRSR_SRC_SW_RST_MASK                 0x40000u
#define SRC_SRSR_SRC_SW_RST_SHIFT                18
#define SRC_SRSR_CSU_ALARM_RST_MASK              0x80000u
#define SRC_SRSR_CSU_ALARM_RST_SHIFT             19
#define SRC_SRSR_REG_1P1_OK_MASK                 0x1000000u
#define SRC_SRSR_REG_1P1_OK_SHIFT                24
#define SRC_SRSR_REG_2P5_OK_MASK                 0x2000000u
#define SRC_SRSR_REG_2P5_OK_SHIFT                25
#define SRC_SRSR_REG_3P0_OK_MASK                 0x4000000u
#define SRC_SRSR_REG_3P0_OK_SHIFT                26
#define SRC_SRSR_CMU_OLR_MASK                    0x8000000u
#define SRC_SRSR_CMU_OLR_SHIFT                   27
#define SRC_SRSR_CMU_FLL_FHH_MASK                0x10000000u
#define SRC_SRSR_CMU_FLL_FHH_SHIFT               28
#define SRC_SRSR_SOSC_OK_MASK                    0x40000000u
#define SRC_SRSR_SOSC_OK_SHIFT                   30
#define SRC_SRSR_CM4_LCK_MASK                    0x80000000u
#define SRC_SRSR_CM4_LCK_SHIFT                   31
/* SECR Bit Fields */
#define SRC_SECR_SPNIDEN_MASK                    0x1u
#define SRC_SECR_SPNIDEN_SHIFT                   0
#define SRC_SECR_SPIDEN_MASK                     0x2u
#define SRC_SECR_SPIDEN_SHIFT                    1
#define SRC_SECR_WRLOCK_MASK                     0x10u
#define SRC_SECR_WRLOCK_SHIFT                    4
/* GPSR Bit Fields */
#define SRC_GPSR_GP_MASK                         0xFFFFFFFFu
#define SRC_GPSR_GP_SHIFT                        0
#define SRC_GPSR_GP(x)                           (((uint32_t)(((uint32_t)(x))<<SRC_GPSR_GP_SHIFT))&SRC_GPSR_GP_MASK)
/* SICR Bit Fields */
#define SRC_SICR_CA5_WDG_RST_MASK                0x2u
#define SRC_SICR_CA5_WDG_RST_SHIFT               1
#define SRC_SICR_WDOG_RST_MASK                   0x18u
#define SRC_SICR_WDOG_RST_SHIFT                  3
#define SRC_SICR_WDOG_RST(x)                     (((uint32_t)(((uint32_t)(x))<<SRC_SICR_WDOG_RST_SHIFT))&SRC_SICR_WDOG_RST_MASK)
#define SRC_SICR_JTAG_RST_MASK                   0x20u
#define SRC_SICR_JTAG_RST_SHIFT                  5
#define SRC_SICR_MDM_SYS_RST_MASK                0x10000u
#define SRC_SICR_MDM_SYS_RST_SHIFT               16
#define SRC_SICR_SNVS_HARD_RST_MASK              0x20000u
#define SRC_SICR_SNVS_HARD_RST_SHIFT             17
#define SRC_SICR_CSU_ALARM_RST_MASK              0x80000u
#define SRC_SICR_CSU_ALARM_RST_SHIFT             19
#define SRC_SICR_REG_1P1_MASK                    0x1000000u
#define SRC_SICR_REG_1P1_SHIFT                   24
#define SRC_SICR_REG_2P5_MASK                    0x2000000u
#define SRC_SICR_REG_2P5_SHIFT                   25
#define SRC_SICR_REG_3P0_MASK                    0x4000000u
#define SRC_SICR_REG_3P0_SHIFT                   26
#define SRC_SICR_CMU_OLR_MASK                    0x8000000u
#define SRC_SICR_CMU_OLR_SHIFT                   27
#define SRC_SICR_CMU_FLL_FHH_MASK                0x10000000u
#define SRC_SICR_CMU_FLL_FHH_SHIFT               28
#define SRC_SICR_CM4_LCK_MASK                    0x80000000u
#define SRC_SICR_CM4_LCK_SHIFT                   31
/* SIMR Bit Fields */
#define SRC_SIMR_CA5_WDG_RST_MASK                0x2u
#define SRC_SIMR_CA5_WDG_RST_SHIFT               1
#define SRC_SIMR_WDOG_RST_MASK                   0x18u
#define SRC_SIMR_WDOG_RST_SHIFT                  3
#define SRC_SIMR_WDOG_RST(x)                     (((uint32_t)(((uint32_t)(x))<<SRC_SIMR_WDOG_RST_SHIFT))&SRC_SIMR_WDOG_RST_MASK)
#define SRC_SIMR_JTAG_RST_MASK                   0x20u
#define SRC_SIMR_JTAG_RST_SHIFT                  5
#define SRC_SIMR_MDM_SYS_RST_MASK                0x10000u
#define SRC_SIMR_MDM_SYS_RST_SHIFT               16
#define SRC_SIMR_SNVS_HARD_RST_MASK              0x20000u
#define SRC_SIMR_SNVS_HARD_RST_SHIFT             17
#define SRC_SIMR_CSU_ALARM_RST_MASK              0x80000u
#define SRC_SIMR_CSU_ALARM_RST_SHIFT             19
#define SRC_SIMR_REG_1P1_OK_MASK                 0x1000000u
#define SRC_SIMR_REG_1P1_OK_SHIFT                24
#define SRC_SIMR_REG_2P5_OK_MASK                 0x2000000u
#define SRC_SIMR_REG_2P5_OK_SHIFT                25
#define SRC_SIMR_REG_3P0_OK_MASK                 0x4000000u
#define SRC_SIMR_REG_3P0_OK_SHIFT                26
#define SRC_SIMR_CMU_OLR_MASK                    0x8000000u
#define SRC_SIMR_CMU_OLR_SHIFT                   27
#define SRC_SIMR_CMU_FLL_FHH_MASK                0x10000000u
#define SRC_SIMR_CMU_FLL_FHH_SHIFT               28
#define SRC_SIMR_SOSC_OK_MASK                    0x40000000u
#define SRC_SIMR_SOSC_OK_SHIFT                   30
#define SRC_SIMR_CM4_LCK_MASK                    0x80000000u
#define SRC_SIMR_CM4_LCK_SHIFT                   31
/* SBMR2 Bit Fields */
#define SRC_SBMR2_SEC_CONFIG_MASK                0x3u
#define SRC_SBMR2_SEC_CONFIG_SHIFT               0
#define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_SEC_CONFIG_SHIFT))&SRC_SBMR2_SEC_CONFIG_MASK)
#define SRC_SBMR2_DIR_BT_DIS_MASK                0x8u
#define SRC_SBMR2_DIR_BT_DIS_SHIFT               3
#define SRC_SBMR2_BT_FUSE_SEL_MASK               0x10u
#define SRC_SBMR2_BT_FUSE_SEL_SHIFT              4
#define SRC_SBMR2_BMOD_MASK                      0x3000000u
#define SRC_SBMR2_BMOD_SHIFT                     24
#define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_BMOD_SHIFT))&SRC_SBMR2_BMOD_MASK)
/* GPR Bit Fields */
#define SRC_GPR_GP_MASK                          0xFFFFFFFFu
#define SRC_GPR_GP_SHIFT                         0
#define SRC_GPR_GP(x)                            (((uint32_t)(((uint32_t)(x))<<SRC_GPR_GP_SHIFT))&SRC_GPR_GP_MASK)
/* HAB Bit Fields */
#define SRC_HAB_GP_MASK                          0xFFFFFFFFu
#define SRC_HAB_GP_SHIFT                         0
#define SRC_HAB_GP(x)                            (((uint32_t)(((uint32_t)(x))<<SRC_HAB_GP_SHIFT))&SRC_HAB_GP_MASK)
/* MISC0 Bit Fields */
#define SRC_MISC0_MISC0_15_1_MASK                0xFFFFu
#define SRC_MISC0_MISC0_15_1_SHIFT               0
#define SRC_MISC0_MISC0_15_1(x)                  (((uint32_t)(((uint32_t)(x))<<SRC_MISC0_MISC0_15_1_SHIFT))&SRC_MISC0_MISC0_15_1_MASK)
#define SRC_MISC0_MISC0_25_16_MASK               0x3FF0000u
#define SRC_MISC0_MISC0_25_16_SHIFT              16
#define SRC_MISC0_MISC0_25_16(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_MISC0_MISC0_25_16_SHIFT))&SRC_MISC0_MISC0_25_16_MASK)
#define SRC_MISC0_MISC0_26_MASK                  0x4000000u
#define SRC_MISC0_MISC0_26_SHIFT                 26
#define SRC_MISC0_MISC0_27_MASK                  0x8000000u
#define SRC_MISC0_MISC0_27_SHIFT                 27
#define SRC_MISC0_MISC0_28_MASK                  0x10000000u
#define SRC_MISC0_MISC0_28_SHIFT                 28
#define SRC_MISC0_MISC0_29_MASK                  0x20000000u
#define SRC_MISC0_MISC0_29_SHIFT                 29
#define SRC_MISC0_MISC0_30_MASK                  0x40000000u
#define SRC_MISC0_MISC0_30_SHIFT                 30
#define SRC_MISC0_MISC0_31_MASK                  0x80000000u
#define SRC_MISC0_MISC0_31_SHIFT                 31
/* MISC1 Bit Fields */
#define SRC_MISC1_MISC1_0_MASK                   0x1u
#define SRC_MISC1_MISC1_0_SHIFT                  0
#define SRC_MISC1_MISC1_1_MASK                   0x2u
#define SRC_MISC1_MISC1_1_SHIFT                  1
#define SRC_MISC1_MISC1_2_MASK                   0x4u
#define SRC_MISC1_MISC1_2_SHIFT                  2
#define SRC_MISC1_MISC1_3_MASK                   0x8u
#define SRC_MISC1_MISC1_3_SHIFT                  3
#define SRC_MISC1_MISC1_4_MASK                   0x10u
#define SRC_MISC1_MISC1_4_SHIFT                  4
#define SRC_MISC1_MISC1_5_MASK                   0x20u
#define SRC_MISC1_MISC1_5_SHIFT                  5
#define SRC_MISC1_MISC1_6_MASK                   0x40u
#define SRC_MISC1_MISC1_6_SHIFT                  6
#define SRC_MISC1_MISC1_7_MASK                   0x80u
#define SRC_MISC1_MISC1_7_SHIFT                  7
#define SRC_MISC1_MISC1_8_MASK                   0x100u
#define SRC_MISC1_MISC1_8_SHIFT                  8
#define SRC_MISC1_MISC1_9_MASK                   0x200u
#define SRC_MISC1_MISC1_9_SHIFT                  9
#define SRC_MISC1_MISC1_10_MASK                  0x400u
#define SRC_MISC1_MISC1_10_SHIFT                 10
#define SRC_MISC1_MISC1_11_MASK                  0x800u
#define SRC_MISC1_MISC1_11_SHIFT                 11
#define SRC_MISC1_MISC1_12_MASK                  0x1000u
#define SRC_MISC1_MISC1_12_SHIFT                 12
#define SRC_MISC1_MISC1_13_MASK                  0x2000u
#define SRC_MISC1_MISC1_13_SHIFT                 13
#define SRC_MISC1_MISC1_14_MASK                  0x4000u
#define SRC_MISC1_MISC1_14_SHIFT                 14
#define SRC_MISC1_MISC1_15_MASK                  0x8000u
#define SRC_MISC1_MISC1_15_SHIFT                 15
#define SRC_MISC1_MISC1_25_16_MASK               0x3FF0000u
#define SRC_MISC1_MISC1_25_16_SHIFT              16
#define SRC_MISC1_MISC1_25_16(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_MISC1_MISC1_25_16_SHIFT))&SRC_MISC1_MISC1_25_16_MASK)
#define SRC_MISC1_MISC1_26_MASK                  0x4000000u
#define SRC_MISC1_MISC1_26_SHIFT                 26
#define SRC_MISC1_MISC1_27_MASK                  0x8000000u
#define SRC_MISC1_MISC1_27_SHIFT                 27
#define SRC_MISC1_MISC1_28_MASK                  0x10000000u
#define SRC_MISC1_MISC1_28_SHIFT                 28
#define SRC_MISC1_MISC1_29_MASK                  0x20000000u
#define SRC_MISC1_MISC1_29_SHIFT                 29
#define SRC_MISC1_MISC1_30_MASK                  0x40000000u
#define SRC_MISC1_MISC1_30_SHIFT                 30
#define SRC_MISC1_MISC1_31_MASK                  0x80000000u
#define SRC_MISC1_MISC1_31_SHIFT                 31
/* MISC2 Bit Fields */
#define SRC_MISC2_MISC2_0_MASK                   0x1u
#define SRC_MISC2_MISC2_0_SHIFT                  0
#define SRC_MISC2_MISC2_7_3_MASK                 0xF8u
#define SRC_MISC2_MISC2_7_3_SHIFT                3
#define SRC_MISC2_MISC2_7_3(x)                   (((uint32_t)(((uint32_t)(x))<<SRC_MISC2_MISC2_7_3_SHIFT))&SRC_MISC2_MISC2_7_3_MASK)
#define SRC_MISC2_MISC2_8_MASK                   0x100u
#define SRC_MISC2_MISC2_8_SHIFT                  8
#define SRC_MISC2_MISC2_9_MASK                   0x200u
#define SRC_MISC2_MISC2_9_SHIFT                  9
#define SRC_MISC2_MISC2_15_10_MASK               0xFC00u
#define SRC_MISC2_MISC2_15_10_SHIFT              10
#define SRC_MISC2_MISC2_15_10(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_MISC2_MISC2_15_10_SHIFT))&SRC_MISC2_MISC2_15_10_MASK)
#define SRC_MISC2_MISC2_31_16_MASK               0xFFFF0000u
#define SRC_MISC2_MISC2_31_16_SHIFT              16
#define SRC_MISC2_MISC2_31_16(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_MISC2_MISC2_31_16_SHIFT))&SRC_MISC2_MISC2_31_16_MASK)
/* MISC3 Bit Fields */
#define SRC_MISC3_MISC3_0_MASK                   0x1u
#define SRC_MISC3_MISC3_0_SHIFT                  0
#define SRC_MISC3_MISC3_1_MASK                   0x2u
#define SRC_MISC3_MISC3_1_SHIFT                  1
#define SRC_MISC3_MISC3_2_MASK                   0x4u
#define SRC_MISC3_MISC3_2_SHIFT                  2
#define SRC_MISC3_MISC3_3_MASK                   0x8u
#define SRC_MISC3_MISC3_3_SHIFT                  3
#define SRC_MISC3_MISC3_4_MASK                   0x10u
#define SRC_MISC3_MISC3_4_SHIFT                  4
#define SRC_MISC3_MISC3_5_MASK                   0x20u
#define SRC_MISC3_MISC3_5_SHIFT                  5
#define SRC_MISC3_MISC3_6_MASK                   0x40u
#define SRC_MISC3_MISC3_6_SHIFT                  6
#define SRC_MISC3_MISC3_7_MASK                   0x80u
#define SRC_MISC3_MISC3_7_SHIFT                  7
#define SRC_MISC3_MISC3_8_MASK                   0x100u
#define SRC_MISC3_MISC3_8_SHIFT                  8
#define SRC_MISC3_MISC3_9_MASK                   0x200u
#define SRC_MISC3_MISC3_9_SHIFT                  9
#define SRC_MISC3_MISC3_10_MASK                  0x400u
#define SRC_MISC3_MISC3_10_SHIFT                 10
#define SRC_MISC3_MISC3_11_MASK                  0x800u
#define SRC_MISC3_MISC3_11_SHIFT                 11
#define SRC_MISC3_MISC3_12_MASK                  0x1000u
#define SRC_MISC3_MISC3_12_SHIFT                 12
#define SRC_MISC3_MISC3_15_13_MASK               0xE000u
#define SRC_MISC3_MISC3_15_13_SHIFT              13
#define SRC_MISC3_MISC3_15_13(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_MISC3_MISC3_15_13_SHIFT))&SRC_MISC3_MISC3_15_13_MASK)
#define SRC_MISC3_MISC3_31_16_MASK               0xFFFF0000u
#define SRC_MISC3_MISC3_31_16_SHIFT              16
#define SRC_MISC3_MISC3_31_16(x)                 (((uint32_t)(((uint32_t)(x))<<SRC_MISC3_MISC3_31_16_SHIFT))&SRC_MISC3_MISC3_31_16_MASK)

/**
 * @}
 */ /* end of group SRC_Register_Masks */


/* SRC - Peripheral instance base addresses */
/** Peripheral SRC base address */
#define SRC_BASE                                 (0x4006E000u)
/** Peripheral SRC base pointer */
#define SRC                                      ((SRC_Type *)SRC_BASE)
/** Array initializer of SRC peripheral base pointers */
#define SRC_BASES                                { SRC }

/**
 * @}
 */ /* end of group SRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TCON Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup TCON_Peripheral_Access_Layer TCON Peripheral Access Layer
 * @{
 */

/** TCON - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL1;                             /**< TCON control1 register, offset: 0x0 */
  __IO uint32_t BMC;                               /**< Bit map control register, offset: 0x4 */
  __IO uint32_t COMP0;                             /**< Comparator 0 configure register, offset: 0x8 */
  __IO uint32_t COMP1;                             /**< Comparator 1 configure register, offset: 0xC */
  __IO uint32_t COMP2;                             /**< Comparator 2 configure register, offset: 0x10 */
  __IO uint32_t COMP3;                             /**< Comparator 3 configure register, offset: 0x14 */
  __IO uint32_t COMP0_MSK;                         /**< Comparator 0 compare value mask register, offset: 0x18 */
  __IO uint32_t COMP1_MSK;                         /**< Comparator 1 compare value mask register, offset: 0x1C */
  __IO uint32_t COMP2_MSK;                         /**< Comparator 2 compare value mask register, offset: 0x20 */
  __IO uint32_t COMP3_MSK;                         /**< Comparator 3 compare value mask register, offset: 0x24 */
  __IO uint32_t PULSE0;                            /**< Pulse 0 configure register, offset: 0x28 */
  __IO uint32_t PULSE1;                            /**< Pulse 1 configure register, offset: 0x2C */
  __IO uint32_t PULSE2;                            /**< Pulse 2 configure register, offset: 0x30 */
  __IO uint32_t PULSE3;                            /**< Pulse 3 configure register, offset: 0x34 */
  __IO uint32_t PULSE4;                            /**< Pulse 4 configure register, offset: 0x38 */
  __IO uint32_t PULSE5;                            /**< Pulse 5 configure register, offset: 0x3C */
  __IO uint32_t PULSE0_MSK;                        /**< Pulse 0 compare value mask register, offset: 0x40 */
  __IO uint32_t PULSE1_MSK;                        /**< Pulse 1 compare value mask register, offset: 0x44 */
  __IO uint32_t PULSE2_MSK;                        /**< Pulse 2 compare value mask register, offset: 0x48 */
  __IO uint32_t PULSE3_MSK;                        /**< Pulse 3 compare value mask register, offset: 0x4C */
  __IO uint32_t PULSE4_MSK;                        /**< Pulse 4 compare value mask register, offset: 0x50 */
  __IO uint32_t PULSE5_MSK;                        /**< Pulse 5 compare value mask register, offset: 0x54 */
  __IO uint32_t SMX0;                              /**< Function control register 0, offset: 0x58 */
  __IO uint32_t SMX1;                              /**< Function control register 1, offset: 0x5C */
  __IO uint32_t SMX2;                              /**< Function control registers 2, offset: 0x60 */
  __IO uint32_t SMX3;                              /**< Function control register 3, offset: 0x64 */
  __IO uint32_t SMX4;                              /**< Function control register 4, offset: 0x68 */
  __IO uint32_t SMX5;                              /**< Function control register 5, offset: 0x6C */
  __IO uint32_t SMX6;                              /**< Function control register 6, offset: 0x70 */
  __IO uint32_t SMX7;                              /**< Function control register 7, offset: 0x74 */
  __IO uint32_t SMX8;                              /**< Function control register 8, offset: 0x78 */
  __IO uint32_t SMX9;                              /**< Function control register 9, offset: 0x7C */
  __IO uint32_t SMX10;                             /**< Function control register 10, offset: 0x80 */
  __IO uint32_t SMX11;                             /**< Function control register 11, offset: 0x84 */
  __IO uint32_t SMX12;                             /**< Function control register 12, offset: 0x88 */
  __IO uint32_t SMX13;                             /**< Function control register 13, offset: 0x8C */
  __IO uint32_t OMUX_LOW;                          /**< TCON output mux control low, offset: 0x90 */
  __IO uint32_t OMUX_HIGH;                         /**< TCON output mux control high, offset: 0x94 */
  __IO uint32_t LUT0;                              /**< TCON look up table 0, offset: 0x98 */
  __IO uint32_t LUT1;                              /**< TCON look up table 1, offset: 0x9C */
  __IO uint32_t LUT2;                              /**< TCON look up table 2, offset: 0xA0 */
  __IO uint32_t LUT3;                              /**< TCON look up table 3, offset: 0xA4 */
  __IO uint32_t LUT4;                              /**< TCON look up table 4, offset: 0xA8 */
  __IO uint32_t LUT5;                              /**< TCON look up table 5, offset: 0xAC */
  __IO uint32_t LUT6;                              /**< TCON look up table 6, offset: 0xB0 */
  __IO uint32_t LUT7;                              /**< TCON look up table 7, offset: 0xB4 */
  __IO uint32_t LUT8;                              /**< TCON look up table 8, offset: 0xB8 */
  __IO uint32_t LUT9;                              /**< TCON look up tables 9, offset: 0xBC */
  __IO uint32_t LUT10;                             /**< TCON look up table 10, offset: 0xC0 */
  __IO uint32_t LUT11;                             /**< TCON look up table 11, offset: 0xC4 */
  __IO uint32_t LUT12;                             /**< TCON look up table 12, offset: 0xC8 */
  __IO uint32_t LUT13;                             /**< TCON look up table 13, offset: 0xCC */
       uint8_t RESERVED_0[52];
  __IO uint32_t CTRL2;                             /**< TCON control2 register, offset: 0x104 */
} TCON_Type;

/* ----------------------------------------------------------------------------
   -- TCON Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup TCON_Register_Masks TCON Register Masks
 * @{
 */

/* CTRL1 Bit Fields */
#define TCON_CTRL1_RGB_PADDING_MASK              0x2u
#define TCON_CTRL1_RGB_PADDING_SHIFT             1
#define TCON_CTRL1_RGB_PADDING_EN_MASK           0x4u
#define TCON_CTRL1_RGB_PADDING_EN_SHIFT          2
#define TCON_CTRL1_COLOR_DEPTH_MASK              0x8u
#define TCON_CTRL1_COLOR_DEPTH_SHIFT             3
#define TCON_CTRL1_VSYNC_INV_MASK                0x10u
#define TCON_CTRL1_VSYNC_INV_SHIFT               4
#define TCON_CTRL1_HSYNC_INV_MASK                0x20u
#define TCON_CTRL1_HSYNC_INV_SHIFT               5
#define TCON_CTRL1_VLEN_MASK                     0xC0u
#define TCON_CTRL1_VLEN_SHIFT                    6
#define TCON_CTRL1_VLEN(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_CTRL1_VLEN_SHIFT))&TCON_CTRL1_VLEN_MASK)
#define TCON_CTRL1_H_REF_SEL_MASK                0x300u
#define TCON_CTRL1_H_REF_SEL_SHIFT               8
#define TCON_CTRL1_H_REF_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_CTRL1_H_REF_SEL_SHIFT))&TCON_CTRL1_H_REF_SEL_MASK)
#define TCON_CTRL1_V_REF_SEL_MASK                0x1C00u
#define TCON_CTRL1_V_REF_SEL_SHIFT               10
#define TCON_CTRL1_V_REF_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_CTRL1_V_REF_SEL_SHIFT))&TCON_CTRL1_V_REF_SEL_MASK)
#define TCON_CTRL1_INIT_DELAY_MASK               0xE000u
#define TCON_CTRL1_INIT_DELAY_SHIFT              13
#define TCON_CTRL1_INIT_DELAY(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_CTRL1_INIT_DELAY_SHIFT))&TCON_CTRL1_INIT_DELAY_MASK)
#define TCON_CTRL1_TCONx_INV_MASK                0xFFF0000u
#define TCON_CTRL1_TCONx_INV_SHIFT               16
#define TCON_CTRL1_TCONx_INV(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_CTRL1_TCONx_INV_SHIFT))&TCON_CTRL1_TCONx_INV_MASK)
#define TCON_CTRL1_INV_EN_MASK                   0x10000000u
#define TCON_CTRL1_INV_EN_SHIFT                  28
#define TCON_CTRL1_TCON_BYPASS_MASK              0x20000000u
#define TCON_CTRL1_TCON_BYPASS_SHIFT             29
#define TCON_CTRL1_TCON_EN_MASK                  0x80000000u
#define TCON_CTRL1_TCON_EN_SHIFT                 31
/* BMC Bit Fields */
#define TCON_BMC_BIT_ORDER_MASK                  0x2u
#define TCON_BMC_BIT_ORDER_SHIFT                 1
#define TCON_BMC_COLOR_ORDER_MASK                0x1Cu
#define TCON_BMC_COLOR_ORDER_SHIFT               2
#define TCON_BMC_COLOR_ORDER(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_BMC_COLOR_ORDER_SHIFT))&TCON_BMC_COLOR_ORDER_MASK)
#define TCON_BMC_CLK_POS_MASK                    0x3E0u
#define TCON_BMC_CLK_POS_SHIFT                   5
#define TCON_BMC_CLK_POS(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_BMC_CLK_POS_SHIFT))&TCON_BMC_CLK_POS_MASK)
/* COMP0 Bit Fields */
#define TCON_COMP0_COMP_VALUE_MASK               0xFFFu
#define TCON_COMP0_COMP_VALUE_SHIFT              0
#define TCON_COMP0_COMP_VALUE(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_COMP0_COMP_VALUE_SHIFT))&TCON_COMP0_COMP_VALUE_MASK)
#define TCON_COMP0_FUNC_SEL_MASK                 0x80000000u
#define TCON_COMP0_FUNC_SEL_SHIFT                31
/* COMP1 Bit Fields */
#define TCON_COMP1_COMP_VALUE_MASK               0xFFFu
#define TCON_COMP1_COMP_VALUE_SHIFT              0
#define TCON_COMP1_COMP_VALUE(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_COMP1_COMP_VALUE_SHIFT))&TCON_COMP1_COMP_VALUE_MASK)
#define TCON_COMP1_FUNC_SEL_MASK                 0x80000000u
#define TCON_COMP1_FUNC_SEL_SHIFT                31
/* COMP2 Bit Fields */
#define TCON_COMP2_COMP_VALUE_MASK               0xFFFu
#define TCON_COMP2_COMP_VALUE_SHIFT              0
#define TCON_COMP2_COMP_VALUE(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_COMP2_COMP_VALUE_SHIFT))&TCON_COMP2_COMP_VALUE_MASK)
#define TCON_COMP2_FUNC_SEL_MASK                 0x80000000u
#define TCON_COMP2_FUNC_SEL_SHIFT                31
/* COMP3 Bit Fields */
#define TCON_COMP3_COMP_VALUE_MASK               0xFFFu
#define TCON_COMP3_COMP_VALUE_SHIFT              0
#define TCON_COMP3_COMP_VALUE(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_COMP3_COMP_VALUE_SHIFT))&TCON_COMP3_COMP_VALUE_MASK)
#define TCON_COMP3_FUNC_SEL_MASK                 0x80000000u
#define TCON_COMP3_FUNC_SEL_SHIFT                31
/* COMP0_MSK Bit Fields */
#define TCON_COMP0_MSK_MSK_MASK                  0xFFFu
#define TCON_COMP0_MSK_MSK_SHIFT                 0
#define TCON_COMP0_MSK_MSK(x)                    (((uint32_t)(((uint32_t)(x))<<TCON_COMP0_MSK_MSK_SHIFT))&TCON_COMP0_MSK_MSK_MASK)
/* COMP1_MSK Bit Fields */
#define TCON_COMP1_MSK_MSK_MASK                  0xFFFu
#define TCON_COMP1_MSK_MSK_SHIFT                 0
#define TCON_COMP1_MSK_MSK(x)                    (((uint32_t)(((uint32_t)(x))<<TCON_COMP1_MSK_MSK_SHIFT))&TCON_COMP1_MSK_MSK_MASK)
/* COMP2_MSK Bit Fields */
#define TCON_COMP2_MSK_MSK_MASK                  0xFFFu
#define TCON_COMP2_MSK_MSK_SHIFT                 0
#define TCON_COMP2_MSK_MSK(x)                    (((uint32_t)(((uint32_t)(x))<<TCON_COMP2_MSK_MSK_SHIFT))&TCON_COMP2_MSK_MSK_MASK)
/* COMP3_MSK Bit Fields */
#define TCON_COMP3_MSK_MSK_MASK                  0xFFFu
#define TCON_COMP3_MSK_MSK_SHIFT                 0
#define TCON_COMP3_MSK_MSK(x)                    (((uint32_t)(((uint32_t)(x))<<TCON_COMP3_MSK_MSK_SHIFT))&TCON_COMP3_MSK_MSK_MASK)
/* PULSE0 Bit Fields */
#define TCON_PULSE0_RESET_MASK                   0xFFFu
#define TCON_PULSE0_RESET_SHIFT                  0
#define TCON_PULSE0_RESET(x)                     (((uint32_t)(((uint32_t)(x))<<TCON_PULSE0_RESET_SHIFT))&TCON_PULSE0_RESET_MASK)
#define TCON_PULSE0_COMPARATOR_SEL_MASK          0xC000u
#define TCON_PULSE0_COMPARATOR_SEL_SHIFT         14
#define TCON_PULSE0_COMPARATOR_SEL(x)            (((uint32_t)(((uint32_t)(x))<<TCON_PULSE0_COMPARATOR_SEL_SHIFT))&TCON_PULSE0_COMPARATOR_SEL_MASK)
#define TCON_PULSE0_SET_MASK                     0xFFF0000u
#define TCON_PULSE0_SET_SHIFT                    16
#define TCON_PULSE0_SET(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_PULSE0_SET_SHIFT))&TCON_PULSE0_SET_MASK)
#define TCON_PULSE0_FUNC_SEL_MASK                0xC0000000u
#define TCON_PULSE0_FUNC_SEL_SHIFT               30
#define TCON_PULSE0_FUNC_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_PULSE0_FUNC_SEL_SHIFT))&TCON_PULSE0_FUNC_SEL_MASK)
/* PULSE1 Bit Fields */
#define TCON_PULSE1_RESET_MASK                   0xFFFu
#define TCON_PULSE1_RESET_SHIFT                  0
#define TCON_PULSE1_RESET(x)                     (((uint32_t)(((uint32_t)(x))<<TCON_PULSE1_RESET_SHIFT))&TCON_PULSE1_RESET_MASK)
#define TCON_PULSE1_COMPARATOR_SEL_MASK          0xC000u
#define TCON_PULSE1_COMPARATOR_SEL_SHIFT         14
#define TCON_PULSE1_COMPARATOR_SEL(x)            (((uint32_t)(((uint32_t)(x))<<TCON_PULSE1_COMPARATOR_SEL_SHIFT))&TCON_PULSE1_COMPARATOR_SEL_MASK)
#define TCON_PULSE1_SET_MASK                     0xFFF0000u
#define TCON_PULSE1_SET_SHIFT                    16
#define TCON_PULSE1_SET(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_PULSE1_SET_SHIFT))&TCON_PULSE1_SET_MASK)
#define TCON_PULSE1_FUNC_SEL_MASK                0xC0000000u
#define TCON_PULSE1_FUNC_SEL_SHIFT               30
#define TCON_PULSE1_FUNC_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_PULSE1_FUNC_SEL_SHIFT))&TCON_PULSE1_FUNC_SEL_MASK)
/* PULSE2 Bit Fields */
#define TCON_PULSE2_RESET_MASK                   0xFFFu
#define TCON_PULSE2_RESET_SHIFT                  0
#define TCON_PULSE2_RESET(x)                     (((uint32_t)(((uint32_t)(x))<<TCON_PULSE2_RESET_SHIFT))&TCON_PULSE2_RESET_MASK)
#define TCON_PULSE2_COMPARATOR_SEL_MASK          0xC000u
#define TCON_PULSE2_COMPARATOR_SEL_SHIFT         14
#define TCON_PULSE2_COMPARATOR_SEL(x)            (((uint32_t)(((uint32_t)(x))<<TCON_PULSE2_COMPARATOR_SEL_SHIFT))&TCON_PULSE2_COMPARATOR_SEL_MASK)
#define TCON_PULSE2_SET_MASK                     0xFFF0000u
#define TCON_PULSE2_SET_SHIFT                    16
#define TCON_PULSE2_SET(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_PULSE2_SET_SHIFT))&TCON_PULSE2_SET_MASK)
#define TCON_PULSE2_FUNC_SEL_MASK                0xC0000000u
#define TCON_PULSE2_FUNC_SEL_SHIFT               30
#define TCON_PULSE2_FUNC_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_PULSE2_FUNC_SEL_SHIFT))&TCON_PULSE2_FUNC_SEL_MASK)
/* PULSE3 Bit Fields */
#define TCON_PULSE3_RESET_MASK                   0xFFFu
#define TCON_PULSE3_RESET_SHIFT                  0
#define TCON_PULSE3_RESET(x)                     (((uint32_t)(((uint32_t)(x))<<TCON_PULSE3_RESET_SHIFT))&TCON_PULSE3_RESET_MASK)
#define TCON_PULSE3_COMPARATOR_SEL_MASK          0xC000u
#define TCON_PULSE3_COMPARATOR_SEL_SHIFT         14
#define TCON_PULSE3_COMPARATOR_SEL(x)            (((uint32_t)(((uint32_t)(x))<<TCON_PULSE3_COMPARATOR_SEL_SHIFT))&TCON_PULSE3_COMPARATOR_SEL_MASK)
#define TCON_PULSE3_SET_MASK                     0xFFF0000u
#define TCON_PULSE3_SET_SHIFT                    16
#define TCON_PULSE3_SET(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_PULSE3_SET_SHIFT))&TCON_PULSE3_SET_MASK)
#define TCON_PULSE3_FUNC_SEL_MASK                0xC0000000u
#define TCON_PULSE3_FUNC_SEL_SHIFT               30
#define TCON_PULSE3_FUNC_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_PULSE3_FUNC_SEL_SHIFT))&TCON_PULSE3_FUNC_SEL_MASK)
/* PULSE4 Bit Fields */
#define TCON_PULSE4_RESET_MASK                   0xFFFu
#define TCON_PULSE4_RESET_SHIFT                  0
#define TCON_PULSE4_RESET(x)                     (((uint32_t)(((uint32_t)(x))<<TCON_PULSE4_RESET_SHIFT))&TCON_PULSE4_RESET_MASK)
#define TCON_PULSE4_COMPARATOR_SEL_MASK          0xC000u
#define TCON_PULSE4_COMPARATOR_SEL_SHIFT         14
#define TCON_PULSE4_COMPARATOR_SEL(x)            (((uint32_t)(((uint32_t)(x))<<TCON_PULSE4_COMPARATOR_SEL_SHIFT))&TCON_PULSE4_COMPARATOR_SEL_MASK)
#define TCON_PULSE4_SET_MASK                     0xFFF0000u
#define TCON_PULSE4_SET_SHIFT                    16
#define TCON_PULSE4_SET(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_PULSE4_SET_SHIFT))&TCON_PULSE4_SET_MASK)
#define TCON_PULSE4_FUNC_SEL_MASK                0xC0000000u
#define TCON_PULSE4_FUNC_SEL_SHIFT               30
#define TCON_PULSE4_FUNC_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_PULSE4_FUNC_SEL_SHIFT))&TCON_PULSE4_FUNC_SEL_MASK)
/* PULSE5 Bit Fields */
#define TCON_PULSE5_RESET_MASK                   0xFFFu
#define TCON_PULSE5_RESET_SHIFT                  0
#define TCON_PULSE5_RESET(x)                     (((uint32_t)(((uint32_t)(x))<<TCON_PULSE5_RESET_SHIFT))&TCON_PULSE5_RESET_MASK)
#define TCON_PULSE5_COMPARATOR_SEL_MASK          0xC000u
#define TCON_PULSE5_COMPARATOR_SEL_SHIFT         14
#define TCON_PULSE5_COMPARATOR_SEL(x)            (((uint32_t)(((uint32_t)(x))<<TCON_PULSE5_COMPARATOR_SEL_SHIFT))&TCON_PULSE5_COMPARATOR_SEL_MASK)
#define TCON_PULSE5_SET_MASK                     0xFFF0000u
#define TCON_PULSE5_SET_SHIFT                    16
#define TCON_PULSE5_SET(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_PULSE5_SET_SHIFT))&TCON_PULSE5_SET_MASK)
#define TCON_PULSE5_FUNC_SEL_MASK                0xC0000000u
#define TCON_PULSE5_FUNC_SEL_SHIFT               30
#define TCON_PULSE5_FUNC_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_PULSE5_FUNC_SEL_SHIFT))&TCON_PULSE5_FUNC_SEL_MASK)
/* PULSE0_MSK Bit Fields */
#define TCON_PULSE0_MSK_RESET_MSK_MASK           0xFFFu
#define TCON_PULSE0_MSK_RESET_MSK_SHIFT          0
#define TCON_PULSE0_MSK_RESET_MSK(x)             (((uint32_t)(((uint32_t)(x))<<TCON_PULSE0_MSK_RESET_MSK_SHIFT))&TCON_PULSE0_MSK_RESET_MSK_MASK)
#define TCON_PULSE0_MSK_SET_MSK_MASK             0xFFF0000u
#define TCON_PULSE0_MSK_SET_MSK_SHIFT            16
#define TCON_PULSE0_MSK_SET_MSK(x)               (((uint32_t)(((uint32_t)(x))<<TCON_PULSE0_MSK_SET_MSK_SHIFT))&TCON_PULSE0_MSK_SET_MSK_MASK)
/* PULSE1_MSK Bit Fields */
#define TCON_PULSE1_MSK_RESET_MSK_MASK           0xFFFu
#define TCON_PULSE1_MSK_RESET_MSK_SHIFT          0
#define TCON_PULSE1_MSK_RESET_MSK(x)             (((uint32_t)(((uint32_t)(x))<<TCON_PULSE1_MSK_RESET_MSK_SHIFT))&TCON_PULSE1_MSK_RESET_MSK_MASK)
#define TCON_PULSE1_MSK_SET_MSK_MASK             0xFFF0000u
#define TCON_PULSE1_MSK_SET_MSK_SHIFT            16
#define TCON_PULSE1_MSK_SET_MSK(x)               (((uint32_t)(((uint32_t)(x))<<TCON_PULSE1_MSK_SET_MSK_SHIFT))&TCON_PULSE1_MSK_SET_MSK_MASK)
/* PULSE2_MSK Bit Fields */
#define TCON_PULSE2_MSK_RESET_MSK_MASK           0xFFFu
#define TCON_PULSE2_MSK_RESET_MSK_SHIFT          0
#define TCON_PULSE2_MSK_RESET_MSK(x)             (((uint32_t)(((uint32_t)(x))<<TCON_PULSE2_MSK_RESET_MSK_SHIFT))&TCON_PULSE2_MSK_RESET_MSK_MASK)
#define TCON_PULSE2_MSK_SET_MSK_MASK             0xFFF0000u
#define TCON_PULSE2_MSK_SET_MSK_SHIFT            16
#define TCON_PULSE2_MSK_SET_MSK(x)               (((uint32_t)(((uint32_t)(x))<<TCON_PULSE2_MSK_SET_MSK_SHIFT))&TCON_PULSE2_MSK_SET_MSK_MASK)
/* PULSE3_MSK Bit Fields */
#define TCON_PULSE3_MSK_RESET_MSK_MASK           0xFFFu
#define TCON_PULSE3_MSK_RESET_MSK_SHIFT          0
#define TCON_PULSE3_MSK_RESET_MSK(x)             (((uint32_t)(((uint32_t)(x))<<TCON_PULSE3_MSK_RESET_MSK_SHIFT))&TCON_PULSE3_MSK_RESET_MSK_MASK)
#define TCON_PULSE3_MSK_SET_MSK_MASK             0xFFF0000u
#define TCON_PULSE3_MSK_SET_MSK_SHIFT            16
#define TCON_PULSE3_MSK_SET_MSK(x)               (((uint32_t)(((uint32_t)(x))<<TCON_PULSE3_MSK_SET_MSK_SHIFT))&TCON_PULSE3_MSK_SET_MSK_MASK)
/* PULSE4_MSK Bit Fields */
#define TCON_PULSE4_MSK_RESET_MSK_MASK           0xFFFu
#define TCON_PULSE4_MSK_RESET_MSK_SHIFT          0
#define TCON_PULSE4_MSK_RESET_MSK(x)             (((uint32_t)(((uint32_t)(x))<<TCON_PULSE4_MSK_RESET_MSK_SHIFT))&TCON_PULSE4_MSK_RESET_MSK_MASK)
#define TCON_PULSE4_MSK_SET_MSK_MASK             0xFFF0000u
#define TCON_PULSE4_MSK_SET_MSK_SHIFT            16
#define TCON_PULSE4_MSK_SET_MSK(x)               (((uint32_t)(((uint32_t)(x))<<TCON_PULSE4_MSK_SET_MSK_SHIFT))&TCON_PULSE4_MSK_SET_MSK_MASK)
/* PULSE5_MSK Bit Fields */
#define TCON_PULSE5_MSK_RESET_MSK_MASK           0xFFFu
#define TCON_PULSE5_MSK_RESET_MSK_SHIFT          0
#define TCON_PULSE5_MSK_RESET_MSK(x)             (((uint32_t)(((uint32_t)(x))<<TCON_PULSE5_MSK_RESET_MSK_SHIFT))&TCON_PULSE5_MSK_RESET_MSK_MASK)
#define TCON_PULSE5_MSK_SET_MSK_MASK             0xFFF0000u
#define TCON_PULSE5_MSK_SET_MSK_SHIFT            16
#define TCON_PULSE5_MSK_SET_MSK(x)               (((uint32_t)(((uint32_t)(x))<<TCON_PULSE5_MSK_SET_MSK_SHIFT))&TCON_PULSE5_MSK_SET_MSK_MASK)
/* SMX0 Bit Fields */
#define TCON_SMX0_X_SEL_MASK                     0x1Fu
#define TCON_SMX0_X_SEL_SHIFT                    0
#define TCON_SMX0_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX0_X_SEL_SHIFT))&TCON_SMX0_X_SEL_MASK)
#define TCON_SMX0_Y_SEL_MASK                     0x3E0u
#define TCON_SMX0_Y_SEL_SHIFT                    5
#define TCON_SMX0_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX0_Y_SEL_SHIFT))&TCON_SMX0_Y_SEL_MASK)
#define TCON_SMX0_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX0_INDEX0_SEL_SHIFT               20
#define TCON_SMX0_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX0_INDEX0_SEL_SHIFT))&TCON_SMX0_INDEX0_SEL_MASK)
#define TCON_SMX0_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX0_INDEX1_SEL_SHIFT               23
#define TCON_SMX0_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX0_INDEX1_SEL_SHIFT))&TCON_SMX0_INDEX1_SEL_MASK)
#define TCON_SMX0_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX0_INDEX2_SEL_SHIFT               26
#define TCON_SMX0_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX0_INDEX2_SEL_SHIFT))&TCON_SMX0_INDEX2_SEL_MASK)
#define TCON_SMX0_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX0_INDEX3_SEL_SHIFT               29
#define TCON_SMX0_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX0_INDEX3_SEL_SHIFT))&TCON_SMX0_INDEX3_SEL_MASK)
/* SMX1 Bit Fields */
#define TCON_SMX1_X_SEL_MASK                     0x1Fu
#define TCON_SMX1_X_SEL_SHIFT                    0
#define TCON_SMX1_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX1_X_SEL_SHIFT))&TCON_SMX1_X_SEL_MASK)
#define TCON_SMX1_Y_SEL_MASK                     0x3E0u
#define TCON_SMX1_Y_SEL_SHIFT                    5
#define TCON_SMX1_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX1_Y_SEL_SHIFT))&TCON_SMX1_Y_SEL_MASK)
#define TCON_SMX1_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX1_INDEX0_SEL_SHIFT               20
#define TCON_SMX1_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX1_INDEX0_SEL_SHIFT))&TCON_SMX1_INDEX0_SEL_MASK)
#define TCON_SMX1_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX1_INDEX1_SEL_SHIFT               23
#define TCON_SMX1_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX1_INDEX1_SEL_SHIFT))&TCON_SMX1_INDEX1_SEL_MASK)
#define TCON_SMX1_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX1_INDEX2_SEL_SHIFT               26
#define TCON_SMX1_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX1_INDEX2_SEL_SHIFT))&TCON_SMX1_INDEX2_SEL_MASK)
#define TCON_SMX1_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX1_INDEX3_SEL_SHIFT               29
#define TCON_SMX1_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX1_INDEX3_SEL_SHIFT))&TCON_SMX1_INDEX3_SEL_MASK)
/* SMX2 Bit Fields */
#define TCON_SMX2_X_SEL_MASK                     0x1Fu
#define TCON_SMX2_X_SEL_SHIFT                    0
#define TCON_SMX2_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX2_X_SEL_SHIFT))&TCON_SMX2_X_SEL_MASK)
#define TCON_SMX2_Y_SEL_MASK                     0x3E0u
#define TCON_SMX2_Y_SEL_SHIFT                    5
#define TCON_SMX2_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX2_Y_SEL_SHIFT))&TCON_SMX2_Y_SEL_MASK)
#define TCON_SMX2_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX2_INDEX0_SEL_SHIFT               20
#define TCON_SMX2_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX2_INDEX0_SEL_SHIFT))&TCON_SMX2_INDEX0_SEL_MASK)
#define TCON_SMX2_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX2_INDEX1_SEL_SHIFT               23
#define TCON_SMX2_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX2_INDEX1_SEL_SHIFT))&TCON_SMX2_INDEX1_SEL_MASK)
#define TCON_SMX2_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX2_INDEX2_SEL_SHIFT               26
#define TCON_SMX2_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX2_INDEX2_SEL_SHIFT))&TCON_SMX2_INDEX2_SEL_MASK)
#define TCON_SMX2_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX2_INDEX3_SEL_SHIFT               29
#define TCON_SMX2_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX2_INDEX3_SEL_SHIFT))&TCON_SMX2_INDEX3_SEL_MASK)
/* SMX3 Bit Fields */
#define TCON_SMX3_X_SEL_MASK                     0x1Fu
#define TCON_SMX3_X_SEL_SHIFT                    0
#define TCON_SMX3_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX3_X_SEL_SHIFT))&TCON_SMX3_X_SEL_MASK)
#define TCON_SMX3_Y_SEL_MASK                     0x3E0u
#define TCON_SMX3_Y_SEL_SHIFT                    5
#define TCON_SMX3_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX3_Y_SEL_SHIFT))&TCON_SMX3_Y_SEL_MASK)
#define TCON_SMX3_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX3_INDEX0_SEL_SHIFT               20
#define TCON_SMX3_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX3_INDEX0_SEL_SHIFT))&TCON_SMX3_INDEX0_SEL_MASK)
#define TCON_SMX3_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX3_INDEX1_SEL_SHIFT               23
#define TCON_SMX3_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX3_INDEX1_SEL_SHIFT))&TCON_SMX3_INDEX1_SEL_MASK)
#define TCON_SMX3_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX3_INDEX2_SEL_SHIFT               26
#define TCON_SMX3_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX3_INDEX2_SEL_SHIFT))&TCON_SMX3_INDEX2_SEL_MASK)
#define TCON_SMX3_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX3_INDEX3_SEL_SHIFT               29
#define TCON_SMX3_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX3_INDEX3_SEL_SHIFT))&TCON_SMX3_INDEX3_SEL_MASK)
/* SMX4 Bit Fields */
#define TCON_SMX4_X_SEL_MASK                     0x1Fu
#define TCON_SMX4_X_SEL_SHIFT                    0
#define TCON_SMX4_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX4_X_SEL_SHIFT))&TCON_SMX4_X_SEL_MASK)
#define TCON_SMX4_Y_SEL_MASK                     0x3E0u
#define TCON_SMX4_Y_SEL_SHIFT                    5
#define TCON_SMX4_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX4_Y_SEL_SHIFT))&TCON_SMX4_Y_SEL_MASK)
#define TCON_SMX4_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX4_INDEX0_SEL_SHIFT               20
#define TCON_SMX4_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX4_INDEX0_SEL_SHIFT))&TCON_SMX4_INDEX0_SEL_MASK)
#define TCON_SMX4_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX4_INDEX1_SEL_SHIFT               23
#define TCON_SMX4_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX4_INDEX1_SEL_SHIFT))&TCON_SMX4_INDEX1_SEL_MASK)
#define TCON_SMX4_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX4_INDEX2_SEL_SHIFT               26
#define TCON_SMX4_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX4_INDEX2_SEL_SHIFT))&TCON_SMX4_INDEX2_SEL_MASK)
#define TCON_SMX4_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX4_INDEX3_SEL_SHIFT               29
#define TCON_SMX4_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX4_INDEX3_SEL_SHIFT))&TCON_SMX4_INDEX3_SEL_MASK)
/* SMX5 Bit Fields */
#define TCON_SMX5_X_SEL_MASK                     0x1Fu
#define TCON_SMX5_X_SEL_SHIFT                    0
#define TCON_SMX5_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX5_X_SEL_SHIFT))&TCON_SMX5_X_SEL_MASK)
#define TCON_SMX5_Y_SEL_MASK                     0x3E0u
#define TCON_SMX5_Y_SEL_SHIFT                    5
#define TCON_SMX5_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX5_Y_SEL_SHIFT))&TCON_SMX5_Y_SEL_MASK)
#define TCON_SMX5_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX5_INDEX0_SEL_SHIFT               20
#define TCON_SMX5_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX5_INDEX0_SEL_SHIFT))&TCON_SMX5_INDEX0_SEL_MASK)
#define TCON_SMX5_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX5_INDEX1_SEL_SHIFT               23
#define TCON_SMX5_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX5_INDEX1_SEL_SHIFT))&TCON_SMX5_INDEX1_SEL_MASK)
#define TCON_SMX5_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX5_INDEX2_SEL_SHIFT               26
#define TCON_SMX5_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX5_INDEX2_SEL_SHIFT))&TCON_SMX5_INDEX2_SEL_MASK)
#define TCON_SMX5_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX5_INDEX3_SEL_SHIFT               29
#define TCON_SMX5_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX5_INDEX3_SEL_SHIFT))&TCON_SMX5_INDEX3_SEL_MASK)
/* SMX6 Bit Fields */
#define TCON_SMX6_X_SEL_MASK                     0x1Fu
#define TCON_SMX6_X_SEL_SHIFT                    0
#define TCON_SMX6_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX6_X_SEL_SHIFT))&TCON_SMX6_X_SEL_MASK)
#define TCON_SMX6_Y_SEL_MASK                     0x3E0u
#define TCON_SMX6_Y_SEL_SHIFT                    5
#define TCON_SMX6_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX6_Y_SEL_SHIFT))&TCON_SMX6_Y_SEL_MASK)
#define TCON_SMX6_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX6_INDEX0_SEL_SHIFT               20
#define TCON_SMX6_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX6_INDEX0_SEL_SHIFT))&TCON_SMX6_INDEX0_SEL_MASK)
#define TCON_SMX6_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX6_INDEX1_SEL_SHIFT               23
#define TCON_SMX6_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX6_INDEX1_SEL_SHIFT))&TCON_SMX6_INDEX1_SEL_MASK)
#define TCON_SMX6_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX6_INDEX2_SEL_SHIFT               26
#define TCON_SMX6_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX6_INDEX2_SEL_SHIFT))&TCON_SMX6_INDEX2_SEL_MASK)
#define TCON_SMX6_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX6_INDEX3_SEL_SHIFT               29
#define TCON_SMX6_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX6_INDEX3_SEL_SHIFT))&TCON_SMX6_INDEX3_SEL_MASK)
/* SMX7 Bit Fields */
#define TCON_SMX7_X_SEL_MASK                     0x1Fu
#define TCON_SMX7_X_SEL_SHIFT                    0
#define TCON_SMX7_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX7_X_SEL_SHIFT))&TCON_SMX7_X_SEL_MASK)
#define TCON_SMX7_Y_SEL_MASK                     0x3E0u
#define TCON_SMX7_Y_SEL_SHIFT                    5
#define TCON_SMX7_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX7_Y_SEL_SHIFT))&TCON_SMX7_Y_SEL_MASK)
#define TCON_SMX7_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX7_INDEX0_SEL_SHIFT               20
#define TCON_SMX7_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX7_INDEX0_SEL_SHIFT))&TCON_SMX7_INDEX0_SEL_MASK)
#define TCON_SMX7_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX7_INDEX1_SEL_SHIFT               23
#define TCON_SMX7_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX7_INDEX1_SEL_SHIFT))&TCON_SMX7_INDEX1_SEL_MASK)
#define TCON_SMX7_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX7_INDEX2_SEL_SHIFT               26
#define TCON_SMX7_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX7_INDEX2_SEL_SHIFT))&TCON_SMX7_INDEX2_SEL_MASK)
#define TCON_SMX7_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX7_INDEX3_SEL_SHIFT               29
#define TCON_SMX7_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX7_INDEX3_SEL_SHIFT))&TCON_SMX7_INDEX3_SEL_MASK)
/* SMX8 Bit Fields */
#define TCON_SMX8_X_SEL_MASK                     0x1Fu
#define TCON_SMX8_X_SEL_SHIFT                    0
#define TCON_SMX8_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX8_X_SEL_SHIFT))&TCON_SMX8_X_SEL_MASK)
#define TCON_SMX8_Y_SEL_MASK                     0x3E0u
#define TCON_SMX8_Y_SEL_SHIFT                    5
#define TCON_SMX8_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX8_Y_SEL_SHIFT))&TCON_SMX8_Y_SEL_MASK)
#define TCON_SMX8_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX8_INDEX0_SEL_SHIFT               20
#define TCON_SMX8_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX8_INDEX0_SEL_SHIFT))&TCON_SMX8_INDEX0_SEL_MASK)
#define TCON_SMX8_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX8_INDEX1_SEL_SHIFT               23
#define TCON_SMX8_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX8_INDEX1_SEL_SHIFT))&TCON_SMX8_INDEX1_SEL_MASK)
#define TCON_SMX8_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX8_INDEX2_SEL_SHIFT               26
#define TCON_SMX8_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX8_INDEX2_SEL_SHIFT))&TCON_SMX8_INDEX2_SEL_MASK)
#define TCON_SMX8_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX8_INDEX3_SEL_SHIFT               29
#define TCON_SMX8_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX8_INDEX3_SEL_SHIFT))&TCON_SMX8_INDEX3_SEL_MASK)
/* SMX9 Bit Fields */
#define TCON_SMX9_X_SEL_MASK                     0x1Fu
#define TCON_SMX9_X_SEL_SHIFT                    0
#define TCON_SMX9_X_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX9_X_SEL_SHIFT))&TCON_SMX9_X_SEL_MASK)
#define TCON_SMX9_Y_SEL_MASK                     0x3E0u
#define TCON_SMX9_Y_SEL_SHIFT                    5
#define TCON_SMX9_Y_SEL(x)                       (((uint32_t)(((uint32_t)(x))<<TCON_SMX9_Y_SEL_SHIFT))&TCON_SMX9_Y_SEL_MASK)
#define TCON_SMX9_INDEX0_SEL_MASK                0x700000u
#define TCON_SMX9_INDEX0_SEL_SHIFT               20
#define TCON_SMX9_INDEX0_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX9_INDEX0_SEL_SHIFT))&TCON_SMX9_INDEX0_SEL_MASK)
#define TCON_SMX9_INDEX1_SEL_MASK                0x3800000u
#define TCON_SMX9_INDEX1_SEL_SHIFT               23
#define TCON_SMX9_INDEX1_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX9_INDEX1_SEL_SHIFT))&TCON_SMX9_INDEX1_SEL_MASK)
#define TCON_SMX9_INDEX2_SEL_MASK                0x1C000000u
#define TCON_SMX9_INDEX2_SEL_SHIFT               26
#define TCON_SMX9_INDEX2_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX9_INDEX2_SEL_SHIFT))&TCON_SMX9_INDEX2_SEL_MASK)
#define TCON_SMX9_INDEX3_SEL_MASK                0xE0000000u
#define TCON_SMX9_INDEX3_SEL_SHIFT               29
#define TCON_SMX9_INDEX3_SEL(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_SMX9_INDEX3_SEL_SHIFT))&TCON_SMX9_INDEX3_SEL_MASK)
/* SMX10 Bit Fields */
#define TCON_SMX10_X_SEL_MASK                    0x1Fu
#define TCON_SMX10_X_SEL_SHIFT                   0
#define TCON_SMX10_X_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX10_X_SEL_SHIFT))&TCON_SMX10_X_SEL_MASK)
#define TCON_SMX10_Y_SEL_MASK                    0x3E0u
#define TCON_SMX10_Y_SEL_SHIFT                   5
#define TCON_SMX10_Y_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX10_Y_SEL_SHIFT))&TCON_SMX10_Y_SEL_MASK)
#define TCON_SMX10_INDEX0_SEL_MASK               0x700000u
#define TCON_SMX10_INDEX0_SEL_SHIFT              20
#define TCON_SMX10_INDEX0_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX10_INDEX0_SEL_SHIFT))&TCON_SMX10_INDEX0_SEL_MASK)
#define TCON_SMX10_INDEX1_SEL_MASK               0x3800000u
#define TCON_SMX10_INDEX1_SEL_SHIFT              23
#define TCON_SMX10_INDEX1_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX10_INDEX1_SEL_SHIFT))&TCON_SMX10_INDEX1_SEL_MASK)
#define TCON_SMX10_INDEX2_SEL_MASK               0x1C000000u
#define TCON_SMX10_INDEX2_SEL_SHIFT              26
#define TCON_SMX10_INDEX2_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX10_INDEX2_SEL_SHIFT))&TCON_SMX10_INDEX2_SEL_MASK)
#define TCON_SMX10_INDEX3_SEL_MASK               0xE0000000u
#define TCON_SMX10_INDEX3_SEL_SHIFT              29
#define TCON_SMX10_INDEX3_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX10_INDEX3_SEL_SHIFT))&TCON_SMX10_INDEX3_SEL_MASK)
/* SMX11 Bit Fields */
#define TCON_SMX11_X_SEL_MASK                    0x1Fu
#define TCON_SMX11_X_SEL_SHIFT                   0
#define TCON_SMX11_X_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX11_X_SEL_SHIFT))&TCON_SMX11_X_SEL_MASK)
#define TCON_SMX11_Y_SEL_MASK                    0x3E0u
#define TCON_SMX11_Y_SEL_SHIFT                   5
#define TCON_SMX11_Y_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX11_Y_SEL_SHIFT))&TCON_SMX11_Y_SEL_MASK)
#define TCON_SMX11_INDEX0_SEL_MASK               0x700000u
#define TCON_SMX11_INDEX0_SEL_SHIFT              20
#define TCON_SMX11_INDEX0_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX11_INDEX0_SEL_SHIFT))&TCON_SMX11_INDEX0_SEL_MASK)
#define TCON_SMX11_INDEX1_SEL_MASK               0x3800000u
#define TCON_SMX11_INDEX1_SEL_SHIFT              23
#define TCON_SMX11_INDEX1_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX11_INDEX1_SEL_SHIFT))&TCON_SMX11_INDEX1_SEL_MASK)
#define TCON_SMX11_INDEX2_SEL_MASK               0x1C000000u
#define TCON_SMX11_INDEX2_SEL_SHIFT              26
#define TCON_SMX11_INDEX2_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX11_INDEX2_SEL_SHIFT))&TCON_SMX11_INDEX2_SEL_MASK)
#define TCON_SMX11_INDEX3_SEL_MASK               0xE0000000u
#define TCON_SMX11_INDEX3_SEL_SHIFT              29
#define TCON_SMX11_INDEX3_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX11_INDEX3_SEL_SHIFT))&TCON_SMX11_INDEX3_SEL_MASK)
/* SMX12 Bit Fields */
#define TCON_SMX12_X_SEL_MASK                    0x1Fu
#define TCON_SMX12_X_SEL_SHIFT                   0
#define TCON_SMX12_X_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX12_X_SEL_SHIFT))&TCON_SMX12_X_SEL_MASK)
#define TCON_SMX12_Y_SEL_MASK                    0x3E0u
#define TCON_SMX12_Y_SEL_SHIFT                   5
#define TCON_SMX12_Y_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX12_Y_SEL_SHIFT))&TCON_SMX12_Y_SEL_MASK)
#define TCON_SMX12_INDEX0_SEL_MASK               0x700000u
#define TCON_SMX12_INDEX0_SEL_SHIFT              20
#define TCON_SMX12_INDEX0_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX12_INDEX0_SEL_SHIFT))&TCON_SMX12_INDEX0_SEL_MASK)
#define TCON_SMX12_INDEX1_SEL_MASK               0x3800000u
#define TCON_SMX12_INDEX1_SEL_SHIFT              23
#define TCON_SMX12_INDEX1_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX12_INDEX1_SEL_SHIFT))&TCON_SMX12_INDEX1_SEL_MASK)
#define TCON_SMX12_INDEX2_SEL_MASK               0x1C000000u
#define TCON_SMX12_INDEX2_SEL_SHIFT              26
#define TCON_SMX12_INDEX2_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX12_INDEX2_SEL_SHIFT))&TCON_SMX12_INDEX2_SEL_MASK)
#define TCON_SMX12_INDEX3_SEL_MASK               0xE0000000u
#define TCON_SMX12_INDEX3_SEL_SHIFT              29
#define TCON_SMX12_INDEX3_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX12_INDEX3_SEL_SHIFT))&TCON_SMX12_INDEX3_SEL_MASK)
/* SMX13 Bit Fields */
#define TCON_SMX13_X_SEL_MASK                    0x1Fu
#define TCON_SMX13_X_SEL_SHIFT                   0
#define TCON_SMX13_X_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX13_X_SEL_SHIFT))&TCON_SMX13_X_SEL_MASK)
#define TCON_SMX13_Y_SEL_MASK                    0x3E0u
#define TCON_SMX13_Y_SEL_SHIFT                   5
#define TCON_SMX13_Y_SEL(x)                      (((uint32_t)(((uint32_t)(x))<<TCON_SMX13_Y_SEL_SHIFT))&TCON_SMX13_Y_SEL_MASK)
#define TCON_SMX13_INDEX0_SEL_MASK               0x700000u
#define TCON_SMX13_INDEX0_SEL_SHIFT              20
#define TCON_SMX13_INDEX0_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX13_INDEX0_SEL_SHIFT))&TCON_SMX13_INDEX0_SEL_MASK)
#define TCON_SMX13_INDEX1_SEL_MASK               0x3800000u
#define TCON_SMX13_INDEX1_SEL_SHIFT              23
#define TCON_SMX13_INDEX1_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX13_INDEX1_SEL_SHIFT))&TCON_SMX13_INDEX1_SEL_MASK)
#define TCON_SMX13_INDEX2_SEL_MASK               0x1C000000u
#define TCON_SMX13_INDEX2_SEL_SHIFT              26
#define TCON_SMX13_INDEX2_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX13_INDEX2_SEL_SHIFT))&TCON_SMX13_INDEX2_SEL_MASK)
#define TCON_SMX13_INDEX3_SEL_MASK               0xE0000000u
#define TCON_SMX13_INDEX3_SEL_SHIFT              29
#define TCON_SMX13_INDEX3_SEL(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_SMX13_INDEX3_SEL_SHIFT))&TCON_SMX13_INDEX3_SEL_MASK)
/* OMUX_LOW Bit Fields */
#define TCON_OMUX_LOW_TCON0_MASK                 0x1Fu
#define TCON_OMUX_LOW_TCON0_SHIFT                0
#define TCON_OMUX_LOW_TCON0(x)                   (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_LOW_TCON0_SHIFT))&TCON_OMUX_LOW_TCON0_MASK)
#define TCON_OMUX_LOW_TCON1_MASK                 0x3E0u
#define TCON_OMUX_LOW_TCON1_SHIFT                5
#define TCON_OMUX_LOW_TCON1(x)                   (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_LOW_TCON1_SHIFT))&TCON_OMUX_LOW_TCON1_MASK)
#define TCON_OMUX_LOW_TCON2_MASK                 0x7C00u
#define TCON_OMUX_LOW_TCON2_SHIFT                10
#define TCON_OMUX_LOW_TCON2(x)                   (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_LOW_TCON2_SHIFT))&TCON_OMUX_LOW_TCON2_MASK)
#define TCON_OMUX_LOW_TCON3_MASK                 0xF8000u
#define TCON_OMUX_LOW_TCON3_SHIFT                15
#define TCON_OMUX_LOW_TCON3(x)                   (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_LOW_TCON3_SHIFT))&TCON_OMUX_LOW_TCON3_MASK)
#define TCON_OMUX_LOW_TCON4_MASK                 0x1F00000u
#define TCON_OMUX_LOW_TCON4_SHIFT                20
#define TCON_OMUX_LOW_TCON4(x)                   (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_LOW_TCON4_SHIFT))&TCON_OMUX_LOW_TCON4_MASK)
#define TCON_OMUX_LOW_TCON5_MASK                 0x3E000000u
#define TCON_OMUX_LOW_TCON5_SHIFT                25
#define TCON_OMUX_LOW_TCON5(x)                   (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_LOW_TCON5_SHIFT))&TCON_OMUX_LOW_TCON5_MASK)
/* OMUX_HIGH Bit Fields */
#define TCON_OMUX_HIGH_TCON6_MASK                0x1Fu
#define TCON_OMUX_HIGH_TCON6_SHIFT               0
#define TCON_OMUX_HIGH_TCON6(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_HIGH_TCON6_SHIFT))&TCON_OMUX_HIGH_TCON6_MASK)
#define TCON_OMUX_HIGH_TCON7_MASK                0x3E0u
#define TCON_OMUX_HIGH_TCON7_SHIFT               5
#define TCON_OMUX_HIGH_TCON7(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_HIGH_TCON7_SHIFT))&TCON_OMUX_HIGH_TCON7_MASK)
#define TCON_OMUX_HIGH_TCON8_MASK                0x7C00u
#define TCON_OMUX_HIGH_TCON8_SHIFT               10
#define TCON_OMUX_HIGH_TCON8(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_HIGH_TCON8_SHIFT))&TCON_OMUX_HIGH_TCON8_MASK)
#define TCON_OMUX_HIGH_TCON9_MASK                0xF8000u
#define TCON_OMUX_HIGH_TCON9_SHIFT               15
#define TCON_OMUX_HIGH_TCON9(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_HIGH_TCON9_SHIFT))&TCON_OMUX_HIGH_TCON9_MASK)
#define TCON_OMUX_HIGH_TCON10_MASK               0x1F00000u
#define TCON_OMUX_HIGH_TCON10_SHIFT              20
#define TCON_OMUX_HIGH_TCON10(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_HIGH_TCON10_SHIFT))&TCON_OMUX_HIGH_TCON10_MASK)
#define TCON_OMUX_HIGH_TCON11_MASK               0x3E000000u
#define TCON_OMUX_HIGH_TCON11_SHIFT              25
#define TCON_OMUX_HIGH_TCON11(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_OMUX_HIGH_TCON11_SHIFT))&TCON_OMUX_HIGH_TCON11_MASK)
/* LUT0 Bit Fields */
#define TCON_LUT0_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT0_LUT_SHIFT                      0
#define TCON_LUT0_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT0_LUT_SHIFT))&TCON_LUT0_LUT_MASK)
/* LUT1 Bit Fields */
#define TCON_LUT1_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT1_LUT_SHIFT                      0
#define TCON_LUT1_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT1_LUT_SHIFT))&TCON_LUT1_LUT_MASK)
/* LUT2 Bit Fields */
#define TCON_LUT2_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT2_LUT_SHIFT                      0
#define TCON_LUT2_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT2_LUT_SHIFT))&TCON_LUT2_LUT_MASK)
/* LUT3 Bit Fields */
#define TCON_LUT3_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT3_LUT_SHIFT                      0
#define TCON_LUT3_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT3_LUT_SHIFT))&TCON_LUT3_LUT_MASK)
/* LUT4 Bit Fields */
#define TCON_LUT4_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT4_LUT_SHIFT                      0
#define TCON_LUT4_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT4_LUT_SHIFT))&TCON_LUT4_LUT_MASK)
/* LUT5 Bit Fields */
#define TCON_LUT5_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT5_LUT_SHIFT                      0
#define TCON_LUT5_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT5_LUT_SHIFT))&TCON_LUT5_LUT_MASK)
/* LUT6 Bit Fields */
#define TCON_LUT6_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT6_LUT_SHIFT                      0
#define TCON_LUT6_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT6_LUT_SHIFT))&TCON_LUT6_LUT_MASK)
/* LUT7 Bit Fields */
#define TCON_LUT7_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT7_LUT_SHIFT                      0
#define TCON_LUT7_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT7_LUT_SHIFT))&TCON_LUT7_LUT_MASK)
/* LUT8 Bit Fields */
#define TCON_LUT8_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT8_LUT_SHIFT                      0
#define TCON_LUT8_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT8_LUT_SHIFT))&TCON_LUT8_LUT_MASK)
/* LUT9 Bit Fields */
#define TCON_LUT9_LUT_MASK                       0xFFFFFFFFu
#define TCON_LUT9_LUT_SHIFT                      0
#define TCON_LUT9_LUT(x)                         (((uint32_t)(((uint32_t)(x))<<TCON_LUT9_LUT_SHIFT))&TCON_LUT9_LUT_MASK)
/* LUT10 Bit Fields */
#define TCON_LUT10_LUT_MASK                      0xFFFFFFFFu
#define TCON_LUT10_LUT_SHIFT                     0
#define TCON_LUT10_LUT(x)                        (((uint32_t)(((uint32_t)(x))<<TCON_LUT10_LUT_SHIFT))&TCON_LUT10_LUT_MASK)
/* LUT11 Bit Fields */
#define TCON_LUT11_LUT_MASK                      0xFFFFFFFFu
#define TCON_LUT11_LUT_SHIFT                     0
#define TCON_LUT11_LUT(x)                        (((uint32_t)(((uint32_t)(x))<<TCON_LUT11_LUT_SHIFT))&TCON_LUT11_LUT_MASK)
/* LUT12 Bit Fields */
#define TCON_LUT12_LUT_MASK                      0xFFFFFFFFu
#define TCON_LUT12_LUT_SHIFT                     0
#define TCON_LUT12_LUT(x)                        (((uint32_t)(((uint32_t)(x))<<TCON_LUT12_LUT_SHIFT))&TCON_LUT12_LUT_MASK)
/* LUT13 Bit Fields */
#define TCON_LUT13_LUT_MASK                      0xFFFFFFFFu
#define TCON_LUT13_LUT_SHIFT                     0
#define TCON_LUT13_LUT(x)                        (((uint32_t)(((uint32_t)(x))<<TCON_LUT13_LUT_SHIFT))&TCON_LUT13_LUT_MASK)
/* CTRL2 Bit Fields */
#define TCON_CTRL2_DIV_RATIO_MASK                0xFFu
#define TCON_CTRL2_DIV_RATIO_SHIFT               0
#define TCON_CTRL2_DIV_RATIO(x)                  (((uint32_t)(((uint32_t)(x))<<TCON_CTRL2_DIV_RATIO_SHIFT))&TCON_CTRL2_DIV_RATIO_MASK)
#define TCON_CTRL2_CLK_OFFSET_MASK               0x1FF0000u
#define TCON_CTRL2_CLK_OFFSET_SHIFT              16
#define TCON_CTRL2_CLK_OFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<TCON_CTRL2_CLK_OFFSET_SHIFT))&TCON_CTRL2_CLK_OFFSET_MASK)

/**
 * @}
 */ /* end of group TCON_Register_Masks */


/* TCON - Peripheral instance base addresses */
/** Peripheral TCON0 base address */
#define TCON0_BASE                               (0x4003D000u)
/** Peripheral TCON0 base pointer */
#define TCON0                                    ((TCON_Type *)TCON0_BASE)
/** Peripheral TCON1 base address */
#define TCON1_BASE                               (0x400BD000u)
/** Peripheral TCON1 base pointer */
#define TCON1                                    ((TCON_Type *)TCON1_BASE)
/** Array initializer of TCON peripheral base pointers */
#define TCON_BASES                               { TCON0, TCON1 }

/**
 * @}
 */ /* end of group TCON_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- UART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
 * @{
 */

/** UART - Register Layout Typedef */
typedef struct {
  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
       uint8_t RESERVED_0[1];
  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
       uint8_t RESERVED_1[1];
  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
  union {                                          /* offset: 0x1B */
    __IO uint8_t WP7816_T_TYPE0;                     /**< UART 7816 Wait Parameter Register, offset: 0x1B */
    __IO uint8_t WP7816_T_TYPE1;                     /**< UART 7816 Wait Parameter Register, offset: 0x1B */
  };
  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
       uint8_t RESERVED_2[1];
  __IO uint8_t C6;                                 /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
  __IO uint8_t PCTH;                               /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
  __IO uint8_t PCTL;                               /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
  __IO uint8_t B1T;                                /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
  __IO uint8_t SDTH;                               /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
  __IO uint8_t SDTL;                               /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
  __IO uint8_t PRE;                                /**< UART CEA709.1-B Preamble, offset: 0x27 */
  __IO uint8_t TPL;                                /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
  __IO uint8_t IE;                                 /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
       uint8_t RESERVED_3[1];
  __IO uint8_t S3;                                 /**< UART CEA709.1-B Status Register, offset: 0x2B */
  __IO uint8_t S4;                                 /**< UART CEA709.1-B Status Register, offset: 0x2C */
  __I  uint8_t RPL;                                /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
  __I  uint8_t RPREL;                              /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
  __IO uint8_t CPW;                                /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
  __IO uint8_t RIDT;                               /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
  __IO uint8_t TIDT;                               /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
} UART_Type;

/* ----------------------------------------------------------------------------
   -- UART Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup UART_Register_Masks UART Register Masks
 * @{
 */

/* BDH Bit Fields */
#define UART_BDH_SBR_MASK                        0x1Fu
#define UART_BDH_SBR_SHIFT                       0
#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
#define UART_BDH_RXEDGIE_MASK                    0x40u
#define UART_BDH_RXEDGIE_SHIFT                   6
#define UART_BDH_LBKDIE_MASK                     0x80u
#define UART_BDH_LBKDIE_SHIFT                    7
/* BDL Bit Fields */
#define UART_BDL_SBR_MASK                        0xFFu
#define UART_BDL_SBR_SHIFT                       0
#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
/* C1 Bit Fields */
#define UART_C1_PT_MASK                          0x1u
#define UART_C1_PT_SHIFT                         0
#define UART_C1_PE_MASK                          0x2u
#define UART_C1_PE_SHIFT                         1
#define UART_C1_ILT_MASK                         0x4u
#define UART_C1_ILT_SHIFT                        2
#define UART_C1_WAKE_MASK                        0x8u
#define UART_C1_WAKE_SHIFT                       3
#define UART_C1_M_MASK                           0x10u
#define UART_C1_M_SHIFT                          4
#define UART_C1_RSRC_MASK                        0x20u
#define UART_C1_RSRC_SHIFT                       5
#define UART_C1_LOOPS_MASK                       0x80u
#define UART_C1_LOOPS_SHIFT                      7
/* C2 Bit Fields */
#define UART_C2_SBK_MASK                         0x1u
#define UART_C2_SBK_SHIFT                        0
#define UART_C2_RWU_MASK                         0x2u
#define UART_C2_RWU_SHIFT                        1
#define UART_C2_RE_MASK                          0x4u
#define UART_C2_RE_SHIFT                         2
#define UART_C2_TE_MASK                          0x8u
#define UART_C2_TE_SHIFT                         3
#define UART_C2_ILIE_MASK                        0x10u
#define UART_C2_ILIE_SHIFT                       4
#define UART_C2_RIE_MASK                         0x20u
#define UART_C2_RIE_SHIFT                        5
#define UART_C2_TCIE_MASK                        0x40u
#define UART_C2_TCIE_SHIFT                       6
#define UART_C2_TIE_MASK                         0x80u
#define UART_C2_TIE_SHIFT                        7
/* S1 Bit Fields */
#define UART_S1_PF_MASK                          0x1u
#define UART_S1_PF_SHIFT                         0
#define UART_S1_FE_MASK                          0x2u
#define UART_S1_FE_SHIFT                         1
#define UART_S1_NF_MASK                          0x4u
#define UART_S1_NF_SHIFT                         2
#define UART_S1_OR_MASK                          0x8u
#define UART_S1_OR_SHIFT                         3
#define UART_S1_IDLE_MASK                        0x10u
#define UART_S1_IDLE_SHIFT                       4
#define UART_S1_RDRF_MASK                        0x20u
#define UART_S1_RDRF_SHIFT                       5
#define UART_S1_TC_MASK                          0x40u
#define UART_S1_TC_SHIFT                         6
#define UART_S1_TDRE_MASK                        0x80u
#define UART_S1_TDRE_SHIFT                       7
/* S2 Bit Fields */
#define UART_S2_RAF_MASK                         0x1u
#define UART_S2_RAF_SHIFT                        0
#define UART_S2_LBKDE_MASK                       0x2u
#define UART_S2_LBKDE_SHIFT                      1
#define UART_S2_BRK13_MASK                       0x4u
#define UART_S2_BRK13_SHIFT                      2
#define UART_S2_RWUID_MASK                       0x8u
#define UART_S2_RWUID_SHIFT                      3
#define UART_S2_RXINV_MASK                       0x10u
#define UART_S2_RXINV_SHIFT                      4
#define UART_S2_MSBF_MASK                        0x20u
#define UART_S2_MSBF_SHIFT                       5
#define UART_S2_RXEDGIF_MASK                     0x40u
#define UART_S2_RXEDGIF_SHIFT                    6
#define UART_S2_LBKDIF_MASK                      0x80u
#define UART_S2_LBKDIF_SHIFT                     7
/* C3 Bit Fields */
#define UART_C3_PEIE_MASK                        0x1u
#define UART_C3_PEIE_SHIFT                       0
#define UART_C3_FEIE_MASK                        0x2u
#define UART_C3_FEIE_SHIFT                       1
#define UART_C3_NEIE_MASK                        0x4u
#define UART_C3_NEIE_SHIFT                       2
#define UART_C3_ORIE_MASK                        0x8u
#define UART_C3_ORIE_SHIFT                       3
#define UART_C3_TXINV_MASK                       0x10u
#define UART_C3_TXINV_SHIFT                      4
#define UART_C3_TXDIR_MASK                       0x20u
#define UART_C3_TXDIR_SHIFT                      5
#define UART_C3_T8_MASK                          0x40u
#define UART_C3_T8_SHIFT                         6
#define UART_C3_R8_MASK                          0x80u
#define UART_C3_R8_SHIFT                         7
/* D Bit Fields */
#define UART_D_RT_MASK                           0xFFu
#define UART_D_RT_SHIFT                          0
#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
/* MA1 Bit Fields */
#define UART_MA1_MA_MASK                         0xFFu
#define UART_MA1_MA_SHIFT                        0
#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
/* MA2 Bit Fields */
#define UART_MA2_MA_MASK                         0xFFu
#define UART_MA2_MA_SHIFT                        0
#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
/* C4 Bit Fields */
#define UART_C4_BRFA_MASK                        0x1Fu
#define UART_C4_BRFA_SHIFT                       0
#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
#define UART_C4_M10_MASK                         0x20u
#define UART_C4_M10_SHIFT                        5
#define UART_C4_MAEN2_MASK                       0x40u
#define UART_C4_MAEN2_SHIFT                      6
#define UART_C4_MAEN1_MASK                       0x80u
#define UART_C4_MAEN1_SHIFT                      7
/* C5 Bit Fields */
#define UART_C5_RDMAS_MASK                       0x20u
#define UART_C5_RDMAS_SHIFT                      5
#define UART_C5_TDMAS_MASK                       0x80u
#define UART_C5_TDMAS_SHIFT                      7
/* ED Bit Fields */
#define UART_ED_PARITYE_MASK                     0x40u
#define UART_ED_PARITYE_SHIFT                    6
#define UART_ED_NOISY_MASK                       0x80u
#define UART_ED_NOISY_SHIFT                      7
/* MODEM Bit Fields */
#define UART_MODEM_TXCTSE_MASK                   0x1u
#define UART_MODEM_TXCTSE_SHIFT                  0
#define UART_MODEM_TXRTSE_MASK                   0x2u
#define UART_MODEM_TXRTSE_SHIFT                  1
#define UART_MODEM_TXRTSPOL_MASK                 0x4u
#define UART_MODEM_TXRTSPOL_SHIFT                2
#define UART_MODEM_RXRTSE_MASK                   0x8u
#define UART_MODEM_RXRTSE_SHIFT                  3
/* IR Bit Fields */
#define UART_IR_TNP_MASK                         0x3u
#define UART_IR_TNP_SHIFT                        0
#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
#define UART_IR_IREN_MASK                        0x4u
#define UART_IR_IREN_SHIFT                       2
/* PFIFO Bit Fields */
#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
#define UART_PFIFO_RXFE_MASK                     0x8u
#define UART_PFIFO_RXFE_SHIFT                    3
#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
#define UART_PFIFO_TXFE_MASK                     0x80u
#define UART_PFIFO_TXFE_SHIFT                    7
/* CFIFO Bit Fields */
#define UART_CFIFO_RXUFE_MASK                    0x1u
#define UART_CFIFO_RXUFE_SHIFT                   0
#define UART_CFIFO_TXOFE_MASK                    0x2u
#define UART_CFIFO_TXOFE_SHIFT                   1
#define UART_CFIFO_RXOFE_MASK                    0x4u
#define UART_CFIFO_RXOFE_SHIFT                   2
#define UART_CFIFO_RXFLUSH_MASK                  0x40u
#define UART_CFIFO_RXFLUSH_SHIFT                 6
#define UART_CFIFO_TXFLUSH_MASK                  0x80u
#define UART_CFIFO_TXFLUSH_SHIFT                 7
/* SFIFO Bit Fields */
#define UART_SFIFO_RXUF_MASK                     0x1u
#define UART_SFIFO_RXUF_SHIFT                    0
#define UART_SFIFO_TXOF_MASK                     0x2u
#define UART_SFIFO_TXOF_SHIFT                    1
#define UART_SFIFO_RXOF_MASK                     0x4u
#define UART_SFIFO_RXOF_SHIFT                    2
#define UART_SFIFO_RXEMPT_MASK                   0x40u
#define UART_SFIFO_RXEMPT_SHIFT                  6
#define UART_SFIFO_TXEMPT_MASK                   0x80u
#define UART_SFIFO_TXEMPT_SHIFT                  7
/* TWFIFO Bit Fields */
#define UART_TWFIFO_TXWATER_MASK                 0xFFu
#define UART_TWFIFO_TXWATER_SHIFT                0
#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
/* TCFIFO Bit Fields */
#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
#define UART_TCFIFO_TXCOUNT_SHIFT                0
#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
/* RWFIFO Bit Fields */
#define UART_RWFIFO_RXWATER_MASK                 0xFFu
#define UART_RWFIFO_RXWATER_SHIFT                0
#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
/* RCFIFO Bit Fields */
#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
#define UART_RCFIFO_RXCOUNT_SHIFT                0
#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
/* C7816 Bit Fields */
#define UART_C7816_ISO_7816E_MASK                0x1u
#define UART_C7816_ISO_7816E_SHIFT               0
#define UART_C7816_TTYPE_MASK                    0x2u
#define UART_C7816_TTYPE_SHIFT                   1
#define UART_C7816_INIT_MASK                     0x4u
#define UART_C7816_INIT_SHIFT                    2
#define UART_C7816_ANACK_MASK                    0x8u
#define UART_C7816_ANACK_SHIFT                   3
#define UART_C7816_ONACK_MASK                    0x10u
#define UART_C7816_ONACK_SHIFT                   4
/* IE7816 Bit Fields */
#define UART_IE7816_RXTE_MASK                    0x1u
#define UART_IE7816_RXTE_SHIFT                   0
#define UART_IE7816_TXTE_MASK                    0x2u
#define UART_IE7816_TXTE_SHIFT                   1
#define UART_IE7816_GTVE_MASK                    0x4u
#define UART_IE7816_GTVE_SHIFT                   2
#define UART_IE7816_INITDE_MASK                  0x10u
#define UART_IE7816_INITDE_SHIFT                 4
#define UART_IE7816_BWTE_MASK                    0x20u
#define UART_IE7816_BWTE_SHIFT                   5
#define UART_IE7816_CWTE_MASK                    0x40u
#define UART_IE7816_CWTE_SHIFT                   6
#define UART_IE7816_WTE_MASK                     0x80u
#define UART_IE7816_WTE_SHIFT                    7
/* IS7816 Bit Fields */
#define UART_IS7816_RXT_MASK                     0x1u
#define UART_IS7816_RXT_SHIFT                    0
#define UART_IS7816_TXT_MASK                     0x2u
#define UART_IS7816_TXT_SHIFT                    1
#define UART_IS7816_GTV_MASK                     0x4u
#define UART_IS7816_GTV_SHIFT                    2
#define UART_IS7816_INITD_MASK                   0x10u
#define UART_IS7816_INITD_SHIFT                  4
#define UART_IS7816_BWT_MASK                     0x20u
#define UART_IS7816_BWT_SHIFT                    5
#define UART_IS7816_CWT_MASK                     0x40u
#define UART_IS7816_CWT_SHIFT                    6
#define UART_IS7816_WT_MASK                      0x80u
#define UART_IS7816_WT_SHIFT                     7
/* WP7816_T_TYPE0 Bit Fields */
#define UART_WP7816_T_TYPE0_WI_MASK              0xFFu
#define UART_WP7816_T_TYPE0_WI_SHIFT             0
#define UART_WP7816_T_TYPE0_WI(x)                (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
/* WP7816_T_TYPE1 Bit Fields */
#define UART_WP7816_T_TYPE1_BWI_MASK             0xFu
#define UART_WP7816_T_TYPE1_BWI_SHIFT            0
#define UART_WP7816_T_TYPE1_BWI(x)               (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
#define UART_WP7816_T_TYPE1_CWI_MASK             0xF0u
#define UART_WP7816_T_TYPE1_CWI_SHIFT            4
#define UART_WP7816_T_TYPE1_CWI(x)               (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
/* WN7816 Bit Fields */
#define UART_WN7816_GTN_MASK                     0xFFu
#define UART_WN7816_GTN_SHIFT                    0
#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
/* WF7816 Bit Fields */
#define UART_WF7816_GTFD_MASK                    0xFFu
#define UART_WF7816_GTFD_SHIFT                   0
#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
/* ET7816 Bit Fields */
#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
#define UART_ET7816_RXTHRESHOLD_SHIFT            0
#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
#define UART_ET7816_TXTHRESHOLD_SHIFT            4
#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
/* TL7816 Bit Fields */
#define UART_TL7816_TLEN_MASK                    0xFFu
#define UART_TL7816_TLEN_SHIFT                   0
#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
/* C6 Bit Fields */
#define UART_C6_CP_MASK                          0x10u
#define UART_C6_CP_SHIFT                         4
#define UART_C6_CE_MASK                          0x20u
#define UART_C6_CE_SHIFT                         5
#define UART_C6_TX709_MASK                       0x40u
#define UART_C6_TX709_SHIFT                      6
#define UART_C6_EN709_MASK                       0x80u
#define UART_C6_EN709_SHIFT                      7
/* PCTH Bit Fields */
#define UART_PCTH_PCTH_MASK                      0xFFu
#define UART_PCTH_PCTH_SHIFT                     0
#define UART_PCTH_PCTH(x)                        (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
/* PCTL Bit Fields */
#define UART_PCTL_PCTL_MASK                      0xFFu
#define UART_PCTL_PCTL_SHIFT                     0
#define UART_PCTL_PCTL(x)                        (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
/* B1T Bit Fields */
#define UART_B1T_B1T_MASK                        0xFFu
#define UART_B1T_B1T_SHIFT                       0
#define UART_B1T_B1T(x)                          (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
/* SDTH Bit Fields */
#define UART_SDTH_SDTH_MASK                      0xFFu
#define UART_SDTH_SDTH_SHIFT                     0
#define UART_SDTH_SDTH(x)                        (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
/* SDTL Bit Fields */
#define UART_SDTL_SDTL_MASK                      0xFFu
#define UART_SDTL_SDTL_SHIFT                     0
#define UART_SDTL_SDTL(x)                        (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
/* PRE Bit Fields */
#define UART_PRE_PREAMBLE_MASK                   0xFFu
#define UART_PRE_PREAMBLE_SHIFT                  0
#define UART_PRE_PREAMBLE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
/* TPL Bit Fields */
#define UART_TPL_TPL_MASK                        0xFFu
#define UART_TPL_TPL_SHIFT                       0
#define UART_TPL_TPL(x)                          (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
/* IE Bit Fields */
#define UART_IE_TXFIE_MASK                       0x1u
#define UART_IE_TXFIE_SHIFT                      0
#define UART_IE_PSIE_MASK                        0x2u
#define UART_IE_PSIE_SHIFT                       1
#define UART_IE_PCTEIE_MASK                      0x4u
#define UART_IE_PCTEIE_SHIFT                     2
#define UART_IE_PTXIE_MASK                       0x8u
#define UART_IE_PTXIE_SHIFT                      3
#define UART_IE_PRXIE_MASK                       0x10u
#define UART_IE_PRXIE_SHIFT                      4
#define UART_IE_ISDIE_MASK                       0x20u
#define UART_IE_ISDIE_SHIFT                      5
#define UART_IE_WBEIE_MASK                       0x40u
#define UART_IE_WBEIE_SHIFT                      6
/* S3 Bit Fields */
#define UART_S3_TXFF_MASK                        0x1u
#define UART_S3_TXFF_SHIFT                       0
#define UART_S3_PSF_MASK                         0x2u
#define UART_S3_PSF_SHIFT                        1
#define UART_S3_PCTEF_MASK                       0x4u
#define UART_S3_PCTEF_SHIFT                      2
#define UART_S3_PTXF_MASK                        0x8u
#define UART_S3_PTXF_SHIFT                       3
#define UART_S3_PRXF_MASK                        0x10u
#define UART_S3_PRXF_SHIFT                       4
#define UART_S3_ISD_MASK                         0x20u
#define UART_S3_ISD_SHIFT                        5
#define UART_S3_WBEF_MASK                        0x40u
#define UART_S3_WBEF_SHIFT                       6
#define UART_S3_PEF_MASK                         0x80u
#define UART_S3_PEF_SHIFT                        7
/* S4 Bit Fields */
#define UART_S4_FE_MASK                          0x1u
#define UART_S4_FE_SHIFT                         0
#define UART_S4_ILCV_MASK                        0x2u
#define UART_S4_ILCV_SHIFT                       1
#define UART_S4_CDET_MASK                        0xCu
#define UART_S4_CDET_SHIFT                       2
#define UART_S4_CDET(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
#define UART_S4_INITF_MASK                       0x10u
#define UART_S4_INITF_SHIFT                      4
/* RPL Bit Fields */
#define UART_RPL_RPL_MASK                        0xFFu
#define UART_RPL_RPL_SHIFT                       0
#define UART_RPL_RPL(x)                          (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
/* RPREL Bit Fields */
#define UART_RPREL_RPREL_MASK                    0xFFu
#define UART_RPREL_RPREL_SHIFT                   0
#define UART_RPREL_RPREL(x)                      (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
/* CPW Bit Fields */
#define UART_CPW_CPW_MASK                        0xFFu
#define UART_CPW_CPW_SHIFT                       0
#define UART_CPW_CPW(x)                          (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
/* RIDT Bit Fields */
#define UART_RIDT_RIDT_MASK                      0xFFu
#define UART_RIDT_RIDT_SHIFT                     0
#define UART_RIDT_RIDT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
/* TIDT Bit Fields */
#define UART_TIDT_TIDT_MASK                      0xFFu
#define UART_TIDT_TIDT_SHIFT                     0
#define UART_TIDT_TIDT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)

/**
 * @}
 */ /* end of group UART_Register_Masks */


/* UART - Peripheral instance base addresses */
/** Peripheral UART0 base address */
#define UART0_BASE                               (0x40027000u)
/** Peripheral UART0 base pointer */
#define UART0                                    ((UART_Type *)UART0_BASE)
/** Peripheral UART1 base address */
#define UART1_BASE                               (0x40028000u)
/** Peripheral UART1 base pointer */
#define UART1                                    ((UART_Type *)UART1_BASE)
/** Peripheral UART2 base address */
#define UART2_BASE                               (0x40029000u)
/** Peripheral UART2 base pointer */
#define UART2                                    ((UART_Type *)UART2_BASE)
/** Peripheral UART3 base address */
#define UART3_BASE                               (0x4002A000u)
/** Peripheral UART3 base pointer */
#define UART3                                    ((UART_Type *)UART3_BASE)
/** Peripheral UART4 base address */
#define UART4_BASE                               (0x400A9000u)
/** Peripheral UART4 base pointer */
#define UART4                                    ((UART_Type *)UART4_BASE)
/** Peripheral UART5 base address */
#define UART5_BASE                               (0x400AA000u)
/** Peripheral UART5 base pointer */
#define UART5                                    ((UART_Type *)UART5_BASE)
/** Array initializer of UART peripheral base pointers */
#define UART_BASES                               { UART0, UART1, UART2, UART3, UART4, UART5 }

/**
 * @}
 */ /* end of group UART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USB Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
 * @{
 */

/** USB - Register Layout Typedef */
typedef struct {
  __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
  __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
  __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
  __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
  __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
  __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
       uint8_t RESERVED_0[104];
  __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
  __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
  __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
  __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
  __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
       uint8_t RESERVED_1[108];
  __I  uint8_t CAPLENGTH;                          /**< Capability Register Length, offset: 0x100 */
       uint8_t RESERVED_2[1];
  __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
       uint8_t RESERVED_3[20];
  __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
       uint8_t RESERVED_4[2];
  __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
       uint8_t RESERVED_5[24];
  __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
  __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
  __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
  __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
       uint8_t RESERVED_6[4];
  union {                                          /* offset: 0x154 */
    __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
    __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
  };
  union {                                          /* offset: 0x158 */
    __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
    __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
  };
       uint8_t RESERVED_7[4];
  __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
  __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
       uint8_t RESERVED_8[4];
  __IO uint32_t IC_USB;                            /**< IC_USB enable and voltage negotiation, offset: 0x16C */
       uint8_t RESERVED_9[8];
  __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
  __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
       uint8_t RESERVED_10[4];
  __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
       uint8_t RESERVED_11[28];
  __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
  __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
  __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
  __IO uint32_t ENDPTPRIME;                        /**< Endpoint Initialization, offset: 0x1B0 */
  __IO uint32_t ENDPTFLUSH;                        /**< Endpoint De-Initialize, offset: 0x1B4 */
  __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
  __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
  __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
  __IO uint32_t ENDPTCTRL[5];                      /**< Endpoint Controln, array offset: 0x1C4, array step: 0x4 */
} USB_Type;

/* ----------------------------------------------------------------------------
   -- USB Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USB_Register_Masks USB Register Masks
 * @{
 */

/* ID Bit Fields */
#define USB_ID_ID_MASK                           0x3Fu
#define USB_ID_ID_SHIFT                          0
#define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x))<<USB_ID_ID_SHIFT))&USB_ID_ID_MASK)
#define USB_ID_NID_MASK                          0x3F00u
#define USB_ID_NID_SHIFT                         8
#define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x))<<USB_ID_NID_SHIFT))&USB_ID_NID_MASK)
#define USB_ID_REVISION_MASK                     0xFF0000u
#define USB_ID_REVISION_SHIFT                    16
#define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x))<<USB_ID_REVISION_SHIFT))&USB_ID_REVISION_MASK)
/* HWGENERAL Bit Fields */
#define USB_HWGENERAL_PHYW_MASK                  0x30u
#define USB_HWGENERAL_PHYW_SHIFT                 4
#define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_PHYW_SHIFT))&USB_HWGENERAL_PHYW_MASK)
#define USB_HWGENERAL_PHYM_MASK                  0x1C0u
#define USB_HWGENERAL_PHYM_SHIFT                 6
#define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_PHYM_SHIFT))&USB_HWGENERAL_PHYM_MASK)
#define USB_HWGENERAL_SM_MASK                    0x600u
#define USB_HWGENERAL_SM_SHIFT                   9
#define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_SM_SHIFT))&USB_HWGENERAL_SM_MASK)
/* HWHOST Bit Fields */
#define USB_HWHOST_HC_MASK                       0x1u
#define USB_HWHOST_HC_SHIFT                      0
#define USB_HWHOST_NPORT_MASK                    0xEu
#define USB_HWHOST_NPORT_SHIFT                   1
#define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x))<<USB_HWHOST_NPORT_SHIFT))&USB_HWHOST_NPORT_MASK)
/* HWDEVICE Bit Fields */
#define USB_HWDEVICE_DC_MASK                     0x1u
#define USB_HWDEVICE_DC_SHIFT                    0
#define USB_HWDEVICE_DEVEP_MASK                  0x3Eu
#define USB_HWDEVICE_DEVEP_SHIFT                 1
#define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HWDEVICE_DEVEP_SHIFT))&USB_HWDEVICE_DEVEP_MASK)
/* HWTXBUF Bit Fields */
#define USB_HWTXBUF_TXBURST_MASK                 0xFFu
#define USB_HWTXBUF_TXBURST_SHIFT                0
#define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HWTXBUF_TXBURST_SHIFT))&USB_HWTXBUF_TXBURST_MASK)
#define USB_HWTXBUF_TXCHANADD_MASK               0xFF0000u
#define USB_HWTXBUF_TXCHANADD_SHIFT              16
#define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x))<<USB_HWTXBUF_TXCHANADD_SHIFT))&USB_HWTXBUF_TXCHANADD_MASK)
/* HWRXBUF Bit Fields */
#define USB_HWRXBUF_RXBURST_MASK                 0xFFu
#define USB_HWRXBUF_RXBURST_SHIFT                0
#define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HWRXBUF_RXBURST_SHIFT))&USB_HWRXBUF_RXBURST_MASK)
#define USB_HWRXBUF_RXADD_MASK                   0xFF00u
#define USB_HWRXBUF_RXADD_SHIFT                  8
#define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x))<<USB_HWRXBUF_RXADD_SHIFT))&USB_HWRXBUF_RXADD_MASK)
/* GPTIMER0LD Bit Fields */
#define USB_GPTIMER0LD_GPTLD_MASK                0xFFFFFFu
#define USB_GPTIMER0LD_GPTLD_SHIFT               0
#define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER0LD_GPTLD_SHIFT))&USB_GPTIMER0LD_GPTLD_MASK)
/* GPTIMER0CTRL Bit Fields */
#define USB_GPTIMER0CTRL_GPTCNT_MASK             0xFFFFFFu
#define USB_GPTIMER0CTRL_GPTCNT_SHIFT            0
#define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER0CTRL_GPTCNT_SHIFT))&USB_GPTIMER0CTRL_GPTCNT_MASK)
#define USB_GPTIMER0CTRL_GPTMODE_MASK            0x1000000u
#define USB_GPTIMER0CTRL_GPTMODE_SHIFT           24
#define USB_GPTIMER0CTRL_GPTRST_MASK             0x40000000u
#define USB_GPTIMER0CTRL_GPTRST_SHIFT            30
#define USB_GPTIMER0CTRL_GPTRUN_MASK             0x80000000u
#define USB_GPTIMER0CTRL_GPTRUN_SHIFT            31
/* GPTIMER1LD Bit Fields */
#define USB_GPTIMER1LD_GPTLD_MASK                0xFFFFFFu
#define USB_GPTIMER1LD_GPTLD_SHIFT               0
#define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER1LD_GPTLD_SHIFT))&USB_GPTIMER1LD_GPTLD_MASK)
/* GPTIMER1CTRL Bit Fields */
#define USB_GPTIMER1CTRL_GPTCNT_MASK             0xFFFFFFu
#define USB_GPTIMER1CTRL_GPTCNT_SHIFT            0
#define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER1CTRL_GPTCNT_SHIFT))&USB_GPTIMER1CTRL_GPTCNT_MASK)
#define USB_GPTIMER1CTRL_GPTMODE_MASK            0x1000000u
#define USB_GPTIMER1CTRL_GPTMODE_SHIFT           24
#define USB_GPTIMER1CTRL_GPTRST_MASK             0x40000000u
#define USB_GPTIMER1CTRL_GPTRST_SHIFT            30
#define USB_GPTIMER1CTRL_GPTRUN_MASK             0x80000000u
#define USB_GPTIMER1CTRL_GPTRUN_SHIFT            31
/* SBUSCFG Bit Fields */
#define USB_SBUSCFG_AHBBRST_MASK                 0x7u
#define USB_SBUSCFG_AHBBRST_SHIFT                0
#define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x))<<USB_SBUSCFG_AHBBRST_SHIFT))&USB_SBUSCFG_AHBBRST_MASK)
/* CAPLENGTH Bit Fields */
#define USB_CAPLENGTH_CAPLENGTH_MASK             0xFFu
#define USB_CAPLENGTH_CAPLENGTH_SHIFT            0
#define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x))<<USB_CAPLENGTH_CAPLENGTH_SHIFT))&USB_CAPLENGTH_CAPLENGTH_MASK)
/* HCIVERSION Bit Fields */
#define USB_HCIVERSION_HCIVERSION_MASK           0xFFFFu
#define USB_HCIVERSION_HCIVERSION_SHIFT          0
#define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x))<<USB_HCIVERSION_HCIVERSION_SHIFT))&USB_HCIVERSION_HCIVERSION_MASK)
/* HCSPARAMS Bit Fields */
#define USB_HCSPARAMS_N_PORTS_MASK               0xFu
#define USB_HCSPARAMS_N_PORTS_SHIFT              0
#define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PORTS_SHIFT))&USB_HCSPARAMS_N_PORTS_MASK)
#define USB_HCSPARAMS_PPC_MASK                   0x10u
#define USB_HCSPARAMS_PPC_SHIFT                  4
#define USB_HCSPARAMS_N_PCC_MASK                 0xF00u
#define USB_HCSPARAMS_N_PCC_SHIFT                8
#define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PCC_SHIFT))&USB_HCSPARAMS_N_PCC_MASK)
#define USB_HCSPARAMS_N_CC_MASK                  0xF000u
#define USB_HCSPARAMS_N_CC_SHIFT                 12
#define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_CC_SHIFT))&USB_HCSPARAMS_N_CC_MASK)
#define USB_HCSPARAMS_PI_MASK                    0x10000u
#define USB_HCSPARAMS_PI_SHIFT                   16
#define USB_HCSPARAMS_N_PTT_MASK                 0xF00000u
#define USB_HCSPARAMS_N_PTT_SHIFT                20
#define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PTT_SHIFT))&USB_HCSPARAMS_N_PTT_MASK)
#define USB_HCSPARAMS_N_TT_MASK                  0xF000000u
#define USB_HCSPARAMS_N_TT_SHIFT                 24
#define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_TT_SHIFT))&USB_HCSPARAMS_N_TT_MASK)
/* HCCPARAMS Bit Fields */
#define USB_HCCPARAMS_ADC_MASK                   0x1u
#define USB_HCCPARAMS_ADC_SHIFT                  0
#define USB_HCCPARAMS_PFL_MASK                   0x2u
#define USB_HCCPARAMS_PFL_SHIFT                  1
#define USB_HCCPARAMS_ASP_MASK                   0x4u
#define USB_HCCPARAMS_ASP_SHIFT                  2
#define USB_HCCPARAMS_IST_MASK                   0xF0u
#define USB_HCCPARAMS_IST_SHIFT                  4
#define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x))<<USB_HCCPARAMS_IST_SHIFT))&USB_HCCPARAMS_IST_MASK)
#define USB_HCCPARAMS_EECP_MASK                  0xFF00u
#define USB_HCCPARAMS_EECP_SHIFT                 8
#define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x))<<USB_HCCPARAMS_EECP_SHIFT))&USB_HCCPARAMS_EECP_MASK)
/* DCIVERSION Bit Fields */
#define USB_DCIVERSION_DCIVERSION_MASK           0xFFFFu
#define USB_DCIVERSION_DCIVERSION_SHIFT          0
#define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x))<<USB_DCIVERSION_DCIVERSION_SHIFT))&USB_DCIVERSION_DCIVERSION_MASK)
/* DCCPARAMS Bit Fields */
#define USB_DCCPARAMS_DEN_MASK                   0x1Fu
#define USB_DCCPARAMS_DEN_SHIFT                  0
#define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x))<<USB_DCCPARAMS_DEN_SHIFT))&USB_DCCPARAMS_DEN_MASK)
#define USB_DCCPARAMS_DC_MASK                    0x80u
#define USB_DCCPARAMS_DC_SHIFT                   7
#define USB_DCCPARAMS_HC_MASK                    0x100u
#define USB_DCCPARAMS_HC_SHIFT                   8
/* USBCMD Bit Fields */
#define USB_USBCMD_RS_MASK                       0x1u
#define USB_USBCMD_RS_SHIFT                      0
#define USB_USBCMD_RST_MASK                      0x2u
#define USB_USBCMD_RST_SHIFT                     1
#define USB_USBCMD_FS1_MASK                      0xCu
#define USB_USBCMD_FS1_SHIFT                     2
#define USB_USBCMD_FS1(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_FS1_SHIFT))&USB_USBCMD_FS1_MASK)
#define USB_USBCMD_PSE_MASK                      0x10u
#define USB_USBCMD_PSE_SHIFT                     4
#define USB_USBCMD_ASE_MASK                      0x20u
#define USB_USBCMD_ASE_SHIFT                     5
#define USB_USBCMD_IAA_MASK                      0x40u
#define USB_USBCMD_IAA_SHIFT                     6
#define USB_USBCMD_ASP_MASK                      0x300u
#define USB_USBCMD_ASP_SHIFT                     8
#define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_ASP_SHIFT))&USB_USBCMD_ASP_MASK)
#define USB_USBCMD_ASPE_MASK                     0x800u
#define USB_USBCMD_ASPE_SHIFT                    11
#define USB_USBCMD_SUTW_MASK                     0x2000u
#define USB_USBCMD_SUTW_SHIFT                    13
#define USB_USBCMD_ATDTW_MASK                    0x4000u
#define USB_USBCMD_ATDTW_SHIFT                   14
#define USB_USBCMD_FS2_MASK                      0x8000u
#define USB_USBCMD_FS2_SHIFT                     15
#define USB_USBCMD_ITC_MASK                      0xFF0000u
#define USB_USBCMD_ITC_SHIFT                     16
#define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_ITC_SHIFT))&USB_USBCMD_ITC_MASK)
/* USBSTS Bit Fields */
#define USB_USBSTS_UI_MASK                       0x1u
#define USB_USBSTS_UI_SHIFT                      0
#define USB_USBSTS_UEI_MASK                      0x2u
#define USB_USBSTS_UEI_SHIFT                     1
#define USB_USBSTS_PCI_MASK                      0x4u
#define USB_USBSTS_PCI_SHIFT                     2
#define USB_USBSTS_FRI_MASK                      0x8u
#define USB_USBSTS_FRI_SHIFT                     3
#define USB_USBSTS_SEI_MASK                      0x10u
#define USB_USBSTS_SEI_SHIFT                     4
#define USB_USBSTS_AAI_MASK                      0x20u
#define USB_USBSTS_AAI_SHIFT                     5
#define USB_USBSTS_URI_MASK                      0x40u
#define USB_USBSTS_URI_SHIFT                     6
#define USB_USBSTS_SRI_MASK                      0x80u
#define USB_USBSTS_SRI_SHIFT                     7
#define USB_USBSTS_SLI_MASK                      0x100u
#define USB_USBSTS_SLI_SHIFT                     8
#define USB_USBSTS_ULPII_MASK                    0x400u
#define USB_USBSTS_ULPII_SHIFT                   10
#define USB_USBSTS_HCH_MASK                      0x1000u
#define USB_USBSTS_HCH_SHIFT                     12
#define USB_USBSTS_RCL_MASK                      0x2000u
#define USB_USBSTS_RCL_SHIFT                     13
#define USB_USBSTS_PS_MASK                       0x4000u
#define USB_USBSTS_PS_SHIFT                      14
#define USB_USBSTS_AS_MASK                       0x8000u
#define USB_USBSTS_AS_SHIFT                      15
#define USB_USBSTS_NAKI_MASK                     0x10000u
#define USB_USBSTS_NAKI_SHIFT                    16
#define USB_USBSTS_TI0_MASK                      0x1000000u
#define USB_USBSTS_TI0_SHIFT                     24
#define USB_USBSTS_TI1_MASK                      0x2000000u
#define USB_USBSTS_TI1_SHIFT                     25
/* USBINTR Bit Fields */
#define USB_USBINTR_UE_MASK                      0x1u
#define USB_USBINTR_UE_SHIFT                     0
#define USB_USBINTR_UEE_MASK                     0x2u
#define USB_USBINTR_UEE_SHIFT                    1
#define USB_USBINTR_PCE_MASK                     0x4u
#define USB_USBINTR_PCE_SHIFT                    2
#define USB_USBINTR_FRE_MASK                     0x8u
#define USB_USBINTR_FRE_SHIFT                    3
#define USB_USBINTR_SEE_MASK                     0x10u
#define USB_USBINTR_SEE_SHIFT                    4
#define USB_USBINTR_AAE_MASK                     0x20u
#define USB_USBINTR_AAE_SHIFT                    5
#define USB_USBINTR_URE_MASK                     0x40u
#define USB_USBINTR_URE_SHIFT                    6
#define USB_USBINTR_SRE_MASK                     0x80u
#define USB_USBINTR_SRE_SHIFT                    7
#define USB_USBINTR_SLE_MASK                     0x100u
#define USB_USBINTR_SLE_SHIFT                    8
#define USB_USBINTR_ULPIE_MASK                   0x400u
#define USB_USBINTR_ULPIE_SHIFT                  10
#define USB_USBINTR_NAKE_MASK                    0x10000u
#define USB_USBINTR_NAKE_SHIFT                   16
#define USB_USBINTR_UAIE_MASK                    0x40000u
#define USB_USBINTR_UAIE_SHIFT                   18
#define USB_USBINTR_UPIE_MASK                    0x80000u
#define USB_USBINTR_UPIE_SHIFT                   19
#define USB_USBINTR_TIE0_MASK                    0x1000000u
#define USB_USBINTR_TIE0_SHIFT                   24
#define USB_USBINTR_TIE1_MASK                    0x2000000u
#define USB_USBINTR_TIE1_SHIFT                   25
/* FRINDEX Bit Fields */
#define USB_FRINDEX_FRINDEX_MASK                 0x3FFFu
#define USB_FRINDEX_FRINDEX_SHIFT                0
#define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x))<<USB_FRINDEX_FRINDEX_SHIFT))&USB_FRINDEX_FRINDEX_MASK)
/* DEVICEADDR Bit Fields */
#define USB_DEVICEADDR_USBADRA_MASK              0x1000000u
#define USB_DEVICEADDR_USBADRA_SHIFT             24
#define USB_DEVICEADDR_USBADR_MASK               0xFE000000u
#define USB_DEVICEADDR_USBADR_SHIFT              25
#define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x))<<USB_DEVICEADDR_USBADR_SHIFT))&USB_DEVICEADDR_USBADR_MASK)
/* PERIODICLISTBASE Bit Fields */
#define USB_PERIODICLISTBASE_BASEADR_MASK        0xFFFFF000u
#define USB_PERIODICLISTBASE_BASEADR_SHIFT       12
#define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x))<<USB_PERIODICLISTBASE_BASEADR_SHIFT))&USB_PERIODICLISTBASE_BASEADR_MASK)
/* ASYNCLISTADDR Bit Fields */
#define USB_ASYNCLISTADDR_ASYBASE_MASK           0xFFFFFFE0u
#define USB_ASYNCLISTADDR_ASYBASE_SHIFT          5
#define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x))<<USB_ASYNCLISTADDR_ASYBASE_SHIFT))&USB_ASYNCLISTADDR_ASYBASE_MASK)
/* ENDPTLISTADDR Bit Fields */
#define USB_ENDPTLISTADDR_EPBASE_MASK            0xFFFFF800u
#define USB_ENDPTLISTADDR_EPBASE_SHIFT           11
#define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x))<<USB_ENDPTLISTADDR_EPBASE_SHIFT))&USB_ENDPTLISTADDR_EPBASE_MASK)
/* BURSTSIZE Bit Fields */
#define USB_BURSTSIZE_RXPBURST_MASK              0xFFu
#define USB_BURSTSIZE_RXPBURST_SHIFT             0
#define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x))<<USB_BURSTSIZE_RXPBURST_SHIFT))&USB_BURSTSIZE_RXPBURST_MASK)
#define USB_BURSTSIZE_TXPBURST_MASK              0x1FF00u
#define USB_BURSTSIZE_TXPBURST_SHIFT             8
#define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x))<<USB_BURSTSIZE_TXPBURST_SHIFT))&USB_BURSTSIZE_TXPBURST_MASK)
/* TXFILLTUNING Bit Fields */
#define USB_TXFILLTUNING_TXSCHOH_MASK            0xFFu
#define USB_TXFILLTUNING_TXSCHOH_SHIFT           0
#define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXSCHOH_SHIFT))&USB_TXFILLTUNING_TXSCHOH_MASK)
#define USB_TXFILLTUNING_TXSCHHEALTH_MASK        0x1F00u
#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       8
#define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USB_TXFILLTUNING_TXSCHHEALTH_MASK)
#define USB_TXFILLTUNING_TXFIFOTHRES_MASK        0x3F0000u
#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       16
#define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USB_TXFILLTUNING_TXFIFOTHRES_MASK)
/* IC_USB Bit Fields */
#define USB_IC_USB_IC_VDD1_MASK                  0x7u
#define USB_IC_USB_IC_VDD1_SHIFT                 0
#define USB_IC_USB_IC_VDD1(x)                    (((uint32_t)(((uint32_t)(x))<<USB_IC_USB_IC_VDD1_SHIFT))&USB_IC_USB_IC_VDD1_MASK)
#define USB_IC_USB_IC1_MASK                      0x8u
#define USB_IC_USB_IC1_SHIFT                     3
/* ENDPTNAK Bit Fields */
#define USB_ENDPTNAK_EPRN_MASK                   0x3Fu
#define USB_ENDPTNAK_EPRN_SHIFT                  0
#define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAK_EPRN_SHIFT))&USB_ENDPTNAK_EPRN_MASK)
#define USB_ENDPTNAK_EPTN_MASK                   0x3F0000u
#define USB_ENDPTNAK_EPTN_SHIFT                  16
#define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAK_EPTN_SHIFT))&USB_ENDPTNAK_EPTN_MASK)
/* ENDPTNAKEN Bit Fields */
#define USB_ENDPTNAKEN_EPRNE_MASK                0x3Fu
#define USB_ENDPTNAKEN_EPRNE_SHIFT               0
#define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAKEN_EPRNE_SHIFT))&USB_ENDPTNAKEN_EPRNE_MASK)
#define USB_ENDPTNAKEN_EPTNE_MASK                0x3F0000u
#define USB_ENDPTNAKEN_EPTNE_SHIFT               16
#define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAKEN_EPTNE_SHIFT))&USB_ENDPTNAKEN_EPTNE_MASK)
/* PORTSC1 Bit Fields */
#define USB_PORTSC1_CCS_MASK                     0x1u
#define USB_PORTSC1_CCS_SHIFT                    0
#define USB_PORTSC1_CSC_MASK                     0x2u
#define USB_PORTSC1_CSC_SHIFT                    1
#define USB_PORTSC1_PE_MASK                      0x4u
#define USB_PORTSC1_PE_SHIFT                     2
#define USB_PORTSC1_PEC_MASK                     0x8u
#define USB_PORTSC1_PEC_SHIFT                    3
#define USB_PORTSC1_OCA_MASK                     0x10u
#define USB_PORTSC1_OCA_SHIFT                    4
#define USB_PORTSC1_OCC_MASK                     0x20u
#define USB_PORTSC1_OCC_SHIFT                    5
#define USB_PORTSC1_FPR_MASK                     0x40u
#define USB_PORTSC1_FPR_SHIFT                    6
#define USB_PORTSC1_SUSP_MASK                    0x80u
#define USB_PORTSC1_SUSP_SHIFT                   7
#define USB_PORTSC1_PR_MASK                      0x100u
#define USB_PORTSC1_PR_SHIFT                     8
#define USB_PORTSC1_HSP_MASK                     0x200u
#define USB_PORTSC1_HSP_SHIFT                    9
#define USB_PORTSC1_LS_MASK                      0xC00u
#define USB_PORTSC1_LS_SHIFT                     10
#define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_LS_SHIFT))&USB_PORTSC1_LS_MASK)
#define USB_PORTSC1_PP_MASK                      0x1000u
#define USB_PORTSC1_PP_SHIFT                     12
#define USB_PORTSC1_PO_MASK                      0x2000u
#define USB_PORTSC1_PO_SHIFT                     13
#define USB_PORTSC1_PIC_MASK                     0xC000u
#define USB_PORTSC1_PIC_SHIFT                    14
#define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PIC_SHIFT))&USB_PORTSC1_PIC_MASK)
#define USB_PORTSC1_PTC_MASK                     0xF0000u
#define USB_PORTSC1_PTC_SHIFT                    16
#define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PTC_SHIFT))&USB_PORTSC1_PTC_MASK)
#define USB_PORTSC1_WKCN_MASK                    0x100000u
#define USB_PORTSC1_WKCN_SHIFT                   20
#define USB_PORTSC1_WKDC_MASK                    0x200000u
#define USB_PORTSC1_WKDC_SHIFT                   21
#define USB_PORTSC1_WKOC_MASK                    0x400000u
#define USB_PORTSC1_WKOC_SHIFT                   22
#define USB_PORTSC1_PHCD_MASK                    0x800000u
#define USB_PORTSC1_PHCD_SHIFT                   23
#define USB_PORTSC1_PFSC_MASK                    0x1000000u
#define USB_PORTSC1_PFSC_SHIFT                   24
#define USB_PORTSC1_PTS1_MASK                    0x2000000u
#define USB_PORTSC1_PTS1_SHIFT                   25
#define USB_PORTSC1_PSPD_MASK                    0xC000000u
#define USB_PORTSC1_PSPD_SHIFT                   26
#define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PSPD_SHIFT))&USB_PORTSC1_PSPD_MASK)
#define USB_PORTSC1_PTW_MASK                     0x10000000u
#define USB_PORTSC1_PTW_SHIFT                    28
#define USB_PORTSC1_STS_MASK                     0x20000000u
#define USB_PORTSC1_STS_SHIFT                    29
#define USB_PORTSC1_PTS2_MASK                    0xC0000000u
#define USB_PORTSC1_PTS2_SHIFT                   30
#define USB_PORTSC1_PTS2(x)                      (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PTS2_SHIFT))&USB_PORTSC1_PTS2_MASK)
/* OTGSC Bit Fields */
#define USB_OTGSC_VD_MASK                        0x1u
#define USB_OTGSC_VD_SHIFT                       0
#define USB_OTGSC_OT_MASK                        0x8u
#define USB_OTGSC_OT_SHIFT                       3
#define USB_OTGSC_IDPU_MASK                      0x20u
#define USB_OTGSC_IDPU_SHIFT                     5
#define USB_OTGSC_ID_MASK                        0x100u
#define USB_OTGSC_ID_SHIFT                       8
#define USB_OTGSC_AVV_MASK                       0x200u
#define USB_OTGSC_AVV_SHIFT                      9
#define USB_OTGSC_ASV_MASK                       0x400u
#define USB_OTGSC_ASV_SHIFT                      10
#define USB_OTGSC_BSV_MASK                       0x800u
#define USB_OTGSC_BSV_SHIFT                      11
#define USB_OTGSC_BSE_MASK                       0x1000u
#define USB_OTGSC_BSE_SHIFT                      12
#define USB_OTGSC_1msT_MASK                      0x2000u
#define USB_OTGSC_1msT_SHIFT                     13
#define USB_OTGSC_DPS_MASK                       0x4000u
#define USB_OTGSC_DPS_SHIFT                      14
#define USB_OTGSC_IDIS_MASK                      0x10000u
#define USB_OTGSC_IDIS_SHIFT                     16
#define USB_OTGSC_AVVIS_MASK                     0x20000u
#define USB_OTGSC_AVVIS_SHIFT                    17
#define USB_OTGSC_ASVIS_MASK                     0x40000u
#define USB_OTGSC_ASVIS_SHIFT                    18
#define USB_OTGSC_BSVIS_MASK                     0x80000u
#define USB_OTGSC_BSVIS_SHIFT                    19
#define USB_OTGSC_BSEIS_MASK                     0x100000u
#define USB_OTGSC_BSEIS_SHIFT                    20
#define USB_OTGSC_1MSS_MASK                      0x200000u
#define USB_OTGSC_1MSS_SHIFT                     21
#define USB_OTGSC_DPIS_MASK                      0x400000u
#define USB_OTGSC_DPIS_SHIFT                     22
#define USB_OTGSC_IDIE_MASK                      0x1000000u
#define USB_OTGSC_IDIE_SHIFT                     24
#define USB_OTGSC_AVVIE_MASK                     0x2000000u
#define USB_OTGSC_AVVIE_SHIFT                    25
#define USB_OTGSC_ASVIE_MASK                     0x4000000u
#define USB_OTGSC_ASVIE_SHIFT                    26
#define USB_OTGSC_BSVIE_MASK                     0x8000000u
#define USB_OTGSC_BSVIE_SHIFT                    27
#define USB_OTGSC_BSEIE_MASK                     0x10000000u
#define USB_OTGSC_BSEIE_SHIFT                    28
#define USB_OTGSC_1MSSE_MASK                     0x20000000u
#define USB_OTGSC_1MSSE_SHIFT                    29
#define USB_OTGSC_DPIE_MASK                      0x40000000u
#define USB_OTGSC_DPIE_SHIFT                     30
/* USBMODE Bit Fields */
#define USB_USBMODE_CM_MASK                      0x3u
#define USB_USBMODE_CM_SHIFT                     0
#define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x))<<USB_USBMODE_CM_SHIFT))&USB_USBMODE_CM_MASK)
#define USB_USBMODE_ES_MASK                      0x4u
#define USB_USBMODE_ES_SHIFT                     2
#define USB_USBMODE_SLOM_MASK                    0x8u
#define USB_USBMODE_SLOM_SHIFT                   3
#define USB_USBMODE_SDIS_MASK                    0x10u
#define USB_USBMODE_SDIS_SHIFT                   4
/* ENDPTSETUPSTAT Bit Fields */
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   0xFFFFu
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  0
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
/* ENDPTPRIME Bit Fields */
#define USB_ENDPTPRIME_PERB_MASK                 0x3Fu
#define USB_ENDPTPRIME_PERB_SHIFT                0
#define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTPRIME_PERB_SHIFT))&USB_ENDPTPRIME_PERB_MASK)
#define USB_ENDPTPRIME_PETB_MASK                 0x3F0000u
#define USB_ENDPTPRIME_PETB_SHIFT                16
#define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTPRIME_PETB_SHIFT))&USB_ENDPTPRIME_PETB_MASK)
/* ENDPTFLUSH Bit Fields */
#define USB_ENDPTFLUSH_FERB_MASK                 0x3Fu
#define USB_ENDPTFLUSH_FERB_SHIFT                0
#define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTFLUSH_FERB_SHIFT))&USB_ENDPTFLUSH_FERB_MASK)
#define USB_ENDPTFLUSH_FETB_MASK                 0x3F0000u
#define USB_ENDPTFLUSH_FETB_SHIFT                16
#define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x))<<USB_ENDPTFLUSH_FETB_SHIFT))&USB_ENDPTFLUSH_FETB_MASK)
/* ENDPTSTAT Bit Fields */
#define USB_ENDPTSTAT_ERBR_MASK                  0x3Fu
#define USB_ENDPTSTAT_ERBR_SHIFT                 0
#define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSTAT_ERBR_SHIFT))&USB_ENDPTSTAT_ERBR_MASK)
#define USB_ENDPTSTAT_ETBR_MASK                  0x3F0000u
#define USB_ENDPTSTAT_ETBR_SHIFT                 16
#define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSTAT_ETBR_SHIFT))&USB_ENDPTSTAT_ETBR_MASK)
/* ENDPTCOMPLETE Bit Fields */
#define USB_ENDPTCOMPLETE_ERCE_MASK              0x3Fu
#define USB_ENDPTCOMPLETE_ERCE_SHIFT             0
#define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCOMPLETE_ERCE_SHIFT))&USB_ENDPTCOMPLETE_ERCE_MASK)
#define USB_ENDPTCOMPLETE_ETCE_MASK              0x3F0000u
#define USB_ENDPTCOMPLETE_ETCE_SHIFT             16
#define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCOMPLETE_ETCE_SHIFT))&USB_ENDPTCOMPLETE_ETCE_MASK)
/* ENDPTCTRL0 Bit Fields */
#define USB_ENDPTCTRL0_RXS_MASK                  0x1u
#define USB_ENDPTCTRL0_RXS_SHIFT                 0
#define USB_ENDPTCTRL0_RXT_MASK                  0xCu
#define USB_ENDPTCTRL0_RXT_SHIFT                 2
#define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL0_RXT_SHIFT))&USB_ENDPTCTRL0_RXT_MASK)
#define USB_ENDPTCTRL0_RXE_MASK                  0x80u
#define USB_ENDPTCTRL0_RXE_SHIFT                 7
#define USB_ENDPTCTRL0_TXS_MASK                  0x10000u
#define USB_ENDPTCTRL0_TXS_SHIFT                 16
#define USB_ENDPTCTRL0_TXT_MASK                  0xC0000u
#define USB_ENDPTCTRL0_TXT_SHIFT                 18
#define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL0_TXT_SHIFT))&USB_ENDPTCTRL0_TXT_MASK)
#define USB_ENDPTCTRL0_TXE_MASK                  0x800000u
#define USB_ENDPTCTRL0_TXE_SHIFT                 23
/* ENDPTCTRL Bit Fields */
#define USB_ENDPTCTRL_RXS_MASK                   0x1u
#define USB_ENDPTCTRL_RXS_SHIFT                  0
#define USB_ENDPTCTRL_RXD_MASK                   0x2u
#define USB_ENDPTCTRL_RXD_SHIFT                  1
#define USB_ENDPTCTRL_RXT_MASK                   0xCu
#define USB_ENDPTCTRL_RXT_SHIFT                  2
#define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL_RXT_SHIFT))&USB_ENDPTCTRL_RXT_MASK)
#define USB_ENDPTCTRL_RXI_MASK                   0x20u
#define USB_ENDPTCTRL_RXI_SHIFT                  5
#define USB_ENDPTCTRL_RXR_MASK                   0x40u
#define USB_ENDPTCTRL_RXR_SHIFT                  6
#define USB_ENDPTCTRL_RXE_MASK                   0x80u
#define USB_ENDPTCTRL_RXE_SHIFT                  7
#define USB_ENDPTCTRL_TXS_MASK                   0x10000u
#define USB_ENDPTCTRL_TXS_SHIFT                  16
#define USB_ENDPTCTRL_TXD_MASK                   0x20000u
#define USB_ENDPTCTRL_TXD_SHIFT                  17
#define USB_ENDPTCTRL_TXT_MASK                   0xC0000u
#define USB_ENDPTCTRL_TXT_SHIFT                  18
#define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL_TXT_SHIFT))&USB_ENDPTCTRL_TXT_MASK)
#define USB_ENDPTCTRL_TXI_MASK                   0x200000u
#define USB_ENDPTCTRL_TXI_SHIFT                  21
#define USB_ENDPTCTRL_TXR_MASK                   0x400000u
#define USB_ENDPTCTRL_TXR_SHIFT                  22
#define USB_ENDPTCTRL_TXE_MASK                   0x800000u
#define USB_ENDPTCTRL_TXE_SHIFT                  23

/**
 * @}
 */ /* end of group USB_Register_Masks */


/* USB - Peripheral instance base addresses */
/** Peripheral USB0 base address */
#define USB0_BASE                                (0x40034000u)
/** Peripheral USB0 base pointer */
#define USB0                                     ((USB_Type *)USB0_BASE)
/** Peripheral USB1 base address */
#define USB1_BASE                                (0x400B4000u)
/** Peripheral USB1 base pointer */
#define USB1                                     ((USB_Type *)USB1_BASE)
/** Array initializer of USB peripheral base pointers */
#define USB_BASES                                { USB0, USB1 }

/**
 * @}
 */ /* end of group USB_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USBC_Peripheral_Access_Layer USBC Peripheral Access Layer
 * @{
 */

/** USBC - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __IO uint32_t CTRL;                              /**< USB OTG Control Register, offset: 0x800 */
       uint8_t RESERVED_1[20];
  __IO uint32_t PHY;                               /**< UTMI PHY Control Register, offset: 0x818 */
} USBC_Type;

/* ----------------------------------------------------------------------------
   -- USBC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USBC_Register_Masks USBC Register Masks
 * @{
 */

/* CTRL Bit Fields */
#define USBC_CTRL_OVER_CUR_DIS_MASK              0x80u
#define USBC_CTRL_OVER_CUR_DIS_SHIFT             7
#define USBC_CTRL_OVER_CUR_POL_MASK              0x100u
#define USBC_CTRL_OVER_CUR_POL_SHIFT             8
#define USBC_CTRL_PM_MASK                        0x200u
#define USBC_CTRL_PM_SHIFT                       9
#define USBC_CTRL_WIE_MASK                       0x400u
#define USBC_CTRL_WIE_SHIFT                      10
#define USBC_CTRL_RESET_MASK                     0x800u
#define USBC_CTRL_RESET_SHIFT                    11
#define USBC_CTRL_SUSPENDM_MASK                  0x1000u
#define USBC_CTRL_SUSPENDM_SHIFT                 12
#define USBC_CTRL_UTMI_ON_CLOCK_MASK             0x2000u
#define USBC_CTRL_UTMI_ON_CLOCK_SHIFT            13
#define USBC_CTRL_WKUP_SW_EN_MASK                0x4000u
#define USBC_CTRL_WKUP_SW_EN_SHIFT               14
#define USBC_CTRL_WKUP_SW_MASK                   0x8000u
#define USBC_CTRL_WKUP_SW_SHIFT                  15
#define USBC_CTRL_WKUP_VBUS_EN_MASK              0x20000u
#define USBC_CTRL_WKUP_VBUS_EN_SHIFT             17
#define USBC_CTRL_VBUS_CH_STAT_MASK              0x1000000u
#define USBC_CTRL_VBUS_CH_STAT_SHIFT             24
#define USBC_CTRL_VBUS_CH_INT_MASK_MASK          0x2000000u
#define USBC_CTRL_VBUS_CH_INT_MASK_SHIFT         25
#define USBC_CTRL_WIR_MASK                       0x80000000u
#define USBC_CTRL_WIR_SHIFT                      31
/* PHY Bit Fields */
#define USBC_PHY_CHRGDET_INT_FLG_MASK            0x1u
#define USBC_PHY_CHRGDET_INT_FLG_SHIFT           0
#define USBC_PHY_CHRGDET_INT_EN_MASK             0x2u
#define USBC_PHY_CHRGDET_INT_EN_SHIFT            1
#define USBC_PHY_CHRGDET_MASK                    0x4u
#define USBC_PHY_CHRGDET_SHIFT                   2
#define USBC_PHY_UTMI_CLK_VLD_MASK               0x80000000u
#define USBC_PHY_UTMI_CLK_VLD_SHIFT              31

/**
 * @}
 */ /* end of group USBC_Register_Masks */


/* USBC - Peripheral instance base addresses */
/** Peripheral USBC0 base address */
#define USBC0_BASE                               (0x40035000u)
/** Peripheral USBC0 base pointer */
#define USBC0                                    ((USBC_Type *)USBC0_BASE)
/** Peripheral USBC1 base address */
#define USBC1_BASE                               (0x400B5000u)
/** Peripheral USBC1 base pointer */
#define USBC1                                    ((USBC_Type *)USBC1_BASE)
/** Array initializer of USBC peripheral base pointers */
#define USBC_BASES                               { USBC0, USBC1 }

/**
 * @}
 */ /* end of group USBC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBPHY Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
 * @{
 */

/** USBPHY - Register Layout Typedef */
typedef struct {
  __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
  __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
  __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
  __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
  __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
       uint8_t RESERVED_0[12];
  __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
  __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
  __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
  __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
  __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
  __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
  __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
  __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
  __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
       uint8_t RESERVED_1[12];
  __IO uint32_t DEBUG;                             /**< USB PHY Debug Register, offset: 0x50 */
  __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
  __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
  __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
  __IO uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
       uint8_t RESERVED_2[12];
  __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
  __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
  __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
  __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
  __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
       uint8_t RESERVED_3[12];
  __IO uint32_t IP;                                /**< USB PHY IP Block Register, offset: 0x90 */
  __IO uint32_t IP_SET;                            /**< USB PHY IP Block Register, offset: 0x94 */
  __IO uint32_t IP_CLR;                            /**< USB PHY IP Block Register, offset: 0x98 */
  __IO uint32_t IP_TOG;                            /**< USB PHY IP Block Register, offset: 0x9C */
} USBPHY_Type;

/* ----------------------------------------------------------------------------
   -- USBPHY Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
 * @{
 */

/* PWD Bit Fields */
#define USBPHY_PWD_RSVD0_MASK                    0x3FFu
#define USBPHY_PWD_RSVD0_SHIFT                   0
#define USBPHY_PWD_RSVD0(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD0_SHIFT))&USBPHY_PWD_RSVD0_MASK)
#define USBPHY_PWD_TXPWDFS_MASK                  0x400u
#define USBPHY_PWD_TXPWDFS_SHIFT                 10
#define USBPHY_PWD_TXPWDIBIAS_MASK               0x800u
#define USBPHY_PWD_TXPWDIBIAS_SHIFT              11
#define USBPHY_PWD_TXPWDV2I_MASK                 0x1000u
#define USBPHY_PWD_TXPWDV2I_SHIFT                12
#define USBPHY_PWD_RSVD1_MASK                    0x1E000u
#define USBPHY_PWD_RSVD1_SHIFT                   13
#define USBPHY_PWD_RSVD1(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD1_SHIFT))&USBPHY_PWD_RSVD1_MASK)
#define USBPHY_PWD_RXPWDENV_MASK                 0x20000u
#define USBPHY_PWD_RXPWDENV_SHIFT                17
#define USBPHY_PWD_RXPWD1PT1_MASK                0x40000u
#define USBPHY_PWD_RXPWD1PT1_SHIFT               18
#define USBPHY_PWD_RXPWDDIFF_MASK                0x80000u
#define USBPHY_PWD_RXPWDDIFF_SHIFT               19
#define USBPHY_PWD_RXPWDRX_MASK                  0x100000u
#define USBPHY_PWD_RXPWDRX_SHIFT                 20
#define USBPHY_PWD_RSVD2_MASK                    0xFFE00000u
#define USBPHY_PWD_RSVD2_SHIFT                   21
#define USBPHY_PWD_RSVD2(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD2_SHIFT))&USBPHY_PWD_RSVD2_MASK)
/* PWD_SET Bit Fields */
#define USBPHY_PWD_SET_RSVD0_MASK                0x3FFu
#define USBPHY_PWD_SET_RSVD0_SHIFT               0
#define USBPHY_PWD_SET_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD0_SHIFT))&USBPHY_PWD_SET_RSVD0_MASK)
#define USBPHY_PWD_SET_TXPWDFS_MASK              0x400u
#define USBPHY_PWD_SET_TXPWDFS_SHIFT             10
#define USBPHY_PWD_SET_TXPWDIBIAS_MASK           0x800u
#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          11
#define USBPHY_PWD_SET_TXPWDV2I_MASK             0x1000u
#define USBPHY_PWD_SET_TXPWDV2I_SHIFT            12
#define USBPHY_PWD_SET_RSVD1_MASK                0x1E000u
#define USBPHY_PWD_SET_RSVD1_SHIFT               13
#define USBPHY_PWD_SET_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD1_SHIFT))&USBPHY_PWD_SET_RSVD1_MASK)
#define USBPHY_PWD_SET_RXPWDENV_MASK             0x20000u
#define USBPHY_PWD_SET_RXPWDENV_SHIFT            17
#define USBPHY_PWD_SET_RXPWD1PT1_MASK            0x40000u
#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           18
#define USBPHY_PWD_SET_RXPWDDIFF_MASK            0x80000u
#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           19
#define USBPHY_PWD_SET_RXPWDRX_MASK              0x100000u
#define USBPHY_PWD_SET_RXPWDRX_SHIFT             20
#define USBPHY_PWD_SET_RSVD2_MASK                0xFFE00000u
#define USBPHY_PWD_SET_RSVD2_SHIFT               21
#define USBPHY_PWD_SET_RSVD2(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD2_SHIFT))&USBPHY_PWD_SET_RSVD2_MASK)
/* PWD_CLR Bit Fields */
#define USBPHY_PWD_CLR_RSVD0_MASK                0x3FFu
#define USBPHY_PWD_CLR_RSVD0_SHIFT               0
#define USBPHY_PWD_CLR_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD0_SHIFT))&USBPHY_PWD_CLR_RSVD0_MASK)
#define USBPHY_PWD_CLR_TXPWDFS_MASK              0x400u
#define USBPHY_PWD_CLR_TXPWDFS_SHIFT             10
#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           0x800u
#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          11
#define USBPHY_PWD_CLR_TXPWDV2I_MASK             0x1000u
#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            12
#define USBPHY_PWD_CLR_RSVD1_MASK                0x1E000u
#define USBPHY_PWD_CLR_RSVD1_SHIFT               13
#define USBPHY_PWD_CLR_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD1_SHIFT))&USBPHY_PWD_CLR_RSVD1_MASK)
#define USBPHY_PWD_CLR_RXPWDENV_MASK             0x20000u
#define USBPHY_PWD_CLR_RXPWDENV_SHIFT            17
#define USBPHY_PWD_CLR_RXPWD1PT1_MASK            0x40000u
#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           18
#define USBPHY_PWD_CLR_RXPWDDIFF_MASK            0x80000u
#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           19
#define USBPHY_PWD_CLR_RXPWDRX_MASK              0x100000u
#define USBPHY_PWD_CLR_RXPWDRX_SHIFT             20
#define USBPHY_PWD_CLR_RSVD2_MASK                0xFFE00000u
#define USBPHY_PWD_CLR_RSVD2_SHIFT               21
#define USBPHY_PWD_CLR_RSVD2(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD2_SHIFT))&USBPHY_PWD_CLR_RSVD2_MASK)
/* PWD_TOG Bit Fields */
#define USBPHY_PWD_TOG_RSVD0_MASK                0x3FFu
#define USBPHY_PWD_TOG_RSVD0_SHIFT               0
#define USBPHY_PWD_TOG_RSVD0(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD0_SHIFT))&USBPHY_PWD_TOG_RSVD0_MASK)
#define USBPHY_PWD_TOG_TXPWDFS_MASK              0x400u
#define USBPHY_PWD_TOG_TXPWDFS_SHIFT             10
#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           0x800u
#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          11
#define USBPHY_PWD_TOG_TXPWDV2I_MASK             0x1000u
#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            12
#define USBPHY_PWD_TOG_RSVD1_MASK                0x1E000u
#define USBPHY_PWD_TOG_RSVD1_SHIFT               13
#define USBPHY_PWD_TOG_RSVD1(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD1_SHIFT))&USBPHY_PWD_TOG_RSVD1_MASK)
#define USBPHY_PWD_TOG_RXPWDENV_MASK             0x20000u
#define USBPHY_PWD_TOG_RXPWDENV_SHIFT            17
#define USBPHY_PWD_TOG_RXPWD1PT1_MASK            0x40000u
#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           18
#define USBPHY_PWD_TOG_RXPWDDIFF_MASK            0x80000u
#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           19
#define USBPHY_PWD_TOG_RXPWDRX_MASK              0x100000u
#define USBPHY_PWD_TOG_RXPWDRX_SHIFT             20
#define USBPHY_PWD_TOG_RSVD2_MASK                0xFFE00000u
#define USBPHY_PWD_TOG_RSVD2_SHIFT               21
#define USBPHY_PWD_TOG_RSVD2(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD2_SHIFT))&USBPHY_PWD_TOG_RSVD2_MASK)
/* TX Bit Fields */
#define USBPHY_TX_D_CAL_MASK                     0xFu
#define USBPHY_TX_D_CAL_SHIFT                    0
#define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_D_CAL_SHIFT))&USBPHY_TX_D_CAL_MASK)
#define USBPHY_TX_RSVD0_MASK                     0xF0u
#define USBPHY_TX_RSVD0_SHIFT                    4
#define USBPHY_TX_RSVD0(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD0_SHIFT))&USBPHY_TX_RSVD0_MASK)
#define USBPHY_TX_TXCAL45DM_MASK                 0xF00u
#define USBPHY_TX_TXCAL45DM_SHIFT                8
#define USBPHY_TX_TXCAL45DM(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DM_SHIFT))&USBPHY_TX_TXCAL45DM_MASK)
#define USBPHY_TX_RSVD1_MASK                     0xF000u
#define USBPHY_TX_RSVD1_SHIFT                    12
#define USBPHY_TX_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD1_SHIFT))&USBPHY_TX_RSVD1_MASK)
#define USBPHY_TX_TXCAL45DP_MASK                 0xF0000u
#define USBPHY_TX_TXCAL45DP_SHIFT                16
#define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DP_SHIFT))&USBPHY_TX_TXCAL45DP_MASK)
#define USBPHY_TX_RSVD2_MASK                     0xFFF00000u
#define USBPHY_TX_RSVD2_SHIFT                    20
#define USBPHY_TX_RSVD2(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD2_SHIFT))&USBPHY_TX_RSVD2_MASK)
/* RX Bit Fields */
#define USBPHY_RX_ENVADJ_MASK                    0x7u
#define USBPHY_RX_ENVADJ_SHIFT                   0
#define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_ENVADJ_SHIFT))&USBPHY_RX_ENVADJ_MASK)
#define USBPHY_RX_RSVD0_MASK                     0x8u
#define USBPHY_RX_RSVD0_SHIFT                    3
#define USBPHY_RX_DISCONADJ_MASK                 0x70u
#define USBPHY_RX_DISCONADJ_SHIFT                4
#define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_DISCONADJ_SHIFT))&USBPHY_RX_DISCONADJ_MASK)
#define USBPHY_RX_RSVD1_MASK                     0x3FFF80u
#define USBPHY_RX_RSVD1_SHIFT                    7
#define USBPHY_RX_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD1_SHIFT))&USBPHY_RX_RSVD1_MASK)
#define USBPHY_RX_RXDBYPASS_MASK                 0x400000u
#define USBPHY_RX_RXDBYPASS_SHIFT                22
#define USBPHY_RX_RSVD2_MASK                     0xFF800000u
#define USBPHY_RX_RSVD2_SHIFT                    23
#define USBPHY_RX_RSVD2(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD2_SHIFT))&USBPHY_RX_RSVD2_MASK)
/* RX_SET Bit Fields */
#define USBPHY_RX_SET_ENVADJ_MASK                0x7u
#define USBPHY_RX_SET_ENVADJ_SHIFT               0
#define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_ENVADJ_SHIFT))&USBPHY_RX_SET_ENVADJ_MASK)
#define USBPHY_RX_SET_RSVD0_MASK                 0x8u
#define USBPHY_RX_SET_RSVD0_SHIFT                3
#define USBPHY_RX_SET_DISCONADJ_MASK             0x70u
#define USBPHY_RX_SET_DISCONADJ_SHIFT            4
#define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_DISCONADJ_SHIFT))&USBPHY_RX_SET_DISCONADJ_MASK)
#define USBPHY_RX_SET_RSVD1_MASK                 0x3FFF80u
#define USBPHY_RX_SET_RSVD1_SHIFT                7
#define USBPHY_RX_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD1_SHIFT))&USBPHY_RX_SET_RSVD1_MASK)
#define USBPHY_RX_SET_RXDBYPASS_MASK             0x400000u
#define USBPHY_RX_SET_RXDBYPASS_SHIFT            22
#define USBPHY_RX_SET_RSVD2_MASK                 0xFF800000u
#define USBPHY_RX_SET_RSVD2_SHIFT                23
#define USBPHY_RX_SET_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD2_SHIFT))&USBPHY_RX_SET_RSVD2_MASK)
/* RX_CLR Bit Fields */
#define USBPHY_RX_CLR_ENVADJ_MASK                0x7u
#define USBPHY_RX_CLR_ENVADJ_SHIFT               0
#define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_ENVADJ_SHIFT))&USBPHY_RX_CLR_ENVADJ_MASK)
#define USBPHY_RX_CLR_RSVD0_MASK                 0x8u
#define USBPHY_RX_CLR_RSVD0_SHIFT                3
#define USBPHY_RX_CLR_DISCONADJ_MASK             0x70u
#define USBPHY_RX_CLR_DISCONADJ_SHIFT            4
#define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_DISCONADJ_SHIFT))&USBPHY_RX_CLR_DISCONADJ_MASK)
#define USBPHY_RX_CLR_RSVD1_MASK                 0x3FFF80u
#define USBPHY_RX_CLR_RSVD1_SHIFT                7
#define USBPHY_RX_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD1_SHIFT))&USBPHY_RX_CLR_RSVD1_MASK)
#define USBPHY_RX_CLR_RXDBYPASS_MASK             0x400000u
#define USBPHY_RX_CLR_RXDBYPASS_SHIFT            22
#define USBPHY_RX_CLR_RSVD2_MASK                 0xFF800000u
#define USBPHY_RX_CLR_RSVD2_SHIFT                23
#define USBPHY_RX_CLR_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD2_SHIFT))&USBPHY_RX_CLR_RSVD2_MASK)
/* RX_TOG Bit Fields */
#define USBPHY_RX_TOG_ENVADJ_MASK                0x7u
#define USBPHY_RX_TOG_ENVADJ_SHIFT               0
#define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_ENVADJ_SHIFT))&USBPHY_RX_TOG_ENVADJ_MASK)
#define USBPHY_RX_TOG_RSVD0_MASK                 0x8u
#define USBPHY_RX_TOG_RSVD0_SHIFT                3
#define USBPHY_RX_TOG_DISCONADJ_MASK             0x70u
#define USBPHY_RX_TOG_DISCONADJ_SHIFT            4
#define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_DISCONADJ_SHIFT))&USBPHY_RX_TOG_DISCONADJ_MASK)
#define USBPHY_RX_TOG_RSVD1_MASK                 0x3FFF80u
#define USBPHY_RX_TOG_RSVD1_SHIFT                7
#define USBPHY_RX_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD1_SHIFT))&USBPHY_RX_TOG_RSVD1_MASK)
#define USBPHY_RX_TOG_RXDBYPASS_MASK             0x400000u
#define USBPHY_RX_TOG_RXDBYPASS_SHIFT            22
#define USBPHY_RX_TOG_RSVD2_MASK                 0xFF800000u
#define USBPHY_RX_TOG_RSVD2_SHIFT                23
#define USBPHY_RX_TOG_RSVD2(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD2_SHIFT))&USBPHY_RX_TOG_RSVD2_MASK)
/* CTRL Bit Fields */
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        0x1u
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       0
#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      0x2u
#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     1
#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         0x4u
#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        2
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    0x8u
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   3
#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       0x10u
#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      4
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      0x20u
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     5
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          0x40u
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         6
#define USBPHY_CTRL_ENOTGIDDETECT_MASK           0x80u
#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          7
#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         0x100u
#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        8
#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       0x200u
#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      9
#define USBPHY_CTRL_RESUME_IRQ_MASK              0x400u
#define USBPHY_CTRL_RESUME_IRQ_SHIFT             10
#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          0x800u
#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         11
#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           0x1000u
#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          12
#define USBPHY_CTRL_DATA_ON_LRADC_MASK           0x2000u
#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT          13
#define USBPHY_CTRL_ENUTMILEVEL2_MASK            0x4000u
#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           14
#define USBPHY_CTRL_ENUTMILEVEL3_MASK            0x8000u
#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           15
#define USBPHY_CTRL_ENIRQWAKEUP_MASK             0x10000u
#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            16
#define USBPHY_CTRL_WAKEUP_IRQ_MASK              0x20000u
#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             17
#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK        0x40000u
#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT       18
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       0x80000u
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      19
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       0x100000u
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      20
#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          0x200000u
#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         21
#define USBPHY_CTRL_ENIDCHG_WKUP_MASK            0x400000u
#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           22
#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          0x800000u
#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         23
#define USBPHY_CTRL_FSDLL_RST_EN_MASK            0x1000000u
#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           24
#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK    0x2000000u
#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT   25
#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK       0x4000000u
#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT      26
#define USBPHY_CTRL_OTG_ID_VALUE_MASK            0x8000000u
#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           27
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       0x10000000u
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      28
#define USBPHY_CTRL_UTMI_SUSPENDM_MASK           0x20000000u
#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          29
#define USBPHY_CTRL_CLKGATE_MASK                 0x40000000u
#define USBPHY_CTRL_CLKGATE_SHIFT                30
#define USBPHY_CTRL_SFTRST_MASK                  0x80000000u
#define USBPHY_CTRL_SFTRST_SHIFT                 31
/* CTRL_SET Bit Fields */
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    0x1u
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   0
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  0x2u
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT 1
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     0x4u
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    2
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK 0x8u
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT 3
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   0x10u
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  4
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  0x20u
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT 5
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      0x40u
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     6
#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       0x80u
#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      7
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     0x100u
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    8
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   0x200u
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  9
#define USBPHY_CTRL_SET_RESUME_IRQ_MASK          0x400u
#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         10
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      0x800u
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     11
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       0x1000u
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      12
#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK       0x2000u
#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT      13
#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        0x4000u
#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       14
#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        0x8000u
#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       15
#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         0x10000u
#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        16
#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          0x20000u
#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         17
#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK    0x40000u
#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT   18
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   0x80000u
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  19
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   0x100000u
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  20
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      0x200000u
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     21
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        0x400000u
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       22
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      0x800000u
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     23
#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        0x1000000u
#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       24
#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK 0x2000000u
#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT 25
#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK   0x4000000u
#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT  26
#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        0x8000000u
#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       27
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   0x10000000u
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  28
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       0x20000000u
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      29
#define USBPHY_CTRL_SET_CLKGATE_MASK             0x40000000u
#define USBPHY_CTRL_SET_CLKGATE_SHIFT            30
#define USBPHY_CTRL_SET_SFTRST_MASK              0x80000000u
#define USBPHY_CTRL_SET_SFTRST_SHIFT             31
/* CTRL_CLR Bit Fields */
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    0x1u
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   0
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  0x2u
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT 1
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     0x4u
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    2
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK 0x8u
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT 3
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   0x10u
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  4
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  0x20u
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT 5
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      0x40u
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     6
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       0x80u
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      7
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     0x100u
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    8
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   0x200u
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  9
#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          0x400u
#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         10
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      0x800u
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     11
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       0x1000u
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      12
#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK       0x2000u
#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT      13
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        0x4000u
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       14
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        0x8000u
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       15
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         0x10000u
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        16
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          0x20000u
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         17
#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK    0x40000u
#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT   18
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   0x80000u
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  19
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   0x100000u
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  20
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      0x200000u
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     21
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        0x400000u
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       22
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      0x800000u
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     23
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        0x1000000u
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       24
#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK 0x2000000u
#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT 25
#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK   0x4000000u
#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT  26
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        0x8000000u
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       27
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   0x10000000u
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  28
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       0x20000000u
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      29
#define USBPHY_CTRL_CLR_CLKGATE_MASK             0x40000000u
#define USBPHY_CTRL_CLR_CLKGATE_SHIFT            30
#define USBPHY_CTRL_CLR_SFTRST_MASK              0x80000000u
#define USBPHY_CTRL_CLR_SFTRST_SHIFT             31
/* CTRL_TOG Bit Fields */
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    0x1u
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   0
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  0x2u
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT 1
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     0x4u
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    2
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK 0x8u
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT 3
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   0x10u
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  4
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  0x20u
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT 5
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      0x40u
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     6
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       0x80u
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      7
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     0x100u
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    8
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   0x200u
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  9
#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          0x400u
#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         10
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      0x800u
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     11
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       0x1000u
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      12
#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK       0x2000u
#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT      13
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        0x4000u
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       14
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        0x8000u
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       15
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         0x10000u
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        16
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          0x20000u
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         17
#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK    0x40000u
#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT   18
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   0x80000u
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  19
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   0x100000u
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  20
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      0x200000u
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     21
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        0x400000u
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       22
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      0x800000u
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     23
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        0x1000000u
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       24
#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK 0x2000000u
#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT 25
#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK   0x4000000u
#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT  26
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        0x8000000u
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       27
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   0x10000000u
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  28
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       0x20000000u
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      29
#define USBPHY_CTRL_TOG_CLKGATE_MASK             0x40000000u
#define USBPHY_CTRL_TOG_CLKGATE_SHIFT            30
#define USBPHY_CTRL_TOG_SFTRST_MASK              0x80000000u
#define USBPHY_CTRL_TOG_SFTRST_SHIFT             31
/* STATUS Bit Fields */
#define USBPHY_STATUS_RSVD0_MASK                 0x7u
#define USBPHY_STATUS_RSVD0_SHIFT                0
#define USBPHY_STATUS_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD0_SHIFT))&USBPHY_STATUS_RSVD0_MASK)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK 0x8u
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT 3
#define USBPHY_STATUS_RSVD1_MASK                 0x30u
#define USBPHY_STATUS_RSVD1_SHIFT                4
#define USBPHY_STATUS_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD1_SHIFT))&USBPHY_STATUS_RSVD1_MASK)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      0x40u
#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     6
#define USBPHY_STATUS_RSVD2_MASK                 0x80u
#define USBPHY_STATUS_RSVD2_SHIFT                7
#define USBPHY_STATUS_OTGID_STATUS_MASK          0x100u
#define USBPHY_STATUS_OTGID_STATUS_SHIFT         8
#define USBPHY_STATUS_RSVD3_MASK                 0x200u
#define USBPHY_STATUS_RSVD3_SHIFT                9
#define USBPHY_STATUS_RESUME_STATUS_MASK         0x400u
#define USBPHY_STATUS_RESUME_STATUS_SHIFT        10
#define USBPHY_STATUS_RSVD4_MASK                 0xFFFFF800u
#define USBPHY_STATUS_RSVD4_SHIFT                11
#define USBPHY_STATUS_RSVD4(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD4_SHIFT))&USBPHY_STATUS_RSVD4_MASK)
/* DEBUG Bit Fields */
#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           0x1u
#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          0
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   0x2u
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  1
#define USBPHY_DEBUG_HSTPULLDOWN_MASK            0xCu
#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           2
#define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          0x30u
#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         4
#define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_RSVD0_MASK                  0xC0u
#define USBPHY_DEBUG_RSVD0_SHIFT                 6
#define USBPHY_DEBUG_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD0_SHIFT))&USBPHY_DEBUG_RSVD0_MASK)
#define USBPHY_DEBUG_TX2RXCOUNT_MASK             0xF00u
#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            8
#define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           0x1000u
#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          12
#define USBPHY_DEBUG_RSVD1_MASK                  0xE000u
#define USBPHY_DEBUG_RSVD1_SHIFT                 13
#define USBPHY_DEBUG_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD1_SHIFT))&USBPHY_DEBUG_RSVD1_MASK)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      0x1F0000u
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     16
#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_RSVD2_MASK                  0xE00000u
#define USBPHY_DEBUG_RSVD2_SHIFT                 21
#define USBPHY_DEBUG_RSVD2(x)                    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD2_SHIFT))&USBPHY_DEBUG_RSVD2_MASK)
#define USBPHY_DEBUG_ENSQUELCHRESET_MASK         0x1000000u
#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        24
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     0x1E000000u
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    25
#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      0x20000000u
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     29
#define USBPHY_DEBUG_CLKGATE_MASK                0x40000000u
#define USBPHY_DEBUG_CLKGATE_SHIFT               30
#define USBPHY_DEBUG_RSVD3_MASK                  0x80000000u
#define USBPHY_DEBUG_RSVD3_SHIFT                 31
/* DEBUG_SET Bit Fields */
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       0x1u
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      0
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK 0x2u
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT 1
#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        0xCu
#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       2
#define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      0x30u
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     4
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_SET_RSVD0_MASK              0xC0u
#define USBPHY_DEBUG_SET_RSVD0_SHIFT             6
#define USBPHY_DEBUG_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD0_SHIFT))&USBPHY_DEBUG_SET_RSVD0_MASK)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         0xF00u
#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        8
#define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       0x1000u
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      12
#define USBPHY_DEBUG_SET_RSVD1_MASK              0xE000u
#define USBPHY_DEBUG_SET_RSVD1_SHIFT             13
#define USBPHY_DEBUG_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD1_SHIFT))&USBPHY_DEBUG_SET_RSVD1_MASK)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  0x1F0000u
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT 16
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_SET_RSVD2_MASK              0xE00000u
#define USBPHY_DEBUG_SET_RSVD2_SHIFT             21
#define USBPHY_DEBUG_SET_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD2_SHIFT))&USBPHY_DEBUG_SET_RSVD2_MASK)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     0x1000000u
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    24
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK 0x1E000000u
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT 25
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  0x20000000u
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT 29
#define USBPHY_DEBUG_SET_CLKGATE_MASK            0x40000000u
#define USBPHY_DEBUG_SET_CLKGATE_SHIFT           30
#define USBPHY_DEBUG_SET_RSVD3_MASK              0x80000000u
#define USBPHY_DEBUG_SET_RSVD3_SHIFT             31
/* DEBUG_CLR Bit Fields */
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       0x1u
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      0
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK 0x2u
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT 1
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        0xCu
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       2
#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      0x30u
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     4
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_CLR_RSVD0_MASK              0xC0u
#define USBPHY_DEBUG_CLR_RSVD0_SHIFT             6
#define USBPHY_DEBUG_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD0_SHIFT))&USBPHY_DEBUG_CLR_RSVD0_MASK)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         0xF00u
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        8
#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       0x1000u
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      12
#define USBPHY_DEBUG_CLR_RSVD1_MASK              0xE000u
#define USBPHY_DEBUG_CLR_RSVD1_SHIFT             13
#define USBPHY_DEBUG_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD1_SHIFT))&USBPHY_DEBUG_CLR_RSVD1_MASK)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  0x1F0000u
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT 16
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_CLR_RSVD2_MASK              0xE00000u
#define USBPHY_DEBUG_CLR_RSVD2_SHIFT             21
#define USBPHY_DEBUG_CLR_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD2_SHIFT))&USBPHY_DEBUG_CLR_RSVD2_MASK)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     0x1000000u
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    24
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK 0x1E000000u
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT 25
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  0x20000000u
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT 29
#define USBPHY_DEBUG_CLR_CLKGATE_MASK            0x40000000u
#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           30
#define USBPHY_DEBUG_CLR_RSVD3_MASK              0x80000000u
#define USBPHY_DEBUG_CLR_RSVD3_SHIFT             31
/* DEBUG_TOG Bit Fields */
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       0x1u
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      0
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK 0x2u
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT 1
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        0xCu
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       2
#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      0x30u
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     4
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TOG_RSVD0_MASK              0xC0u
#define USBPHY_DEBUG_TOG_RSVD0_SHIFT             6
#define USBPHY_DEBUG_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD0_SHIFT))&USBPHY_DEBUG_TOG_RSVD0_MASK)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         0xF00u
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        8
#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       0x1000u
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      12
#define USBPHY_DEBUG_TOG_RSVD1_MASK              0xE000u
#define USBPHY_DEBUG_TOG_RSVD1_SHIFT             13
#define USBPHY_DEBUG_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD1_SHIFT))&USBPHY_DEBUG_TOG_RSVD1_MASK)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  0x1F0000u
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT 16
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_TOG_RSVD2_MASK              0xE00000u
#define USBPHY_DEBUG_TOG_RSVD2_SHIFT             21
#define USBPHY_DEBUG_TOG_RSVD2(x)                (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD2_SHIFT))&USBPHY_DEBUG_TOG_RSVD2_MASK)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     0x1000000u
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    24
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK 0x1E000000u
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT 25
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  0x20000000u
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT 29
#define USBPHY_DEBUG_TOG_CLKGATE_MASK            0x40000000u
#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           30
#define USBPHY_DEBUG_TOG_RSVD3_MASK              0x80000000u
#define USBPHY_DEBUG_TOG_RSVD3_SHIFT             31
/* DEBUG0_STATUS Bit Fields */
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK 0xFFFFu
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT 0
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK 0x3FF0000u
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT 16
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  0xFC000000u
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT 26
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
/* DEBUG1 Bit Fields */
#define USBPHY_DEBUG1_RSVD0_MASK                 0x1FFFu
#define USBPHY_DEBUG1_RSVD0_SHIFT                0
#define USBPHY_DEBUG1_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD0_SHIFT))&USBPHY_DEBUG1_RSVD0_MASK)
#define USBPHY_DEBUG1_ENTAILADJVD_MASK           0x6000u
#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          13
#define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_RSVD1_MASK                 0xFFFF8000u
#define USBPHY_DEBUG1_RSVD1_SHIFT                15
#define USBPHY_DEBUG1_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD1_SHIFT))&USBPHY_DEBUG1_RSVD1_MASK)
/* DEBUG1_SET Bit Fields */
#define USBPHY_DEBUG1_SET_RSVD0_MASK             0x1FFFu
#define USBPHY_DEBUG1_SET_RSVD0_SHIFT            0
#define USBPHY_DEBUG1_SET_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD0_SHIFT))&USBPHY_DEBUG1_SET_RSVD0_MASK)
#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       0x6000u
#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      13
#define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_SET_RSVD1_MASK             0xFFFF8000u
#define USBPHY_DEBUG1_SET_RSVD1_SHIFT            15
#define USBPHY_DEBUG1_SET_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD1_SHIFT))&USBPHY_DEBUG1_SET_RSVD1_MASK)
/* DEBUG1_CLR Bit Fields */
#define USBPHY_DEBUG1_CLR_RSVD0_MASK             0x1FFFu
#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT            0
#define USBPHY_DEBUG1_CLR_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD0_SHIFT))&USBPHY_DEBUG1_CLR_RSVD0_MASK)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       0x6000u
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      13
#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_CLR_RSVD1_MASK             0xFFFF8000u
#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT            15
#define USBPHY_DEBUG1_CLR_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD1_SHIFT))&USBPHY_DEBUG1_CLR_RSVD1_MASK)
/* DEBUG1_TOG Bit Fields */
#define USBPHY_DEBUG1_TOG_RSVD0_MASK             0x1FFFu
#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT            0
#define USBPHY_DEBUG1_TOG_RSVD0(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD0_SHIFT))&USBPHY_DEBUG1_TOG_RSVD0_MASK)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       0x6000u
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      13
#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_TOG_RSVD1_MASK             0xFFFF8000u
#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT            15
#define USBPHY_DEBUG1_TOG_RSVD1(x)               (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD1_SHIFT))&USBPHY_DEBUG1_TOG_RSVD1_MASK)
/* VERSION Bit Fields */
#define USBPHY_VERSION_STEP_MASK                 0xFFFFu
#define USBPHY_VERSION_STEP_SHIFT                0
#define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_STEP_SHIFT))&USBPHY_VERSION_STEP_MASK)
#define USBPHY_VERSION_MINOR_MASK                0xFF0000u
#define USBPHY_VERSION_MINOR_SHIFT               16
#define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MINOR_SHIFT))&USBPHY_VERSION_MINOR_MASK)
#define USBPHY_VERSION_MAJOR_MASK                0xFF000000u
#define USBPHY_VERSION_MAJOR_SHIFT               24
#define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MAJOR_SHIFT))&USBPHY_VERSION_MAJOR_MASK)
/* IP Bit Fields */
#define USBPHY_IP_PLL_POWER_MASK                 0x1u
#define USBPHY_IP_PLL_POWER_SHIFT                0
#define USBPHY_IP_PLL_LOCKED_MASK                0x2u
#define USBPHY_IP_PLL_LOCKED_SHIFT               1
#define USBPHY_IP_EN_USB_CLKS_MASK               0x4u
#define USBPHY_IP_EN_USB_CLKS_SHIFT              2
#define USBPHY_IP_RSVD0_MASK                     0xFFF8u
#define USBPHY_IP_RSVD0_SHIFT                    3
#define USBPHY_IP_RSVD0(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_RSVD0_SHIFT))&USBPHY_IP_RSVD0_MASK)
#define USBPHY_IP_ANALOG_TESTMODE_MASK           0x10000u
#define USBPHY_IP_ANALOG_TESTMODE_SHIFT          16
#define USBPHY_IP_TSTI_TX_DM_MASK                0x20000u
#define USBPHY_IP_TSTI_TX_DM_SHIFT               17
#define USBPHY_IP_TSTI_TX_DP_MASK                0x40000u
#define USBPHY_IP_TSTI_TX_DP_SHIFT               18
#define USBPHY_IP_RSVD1_MASK                     0xFFF80000u
#define USBPHY_IP_RSVD1_SHIFT                    19
#define USBPHY_IP_RSVD1(x)                       (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_RSVD1_SHIFT))&USBPHY_IP_RSVD1_MASK)
/* IP_SET Bit Fields */
#define USBPHY_IP_SET_PLL_POWER_MASK             0x1u
#define USBPHY_IP_SET_PLL_POWER_SHIFT            0
#define USBPHY_IP_SET_PLL_LOCKED_MASK            0x2u
#define USBPHY_IP_SET_PLL_LOCKED_SHIFT           1
#define USBPHY_IP_SET_EN_USB_CLKS_MASK           0x4u
#define USBPHY_IP_SET_EN_USB_CLKS_SHIFT          2
#define USBPHY_IP_SET_RSVD0_MASK                 0xFFF8u
#define USBPHY_IP_SET_RSVD0_SHIFT                3
#define USBPHY_IP_SET_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_SET_RSVD0_SHIFT))&USBPHY_IP_SET_RSVD0_MASK)
#define USBPHY_IP_SET_ANALOG_TESTMODE_MASK       0x10000u
#define USBPHY_IP_SET_ANALOG_TESTMODE_SHIFT      16
#define USBPHY_IP_SET_TSTI_TX_DM_MASK            0x20000u
#define USBPHY_IP_SET_TSTI_TX_DM_SHIFT           17
#define USBPHY_IP_SET_TSTI_TX_DP_MASK            0x40000u
#define USBPHY_IP_SET_TSTI_TX_DP_SHIFT           18
#define USBPHY_IP_SET_RSVD1_MASK                 0xFFF80000u
#define USBPHY_IP_SET_RSVD1_SHIFT                19
#define USBPHY_IP_SET_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_SET_RSVD1_SHIFT))&USBPHY_IP_SET_RSVD1_MASK)
/* IP_CLR Bit Fields */
#define USBPHY_IP_CLR_PLL_POWER_MASK             0x1u
#define USBPHY_IP_CLR_PLL_POWER_SHIFT            0
#define USBPHY_IP_CLR_PLL_LOCKED_MASK            0x2u
#define USBPHY_IP_CLR_PLL_LOCKED_SHIFT           1
#define USBPHY_IP_CLR_EN_USB_CLKS_MASK           0x4u
#define USBPHY_IP_CLR_EN_USB_CLKS_SHIFT          2
#define USBPHY_IP_CLR_RSVD0_MASK                 0xFFF8u
#define USBPHY_IP_CLR_RSVD0_SHIFT                3
#define USBPHY_IP_CLR_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_CLR_RSVD0_SHIFT))&USBPHY_IP_CLR_RSVD0_MASK)
#define USBPHY_IP_CLR_ANALOG_TESTMODE_MASK       0x10000u
#define USBPHY_IP_CLR_ANALOG_TESTMODE_SHIFT      16
#define USBPHY_IP_CLR_TSTI_TX_DM_MASK            0x20000u
#define USBPHY_IP_CLR_TSTI_TX_DM_SHIFT           17
#define USBPHY_IP_CLR_TSTI_TX_DP_MASK            0x40000u
#define USBPHY_IP_CLR_TSTI_TX_DP_SHIFT           18
#define USBPHY_IP_CLR_RSVD1_MASK                 0xFFF80000u
#define USBPHY_IP_CLR_RSVD1_SHIFT                19
#define USBPHY_IP_CLR_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_CLR_RSVD1_SHIFT))&USBPHY_IP_CLR_RSVD1_MASK)
/* IP_TOG Bit Fields */
#define USBPHY_IP_TOG_PLL_POWER_MASK             0x1u
#define USBPHY_IP_TOG_PLL_POWER_SHIFT            0
#define USBPHY_IP_TOG_PLL_LOCKED_MASK            0x2u
#define USBPHY_IP_TOG_PLL_LOCKED_SHIFT           1
#define USBPHY_IP_TOG_EN_USB_CLKS_MASK           0x4u
#define USBPHY_IP_TOG_EN_USB_CLKS_SHIFT          2
#define USBPHY_IP_TOG_RSVD0_MASK                 0xFFF8u
#define USBPHY_IP_TOG_RSVD0_SHIFT                3
#define USBPHY_IP_TOG_RSVD0(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_TOG_RSVD0_SHIFT))&USBPHY_IP_TOG_RSVD0_MASK)
#define USBPHY_IP_TOG_ANALOG_TESTMODE_MASK       0x10000u
#define USBPHY_IP_TOG_ANALOG_TESTMODE_SHIFT      16
#define USBPHY_IP_TOG_TSTI_TX_DM_MASK            0x20000u
#define USBPHY_IP_TOG_TSTI_TX_DM_SHIFT           17
#define USBPHY_IP_TOG_TSTI_TX_DP_MASK            0x40000u
#define USBPHY_IP_TOG_TSTI_TX_DP_SHIFT           18
#define USBPHY_IP_TOG_RSVD1_MASK                 0xFFF80000u
#define USBPHY_IP_TOG_RSVD1_SHIFT                19
#define USBPHY_IP_TOG_RSVD1(x)                   (((uint32_t)(((uint32_t)(x))<<USBPHY_IP_TOG_RSVD1_SHIFT))&USBPHY_IP_TOG_RSVD1_MASK)

/**
 * @}
 */ /* end of group USBPHY_Register_Masks */


/* USBPHY - Peripheral instance base addresses */
/** Peripheral USBPHY0 base address */
#define USBPHY0_BASE                             (0x40050800u)
/** Peripheral USBPHY0 base pointer */
#define USBPHY0                                  ((USBPHY_Type *)USBPHY0_BASE)
/** Peripheral USBPHY1 base address */
#define USBPHY1_BASE                             (0x40050C00u)
/** Peripheral USBPHY1 base pointer */
#define USBPHY1                                  ((USBPHY_Type *)USBPHY1_BASE)
/** Array initializer of USBPHY peripheral base pointers */
#define USBPHY_BASES                             { USBPHY0, USBPHY1 }

/**
 * @}
 */ /* end of group USBPHY_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USB_ANALOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer
 * @{
 */

/** USB_ANALOG - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[416];
  __IO uint32_t USB0_VBUS_DETECT;                  /**< USB0 VBUS Detect control register, offset: 0x1A0 */
       uint8_t RESERVED_1[12];
  __IO uint32_t USB0_CHRG_DETECT;                  /**< USB0 Charger Detect control register, offset: 0x1B0 */
       uint8_t RESERVED_2[12];
  __I  uint32_t USB0_VBUS_DETECT_STATUS;           /**< USB0 VBUS Detect Status definition register, offset: 0x1C0 */
       uint8_t RESERVED_3[12];
  __I  uint32_t USB0_CHRG_DETECT_STATUS;           /**< USB0 Charger Detect Status definition register, offset: 0x1D0 */
       uint8_t RESERVED_4[12];
  __IO uint32_t USB0_LOOPBACK;                     /**< USB0 Loopback register, offset: 0x1E0 */
       uint8_t RESERVED_5[12];
  __IO uint32_t USB0_MISC;                         /**< USB0 Miscellaneous definition register, offset: 0x1F0 */
       uint8_t RESERVED_6[12];
  __IO uint32_t USB1_VBUS_DETECT;                  /**< USB1 VBUS Detect control register, offset: 0x200 */
       uint8_t RESERVED_7[12];
  __IO uint32_t USB1_CHRG_DETECT;                  /**< USB1 Charger Detect control register, offset: 0x210 */
       uint8_t RESERVED_8[12];
  __I  uint32_t USB1_VBUS_DETECT_STATUS;           /**< USB1 VBUS Detect STS definition register, offset: 0x220 */
       uint8_t RESERVED_9[12];
  __I  uint32_t USB1_CHRG_DETECT_STATUS;           /**< USB1 Charger Detect Status definition register, offset: 0x230 */
       uint8_t RESERVED_10[12];
  __IO uint32_t USB1_LOOPBACK;                     /**< USB1 Loopback register, offset: 0x240 */
       uint8_t RESERVED_11[12];
  __IO uint32_t USB1_MISC;                         /**< USB1 Miscellaneous definition register, offset: 0x250 */
} USB_ANALOG_Type;

/* ----------------------------------------------------------------------------
   -- USB_ANALOG Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks
 * @{
 */

/* USB0_VBUS_DETECT Bit Fields */
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_THRESH_MASK)
#define USB_ANALOG_USB0_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK 0x8u
#define USB_ANALOG_USB0_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT 3
#define USB_ANALOG_USB0_VBUS_DETECT_SESSEND_OVERRIDE_MASK 0x10u
#define USB_ANALOG_USB0_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT 4
#define USB_ANALOG_USB0_VBUS_DETECT_BVALID_OVERRIDE_MASK 0x20u
#define USB_ANALOG_USB0_VBUS_DETECT_BVALID_OVERRIDE_SHIFT 5
#define USB_ANALOG_USB0_VBUS_DETECT_AVALID_OVERRIDE_MASK 0x40u
#define USB_ANALOG_USB0_VBUS_DETECT_AVALID_OVERRIDE_SHIFT 6
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK 0x80u
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT 7
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_TO_B_MASK 0x40000u
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_TO_B_SHIFT 18
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
#define USB_ANALOG_USB0_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20
#define USB_ANALOG_USB0_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u
#define USB_ANALOG_USB0_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26
#define USB_ANALOG_USB0_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u
#define USB_ANALOG_USB0_VBUS_DETECT_CHARGE_VBUS_SHIFT 27
#define USB_ANALOG_USB0_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK 0x80000000u
#define USB_ANALOG_USB0_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT 31
/* USB0_CHRG_DETECT Bit Fields */
#define USB_ANALOG_USB0_CHRG_DETECT_FORCE_DETECT_MASK 0x1u
#define USB_ANALOG_USB0_CHRG_DETECT_FORCE_DETECT_SHIFT 0
#define USB_ANALOG_USB0_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u
#define USB_ANALOG_USB0_CHRG_DETECT_CHK_CONTACT_SHIFT 18
#define USB_ANALOG_USB0_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u
#define USB_ANALOG_USB0_CHRG_DETECT_CHK_CHRG_B_SHIFT 19
#define USB_ANALOG_USB0_CHRG_DETECT_EN_B_MASK    0x100000u
#define USB_ANALOG_USB0_CHRG_DETECT_EN_B_SHIFT   20
#define USB_ANALOG_USB0_CHRG_DETECT_CHRG_DET_STATUS_MASK 0x200000u
#define USB_ANALOG_USB0_CHRG_DETECT_CHRG_DET_STATUS_SHIFT 21
#define USB_ANALOG_USB0_CHRG_DETECT_CHRG_DET_CTRL_MASK 0x400000u
#define USB_ANALOG_USB0_CHRG_DETECT_CHRG_DET_CTRL_SHIFT 22
/* USB0_VBUS_DETECT_STATUS Bit Fields */
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_SESSEND_MASK 0x1u
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_SESSEND_SHIFT 0
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_BVALID_MASK 0x2u
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_BVALID_SHIFT 1
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_AVALID_MASK 0x4u
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_AVALID_SHIFT 2
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_VBUS_VALID_MASK 0x8u
#define USB_ANALOG_USB0_VBUS_DETECT_STATUS_VBUS_VALID_SHIFT 3
/* USB0_CHRG_DETECT_STATUS Bit Fields */
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_PLUG_CONTACT_MASK 0x1u
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_PLUG_CONTACT_SHIFT 0
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_CHRG_DETECTED_MASK 0x2u
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_CHRG_DETECTED_SHIFT 1
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_DM_STATE_MASK 0x4u
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_DM_STATE_SHIFT 2
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_DP_STATE_MASK 0x8u
#define USB_ANALOG_USB0_CHRG_DETECT_STATUS_DP_STATE_SHIFT 3
/* USB0_LOOPBACK Bit Fields */
#define USB_ANALOG_USB0_LOOPBACK_UTMI_TESTSTART_MASK 0x1u
#define USB_ANALOG_USB0_LOOPBACK_UTMI_TESTSTART_SHIFT 0
#define USB_ANALOG_USB0_LOOPBACK_UTMI_DIG_TST0_MASK 0x2u
#define USB_ANALOG_USB0_LOOPBACK_UTMI_DIG_TST0_SHIFT 1
#define USB_ANALOG_USB0_LOOPBACK_UTMI_DIG_TST1_MASK 0x4u
#define USB_ANALOG_USB0_LOOPBACK_UTMI_DIG_TST1_SHIFT 2
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_HS_MODE_MASK 0x8u
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_HS_MODE_SHIFT 3
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_LS_MODE_MASK 0x10u
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_LS_MODE_SHIFT 4
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_EN_MASK 0x20u
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_EN_SHIFT 5
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_HIZ_MASK 0x40u
#define USB_ANALOG_USB0_LOOPBACK_TSTI_TX_HIZ_SHIFT 6
#define USB_ANALOG_USB0_LOOPBACK_UTMO_DIG_TST0_MASK 0x80u
#define USB_ANALOG_USB0_LOOPBACK_UTMO_DIG_TST0_SHIFT 7
#define USB_ANALOG_USB0_LOOPBACK_UTMO_DIG_TST1_MASK 0x100u
#define USB_ANALOG_USB0_LOOPBACK_UTMO_DIG_TST1_SHIFT 8
/* USB0_MISC Bit Fields */
#define USB_ANALOG_USB0_MISC_HS_USE_EXTERNAL_R_MASK 0x1u
#define USB_ANALOG_USB0_MISC_HS_USE_EXTERNAL_R_SHIFT 0
#define USB_ANALOG_USB0_MISC_EN_DEGLITCH_MASK    0x2u
#define USB_ANALOG_USB0_MISC_EN_DEGLITCH_SHIFT   1
#define USB_ANALOG_USB0_MISC_EN_CLK_TO_UTMI_MASK 0x40000000u
#define USB_ANALOG_USB0_MISC_EN_CLK_TO_UTMI_SHIFT 30
/* USB1_VBUS_DETECT Bit Fields */
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
#define USB_ANALOG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK 0x8u
#define USB_ANALOG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT 3
#define USB_ANALOG_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK 0x10u
#define USB_ANALOG_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT 4
#define USB_ANALOG_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK 0x20u
#define USB_ANALOG_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT 5
#define USB_ANALOG_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK 0x40u
#define USB_ANALOG_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT 6
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK 0x80u
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT 7
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK 0x40000u
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT 18
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u
#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20
#define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u
#define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26
#define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u
#define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_SHIFT 27
#define USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK 0x80000000u
#define USB_ANALOG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT 31
/* USB1_CHRG_DETECT Bit Fields */
#define USB_ANALOG_USB1_CHRG_DETECT_FORCE_DETECT_MASK 0x1u
#define USB_ANALOG_USB1_CHRG_DETECT_FORCE_DETECT_SHIFT 0
#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u
#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT 18
#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u
#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT 19
#define USB_ANALOG_USB1_CHRG_DETECT_EN_B_MASK    0x100000u
#define USB_ANALOG_USB1_CHRG_DETECT_EN_B_SHIFT   20
#define USB_ANALOG_USB1_CHRG_DETECT_CHRG_DET_STATUS_MASK 0x200000u
#define USB_ANALOG_USB1_CHRG_DETECT_CHRG_DET_STATUS_SHIFT 21
#define USB_ANALOG_USB1_CHRG_DETECT_CHRG_DET_CTRL_MASK 0x400000u
#define USB_ANALOG_USB1_CHRG_DETECT_CHRG_DET_CTRL_SHIFT 22
/* USB1_VBUS_DETECT_STATUS Bit Fields */
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_SESSEND_MASK 0x1u
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_SESSEND_SHIFT 0
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_BVALID_MASK 0x2u
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_BVALID_SHIFT 1
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_AVALID_MASK 0x4u
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_AVALID_SHIFT 2
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_VBUS_VALID_MASK 0x8u
#define USB_ANALOG_USB1_VBUS_DETECT_STATUS_VBUS_VALID_SHIFT 3
/* USB1_CHRG_DETECT_STATUS Bit Fields */
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_PLUG_CONTACT_MASK 0x1u
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_PLUG_CONTACT_SHIFT 0
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_CHRG_DETECTED_MASK 0x2u
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_CHRG_DETECTED_SHIFT 1
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_DM_STATE_MASK 0x4u
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_DM_STATE_SHIFT 2
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_DP_STATE_MASK 0x8u
#define USB_ANALOG_USB1_CHRG_DETECT_STATUS_DP_STATE_SHIFT 3
/* USB1_LOOPBACK Bit Fields */
#define USB_ANALOG_USB1_LOOPBACK_UTMI_TESTSTART_MASK 0x1u
#define USB_ANALOG_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT 0
#define USB_ANALOG_USB1_LOOPBACK_UTMI_DIG_TST0_MASK 0x2u
#define USB_ANALOG_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT 1
#define USB_ANALOG_USB1_LOOPBACK_UTMI_DIG_TST1_MASK 0x4u
#define USB_ANALOG_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT 2
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK 0x8u
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT 3
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK 0x10u
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT 4
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_EN_MASK 0x20u
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_EN_SHIFT 5
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_HIZ_MASK 0x40u
#define USB_ANALOG_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT 6
#define USB_ANALOG_USB1_LOOPBACK_UTM1_DIG_TST0_MASK 0x80u
#define USB_ANALOG_USB1_LOOPBACK_UTM1_DIG_TST0_SHIFT 7
#define USB_ANALOG_USB1_LOOPBACK_UTM1_DIG_TST1_MASK 0x100u
#define USB_ANALOG_USB1_LOOPBACK_UTM1_DIG_TST1_SHIFT 8
/* USB1_MISC Bit Fields */
#define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_MASK 0x1u
#define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_SHIFT 0
#define USB_ANALOG_USB1_MISC_EN_DEGLITCH_MASK    0x2u
#define USB_ANALOG_USB1_MISC_EN_DEGLITCH_SHIFT   1
#define USB_ANALOG_USB1_MISC_EN_CLK_TO_UTMI_MASK 0x40000000u
#define USB_ANALOG_USB1_MISC_EN_CLK_TO_UTMI_SHIFT 30

/**
 * @}
 */ /* end of group USB_ANALOG_Register_Masks */


/* USB_ANALOG - Peripheral instance base addresses */
/** Peripheral USB_ANALOG base address */
#define USB_ANALOG_BASE                          (0x40050000u)
/** Peripheral USB_ANALOG base pointer */
#define USB_ANALOG                               ((USB_ANALOG_Type *)USB_ANALOG_BASE)
/** Array initializer of USB_ANALOG peripheral base pointers */
#define USB_ANALOG_BASES                         { USB_ANALOG }

/**
 * @}
 */ /* end of group USB_ANALOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VDEC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup VDEC_Peripheral_Access_Layer VDEC Peripheral Access Layer
 * @{
 */

/** VDEC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CFC1;                              /**< 2D Comb Filter Control 1, offset: 0x0 */
       uint8_t RESERVED_0[32];
  __IO uint32_t BRSTGT;                            /**< Burst Gate, offset: 0x24 */
       uint8_t RESERVED_1[24];
  __IO uint32_t HZPOS;                             /**< Horizontal Position, offset: 0x40 */
  __IO uint32_t VRTPOS;                            /**< Vertical Position, offset: 0x44 */
       uint8_t RESERVED_2[12];
  __IO uint32_t HVSHFT;                            /**< Output Conditioning and HV Shift, offset: 0x54 */
  __IO uint32_t HSIGS;                             /**< HSync Ignore Start, offset: 0x58 */
  __IO uint32_t HSIGE;                             /**< HSync Ignore End, offset: 0x5C */
  __IO uint32_t VSCON1;                            /**< VSync Control 1, offset: 0x60 */
  __IO uint32_t VSCON2;                            /**< VSync Control 2, offset: 0x64 */
       uint8_t RESERVED_3[4];
  __IO uint32_t YCDEL;                             /**< Y/C Delay and Chroma Debug, offset: 0x6C */
  __IO uint32_t AFTCLP;                            /**< After Clamp, offset: 0x70 */
       uint8_t RESERVED_4[4];
  __IO uint32_t DCOFF;                             /**< DC Offset, offset: 0x78 */
       uint8_t RESERVED_5[8];
  __IO uint32_t CSID;                              /**< Chroma Swap, Invert, and Debug, offset: 0x84 */
  __IO uint32_t CBGN;                              /**< Cb Gain, offset: 0x88 */
  __IO uint32_t CRGN;                              /**< Cr Gain, offset: 0x8C */
  __IO uint32_t CNTR;                              /**< Contrast, offset: 0x90 */
  __IO uint32_t BRT;                               /**< Brightness, offset: 0x94 */
  __IO uint32_t HUE;                               /**< Hue, offset: 0x98 */
  __IO uint32_t CHBTH;                             /**< Chroma Burst Threshold, offset: 0x9C */
       uint8_t RESERVED_6[4];
  __IO uint32_t SHPIMP;                            /**< Sharpness Improvement, offset: 0xA4 */
  __IO uint32_t CHPLLIM;                           /**< Chroma PLL and Input Mode, offset: 0xA8 */
  __I  uint32_t VIDMOD;                            /**< Video Mode, offset: 0xAC */
  __IO uint32_t VIDSTS;                            /**< Video Status, offset: 0xB0 */
  __I  uint32_t NOISE;                             /**< Noise Detector, offset: 0xB4 */
  __IO uint32_t STDDBG;                            /**< Standards and Debug, offset: 0xB8 */
  __IO uint32_t MANOVR;                            /**< Manual Override, offset: 0xBC */
       uint8_t RESERVED_7[8];
  __IO uint32_t VSSGTH;                            /**< VSync and Signal Thresholds, offset: 0xC8 */
       uint8_t RESERVED_8[4];
  __IO uint32_t DBGFBH;                            /**< Debug Framebuffer, offset: 0xD0 */
  __IO uint32_t DBGFBL;                            /**< Debug Framebuffer 2, offset: 0xD4 */
  __IO uint32_t HACTS;                             /**< H Active Start, offset: 0xD8 */
  __IO uint32_t HACTE;                             /**< H Active End, offset: 0xDC */
  __IO uint32_t VACTS;                             /**< V Active Start, offset: 0xE0 */
  __IO uint32_t VACTE;                             /**< V Active End, offset: 0xE4 */
       uint8_t RESERVED_9[4];
  __IO uint32_t HSTIP;                             /**< HSync Tip, offset: 0xEC */
       uint8_t RESERVED_10[8];
  __IO uint32_t BLSCRCR;                           /**< Bluescreen Cr, offset: 0xF8 */
  __IO uint32_t BLSCRCB;                           /**< Bluescreen Cb, offset: 0xFC */
       uint8_t RESERVED_11[4];
  __IO uint32_t LMAGC2;                            /**< Luma AGC Control 2, offset: 0x104 */
       uint8_t RESERVED_12[4];
  __IO uint32_t CHAGC2;                            /**< Chroma AGC Control 2, offset: 0x10C */
       uint8_t RESERVED_13[4];
  __IO uint32_t MINTH;                             /**< Minimum Threshold, offset: 0x114 */
       uint8_t RESERVED_14[4];
  __I  uint32_t VFRQOH;                            /**< Vertical Lines High, offset: 0x11C */
  __I  uint32_t VFRQOL;                            /**< Vertical Lines Low, offset: 0x120 */
} VDEC_Type;

/* ----------------------------------------------------------------------------
   -- VDEC Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup VDEC_Register_Masks VDEC Register Masks
 * @{
 */

/* CFC1 Bit Fields */
#define VDEC_CFC1_rc_combmode_override_MASK      0xFu
#define VDEC_CFC1_rc_combmode_override_SHIFT     0
#define VDEC_CFC1_rc_combmode_override(x)        (((uint32_t)(((uint32_t)(x))<<VDEC_CFC1_rc_combmode_override_SHIFT))&VDEC_CFC1_rc_combmode_override_MASK)
#define VDEC_CFC1_rc_debugout_MASK               0xF0u
#define VDEC_CFC1_rc_debugout_SHIFT              4
#define VDEC_CFC1_rc_debugout(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_CFC1_rc_debugout_SHIFT))&VDEC_CFC1_rc_debugout_MASK)
/* BRSTGT Bit Fields */
#define VDEC_BRSTGT_rc_cburststart_MASK          0xFFu
#define VDEC_BRSTGT_rc_cburststart_SHIFT         0
#define VDEC_BRSTGT_rc_cburststart(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_BRSTGT_rc_cburststart_SHIFT))&VDEC_BRSTGT_rc_cburststart_MASK)
/* HZPOS Bit Fields */
#define VDEC_HZPOS_ro_hpramp_cmp_MASK            0xFFu
#define VDEC_HZPOS_ro_hpramp_cmp_SHIFT           0
#define VDEC_HZPOS_ro_hpramp_cmp(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_HZPOS_ro_hpramp_cmp_SHIFT))&VDEC_HZPOS_ro_hpramp_cmp_MASK)
/* VRTPOS Bit Fields */
#define VDEC_VRTPOS_ro_vline_cmp_MASK            0xFFu
#define VDEC_VRTPOS_ro_vline_cmp_SHIFT           0
#define VDEC_VRTPOS_ro_vline_cmp(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_VRTPOS_ro_vline_cmp_SHIFT))&VDEC_VRTPOS_ro_vline_cmp_MASK)
/* HVSHFT Bit Fields */
#define VDEC_HVSHFT_ro_hzero_sel_MASK            0x1u
#define VDEC_HVSHFT_ro_hzero_sel_SHIFT           0
#define VDEC_HVSHFT_ro_invfield_MASK             0x2u
#define VDEC_HVSHFT_ro_invfield_SHIFT            1
#define VDEC_HVSHFT_ro_vzero_sel_MASK            0x10u
#define VDEC_HVSHFT_ro_vzero_sel_SHIFT           4
#define VDEC_HVSHFT_ro_useactive_MASK            0x20u
#define VDEC_HVSHFT_ro_useactive_SHIFT           5
#define VDEC_HVSHFT_antialias_dis_MASK           0x40u
#define VDEC_HVSHFT_antialias_dis_SHIFT          6
/* HSIGS Bit Fields */
#define VDEC_HSIGS_rv_ignorestart_MASK           0xFFu
#define VDEC_HSIGS_rv_ignorestart_SHIFT          0
#define VDEC_HSIGS_rv_ignorestart(x)             (((uint32_t)(((uint32_t)(x))<<VDEC_HSIGS_rv_ignorestart_SHIFT))&VDEC_HSIGS_rv_ignorestart_MASK)
/* HSIGE Bit Fields */
#define VDEC_HSIGE_rv_ignoreend_MASK             0xFFu
#define VDEC_HSIGE_rv_ignoreend_SHIFT            0
#define VDEC_HSIGE_rv_ignoreend(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_HSIGE_rv_ignoreend_SHIFT))&VDEC_HSIGE_rv_ignoreend_MASK)
/* VSCON1 Bit Fields */
#define VDEC_VSCON1_rh_vdet_dbg_MASK             0x7u
#define VDEC_VSCON1_rh_vdet_dbg_SHIFT            0
#define VDEC_VSCON1_rh_vdet_dbg(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON1_rh_vdet_dbg_SHIFT))&VDEC_VSCON1_rh_vdet_dbg_MASK)
#define VDEC_VSCON1_rh_robust625det_MASK         0x8u
#define VDEC_VSCON1_rh_robust625det_SHIFT        3
#define VDEC_VSCON1_rh_dis_vsyncdetect_MASK      0x10u
#define VDEC_VSCON1_rh_dis_vsyncdetect_SHIFT     4
#define VDEC_VSCON1_rh_vsynchalfmode_MASK        0x20u
#define VDEC_VSCON1_rh_vsynchalfmode_SHIFT       5
#define VDEC_VSCON1_rh_modadd_dis_MASK           0x40u
#define VDEC_VSCON1_rh_modadd_dis_SHIFT          6
#define VDEC_VSCON1_rh_8or16_MASK                0x80u
#define VDEC_VSCON1_rh_8or16_SHIFT               7
/* VSCON2 Bit Fields */
#define VDEC_VSCON2_rh_vcr_phasethr_MASK         0x3u
#define VDEC_VSCON2_rh_vcr_phasethr_SHIFT        0
#define VDEC_VSCON2_rh_vcr_phasethr(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_vcr_phasethr_SHIFT))&VDEC_VSCON2_rh_vcr_phasethr_MASK)
#define VDEC_VSCON2_rh_vcr_force_dis_MASK        0xCu
#define VDEC_VSCON2_rh_vcr_force_dis_SHIFT       2
#define VDEC_VSCON2_rh_vcr_force_dis(x)          (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_vcr_force_dis_SHIFT))&VDEC_VSCON2_rh_vcr_force_dis_MASK)
#define VDEC_VSCON2_rh_hsw_coring_MASK           0x30u
#define VDEC_VSCON2_rh_hsw_coring_SHIFT          4
#define VDEC_VSCON2_rh_hsw_coring(x)             (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_hsw_coring_SHIFT))&VDEC_VSCON2_rh_hsw_coring_MASK)
#define VDEC_VSCON2_rh_smooth_hsw_MASK           0x40u
#define VDEC_VSCON2_rh_smooth_hsw_SHIFT          6
#define VDEC_VSCON2_rh_disable_hsw_MASK          0x80u
#define VDEC_VSCON2_rh_disable_hsw_SHIFT         7
/* YCDEL Bit Fields */
#define VDEC_YCDEL_rd_nopalave_MASK              0x1u
#define VDEC_YCDEL_rd_nopalave_SHIFT             0
#define VDEC_YCDEL_rd_narrow_MASK                0x2u
#define VDEC_YCDEL_rd_narrow_SHIFT               1
#define VDEC_YCDEL_rd_wide_MASK                  0x4u
#define VDEC_YCDEL_rd_wide_SHIFT                 2
#define VDEC_YCDEL_rd_lumadel_MASK               0xF0u
#define VDEC_YCDEL_rd_lumadel_SHIFT              4
#define VDEC_YCDEL_rd_lumadel(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_YCDEL_rd_lumadel_SHIFT))&VDEC_YCDEL_rd_lumadel_MASK)
/* AFTCLP Bit Fields */
#define VDEC_AFTCLP_rh_shortframe_MASK           0x1u
#define VDEC_AFTCLP_rh_shortframe_SHIFT          0
#define VDEC_AFTCLP_rl_disoffset_MASK            0x2u
#define VDEC_AFTCLP_rl_disoffset_SHIFT           1
#define VDEC_AFTCLP_rl_resetoffset_MASK          0x4u
#define VDEC_AFTCLP_rl_resetoffset_SHIFT         2
#define VDEC_AFTCLP_rc_afterclamp_update_en_MASK 0x10u
#define VDEC_AFTCLP_rc_afterclamp_update_en_SHIFT 4
#define VDEC_AFTCLP_rc_midfield_dis_MASK         0x20u
#define VDEC_AFTCLP_rc_midfield_dis_SHIFT        5
#define VDEC_AFTCLP_rc_aoutoafterclamp_dis_MASK  0x40u
#define VDEC_AFTCLP_rc_aoutoafterclamp_dis_SHIFT 6
/* DCOFF Bit Fields */
#define VDEC_DCOFF_rl_dcoffsetI_MASK             0x3u
#define VDEC_DCOFF_rl_dcoffsetI_SHIFT            0
#define VDEC_DCOFF_rl_dcoffsetI(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_DCOFF_rl_dcoffsetI_SHIFT))&VDEC_DCOFF_rl_dcoffsetI_MASK)
#define VDEC_DCOFF_rl_linemeasure_dis_MASK       0x8u
#define VDEC_DCOFF_rl_linemeasure_dis_SHIFT      3
#define VDEC_DCOFF_rl_dcoffsetP_MASK             0x70u
#define VDEC_DCOFF_rl_dcoffsetP_SHIFT            4
#define VDEC_DCOFF_rl_dcoffsetP(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_DCOFF_rl_dcoffsetP_SHIFT))&VDEC_DCOFF_rl_dcoffsetP_MASK)
/* CSID Bit Fields */
#define VDEC_CSID_rd_swapcrcb_MASK               0x1u
#define VDEC_CSID_rd_swapcrcb_SHIFT              0
#define VDEC_CSID_rd_invcr_MASK                  0x2u
#define VDEC_CSID_rd_invcr_SHIFT                 1
#define VDEC_CSID_rd_invcb_MASK                  0x4u
#define VDEC_CSID_rd_invcb_SHIFT                 2
#define VDEC_CSID_rd_nopalhue_MASK               0x8u
#define VDEC_CSID_rd_nopalhue_SHIFT              3
#define VDEC_CSID_rd_bypasshilbert_MASK          0x80u
#define VDEC_CSID_rd_bypasshilbert_SHIFT         7
/* CBGN Bit Fields */
#define VDEC_CBGN_rd_cbgain_MASK                 0xFFu
#define VDEC_CBGN_rd_cbgain_SHIFT                0
#define VDEC_CBGN_rd_cbgain(x)                   (((uint32_t)(((uint32_t)(x))<<VDEC_CBGN_rd_cbgain_SHIFT))&VDEC_CBGN_rd_cbgain_MASK)
/* CRGN Bit Fields */
#define VDEC_CRGN_rd_crgain_MASK                 0xFFu
#define VDEC_CRGN_rd_crgain_SHIFT                0
#define VDEC_CRGN_rd_crgain(x)                   (((uint32_t)(((uint32_t)(x))<<VDEC_CRGN_rd_crgain_SHIFT))&VDEC_CRGN_rd_crgain_MASK)
/* CNTR Bit Fields */
#define VDEC_CNTR_rd_lumagain_MASK               0xFFu
#define VDEC_CNTR_rd_lumagain_SHIFT              0
#define VDEC_CNTR_rd_lumagain(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_CNTR_rd_lumagain_SHIFT))&VDEC_CNTR_rd_lumagain_MASK)
/* BRT Bit Fields */
#define VDEC_BRT_rc_blacklevel_MASK              0xFFu
#define VDEC_BRT_rc_blacklevel_SHIFT             0
#define VDEC_BRT_rc_blacklevel(x)                (((uint32_t)(((uint32_t)(x))<<VDEC_BRT_rc_blacklevel_SHIFT))&VDEC_BRT_rc_blacklevel_MASK)
/* HUE Bit Fields */
#define VDEC_HUE_rd_ch_thresh_MASK               0xFFu
#define VDEC_HUE_rd_ch_thresh_SHIFT              0
#define VDEC_HUE_rd_ch_thresh(x)                 (((uint32_t)(((uint32_t)(x))<<VDEC_HUE_rd_ch_thresh_SHIFT))&VDEC_HUE_rd_ch_thresh_MASK)
/* CHBTH Bit Fields */
#define VDEC_CHBTH_rd_ch_thresh_MASK             0xFFu
#define VDEC_CHBTH_rd_ch_thresh_SHIFT            0
#define VDEC_CHBTH_rd_ch_thresh(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_CHBTH_rd_ch_thresh_SHIFT))&VDEC_CHBTH_rd_ch_thresh_MASK)
/* SHPIMP Bit Fields */
#define VDEC_SHPIMP_rd_peak_MASK                 0xFu
#define VDEC_SHPIMP_rd_peak_SHIFT                0
#define VDEC_SHPIMP_rd_peak(x)                   (((uint32_t)(((uint32_t)(x))<<VDEC_SHPIMP_rd_peak_SHIFT))&VDEC_SHPIMP_rd_peak_MASK)
#define VDEC_SHPIMP_rd_slope_MASK                0xF0u
#define VDEC_SHPIMP_rd_slope_SHIFT               4
#define VDEC_SHPIMP_rd_slope(x)                  (((uint32_t)(((uint32_t)(x))<<VDEC_SHPIMP_rd_slope_SHIFT))&VDEC_SHPIMP_rd_slope_MASK)
/* CHPLLIM Bit Fields */
#define VDEC_CHPLLIM_rd_inputcables_MASK         0x7u
#define VDEC_CHPLLIM_rd_inputcables_SHIFT        0
#define VDEC_CHPLLIM_rd_inputcables(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_CHPLLIM_rd_inputcables_SHIFT))&VDEC_CHPLLIM_rd_inputcables_MASK)
#define VDEC_CHPLLIM_rd_locked_force_MASK        0x8u
#define VDEC_CHPLLIM_rd_locked_force_SHIFT       3
#define VDEC_CHPLLIM_rd_chlock_atten_MASK        0x70u
#define VDEC_CHPLLIM_rd_chlock_atten_SHIFT       4
#define VDEC_CHPLLIM_rd_chlock_atten(x)          (((uint32_t)(((uint32_t)(x))<<VDEC_CHPLLIM_rd_chlock_atten_SHIFT))&VDEC_CHPLLIM_rd_chlock_atten_MASK)
/* VIDMOD Bit Fields */
#define VDEC_VIDMOD_havesignal_MASK              0x1u
#define VDEC_VIDMOD_havesignal_SHIFT             0
#define VDEC_VIDMOD_Hlocked_MASK                 0x2u
#define VDEC_VIDMOD_Hlocked_SHIFT                1
#define VDEC_VIDMOD_chroma_MASK                  0x4u
#define VDEC_VIDMOD_chroma_SHIFT                 2
#define VDEC_VIDMOD_ch_locked_MASK               0x8u
#define VDEC_VIDMOD_ch_locked_SHIFT              3
#define VDEC_VIDMOD_m625_MASK                    0x10u
#define VDEC_VIDMOD_m625_SHIFT                   4
#define VDEC_VIDMOD_Secam_MASK                   0x20u
#define VDEC_VIDMOD_Secam_SHIFT                  5
#define VDEC_VIDMOD_F443_MASK                    0x40u
#define VDEC_VIDMOD_F443_SHIFT                   6
#define VDEC_VIDMOD_Pal_MASK                     0x80u
#define VDEC_VIDMOD_Pal_SHIFT                    7
/* VIDSTS Bit Fields */
#define VDEC_VIDSTS_Nonarith_MASK                0x1u
#define VDEC_VIDSTS_Nonarith_SHIFT               0
#define VDEC_VIDSTS_Nonarith3D_MASK              0x2u
#define VDEC_VIDSTS_Nonarith3D_SHIFT             1
#define VDEC_VIDSTS_Vcrdetect_MASK               0x4u
#define VDEC_VIDSTS_Vcrdetect_SHIFT              2
/* NOISE Bit Fields */
#define VDEC_NOISE_Noise_MASK                    0xFFu
#define VDEC_NOISE_Noise_SHIFT                   0
#define VDEC_NOISE_Noise(x)                      (((uint32_t)(((uint32_t)(x))<<VDEC_NOISE_Noise_SHIFT))&VDEC_NOISE_Noise_MASK)
/* STDDBG Bit Fields */
#define VDEC_STDDBG_standard_filter_MASK         0x3u
#define VDEC_STDDBG_standard_filter_SHIFT        0
#define VDEC_STDDBG_standard_filter(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_STDDBG_standard_filter_SHIFT))&VDEC_STDDBG_standard_filter_MASK)
#define VDEC_STDDBG_force_havesignal_MASK        0x8u
#define VDEC_STDDBG_force_havesignal_SHIFT       3
#define VDEC_STDDBG_force_2dntsc443_MASK         0x20u
#define VDEC_STDDBG_force_2dntsc443_SHIFT        5
#define VDEC_STDDBG_ntscj_MASK                   0x40u
#define VDEC_STDDBG_ntscj_SHIFT                  6
#define VDEC_STDDBG_rd_fc_maual_MASK             0x80u
#define VDEC_STDDBG_rd_fc_maual_SHIFT            7
/* MANOVR Bit Fields */
#define VDEC_MANOVR_manual_625_MASK              0x1u
#define VDEC_MANOVR_manual_625_SHIFT             0
#define VDEC_MANOVR_secam_manual_MASK            0x2u
#define VDEC_MANOVR_secam_manual_SHIFT           1
#define VDEC_MANOVR_four43_manual_MASK           0x4u
#define VDEC_MANOVR_four43_manual_SHIFT          2
#define VDEC_MANOVR_pal_manual_MASK              0x8u
#define VDEC_MANOVR_pal_manual_SHIFT             3
#define VDEC_MANOVR_line625_override_MASK        0x10u
#define VDEC_MANOVR_line625_override_SHIFT       4
#define VDEC_MANOVR_secam_override_MASK          0x20u
#define VDEC_MANOVR_secam_override_SHIFT         5
#define VDEC_MANOVR_f443_override_MASK           0x40u
#define VDEC_MANOVR_f443_override_SHIFT          6
#define VDEC_MANOVR_pal_override_MASK            0x80u
#define VDEC_MANOVR_pal_override_SHIFT           7
/* VSSGTH Bit Fields */
#define VDEC_VSSGTH_nosigthresh_MASK             0x7u
#define VDEC_VSSGTH_nosigthresh_SHIFT            0
#define VDEC_VSSGTH_nosigthresh(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_VSSGTH_nosigthresh_SHIFT))&VDEC_VSSGTH_nosigthresh_MASK)
#define VDEC_VSSGTH_rh_vsynclength_MASK          0xF0u
#define VDEC_VSSGTH_rh_vsynclength_SHIFT         4
#define VDEC_VSSGTH_rh_vsynclength(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_VSSGTH_rh_vsynclength_SHIFT))&VDEC_VSSGTH_rh_vsynclength_MASK)
/* DBGFBH Bit Fields */
#define VDEC_DBGFBH_clamp_delayH_MASK            0x3u
#define VDEC_DBGFBH_clamp_delayH_SHIFT           0
#define VDEC_DBGFBH_clamp_delayH(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_DBGFBH_clamp_delayH_SHIFT))&VDEC_DBGFBH_clamp_delayH_MASK)
/* DBGFBL Bit Fields */
#define VDEC_DBGFBL_clamp_delayL_MASK            0xFFu
#define VDEC_DBGFBL_clamp_delayL_SHIFT           0
#define VDEC_DBGFBL_clamp_delayL(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_DBGFBL_clamp_delayL_SHIFT))&VDEC_DBGFBL_clamp_delayL_MASK)
/* HACTS Bit Fields */
#define VDEC_HACTS_ro_hactivestart_MASK          0xFFu
#define VDEC_HACTS_ro_hactivestart_SHIFT         0
#define VDEC_HACTS_ro_hactivestart(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_HACTS_ro_hactivestart_SHIFT))&VDEC_HACTS_ro_hactivestart_MASK)
/* HACTE Bit Fields */
#define VDEC_HACTE_ro_hactiveend_MASK            0xFFu
#define VDEC_HACTE_ro_hactiveend_SHIFT           0
#define VDEC_HACTE_ro_hactiveend(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_HACTE_ro_hactiveend_SHIFT))&VDEC_HACTE_ro_hactiveend_MASK)
/* VACTS Bit Fields */
#define VDEC_VACTS_ro_vactivestart_MASK          0xFFu
#define VDEC_VACTS_ro_vactivestart_SHIFT         0
#define VDEC_VACTS_ro_vactivestart(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_VACTS_ro_vactivestart_SHIFT))&VDEC_VACTS_ro_vactivestart_MASK)
/* VACTE Bit Fields */
#define VDEC_VACTE_ro_vactiveend_MASK            0xFFu
#define VDEC_VACTE_ro_vactiveend_SHIFT           0
#define VDEC_VACTE_ro_vactiveend(x)              (((uint32_t)(((uint32_t)(x))<<VDEC_VACTE_ro_vactiveend_SHIFT))&VDEC_VACTE_ro_vactiveend_MASK)
/* HSTIP Bit Fields */
#define VDEC_HSTIP_rh_tipgate_start_MASK         0xFFu
#define VDEC_HSTIP_rh_tipgate_start_SHIFT        0
#define VDEC_HSTIP_rh_tipgate_start(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_HSTIP_rh_tipgate_start_SHIFT))&VDEC_HSTIP_rh_tipgate_start_MASK)
/* BLSCRCR Bit Fields */
#define VDEC_BLSCRCR_bluescreen_y_MASK           0xFFu
#define VDEC_BLSCRCR_bluescreen_y_SHIFT          0
#define VDEC_BLSCRCR_bluescreen_y(x)             (((uint32_t)(((uint32_t)(x))<<VDEC_BLSCRCR_bluescreen_y_SHIFT))&VDEC_BLSCRCR_bluescreen_y_MASK)
/* BLSCRCB Bit Fields */
#define VDEC_BLSCRCB_bluescreen_cb_MASK          0xFFu
#define VDEC_BLSCRCB_bluescreen_cb_SHIFT         0
#define VDEC_BLSCRCB_bluescreen_cb(x)            (((uint32_t)(((uint32_t)(x))<<VDEC_BLSCRCB_bluescreen_cb_SHIFT))&VDEC_BLSCRCB_bluescreen_cb_MASK)
/* LMAGC2 Bit Fields */
#define VDEC_LMAGC2_ragc_target_MASK             0xFFu
#define VDEC_LMAGC2_ragc_target_SHIFT            0
#define VDEC_LMAGC2_ragc_target(x)               (((uint32_t)(((uint32_t)(x))<<VDEC_LMAGC2_ragc_target_SHIFT))&VDEC_LMAGC2_ragc_target_MASK)
/* CHAGC2 Bit Fields */
#define VDEC_CHAGC2_rd_chagc_target_MASK         0xFFu
#define VDEC_CHAGC2_rd_chagc_target_SHIFT        0
#define VDEC_CHAGC2_rd_chagc_target(x)           (((uint32_t)(((uint32_t)(x))<<VDEC_CHAGC2_rd_chagc_target_SHIFT))&VDEC_CHAGC2_rd_chagc_target_MASK)
/* MINTH Bit Fields */
#define VDEC_MINTH_minthresh_MASK                0xFFu
#define VDEC_MINTH_minthresh_SHIFT               0
#define VDEC_MINTH_minthresh(x)                  (((uint32_t)(((uint32_t)(x))<<VDEC_MINTH_minthresh_SHIFT))&VDEC_MINTH_minthresh_MASK)
/* VFRQOH Bit Fields */
#define VDEC_VFRQOH_vfreqo_MASK                  0xFu
#define VDEC_VFRQOH_vfreqo_SHIFT                 0
#define VDEC_VFRQOH_vfreqo(x)                    (((uint32_t)(((uint32_t)(x))<<VDEC_VFRQOH_vfreqo_SHIFT))&VDEC_VFRQOH_vfreqo_MASK)
/* VFRQOL Bit Fields */
#define VDEC_VFRQOL_vfreqo_MASK                  0xFFu
#define VDEC_VFRQOL_vfreqo_SHIFT                 0
#define VDEC_VFRQOL_vfreqo(x)                    (((uint32_t)(((uint32_t)(x))<<VDEC_VFRQOL_vfreqo_SHIFT))&VDEC_VFRQOL_vfreqo_MASK)

/**
 * @}
 */ /* end of group VDEC_Register_Masks */


/* VDEC - Peripheral instance base addresses */
/** Peripheral VDEC base address */
#define VDEC_BASE                                (0x400C8000u)
/** Peripheral VDEC base pointer */
#define VDEC                                     ((VDEC_Type *)VDEC_BASE)
/** Array initializer of VDEC peripheral base pointers */
#define VDEC_BASES                               { VDEC }

/**
 * @}
 */ /* end of group VDEC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VIU3 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup VIU3_Peripheral_Access_Layer VIU3 Peripheral Access Layer
 * @{
 */

/** VIU3 - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCR;                               /**< Status And Configuration Register, offset: 0x0 */
  __IO uint32_t LUMA_COMP;                         /**< Luminance Coefficients For Red, Green And Blue Matrix, offset: 0x4 */
  __IO uint32_t CHROMA_RED;                        /**< Chroma Coefficients For Red Matrix, offset: 0x8 */
  __IO uint32_t CHROMA_GREEN;                      /**< Chroma Coefficients For Green Matrix, offset: 0xC */
  __IO uint32_t CHROMA_BLUE;                       /**< Chroma Coefficients For Blue Matrix, offset: 0x10 */
  __IO uint32_t DMA_ADDR;                          /**< Base Address Of Every Field/Frame Of Picture In Memory, offset: 0x14 */
  __IO uint32_t DMA_INC;                           /**< Horizontal DMA Increment, offset: 0x18 */
  __IO uint32_t INVSZ;                             /**< Input Video Pixel and Line Count, offset: 0x1C */
  __IO uint32_t HPRALRM;                           /**< High IPM Request Priority Alarm, offset: 0x20 */
  __IO uint32_t ALPHA;                             /**< Programable Alpha Value, offset: 0x24 */
  __IO uint32_t HFACTOR;                           /**< Down Scaling Factor In Horizontal Direction, offset: 0x28 */
  __IO uint32_t VFACTOR;                           /**< Down Scaling Factor In Vertical Direction, offset: 0x2C */
  __IO uint32_t VID_SIZE;                          /**< Down Scaling Destination Pixel and Line Count, offset: 0x30 */
  __IO uint32_t LUT_ADDR;                          /**< B/C Adjust Look-up-table Current Address, offset: 0x34 */
  __IO uint32_t LUT_DATA;                          /**< B/C Adjust Look-up-table Data Entry, offset: 0x38 */
  __IO uint32_t EXT_CONFIG;                        /**< Extended Configuration Register, offset: 0x3C */
  __IO uint32_t RGB_Y;                             /**< Red, Green and Blue Coefficients for Luminance component, offset: 0x40 */
  __IO uint32_t RGB_U;                             /**< Red, Green and Blue Coefficients for Chroma U component, offset: 0x44 */
  __IO uint32_t RGB_V;                             /**< Red, Green and Blue Coefficients for Chroma V component, offset: 0x48 */
} VIU3_Type;

/* ----------------------------------------------------------------------------
   -- VIU3 Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup VIU3_Register_Masks VIU3 Register Masks
 * @{
 */

/* SCR Bit Fields */
#define VIU3_SCR_SOFT_RESET_MASK                 0x1u
#define VIU3_SCR_SOFT_RESET_SHIFT                0
#define VIU3_SCR_FORMAT_CTRL_MASK                0xEu
#define VIU3_SCR_FORMAT_CTRL_SHIFT               1
#define VIU3_SCR_FORMAT_CTRL(x)                  (((uint32_t)(((uint32_t)(x))<<VIU3_SCR_FORMAT_CTRL_SHIFT))&VIU3_SCR_FORMAT_CTRL_MASK)
#define VIU3_SCR_ERROR_CODE_MASK                 0xF0u
#define VIU3_SCR_ERROR_CODE_SHIFT                4
#define VIU3_SCR_ERROR_CODE(x)                   (((uint32_t)(((uint32_t)(x))<<VIU3_SCR_ERROR_CODE_SHIFT))&VIU3_SCR_ERROR_CODE_MASK)
#define VIU3_SCR_FIELD_EN_MASK                   0x100u
#define VIU3_SCR_FIELD_EN_SHIFT                  8
#define VIU3_SCR_VSYNC_EN_MASK                   0x200u
#define VIU3_SCR_VSYNC_EN_SHIFT                  9
#define VIU3_SCR_HSYNC_EN_MASK                   0x400u
#define VIU3_SCR_HSYNC_EN_SHIFT                  10
#define VIU3_SCR_VSTART_EN_MASK                  0x800u
#define VIU3_SCR_VSTART_EN_SHIFT                 11
#define VIU3_SCR_DMA_END_EN_MASK                 0x1000u
#define VIU3_SCR_DMA_END_EN_SHIFT                12
#define VIU3_SCR_ERROR_EN_MASK                   0x2000u
#define VIU3_SCR_ERROR_EN_SHIFT                  13
#define VIU3_SCR_ECC_EN_MASK                     0x4000u
#define VIU3_SCR_ECC_EN_SHIFT                    14
#define VIU3_SCR_FIELD_IRQ_MASK                  0x10000u
#define VIU3_SCR_FIELD_IRQ_SHIFT                 16
#define VIU3_SCR_VSYNC_IRQ_MASK                  0x20000u
#define VIU3_SCR_VSYNC_IRQ_SHIFT                 17
#define VIU3_SCR_HSYNC_IRQ_MASK                  0x40000u
#define VIU3_SCR_HSYNC_IRQ_SHIFT                 18
#define VIU3_SCR_VSTART_IRQ_MASK                 0x80000u
#define VIU3_SCR_VSTART_IRQ_SHIFT                19
#define VIU3_SCR_DMA_END_IRQ_MASK                0x100000u
#define VIU3_SCR_DMA_END_IRQ_SHIFT               20
#define VIU3_SCR_ERROR_IRQ_MASK                  0x200000u
#define VIU3_SCR_ERROR_IRQ_SHIFT                 21
#define VIU3_SCR_MODE444_MASK                    0x800000u
#define VIU3_SCR_MODE444_SHIFT                   23
#define VIU3_SCR_BC_EN_MASK                      0x1000000u
#define VIU3_SCR_BC_EN_SHIFT                     24
#define VIU3_SCR_YUV2RGB_EN_MASK                 0x2000000u
#define VIU3_SCR_YUV2RGB_EN_SHIFT                25
#define VIU3_SCR_SCALER_EN_MASK                  0x4000000u
#define VIU3_SCR_SCALER_EN_SHIFT                 26
#define VIU3_SCR_DMA_ACT_MASK                    0x8000000u
#define VIU3_SCR_DMA_ACT_SHIFT                   27
#define VIU3_SCR_FIELD_NO_MASK                   0x10000000u
#define VIU3_SCR_FIELD_NO_SHIFT                  28
#define VIU3_SCR_DITHER_ON_MASK                  0x20000000u
#define VIU3_SCR_DITHER_ON_SHIFT                 29
#define VIU3_SCR_ROUND_ON_MASK                   0x40000000u
#define VIU3_SCR_ROUND_ON_SHIFT                  30
#define VIU3_SCR_MODE32BIT_MASK                  0x80000000u
#define VIU3_SCR_MODE32BIT_SHIFT                 31
/* LUMA_COMP Bit Fields */
#define VIU3_LUMA_COMP_Y_BLUE_MASK               0x3FFu
#define VIU3_LUMA_COMP_Y_BLUE_SHIFT              0
#define VIU3_LUMA_COMP_Y_BLUE(x)                 (((uint32_t)(((uint32_t)(x))<<VIU3_LUMA_COMP_Y_BLUE_SHIFT))&VIU3_LUMA_COMP_Y_BLUE_MASK)
#define VIU3_LUMA_COMP_Y_GREEN_MASK              0x1FF800u
#define VIU3_LUMA_COMP_Y_GREEN_SHIFT             11
#define VIU3_LUMA_COMP_Y_GREEN(x)                (((uint32_t)(((uint32_t)(x))<<VIU3_LUMA_COMP_Y_GREEN_SHIFT))&VIU3_LUMA_COMP_Y_GREEN_MASK)
#define VIU3_LUMA_COMP_Y_RED_MASK                0xFFC00000u
#define VIU3_LUMA_COMP_Y_RED_SHIFT               22
#define VIU3_LUMA_COMP_Y_RED(x)                  (((uint32_t)(((uint32_t)(x))<<VIU3_LUMA_COMP_Y_RED_SHIFT))&VIU3_LUMA_COMP_Y_RED_MASK)
/* CHROMA_RED Bit Fields */
#define VIU3_CHROMA_RED_CB_RED_MASK              0xFFFu
#define VIU3_CHROMA_RED_CB_RED_SHIFT             0
#define VIU3_CHROMA_RED_CB_RED(x)                (((uint32_t)(((uint32_t)(x))<<VIU3_CHROMA_RED_CB_RED_SHIFT))&VIU3_CHROMA_RED_CB_RED_MASK)
#define VIU3_CHROMA_RED_CR_RED_MASK              0x7FF0000u
#define VIU3_CHROMA_RED_CR_RED_SHIFT             16
#define VIU3_CHROMA_RED_CR_RED(x)                (((uint32_t)(((uint32_t)(x))<<VIU3_CHROMA_RED_CR_RED_SHIFT))&VIU3_CHROMA_RED_CR_RED_MASK)
/* CHROMA_GREEN Bit Fields */
#define VIU3_CHROMA_GREEN_CB_GREEN_MASK          0xFFFu
#define VIU3_CHROMA_GREEN_CB_GREEN_SHIFT         0
#define VIU3_CHROMA_GREEN_CB_GREEN(x)            (((uint32_t)(((uint32_t)(x))<<VIU3_CHROMA_GREEN_CB_GREEN_SHIFT))&VIU3_CHROMA_GREEN_CB_GREEN_MASK)
#define VIU3_CHROMA_GREEN_CR_GREEN_MASK          0x7FF0000u
#define VIU3_CHROMA_GREEN_CR_GREEN_SHIFT         16
#define VIU3_CHROMA_GREEN_CR_GREEN(x)            (((uint32_t)(((uint32_t)(x))<<VIU3_CHROMA_GREEN_CR_GREEN_SHIFT))&VIU3_CHROMA_GREEN_CR_GREEN_MASK)
/* CHROMA_BLUE Bit Fields */
#define VIU3_CHROMA_BLUE_CB_BLUE_MASK            0xFFFu
#define VIU3_CHROMA_BLUE_CB_BLUE_SHIFT           0
#define VIU3_CHROMA_BLUE_CB_BLUE(x)              (((uint32_t)(((uint32_t)(x))<<VIU3_CHROMA_BLUE_CB_BLUE_SHIFT))&VIU3_CHROMA_BLUE_CB_BLUE_MASK)
#define VIU3_CHROMA_BLUE_CR_BLUE_MASK            0x7FF0000u
#define VIU3_CHROMA_BLUE_CR_BLUE_SHIFT           16
#define VIU3_CHROMA_BLUE_CR_BLUE(x)              (((uint32_t)(((uint32_t)(x))<<VIU3_CHROMA_BLUE_CR_BLUE_SHIFT))&VIU3_CHROMA_BLUE_CR_BLUE_MASK)
/* DMA_ADDR Bit Fields */
#define VIU3_DMA_ADDR_ADDR_MASK                  0xFFFFFFF8u
#define VIU3_DMA_ADDR_ADDR_SHIFT                 3
#define VIU3_DMA_ADDR_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<VIU3_DMA_ADDR_ADDR_SHIFT))&VIU3_DMA_ADDR_ADDR_MASK)
/* DMA_INC Bit Fields */
#define VIU3_DMA_INC_INC_MASK                    0xFFF8u
#define VIU3_DMA_INC_INC_SHIFT                   3
#define VIU3_DMA_INC_INC(x)                      (((uint32_t)(((uint32_t)(x))<<VIU3_DMA_INC_INC_SHIFT))&VIU3_DMA_INC_INC_MASK)
/* INVSZ Bit Fields */
#define VIU3_INVSZ_PIXELC_MASK                   0xFFFFu
#define VIU3_INVSZ_PIXELC_SHIFT                  0
#define VIU3_INVSZ_PIXELC(x)                     (((uint32_t)(((uint32_t)(x))<<VIU3_INVSZ_PIXELC_SHIFT))&VIU3_INVSZ_PIXELC_MASK)
#define VIU3_INVSZ_LINEC_MASK                    0xFFFF0000u
#define VIU3_INVSZ_LINEC_SHIFT                   16
#define VIU3_INVSZ_LINEC(x)                      (((uint32_t)(((uint32_t)(x))<<VIU3_INVSZ_LINEC_SHIFT))&VIU3_INVSZ_LINEC_MASK)
/* HPRALRM Bit Fields */
#define VIU3_HPRALRM_ALARM_MASK                  0xFFu
#define VIU3_HPRALRM_ALARM_SHIFT                 0
#define VIU3_HPRALRM_ALARM(x)                    (((uint32_t)(((uint32_t)(x))<<VIU3_HPRALRM_ALARM_SHIFT))&VIU3_HPRALRM_ALARM_MASK)
/* ALPHA Bit Fields */
#define VIU3_ALPHA_ALPHA_MASK                    0xFFu
#define VIU3_ALPHA_ALPHA_SHIFT                   0
#define VIU3_ALPHA_ALPHA(x)                      (((uint32_t)(((uint32_t)(x))<<VIU3_ALPHA_ALPHA_SHIFT))&VIU3_ALPHA_ALPHA_MASK)
/* HFACTOR Bit Fields */
#define VIU3_HFACTOR_FACTOR_MASK                 0x7FFu
#define VIU3_HFACTOR_FACTOR_SHIFT                0
#define VIU3_HFACTOR_FACTOR(x)                   (((uint32_t)(((uint32_t)(x))<<VIU3_HFACTOR_FACTOR_SHIFT))&VIU3_HFACTOR_FACTOR_MASK)
/* VFACTOR Bit Fields */
#define VIU3_VFACTOR_FACTOR_MASK                 0x7FFu
#define VIU3_VFACTOR_FACTOR_SHIFT                0
#define VIU3_VFACTOR_FACTOR(x)                   (((uint32_t)(((uint32_t)(x))<<VIU3_VFACTOR_FACTOR_SHIFT))&VIU3_VFACTOR_FACTOR_MASK)
/* VID_SIZE Bit Fields */
#define VIU3_VID_SIZE_PIXELC_MASK                0xFFFFu
#define VIU3_VID_SIZE_PIXELC_SHIFT               0
#define VIU3_VID_SIZE_PIXELC(x)                  (((uint32_t)(((uint32_t)(x))<<VIU3_VID_SIZE_PIXELC_SHIFT))&VIU3_VID_SIZE_PIXELC_MASK)
#define VIU3_VID_SIZE_LINEC_MASK                 0xFFFF0000u
#define VIU3_VID_SIZE_LINEC_SHIFT                16
#define VIU3_VID_SIZE_LINEC(x)                   (((uint32_t)(((uint32_t)(x))<<VIU3_VID_SIZE_LINEC_SHIFT))&VIU3_VID_SIZE_LINEC_MASK)
/* LUT_ADDR Bit Fields */
#define VIU3_LUT_ADDR_ADDR_MASK                  0x3FCu
#define VIU3_LUT_ADDR_ADDR_SHIFT                 2
#define VIU3_LUT_ADDR_ADDR(x)                    (((uint32_t)(((uint32_t)(x))<<VIU3_LUT_ADDR_ADDR_SHIFT))&VIU3_LUT_ADDR_ADDR_MASK)
/* LUT_DATA Bit Fields */
#define VIU3_LUT_DATA_DATA_MASK                  0xFFFFFFFFu
#define VIU3_LUT_DATA_DATA_SHIFT                 0
#define VIU3_LUT_DATA_DATA(x)                    (((uint32_t)(((uint32_t)(x))<<VIU3_LUT_DATA_DATA_SHIFT))&VIU3_LUT_DATA_DATA_MASK)
/* EXT_CONFIG Bit Fields */
#define VIU3_EXT_CONFIG_HMIRROR_EN_MASK          0x1u
#define VIU3_EXT_CONFIG_HMIRROR_EN_SHIFT         0
#define VIU3_EXT_CONFIG_DE_POL_MASK              0x2u
#define VIU3_EXT_CONFIG_DE_POL_SHIFT             1
#define VIU3_EXT_CONFIG_HSYNC_POL_MASK           0x4u
#define VIU3_EXT_CONFIG_HSYNC_POL_SHIFT          2
#define VIU3_EXT_CONFIG_VSYNC_POL_MASK           0x8u
#define VIU3_EXT_CONFIG_VSYNC_POL_SHIFT          3
#define VIU3_EXT_CONFIG_PCLK_POL_MASK            0x10u
#define VIU3_EXT_CONFIG_PCLK_POL_SHIFT           4
#define VIU3_EXT_CONFIG_INP_FORMAT_MASK          0xE0u
#define VIU3_EXT_CONFIG_INP_FORMAT_SHIFT         5
#define VIU3_EXT_CONFIG_INP_FORMAT(x)            (((uint32_t)(((uint32_t)(x))<<VIU3_EXT_CONFIG_INP_FORMAT_SHIFT))&VIU3_EXT_CONFIG_INP_FORMAT_MASK)
#define VIU3_EXT_CONFIG_DE_VALID_MASK            0x100u
#define VIU3_EXT_CONFIG_DE_VALID_SHIFT           8
#define VIU3_EXT_CONFIG_RGB2YUV_EN_MASK          0x200u
#define VIU3_EXT_CONFIG_RGB2YUV_EN_SHIFT         9
#define VIU3_EXT_CONFIG_LENDIAN_MASK             0x800u
#define VIU3_EXT_CONFIG_LENDIAN_SHIFT            11
#define VIU3_EXT_CONFIG_CS_EN_MASK               0x1000u
#define VIU3_EXT_CONFIG_CS_EN_SHIFT              12
/* RGB_Y Bit Fields */
#define VIU3_RGB_Y_B_Y_MASK                      0x3Fu
#define VIU3_RGB_Y_B_Y_SHIFT                     0
#define VIU3_RGB_Y_B_Y(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_Y_B_Y_SHIFT))&VIU3_RGB_Y_B_Y_MASK)
#define VIU3_RGB_Y_G_Y_MASK                      0xFF800u
#define VIU3_RGB_Y_G_Y_SHIFT                     11
#define VIU3_RGB_Y_G_Y(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_Y_G_Y_SHIFT))&VIU3_RGB_Y_G_Y_MASK)
#define VIU3_RGB_Y_R_Y_MASK                      0x3FC00000u
#define VIU3_RGB_Y_R_Y_SHIFT                     22
#define VIU3_RGB_Y_R_Y(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_Y_R_Y_SHIFT))&VIU3_RGB_Y_R_Y_MASK)
/* RGB_U Bit Fields */
#define VIU3_RGB_U_B_U_MASK                      0xFFu
#define VIU3_RGB_U_B_U_SHIFT                     0
#define VIU3_RGB_U_B_U(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_U_B_U_SHIFT))&VIU3_RGB_U_B_U_MASK)
#define VIU3_RGB_U_G_U_MASK                      0x7F800u
#define VIU3_RGB_U_G_U_SHIFT                     11
#define VIU3_RGB_U_G_U(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_U_G_U_SHIFT))&VIU3_RGB_U_G_U_MASK)
#define VIU3_RGB_U_R_U_MASK                      0x1FC00000u
#define VIU3_RGB_U_R_U_SHIFT                     22
#define VIU3_RGB_U_R_U(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_U_R_U_SHIFT))&VIU3_RGB_U_R_U_MASK)
/* RGB_V Bit Fields */
#define VIU3_RGB_V_B_V_MASK                      0x3Fu
#define VIU3_RGB_V_B_V_SHIFT                     0
#define VIU3_RGB_V_B_V(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_V_B_V_SHIFT))&VIU3_RGB_V_B_V_MASK)
#define VIU3_RGB_V_G_V_MASK                      0x7F800u
#define VIU3_RGB_V_G_V_SHIFT                     11
#define VIU3_RGB_V_G_V(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_V_G_V_SHIFT))&VIU3_RGB_V_G_V_MASK)
#define VIU3_RGB_V_R_V_MASK                      0x3FC00000u
#define VIU3_RGB_V_R_V_SHIFT                     22
#define VIU3_RGB_V_R_V(x)                        (((uint32_t)(((uint32_t)(x))<<VIU3_RGB_V_R_V_SHIFT))&VIU3_RGB_V_R_V_MASK)

/**
 * @}
 */ /* end of group VIU3_Register_Masks */


/* VIU3 - Peripheral instance base addresses */
/** Peripheral VIU3 base address */
#define VIU3_BASE                                (0x400C9000u)
/** Peripheral VIU3 base pointer */
#define VIU3                                     ((VIU3_Type *)VIU3_BASE)
/** Array initializer of VIU3 peripheral base pointers */
#define VIU3_BASES                               { VIU3 }

/**
 * @}
 */ /* end of group VIU3_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- VREG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup VREG_Peripheral_Access_Layer VREG Peripheral Access Layer
 * @{
 */

/** VREG - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control Register, offset: 0x0 */
  __IO uint32_t STAT;                              /**< Status register, offset: 0x4 */
} VREG_Type;

/* ----------------------------------------------------------------------------
   -- VREG Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup VREG_Register_Masks VREG Register Masks
 * @{
 */

/* CTRL Bit Fields */
#define VREG_CTRL_HVDMASK_MASK                   0x1u
#define VREG_CTRL_HVDMASK_SHIFT                  0
#define VREG_CTRL_POR1P2_PD_MASK                 0x4u
#define VREG_CTRL_POR1P2_PD_SHIFT                2
#define VREG_CTRL_HVD_PD_MASK                    0x8u
#define VREG_CTRL_HVD_PD_SHIFT                   3
#define VREG_CTRL_PORPU_MASK                     0x10000u
#define VREG_CTRL_PORPU_SHIFT                    16
/* STAT Bit Fields */
#define VREG_STAT_HVDSTAT_MASK                   0x1u
#define VREG_STAT_HVDSTAT_SHIFT                  0

/**
 * @}
 */ /* end of group VREG_Register_Masks */


/* VREG - Peripheral instance base addresses */
/** Peripheral VREG base address */
#define VREG_BASE                                (0x4006D000u)
/** Peripheral VREG base pointer */
#define VREG                                     ((VREG_Type *)VREG_BASE)
/** Array initializer of VREG peripheral base pointers */
#define VREG_BASES                               { VREG }

/**
 * @}
 */ /* end of group VREG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WDOG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
 * @{
 */

/** WDOG - Register Layout Typedef */
typedef struct {
  __IO uint16_t WCR;                               /**< Watchdog Control Register, offset: 0x0 */
  __IO uint16_t WSR;                               /**< Watchdog Service Register, offset: 0x2 */
  __I  uint16_t WRSR;                              /**< Watchdog Reset Status Register, offset: 0x4 */
  __IO uint16_t WICR;                              /**< Watchdog Interrupt Control Register, offset: 0x6 */
  __IO uint16_t WMCR;                              /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
} WDOG_Type;

/* ----------------------------------------------------------------------------
   -- WDOG Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup WDOG_Register_Masks WDOG Register Masks
 * @{
 */

/* WCR Bit Fields */
#define WDOG_WCR_WDZST_MASK                      0x1u
#define WDOG_WCR_WDZST_SHIFT                     0
#define WDOG_WCR_WDBG_MASK                       0x2u
#define WDOG_WCR_WDBG_SHIFT                      1
#define WDOG_WCR_WDE_MASK                        0x4u
#define WDOG_WCR_WDE_SHIFT                       2
#define WDOG_WCR_WDT_MASK                        0x8u
#define WDOG_WCR_WDT_SHIFT                       3
#define WDOG_WCR_SRS_MASK                        0x10u
#define WDOG_WCR_SRS_SHIFT                       4
#define WDOG_WCR_WDA_MASK                        0x20u
#define WDOG_WCR_WDA_SHIFT                       5
#define WDOG_WCR_SRE_MASK                        0x40u
#define WDOG_WCR_SRE_SHIFT                       6
#define WDOG_WCR_WDW_MASK                        0x80u
#define WDOG_WCR_WDW_SHIFT                       7
#define WDOG_WCR_WT_MASK                         0xFF00u
#define WDOG_WCR_WT_SHIFT                        8
#define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x))<<WDOG_WCR_WT_SHIFT))&WDOG_WCR_WT_MASK)
/* WSR Bit Fields */
#define WDOG_WSR_WSR_MASK                        0xFFFFu
#define WDOG_WSR_WSR_SHIFT                       0
#define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x))<<WDOG_WSR_WSR_SHIFT))&WDOG_WSR_WSR_MASK)
/* WRSR Bit Fields */
#define WDOG_WRSR_SFTW_MASK                      0x1u
#define WDOG_WRSR_SFTW_SHIFT                     0
#define WDOG_WRSR_TOUT_MASK                      0x2u
#define WDOG_WRSR_TOUT_SHIFT                     1
#define WDOG_WRSR_POR_MASK                       0x10u
#define WDOG_WRSR_POR_SHIFT                      4
/* WICR Bit Fields */
#define WDOG_WICR_WICT_MASK                      0xFFu
#define WDOG_WICR_WICT_SHIFT                     0
#define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x))<<WDOG_WICR_WICT_SHIFT))&WDOG_WICR_WICT_MASK)
#define WDOG_WICR_WTIS_MASK                      0x4000u
#define WDOG_WICR_WTIS_SHIFT                     14
#define WDOG_WICR_WIE_MASK                       0x8000u
#define WDOG_WICR_WIE_SHIFT                      15
/* WMCR Bit Fields */
#define WDOG_WMCR_PDE_MASK                       0x1u
#define WDOG_WMCR_PDE_SHIFT                      0

/**
 * @}
 */ /* end of group WDOG_Register_Masks */


/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG base address */
#define WDOG_BASE                                (0u)
/** Peripheral WDOG base pointer */
#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASES                               { WDOG }

/**
 * @}
 */ /* end of group WDOG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WKPU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup WKPU_Peripheral_Access_Layer WKPU Peripheral Access Layer
 * @{
 */

/** WKPU - Register Layout Typedef */
typedef struct {
  __IO uint32_t NSR;                               /**< NMI Status Flag Register, offset: 0x0 */
       uint8_t RESERVED_0[4];
  __IO uint32_t NCR;                               /**< NMI Configuration Register, offset: 0x8 */
       uint8_t RESERVED_1[8];
  __IO uint32_t WISR;                              /**< Wakeup/Interrupt Status Flag Register, offset: 0x14 */
  __IO uint32_t IRER;                              /**< Interrupt Request Enable Register, offset: 0x18 */
  __IO uint32_t WRER;                              /**< Wakeup Request Enable Register, offset: 0x1C */
       uint8_t RESERVED_2[8];
  __IO uint32_t WIREER;                            /**< Wakeup/Interrupt Rising-Edge Event Enable Register, offset: 0x28 */
  __IO uint32_t WIFEER;                            /**< Wakeup/Interrupt Falling-Edge Event Enable Register, offset: 0x2C */
  __IO uint32_t WIFER;                             /**< Wakeup/Interrupt Filter Enable Register, offset: 0x30 */
  __IO uint32_t WIPUER;                            /**< Wakeup/Interrupt Pullup Enable Register, offset: 0x34 */
} WKPU_Type;

/* ----------------------------------------------------------------------------
   -- WKPU Register Masks
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup WKPU_Register_Masks WKPU Register Masks
 * @{
 */

/* NSR Bit Fields */
#define WKPU_NSR_NOVF0_MASK                      0x40000000u
#define WKPU_NSR_NOVF0_SHIFT                     30
#define WKPU_NSR_NIF0_MASK                       0x80000000u
#define WKPU_NSR_NIF0_SHIFT                      31
/* NCR Bit Fields */
#define WKPU_NCR_NFE0_MASK                       0x1000000u
#define WKPU_NCR_NFE0_SHIFT                      24
#define WKPU_NCR_NFEE0_MASK                      0x2000000u
#define WKPU_NCR_NFEE0_SHIFT                     25
#define WKPU_NCR_NREE0_MASK                      0x4000000u
#define WKPU_NCR_NREE0_SHIFT                     26
#define WKPU_NCR_NWRE0_MASK                      0x10000000u
#define WKPU_NCR_NWRE0_SHIFT                     28
#define WKPU_NCR_NDSS0_MASK                      0x60000000u
#define WKPU_NCR_NDSS0_SHIFT                     29
#define WKPU_NCR_NDSS0(x)                        (((uint32_t)(((uint32_t)(x))<<WKPU_NCR_NDSS0_SHIFT))&WKPU_NCR_NDSS0_MASK)
#define WKPU_NCR_NLOCK0_MASK                     0x80000000u
#define WKPU_NCR_NLOCK0_SHIFT                    31
/* WISR Bit Fields */
#define WKPU_WISR_EIF_MASK                       0xFFFFFFFFu
#define WKPU_WISR_EIF_SHIFT                      0
#define WKPU_WISR_EIF(x)                         (((uint32_t)(((uint32_t)(x))<<WKPU_WISR_EIF_SHIFT))&WKPU_WISR_EIF_MASK)
/* IRER Bit Fields */
#define WKPU_IRER_EIRE_MASK                      0xFFFFFFFFu
#define WKPU_IRER_EIRE_SHIFT                     0
#define WKPU_IRER_EIRE(x)                        (((uint32_t)(((uint32_t)(x))<<WKPU_IRER_EIRE_SHIFT))&WKPU_IRER_EIRE_MASK)
/* WRER Bit Fields */
#define WKPU_WRER_WRE_MASK                       0xFFFFFFFFu
#define WKPU_WRER_WRE_SHIFT                      0
#define WKPU_WRER_WRE(x)                         (((uint32_t)(((uint32_t)(x))<<WKPU_WRER_WRE_SHIFT))&WKPU_WRER_WRE_MASK)
/* WIREER Bit Fields */
#define WKPU_WIREER_IREE_MASK                    0xFFFFFFFFu
#define WKPU_WIREER_IREE_SHIFT                   0
#define WKPU_WIREER_IREE(x)                      (((uint32_t)(((uint32_t)(x))<<WKPU_WIREER_IREE_SHIFT))&WKPU_WIREER_IREE_MASK)
/* WIFEER Bit Fields */
#define WKPU_WIFEER_IFEEx_MASK                   0xFFFFFFFFu
#define WKPU_WIFEER_IFEEx_SHIFT                  0
#define WKPU_WIFEER_IFEEx(x)                     (((uint32_t)(((uint32_t)(x))<<WKPU_WIFEER_IFEEx_SHIFT))&WKPU_WIFEER_IFEEx_MASK)
/* WIFER Bit Fields */
#define WKPU_WIFER_IFE_MASK                      0xFFFFFFFFu
#define WKPU_WIFER_IFE_SHIFT                     0
#define WKPU_WIFER_IFE(x)                        (((uint32_t)(((uint32_t)(x))<<WKPU_WIFER_IFE_SHIFT))&WKPU_WIFER_IFE_MASK)
/* WIPUER Bit Fields */
#define WKPU_WIPUER_IPUE_MASK                    0xFFFFFFFFu
#define WKPU_WIPUER_IPUE_SHIFT                   0
#define WKPU_WIPUER_IPUE(x)                      (((uint32_t)(((uint32_t)(x))<<WKPU_WIPUER_IPUE_SHIFT))&WKPU_WIPUER_IPUE_MASK)

/**
 * @}
 */ /* end of group WKPU_Register_Masks */


/* WKPU - Peripheral instance base addresses */
/** Peripheral WKPU base address */
#define WKPU_BASE                                (0x4006A000u)
/** Peripheral WKPU base pointer */
#define WKPU                                     ((WKPU_Type *)WKPU_BASE)
/** Array initializer of WKPU peripheral base pointers */
#define WKPU_BASES                               { WKPU }

/**
 * @}
 */ /* end of group WKPU_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #pragma pop
#elif defined(__CWCC__)
  #pragma pop
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=default
#else
  #error Not supported compiler type
#endif

/**
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Backward Compatibility
   ---------------------------------------------------------------------------- */

/**
 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
 * @{
 */

/* No backward compatibility issues. */

/**
 * @}
 */ /* end of group Backward_Compatibility_Symbols */


#endif  /* #if !defined(MVF50GS10MK50_H_) */

/* MVF50GS10MK50.h, eof. */
