
#ifndef _DMA_H_
#define _DMA_H_

#include "common.h"
#include "MVF50GS10MK50.h"

/* Clock gating for DMA modules - Platform clock registers */
//#define ENABLE_DMA0_CLOCKS        { CCM.CCPGR1.R |= 0x00F0000; }
//#define ENABLE_DMA1_CLOCKS        { CCM.CCPGR3.R |= 0x00F0000; }
#define ENABLE_DMA0_CLOCKS        { CCM->CCPGR1 |= 0x00F0000; }
#define ENABLE_DMA1_CLOCKS        { CCM->CCPGR3 |= 0x00F0000; }
#define ENABLE_DMAx_CLOCKS        { ENABLE_DMA0_CLOCKS; ENABLE_DMA1_CLOCKS; }

//#define ENABLE_DMA_MUX01_CLOCKS   { CCM.CCGR0.B.CG4 = 1; CCM.CCGR0.B.CG5 = 1; }
//#define ENABLE_DMA_MUX23_CLOCKS   { CCM.CCGR6.B.CG97 = 1; CCM.CCGR6.B.CG98 = 1; }
#define ENABLE_DMA_MUX01_CLOCKS   { CCM->CCGR0 |= 0x500; } 	//CCM_CCGR0_CG4{1); CCM->CCGR0 |= CCM_CCGR0_CG5{1); }
#define ENABLE_DMA_MUX23_CLOCKS   { CCM->CCGR6 |= 0x14; }	//0xCCM_CCGR6_CG1(1); CCM->CCGR6 |= CCM_CCGR6_CG2(1); }
#define ENABLE_DMA_MUXx_CLOCKS    { ENABLE_DMA_MUX01_CLOCKS; ENABLE_DMA_MUX23_CLOCKS; }


#define DDR_TCD0_SADDR 		(DMA0_BASE+0x1000)
#define DDR_TCD0_SOFF		(DMA0_BASE+0x1004)
#define DDR_TCD0_ATTR		(DMA0_BASE+0x1006)
#define DDR_TCD0_NBYTES 	(DMA0_BASE+0x1008)
#define DDR_TCD0_SLAST		(DMA0_BASE+0x100C)
#define DDR_TCD0_DADDR		(DMA0_BASE+0x1010)
#define DDR_TCD0_DOFF 		(DMA0_BASE+0x1014)
#define DDR_TCD0_CITER		(DMA0_BASE+0x1016)
#define DDR_TCD0_DLAST		(DMA0_BASE+0x1018)
#define DDR_TCD0_BITER		(DMA0_BASE+0x101E)
#define DDR_TCD0_CSR		(DMA0_BASE+0x101C)

/* Prototypes */
void dma_data_xfer(DMA_Type *ptrDMA, uint8_t dma_mux_ch0, uint8_t dma_source_ch, uint32_t source_addr, uint32_t destination_addr, uint32_t num_bytes);
void init_dma_tcd(DMA_Type *ptrDMA, int dma_ch);

#endif /* _DMA_H_ */
