Psoc : Powering on the supplies......done PSoC : Programming IDT device   PSoC: Bye, switching to Processor UART sdfjhdsfkjgsdfdsgfjhdghjfsg Initializing....fixed Memory ddr_freq_mhz=1600Configuring DDR for 1600 MT/s data rate fixed_ddr_parm=750 fixed_ddr_parm=850 sdfkjdfkfjkfkfdjkdjfhjkfdh fixed_ddr_parm=607 fixed_ddr_parm=749 sdfkjdfkfjkfkfdjkdjfhjkfdh fixed_ddr_parm=1500 fixed_ddr_parm=3200 sdfkjdfkfjkfkfdjkdjfhjkfdh jsdfhjfdhsjhj loop1.1 loop1.1 loop1.1 dsfjhfjsdfhjdfh @NIL under fixed ddr parameter config_SYS_SDRAM_size=4096 ddr_size=54 mem=0 @NIL calling~>fsl_ddr_set_memctl_regs ctrl_num=0 step=0 cs[0].bnds = 0x000001ff cs[0].config = 0x80040412 cs[0].config_2 = 0x00000000 cs[1].bnds = 0x00000000 cs[1].config = 0x00000000 cs[1].config_2 = 0x00000000 timing_cfg_3 = 0x01111000 timing_cfg_0 = 0x91550018 timing_cfg_1 = 0xbcb40c52 timing_cfg_2 = 0x0048c11c ddr_sdram_cfg = 0xe5040008 ddr_sdram_cfg_2 = 0x00401110 ddr_sdram_cfg_3 = 0x00000000 ddr_sdram_mode = 0x01010214 ddr_sdram_mode_2 = 0x00000000 ddr_sdram_mode_3 = 0x00000000 ddr_sdram_mode_4 = 0x00000000 ddr_sdram_mode_5 = 0x00000000 ddr_sdram_mode_6 = 0x00000000 ddr_sdram_mode_7 = 0x00000000 ddr_sdram_mode_8 = 0x00000000 ddr_sdram_mode_9 = 0x00000000 ddr_sdram_mode_10 = 0x00000000 ddr_sdram_mode_11 = 0x00000000 ddr_sdram_mode_12 = 0x00000000 ddr_sdram_mode_13 = 0x00000000 ddr_sdram_mode_14 = 0x00000000 ddr_sdram_mode_15 = 0x00000000 ddr_sdram_mode_16 = 0x00000000 ddr_sdram_md_cntl = 0x20000000 ddr_sdram_interval = 0x18600618 ddr_data_init = 0xdeadbeef ddr_sdram_clk_cntl = 0x02000000 ddr_init_addr = 0x00000000 ddr_init_ext_addr = 0x00000000 timing_cfg_4 = 0x00000002 timing_cfg_5 = 0x03401400 timing_cfg_6 = 0x00000000 timing_cfg_7 = 0x00000000 timing_cfg_8 = 0x00000000 timing_cfg_9 = 0x00000000 ddr_zq_cntl = 0x8a090705 ddr_wrlvl_cntl = 0x02000000 ddr_wrlvl_cntl_2 = 0x00000000 ddr_wrlvl_cntl_3 = 0x00000000 ddr_sr_cntr = 0x20000000 ddr_sdram_rcw_1 = 0x00000000 ddr_sdram_rcw_2 = 0x00000000 ddr_sdram_rcw_3 = 0x00000000 ddr_sdram_rcw_4 = 0x00000000 ddr_sdram_rcw_5 = 0x00000000 ddr_sdram_rcw_6 = 0x00000000 dq_map_0 = 0x00000000 dq_map_1 = 0x00000000 dq_map_2 = 0x00000000 dq_map_3 = 0x00000000 ddr_eor = 0x00000000 ddr_cdr1 = 0x00000000 ddr_cdr2 = 0x00000000 err_disable = 0x00000000 err_int_en = 0x00000000 debug[0] = 0x00000000 debug[1] = 0x00000000 debug[2] = 0x00000000 debug[3] = 0x00000000 debug[4] = 0x00000000 debug[5] = 0x00000000 debug[6] = 0x00000000 debug[7] = 0x00000000 debug[8] = 0x00000000 debug[9] = 0x00000000 debug[10] = 0x00000000 debug[11] = 0x00000000 debug[12] = 0x00000000 debug[13] = 0x00000000 debug[14] = 0x00000000 debug[15] = 0x00000000 debug[16] = 0x00000000 debug[17] = 0x00000000 debug[18] = 0x00000000 debug[19] = 0x00000000 debug[20] = 0x00000000 debug[21] = 0x00000000 debug[22] = 0x00000000 debug[23] = 0x00000000 debug[24] = 0x00000000 debug[25] = 0x00000000 debug[26] = 0x00000000 debug[27] = 0x00000000 debug[28] = 0x00000000 debug[29] = 0x00000000 debug[30] = 0x00000000 debug[31] = 0x00000000 config_fsl_DDR_BIST has been enabled1.0 config_fsl_DDR_BIST has been enabled1.1 case0 has been executed @NIL1.0 @NIL1.1 regs->cs[i].bnds 0x000001ff @NIL1.2 @NIL1.4 @NIL1.5 ################################### cs[0].bnds = 0x000001ff cs[0].config = 0x80040412 cs[0].config_2 = 0x00000000 cs[1].bnds = 0x00000000 cs[1].config = 0x00000000 cs[1].config_2 = 0x00000000 timing_cfg_3 = 0x01111000 timing_cfg_0 = 0x91550018 timing_cfg_1 = 0xbcb40c52 timing_cfg_2 = 0x0048c11c ddr_sdram_cfg = 0xe5040008 ddr_sdram_cfg_2 = 0x00401110 ddr_sdram_cfg_3 = 0x00000000 ddr_sdram_mode = 0x01010214 ddr_sdram_mode_2 = 0x00000000 ddr_sdram_mode_3 = 0x00000000 ddr_sdram_mode_4 = 0x00000000 ddr_sdram_mode_5 = 0x00000000 ddr_sdram_mode_6 = 0x00000000 ddr_sdram_mode_7 = 0x00000000 ddr_sdram_mode_8 = 0x00000000 ddr_sdram_mode_9 = 0x00000000 ddr_sdram_mode_10 = 0x00000000 ddr_sdram_mode_11 = 0x00000000 ddr_sdram_mode_12 = 0x00000000 ddr_sdram_mode_13 = 0x00000000 ddr_sdram_mode_14 = 0x00000000 ddr_sdram_mode_15 = 0x00000000 ddr_sdram_mode_16 = 0x00000000 ddr_sdram_md_cntl = 0x20000000 ddr_sdram_interval = 0x18600618 ddr_data_init = 0xdeadbeef ddr_sdram_clk_cntl = 0x02000000 ddr_init_addr = 0x00000000 ddr_init_ext_addr = 0x00000000 timing_cfg_4 = 0x00000002 timing_cfg_5 = 0x03401400 timing_cfg_6 = 0x00000000 timing_cfg_7 = 0x00000000 timing_cfg_8 = 0x00000000 timing_cfg_9 = 0x00000000 ddr_zq_cntl = 0x8a090705 ddr_wrlvl_cntl = 0x02000000 ddr_wrlvl_cntl_2 = 0x00000000 ddr_wrlvl_cntl_3 = 0x00000000 ddr_sr_cntr = 0x20000000 ddr_sdram_rcw_1 = 0x00000000 ddr_sdram_rcw_2 = 0x00000000 ddr_sdram_rcw_3 = 0x00000000 ddr_sdram_rcw_4 = 0x00000000 ddr_sdram_rcw_5 = 0x00000000 ddr_sdram_rcw_6 = 0x00000000 dq_map_0 = 0x00000000 dq_map_1 = 0x00000000 dq_map_2 = 0x00000000 dq_map_3 = 0x00000000 ddr_eor = 0x00000000 ddr_cdr1 = 0x00000000 ddr_cdr2 = 0x00000000 err_disable = 0x00000000 err_int_en = 0x00000000 debug[0] = 0x00000000 debug[1] = 0x00000000 debug[2] = 0x00000000 debug[3] = 0x00000000 debug[4] = 0x00000000 debug[5] = 0x00000000 debug[6] = 0x00000000 debug[7] = 0x00000000 debug[8] = 0x00000000 debug[9] = 0x00000000 debug[10] = 0x00000000 debug[11] = 0x00000000 debug[12] = 0x00000000 debug[13] = 0x00000000 debug[14] = 0x00000000 debug[15] = 0x00000000 debug[16] = 0x00000000 debug[17] = 0x00000000 debug[18] = 0x00000000 debug[19] = 0x00000000 debug[20] = 0x00000000 debug[21] = 0x00000000 debug[22] = 0x00000000 debug[23] = 0x00000000 debug[24] = 0x00000000 debug[25] = 0x00000000 debug[26] = 0x00000000 debug[27] = 0x00000000 debug[28] = 0x00000000 debug[29] = 0x00000000 debug[30] = 0x00000000 debug[31] = 0x00000000##################################### @NIL 1.9 else warm reboot cs[0].bnds = 0x000001ff cs[0].config = 0x80040412 cs[0].config_2 = 0x00000000 cs[1].bnds = 0x00000000 cs[1].config = 0x00000000 cs[1].config_2 = 0x00000000 timing_cfg_3 = 0x01111000 timing_cfg_0 = 0x91550018 timing_cfg_1 = 0xbcb40c52 timing_cfg_2 = 0x0048c11c ddr_sdram_cfg = 0xe5040008 ddr_sdram_cfg_2 = 0x00401110 ddr_sdram_cfg_3 = 0x00000000 ddr_sdram_mode = 0x01010214 ddr_sdram_mode_2 = 0x00000000 ddr_sdram_mode_3 = 0x00000000 ddr_sdram_mode_4 = 0x00000000 ddr_sdram_mode_5 = 0x00000000 ddr_sdram_mode_6 = 0x00000000 ddr_sdram_mode_7 = 0x00000000 ddr_sdram_mode_8 = 0x00000000 ddr_sdram_mode_9 = 0x00000000 ddr_sdram_mode_10 = 0x00000000 ddr_sdram_mode_11 = 0x00000000 ddr_sdram_mode_12 = 0x00000000 ddr_sdram_mode_13 = 0x00000000 ddr_sdram_mode_14 = 0x00000000 ddr_sdram_mode_15 = 0x00000000 ddr_sdram_mode_16 = 0x00000000 ddr_sdram_md_cntl = 0x20000000 ddr_sdram_interval = 0x18600618 ddr_data_init = 0xdeadbeef ddr_sdram_clk_cntl = 0x02000000 ddr_init_addr = 0x00000000 ddr_init_ext_addr = 0x00000000 timing_cfg_4 = 0x00000002 timing_cfg_5 = 0x03401400 timing_cfg_6 = 0x00000000 timing_cfg_7 = 0x00000000 timing_cfg_8 = 0x00000000 timing_cfg_9 = 0x00000000 ddr_zq_cntl = 0x8a090705 ddr_wrlvl_cntl = 0x02000000 ddr_wrlvl_cntl_2 = 0x00000000 ddr_wrlvl_cntl_3 = 0x00000000 ddr_sr_cntr = 0x20000000 ddr_sdram_rcw_1 = 0x00000000 ddr_sdram_rcw_2 = 0x00000000 ddr_sdram_rcw_3 = 0x00000000 ddr_sdram_rcw_4 = 0x00000000 ddr_sdram_rcw_5 = 0x00000000 ddr_sdram_rcw_6 = 0x00000000 dq_map_0 = 0x00000000 dq_map_1 = 0x00000000 dq_map_2 = 0x00000000 dq_map_3 = 0x00000000 ddr_eor = 0x00000000 ddr_cdr1 = 0x00000000 ddr_cdr2 = 0x00000000 err_disable = 0x00000000 err_int_en = 0x00000000 debug[0] = 0x00000000 debug[1] = 0x00000000 debug[2] = 0x00000000 debug[3] = 0x00000000 debug[4] = 0x00000000 debug[5] = 0x00000000 debug[6] = 0x00000000 debug[7] = 0x00000000 debug[8] = 0x00000000 debug[9] = 0x00000000 debug[10] = 0x00000000 debug[11] = 0x00000000 debug[12] = 0x00000000 debug[13] = 0x00000000 debug[14] = 0x00000000 debug[15] = 0x00000000 debug[16] = 0x00000000 debug[17] = 0x00000000 debug[18] = 0x00000000 debug[19] = 0x00000000 debug[20] = 0x00000000 debug[21] = 0x00000000 debug[22] = 0x00000000 debug[23] = 0x00000000 debug[24] = 0x00000000 debug[25] = 0x00000000 debug[26] = 0x00000000 debug[27] = 0x00000000 debug[28] = 0x00000000 debug[29] = 0x00000000 debug[30] = 0x00000000 debug[31] = 0x00000000 ddr-err_disable @NIL3.0 @NIL4.2 set but do not enable menory @NIL4.6 total 4 GB Need to wait up to 132 * 10ms this is anil Current value of FSLDDR: ddr_sdram_cfg_2 = 0x00401100 dfjfdsdjfhjfdhjkfh Performing DDR_BIST @NIL config_law register of the Memory returning ddr_size @NIL~> dram_size=02 GiB left unmapped @NILgetting dram_size=10 @NIL~> dram_size=48Loading second stage boot loader ................................................................................................. U-Boot 2016.012.0+ga9b437f (Oct 04 2024 - 10:21:31 +0530) CPU0: T1042, Version: 1.1, (0x85200211) Core: e5500, Version: 2.1, (0x80241021) Single Source Clock Configuration Clock Configuration: CPU0:1200 MHz, CPU1:1200 MHz, CPU2:1200 MHz, CPU3:1200 MHz, CCB:600 MHz, DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:150 MHz QE:300 MHz FMAN1: 600 MHz QMAN: 300 MHz PME: 300 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Reset Configuration Word (RCW): 00000000: 0c10000c 0c000000 00000000 00000000 00000010: 86000000 00000012 ec110000 21000000 00000020: 00000000 00000000 60000000 00038000 00000030: 00000000 c0160a05 00000000 00000000 I2C: ready Board: T1042D4RDB SPI: ready @NIL~>>>DRAM: under_init_func_ram @NIL initdram sdfjhdsfkjgsdfdsgfjhdghjfsg ddr_freq_mhz=1600Configuring DDR for 1600 MT/s data rate fixed_ddr_parm=750 fixed_ddr_parm=850 sdfkjdfkfjkfkfdjkdjfhjkfdh fixed_ddr_parm=607 fixed_ddr_parm=749 sdfkjdfkfjkfkfdjkdjfhjkfdh fixed_ddr_parm=1500 fixed_ddr_parm=3200 sdfkjdfkfjkfkfdjkdjfhjkfdh jsdfhjfdhsjhj loop1.1 loop1.1 loop1.1 dsfjhfjsdfhjdfh @NIL under fixed ddr parameter config_SYS_SDRAM_size=4096 ddr_size=54 mem=0 @NIL calling~>fsl_ddr_set_memctl_regs ctrl_num=0 step=0 cs[0].bnds = 0x000001ff cs[0].config = 0x80040412 cs[0].config_2 = 0x00000000 cs[1].bnds = 0x00000000 cs[1].config = 0x00000000 cs[1].config_2 = 0x00000000 timing_cfg_3 = 0x01111000 timing_cfg_0 = 0x91550018 timing_cfg_1 = 0xbcb40c52 timing_cfg_2 = 0x0048c11c ddr_sdram_cfg = 0xe5040008 ddr_sdram_cfg_2 = 0x00401110 ddr_sdram_cfg_3 = 0x00000000 ddr_sdram_mode = 0x01010214 ddr_sdram_mode_2 = 0x00000000 ddr_sdram_mode_3 = 0x00000000 ddr_sdram_mode_4 = 0x00000000 ddr_sdram_mode_5 = 0x00000000 ddr_sdram_mode_6 = 0x00000000 ddr_sdram_mode_7 = 0x00000000 ddr_sdram_mode_8 = 0x00000000 ddr_sdram_mode_9 = 0x00000000 ddr_sdram_mode_10 = 0x00000000 ddr_sdram_mode_11 = 0x00000000 ddr_sdram_mode_12 = 0x00000000 ddr_sdram_mode_13 = 0x00000000 ddr_sdram_mode_14 = 0x00000000 ddr_sdram_mode_15 = 0x00000000 ddr_sdram_mode_16 = 0x00000000 ddr_sdram_md_cntl = 0x20000000 ddr_sdram_interval = 0x18600618 ddr_data_init = 0xdeadbeef ddr_sdram_clk_cntl = 0x02000000 ddr_init_addr = 0x00000000 ddr_init_ext_addr = 0x00000000 timing_cfg_4 = 0x00000002 timing_cfg_5 = 0x03401400 timing_cfg_6 = 0x00000000 timing_cfg_7 = 0x00000000 timing_cfg_8 = 0x00000000 timing_cfg_9 = 0x00000000 ddr_zq_cntl = 0x8a090705 ddr_wrlvl_cntl = 0x02000000 ddr_wrlvl_cntl_2 = 0x00000000 ddr_wrlvl_cntl_3 = 0x00000000 ddr_sr_cntr = 0x20000000 ddr_sdram_rcw_1 = 0x00000000 ddr_sdram_rcw_2 = 0x00000000 ddr_sdram_rcw_3 = 0x00000000 ddr_sdram_rcw_4 = 0x00000000 ddr_sdram_rcw_5 = 0x00000000 ddr_sdram_rcw_6 = 0x00000000 dq_map_0 = 0x00000000 dq_map_1 = 0x00000000 dq_map_2 = 0x00000000 dq_map_3 = 0x00000000 ddr_eor = 0x00000000 ddr_cdr1 = 0x00000000 ddr_cdr2 = 0x00000000 err_disable = 0x00000000 err_int_en = 0x00000000 debug[0] = 0x00000000 debug[1] = 0x00000000 debug[2] = 0x00000000 debug[3] = 0x00000000 debug[4] = 0x00000000 debug[5] = 0x00000000 debug[6] = 0x00000000 debug[7] = 0x00000000 debug[8] = 0x00000000 debug[9] = 0x00000000 debug[10] = 0x00000000 debug[11] = 0x00000000 debug[12] = 0x00000000 debug[13] = 0x00000000 debug[14] = 0x00000000 debug[15] = 0x00000000 debug[16] = 0x00000000 debug[17] = 0x00000000 debug[18] = 0x00000000 debug[19] = 0x00000000 debug[20] = 0x00000000 debug[21] = 0x00000000 debug[22] = 0x00000000 debug[23] = 0x00000000 debug[24] = 0x00000000 debug[25] = 0x00000000 debug[26] = 0x00000000 debug[27] = 0x00000000 debug[28] = 0x00000000 debug[29] = 0x00000000 debug[30] = 0x00000000 debug[31] = 0x00000000 config_fsl_DDR_BIST has been enabled1.0 config_fsl_DDR_BIST has been enabled1.1 case0 has been executed @NIL1.0 @NIL1.1 regs->cs[i].bnds 0x000001ff @NIL1.2 @NIL1.4 @NIL1.5 ################################### cs[0].bnds = 0x000001ff cs[0].config = 0x80040412 cs[0].config_2 = 0x00000000 cs[1].bnds = 0x00000000 cs[1].config = 0x00000000 cs[1].config_2 = 0x00000000 timing_cfg_3 = 0x01111000 timing_cfg_0 = 0x91550018 timing_cfg_1 = 0xbcb40c52 timing_cfg_2 = 0x0048c11c ddr_sdram_cfg = 0xe5040008 ddr_sdram_cfg_2 = 0x00401110 ddr_sdram_cfg_3 = 0x00000000 ddr_sdram_mode = 0x01010214 ddr_sdram_mode_2 = 0x00000000 ddr_sdram_mode_3 = 0x00000000 ddr_sdram_mode_4 = 0x00000000 ddr_sdram_mode_5 = 0x00000000 ddr_sdram_mode_6 = 0x00000000 ddr_sdram_mode_7 = 0x00000000 ddr_sdram_mode_8 = 0x00000000 ddr_sdram_mode_9 = 0x00000000 ddr_sdram_mode_10 = 0x00000000 ddr_sdram_mode_11 = 0x00000000 ddr_sdram_mode_12 = 0x00000000 ddr_sdram_mode_13 = 0x00000000 ddr_sdram_mode_14 = 0x00000000 ddr_sdram_mode_15 = 0x00000000 ddr_sdram_mode_16 = 0x00000000 ddr_sdram_md_cntl = 0x20000000 ddr_sdram_interval = 0x18600618 ddr_data_init = 0xdeadbeef ddr_sdram_clk_cntl = 0x02000000 ddr_init_addr = 0x00000000 ddr_init_ext_addr = 0x00000000 timing_cfg_4 = 0x00000002 timing_cfg_5 = 0x03401400 timing_cfg_6 = 0x00000000 timing_cfg_7 = 0x00000000 timing_cfg_8 = 0x00000000 timing_cfg_9 = 0x00000000 ddr_zq_cntl = 0x8a090705 ddr_wrlvl_cntl = 0x02000000 ddr_wrlvl_cntl_2 = 0x00000000 ddr_wrlvl_cntl_3 = 0x00000000 ddr_sr_cntr = 0x20000000 ddr_sdram_rcw_1 = 0x00000000 ddr_sdram_rcw_2 = 0x00000000 ddr_sdram_rcw_3 = 0x00000000 ddr_sdram_rcw_4 = 0x00000000 ddr_sdram_rcw_5 = 0x00000000 ddr_sdram_rcw_6 = 0x00000000 dq_map_0 = 0x00000000 dq_map_1 = 0x00000000 dq_map_2 = 0x00000000 dq_map_3 = 0x00000000 ddr_eor = 0x00000000 ddr_cdr1 = 0x00000000 ddr_cdr2 = 0x00000000 err_disable = 0x00000000 err_int_en = 0x00000000 debug[0] = 0x00000000 debug[1] = 0x00000000 debug[2] = 0x00000000 debug[3] = 0x00000000 debug[4] = 0x00000000 debug[5] = 0x00000000 debug[6] = 0x00000000 debug[7] = 0x00000000 debug[8] = 0x00000000 debug[9] = 0x00000000 debug[10] = 0x00000000 debug[11] = 0x00000000 debug[12] = 0x00000000 debug[13] = 0x00000000 debug[14] = 0x00000000 debug[15] = 0x00000000 debug[16] = 0x00000000 debug[17] = 0x00000000 debug[18] = 0x00000000 debug[19] = 0x00000000 debug[20] = 0x00000000 debug[21] = 0x00000000 debug[22] = 0x00000000 debug[23] = 0x00000000 debug[24] = 0x00000000 debug[25] = 0x00000000 debug[26] = 0x00000000 debug[27] = 0x00000000 debug[28] = 0x00000000 debug[29] = 0x00000000 debug[30] = 0x00000000 debug[31] = 0x00000000##################################### @NIL 1.9 else warm reboot cs[0].bnds = 0x000001ff cs[0].config = 0x80040412 cs[0].config_2 = 0x00000000 cs[1].bnds = 0x00000000 cs[1].config = 0x00000000 cs[1].config_2 = 0x00000000 timing_cfg_3 = 0x01111000 timing_cfg_0 = 0x91550018 timing_cfg_1 = 0xbcb40c52 timing_cfg_2 = 0x0048c11c ddr_sdram_cfg = 0xe5040008 ddr_sdram_cfg_2 = 0x00401110 ddr_sdram_cfg_3 = 0x00000000 ddr_sdram_mode = 0x01010214 ddr_sdram_mode_2 = 0x00000000 ddr_sdram_mode_3 = 0x00000000 ddr_sdram_mode_4 = 0x00000000 ddr_sdram_mode_5 = 0x00000000 ddr_sdram_mode_6 = 0x00000000 ddr_sdram_mode_7 = 0x00000000 ddr_sdram_mode_8 = 0x00000000 ddr_sdram_mode_9 = 0x00000000 ddr_sdram_mode_10 = 0x00000000 ddr_sdram_mode_11 = 0x00000000 ddr_sdram_mode_12 = 0x00000000 ddr_sdram_mode_13 = 0x00000000 ddr_sdram_mode_14 = 0x00000000 ddr_sdram_mode_15 = 0x00000000 ddr_sdram_mode_16 = 0x00000000 ddr_sdram_md_cntl = 0x20000000 ddr_sdram_interval = 0x18600618 ddr_data_init = 0xdeadbeef ddr_sdram_clk_cntl = 0x02000000 ddr_init_addr = 0x00000000 ddr_init_ext_addr = 0x00000000 timing_cfg_4 = 0x00000002 timing_cfg_5 = 0x03401400 timing_cfg_6 = 0x00000000 timing_cfg_7 = 0x00000000 timing_cfg_8 = 0x00000000 timing_cfg_9 = 0x00000000 ddr_zq_cntl = 0x8a090705 ddr_wrlvl_cntl = 0x02000000 ddr_wrlvl_cntl_2 = 0x00000000 ddr_wrlvl_cntl_3 = 0x00000000 ddr_sr_cntr = 0x20000000 ddr_sdram_rcw_1 = 0x00000000 ddr_sdram_rcw_2 = 0x00000000 ddr_sdram_rcw_3 = 0x00000000 ddr_sdram_rcw_4 = 0x00000000 ddr_sdram_rcw_5 = 0x00000000 ddr_sdram_rcw_6 = 0x00000000 dq_map_0 = 0x00000000 dq_map_1 = 0x00000000 dq_map_2 = 0x00000000 dq_map_3 = 0x00000000 ddr_eor = 0x00000000 ddr_cdr1 = 0x00000000 ddr_cdr2 = 0x00000000 err_disable = 0x00000000 err_int_en = 0x00000000 debug[0] = 0x00000000 debug[1] = 0x00000000 debug[2] = 0x00000000 debug[3] = 0x00000000 debug[4] = 0x00000000 debug[5] = 0x00000000 debug[6] = 0x00000000 debug[7] = 0x00000000 debug[8] = 0x00000000 debug[9] = 0x00000000 debug[10] = 0x00000000 debug[11] = 0x00000000 debug[12] = 0x00000000 debug[13] = 0x00000000 debug[14] = 0x00000000 debug[15] = 0x00000000 debug[16] = 0x00000000 debug[17] = 0x00000000 debug[18] = 0x00000000 debug[19] = 0x00000000 debug[20] = 0x00000000 debug[21] = 0x00000000 debug[22] = 0x00000000 debug[23] = 0x00000000 debug[24] = 0x00000000 debug[25] = 0x00000000 debug[26] = 0x00000000 debug[27] = 0x00000000 debug[28] = 0x00000000 debug[29] = 0x00000000 debug[30] = 0x00000000 debug[31] = 0x00000000 ddÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ­¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïÞ¾ïd card.