SPI Flash boot...
SDRAM test phase 1:
SDRAM test phase 2:
SDRAM test passed.
Second program loader running in sram...
Loading second stage boot loader ...............................................................

U-Boot 2015.01 (Oct 22 2021 - 15:09:05)

CPU1:  P1022E, Version: 1.1, (0x80ee0011)
Core:  e500, Version: 5.1, (0x80211151)
Clock Configuration:
       CPU0:1066.667 MHz, CPU1:1066.667 MHz,
       CCB:533.333 MHz,
       DDR:333.333 MHz (666.667 MT/s ??data rate) (Asynchronous), LBC:33.333 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Board: C-DOT DWDM XGM(P1022)
I2C?:   ready
SPI?:   ready
DRAM:  Detected UDIMM 4KTF25664HZ-1G9P1
2 GiB (DDR3, 64-bit, CL=5, ECC off)
Flash?: 0 Bytes
L2:    256 KiB already enabled
512 MiB
MMC:   FSL_SDHC: 0
SF: Detected MT25QL256A with page size 256 Bytes, erase size 4 KiB, total 64 MiB
EEPROM: Read failed.
PCIe1: Root Complex of Slot 1, x4 gen1, regs @ 0xffe0a000
  01:00.0     - 11f8:5400 - Build before PCI Rev2.0
PCIe1: Bus 00 - 01
PCIe2: disabled
PCIe3: disabled
In:    serial
Out:   serial
Err:   serial
 XGM: All devices out of reset 0x0
Net:   Phy 30 not found
PHY reset timed out
XGM:: WRITE MULTI-CHIP MODE SMI_CMD REG VALUE= 0x9a03
XGM:: WRITE MULTI-CHIP MODE SMI_CMD REG SUCCESS
XGM:: READ MULTI-CHIP MODE SMI_CMD REG 0x1a03
XGM:: READ MULTI-CHIP MODE SMI_DATA REG VALUE= 0x1152
XGM:: SWITCH IDENTIFIER REG VALUE= 0x11520000
eTSEC1, eTSEC2 [PRIME]
Hit any key to stop autoboot:  0
XGM=>
XGM=>