/* =========================================================================
 *  This code (or certain portions of it) is released for use under license
 *  from Imagination Technologies Limited.
 *  Copyright (c) 2019 Imagination Technologies Limited
 *  Copyright 2015-2016 Freescale Semiconductor, Inc.
 *  Copyright 2017-2022 NXP
 *
 *  NXP Confidential. This software is owned or controlled by NXP and may only
 *  be used strictly in accordance with the applicable license terms. By
 *  expressly accepting such terms or by downloading, installing, activating
 *  and/or otherwise using the software, you are agreeing that you have read,
 *  and that you agree to comply with and are bound by, such license terms. If
 *  you do not agree to be bound by the applicable license terms, then you may
 *  not retain, install, activate or otherwise use the software.
 *  <<< PFE Restricted Software >>>
 *
 * ========================================================================= */

#ifndef PFE_CLASS_CSR_H_
#define PFE_CLASS_CSR_H_

/*==================================================================================================
*                                     FILE VERSION CHECK
==================================================================================================*/
#ifdef PFE_SRC_VERSION_CHECK
    #if (PFE_SRC_VERSION_CHECK != 43100440)
        #error "This header file was included from incompatible source file (different SW version)"
    #endif
#else
    #define PFE_SRC_VERSION_CHECK 43100440
#endif

#include "pfe_class.h"

#ifndef PFE_CBUS_H_
#error Missing cbus.h
#endif /* PFE_CBUS_H_ */

#define CLASS_VERSION               (CBUS_CLASS_CSR_BASE_ADDR + 0x000U)
#define CLASS_TX_CTRL               (CBUS_CLASS_CSR_BASE_ADDR + 0x004U)
#define CLASS_INQ_PKTPTR            (CBUS_CLASS_CSR_BASE_ADDR + 0x010U)
#define CLASS_HDR_SIZE              (CBUS_CLASS_CSR_BASE_ADDR + 0x014U)
#define CLASS_PE0_QB_DM_ADDR0       (CBUS_CLASS_CSR_BASE_ADDR + 0x020U)
#define CLASS_PE0_QB_DM_ADDR1       (CBUS_CLASS_CSR_BASE_ADDR + 0x024U)
#define CLASS_PE0_RO_DM_ADDR0       (CBUS_CLASS_CSR_BASE_ADDR + 0x060U)
#define CLASS_PE0_RO_DM_ADDR1       (CBUS_CLASS_CSR_BASE_ADDR + 0x064U)
#define CLASS_MEM_ACCESS_ADDR       (CBUS_CLASS_CSR_BASE_ADDR + 0x100U)
#define CLASS_MEM_ACCESS_WDATA      (CBUS_CLASS_CSR_BASE_ADDR + 0x104U)
#define CLASS_MEM_ACCESS_RDATA      (CBUS_CLASS_CSR_BASE_ADDR + 0x108U)
#define CLASS_TM_INQ_ADDR           (CBUS_CLASS_CSR_BASE_ADDR + 0x114U)
#define CLASS_PE_STATUS             (CBUS_CLASS_CSR_BASE_ADDR + 0x118U)
#define CLASS_PHY1_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x11cU)
#define CLASS_PHY1_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x120U)
#define CLASS_PHY1_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x124U)
#define CLASS_PHY1_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x128U)
#define CLASS_PHY1_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x12cU)
#define CLASS_PHY1_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x130U)
#define CLASS_PHY1_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x134U)
#define CLASS_PHY1_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x138U)
#define CLASS_PHY1_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x13cU)
#define CLASS_PHY1_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x140U)
#define CLASS_PHY2_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x144U)
#define CLASS_PHY2_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x148U)
#define CLASS_PHY2_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x14cU)
#define CLASS_PHY2_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x150U)
#define CLASS_PHY2_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x154U)
#define CLASS_PHY2_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x158U)
#define CLASS_PHY2_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x15cU)
#define CLASS_PHY2_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x160U)
#define CLASS_PHY2_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x164U)
#define CLASS_PHY2_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x168U)
#define CLASS_PHY3_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x16cU)
#define CLASS_PHY3_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x170U)
#define CLASS_PHY3_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x174U)
#define CLASS_PHY3_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x178U)
#define CLASS_PHY3_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x17cU)
#define CLASS_PHY3_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x180U)
#define CLASS_PHY3_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x184U)
#define CLASS_PHY3_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x188U)
#define CLASS_PHY3_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x18cU)
#define CLASS_PHY3_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x190U)
#define CLASS_PHY1_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x194U)
#define CLASS_PHY1_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x198U)
#define CLASS_PHY1_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x19cU)
#define CLASS_PHY1_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1a0U)
#define CLASS_PHY2_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x1a4U)
#define CLASS_PHY2_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x1a8U)
#define CLASS_PHY2_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1acU)
#define CLASS_PHY2_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1b0U)
#define CLASS_PHY3_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x1b4U)
#define CLASS_PHY3_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x1b8U)
#define CLASS_PHY3_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1bcU)
#define CLASS_PHY3_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1c0U)
#define CLASS_PHY4_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x1c4U)
#define CLASS_PHY4_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x1c8U)
#define CLASS_PHY4_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1ccU)
#define CLASS_PHY4_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x1d0U)
#define CLASS_PHY4_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x1d4U)
#define CLASS_PHY4_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x1d8U)
#define CLASS_PHY4_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x1dcU)
#define CLASS_PHY4_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x1e0U)
#define CLASS_PHY4_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x1e4U)
#define CLASS_PHY4_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x1e8U)
#define CLASS_PHY4_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x1ecU)
#define CLASS_PHY4_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x1f0U)
#define CLASS_PHY4_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x1f4U)
#define CLASS_PHY4_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x1f8U)
#define CLASS_PE_SYS_CLK_RATIO      (CBUS_CLASS_CSR_BASE_ADDR + 0x200U)
#define CLASS_AFULL_THRES           (CBUS_CLASS_CSR_BASE_ADDR + 0x204U)
#define CLASS_GAP_BETWEEN_READS     (CBUS_CLASS_CSR_BASE_ADDR + 0x208U)
#define CLASS_MAX_BUF_CNT           (CBUS_CLASS_CSR_BASE_ADDR + 0x20cU)
#define CLASS_TSQ_FIFO_THRES        (CBUS_CLASS_CSR_BASE_ADDR + 0x210U)
#define CLASS_TSQ_MAX_CNT           (CBUS_CLASS_CSR_BASE_ADDR + 0x214U)
#define CLASS_IRAM_DATA_0           (CBUS_CLASS_CSR_BASE_ADDR + 0x218U)
#define CLASS_IRAM_DATA_1           (CBUS_CLASS_CSR_BASE_ADDR + 0x21cU)
#define CLASS_IRAM_DATA_2           (CBUS_CLASS_CSR_BASE_ADDR + 0x220U)
#define CLASS_IRAM_DATA_3           (CBUS_CLASS_CSR_BASE_ADDR + 0x224U)
#define CLASS_BUS_ACCESS_ADDR       (CBUS_CLASS_CSR_BASE_ADDR + 0x228U)
#define CLASS_BUS_ACCESS_WDATA      (CBUS_CLASS_CSR_BASE_ADDR + 0x22cU)
#define CLASS_BUS_ACCESS_RDATA      (CBUS_CLASS_CSR_BASE_ADDR + 0x230U)
#define CLASS_ROUTE_HASH_ENTRY_SIZE (CBUS_CLASS_CSR_BASE_ADDR + 0x234U)
#define ROUTE_ENTRY_SIZE(size)      ((size) & 0x3ffU)
#define ROUTE_HASH_SIZE(hash_bits)  (((uint32_t)(hash_bits) & 0xffUL) << 16U)
#define CLASS_ROUTE_TABLE_BASE      (CBUS_CLASS_CSR_BASE_ADDR + 0x238U)
#define CLASS_ROUTE_MULTI           (CBUS_CLASS_CSR_BASE_ADDR + 0x23cU)
#define CLASS_SMEM_OFFSET           (CBUS_CLASS_CSR_BASE_ADDR + 0x240U)
#define CLASS_LMEM_BUF_SIZE         (CBUS_CLASS_CSR_BASE_ADDR + 0x244U)
#define CLASS_VLAN_ID               (CBUS_CLASS_CSR_BASE_ADDR + 0x248U)
#define CLASS_BMU1_BUF_FREE         (CBUS_CLASS_CSR_BASE_ADDR + 0x24cU)
#define CLASS_USE_TMU_INQ           (CBUS_CLASS_CSR_BASE_ADDR + 0x250U)
#define CLASS_VLAN_ID1              (CBUS_CLASS_CSR_BASE_ADDR + 0x254U)
#define CLASS_BUS_ACCESS_BASE       (CBUS_CLASS_CSR_BASE_ADDR + 0x258U)
#define CLASS_HIF_PARSE             (CBUS_CLASS_CSR_BASE_ADDR + 0x25cU)
#define CLASS_HOST_PE0_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x260U)
#define CLASS_PE0_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x264U)
#define CLASS_HOST_PE1_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x268U)
#define CLASS_PE1_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x26cU)
#define CLASS_HOST_PE2_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x270U)
#define CLASS_PE2_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x274U)
#define CLASS_HOST_PE3_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x278U)
#define CLASS_PE3_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x27cU)
#define CLASS_HOST_PE4_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x280U)
#define CLASS_PE4_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x284U)
#define CLASS_HOST_PE5_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x288U)
#define CLASS_PE5_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x28cU)
#define CLASS_PE_INT_SRC            (CBUS_CLASS_CSR_BASE_ADDR + 0x290U)
#define CLASS_PE_INT_ENABLE         (CBUS_CLASS_CSR_BASE_ADDR + 0x294U)
#define CLASS_TPID0_TPID1           (CBUS_CLASS_CSR_BASE_ADDR + 0x298U)
#define CLASS_TPID2                 (CBUS_CLASS_CSR_BASE_ADDR + 0x29cU)
#define CLASS_L4_CHKSUM             (CBUS_CLASS_CSR_BASE_ADDR + 0x2a0U)
#define CLASS_PE0_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2a4U)
#define CLASS_PE1_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2a8U)
#define CLASS_PE2_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2acU)
#define CLASS_PE3_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2b0U)
#define CLASS_PE4_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2b4U)
#define CLASS_PE5_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2b8U)
#define CLASS_STATE                 (CBUS_CLASS_CSR_BASE_ADDR + 0x2bcU)
#define CLASS_QB_BUF_AVAIL          (CBUS_CLASS_CSR_BASE_ADDR + 0x2c0U)
#define CLASS_RO_BUF_AVAIL          (CBUS_CLASS_CSR_BASE_ADDR + 0x2c4U)
#define CLASS_PE6_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2c8U)
#define CLASS_PE7_DEBUG             (CBUS_CLASS_CSR_BASE_ADDR + 0x2ccU)
#define CLASS_HOST_PE6_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x2d0U)
#define CLASS_PE6_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x2d4U)
#define CLASS_HOST_PE7_GP           (CBUS_CLASS_CSR_BASE_ADDR + 0x2d8U)
#define CLASS_PE7_GP                (CBUS_CLASS_CSR_BASE_ADDR + 0x2dcU)
#define CLASS_DOS_CONTRL1           (CBUS_CLASS_CSR_BASE_ADDR + 0x2e0U)
#define CLASS_DOS_CONTRL2           (CBUS_CLASS_CSR_BASE_ADDR + 0x2e4U)
#define CLASS_DOS_TCP_FLAGCHK_COMB_VALUE1   (CBUS_CLASS_CSR_BASE_ADDR + 0x2e8U)
#define CLASS_DOS_ICMPV4_MAX_PKTLEN (CBUS_CLASS_CSR_BASE_ADDR + 0x2ecU)
#define CLASS_INQ_AFULL_THRES       (CBUS_CLASS_CSR_BASE_ADDR + 0x2f0U)
#define CLASS_DMEM_BRS_OFFSET       (CBUS_CLASS_CSR_BASE_ADDR + 0x2f4U)
#define CLASS_PHY5_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x300U)
#define CLASS_PHY5_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x304U)
#define CLASS_PHY5_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x308U)
#define CLASS_PHY5_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x30cU)
#define CLASS_PHY5_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x310U)
#define CLASS_PHY5_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x314U)
#define CLASS_PHY5_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x318U)
#define CLASS_PHY5_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x31cU)
#define CLASS_PHY5_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x320U)
#define CLASS_PHY5_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x324U)
#define CLASS_PHY5_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x328U)
#define CLASS_PHY5_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x32cU)
#define CLASS_PHY5_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x330U)
#define CLASS_PHY5_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x334U)
#define CLASS_PHY6_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x340U)
#define CLASS_PHY6_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x344U)
#define CLASS_PHY6_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x348U)
#define CLASS_PHY6_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x34cU)
#define CLASS_PHY6_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x350U)
#define CLASS_PHY6_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x354U)
#define CLASS_PHY6_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x358U)
#define CLASS_PHY6_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x35cU)
#define CLASS_PHY6_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x360U)
#define CLASS_PHY6_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x364U)
#define CLASS_PHY6_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x368U)
#define CLASS_PHY6_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x36cU)
#define CLASS_PHY6_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x370U)
#define CLASS_PHY6_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x374U)
#define CLASS_PHY7_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x380U)
#define CLASS_PHY7_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x384U)
#define CLASS_PHY7_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x388U)
#define CLASS_PHY7_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x38cU)
#define CLASS_PHY7_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x390U)
#define CLASS_PHY7_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x394U)
#define CLASS_PHY7_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x398U)
#define CLASS_PHY7_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x39cU)
#define CLASS_PHY7_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x3a0U)
#define CLASS_PHY7_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x3a4U)
#define CLASS_PHY7_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x3a8U)
#define CLASS_PHY7_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x3acU)
#define CLASS_PHY7_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x3b0U)
#define CLASS_PHY7_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x3b4U)
#define CLASS_PHY8_RX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x3c0U)
#define CLASS_PHY8_TX_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x3c4U)
#define CLASS_PHY8_LP_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x3c8U)
#define CLASS_PHY8_INTF_FAIL_PKTS   (CBUS_CLASS_CSR_BASE_ADDR + 0x3ccU)
#define CLASS_PHY8_INTF_MATCH_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x3d0U)
#define CLASS_PHY8_L3_FAIL_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x3d4U)
#define CLASS_PHY8_V4_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x3d8U)
#define CLASS_PHY8_V6_PKTS          (CBUS_CLASS_CSR_BASE_ADDR + 0x3dcU)
#define CLASS_PHY8_CHKSUM_ERR_PKTS  (CBUS_CLASS_CSR_BASE_ADDR + 0x3e0U)
#define CLASS_PHY8_TTL_ERR_PKTS     (CBUS_CLASS_CSR_BASE_ADDR + 0x3e4U)
#define CLASS_PHY8_ICMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x3e8U)
#define CLASS_PHY8_IGMP_PKTS        (CBUS_CLASS_CSR_BASE_ADDR + 0x3ecU)
#define CLASS_PHY8_TCP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x3f0U)
#define CLASS_PHY8_UDP_PKTS         (CBUS_CLASS_CSR_BASE_ADDR + 0x3f4U)
#define CLASS_SNOOP_SPL_MCAST_ADDR1_LSB (CBUS_CLASS_CSR_BASE_ADDR + 0x3f8U)
#define CLASS_SNOOP_SPL_MCAST_ADDR1_MSB (CBUS_CLASS_CSR_BASE_ADDR + 0x3fcU)
#define CLASS_SNOOP_SPL_MCAST_ADDR2_LSB (CBUS_CLASS_CSR_BASE_ADDR + 0x400U)
#define CLASS_SNOOP_SPL_MCAST_ADDR2_MSB (CBUS_CLASS_CSR_BASE_ADDR + 0x404U)
#define CLASS_SNOOP_SPL_MCAST_MASK1_LSB (CBUS_CLASS_CSR_BASE_ADDR + 0x408U)
#define CLASS_SNOOP_SPL_MCAST_MASK1_MSB (CBUS_CLASS_CSR_BASE_ADDR + 0x40cU)
#define CLASS_SNOOP_SPL_MCAST_MASK2_LSB (CBUS_CLASS_CSR_BASE_ADDR + 0x410U)
#define CLASS_SNOOP_SPL_MCAST_MASK2_MSB (CBUS_CLASS_CSR_BASE_ADDR + 0x414U)

#define CLASS_LMEM_DATA_OFFSET              (CBUS_CLASS_CSR_BASE_ADDR + 0x418U)
#define CLASS_BCAST_PORTMAP                 (CBUS_CLASS_CSR_BASE_ADDR + 0x41cU)
#define CLASS_DAMACHASH_HOST_CMD_REG        (CBUS_CLASS_CSR_BASE_ADDR + 0x420U)
#define CLASS_DAMACHASH_HOST_MAC_ADDR1_REG  (CBUS_CLASS_CSR_BASE_ADDR + 0x424U)
#define CLASS_DAMACHASH_HOST_MAC_ADDR2_REG  (CBUS_CLASS_CSR_BASE_ADDR + 0x428U)
#define CLASS_DAMACHASH_HOST_MAC_ADDR3_REG  (CBUS_CLASS_CSR_BASE_ADDR + 0x42cU)
#define CLASS_DAMACHASH_HOST_MAC_ADDR4_REG  (CBUS_CLASS_CSR_BASE_ADDR + 0x430U)
#define CLASS_DAMACHASH_HOST_MAC_ADDR5_REG  (CBUS_CLASS_CSR_BASE_ADDR + 0x434U)
#define CLASS_DAMACHASH_HOST_ENTRY_REG      (CBUS_CLASS_CSR_BASE_ADDR + 0x438U)
#define CLASS_DAMACHASH_HOST_STATUS_REG     (CBUS_CLASS_CSR_BASE_ADDR + 0x43cU)
#define CLASS_DAMACHASH_HOST_DIRECT         (CBUS_CLASS_CSR_BASE_ADDR + 0x440U)
#define CLASS_DAMACHASH_PE_CMD_REG          (CBUS_CLASS_CSR_BASE_ADDR + 0x444U)
#define CLASS_DAMACHASH_PE_MAC_ADDR1_REG    (CBUS_CLASS_CSR_BASE_ADDR + 0x448U)
#define CLASS_DAMACHASH_PE_MAC_ADDR2_REG    (CBUS_CLASS_CSR_BASE_ADDR + 0x44cU)
#define CLASS_DAMACHASH_PE_MAC_ADDR3_REG    (CBUS_CLASS_CSR_BASE_ADDR + 0x450U)
#define CLASS_DAMACHASH_PE_MAC_ADDR4_REG    (CBUS_CLASS_CSR_BASE_ADDR + 0x454U)
#define CLASS_DAMACHASH_PE_MAC_ADDR5_REG    (CBUS_CLASS_CSR_BASE_ADDR + 0x458U)
#define CLASS_DAMACHASH_PE_ENTRY_REG        (CBUS_CLASS_CSR_BASE_ADDR + 0x45cU)
#define CLASS_DAMACHASH_PE_STATUS_REG       (CBUS_CLASS_CSR_BASE_ADDR + 0x460U)
#define CLASS_DAMACHASH_PE_DIRECT           (CBUS_CLASS_CSR_BASE_ADDR + 0x464U)
#define CLASS_DAMACHASH_FREELIST_ENTRIES    (CBUS_CLASS_CSR_BASE_ADDR + 0x468U)
#define CLASS_DAMACHASH_FREELIST_HEAD_PTR   (CBUS_CLASS_CSR_BASE_ADDR + 0x46cU)
#define CLASS_DAMACHASH_FREELIST_TAIL_PTR   (CBUS_CLASS_CSR_BASE_ADDR + 0x470U)
#define CLASS_DAVLANHASH_HOST_CMD_REG       (CBUS_CLASS_CSR_BASE_ADDR + 0x474U)
#define CLASS_DAVLANHASH_HOST_MAC_ADDR1_REG (CBUS_CLASS_CSR_BASE_ADDR + 0x478U)
#define CLASS_DAVLANHASH_HOST_MAC_ADDR2_REG (CBUS_CLASS_CSR_BASE_ADDR + 0x47cU)
#define CLASS_DAVLANHASH_HOST_MAC_ADDR3_REG (CBUS_CLASS_CSR_BASE_ADDR + 0x480U)
#define CLASS_DAVLANHASH_HOST_MAC_ADDR4_REG (CBUS_CLASS_CSR_BASE_ADDR + 0x484U)
#define CLASS_DAVLANHASH_HOST_MAC_ADDR5_REG (CBUS_CLASS_CSR_BASE_ADDR + 0x488U)
#define CLASS_DAVLANHASH_HOST_ENTRY_REG     (CBUS_CLASS_CSR_BASE_ADDR + 0x48cU)
#define CLASS_DAVLANHASH_HOST_STATUS_REG    (CBUS_CLASS_CSR_BASE_ADDR + 0x490U)
#define CLASS_DAVLANHASH_HOST_DIRECT        (CBUS_CLASS_CSR_BASE_ADDR + 0x494U)
#define CLASS_DAVLANHASH_PE_CMD_REG         (CBUS_CLASS_CSR_BASE_ADDR + 0x498U)
#define CLASS_DAVLANHASH_PE_MAC_ADDR1_REG   (CBUS_CLASS_CSR_BASE_ADDR + 0x49cU)
#define CLASS_DAVLANHASH_PE_MAC_ADDR2_REG   (CBUS_CLASS_CSR_BASE_ADDR + 0x4a0U)
#define CLASS_DAVLANHASH_PE_MAC_ADDR3_REG   (CBUS_CLASS_CSR_BASE_ADDR + 0x4a4U)
#define CLASS_DAVLANHASH_PE_MAC_ADDR4_REG   (CBUS_CLASS_CSR_BASE_ADDR + 0x4a8U)
#define CLASS_DAVLANHASH_PE_MAC_ADDR5_REG   (CBUS_CLASS_CSR_BASE_ADDR + 0x4acU)
#define CLASS_DAVLANHASH_PE_ENTRY_REG       (CBUS_CLASS_CSR_BASE_ADDR + 0x4b0U)
#define CLASS_DAVLANHASH_PE_STATUS_REG      (CBUS_CLASS_CSR_BASE_ADDR + 0x4b4U)
#define CLASS_DAVLANHASH_PE_DIRECT          (CBUS_CLASS_CSR_BASE_ADDR + 0x4b8U)
#define CLASS_DAVLANHASH_FREELIST_ENTRIES   (CBUS_CLASS_CSR_BASE_ADDR + 0x4bcU)
#define CLASS_DAVLANHASH_FREELIST_HEAD_PTR  (CBUS_CLASS_CSR_BASE_ADDR + 0x4c0U)
#define CLASS_DAVLANHASH_FREELIST_TAIL_PTR  (CBUS_CLASS_CSR_BASE_ADDR + 0x4c4U)
#define CLASS_SNOOP_SPL_ETYPE_REG01     (CBUS_CLASS_CSR_BASE_ADDR + 0x4c8U)
#define CLASS_SNOOP_SPL_ETYPE_REG23     (CBUS_CLASS_CSR_BASE_ADDR + 0x4ccU)
#define CLASS_SNOOP_CONTROL             (CBUS_CLASS_CSR_BASE_ADDR + 0x4d0U)

#define CLASS_TPID_EN                   (CBUS_CLASS_CSR_BASE_ADDR + 0x4d4U)
#define CLASS_STPID01                   (CBUS_CLASS_CSR_BASE_ADDR + 0x4d8U)
#define CLASS_STPID2                    (CBUS_CLASS_CSR_BASE_ADDR + 0x4dcU)
#define CLASS_DIS_PORT_FETCH            (CBUS_CLASS_CSR_BASE_ADDR + 0x4e0U)

#define CLASS_GLOBAL_REGISTER           (CBUS_CLASS_CSR_BASE_ADDR + 0x4e4U)
#define CLASS_DOS_ICMPV6_MAX_PKTLEN     (CBUS_CLASS_CSR_BASE_ADDR + 0x4e8U)
#define CLASS_DEBUG_BUS01               (CBUS_CLASS_CSR_BASE_ADDR + 0x4ecU)
#define CLASS_DEBUG_BUS23               (CBUS_CLASS_CSR_BASE_ADDR + 0x4f0U)
#define CLASS_DEBUG_BUS45               (CBUS_CLASS_CSR_BASE_ADDR + 0x4f4U)
#define CLASS_DEBUG_BUS67               (CBUS_CLASS_CSR_BASE_ADDR + 0x4f8U)
#define CLASS_DEBUG_BUS89               (CBUS_CLASS_CSR_BASE_ADDR + 0x4fcU)
#define CLASS_DEBUG_BUS1011             (CBUS_CLASS_CSR_BASE_ADDR + 0x500U)
#define CLASS_DEBUG_BUS12               (CBUS_CLASS_CSR_BASE_ADDR + 0x504U)
#define CLASS_DDR_BUF_SIZE              (CBUS_CLASS_CSR_BASE_ADDR + 0x508U)
#define CLASS_AXI_CTRL_ADDR             (CBUS_CLASS_CSR_BASE_ADDR + 0x50cU)
#define CLASS_PE_CONFIG                 (CBUS_CLASS_CSR_BASE_ADDR + 0x510U)

/* CLASS defines */
#define CLASS_PBUF_SIZE             0x200UL
#define CLASS_PBUF_HEADER_OFFSET    0x00UL

#define CLASS_PBUF0_BASE_ADDR       0x000UL
#define CLASS_PBUF1_BASE_ADDR       (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
#define CLASS_PBUF2_BASE_ADDR       (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
#define CLASS_PBUF3_BASE_ADDR       (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)

#define CLASS_PBUF0_HEADER_BASE_ADDR    (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
#define CLASS_PBUF1_HEADER_BASE_ADDR    (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
#define CLASS_PBUF2_HEADER_BASE_ADDR    (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
#define CLASS_PBUF3_HEADER_BASE_ADDR    (CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)

#define CLASS_PE0_RO_DM_ADDR0_VAL   ((CLASS_PBUF1_BASE_ADDR << 16U) | CLASS_PBUF0_BASE_ADDR)
#define CLASS_PE0_RO_DM_ADDR1_VAL   ((CLASS_PBUF3_BASE_ADDR << 16U) | CLASS_PBUF2_BASE_ADDR)

#define CLASS_PE0_QB_DM_ADDR0_VAL   ((CLASS_PBUF1_HEADER_BASE_ADDR << 16U) | CLASS_PBUF0_HEADER_BASE_ADDR)
#define CLASS_PE0_QB_DM_ADDR1_VAL   ((CLASS_PBUF3_HEADER_BASE_ADDR << 16U) | CLASS_PBUF2_HEADER_BASE_ADDR)

#define CLASS_TPID_DOT1Q            0x8100UL
#define CLASS_TPID_DOT1AD_0         0x88A8UL
#define CLASS_TPID_DOT1AD_1         0x9100UL
#define CLASS_TPID0_TPID1_VAL         ((CLASS_TPID_DOT1AD_0 << 16U) | CLASS_TPID_DOT1Q)
#define CLASS_TPID2_VAL                               (CLASS_TPID_DOT1AD_1)

#define RT_TWO_LEVEL_REF(x)         ((!!x) ? (1UL << 0U) : 0U)
#define PHYNO_IN_HASH(x)            ((!!x) ? (1UL << 1U) : 0U)
#define PARSE_ROUTE_EN(x)           ((!!x) ? (1UL << 3U) : 0U)
#define VLAN_AWARE_BRIDGE(x)        ((!!x) ? (1UL << 4U) : 0U)
#define PARSE_BRIDGE_EN(x)          ((!!x) ? (1UL << 5U) : 0U)
#define IPALIGNED_PKT(x)            ((!!x) ? (1UL << 6U) : 0U)
#define ARC_HIT_CHECK_EN(x)         ((!!x) ? (1UL << 7U) : 0U)
#define VLAN_AWARE_BRIDGE_PHY1(x)   ((!!x) ? (1UL << 8U) : 0U)
#define VLAN_AWARE_BRIDGE_PHY2(x)   ((!!x) ? (1UL << 9U) : 0U)
#define VLAN_AWARE_BRIDGE_PHY3(x)   ((!!x) ? (1UL << 10U) : 0U)
#define CLASS_TOE(x)                ((!!x) ? (1UL << 11U) : 0U)
#define ASYM_HASH(x)                ((((uint32_t)(x)) & 0x3UL) << 12U)
#define ASYM_HASH_NORMAL            0x0U
#define ASYM_HASH_SPORT_CRC         0x1U
#define ASYM_HASH_SIP_CRC           0x2U
#define ASYM_HASH_SIP_SPORT_CRC     0x3U
#define SYM_RTENTRY(x)              ((!!x) ? (1UL << 14U) : 0U)
#define QB2BUS_ENDIANESS(x)         ((!!x) ? (1UL << 15U) : 0U)
#define LEN_CHECK(x)                ((!!x) ? (1UL << 16U) : 0U)
#define USE_DEFAULT_VLANID(x)       ((!!x) ? (1UL << 0U) : 0UL)
#define DEF_VLANID(x)               ((((uint32_t)(x)) & 0xfffUL) << 1U)
#define PE_IBUS_WRITE               (1UL<<31U)
#define PE_IBUS_READ                (0UL<<31U)
#define PE_IBUS_ACCESS_IMEM         (1UL<<17U)
#define PE_IBUS_ACCESS_DMEM         (1UL<<18U)
#define PE_IBUS_PE_ID(x)            ((((uint32_t)(x)) & 0xfUL) << 20U)
#define PE_IBUS_WREN(x)             ((((uint32_t)(x)) & 0xfUL) << 24U)
#define PE_IBUS_BYTES(x)            ((1UL << (x)) - 1U) << (4U - (x)) /* 0x1 = LSB, 0x8 = MSB (BE) */
#define AXI_DBUS_BURST_SIZE(x)      ((((uint16_t)(x)) & 0x3ffU) << 4U)

#ifdef PFE_CFG_TARGET_OS_AUTOSAR
#define ETH_43_PFE_START_SEC_CODE
#include "Eth_43_PFE_MemMap.h"
#endif /* PFE_CFG_TARGET_OS_AUTOSAR */

void pfe_class_cfg_set_config(addr_t base_va, const pfe_class_cfg_t *cfg);
void pfe_class_cfg_reset(addr_t base_va);
void pfe_class_cfg_enable(addr_t base_va);
void pfe_class_cfg_disable(addr_t base_va);

#if !defined(PFE_CFG_TARGET_OS_AUTOSAR) || defined(PFE_CFG_TEXT_STATS)
uint32_t pfe_class_cfg_get_text_stat(addr_t base_va, char_t *buf, uint32_t size, uint8_t verb_level);
#endif /* !defined(PFE_CFG_TARGET_OS_AUTOSAR) || defined(PFE_CFG_TEXT_STATS) */

errno_t pfe_class_cfg_set_rtable(addr_t base_va, addr_t rtable_pa, uint32_t rtable_len, uint32_t entry_size);
void pfe_class_cfg_set_def_vlan(addr_t base_va, uint16_t vlan);
void pfe_class_cfg_rtable_lookup_enable(const addr_t base_va);
void pfe_class_cfg_rtable_lookup_disable(const addr_t base_va);

#ifdef PFE_CFG_TARGET_OS_AUTOSAR
#define ETH_43_PFE_STOP_SEC_CODE
#include "Eth_43_PFE_MemMap.h"
#endif /* PFE_CFG_TARGET_OS_AUTOSAR */

#endif /* PFE_CLASS_CSR_H_ */

