Clock_Ip_CgmXPcfsSdurDivcDiveDivs (const struct Clock_Ip_PcfsConfigType * Config)
{
  uint32 DivEndValue;
  uint32 DivStartValue;
  uint32 DivcRate;
  uint32 DivcInit;
  uint32 Sdur;
  uint32 K;
  uint32 Var3;
  uint32 Var2;
  uint32 Var1;
  uint32 Index;
  uint32 Rate;
  uint32 AmaxBrut;
  uint32 Fsafe;
  uint32 Finput;
  static uint32 Hash[52];
  static const uint32 PcfsRate[6] = {0, 12, 48, 112, 184, 1000};
  static const uint32 AMax[6] = {0, 5, 10, 15, 20, 100};
  uint32 HwIndex;
  volatile struct Clock_Ip_CgmPcfsType * CgmPcfsBase;
  <unnamed type> _1;
  int _2;
  unsigned char _3;
  int _4;
  <unnamed type> _5;
  int _6;
  unsigned char _7;
  <unnamed type> _8;
  int _9;
  unsigned char _10;
  int _11;
  long unsigned int _12;
  long unsigned int _13;
  long unsigned int _14;
  long unsigned int _15;
  <unnamed type> _16;
  long unsigned int _17;
  long unsigned int _18;
  <unnamed type> _19;
  long unsigned int _20;
  long unsigned int _21;
  long unsigned int _22;
  long unsigned int _23;
  long unsigned int _24;
  long unsigned int _25;
  long unsigned int _26;
  <unnamed type> _27;
  long unsigned int _28;
  long unsigned int _29;
  <unnamed type> _30;
  long unsigned int _31;
  long unsigned int _32;
  long unsigned int _33;
  <unnamed type> _34;
  int _35;
  unsigned char _36;
  int _37;
  long unsigned int _38;
  long unsigned int _39;
  long unsigned int _40;
  long unsigned int _41;
  long unsigned int _42;
  long unsigned int _43;
  long unsigned int _44;
  long unsigned int _45;
  long unsigned int _46;
  long unsigned int _47;
  long unsigned int _48;
  long unsigned int _49;
  long unsigned int _50;
  long unsigned int _51;
  long unsigned int _52;
  long unsigned int _53;
  long unsigned int _54;
  long unsigned int _55;
  long unsigned int _56;
  long unsigned int _57;
  long unsigned int _58;
  long unsigned int _59;
  long unsigned int _60;
  long unsigned int _61;
  long unsigned int _62;
  long unsigned int _63;
  long unsigned int _64;
  long unsigned int _65;
  long unsigned int _66;
  long unsigned int _67;
  long unsigned int _68;
  long unsigned int _69;
  long unsigned int _70;
  long unsigned int _71;
  long unsigned int _72;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = Config_85(D)->SelectorName;
  _2 = (int) _1;
  _3 = Clock_Ip_au8ClockFeatures[_2][0];
  _4 = (int) _3;
  CgmPcfsBase_86 = Clock_Ip_apxCgmPcfs[_4];
  # DEBUG CgmPcfsBase => CgmPcfsBase_86
  # DEBUG BEGIN_STMT
  _5 = Config_85(D)->Name;
  _6 = (int) _5;
  _7 = Clock_Ip_au8ClockFeatures[_6][7];
  HwIndex_87 = (uint32) _7;
  # DEBUG HwIndex => HwIndex_87
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  Finput_88 = 0;
  # DEBUG Finput => Finput_88
  # DEBUG BEGIN_STMT
  Fsafe_89 = 0;
  # DEBUG Fsafe => Fsafe_89
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  Rate_90 = 0;
  # DEBUG Rate => Rate_90
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  _8 = Config_85(D)->Name;
  _9 = (int) _8;
  _10 = Clock_Ip_au8ClockFeatures[_9][7];
  _11 = (int) _10;
  _12 = Hash[_11];
  _13 = Config_85(D)->ClockSourceFrequency;
  _14 = Config_85(D)->MaxAllowableIDDchange;
  _15 = _13 ^ _14;
  _16 = Config_85(D)->Name;
  _17 = (long unsigned int) _16;
  _18 = _15 ^ _17;
  _19 = Config_85(D)->SelectorName;
  _20 = (long unsigned int) _19;
  _21 = _18 ^ _20;
  _22 = Config_85(D)->StepDuration;
  _23 = _21 ^ _22;
  if (_12 != _23)
    goto <bb 3>; [INV]
  else
    goto <bb 20>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _24 = Config_85(D)->ClockSourceFrequency;
  _25 = Config_85(D)->MaxAllowableIDDchange;
  _26 = _24 ^ _25;
  _27 = Config_85(D)->Name;
  _28 = (long unsigned int) _27;
  _29 = _26 ^ _28;
  _30 = Config_85(D)->SelectorName;
  _31 = (long unsigned int) _30;
  _32 = _29 ^ _31;
  _33 = Config_85(D)->StepDuration;
  _34 = Config_85(D)->Name;
  _35 = (int) _34;
  _36 = Clock_Ip_au8ClockFeatures[_35][7];
  _37 = (int) _36;
  _38 = _32 ^ _33;
  Hash[_37] = _38;
  # DEBUG BEGIN_STMT
  _39 = Config_85(D)->ClockSourceFrequency;
  Finput_92 = _39 / 1000000;
  # DEBUG Finput => Finput_92
  # DEBUG BEGIN_STMT
  _40 = Clock_Ip_GetConfiguredFrequencyValue (0);
  Fsafe_94 = _40 / 1000000;
  # DEBUG Fsafe => Fsafe_94
  # DEBUG BEGIN_STMT
  _41 = Config_85(D)->MaxAllowableIDDchange;
  _42 = Config_85(D)->StepDuration;
  _43 = _41 * _42;
  _44 = _43 * 100000;
  _45 = Finput_92 * 2360;
  AmaxBrut_95 = _44 / _45;
  # DEBUG AmaxBrut => AmaxBrut_95
  # DEBUG BEGIN_STMT
  Rate_96 = AmaxBrut_95;
  # DEBUG Rate => Rate_96
  # DEBUG BEGIN_STMT
  _46 = AMax[0];
  if (AmaxBrut_95 < _46)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  # DEBUG BEGIN_STMT
  Rate_101 = PcfsRate[0];
  # DEBUG Rate => Rate_101
  goto <bb 12>; [INV]

  <bb 5> :
  # DEBUG BEGIN_STMT
  _47 = AMax[5];
  if (AmaxBrut_95 > _47)
    goto <bb 6>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 6> :
  # DEBUG BEGIN_STMT
  Rate_100 = PcfsRate[5];
  # DEBUG Rate => Rate_100
  goto <bb 12>; [INV]

  <bb 7> :
  # DEBUG BEGIN_STMT
  Index_97 = 1;
  # DEBUG Index => Index_97
  goto <bb 11>; [INV]

  <bb 8> :
  # DEBUG BEGIN_STMT
  _48 = Index_76 + 4294967295;
  _49 = AMax[_48];
  if (AmaxBrut_95 > _49)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  # DEBUG BEGIN_STMT
  Rate_98 = PcfsRate[Index_76];
  # DEBUG Rate => Rate_98

  <bb 10> :
  # Rate_73 = PHI <Rate_74(8), Rate_98(9)>
  # DEBUG Rate => Rate_73
  # DEBUG BEGIN_STMT
  Index_99 = Index_76 + 1;
  # DEBUG Index => Index_99

  <bb 11> :
  # Rate_74 = PHI <Rate_96(7), Rate_73(10)>
  # Index_76 = PHI <Index_97(7), Index_99(10)>
  # DEBUG Index => Index_76
  # DEBUG Rate => Rate_74
  # DEBUG BEGIN_STMT
  if (Index_76 <= 5)
    goto <bb 8>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 12> :
  # Rate_75 = PHI <Rate_101(4), Rate_100(6), Rate_74(11)>
  # DEBUG Rate => Rate_75
  # DEBUG BEGIN_STMT
  _50 = Finput_92 * 2048000;
  _51 = Fsafe_94 * Rate_75;
  _52 = _50 / _51;
  _53 = 2048000 / Rate_75;
  _54 = _52 - _53;
  Var1_102 = _54 + 256;
  # DEBUG Var1 => Var1_102
  # DEBUG BEGIN_STMT
  Var2_103 = 1073741824;
  # DEBUG Var2 => Var2_103
  # DEBUG BEGIN_STMT
  Var3_104 = 0;
  # DEBUG Var3 => Var3_104
  # DEBUG BEGIN_STMT
  goto <bb 14>; [INV]

  <bb 13> :
  # DEBUG BEGIN_STMT
  Var2_119 = Var2_79 >> 2;
  # DEBUG Var2 => Var2_119

  <bb 14> :
  # Var2_79 = PHI <Var2_103(12), Var2_119(13)>
  # DEBUG Var2 => Var2_79
  # DEBUG BEGIN_STMT
  if (Var2_79 > Var1_102)
    goto <bb 13>; [INV]
  else
    goto <bb 18>; [INV]

  <bb 15> :
  # DEBUG BEGIN_STMT
  _55 = Var3_82 + Var2_80;
  if (Var1_78 >= _55)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  # DEBUG BEGIN_STMT
  _56 = Var3_82 + Var2_80;
  Var1_115 = Var1_78 - _56;
  # DEBUG Var1 => Var1_115
  # DEBUG BEGIN_STMT
  _57 = Var2_80 << 1;
  Var3_116 = Var3_82 + _57;
  # DEBUG Var3 => Var3_116

  <bb 17> :
  # Var1_77 = PHI <Var1_78(15), Var1_115(16)>
  # Var3_81 = PHI <Var3_82(15), Var3_116(16)>
  # DEBUG Var3 => Var3_81
  # DEBUG Var1 => Var1_77
  # DEBUG BEGIN_STMT
  Var3_117 = Var3_81 >> 1;
  # DEBUG Var3 => Var3_117
  # DEBUG BEGIN_STMT
  Var2_118 = Var2_80 >> 2;
  # DEBUG Var2 => Var2_118

  <bb 18> :
  # Var1_78 = PHI <Var1_102(14), Var1_77(17)>
  # Var2_80 = PHI <Var2_79(14), Var2_118(17)>
  # Var3_82 = PHI <Var3_104(14), Var3_117(17)>
  # DEBUG Var3 => Var3_82
  # DEBUG Var2 => Var2_80
  # DEBUG Var1 => Var1_78
  # DEBUG BEGIN_STMT
  if (Var2_80 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 19> :
  # DEBUG BEGIN_STMT
  _58 = Var3_82 << 2;
  _59 = _58 + 191;
  K_105 = _59 >> 7;
  # DEBUG K => K_105
  # DEBUG BEGIN_STMT
  _60 = Config_85(D)->StepDuration;
  Sdur_106 = Fsafe_94 * _60;
  # DEBUG Sdur => Sdur_106
  # DEBUG BEGIN_STMT
  DivcInit_107 = Rate_75 * K_105;
  # DEBUG DivcInit => DivcInit_107
  # DEBUG BEGIN_STMT
  DivcRate_108 = Rate_75;
  # DEBUG DivcRate => DivcRate_108
  # DEBUG BEGIN_STMT
  _61 = Rate_75 * K_105;
  _62 = K_105 + 1;
  _63 = _61 * _62;
  _64 = _63 >> 1;
  DivStartValue_109 = _64 + 999;
  # DEBUG DivStartValue => DivStartValue_109
  # DEBUG BEGIN_STMT
  _65 = Finput_92 * 1000;
  _66 = _65 / Fsafe_94;
  DivEndValue_110 = _66 + 4294967295;
  # DEBUG DivEndValue => DivEndValue_110
  # DEBUG BEGIN_STMT
  _67 = Sdur_106 & 65535;
  CgmPcfsBase_86->PCFS_SDUR ={v} _67;
  # DEBUG BEGIN_STMT
  _68 = DivcRate_108 & 255;
  _69 = DivcInit_107 << 16;
  _70 = _68 | _69;
  CgmPcfsBase_86->PCFS[HwIndex_87].DIVC ={v} _70;
  # DEBUG BEGIN_STMT
  _71 = DivEndValue_110 & 1048575;
  CgmPcfsBase_86->PCFS[HwIndex_87].DIVE ={v} _71;
  # DEBUG BEGIN_STMT
  _72 = DivStartValue_109 & 1048575;
  CgmPcfsBase_86->PCFS[HwIndex_87].DIVS ={v} _72;

  <bb 20> :
  return;

}


Clock_Ip_ProgressiveFrequencyClockSwitchEmpty (const struct Clock_Ip_PcfsConfigType * Config)
{
  <bb 2> :
  # DEBUG BEGIN_STMT
  return;

}


