Clock_Ip_SetPlldigPll0divDeDivOutput (const struct Clock_Ip_DividerConfigType * Config)
{
  uint32 RegValue;
  uint32 DividerIndex;
  uint32 Instance;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = Config->Name;
  _2 = (int) _1;
  _3 = Clock_Ip_au8ClockFeatures[_2][0];
  Instance = (uint32) _3;
  # DEBUG BEGIN_STMT
  _4 = Config->Name;
  _5 = (int) _4;
  _6 = Clock_Ip_au8ClockFeatures[_5][5];
  DividerIndex = (uint32) _6;
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  _7 = Clock_Ip_pxPll[Instance];
  _8 = _7->PLLODIV[DividerIndex];
  _9 = Clock_Ip_pxPll[Instance];
  _10 = _8 & 2147483647;
  _9->PLLODIV[DividerIndex] = _10;
  # DEBUG BEGIN_STMT
  _11 = Config->Value;
  if (_11 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _12 = Clock_Ip_pxPll[Instance];
  RegValue = _12->PLLODIV[DividerIndex];
  # DEBUG BEGIN_STMT
  RegValue = RegValue | 2147483648;
  # DEBUG BEGIN_STMT
  RegValue = RegValue & 4278255615;
  # DEBUG BEGIN_STMT
  _13 = Config->Value;
  _14 = _13 + 4294967295;
  _15 = _14 << 16;
  _16 = _15 & 16711680;
  RegValue = RegValue | _16;
  # DEBUG BEGIN_STMT
  _17 = Clock_Ip_pxPll[Instance];
  _17->PLLODIV[DividerIndex] = RegValue;

  <bb 4> :
  return;

}


Clock_Ip_SetCgmXDeDivWithoutPhase (const struct Clock_Ip_DividerConfigType * Config)
{
  uint32 RegValue;
  uint32 DividerShift;
  uint32 DividerMask;
  uint32 DividerIndex;
  uint32 SelectorIndex;
  uint32 Instance;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = Config->Name;
  _2 = (int) _1;
  _3 = Clock_Ip_au8ClockFeatures[_2][0];
  Instance = (uint32) _3;
  # DEBUG BEGIN_STMT
  _4 = Config->Name;
  _5 = (int) _4;
  _6 = Clock_Ip_au8ClockFeatures[_5][4];
  SelectorIndex = (uint32) _6;
  # DEBUG BEGIN_STMT
  _7 = Config->Name;
  _8 = (int) _7;
  _9 = Clock_Ip_au8ClockFeatures[_8][5];
  DividerIndex = (uint32) _9;
  # DEBUG BEGIN_STMT
  _10 = Config->Name;
  _11 = (int) _10;
  _12 = Clock_Ip_au8ClockFeatures[_11][2];
  _13 = (int) _12;
  DividerMask = Clock_Ip_axFeatureExtensions[_13].DividerValueMask;
  # DEBUG BEGIN_STMT
  _14 = Config->Name;
  _15 = (int) _14;
  _16 = Clock_Ip_au8ClockFeatures[_15][2];
  _17 = (int) _16;
  DividerShift = Clock_Ip_axFeatureExtensions[_17].DividerValueShift;
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  _18 = Config->Value;
  if (_18 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _19 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  RegValue = _19->Divider[DividerIndex];
  # DEBUG BEGIN_STMT
  _20 = ~DividerMask;
  RegValue = RegValue & _20;
  # DEBUG BEGIN_STMT
  _21 = Config->Value;
  _22 = _21 + 4294967295;
  _23 = _22 << DividerShift;
  _24 = DividerMask & _23;
  RegValue = RegValue | _24;
  # DEBUG BEGIN_STMT
  _25 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _25->Divider[DividerIndex] = RegValue;

  <bb 4> :
  # DEBUG BEGIN_STMT
  _26 = Config->Value;
  if (_26 != 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  # DEBUG BEGIN_STMT
  _27 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _28 = _27->Divider[DividerIndex];
  _29 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _30 = _28 | 2147483648;
  _29->Divider[DividerIndex] = _30;
  goto <bb 7>; [INV]

  <bb 6> :
  # DEBUG BEGIN_STMT
  _31 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _32 = _31->Divider[DividerIndex];
  _33 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _34 = _32 & 2147483647;
  _33->Divider[DividerIndex] = _34;

  <bb 7> :
  return;

}


Clock_Ip_SetCgmXDeDivStatWithoutPhase (const struct Clock_Ip_DividerConfigType * Config)
{
  uint32 DividerStatus;
  uint32 TimeoutTicks;
  uint32 ElapsedTime;
  uint32 StartTime;
  boolean TimeoutOccurred;
  uint32 RegValue;
  uint32 DividerShift;
  uint32 DividerMask;
  uint32 DividerIndex;
  uint32 SelectorIndex;
  uint32 Instance;

  <bb 2> :
  # DEBUG BEGIN_STMT
  _1 = Config->Name;
  _2 = (int) _1;
  _3 = Clock_Ip_au8ClockFeatures[_2][0];
  Instance = (uint32) _3;
  # DEBUG BEGIN_STMT
  _4 = Config->Name;
  _5 = (int) _4;
  _6 = Clock_Ip_au8ClockFeatures[_5][4];
  SelectorIndex = (uint32) _6;
  # DEBUG BEGIN_STMT
  _7 = Config->Name;
  _8 = (int) _7;
  _9 = Clock_Ip_au8ClockFeatures[_8][5];
  DividerIndex = (uint32) _9;
  # DEBUG BEGIN_STMT
  _10 = Config->Name;
  _11 = (int) _10;
  _12 = Clock_Ip_au8ClockFeatures[_11][2];
  _13 = (int) _12;
  DividerMask = Clock_Ip_axFeatureExtensions[_13].DividerValueMask;
  # DEBUG BEGIN_STMT
  _14 = Config->Name;
  _15 = (int) _14;
  _16 = Clock_Ip_au8ClockFeatures[_15][2];
  _17 = (int) _16;
  DividerShift = Clock_Ip_axFeatureExtensions[_17].DividerValueShift;
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  TimeoutOccurred = 0;
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  _18 = Config->Value;
  if (_18 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  # DEBUG BEGIN_STMT
  _19 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  RegValue = _19->Divider[DividerIndex];
  # DEBUG BEGIN_STMT
  _20 = ~DividerMask;
  RegValue = RegValue & _20;
  # DEBUG BEGIN_STMT
  _21 = Config->Value;
  _22 = _21 + 4294967295;
  _23 = _22 << DividerShift;
  _24 = DividerMask & _23;
  RegValue = RegValue | _24;
  # DEBUG BEGIN_STMT
  _25 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _25->Divider[DividerIndex] = RegValue;

  <bb 4> :
  # DEBUG BEGIN_STMT
  Clock_Ip_StartTimeout (&StartTime, &ElapsedTime, &TimeoutTicks, 50000);

  <bb 5> :
  # DEBUG BEGIN_STMT
  # DEBUG BEGIN_STMT
  _26 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _27 = _26->MUX_DIV_UPD_STAT;
  DividerStatus = _27 & 1;
  # DEBUG BEGIN_STMT
  TimeoutTicks.0_28 = TimeoutTicks;
  TimeoutOccurred = Clock_Ip_TimeoutExpired (&StartTime, &ElapsedTime, TimeoutTicks.0_28);
  # DEBUG BEGIN_STMT
  if (DividerStatus == 1)
    goto <bb 6>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 6> :
  if (TimeoutOccurred == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 7> :
  # DEBUG BEGIN_STMT
  if (TimeoutOccurred == 0)
    goto <bb 8>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 8> :
  # DEBUG BEGIN_STMT
  _29 = Config->Value;
  if (_29 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  # DEBUG BEGIN_STMT
  _30 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _31 = _30->Divider[DividerIndex];
  _32 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _33 = _31 | 2147483648;
  _32->Divider[DividerIndex] = _33;
  goto <bb 12>; [INV]

  <bb 10> :
  # DEBUG BEGIN_STMT
  _34 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _35 = _34->Divider[DividerIndex];
  _36 = Clock_Ip_apxCgm[Instance][SelectorIndex];
  _37 = _35 & 2147483647;
  _36->Divider[DividerIndex] = _37;
  goto <bb 12>; [INV]

  <bb 11> :
  # DEBUG BEGIN_STMT
  _38 = Config->Name;
  Clock_Ip_ReportClockErrors (1, _38);

  <bb 12> :
  StartTime = {CLOBBER};
  ElapsedTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  return;

}


Clock_Ip_Callback_DividerEmpty (const struct Clock_Ip_DividerConfigType * Config)
{
  <bb 2> :
  # DEBUG BEGIN_STMT
  return;

}


