/*
 *  Copyright 2020-2022 NXP
 *
 *  NXP Confidential. This software is owned or controlled by NXP and may only
 *  be used strictly in accordance with the applicable license terms. By
 *  expressly accepting such terms or by downloading, installing, activating
 *  and/or otherwise using the software, you are agreeing that you have read,
 *  and that you agree to comply with and are bound by, such license terms. If
 *  you do not agree to be bound by the applicable license terms, then you may
 *  not retain, install, activate or otherwise use the software.
 *
 *  This file contains sample code only. It is not part of the production code deliverables.
 */

/*
* DIAB Linker Command File:
* 0x20100000	0x2010FFFF	64KB	M7_0 TCM Backdoor
* 0x20180000	0x2018FFFF	64KB	M7_1 TCM Backdoor
* 0x20200000	0x2020FFFF	64KB	M7_2 TCM Backdoor
* 0x24000000	0x33FFFFFF	262144	Standby RAM (32K)
* 0x34000000	0x34800000	8MB	Internal SRAM
*/

MEMORY
{
    int_itcm                : ORIGIN = 0x00000000, LENGTH = 0x00000000 /* 0KB - Not Supported */
    int_dtcm                : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* 64KB  */
    int_sram_shareable      : ORIGIN = 0x22C00000, LENGTH = 0x00004000 /* 16KB  */
    int_sram                : ORIGIN = 0x34000000, LENGTH = 0x001F0000 /* 2MB - 64KB  */
    int_sram_firmware       : ORIGIN = 0x341F0000, LENGTH = 0x00010000 /* PFE firmware 64KB */
    int_sram_rsvd           : ORIGIN = 0x34200000, LENGTH = 0x00200000 /* 2MB   */
    int_sram_stack_c0       : ORIGIN = 0x34400000, LENGTH = 0x00002000 /* 8KB   */
    int_sram_stack_c1       : ORIGIN = 0x34402000, LENGTH = 0x00002000 /* 8KB   */
    int_sram_stack_c2       : ORIGIN = 0x34404000, LENGTH = 0x00002000 /* 8KB   */
    int_sram_no_cache_rsvd  : ORIGIN = 0x34500000, LENGTH = 0x0004B000 /* 300KB */
    int_sram_no_cacheable   : ORIGIN = 0x3454B000, LENGTH = 0x000B5000 /* 724KB */
    int_sram_bmu_mem        : ORIGIN = 0x34600000, LENGTH = 0x00200000 /* 2MB   */
    ram_rsvd2               : ORIGIN = 0x34800000, LENGTH = 0          /* End of SRAM */

    LLCE_CAN_SHAREDMEMORY   : ORIGIN = 0x43800000 LENGTH = 0x3D000
    LLCE_LIN_SHAREDMEMORY   : ORIGIN = 0x4383D000 LENGTH = 0x3000
    LLCE_BOOT_END           : ORIGIN = 0x43840000 LENGTH = 0x50
}

SECTIONS
{
    GROUP :
    {
        .boot_header (COMMENT) :
        {
            *(.boot_header)
        }

        .text (TEXT) :
        {
            __wrs_text_start = .;
            . = ALIGN(4);
            KEEP(*(.core_loop))
            . = ALIGN(4);
            *(.startup)
            . = ALIGN(4);
            *(.systeminit)
            . = ALIGN(4);
            *(.text.startup)
            . = ALIGN(4);
            *(.text, ".text.*")
            . = ALIGN(4);
            *(.mcal_text)
            *(.rdata)
            *(.frame_info)
            *(.j_class_table)
            *(.rela.dyn)
            *(.rel.dyn)
            __wrs_text_end = .;
        }

        .rodata (TEXT) :
        {
            . = ALIGN(4);
            *(.rodata, ".rodata.*")
            . = ALIGN(4);
            *(.mcal_const_cfg)
            . = ALIGN(4);
            *(.mcal_const)
            . = ALIGN(4);
            __init_table = .;
            KEEP(*(.init_table))
            . = ALIGN(4);
            __zero_table = .;
            KEEP(*(.zero_table))
        }

        ARM.extab (TEXT) :
        {
            *(".ARM.extab*" ".gnu.linkonce.armextab.*")
        }

        .ARM.exidx (TEXT) :
        {
            *(".ARM.exidx*" ".gnu.linkonce.armexidx.*")
        }

        .ctors (=TEXT) ALIGN(4) : { ctordtor.o(.ctors) *(.ctors) }
        .init_array (=TEXT) ALIGN(4) : { ctordtor.o(.init_array) *(.init_array) }
        .dtors (=TEXT) ALIGN(4) : { ctordtor.o(.dtors) *(.dtors) }
        .fini_array (=TEXT) ALIGN(4) : { ctordtor.o(.fini_array) *(.fini_array) }

        .lib (TEXT) :
        {
            . = ALIGN(4);
            *(.init)                   /* section used in crtlibso.o files */
            *(.fini)                   /* section used in crtlibso.o files */
            *(.ctors)                  /* section used in ctordtor.o files */
            *(.dtors)                  /* section used in ctordtor.o files */
            . = ALIGN(4);
        }
        __etext = .;

        .ramcode (DATA) :
        {
            . = ALIGN(4);
            *(.acfls_code_rom)
            . = ALIGN(4);
            *(.aceep_code_rom)
            . = ALIGN(4);
            *(.acmcu_code_rom)
            . = ALIGN(4);
            *(.ramcode)
        }

        .data (DATA) :
        {
            . = ALIGN(4);
            *(.data, ".data.*")
            . = ALIGN(4);
            *(.mcal_data)
            . = ALIGN(16);
        }

        .bss (DATA) :
        {
            __sram_bss_start = .;
            *(.bss, ".bss.*")
            . = ALIGN(16);
            *(.mcal_bss)
            . = ALIGN(4);
            __sram_bss_end = .;
        }
    } > int_sram

    GROUP :
    {
        .rodata (TEXT):
        {
            . = ALIGN(4);
            *(.pfe_class_fw_mem)
            . = ALIGN(4);
        }
    } > int_sram_firmware

    GROUP :
    {
        .non_cacheable (DATA) :
        {
            /* Make sure that this section is placed within supported memory range 0x40000 to 0xBFFFFFFF */
            . = ALIGN(4);
            *(.pfe_buf_mem)
            . = ALIGN(4);
            *(.pfe_bd_mem)
            . = ALIGN(4);
            KEEP(*(.int_results))
            . += 0x100;
            . = ALIGN(4096);
            __interrupts_ram_start = .;
            KEEP(*(.intc_vector))
            . = ALIGN(16);
            __non_cacheable_bss_start = .;
            *(.mcal_bss_no_cacheable)
            . = ALIGN(4);
            __non_cacheable_bss_end = .;
            . = ALIGN(4);
            *(.mcal_data_no_cacheable)
            . = ALIGN(4);
            *(.mcal_const_no_cacheable)
            . = ALIGN(4096);
            *(.pfe_ddr_pool)
        }
    } > int_sram_no_cacheable

    GROUP :
    {
        .bmu_mem (DATA) :
        {
            /* The alignment must be at least : PFE_CFG_BMU2_BUF_COUNT * PFE_CFG_BMU2_BUF_SIZE */
            . = ALIGN(0x200000);
            KEEP(*(.pfe_bmu_mem))
        }
    } > int_sram_bmu_mem

    GROUP :
    {
        .llce_boot_end (DATA) :
        {
            KEEP(*(.llce_boot_end))
        }
    } > LLCE_BOOT_END

    GROUP :
    {
        .can_43_llce_sharedmemory (DATA) :
        {
            KEEP(*(.can_43_llce_sharedmemory))
        }
    } > LLCE_CAN_SHAREDMEMORY

    GROUP :
    {
        .lin_43_llce_sharedmemory (DATA) :
        {
            KEEP(*(.lin_43_llce_sharedmemory))
        }
    } > LLCE_LIN_SHAREDMEMORY

    GROUP :
    {
        .shareable (DATA) :
        {
            . = ALIGN(16);
            __shareable_bss_start = .;
            *(.mcal_shared_bss)
            . = ALIGN(4);
            __shareable_bss_end = .;
            . = ALIGN(16);
            *(.mcal_shared_data)
        }
    } > int_sram_shareable

    __Stack_end_c0           = ADDR(int_sram_stack_c0);
    __Stack_start_c0         = ADDR(int_sram_stack_c0) + SIZEOF(int_sram_stack_c0);
    __Stack_end_c1           = ADDR(int_sram_stack_c1);
    __Stack_start_c1         = ADDR(int_sram_stack_c1) + SIZEOF(int_sram_stack_c1);
    __Stack_end_c2           = ADDR(int_sram_stack_c2);
    __Stack_start_c2         = ADDR(int_sram_stack_c2) + SIZEOF(int_sram_stack_c2);
    __Stack_end_c3           = 0;
    __Stack_start_c3         = 0;

    __INT_SRAM_START         = ADDR(int_sram);
    __INT_SRAM_END           = ADDR(ram_rsvd2);

    __INT_ITCM_START         = ADDR(int_itcm);
    __INT_ITCM_END           = ADDR(int_itcm) + SIZEOF(int_itcm);

    __INT_DTCM_START         = ADDR(int_dtcm);
    __INT_DTCM_END           = ADDR(int_dtcm) + SIZEOF(int_dtcm);

    __RAM_SHAREABLE_START    = ADDR(int_sram_shareable);
    __RAM_SHAREABLE_END      = ADDR(int_sram_shareable) + SIZEOF(int_sram_shareable) - 1;
    __ROM_SHAREABLE_START    = 0;
    __ROM_SHAREABLE_END      = 0;
    __RAM_NO_CACHEABLE_START = ADDR(int_sram_no_cacheable);
    __RAM_NO_CACHEABLE_END   = ADDR(int_sram_no_cacheable) + SIZEOF(int_sram_no_cacheable) - 1;
    __ROM_NO_CACHEABLE_START = 0;
    __ROM_NO_CACHEABLE_END   = 0;
    __RAM_CACHEABLE_START    = ADDR(int_sram);
    __RAM_CACHEABLE_END      = ADDR(int_sram) + SIZEOF(int_sram) - 1;
    __ROM_CACHEABLE_START    = 0;
    __ROM_CACHEABLE_END      = 0;

    __BSS_SRAM_START         = __sram_bss_start;
    __BSS_SRAM_END           = __sram_bss_end;
    __BSS_SRAM_SIZE          = __sram_bss_end - __sram_bss_start;

    __BSS_SRAM_NC_START      = __non_cacheable_bss_start;
    __BSS_SRAM_NC_SIZE       = __non_cacheable_bss_end - __non_cacheable_bss_start;
    __BSS_SRAM_NC_END        = __non_cacheable_bss_end;

    __BSS_SRAM_SH_START      = __shareable_bss_start;
    __BSS_SRAM_SH_SIZE       = __shareable_bss_end - __shareable_bss_start;
    __BSS_SRAM_SH_END        = __shareable_bss_end;

    __RAM_INTERRUPT_START    = __interrupts_ram_start;
    __ROM_INTERRUPT_START    = 0;
    __ROM_INTERRUPT_END      = 0;

    __INIT_TABLE             = __init_table;
    __ZERO_TABLE             = __zero_table;

    __RAM_INIT               = 0;
    __ITCM_INIT              = 0;
    __DTCM_INIT              = 1;
}
