/*==================================================================================================
*   Project              : RTD AUTOSAR 4.4
*   Platform             : CORTEXM
*   Peripheral           : 
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 4.0.0
*   Build Version        : S32_RTD_4_0_0_D2210_ASR_REL_4_4_REV_0000_20221031
*
*   (c) Copyright 2022 NXP Semiconductors
*   All Rights Reserved.
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/


#ifdef __cplusplus
extern "C" {
#endif

/*==================================================================================================
                                         INCLUDE FILES
==================================================================================================*/
#include "IntCtrl_Ip_Cfg.h"
/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define PLATFORM_INTCTRL_IP_CFG_VENDOR_ID_C                          43
#define PLATFORM_INTCTRL_IP_CFG_SW_MAJOR_VERSION_C                   4
#define PLATFORM_INTCTRL_IP_CFG_SW_MINOR_VERSION_C                   0
#define PLATFORM_INTCTRL_IP_CFG_SW_PATCH_VERSION_C                   0
/*==================================================================================================
                                      FILE VERSION CHECKS
==================================================================================================*/
/* Check if current file and IntCtrl_Ip_Cfg header file are of the same vendor */
#if (PLATFORM_INTCTRL_IP_CFG_VENDOR_ID_C != PLATFORM_INTCTRL_IP_CFG_VENDOR_ID)
    #error "IntCtrl_Ip_Cfg.c and IntCtrl_Ip_Cfg.h have different vendor ids"
#endif

/* Check if current file and IntCtrl_Ip_Cfg header file are of the same Software version */
#if ((PLATFORM_INTCTRL_IP_CFG_SW_MAJOR_VERSION_C != PLATFORM_INTCTRL_IP_CFG_SW_MAJOR_VERSION) || \
     (PLATFORM_INTCTRL_IP_CFG_SW_MINOR_VERSION_C != PLATFORM_INTCTRL_IP_CFG_SW_MINOR_VERSION) || \
     (PLATFORM_INTCTRL_IP_CFG_SW_PATCH_VERSION_C != PLATFORM_INTCTRL_IP_CFG_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of IntCtrl_Ip_Cfg.c and IntCtrl_Ip_Cfg.h are different"
#endif
/*==================================================================================================
                                       GLOBAL VARIABLES
==================================================================================================*/
#define PLATFORM_START_SEC_CONFIG_DATA_UNSPECIFIED
#include "Platform_MemMap.h"

/* List of configurations for interrupts */
static const IntCtrl_Ip_IrqConfigType aIrqConfiguration[] = {
    {MSCM_Pcie_1_MSI_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT0_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT1_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT2_IRQn, (boolean)FALSE, 0U},
    {MSCM_Pcie_0_MSI_IRQn, (boolean)FALSE, 0U},
    {CTI_INT0_IRQn, (boolean)FALSE, 0U},
    {CTI_INT1_IRQn, (boolean)FALSE, 0U},
    {MCM_IRQn, (boolean)FALSE, 0U},
    {DMA0_0_15_IRQn, (boolean)FALSE, 0U},
    {DMA0_16_31_IRQn, (boolean)FALSE, 0U},
    {DMA0_ERR0_IRQn, (boolean)FALSE, 0U},
    {DMA1_0_15_IRQn, (boolean)FALSE, 0U},
    {DMA1_16_31_IRQn, (boolean)FALSE, 0U},
    {DMA1_ERR0_IRQn, (boolean)FALSE, 0U},
    {SWT0_IRQn, (boolean)FALSE, 0U},
    {SWT1_IRQn, (boolean)FALSE, 0U},
    {SWT2_IRQn, (boolean)FALSE, 0U},
    {SWT3_IRQn, (boolean)FALSE, 0U},
    {SWT4_IRQn, (boolean)FALSE, 0U},
    {SWT5_IRQn, (boolean)FALSE, 0U},
    {SWT6_IRQn, (boolean)FALSE, 0U},
    {SWT7_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT3_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT4_IRQn, (boolean)FALSE, 0U},
    {STM0_IRQn, (boolean)FALSE, 0U},
    {STM1_IRQn, (boolean)FALSE, 0U},
    {STM2_IRQn, (boolean)FALSE, 0U},
    {STM3_IRQn, (boolean)FALSE, 0U},
    {STM4_IRQn, (boolean)FALSE, 0U},
    {STM5_IRQn, (boolean)FALSE, 0U},
    {STM6_IRQn, (boolean)FALSE, 0U},
    {STM7_IRQn, (boolean)FALSE, 0U},
    {QSPI0_IRQn, (boolean)FALSE, 0U},
    {QSPI1_IRQn, (boolean)FALSE, 0U},
    {QSPI2_IRQn, (boolean)FALSE, 0U},
    {STCU2_LBIST_MBIST_IRQn, (boolean)FALSE, 0U},
    {USDHC_IRQn, (boolean)FALSE, 0U},
    {CAN0_ORED_IRQn, (boolean)FALSE, 0U},
    {CAN0_ERR_IRQn, (boolean)FALSE, 0U},
    {CAN0_ORED_0_7_MB_IRQn, (boolean)FALSE, 0U},
    {CAN0_ORED_8_127_MB_IRQn, (boolean)FALSE, 0U},
    {CAN1_ORED_IRQn, (boolean)FALSE, 0U},
    {CAN1_ERR_IRQn, (boolean)FALSE, 0U},
    {CAN1_ORED_0_7_MB_IRQn, (boolean)FALSE, 0U},
    {CAN1_ORED_8_127_MB_IRQn, (boolean)FALSE, 0U},
    {CAN2_ORED_IRQn, (boolean)FALSE, 0U},
    {CAN2_ERR_IRQn, (boolean)FALSE, 0U},
    {CAN2_ORED_0_7_MB_IRQn, (boolean)FALSE, 0U},
    {CAN2_ORED_8_127_MB_IRQn, (boolean)FALSE, 0U},
    {CAN3_ORED_IRQn, (boolean)FALSE, 0U},
    {CAN3_ERR_IRQn, (boolean)FALSE, 0U},
    {CAN3_ORED_0_7_MB_IRQn, (boolean)FALSE, 0U},
    {CAN3_ORED_8_127_MB_IRQn, (boolean)FALSE, 0U},
    {PIT0_IRQn, (boolean)FALSE, 0U},
    {PIT1_IRQn, (boolean)FALSE, 0U},
    {FTM0_IRQn, (boolean)FALSE, 0U},
    {FTM1_IRQn, (boolean)FALSE, 0U},
    {GMAC0_Common_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH0_TX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH0_RX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH1_TX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH1_RX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH2_TX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH2_RX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH3_TX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH3_RX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH4_TX_IRQn, (boolean)FALSE, 0U},
    {GMAC0_CH4_RX_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT5_IRQn, (boolean)FALSE, 0U},
    {MSCM_INT6_IRQn, (boolean)FALSE, 0U},
    {SAR_ADC0_INT_IRQn, (boolean)FALSE, 0U},
    {SAR_ADC1_INT_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_NCERR_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_CERR_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_CH0_RX_FIFO_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_CH1_RX_FIFO_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_WKUP_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_STATUS_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_CMBERR_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_TX_BUFF_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_RX_BUFF_IRQn, (boolean)FALSE, 0U},
    {FLEXRAY0_MODULE_IRQn, (boolean)FALSE, 0U},
    {LINFLEXD0_IRQn, (boolean)FALSE, 0U},
    {LINFLEXD1_IRQn, (boolean)FALSE, 0U},
    {LINFLEXD2_IRQn, (boolean)FALSE, 0U},
    {SPI0_IRQn, (boolean)FALSE, 0U},
    {SPI1_IRQn, (boolean)FALSE, 0U},
    {SPI2_IRQn, (boolean)FALSE, 0U},
    {SPI3_IRQn, (boolean)FALSE, 0U},
    {SPI4_IRQn, (boolean)FALSE, 0U},
    {SPI5_IRQn, (boolean)FALSE, 0U},
    {I2C0_IRQn, (boolean)FALSE, 0U},
    {I2C1_IRQn, (boolean)FALSE, 0U},
    {I2C2_IRQn, (boolean)FALSE, 0U},
    {I2C3_IRQn, (boolean)FALSE, 0U},
    {I2C4_IRQn, (boolean)FALSE, 0U},
    {MC_RGM_IRQn, (boolean)FALSE, 0U},
    {FCCU_ALARM_IRQn, (boolean)FALSE, 0U},
    {FCCU_MISC_IRQn, (boolean)FALSE, 0U},
    {SBSW_IRQn, (boolean)FALSE, 0U},
    {HSE_MU0_TX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU0_RX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU0_ORED_IRQn, (boolean)FALSE, 0U},
    {HSE_MU1_TX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU1_RX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU1_ORED_IRQn, (boolean)FALSE, 0U},
    {HSE_MU2_TX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU2_RX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU2_ORED_IRQn, (boolean)FALSE, 0U},
    {HSE_MU3_TX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU3_RX_IRQn, (boolean)FALSE, 0U},
    {HSE_MU3_ORED_IRQn, (boolean)FALSE, 0U},
    {DDR0_SCRUB_IRQn, (boolean)FALSE, 0U},
    {DDR0_PHY_IRQn, (boolean)FALSE, 0U},
    {CTU_FIFO_FULL_EMPTY_IRQn, (boolean)FALSE, 0U},
    {CTU_M_RELOAD_IRQn, (boolean)FALSE, 0U},
    {CTU_ERR_IRQn, (boolean)FALSE, 0U},
    {TMU_ALARM_IRQn, (boolean)FALSE, 0U},
    {RTC_SYS_CONT_IRQn, (boolean)FALSE, 0U},
    {PCIE0_ORED_DMA_IRQn, (boolean)FALSE, 0U},
    {PCIE0_LINK_IRQn, (boolean)FALSE, 0U},
    {PCIE0_AXI_MSI_IRQn, (boolean)FALSE, 0U},
    {PCIE0_PHY_DOWM_IRQn, (boolean)FALSE, 0U},
    {PCIE0_PHY_UP_IRQn, (boolean)FALSE, 0U},
    {PCIE0_INTA_IRQn, (boolean)FALSE, 0U},
    {PCIE0_INTB_IRQn, (boolean)FALSE, 0U},
    {PCIE0_INTC_IRQn, (boolean)FALSE, 0U},
    {PCIE0_INTD_IRQn, (boolean)FALSE, 0U},
    {PCIE0_MISC_IRQn, (boolean)FALSE, 0U},
    {PCIE0_PCS_IRQn, (boolean)FALSE, 0U},
    {PCIE0_TLP_NC_IRQn, (boolean)FALSE, 0U},
    {CORTEX_A53_ERR_L2RAM_CLUSTER0_IRQn, (boolean)FALSE, 0U},
    {CORTEX_A53_ERR_LIVLOCK_CLUSTER0_IRQn, (boolean)FALSE, 0U},
    {CORTEX_A53_ERR_L2RAM_CLUSTER1_IRQn, (boolean)FALSE, 0U},
    {CORTEX_A53_ERR_LIVLOCK_CLUSTER1_IRQn, (boolean)FALSE, 0U},
    {JDC_IRQn, (boolean)FALSE, 0U},
    {SWT8_IRQn, (boolean)FALSE, 0U},
    {SWT9_IRQn, (boolean)FALSE, 0U},
    {SWT10_IRQn, (boolean)FALSE, 0U},
    {SWT11_IRQn, (boolean)FALSE, 0U},
    {STM8_IRQn, (boolean)FALSE, 0U},
    {STM9_IRQn, (boolean)FALSE, 0U},
    {STM10_IRQn, (boolean)FALSE, 0U},
    {STM11_IRQn, (boolean)FALSE, 0U},
    {MCSCM_INT7_IRQn, (boolean)FALSE, 0U},
    {MCSCM_INT8_IRQn, (boolean)FALSE, 0U},
    {MCSCM_INT9_IRQn, (boolean)FALSE, 0U},
    {MCSCM_INT10_IRQn, (boolean)FALSE, 0U},
    {MCSCM_INT11_IRQn, (boolean)FALSE, 0U},
    {LLCE0_INT0_IRQn, (boolean)FALSE, 0U},
    {LLCE0_INT1_IRQn, (boolean)FALSE, 0U},
    {LLCE0_INT2_IRQn, (boolean)FALSE, 0U},
    {LLCE0_INT3_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR14_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR15_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR16_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR17_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR18_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR19_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR20_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR21_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR22_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR23_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR24_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR25_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR26_IRQn, (boolean)FALSE, 0U},
    {LLCE0_ICSR27_IRQn, (boolean)FALSE, 0U},
    {PFE0_CH0_STAT_IRQn, (boolean)FALSE, 0U},
    {PFE0_CH1_STAT_IRQn, (boolean)FALSE, 0U},
    {PFE0_CH2_STAT_IRQn, (boolean)FALSE, 0U},
    {PFE0_CH3_STAT_IRQn, (boolean)FALSE, 0U},
    {PFE0_BMU1_BMU2_IRQn, (boolean)FALSE, 0U},
    {PFE0_HIF_NC_IRQn, (boolean)FALSE, 0U},
    {PFE0_UT_GPT_IRQn, (boolean)FALSE, 0U},
    {PFE0_PMT_IRQn, (boolean)FALSE, 0U},
    {PFE0_ORED_IRQn, (boolean)FALSE, 0U},
    {STM_TS_CH_REQ_IRQn, (boolean)FALSE, 0U},
    {SIUL1_ORED_IRQn, (boolean)FALSE, 0U},
    {USB0_OTG_CORE_IRQn, (boolean)FALSE, 0U},
    {USB0_OTG_WKP_IRQn, (boolean)FALSE, 0U},
    {WKPU_GRP_IRQn, (boolean)FALSE, 0U},
    {PCIE1_ORED_DMA_IRQn, (boolean)FALSE, 0U},
    {PCIE1_STAT_IRQn, (boolean)FALSE, 0U},
    {PCIE1_AXI_MSI_IRQn, (boolean)FALSE, 0U},
    {PCIE1_PHY_LDOWN_IRQn, (boolean)FALSE, 0U},
    {PCIE1_PHY_LUP_IRQn, (boolean)FALSE, 0U},
    {PCIE1_INTA_IRQn, (boolean)FALSE, 0U},
    {PCIE1_INTB_IRQn, (boolean)FALSE, 0U},
    {PCIE1_INTC_IRQn, (boolean)FALSE, 0U},
    {PCIE1_INTD_IRQn, (boolean)FALSE, 0U},
    {PCIE1_MISC_IRQn, (boolean)FALSE, 0U},
    {PCIE1_PCS_IRQn, (boolean)FALSE, 0U},
    {PCIE1_TLP_IRQn, (boolean)FALSE, 0U},
    {XRDC_ERR_IRQn, (boolean)FALSE, 0U},
    {XRDC_MANAGER_ERR_IRQn, (boolean)FALSE, 0U},
};

/* Configuration structure for interrupt controller */
const IntCtrl_Ip_CtrlConfigType intCtrlConfig = {
    195U,
    
    aIrqConfiguration
    
};
    

#define PLATFORM_STOP_SEC_CONFIG_DATA_UNSPECIFIED
#include "Platform_MemMap.h"

#ifdef __cplusplus
}
#endif
