/**
*   @file    Reg_eSys_Dma.h
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcl - eDMA Registers and Macros Definitions.
*   @details eDMA Registers and Macros Definitions.
*
*   @addtogroup DMA_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

/**
@file        Reg_eSys_Dma.h
*/

#ifndef REG_ESYS_DMA_H
#define REG_ESYS_DMA_H


#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section Reg_eSys_Dma_h_REF_1
* Violates MISRA 2012 Advisory Directive 4.9, A function should be used in preference to a function-like macro where they are interchangeable.
* Function like macro are used to reduce code complexity.
*
* @section Reg_eSys_Dma_h_REF_2
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Declaration is reserved for future feature.
*/

/*==================================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/

#include "Reg_eSys.h"
#include "Reg_eSys_DmaV2.h"
#include "Reg_eSys_DmaV3.h"


/*==================================================================================================
*                               SOURCE FILE VERSION INFORMATION
==================================================================================================*/
/**
* @file           Reg_eSys_Dma.h
* @requirements
*/
#define DMA_VENDOR_ID_REG                       43
#define DMA_AR_RELEASE_MAJOR_VERSION_REG        4
#define DMA_AR_RELEASE_MINOR_VERSION_REG        3
#define DMA_AR_RELEASE_REVISION_VERSION_REG     1
#define DMA_SW_MAJOR_VERSION_REG                1
#define DMA_SW_MINOR_VERSION_REG                0
#define DMA_SW_PATCH_VERSION_REG                0


/*==================================================================================================
*                                      FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if header file and Reg_eSys.h header file are of the same Autosar version */
    #if ((REG_ESYS_AR_RELEASE_MAJOR_VERSION != DMA_AR_RELEASE_MAJOR_VERSION_REG) || \
         (REG_ESYS_AR_RELEASE_MINOR_VERSION != DMA_AR_RELEASE_MINOR_VERSION_REG))
        #error "AutoSar Version Numbers of Reg_eSys.h and Reg_eSys_Dma.h are different"
    #endif
#endif
/*==================================================================================================
*                                 GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/

/*==================================================================================================
*                                             ENUMS
==================================================================================================*/


/*==================================================================================================
*                                           CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                       DEFINES AND MACROS
==================================================================================================*/
#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)
/* for backward compatibility:
      - if DMA_NB_CONTOLERS not defined by Reg_eSys.h is supposed that only one controller exist
      - if MCL_DMA_INSTANCE_CHANNELS_NO not defined by Reg_eSys.h is supposed that DMA support only 16 channels*/

#ifndef MCL_DMA_NB_CONTROLLERS
    #define MCL_DMA_NB_CONTROLLERS                    (0x01U)
#endif

#ifndef MCL_DMA_INSTANCE_CHANNELS_NO
    #define MCL_DMA_INSTANCE_CHANNELS_NO              (0x10UL)
#endif

/**
* @brief Used to decide priority registers address based on endianess
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_BYTES_IN_WORD_U32                         (0x4UL)

/**
* @brief Macro to get the DMA Module address by module index.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_MOD_BASE_ADDR32(mIdx)               ((uint32)DMAV2_MOD_BASE_ADDR32(mIdx))
/**
* @brief macro to get the DMA Module base address by channel
* eDMAV2 channel numbers are ranging  from [MCL_EDMAV3_CHANNELS_NO to MCL_EDMA_TOTAL_CHANNELS_NO]
*/
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
#define DMA_MOD_BASE_CH_ADDR32(channel)         ((uint32)DMAV2_MOD_BASE_CH_ADDR32(channel))
/**
* @brief macro to get the DMA Module instance by channel
*/
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
#define DMA_MOD_IDX_U32(channel)                ((uint32)((channel)/MCL_DMAV2_INSTANCE_CHANNELS_NO))
/**
* @brief Mask used to limit channels to max channels available in one DMA instance
*/
#define DMA_CTRL_MAX_CHANNELS_MASK_U32          ((uint32)MCL_DMAV2_INSTANCE_CHANNELS_NO - 1U)
/**
* @brief Define for checking the module corresponding to a channel
*/
#define DMA_CHANNELS_PER_MODULE_U8          ((uint8)(MCL_DMA_INSTANCE_CHANNELS_NO))

/**
* @brief Define for checking the module DMAV2 corresponding to a channel
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMAV2_CHANNELS_PER_MODULE_U8          ((uint8)(MCL_DMAV2_INSTANCE_CHANNELS_NO))
/**
* @brief Mask used to limit minor loop offset to max offset value.
*/
#define DMA_TCD_MAX_MLOFF_MASK_U32          ((uint32)(0xFFFFFUL))

/**
* @brief Mask used to limit link channel value to max possible value.
*/
#define DMA_TCD_MAX_LINKCH_MASK_U32         ((uint32)MCL_DMAV2_INSTANCE_CHANNELS_NO -1U)
/**
* @brief Mask used to limit iterator value to max possible value.
*/
#define DMA_TCD_MAX_ITER_MASK_U32           ((uint32)(0x1FFUL))

/**
* @brief Mask used to limit minor loop bytes to transfer to max number of bytes.
*/
#define DMA_TCD_MAX_MLOFF_NBYTES_MASK_U16   ((uint16)(0x3FFUL))

/**
* @brief Mask used to limit the address modulo to max possible value.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_MAX_MOD_MASK_U16            ((uint16)(0x1FUL))

/**
* @brief Mask used to limit the transfer size to max possible value.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_MAX_SIZE_MASK_U16           ((uint16)(0x7UL))

/**
* @brief Mask used to limit the NBYTES to max possible value.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_MAX_NBYTES_MASK_U32         ((uint32)(0x3FFFFFFFUL))

/**
* @brief Mask used to select the priority from DCHPRI value
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_CH_PRI_MASK_U8                  ((uint8)(0x4UL))

/**
* @brief Mask used to select SMOD and SSIZE transfer attributes
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_SMOD_SSIZE_MASK_U16         ((uint16)(0xFF00UL))

/**
* @brief Mask used to select DMOD and DSIZE transfer attributes
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DMOD_DSIZE_MASK_U16         ((uint16)(0xFFUL))

/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_6TH_DEFAULT_VAL_U32         ((uint32) (0x00000000UL))
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_8TH_DEFAULT_VAL_U32         ((uint32) (0x00000000UL))
/** @brief Mask for SMOD_SSIZE in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_SMOD_SSIZE_MASK_U32         ((uint32)(0xFF000000UL))
/** @brief Mask for SOFF in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_TA_SOFF_MASK_U32            ((uint32)(0x0000FFFFUL))
/** @brief Mask for DOFF in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DOFF_MASK_U32               ((uint32)(0x0000FFFFUL))
/** @brief Mask for CITER in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_CITER_MASK_U32              ((uint32)(0xFFFF0000UL))
/** @brief Mask for CITER ELINK YES in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_CITER_ELINK_YES_MASK_U32    ((uint32)(0x01FF0000UL))
/** @brief Mask for CITER ELINK NO in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_CITER_ELINK_NO_MASK_U32     ((uint32)(0x7FFF0000UL))
/** @brief Mask for DMOD_DSIZE in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DMOD_DSIZE_MASK_U32         ((uint32)(0x00FF0000UL))
/** @brief Mask for BITER in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_BITER_MASK_U32              ((uint32)(0xFFFF0000UL))
/** @brief Mask for BITER in a 16-bit word */
#define DMA_TCD_BITER_ELINK_YES_MASK_U16    ((uint16)(0x01FFUL))
/** @brief Mask for BITER in a 16-bit word */
#define DMA_TCD_BITER_ELINK_NO_MASK_U16     ((uint16)(0x7FFFUL))
/** @brief Mask for FLAGS in a 32-bit word */
#define DMA_TCD_FLAGS_MASK_U32              ((uint32)(0x000000FFUL))
/** @brief Mask for MAJORLINCH in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_MAJORLINCH_MASK_U32         ((uint32)(0x00003F00))
/** @brief Mask for MAJOR_E_LINK in a 32-bit word */
#define DMA_TCD_MAJOR_E_LINK_MASK_U32       ((uint32)(0x00000020UL))
/** @brief Mask for E_SG in a 32-bit word */
#define DMA_TCD_E_SG_MASK_U32               ((uint32)(0x00000010UL))

/**
* @brief TCD address offset
*/
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
#define DMA_TCD_OFFSET_U32         (DMAV2_TCD_OFFSET_U32)
/** @brief Offset in words for DLAST_SGA in TCD */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DLAST_SGA_WORD_OFFSET_U32           ((uint32) 0x06UL)

/**
* @brief Offset to destination address field in TCD - Transfer Control Descriptor structure.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DADDR_WORD_OFFSET_U32               ((uint32) 0x04UL)

/**
* @brief Offset to destination address offset field in TCD - Transfer Control Descriptor structure.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DOFF_WORD_OFFSET_U32                ((uint32) 0x05UL)

/** @brief Offset of CITER in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_CITER_OFFSET_IN_WORD_U32            ((uint32) 0x10UL)

/** @brief Offset of SMOD_SSIZE in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_SMOD_SSIZE_OFFSET_IN_WORD_U32       ((uint32)(0x18UL))

/** @brief Offset of DMOD_DSIZE in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DMOD_DSIZE_OFFSET_IN_WORD_U32       ((uint32)(0x10UL))

/** @brief Offset in words for CITER in TCD */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_CITER_WORD_OFFSET_U32               ((uint32) 0x14UL)

/** @brief Offset in words for BITER in TCD */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_BITER_CCS_WORD_OFFSET_U32           ((uint32) 0x07UL)

/** @brief Offset of MAJORLINCH in a 32-bit word */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_MAJORLINKCH_OFFSET_IN_WORD_U32      ((uint32) 0x8UL)

#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)
    /** @brief Offset to tcd_csr from the 8th word */
    #define DMA_TCD_CSR_OFFSET_U32                  ((uint32) 0x1UL)
    /** @brief Offset to biter from the 8th word */
    #define DMA_TCD_BITER_OFFSET_U32                ((uint32) 0x2UL)
    /** @brief Offset to citer from the 6th word */
    #define DMA_TCD_CITER_OFFSET_U32                ((uint32) 0x2UL)
#else
    /** @brief Offset to tcd_csr from the 8th word */
    #define DMA_TCD_CSR_OFFSET_U32                  ((uint32) 0x2UL)
    /** @brief Offset to biter from the 8th word */
    #define DMA_TCD_BITER_OFFSET_U32                ((uint32) 0x0UL)
    /** @brief Offset to citer from the 6th word */
    #define DMA_TCD_CITER_OFFSET_U32                ((uint32) 0x0UL)
#endif

/**
* @brief Offset to Source address in TCD - Transfer Control Descriptor structure.
*/
#define DMA_TCD_1ST_WORD_OFFSET_U32                 ((uint32) 0x00UL)
/**
* @brief Offset to smod, ssize, dmod, dsize, soff fields in TCD-Transfer Control Descriptor structure.
*/
#define DMA_TCD_2ND_WORD_OFFSET_U32                 ((uint32) 0x04UL)
/**
* @brief Offset to smloe, dmloe, mloff, nbytes fields in TCD - Transfer Control Descriptor structure.
*/
#define DMA_TCD_3RD_WORD_OFFSET_U32                 ((uint32) 0x08UL)
/**
* @brief Offset to slast field in TCD - Transfer Control Descriptor structure.
*/
#define DMA_TCD_4TH_WORD_OFFSET_U32                 ((uint32) 0x0CUL)
/**
* @brief Offset to destination address field in TCD - Transfer Control Descriptor structure.
*/
#define DMA_TCD_5TH_WORD_OFFSET_U32                 ((uint32) 0x10UL)
/**
* @brief Offset to citer, doff fields in TCD - Transfer Control Descriptor structure.
*/
#define DMA_TCD_6TH_WORD_OFFSET_U32                 ((uint32) 0x14UL)
/**
* @brief Offset to dlast_sga field in TCD - Transfer Control Descriptor structure.
*/
#define DMA_TCD_7TH_WORD_OFFSET_U32                 ((uint32) 0x18UL)
/**
* @brief Offset to biter, channle control/status fields in TCD - Transfer Control Descriptor structure
*/
#define DMA_TCD_8TH_WORD_OFFSET_U32                 ((uint32) 0x1CUL)

/** @brief offset used in Tcd configuration functions to get each word's address */
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_1ST_WORD_ARRAY_OFFSET        (0UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_2ND_WORD_ARRAY_OFFSET        (1UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_3RD_WORD_ARRAY_OFFSET        (2UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_4TH_WORD_ARRAY_OFFSET        (3UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_5TH_WORD_ARRAY_OFFSET        (4UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_6TH_WORD_ARRAY_OFFSET        (5UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_7TH_WORD_ARRAY_OFFSET        (6UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_8TH_WORD_ARRAY_OFFSET        (7UL)

/** @brief ITER ELINK for setting ELINK in a TCD word */
#define DMA_TCD_ITER_ELINK_U32                      (0x80000000UL)

/** @brief ITER ELINK for setting ELINK in CITER or BITER */
#define DMA_TCD_ITER_ELINK_U16                      ((uint16)(0x8000L))

/** memory distance between two consecutive TCDs*/
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
#define DMA_TCD_GAP_U32(channel)                    (DMAV2_TCD_GAP_U32(channel))
 /** address of the TCD registers */
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
#define DMA_TCD(channel) \
    ((uint32)(DMA_MOD_BASE_CH_ADDR32((channel)) + DMA_TCD_OFFSET_U32 + \
    ((DMA_TCD_GAP_U32((channel))))))
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
#define DMA_TCD_CHANNEL(channel, offset) ((uint32)(DMA_TCD((channel)) + (offset)))

#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
    #define LITTLE_ENDIAN_FORMULA(byte) ((uint32)((uint32)(((uint32)(DMA_BYTES_IN_WORD_U32 * \
        ((uint32)((byte) / DMA_BYTES_IN_WORD_U32)))) + DMA_BYTES_IN_WORD_U32) -((uint32)((byte) % DMA_BYTES_IN_WORD_U32) + 1U)))
#endif

/**
* @{
* @brief masks used to set the DMA_CR common for fields.
*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_VLD_U32              ((uint32)0x80000000UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_SAE_U32              ((uint32)0x00000080UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_SOE_U32              ((uint32)0x00000040UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_DAE_U32              ((uint32)0x00000020UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_DOE_U32              ((uint32)0x00000010UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_NCE_U32              ((uint32)0x00000008UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_SGE_U32              ((uint32)0x00000004UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_SBE_U32              ((uint32)0x00000002UL)
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_DBE_U32              ((uint32)0x00000001UL)
#define DMA_ES_BUS_U32              ((uint32)0x00000003UL)
#define DMA_ES_DESCRIPTOR_U32       ((uint32)0x000000FCUL)
/* @violates @ref Reg_eSys_Dma_h_REF_1 MISRA 2012 Advisory 4.9*/
/* @violates @ref Reg_eSys_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ES_UCE_U32         (DMAV2_ES_UCE_U32)
/*==================================================================================================
*                                 STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/


/*==================================================================================================
*                                      FUNCTION PROTOTYPES
==================================================================================================*/
#endif
#endif
#ifdef __cplusplus
}
#endif


#endif /* REG_ESYS_DMA_H */

/** @} */

