/**
*   @file    Reg_eSys_DmaV2.h
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcl - eDMAV2 Registers and Macros Definitions.
*   @details eDMA Registers and Macros Definitions.
*
*   @addtogroup DMA_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

/**
@file        Reg_eSys_DmaV2.h
*/

#ifndef REG_ESYS_DMAV2_H
#define REG_ESYS_DMAV2_H


#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, A function should be used in preference to a function-like macro where they are interchangeable.
* Function like macro are used to reduce code complexity.
*
* @section Reg_eSys_DmaV2_h_REF_1
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Macros are used only in some configurations or for future releases.
*/
/*==================================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/

#include "Reg_eSys.h"


/*==================================================================================================
*                               SOURCE FILE VERSION INFORMATION
==================================================================================================*/
/**
* @file           Reg_eSys_Dma.h
* @requirements
*/

/*==================================================================================================
*                                 GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/

/*==================================================================================================
*                                             ENUMS
==================================================================================================*/


/*==================================================================================================
*                                           CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                       DEFINES AND MACROS
==================================================================================================*/
#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)

#ifndef DMA0_BASEADDR
    #define DMA0_BASEADDR  (0x01UL)
#endif
#ifndef DMA1_BASEADDR
    #define DMA1_BASEADDR  (0x01UL)
#endif
/**
* @brief Macro to get the DMA V2 Module address by module index.
*/
#define DMAV2_MOD_BASE_ADDR32(mIdx) \
    ((uint32)(((mIdx)>0UL) ? \
    (DMA1_BASEADDR) : (DMA0_BASEADDR)))

#define DMAV2_CR_ADDR32(mIdx)         ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx))))

#define DMAV2_ES_ADDR32(mIdx)         ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000004UL ))

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ERQH_ADDR32(mIdx)       ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000008UL ))

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ERQL_ADDR32(mIdx)       ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000000CUL ))

#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)
    /**
    * @{
    * @brief Macros used to get the DMA registers address by DMA index
    */

    #define DMAV2_SERQ_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001BUL ))

    #define DMAV2_CERQ_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001AUL ))

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_SEEI_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000019UL ))

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_CEEI_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000018UL ))

    #define DMAV2_CINT_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001FUL ))

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_CERR_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001EUL ))
#else

    #define DMAV2_SERQ_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000018UL ))

    #define DMAV2_CERQ_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000019UL ))
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_SEEI_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001AUL ))
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_CEEI_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001BUL ))

    #define DMAV2_CINT_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001CUL ))
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_CERR_ADDR32(mIdx)   ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000001DUL ))
#endif


#define DMAV2_INTH_ADDR32(mIdx)       ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000020UL ))

#define DMAV2_INTL_ADDR32(mIdx)      ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000024UL ))

#define DMAV2_EERH_ADDR32(mIdx)       ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x00000028UL ))

#define DMAV2_EERL_ADDR32(mIdx)       ((uint32)( DMAV2_MOD_BASE_ADDR32((mIdx)) + 0x0000002CUL ))

/**
* @brief TCD address offset for the eDMA2 IP version
*/
#define DMAV2_TCD_OFFSET_U32          ((uint32)(0x1000UL))

/**
* @brief Gap between TCD 0 and TCD of channel
* Gap between two TCD is 0x20
*/
#define DMAV2_TCD_GAP_U32(channel)    ((uint32)(((((uint32)channel) % MCL_DMAV2_INSTANCE_CHANNELS_NO) * ((uint32)0x20U))))
/**
* @brief default value for the DMA_CR register
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_DEFAULT_VAL_U32      ((uint32)(0x0000E400UL))

/**
* @brief Channel priority block address offset
*/
#define DMAV2_CPT_OFFSET_U32          ((uint32)(0x0100UL))

/**
* @brief Channel master ID replication address offset
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_DCHMID_OFFSET_U32       ((uint32)(0x0140UL))
/**
* @brief Enable Asynchronous Request address offset
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_EARS_OFFSET_U32         ((uint32)(0x44UL))

/**
* @{
* @brief DMA CERR CAEI mask.
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CERR_CAEI_U8            ((uint8)0x40UL)

/**
* @{
* @brief DMA_DCHPRI register bit masks.
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_DCHPRI_ECP_U8           ((uint8)0x80UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_DCHPRI_DPA_U8           ((uint8)0x40UL)
/** @} */
/**
* @{
* @brief DMA_ES register bit masks.
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ES_UCE_U32              ((uint32)0x00020000UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ES_ECX_U32              ((uint32)0x00010000UL)
#define DMAV2_ES_GPE_U32              ((uint32)0x00008000UL)
#define DMAV2_ES_CPE_U32              ((uint32)0x00004000UL)
#if (MCL_ENABLE_DMA == STD_ON)
#if ((MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON) || (MCL_DMA_GET_CH_ERR_STATUS_API == STD_ON) || (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON))

#if (MCL_DMA_INSTANCE_CHANNELS_NO == 0x40U)
    /* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_ES_ERRCHN_U32       ((uint32)0x00003F00UL)
#else
    /* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_ES_ERRCHN_U32       ((uint32)0x00001F00UL)
#endif

/**
* @{
* @brief DMA_ES register shift value.
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ES_ERRCHN_SHIFT_RIGTH_U8         ((uint8)8U)
#endif
#endif /*(MCL_ENABLE_DMA == STD_ON)*/

/**
* @{
* shift value used for GRPPRI bits from DMA_DCHPRI register
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_DCHPRI_GRPPRI_SHIFT_LEFT_U8      ((uint8)4U)

/**
* @{
* @brief masks used to set the DMA_CR fields.
*/
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_EBW_U32              ((uint32)0x00000001UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_EDBG_U32             ((uint32)0x00000002UL)
#define DMAV2_CR_ERCA_U32             ((uint32)0x00000004UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_ERGA_U32             ((uint32)0x00000008UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_HOE_U32              ((uint32)0x00000010UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_HALT_U32             ((uint32)0x00000020UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_CLM_U32              ((uint32)0x00000040UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_EMLM_U32             ((uint32)0x00000080UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP0PRI_0_U32           ((uint32)0x00000000UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP0PRI_1_U32           ((uint32)0x00000100UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP0PRI_2_U32           ((uint32)0x00000200UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP0PRI_3_U32           ((uint32)0x00000300UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP1PRI_0_U32           ((uint32)0x00000000UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP1PRI_1_U32           ((uint32)0x00000400UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP1PRI_2_U32           ((uint32)0x00000800UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_GRP1PRI_3_U32           ((uint32)0x00000C00UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_ECX_U32              ((uint32)0x00010000UL)
/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CR_CX_U32               ((uint32)0x00020000UL)

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_MOD_IDX_U32(channel) \
    ((uint32)((channel)/MCL_DMAV2_INSTANCE_CHANNELS_NO))

#define DMAV2_MOD_BASE_CH_ADDR32(channel) DMAV2_MOD_BASE_ADDR32(DMAV2_MOD_IDX_U32(channel))

/**
* @{
* @brief Low Level Macros used to access DMA registers for read/write operations.
*/
#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)

    #define DMAV2_CPR(channel) \
        ((uint32)(DMAV2_MOD_BASE_CH_ADDR32(channel) + DMAV2_CPT_OFFSET_U32 + \
        (LITTLE_ENDIAN_FORMULA((channel) & DMA_CTRL_MAX_CHANNELS_MASK_U32))))
#else

    #define DMAV2_CPR(channel) \
        ((uint32)(DMAV2_MOD_BASE_CH_ADDR32(channel) + DMAV2_CPT_OFFSET_U32 + \
        ((channel) & DMA_CTRL_MAX_CHANNELS_MASK_U32)))
#endif
#if (MCL_ENABLE_DMA == STD_ON)
#if (MCL_DMA_ENABLE_INIT_DCHMID == STD_ON)

/* @violates @ref Reg_eSys_DmaV2_h_REF_1 MISRA 2012 Advisory 2.5*/
    #define DMAV2_DCHMID(channel) \
        ((uint32)(DMAV2_MOD_BASE_CH_ADDR32(channel) + DMAV2_DCHMID_OFFSET_U32 + \
        (((channel)) & DMA_CTRL_MAX_CHANNELS_MASK_U32)))
#endif
#endif /*(MCL_ENABLE_DMA == STD_ON)*/

#ifdef MCL_DMA_SETUP_EARS
#if (MCL_DMA_SETUP_EARS == STD_ON)

    /** address of the EARS registers */
#define DMAV2_EARS(channel) \
        ((uint32)(DMAV2_MOD_BASE_CH_ADDR32(channel) + DMAV2_EARS_OFFSET_U32))
#endif
#endif


#endif
#endif  /*MCL_ENABLE_DMA*/
#ifdef __cplusplus
}
#endif

#endif /* REG_ESYS_DMAV2_H */

/** @} */
