/**
*   @file           Mcl_Dma_Irq.c
*   @version        1.0.0
*
*   @brief          AUTOSAR Mcl - Dma interrupt handler driver source file.
*   @details        Dma interrupt handling routines.
*
*   @addtogroup     MCL_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, Objects shall be defined at block scope if they are only accessed from within a single function.
* These objects are used in various parts of the code.
* @section [global]
* Violates MISRA 2012 Required Rule 14.4, the controlling expression of an if statement and the controlling expression of an iteration-statement shall have essentially Boolean type.
*SMCAL coding guideline, Rule 3.3:
* Multi-statement macros shall be wrapped in a do-while loop
* so the macro can appear safely inside if clauses or other places that expect a single statement or a statement block
*
* @section Mcl_DMA_Irq_c_REF_1
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer to object and an integer type.
* The cast is used to access memory mapped registers.
*
* @section Mcl_DMA_Irq_c_REF_2
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once.
* This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement [SWS_MemMap_00003].
*
* @section Mcl_DMA_Irq_c_REF_3
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void and an arithmetic type.
* This macro computes the address of any register by using the hardware offset of the controller. The address calculated as an unsigned int is passed to a macro for initializing the pointer with that address.
*
* @section Mcl_DMA_Irq_c_REF_4
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor directives or comments.
* <MA>_MemMap.h is included after each section define in order to set the current memory section as defined by AUTOSAR.
*
* @section Mcl_DMA_Irq_c_REF_5
* Violates MISRA 2012 Advisory Rule 13.4, The result of an assignment operator should not be used.
* They are use to reduce code complexity.
*
* @section Mcl_DMA_Irq_c_REF_6
* Violates MISRA 2012 Required Rule 10.8, The value of a composite expression shall no be cast to a different essential type category or a wider essential type.
* This violation is due to the complex expression (macro) is given as parameter is not evaluated at preprocessing step.
*
* @section Mcl_DMA_Irq_c_REF_7
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable code.
* This violation due to the fact that the value of defined macro is gotten from resource and always be a fixed value.
*
* @section Mcl_DMA_Irq_c_REF_8
* Violates MISRA 2012 Required Rule 14.3, Controlling expressions shall not be invariant.
* This violation due to the fact that the value of defined macro is gotten from resource and always be a fixed value.
*/

/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/

#include "Mcl_IPW_Notif.h"
#include "Reg_eSys_Dma.h"
#include "StdRegMacros.h"

#include "Mcal.h"
#include "Mcl_Dma_Types.h"
#include "Mcl_Dma.h"
#include "Mcl_IPW.h"
#include "CDD_Mcl_Cfg.h"
/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define MCL_DMA_IRQ_VENDOR_ID_C                       43
#define MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C        4
#define MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C        3
#define MCL_DMA_IRQ_AR_RELEASE_REVISION_VERSION_C     1
#define MCL_DMA_IRQ_SW_MAJOR_VERSION_C                1
#define MCL_DMA_IRQ_SW_MINOR_VERSION_C                0
#define MCL_DMA_IRQ_SW_PATCH_VERSION_C                0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/

/* Check if current file and Mcl_IPW_Notif.h file are of the same vendor */
#if (MCL_DMA_IRQ_VENDOR_ID_C != MCL_IPW_NOTIF_VENDOR_ID)
    #error "Mcl_Dma_Irq.c and Mcl_IPW_Notif.h have different vendor ids"
#endif
/* Check if source file and Mcl_IPW_Notif.h file are of the same Autosar version */
#if ((MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C    != MCL_IPW_NOTIF_AR_RELEASE_MAJOR_VERSION) || \
     (MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C    != MCL_IPW_NOTIF_AR_RELEASE_MINOR_VERSION)|| \
     (MCL_DMA_IRQ_AR_RELEASE_REVISION_VERSION_C != MCL_IPW_NOTIF_AR_RELEASE_REVISION_VERSION))
    #error "AutoSar Version Numbers of Mcl_Dma_Irq.c and Mcl_IPW_Notif.h are different"
#endif

/* Check if source file and Mcl_IPW_Notif.h file are of the same software version */
#if ((MCL_DMA_IRQ_SW_MAJOR_VERSION_C != MCL_IPW_NOTIF_SW_MAJOR_VERSION) || \
     (MCL_DMA_IRQ_SW_MINOR_VERSION_C != MCL_IPW_NOTIF_SW_MINOR_VERSION)|| \
     (MCL_DMA_IRQ_SW_PATCH_VERSION_C != MCL_IPW_NOTIF_SW_PATCH_VERSION))
    #error "Software Version Numbers of Mcl_Dma_Irq.c and Mcl_IPW_Notif.h are different"
#endif


/* Check if current file and Reg_sSys_Dma.h file are of the same vendor */
#if (MCL_DMA_IRQ_VENDOR_ID_C != DMA_VENDOR_ID_REG)
    #error "Mcl_Dma_Irq.c and Reg_sSys_Dma.h have different vendor ids"
#endif
/* Check if source file and Reg_sSys_Dma.h file are of the same Autosar version */
#if ((MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C    != DMA_AR_RELEASE_MAJOR_VERSION_REG) || \
     (MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C    != DMA_AR_RELEASE_MINOR_VERSION_REG)|| \
     (MCL_DMA_IRQ_AR_RELEASE_REVISION_VERSION_C != DMA_AR_RELEASE_REVISION_VERSION_REG))
    #error "AutoSar Version Numbers of Mcl_Dma_Irq.c and Reg_sSys_Dma.h are different"
#endif

/* Check if source file and Reg_sSys_Dma.h file are of the same software version */
#if ((MCL_DMA_IRQ_SW_MAJOR_VERSION_C != DMA_SW_MAJOR_VERSION_REG) || \
     (MCL_DMA_IRQ_SW_MINOR_VERSION_C != DMA_SW_MINOR_VERSION_REG)|| \
     (MCL_DMA_IRQ_SW_PATCH_VERSION_C != DMA_SW_PATCH_VERSION_REG))
    #error "Software Version Numbers of Mcl_Dma_Irq.c and Reg_sSys_Dma.h are different"
#endif
/* Check if source file and Mcl_Dma header file are of the same vendor */
#if (MCL_DMA_IRQ_VENDOR_ID_C != MCL_DMA_VENDOR_ID)
    #error "Mcl_Dma_Irq.c and Mcl_Dma.h have different vendor IDs"
#endif
/* Check if source file and Mcl_Dma header file are of the same Autosar version */
#if ((MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C != MCL_DMA_AR_RELEASE_MAJOR_VERSION) || \
     (MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C != MCL_DMA_AR_RELEASE_MINOR_VERSION) || \
     (MCL_DMA_IRQ_AR_RELEASE_REVISION_VERSION_C != MCL_DMA_AR_RELEASE_REVISION_VERSION))
    #error "AutoSar Version Numbers of Mcl_Dma.h and Mcl_Dma_Irq.c are different"
#endif
/* Check if source file and Mcl_Dma header file are of the same Software version */
#if ((MCL_DMA_IRQ_SW_MAJOR_VERSION_C != MCL_DMA_SW_MAJOR_VERSION) || \
     (MCL_DMA_IRQ_SW_MINOR_VERSION_C != MCL_DMA_SW_MINOR_VERSION) || \
     (MCL_DMA_IRQ_SW_PATCH_VERSION_C != MCL_DMA_SW_PATCH_VERSION))
    #error "Software Version Numbers of Mcl_Dma.h and Mcl_Dma_Irq.c are different"
#endif

/* Check if header file and Mcl_Dma_Types.h header file are of the same vendor */
#if (MCL_DMA_IRQ_VENDOR_ID_C != MCL_DMA_TYPES_VENDOR_ID)
    #error "Mcl_Dma_Irq.c and Mcl_Dma_Types.h have different vendor ids"
#endif
/* Check if header file and Mcl_Dma_Types.h header file are of the same Autosar version */
#if ((MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C    != MCL_DMA_TYPES_AR_RELEASE_MAJOR_VERSION) || \
     (MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C    != MCL_DMA_TYPES_AR_RELEASE_MINOR_VERSION) || \
     (MCL_DMA_IRQ_AR_RELEASE_REVISION_VERSION_C != MCL_DMA_TYPES_AR_RELEASE_REVISION_VERSION))
    #error "AutoSar Version Numbers of Mcl_Dma_Irq.c and Mcl_Dma_Types.h are different"
#endif
/* Check if header file and Mcl_Dma_Types.h header file are of the same software version */
#if ((MCL_DMA_IRQ_SW_MAJOR_VERSION_C != MCL_DMA_TYPES_SW_MAJOR_VERSION) || \
     (MCL_DMA_IRQ_SW_MINOR_VERSION_C != MCL_DMA_TYPES_SW_MINOR_VERSION) || \
     (MCL_DMA_IRQ_SW_PATCH_VERSION_C != MCL_DMA_TYPES_SW_PATCH_VERSION))
    #error "Software Version Numbers of Mcl_Dma_Irq.c and Mcl_Dma_Types.h are different"
#endif

/* Check if source file and Mcal header file are of the same Autosar version */
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    #if ((MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
         (MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Mcl_Dma_Irq.c and Mcal.h are different"
    #endif
#endif

/* Check if source file and StdRegMacros header file are of the same Autosar version */
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    #if ((MCL_DMA_IRQ_AR_RELEASE_MAJOR_VERSION_C != STDREGMACROS_AR_RELEASE_MAJOR_VERSION) || \
         (MCL_DMA_IRQ_AR_RELEASE_MINOR_VERSION_C != STDREGMACROS_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Mcl_Dma_Irq.cand StdRegMacros.h are different"
    #endif
#endif


/*==================================================================================================
*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/

/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/

/*==================================================================================================
*                                      LOCAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      LOCAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                      GLOBAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      GLOBAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/
#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
    #if ((MCL_DMA_COMBINED_TR_COMPLETION_ISR == STD_ON) || (MCL_DMA_TR_COMPLETION_MIXED_ISR == STD_ON) || (MCL_DMA_COMBINED_GROUP_COMPLETION_ISR == STD_ON))
    LOCAL_INLINE FUNC (void, MCL_CODE) Mcl_DmaProcessCombinedInterrupt
    (
        VAR(Mcl_DmaInstanceType, AUTOMATIC) DmaHwInstance
    );
    #endif
    #if (MCL_DMA_TR_SEPARATED_ISR == STD_ON)
    LOCAL_INLINE FUNC (void, MCL_CODE) Mcl_DmaProcessInterrupt
    (
        VAR(Mcl_DmaChannelType, AUTOMATIC) HwChannel
    );
    #endif
#endif

#if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
LOCAL_INLINE FUNC (void, MCL_CODE) Mcl_DmaProcessErrorInterrupt
(
    VAR(Mcl_DmaInstanceType, AUTOMATIC) DmaHwInstance
);
#endif /* ( MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON ) */

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
    #if (MCL_DMA_COMBINED_TR_COMPLETION_ISR == STD_ON)
    ISR(MCL_DMA0_CH_COMPLETE_ISR);
    #if (MCL_DMA_NB_CONTROLLERS == 0x02U)
    ISR(MCL_DMA1_CH_COMPLETE_ISR);
    #endif
    #endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
    #if (MCL_DMA_COMBINED_GROUP_COMPLETION_ISR == STD_ON)
    #ifdef MCL_DMA_GROUP0_ISR_USED
    ISR(MCL_DMA_GROUP0_COMPLETE_ISR);
    #endif
    #ifdef MCL_DMA_GROUP1_ISR_USED
    ISR(MCL_DMA_GROUP1_COMPLETE_ISR);
    #endif
    #ifdef MCL_DMA_GROUP2_ISR_USED
    ISR(MCL_DMA_GROUP2_COMPLETE_ISR);
    #endif
    #ifdef MCL_DMA_GROUP3_ISR_USED
    ISR(MCL_DMA_GROUP3_COMPLETE_ISR);
    #endif
    #endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
    #if (MCL_DMA_TR_COMPLETION_MIXED_ISR == STD_ON)
        ISR(MCL_DMA_CH_MIXED_96_127_COMPLETE_ISR);
    #endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
    #if (MCL_DMA_TR_SEPARATED_ISR == STD_ON)

    #ifdef MCL_DMA_CH_0_ISR_USED
    ISR(MCL_DMA_CH_0_ISR);
    #endif
    #ifdef MCL_DMA_CH_1_ISR_USED
    ISR(MCL_DMA_CH_1_ISR);
    #endif
    #ifdef MCL_DMA_CH_2_ISR_USED
    ISR(MCL_DMA_CH_2_ISR);
    #endif
    #ifdef MCL_DMA_CH_3_ISR_USED
    ISR(MCL_DMA_CH_3_ISR);
    #endif
    #ifdef MCL_DMA_CH_4_ISR_USED
    ISR(MCL_DMA_CH_4_ISR);
    #endif
    #ifdef MCL_DMA_CH_5_ISR_USED
    ISR(MCL_DMA_CH_5_ISR);
    #endif
    #ifdef MCL_DMA_CH_6_ISR_USED
    ISR(MCL_DMA_CH_6_ISR);
    #endif
    #ifdef MCL_DMA_CH_7_ISR_USED
    ISR(MCL_DMA_CH_7_ISR);
    #endif
    #ifdef MCL_DMA_CH_8_ISR_USED
    ISR(MCL_DMA_CH_8_ISR);
    #endif
    #ifdef MCL_DMA_CH_9_ISR_USED
    ISR(MCL_DMA_CH_9_ISR);
    #endif
    #ifdef MCL_DMA_CH_10_ISR_USED
    ISR(MCL_DMA_CH_10_ISR);
    #endif
    #ifdef MCL_DMA_CH_11_ISR_USED
    ISR(MCL_DMA_CH_11_ISR);
    #endif
    #ifdef MCL_DMA_CH_12_ISR_USED
    ISR(MCL_DMA_CH_12_ISR);
    #endif
    #ifdef MCL_DMA_CH_13_ISR_USED
    ISR(MCL_DMA_CH_13_ISR);
    #endif
    #ifdef MCL_DMA_CH_14_ISR_USED
    ISR(MCL_DMA_CH_14_ISR);
    #endif
    #ifdef MCL_DMA_CH_15_ISR_USED
    ISR(MCL_DMA_CH_15_ISR);
    #endif
    #ifdef MCL_DMA_CH_16_ISR_USED
    ISR(MCL_DMA_CH_16_ISR);
    #endif
    #ifdef MCL_DMA_CH_17_ISR_USED
    ISR(MCL_DMA_CH_17_ISR);
    #endif
    #ifdef MCL_DMA_CH_18_ISR_USED
    ISR(MCL_DMA_CH_18_ISR);
    #endif
    #ifdef MCL_DMA_CH_19_ISR_USED
    ISR(MCL_DMA_CH_19_ISR);
    #endif
    #ifdef MCL_DMA_CH_20_ISR_USED
    ISR(MCL_DMA_CH_20_ISR);
    #endif
    #ifdef MCL_DMA_CH_21_ISR_USED
    ISR(MCL_DMA_CH_21_ISR);
    #endif
    #ifdef MCL_DMA_CH_22_ISR_USED
    ISR(MCL_DMA_CH_22_ISR);
    #endif
    #ifdef MCL_DMA_CH_23_ISR_USED
    ISR(MCL_DMA_CH_23_ISR);
    #endif
    #ifdef MCL_DMA_CH_24_ISR_USED
    ISR(MCL_DMA_CH_24_ISR);
    #endif
    #ifdef MCL_DMA_CH_25_ISR_USED
    ISR(MCL_DMA_CH_25_ISR);
    #endif
    #ifdef MCL_DMA_CH_26_ISR_USED
    ISR(MCL_DMA_CH_26_ISR);
    #endif
    #ifdef MCL_DMA_CH_27_ISR_USED
    ISR(MCL_DMA_CH_27_ISR);
    #endif
    #ifdef MCL_DMA_CH_28_ISR_USED
    ISR(MCL_DMA_CH_28_ISR);
    #endif
    #ifdef MCL_DMA_CH_29_ISR_USED
    ISR(MCL_DMA_CH_29_ISR);
    #endif
    #ifdef MCL_DMA_CH_30_ISR_USED
    ISR(MCL_DMA_CH_30_ISR);
    #endif
    #ifdef MCL_DMA_CH_31_ISR_USED
    ISR(MCL_DMA_CH_31_ISR);
    #endif
    #ifdef MCL_DMA_CH_32_ISR_USED
    ISR(MCL_DMA_CH_32_ISR);
    #endif
    #ifdef MCL_DMA_CH_33_ISR_USED
    ISR(MCL_DMA_CH_33_ISR);
    #endif
    #ifdef MCL_DMA_CH_34_ISR_USED
    ISR(MCL_DMA_CH_34_ISR);
    #endif
    #ifdef MCL_DMA_CH_35_ISR_USED
    ISR(MCL_DMA_CH_35_ISR);
    #endif
    #ifdef MCL_DMA_CH_36_ISR_USED
    ISR(MCL_DMA_CH_36_ISR);
    #endif
    #ifdef MCL_DMA_CH_37_ISR_USED
    ISR(MCL_DMA_CH_37_ISR);
    #endif
    #ifdef MCL_DMA_CH_38_ISR_USED
    ISR(MCL_DMA_CH_38_ISR);
    #endif
    #ifdef MCL_DMA_CH_39_ISR_USED
    ISR(MCL_DMA_CH_39_ISR);
    #endif
    #ifdef MCL_DMA_CH_40_ISR_USED
    ISR(MCL_DMA_CH_40_ISR);
    #endif
    #ifdef MCL_DMA_CH_41_ISR_USED
    ISR(MCL_DMA_CH_41_ISR);
    #endif
    #ifdef MCL_DMA_CH_42_ISR_USED
    ISR(MCL_DMA_CH_42_ISR);
    #endif
    #ifdef MCL_DMA_CH_43_ISR_USED
    ISR(MCL_DMA_CH_43_ISR);
    #endif
    #ifdef MCL_DMA_CH_44_ISR_USED
    ISR(MCL_DMA_CH_44_ISR);
    #endif
    #ifdef MCL_DMA_CH_45_ISR_USED
    ISR(MCL_DMA_CH_45_ISR);
    #endif
    #ifdef MCL_DMA_CH_46_ISR_USED
    ISR(MCL_DMA_CH_46_ISR);
    #endif
    #ifdef MCL_DMA_CH_47_ISR_USED
    ISR(MCL_DMA_CH_47_ISR);
    #endif
    #ifdef MCL_DMA_CH_48_ISR_USED
    ISR(MCL_DMA_CH_48_ISR);
    #endif
    #ifdef MCL_DMA_CH_49_ISR_USED
    ISR(MCL_DMA_CH_49_ISR);
    #endif
    #ifdef MCL_DMA_CH_50_ISR_USED
    ISR(MCL_DMA_CH_50_ISR);
    #endif
    #ifdef MCL_DMA_CH_51_ISR_USED
    ISR(MCL_DMA_CH_51_ISR);
    #endif
    #ifdef MCL_DMA_CH_52_ISR_USED
    ISR(MCL_DMA_CH_52_ISR);
    #endif
    #ifdef MCL_DMA_CH_53_ISR_USED
    ISR(MCL_DMA_CH_53_ISR);
    #endif
    #ifdef MCL_DMA_CH_54_ISR_USED
    ISR(MCL_DMA_CH_54_ISR);
    #endif
    #ifdef MCL_DMA_CH_55_ISR_USED
    ISR(MCL_DMA_CH_55_ISR);
    #endif
    #ifdef MCL_DMA_CH_56_ISR_USED
    ISR(MCL_DMA_CH_56_ISR);
    #endif
    #ifdef MCL_DMA_CH_57_ISR_USED
    ISR(MCL_DMA_CH_57_ISR);
    #endif
    #ifdef MCL_DMA_CH_58_ISR_USED
    ISR(MCL_DMA_CH_58_ISR);
    #endif
    #ifdef MCL_DMA_CH_59_ISR_USED
    ISR(MCL_DMA_CH_59_ISR);
    #endif
    #ifdef MCL_DMA_CH_60_ISR_USED
    ISR(MCL_DMA_CH_60_ISR);
    #endif
    #ifdef MCL_DMA_CH_61_ISR_USED
    ISR(MCL_DMA_CH_61_ISR);
    #endif
    #ifdef MCL_DMA_CH_62_ISR_USED
    ISR(MCL_DMA_CH_62_ISR);
    #endif
    #ifdef MCL_DMA_CH_63_ISR_USED
    ISR(MCL_DMA_CH_63_ISR);
    #endif
    #ifdef MCL_DMA_CH_64_ISR_USED
    ISR(MCL_DMA_CH_64_ISR);
    #endif
    #ifdef MCL_DMA_CH_65_ISR_USED
    ISR(MCL_DMA_CH_65_ISR);
    #endif
    #ifdef MCL_DMA_CH_66_ISR_USED
    ISR(MCL_DMA_CH_66_ISR);
    #endif
    #ifdef MCL_DMA_CH_67_ISR_USED
    ISR(MCL_DMA_CH_67_ISR);
    #endif
    #ifdef MCL_DMA_CH_68_ISR_USED
    ISR(MCL_DMA_CH_68_ISR);
    #endif
    #ifdef MCL_DMA_CH_69_ISR_USED
    ISR(MCL_DMA_CH_69_ISR);
    #endif
    #ifdef MCL_DMA_CH_70_ISR_USED
    ISR(MCL_DMA_CH_70_ISR);
    #endif
    #ifdef MCL_DMA_CH_71_ISR_USED
    ISR(MCL_DMA_CH_71_ISR);
    #endif
    #ifdef MCL_DMA_CH_72_ISR_USED
    ISR(MCL_DMA_CH_72_ISR);
    #endif
    #ifdef MCL_DMA_CH_73_ISR_USED
    ISR(MCL_DMA_CH_73_ISR);
    #endif
    #ifdef MCL_DMA_CH_74_ISR_USED
    ISR(MCL_DMA_CH_74_ISR);
    #endif
    #ifdef MCL_DMA_CH_75_ISR_USED
    ISR(MCL_DMA_CH_75_ISR);
    #endif
    #ifdef MCL_DMA_CH_76_ISR_USED
    ISR(MCL_DMA_CH_76_ISR);
    #endif
    #ifdef MCL_DMA_CH_77_ISR_USED
    ISR(MCL_DMA_CH_77_ISR);
    #endif
    #ifdef MCL_DMA_CH_78_ISR_USED
    ISR(MCL_DMA_CH_78_ISR);
    #endif
    #ifdef MCL_DMA_CH_79_ISR_USED
    ISR(MCL_DMA_CH_79_ISR);
    #endif
    #ifdef MCL_DMA_CH_80_ISR_USED
    ISR(MCL_DMA_CH_80_ISR);
    #endif
    #ifdef MCL_DMA_CH_81_ISR_USED
    ISR(MCL_DMA_CH_81_ISR);
    #endif
    #ifdef MCL_DMA_CH_82_ISR_USED
    ISR(MCL_DMA_CH_82_ISR);
    #endif
    #ifdef MCL_DMA_CH_83_ISR_USED
    ISR(MCL_DMA_CH_83_ISR);
    #endif
    #ifdef MCL_DMA_CH_84_ISR_USED
    ISR(MCL_DMA_CH_84_ISR);
    #endif
    #ifdef MCL_DMA_CH_85_ISR_USED
    ISR(MCL_DMA_CH_85_ISR);
    #endif
    #ifdef MCL_DMA_CH_86_ISR_USED
    ISR(MCL_DMA_CH_86_ISR);
    #endif
    #ifdef MCL_DMA_CH_87_ISR_USED
    ISR(MCL_DMA_CH_87_ISR);
    #endif
    #ifdef MCL_DMA_CH_88_ISR_USED
    ISR(MCL_DMA_CH_88_ISR);
    #endif
    #ifdef MCL_DMA_CH_89_ISR_USED
    ISR(MCL_DMA_CH_89_ISR);
    #endif
    #ifdef MCL_DMA_CH_90_ISR_USED
    ISR(MCL_DMA_CH_90_ISR);
    #endif
    #ifdef MCL_DMA_CH_91_ISR_USED
    ISR(MCL_DMA_CH_91_ISR);
    #endif
    #ifdef MCL_DMA_CH_92_ISR_USED
    ISR(MCL_DMA_CH_92_ISR);
    #endif
    #ifdef MCL_DMA_CH_93_ISR_USED
    ISR(MCL_DMA_CH_93_ISR);
    #endif
    #ifdef MCL_DMA_CH_94_ISR_USED
    ISR(MCL_DMA_CH_94_ISR);
    #endif
    #ifdef MCL_DMA_CH_95_ISR_USED
    ISR(MCL_DMA_CH_95_ISR);
    #endif
    
#if (MCL_DMAV2_COMPLETION_GROUP_ISR == STD_OFF)

    #ifdef MCL_DMA_CH_96_ISR_USED
    ISR(MCL_DMA_CH_96_ISR);
    #endif
    #ifdef MCL_DMA_CH_97_ISR_USED
    ISR(MCL_DMA_CH_97_ISR);
    #endif
    #ifdef MCL_DMA_CH_98_ISR_USED
    ISR(MCL_DMA_CH_98_ISR);
    #endif
    #ifdef MCL_DMA_CH_99_ISR_USED
    ISR(MCL_DMA_CH_99_ISR);
    #endif
    #ifdef MCL_DMA_CH_100_ISR_USED
    ISR(MCL_DMA_CH_100_ISR);
    #endif
    #ifdef MCL_DMA_CH_101_ISR_USED
    ISR(MCL_DMA_CH_101_ISR);
    #endif
    #ifdef MCL_DMA_CH_102_ISR_USED
    ISR(MCL_DMA_CH_102_ISR);
    #endif
    #ifdef MCL_DMA_CH_103_ISR_USED
    ISR(MCL_DMA_CH_103_ISR);
    #endif
    #ifdef MCL_DMA_CH_104_ISR_USED
    ISR(MCL_DMA_CH_104_ISR);
    #endif
    #ifdef MCL_DMA_CH_105_ISR_USED
    ISR(MCL_DMA_CH_105_ISR);
    #endif
    #ifdef MCL_DMA_CH_106_ISR_USED
    ISR(MCL_DMA_CH_106_ISR);
    #endif
    #ifdef MCL_DMA_CH_107_ISR_USED
    ISR(MCL_DMA_CH_107_ISR);
    #endif
    #ifdef MCL_DMA_CH_108_ISR_USED
    ISR(MCL_DMA_CH_108_ISR);
    #endif
    #ifdef MCL_DMA_CH_109_ISR_USED
    ISR(MCL_DMA_CH_109_ISR);
    #endif
    #ifdef MCL_DMA_CH_110_ISR_USED
    ISR(MCL_DMA_CH_110_ISR);
    #endif
    #ifdef MCL_DMA_CH_111_ISR_USED
    ISR(MCL_DMA_CH_111_ISR);
    #endif
    #ifdef MCL_DMA_CH_112_ISR_USED
    ISR(MCL_DMA_CH_112_ISR);
    #endif
    #ifdef MCL_DMA_CH_113_ISR_USED
    ISR(MCL_DMA_CH_113_ISR);
    #endif
    #ifdef MCL_DMA_CH_114_ISR_USED
    ISR(MCL_DMA_CH_114_ISR);
    #endif
    #ifdef MCL_DMA_CH_115_ISR_USED
    ISR(MCL_DMA_CH_115_ISR);
    #endif
    #ifdef MCL_DMA_CH_116_ISR_USED
    ISR(MCL_DMA_CH_116_ISR);
    #endif
    #ifdef MCL_DMA_CH_117_ISR_USED
    ISR(MCL_DMA_CH_117_ISR);
    #endif
    #ifdef MCL_DMA_CH_118_ISR_USED
    ISR(MCL_DMA_CH_118_ISR);
    #endif
    #ifdef MCL_DMA_CH_119_ISR_USED
    ISR(MCL_DMA_CH_119_ISR);
    #endif
    #ifdef MCL_DMA_CH_120_ISR_USED
    ISR(MCL_DMA_CH_120_ISR);
    #endif
    #ifdef MCL_DMA_CH_121_ISR_USED
    ISR(MCL_DMA_CH_121_ISR);
    #endif
    #ifdef MCL_DMA_CH_122_ISR_USED
    ISR(MCL_DMA_CH_122_ISR);
    #endif
    #ifdef MCL_DMA_CH_123_ISR_USED
    ISR(MCL_DMA_CH_123_ISR);
    #endif
    #ifdef MCL_DMA_CH_124_ISR_USED
    ISR(MCL_DMA_CH_124_ISR);
    #endif
    #ifdef MCL_DMA_CH_125_ISR_USED
    ISR(MCL_DMA_CH_125_ISR);
    #endif
    #ifdef MCL_DMA_CH_126_ISR_USED
    ISR(MCL_DMA_CH_126_ISR);
    #endif
    #ifdef MCL_DMA_CH_127_ISR_USED
    ISR(MCL_DMA_CH_127_ISR);
    #endif
#else
    #if (defined MCL_DMA_CH_96_ISR_USED) || (defined MCL_DMA_CH_97_ISR_USED) || (defined MCL_DMA_CH_98_ISR_USED) || (defined MCL_DMA_CH_99_ISR_USED) || \
        (defined MCL_DMA_CH_100_ISR_USED) || (defined MCL_DMA_CH_101_ISR_USED) || (defined MCL_DMA_CH_102_ISR_USED) || (defined MCL_DMA_CH_103_ISR_USED)
        ISR(MCL_DMA_CH_96_103_ISR);
    #endif
    #if (defined MCL_DMA_CH_104_ISR_USED) || (defined MCL_DMA_CH_105_ISR_USED) || (defined MCL_DMA_CH_106_ISR_USED) || (defined MCL_DMA_CH_107_ISR_USED) || \
        (defined MCL_DMA_CH_108_ISR_USED) || (defined MCL_DMA_CH_109_ISR_USED) || (defined MCL_DMA_CH_110_ISR_USED) || (defined MCL_DMA_CH_111_ISR_USED)
        ISR(MCL_DMA_CH_104_111_ISR);
    #endif
    #if (defined MCL_DMA_CH_112_ISR_USED) || (defined MCL_DMA_CH_113_ISR_USED) || (defined MCL_DMA_CH_114_ISR_USED) || (defined MCL_DMA_CH_115_ISR_USED) || \
        (defined MCL_DMA_CH_116_ISR_USED) || (defined MCL_DMA_CH_117_ISR_USED) || (defined MCL_DMA_CH_118_ISR_USED) || (defined MCL_DMA_CH_119_ISR_USED)
        ISR(MCL_DMA_CH_112_119_ISR);
    #endif
    #if (defined MCL_DMA_CH_120_ISR_USED) || (defined MCL_DMA_CH_121_ISR_USED) || (defined MCL_DMA_CH_122_ISR_USED) || (defined MCL_DMA_CH_123_ISR_USED) || \
        (defined MCL_DMA_CH_124_ISR_USED) || (defined MCL_DMA_CH_125_ISR_USED) || (defined MCL_DMA_CH_126_ISR_USED) || (defined MCL_DMA_CH_127_ISR_USED)
        ISR(MCL_DMA_CH_120_127_ISR);
    #endif
#endif
#endif
#endif

#if (MCL_DMA_COMBINED_ERROR_ISR  == STD_OFF)
    #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
    ISR(MCL_DMA0_ERROR_ISR);
    ISR(MCL_DMA1_ERROR_ISR);
    ISR(MCL_DMA2_ERROR_ISR);
    #endif
#endif

#if (MCL_DMA_COMBINED_ERROR_ISR  == STD_ON)
    #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
    ISR(MCL_DMA_ERROR_ISR);
    #endif
#endif
/*==================================================================================================
*                                       LOCAL FUNCTIONS
==================================================================================================*/

/*==================================================================================================
*                                       GLOBAL FUNCTIONS
==================================================================================================*/
#define MCL_START_SEC_CODE
/* @violates @ref Mcl_DMA_Irq_c_REF_2 MISRA 2012 Required 4.10*/
/* @violates @ref Mcl_DMA_Irq_c_REF_4 MISRA 2012 Advisory 20.1*/
#include "Mcl_MemMap.h"

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
#if (MCL_DMA_COMBINED_TR_COMPLETION_ISR == STD_ON) || (MCL_DMA_TR_COMPLETION_MIXED_ISR == STD_ON) || (MCL_DMA_COMBINED_GROUP_COMPLETION_ISR == STD_ON) || (MCL_DMAV2_COMPLETION_GROUP_ISR == STD_ON)
    /**
    * @brief          Interrupt service routine to process the Dma interrupt
    * @details        This function:
    *                 - clears the unified channel interrupt flag bit in Control register
    *                 - calls the LLD layer handler
    *
    * @param[in]      DmaHwInstance      Dma Hardware Instance
    * @return void
    *
    * @api
    * @implements  Mcl_DmaProcessInterrupt_Activity
    */
    LOCAL_INLINE FUNC (void, MCL_CODE) Mcl_DmaProcessCombinedInterrupt
    (
        VAR(Mcl_DmaInstanceType, AUTOMATIC) DmaHwInstance
    )
    {
        /* @brief Variable storing the relative channel number */
        VAR(Mcl_DmaChannelType, AUTOMATIC) RelChannel = (uint8)0;
        /* @brief Variable storing content of Status register */
        VAR(uint32, AUTOMATIC) u32InerruptReqValue = (uint32)0;
        /* @brief Variable check the interrupt request already exist or not */
        VAR(boolean, AUTOMATIC) bIsrStatus = (boolean)FALSE;
        #ifdef MCAL_CACHE_RUNTIME_MNGMNT
        #if (STD_ON == MCAL_CACHE_RUNTIME_MNGMNT)
        #if (STD_ON == MCL_SYNCRONIZE_CACHE)
        /* @brief Return value of the cache operation*/
        VAR(Std_ReturnType, AUTOMATIC) retValCacheOperation = (Std_ReturnType)E_NOT_OK;

        /* invalidate DCACHE to synchronize data */
        retValCacheOperation = Mcl_IPW_CacheClear(MCL_LMEM_CACHE_ALL);
        if ((Std_ReturnType)E_NOT_OK == retValCacheOperation)
        {
            /* memory synchronization failed, notify user */
            #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
            Mcl_IPW_ErrorNotification(0xFFU, MCL_DMA_MEM_SYNC_ERROR);
            RelChannel = 0;
            #endif
        }
        else
        {
            /* cache memory sync successful */
        }
        #endif
        #endif
        #endif
        /*Check interrupt DMA v3*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_7 MISRA 2012 Required 2.1*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_8 MISRA 2012 Required 14.3*/
        if ((DMAV3_INSTANCES_NUMBER_U32 != 0U) && (DMAV3_INSTANCES_NUMBER_U32 > DmaHwInstance))
        {
            /* @violates @ref Mcl_DMA_Irq_c_REF_7 MISRA 2012 Required 2.1*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_8 MISRA 2012 Required 14.3*/
            while((MCL_EDMAV3_CHANNELS_NO != 0U) && (RelChannel < MCL_EDMAV3_CHANNELS_NO) && ((boolean)FALSE == bIsrStatus))
            {
                /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
                /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
                /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
                u32InerruptReqValue = (uint32)REG_READ32(DMAV3_CH_INT_ADDR((uint32)RelChannel));
                if((uint32)0 != (u32InerruptReqValue & DMAV3_CH_INT_U32))
                {
                    bIsrStatus = (boolean)TRUE;
                }
                else
                {
                    RelChannel = RelChannel + (uint8)1;
                }
            }
        }
        else
        {
            /* get the interrupt requests for low channels*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
            u32InerruptReqValue = (uint32)REG_READ32(DMAV2_INTL_ADDR32(DmaHwInstance));
            /* get the channel for which the ISR was requested*/
            while((RelChannel < 32U) && ((boolean)FALSE == bIsrStatus))
            {
                if(((uint32)0 != (u32InerruptReqValue & (uint32)(((uint32)1u << (uint32)RelChannel)))))
                {
                    bIsrStatus = (boolean)TRUE;
                }
                else
                {
                    RelChannel = RelChannel + (uint8)1;
                }
            }
#if (MCL_DMA_INSTANCE_CHANNELS_NO == 0x40U)
            /* get the interrupt requests for high channels*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
            u32InerruptReqValue = (uint32)REG_READ32(DMAV2_INTH_ADDR32(DmaHwInstance));
            /* get the channel for which the ISR was requested*/
            while((RelChannel < (uint8)DMA_CHANNELS_PER_MODULE_U8) && ((boolean)FALSE == bIsrStatus))
            {
                if(((uint32)0 != (u32InerruptReqValue & (uint32)(((uint32)1u << (uint32)((uint32)RelChannel - (uint32)32U))))))
                {
                    bIsrStatus = (boolean)TRUE;
                }
                else
                {
                    RelChannel = RelChannel + (uint8)1;
                }
            }
            /* @violates @ref Mcl_DMA_Irq_c_REF_7 MISRA 2012 Required 2.1*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_8 MISRA 2012 Required 14.3*/
            if ((DmaHwInstance == DMA_INSTANCE1) && (DMA_CHANNELS_PER_MODULE_U8 ==64U))
            {
                RelChannel = RelChannel + DMA_CHANNELS_PER_MODULE_U8;
            }
#endif
            RelChannel = RelChannel + MCL_EDMAV3_CHANNELS_NO;
        }
        /* check if any ISR request is set*/
        if((boolean)TRUE == bIsrStatus)
        {
            /* reset DMA channel interrupt flag (IRQ ACK) */
            /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_5 MISRA 2012 Advisory 13.4*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
            DMA_CLEAR_INT_REQ((uint32)RelChannel);
            /* Check that the interrupt was enabled for the corresponding DMA channel */
            /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
            if (((boolean)TRUE == DMA_TCD_GET_INT_MAJ((uint32)RelChannel)) || ((boolean)TRUE == DMA_TCD_GET_INT_HALF((uint32)RelChannel)))
            {
                /* Call Dma channel notification */
                Mcl_IPW_DmaChannelNotification(RelChannel);
            }
            else
            {
              /*Empty else to fix misra*/
            }
         }
         else
         {
            /*Empty else to fix misra*/
         }
    }
#endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
#if (MCL_DMA_TR_SEPARATED_ISR == STD_ON)
    /**
    * @brief          Interrupt service routine to process the Dma interrupt
    * @details        This function:
    *                 - clears the unified channel interrupt flag bit in Control register
    *                 - calls the LLD layer handler
    *
    * @param[in]      HwChannel      Dma channel ID that triggered the interrupt
    *
    * @return void
    *
    * @api
    * @implements  Mcl_DmaProcessInterrupt_Activity
    */
    LOCAL_INLINE FUNC (void, MCL_CODE) Mcl_DmaProcessInterrupt
    (
        VAR(Mcl_DmaChannelType, AUTOMATIC) HwChannel
    )
    {
        /* @brief Variable storing content of Status register */
        VAR(boolean, AUTOMATIC) bIsrStatus = (boolean)FALSE;

        /* Check that the interrupt was enabled for the corresponding DMA channel */
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
        if (((boolean)TRUE==DMA_TCD_GET_INT_MAJ((uint32)HwChannel)) || ((boolean)TRUE==DMA_TCD_GET_INT_HALF((uint32)HwChannel)))
        {
            /* Get the interrupt request for the corresponding DMA channel */
            bIsrStatus = Mcl_Dma_GetMultiRegChInfo(HwChannel, MCL_DMA_GET_INT);
        }
        else
        {
          /*Empty else to fix misra*/
        }
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_5 MISRA 2012 Advisory 13.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
        DMA_CLEAR_INT_REQ(HwChannel);

        /* Check if isr was enabled on the corresponding channel and interrupt request was set */
        if ((boolean)TRUE == bIsrStatus)
        {
            /* Call Dma channel notification */
            Mcl_IPW_DmaChannelNotification(HwChannel);
        }
        else
        {
          /*Empty else to fix misra*/
        }
#if (MCL_DMA_COMBINED_ERROR_COMPLETION_PER_CHANNEL_ISR == STD_ON)

#if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
        bIsrStatus = Mcl_Dma_GetMultiRegChInfo(HwChannel, MCL_DMA_GET_ERR);

        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_5 MISRA 2012 Advisory 13.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
        DMA_CLEAR_INT_ERR_REQ(HwChannel);

        /* Check if flag error interrupt request was set */
        if ((boolean)TRUE == bIsrStatus)
        {
            /* Call Dma channel error notification */
            /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
            Mcl_DmaProcessErrorInterrupt((uint8)DMA_MOD_IDX_U32(HwChannel));
        }
        else
        {
          /*Empty else to fix misra*/
        }
#else
    /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_Irq_c_REF_5 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
    DMA_CLEAR_INT_ERR_REQ(HwChannel);
#endif
#endif
    }
#endif
#endif

#if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
/**
* @brief          Interrupt service routine to process the Dma error interrupt
* @details        This function:
*                 - checks the error type
*                 - calls higher level function to report error
*
* @param[in]
*
* @return void
*
* @api
* @implements  Mcl_DmaProcessErrorInterrupt_Activity
*/
LOCAL_INLINE FUNC(void, MCL_CODE) Mcl_DmaProcessErrorInterrupt
(
    VAR(Mcl_DmaInstanceType, AUTOMATIC) DmaHwInstance
)
{

    VAR(uint32,AUTOMATIC) u32ErrorStatus;
    VAR(uint8,AUTOMATIC) u8ErrChannel;
    u8ErrChannel = Mcl_Dma_GetNumChannelError(DmaHwInstance);
    /* @violates @ref Mcl_DMA_Irq_c_REF_7 MISRA 2012 Required 2.1*/
    /* @violates @ref Mcl_DMA_Irq_c_REF_8 MISRA 2012 Required 14.3*/
    if ((DMAV3_INSTANCES_NUMBER_U32 != 0U) && (DMAV3_INSTANCES_NUMBER_U32 > DmaHwInstance))
    {
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
        u32ErrorStatus = REG_READ32(DMAV3_ES_ADDR32((uint32)(DmaHwInstance)));
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_5 MISRA 2012 Advisory 13.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/         
        DMA_CLEAR_INT_ERR_REQ(u8ErrChannel);
    }
    else
    {
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
        u32ErrorStatus = REG_READ32(DMAV2_ES_ADDR32((uint32)(DmaHwInstance)));
        /* Clear all error indicators */
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_6 MISRA 2012 Required 10.8*/
        REG_WRITE8(DMAV2_CERR_ADDR32((uint32)(DmaHwInstance)), DMAV2_CERR_CAEI_U8);
    }

    if ((uint32)0U != u32ErrorStatus )
    {
        #if (MCL_DMA_ECC_REPORTING_ENABLED == STD_ON)
        if(0U != (u32ErrorStatus & DMA_ES_UCE_U32))
        {
            /* Uncorrectable  ECC error detected */
            Mcl_IPW_ErrorNotification(u8ErrChannel,MCL_DMA_ECC_ERROR);
        }
        else
        #endif
        if((uint32)0U != (u32ErrorStatus & DMA_ES_BUS_U32))
        {
            /* Source or destination bus error detected */
            Mcl_IPW_ErrorNotification(u8ErrChannel,MCL_DMA_BUS_ERROR);
        }
        else if((uint32)0U != (u32ErrorStatus & DMA_ES_DESCRIPTOR_U32))
        {
            /* Descriptor error detected */
            Mcl_IPW_ErrorNotification(u8ErrChannel,MCL_DMA_DESCRIPTOR_ERROR);
        }
        else if((uint32)0U != (u32ErrorStatus & (DMAV2_ES_GPE_U32 | DMAV2_ES_CPE_U32)))
        {
            /* Priority error detected */
                Mcl_IPW_ErrorNotification(u8ErrChannel,MCL_DMA_PRIORITY_ERROR);
        }
        else
        {
            /* Unrecognized error detected */
            Mcl_IPW_ErrorNotification(u8ErrChannel,MCL_DMA_UNRECOGNIZED_ERROR);

            /* Comment added to workaround MISRA tool check bug, which failed to detect a final 'else'
               block if that block ended with a preprocessing directive.*/
        }
    }
    else
    {
        /* No errors present */
    }
}
#endif /* ( MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON) */

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
#if (MCL_DMA_COMBINED_TR_COMPLETION_ISR == STD_ON)
    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA module: 0  channel: 0
    *
    * @isr
    */
    ISR(MCL_DMA0_CH_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE0);
        EXIT_INTERRUPT();
    }

    #if (MCL_DMA_NB_CONTROLLERS == 0x02U)
    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA module: 0  channel: 0
    *
    * @isr
    */
    ISR(MCL_DMA1_CH_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);
        EXIT_INTERRUPT();
    }
    #endif
#endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
    #if (MCL_DMA_COMBINED_GROUP_COMPLETION_ISR == STD_ON)
    #ifdef MCL_DMA_GROUP0_ISR_USED
    ISR(MCL_DMA_GROUP0_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE0);
        EXIT_INTERRUPT();
    }
    #endif
    #ifdef MCL_DMA_GROUP1_ISR_USED
    ISR(MCL_DMA_GROUP1_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE0);
        EXIT_INTERRUPT();
    }
    #endif
    #ifdef MCL_DMA_GROUP2_ISR_USED
    ISR(MCL_DMA_GROUP2_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);
        EXIT_INTERRUPT();
    }
    #endif
    #ifdef MCL_DMA_GROUP3_ISR_USED
    ISR(MCL_DMA_GROUP3_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);
        EXIT_INTERRUPT();
    }
    #endif
    #endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
#if (MCL_DMA_TR_COMPLETION_MIXED_ISR == STD_ON)
    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channels eDMA_96 to eDMA_127
    *
    * @isr
    */
    ISR(MCL_DMA_CH_MIXED_96_127_COMPLETE_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);
        EXIT_INTERRUPT();
    }
#endif
#endif

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
#if (MCL_DMA_TR_SEPARATED_ISR == STD_ON)

    #ifdef MCL_DMA_CH_0_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 0
    *
    * @isr
    */
    ISR(MCL_DMA_CH_0_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_0);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_0_ISR_USED */

    #ifdef MCL_DMA_CH_1_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 1
    *
    * @isr
    */
    ISR(MCL_DMA_CH_1_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_1);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_1_ISR_USED */
    #ifdef MCL_DMA_CH_2_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 2
    *
    * @isr
    */
    ISR(MCL_DMA_CH_2_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_2);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_2_ISR_USED */
    #ifdef MCL_DMA_CH_3_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 3
    *
    * @isr
    */
    ISR(MCL_DMA_CH_3_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_3);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_3_ISR_USED */
    #ifdef MCL_DMA_CH_4_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 4
    *
    * @isr
    */
    ISR(MCL_DMA_CH_4_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_4);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_4_ISR_USED */
    #ifdef MCL_DMA_CH_5_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 5
    *
    * @isr
    */
    ISR(MCL_DMA_CH_5_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_5);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_5_ISR_USED */
    #ifdef MCL_DMA_CH_6_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 6
    *
    * @isr
    */
    ISR(MCL_DMA_CH_6_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_6);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_6_ISR_USED */
    #ifdef MCL_DMA_CH_7_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 7
    *
    * @isr
    */
    ISR(MCL_DMA_CH_7_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_7);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_7_ISR_USED */
    #ifdef MCL_DMA_CH_8_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 8
    *
    * @isr
    */
    ISR(MCL_DMA_CH_8_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_8);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_8_ISR_USED */
    #ifdef MCL_DMA_CH_9_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 9
    *
    * @isr
    */
    ISR(MCL_DMA_CH_9_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_9);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_9_ISR_USED */
    #ifdef MCL_DMA_CH_10_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 10
    *
    * @isr
    */
    ISR(MCL_DMA_CH_10_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_10);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_10_ISR_USED */
    #ifdef MCL_DMA_CH_11_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 11
    *
    * @isr
    */
    ISR(MCL_DMA_CH_11_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_11);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_11_ISR_USED */
    #ifdef MCL_DMA_CH_12_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 12
    *
    * @isr
    */
    ISR(MCL_DMA_CH_12_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_12);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_12_ISR_USED */
    #ifdef MCL_DMA_CH_13_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 13
    *
    * @isr
    */
    ISR(MCL_DMA_CH_13_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_13);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_13_ISR_USED */
    #ifdef MCL_DMA_CH_14_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 14
    *
    * @isr
    */
    ISR(MCL_DMA_CH_14_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_14);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_14_ISR_USED */
    #ifdef MCL_DMA_CH_15_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 15
    *
    * @isr
    */
    ISR(MCL_DMA_CH_15_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_15);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_15_ISR_USED */
    #ifdef MCL_DMA_CH_16_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 16
    *
    * @isr
    */
    ISR(MCL_DMA_CH_16_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_16);
        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_16_ISR_USED */
    #ifdef MCL_DMA_CH_17_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 17
    *
    * @isr
    */

    ISR(MCL_DMA_CH_17_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_17);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_17_ISR_USED */
    #ifdef MCL_DMA_CH_18_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 18
    *
    * @isr
    */

    ISR(MCL_DMA_CH_18_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_18);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_18_ISR_USED */
    #ifdef MCL_DMA_CH_19_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 19
    *
    * @isr
    */

    ISR(MCL_DMA_CH_19_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_19);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_19_ISR_USED */
    #ifdef MCL_DMA_CH_20_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 20
    *
    * @isr
    */

    ISR(MCL_DMA_CH_20_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_20);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_20_ISR_USED */
    #ifdef MCL_DMA_CH_21_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 21
    *
    * @isr
    */

    ISR(MCL_DMA_CH_21_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_21);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_21_ISR_USED */
    #ifdef MCL_DMA_CH_22_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 22
    *
    * @isr
    */

    ISR(MCL_DMA_CH_22_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_22);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_22_ISR_USED */
    #ifdef MCL_DMA_CH_23_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 23
    *
    * @isr
    */

    ISR(MCL_DMA_CH_23_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_23);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_23_ISR_USED */
    #ifdef MCL_DMA_CH_24_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 24
    *
    * @isr
    */

    ISR(MCL_DMA_CH_24_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_24);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_24_ISR_USED */
    #ifdef MCL_DMA_CH_25_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 25
    *
    * @isr
    */

    ISR(MCL_DMA_CH_25_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_25);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_25_ISR_USED */
    #ifdef MCL_DMA_CH_26_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 26
    *
    * @isr
    */

    ISR(MCL_DMA_CH_26_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_26);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_26_ISR_USED */
    #ifdef MCL_DMA_CH_27_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 27
    *
    * @isr
    */

    ISR(MCL_DMA_CH_27_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_27);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_27_ISR_USED */
    #ifdef MCL_DMA_CH_28_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 28
    *
    * @isr
    */

    ISR(MCL_DMA_CH_28_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_28);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_28_ISR_USED */
    #ifdef MCL_DMA_CH_29_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 29
    *
    * @isr
    */

    ISR(MCL_DMA_CH_29_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_29);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_29_ISR_USED */
    #ifdef MCL_DMA_CH_30_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 30
    *
    * @isr
    */

    ISR(MCL_DMA_CH_30_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_30);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_30_ISR_USED */
    #ifdef MCL_DMA_CH_31_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 31
    *
    * @isr
    */

    ISR(MCL_DMA_CH_31_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_31);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_31_ISR_USED */
    #ifdef MCL_DMA_CH_32_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 32
    *
    * @isr
    */

    ISR(MCL_DMA_CH_32_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_32);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_32_ISR_USED */
    #ifdef MCL_DMA_CH_33_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 33
    *
    * @isr
    */

    ISR(MCL_DMA_CH_33_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_33);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_33_ISR_USED */
    #ifdef MCL_DMA_CH_34_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 34
    *
    * @isr
    */

    ISR(MCL_DMA_CH_34_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_34);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_34_ISR_USED */
    #ifdef MCL_DMA_CH_35_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 35
    *
    * @isr
    */

    ISR(MCL_DMA_CH_35_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_35);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_35_ISR_USED */
    #ifdef MCL_DMA_CH_36_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 36
    *
    * @isr
    */

    ISR(MCL_DMA_CH_36_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_36);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_36_ISR_USED */
    #ifdef MCL_DMA_CH_37_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 37
    *
    * @isr
    */

    ISR(MCL_DMA_CH_37_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_37);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_37_ISR_USED */
    #ifdef MCL_DMA_CH_38_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 38
    *
    * @isr
    */

    ISR(MCL_DMA_CH_38_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_38);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_38_ISR_USED */
    #ifdef MCL_DMA_CH_39_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 39
    *
    * @isr
    */

    ISR(MCL_DMA_CH_39_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_39);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_39_ISR_USED */
    #ifdef MCL_DMA_CH_40_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 40
    *
    * @isr
    */

    ISR(MCL_DMA_CH_40_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_40);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_40_ISR_USED */
    #ifdef MCL_DMA_CH_41_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 41
    *
    * @isr
    */

    ISR(MCL_DMA_CH_41_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_41);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_41_ISR_USED */
    #ifdef MCL_DMA_CH_42_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 42
    *
    * @isr
    */

    ISR(MCL_DMA_CH_42_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_42);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_42_ISR_USED */
    #ifdef MCL_DMA_CH_43_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 43
    *
    * @isr
    */

    ISR(MCL_DMA_CH_43_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_43);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_43_ISR_USED */
    #ifdef MCL_DMA_CH_44_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 44
    *
    * @isr
    */

    ISR(MCL_DMA_CH_44_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_44);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_44_ISR_USED */
    #ifdef MCL_DMA_CH_45_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 45
    *
    * @isr
    */

    ISR(MCL_DMA_CH_45_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_45);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_45_ISR_USED */
    #ifdef MCL_DMA_CH_46_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 46
    *
    * @isr
    */

    ISR(MCL_DMA_CH_46_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_46);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_46_ISR_USED */
    #ifdef MCL_DMA_CH_47_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 47
    *
    * @isr
    */

    ISR(MCL_DMA_CH_47_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_47);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_47_ISR_USED */
    #ifdef MCL_DMA_CH_48_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 48
    *
    * @isr
    */

    ISR(MCL_DMA_CH_48_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_48);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_48_ISR_USED */
    #ifdef MCL_DMA_CH_49_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 49
    *
    * @isr
    */

    ISR(MCL_DMA_CH_49_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_49);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_49_ISR_USED */
    #ifdef MCL_DMA_CH_50_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 50
    *
    * @isr
    */

    ISR(MCL_DMA_CH_50_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_50);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_50_ISR_USED */
    #ifdef MCL_DMA_CH_51_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 51
    *
    * @isr
    */

    ISR(MCL_DMA_CH_51_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_51);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_51_ISR_USED */
    #ifdef MCL_DMA_CH_52_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 52
    *
    * @isr
    */

    ISR(MCL_DMA_CH_52_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_52);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_52_ISR_USED */
    #ifdef MCL_DMA_CH_53_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 53
    *
    * @isr
    */

    ISR(MCL_DMA_CH_53_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_53);

        EXIT_INTERRUPT();
    }

    #endif /* MCL_DMA_CH_53_ISR_USED */
    #ifdef MCL_DMA_CH_54_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 54
    *
    * @isr
    */

    ISR(MCL_DMA_CH_54_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_54);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_54_ISR_USED */
    #ifdef MCL_DMA_CH_55_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 55
    *
    * @isr
    */

    ISR(MCL_DMA_CH_55_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_55);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_55_ISR_USED */
    #ifdef MCL_DMA_CH_56_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 56
    *
    * @isr
    */

    ISR(MCL_DMA_CH_56_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_56);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_56_ISR_USED */
    #ifdef MCL_DMA_CH_57_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 57
    *
    * @isr
    */

    ISR(MCL_DMA_CH_57_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_57);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_57_ISR_USED */
    #ifdef MCL_DMA_CH_58_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 58
    *
    * @isr
    */

    ISR(MCL_DMA_CH_58_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_58);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_58_ISR_USED */
    #ifdef MCL_DMA_CH_59_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 59
    *
    * @isr
    */

    ISR(MCL_DMA_CH_59_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_59);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_59_ISR_USED */
    #ifdef MCL_DMA_CH_60_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 60
    *
    * @isr
    */

    ISR(MCL_DMA_CH_60_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_60);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_60_ISR_USED */
    #ifdef MCL_DMA_CH_61_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 61
    *
    * @isr
    */

    ISR(MCL_DMA_CH_61_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_61);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_61_ISR_USED */
    #ifdef MCL_DMA_CH_62_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 62
    *
    * @isr
    */

    ISR(MCL_DMA_CH_62_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_62);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_62_ISR_USED */
    #ifdef MCL_DMA_CH_63_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 63
    *
    * @isr
    */

    ISR(MCL_DMA_CH_63_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_63);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_63_ISR_USED */
    #ifdef MCL_DMA_CH_64_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 64
    *
    * @isr
    */

    ISR(MCL_DMA_CH_64_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_64);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_64_ISR_USED */
    #ifdef MCL_DMA_CH_65_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 65
    *
    * @isr
    */

    ISR(MCL_DMA_CH_65_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_65);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_65_ISR_USED */
    #ifdef MCL_DMA_CH_66_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 66
    *
    * @isr
    */

    ISR(MCL_DMA_CH_66_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_66);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_66_ISR_USED */
    #ifdef MCL_DMA_CH_67_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 67
    *
    * @isr
    */

    ISR(MCL_DMA_CH_67_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_67);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_67_ISR_USED */
    #ifdef MCL_DMA_CH_68_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 68
    *
    * @isr
    */

    ISR(MCL_DMA_CH_68_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_68);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_68_ISR_USED */
    #ifdef MCL_DMA_CH_69_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 69
    *
    * @isr
    */

    ISR(MCL_DMA_CH_69_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_69);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_69_ISR_USED */
    #ifdef MCL_DMA_CH_70_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 70
    *
    * @isr
    */

    ISR(MCL_DMA_CH_70_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_70);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_70_ISR_USED */
    #ifdef MCL_DMA_CH_71_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 71
    *
    * @isr
    */

    ISR(MCL_DMA_CH_71_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_71);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_71_ISR_USED */
    #ifdef MCL_DMA_CH_72_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 72
    *
    * @isr
    */

    ISR(MCL_DMA_CH_72_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_72);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_72_ISR_USED */
    #ifdef MCL_DMA_CH_73_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 73
    *
    * @isr
    */

    ISR(MCL_DMA_CH_73_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_73);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_73_ISR_USED */
    #ifdef MCL_DMA_CH_74_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 74
    *
    * @isr
    */

    ISR(MCL_DMA_CH_74_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_74);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_74_ISR_USED */
    #ifdef MCL_DMA_CH_75_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 75
    *
    * @isr
    */

    ISR(MCL_DMA_CH_75_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_75);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_75_ISR_USED */
    #ifdef MCL_DMA_CH_76_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 76
    *
    * @isr
    */

    ISR(MCL_DMA_CH_76_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_76);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_76_ISR_USED */
    #ifdef MCL_DMA_CH_77_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 77
    *
    * @isr
    */

    ISR(MCL_DMA_CH_77_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_77);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_77_ISR_USED */
    #ifdef MCL_DMA_CH_78_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 78
    *
    * @isr
    */

    ISR(MCL_DMA_CH_78_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_78);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_78_ISR_USED */
    #ifdef MCL_DMA_CH_79_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 79
    *
    * @isr
    */

    ISR(MCL_DMA_CH_79_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_79);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_79_ISR_USED */
    #ifdef MCL_DMA_CH_80_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 80
    *
    * @isr
    */

    ISR(MCL_DMA_CH_80_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_80);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_80_ISR_USED */
    #ifdef MCL_DMA_CH_81_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 81
    *
    * @isr
    */

    ISR(MCL_DMA_CH_81_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_81);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_81_ISR_USED */
    #ifdef MCL_DMA_CH_82_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 82
    *
    * @isr
    */

    ISR(MCL_DMA_CH_82_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_82);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_82_ISR_USED */
    #ifdef MCL_DMA_CH_83_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 83
    *
    * @isr
    */

    ISR(MCL_DMA_CH_83_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_83);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_83_ISR_USED */
    #ifdef MCL_DMA_CH_84_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 84
    *
    * @isr
    */

    ISR(MCL_DMA_CH_84_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_84);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_84_ISR_USED */
    #ifdef MCL_DMA_CH_85_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 85
    *
    * @isr
    */

    ISR(MCL_DMA_CH_85_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_85);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_85_ISR_USED */
    #ifdef MCL_DMA_CH_86_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 86
    *
    * @isr
    */

    ISR(MCL_DMA_CH_86_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_86);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_86_ISR_USED */
    #ifdef MCL_DMA_CH_87_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 87
    *
    * @isr
    */

    ISR(MCL_DMA_CH_87_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_87);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_87_ISR_USED */
    #ifdef MCL_DMA_CH_88_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 88
    *
    * @isr
    */

    ISR(MCL_DMA_CH_88_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_88);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_88_ISR_USED */
    #ifdef MCL_DMA_CH_89_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 89
    *
    * @isr
    */

    ISR(MCL_DMA_CH_89_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_89);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_89_ISR_USED */
    #ifdef MCL_DMA_CH_90_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 90
    *
    * @isr
    */

    ISR(MCL_DMA_CH_90_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_90);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_90_ISR_USED */
    #ifdef MCL_DMA_CH_91_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 91
    *
    * @isr
    */

    ISR(MCL_DMA_CH_91_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_91);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_91_ISR_USED */
    #ifdef MCL_DMA_CH_92_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 92
    *
    * @isr
    */

    ISR(MCL_DMA_CH_92_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_92);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_92_ISR_USED */
    #ifdef MCL_DMA_CH_93_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 93
    *
    * @isr
    */

    ISR(MCL_DMA_CH_93_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_93);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_93_ISR_USED */
    #ifdef MCL_DMA_CH_94_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 94
    *
    * @isr
    */

    ISR(MCL_DMA_CH_94_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_94);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_94_ISR_USED */
    #ifdef MCL_DMA_CH_95_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 95
    *
    * @isr
    */

    ISR(MCL_DMA_CH_95_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_95);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_95_ISR_USED */
#if (MCL_DMAV2_COMPLETION_GROUP_ISR == STD_OFF)
    #ifdef MCL_DMA_CH_96_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 96
    *
    * @isr
    */

    ISR(MCL_DMA_CH_96_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_96);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_96_ISR_USED */
    #ifdef MCL_DMA_CH_97_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 97
    *
    * @isr
    */

    ISR(MCL_DMA_CH_97_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_97);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_97_ISR_USED */
    #ifdef MCL_DMA_CH_98_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 98
    *
    * @isr
    */

    ISR(MCL_DMA_CH_98_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_98);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_98_ISR_USED */
    #ifdef MCL_DMA_CH_99_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 99
    *
    * @isr
    */

    ISR(MCL_DMA_CH_99_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_99);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_99_ISR_USED */
    #ifdef MCL_DMA_CH_100_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 100
    *
    * @isr
    */

    ISR(MCL_DMA_CH_100_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_100);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_100_ISR_USED */
    #ifdef MCL_DMA_CH_101_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 101
    *
    * @isr
    */

    ISR(MCL_DMA_CH_101_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_101);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_101_ISR_USED */
    #ifdef MCL_DMA_CH_102_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 102
    *
    * @isr
    */

    ISR(MCL_DMA_CH_102_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_102);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_102_ISR_USED */
    #ifdef MCL_DMA_CH_103_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 103
    *
    * @isr
    */

    ISR(MCL_DMA_CH_103_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_103);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_103_ISR_USED */
    #ifdef MCL_DMA_CH_104_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 104
    *
    * @isr
    */

    ISR(MCL_DMA_CH_104_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_104);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_104_ISR_USED */
    #ifdef MCL_DMA_CH_105_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 105
    *
    * @isr
    */

    ISR(MCL_DMA_CH_105_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_105);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_105_ISR_USED */
    #ifdef MCL_DMA_CH_106_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 106
    *
    * @isr
    */

    ISR(MCL_DMA_CH_106_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_106);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_106_ISR_USED */
    #ifdef MCL_DMA_CH_107_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 107
    *
    * @isr
    */

    ISR(MCL_DMA_CH_107_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_107);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_107_ISR_USED */
    #ifdef MCL_DMA_CH_108_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 108
    *
    * @isr
    */

    ISR(MCL_DMA_CH_108_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_108);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_108_ISR_USED */
    #ifdef MCL_DMA_CH_109_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 109
    *
    * @isr
    */

    ISR(MCL_DMA_CH_109_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_109);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_109_ISR_USED */
    #ifdef MCL_DMA_CH_110_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 110
    *
    * @isr
    */

    ISR(MCL_DMA_CH_110_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_110);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_110_ISR_USED */
    #ifdef MCL_DMA_CH_111_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 111
    *
    * @isr
    */

    ISR(MCL_DMA_CH_111_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_111);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_111_ISR_USED */
    #ifdef MCL_DMA_CH_112_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 112
    *
    * @isr
    */

    ISR(MCL_DMA_CH_112_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_112);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_112_ISR_USED */
    #ifdef MCL_DMA_CH_113_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 113
    *
    * @isr
    */

    ISR(MCL_DMA_CH_113_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_113);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_113_ISR_USED */
    #ifdef MCL_DMA_CH_114_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 114
    *
    * @isr
    */

    ISR(MCL_DMA_CH_114_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_114);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_114_ISR_USED */
    #ifdef MCL_DMA_CH_115_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 115
    *
    * @isr
    */

    ISR(MCL_DMA_CH_115_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_115);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_115_ISR_USED */
    #ifdef MCL_DMA_CH_116_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 116
    *
    * @isr
    */

    ISR(MCL_DMA_CH_116_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_116);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_116_ISR_USED */
    #ifdef MCL_DMA_CH_117_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 117
    *
    * @isr
    */

    ISR(MCL_DMA_CH_117_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_117);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_117_ISR_USED */
    #ifdef MCL_DMA_CH_118_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 118
    *
    * @isr
    */

    ISR(MCL_DMA_CH_118_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_118);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_118_ISR_USED */
    #ifdef MCL_DMA_CH_119_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 119
    *
    * @isr
    */

    ISR(MCL_DMA_CH_119_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_119);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_119_ISR_USED */
    #ifdef MCL_DMA_CH_120_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 120
    *
    * @isr
    */

    ISR(MCL_DMA_CH_120_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_120);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_120_ISR_USED */
    #ifdef MCL_DMA_CH_121_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 121
    *
    * @isr
    */

    ISR(MCL_DMA_CH_121_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_121);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_121_ISR_USED */
    #ifdef MCL_DMA_CH_122_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 122
    *
    * @isr
    */

    ISR(MCL_DMA_CH_122_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_122);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_122_ISR_USED */
    #ifdef MCL_DMA_CH_123_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 123
    *
    * @isr
    */

    ISR(MCL_DMA_CH_123_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_123);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_123_ISR_USED */
    #ifdef MCL_DMA_CH_124_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 124
    *
    * @isr
    */

    ISR(MCL_DMA_CH_124_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_124);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_124_ISR_USED */
    #ifdef MCL_DMA_CH_125_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 125
    *
    * @isr
    */

    ISR(MCL_DMA_CH_125_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_125);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_125_ISR_USED */
    #ifdef MCL_DMA_CH_126_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 126
    *
    * @isr
    */

    ISR(MCL_DMA_CH_126_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_126);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_126_ISR_USED */
    #ifdef MCL_DMA_CH_127_ISR_USED

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA channel: 127
    *
    * @isr
    */

    ISR(MCL_DMA_CH_127_ISR)
    {
        Mcl_DmaProcessInterrupt(DMA_HW_CHANNEL_127);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_CH_127_ISR_USED */
#else
    #if (defined MCL_DMA_CH_96_ISR_USED) || (defined MCL_DMA_CH_97_ISR_USED) || (defined MCL_DMA_CH_98_ISR_USED) || (defined MCL_DMA_CH_99_ISR_USED) || \
        (defined MCL_DMA_CH_100_ISR_USED) || (defined MCL_DMA_CH_101_ISR_USED) || (defined MCL_DMA_CH_102_ISR_USED) || (defined MCL_DMA_CH_103_ISR_USED)
    ISR(MCL_DMA_CH_96_103_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);

        EXIT_INTERRUPT();
    }
    #endif
    #if (defined MCL_DMA_CH_104_ISR_USED) || (defined MCL_DMA_CH_105_ISR_USED) || (defined MCL_DMA_CH_106_ISR_USED) || (defined MCL_DMA_CH_107_ISR_USED) || \
        (defined MCL_DMA_CH_108_ISR_USED) || (defined MCL_DMA_CH_109_ISR_USED) || (defined MCL_DMA_CH_110_ISR_USED) || (defined MCL_DMA_CH_111_ISR_USED)
    ISR(MCL_DMA_CH_104_111_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);

        EXIT_INTERRUPT();
    }
    #endif
    #if (defined MCL_DMA_CH_112_ISR_USED) || (defined MCL_DMA_CH_113_ISR_USED) || (defined MCL_DMA_CH_114_ISR_USED) || (defined MCL_DMA_CH_115_ISR_USED) || \
        (defined MCL_DMA_CH_116_ISR_USED) || (defined MCL_DMA_CH_117_ISR_USED) || (defined MCL_DMA_CH_118_ISR_USED) || (defined MCL_DMA_CH_119_ISR_USED)
    ISR(MCL_DMA_CH_112_119_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);
        EXIT_INTERRUPT();
    }
    #endif
    #if (defined MCL_DMA_CH_120_ISR_USED) || (defined MCL_DMA_CH_121_ISR_USED) || (defined MCL_DMA_CH_122_ISR_USED) || (defined MCL_DMA_CH_123_ISR_USED) || \
        (defined MCL_DMA_CH_124_ISR_USED) || (defined MCL_DMA_CH_125_ISR_USED) || (defined MCL_DMA_CH_126_ISR_USED) || (defined MCL_DMA_CH_127_ISR_USED)
    ISR(MCL_DMA_CH_120_127_ISR)
    {
        Mcl_DmaProcessCombinedInterrupt(DMA_INSTANCE1);
        EXIT_INTERRUPT();
    }
    #endif    
#endif
#endif
#endif

#if (MCL_DMA_COMBINED_ERROR_ISR  == STD_OFF)
    #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA Combined Error
    *
    * @isr
    */

    ISR(MCL_DMA0_ERROR_ISR)
    {
        Mcl_DmaProcessErrorInterrupt(DMA_INSTANCE0);

        EXIT_INTERRUPT();
    }
    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA Combined Error
    *
    * @isr
    */

    ISR(MCL_DMA1_ERROR_ISR)
    {
        Mcl_DmaProcessErrorInterrupt(DMA_INSTANCE1);

        EXIT_INTERRUPT();
    }
        /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for DMA Combined Error
    *
    * @isr
    */

    ISR(MCL_DMA2_ERROR_ISR)
    {
        Mcl_DmaProcessErrorInterrupt(DMA_INSTANCE2);

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_ERROR_INTERRUPTS_USED */
#endif

#if (MCL_DMA_COMBINED_ERROR_ISR  == STD_ON)
    #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)

    /**
    * @brief          Independent interrupt handler.
    * @details        Interrupt handler for the case when one combined error ISR is availabl for more than 1 DMA controllers
    *
    * @isr
    */

    ISR(MCL_DMA_ERROR_ISR)
    {
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        VAR(uint32,AUTOMATIC) u32ErrorStatus0 = REG_READ32(DMAV2_ES_ADDR32((uint32)(DMA_INSTANCE0)));
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        VAR(uint32,AUTOMATIC) u32ErrorStatus1 = REG_READ32(DMAV2_ES_ADDR32((uint32)(DMA_INSTANCE1)));
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/        
        VAR(uint32,AUTOMATIC) u32ErrorStatusChannelInstance1H = REG_READ32(DMAV2_EERH_ADDR32((uint32)(DMA_INSTANCE1))) ;
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/        
        VAR(uint32,AUTOMATIC) u32ErrorStatusChannelInstance1L = REG_READ32(DMAV2_EERL_ADDR32((uint32)(DMA_INSTANCE1))) ;
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/       
        VAR(uint32,AUTOMATIC) u32ErrorStatusChannelInstance0H = REG_READ32(DMAV2_EERH_ADDR32((uint32)(DMA_INSTANCE0))) ;
        /* @violates @ref Mcl_DMA_Irq_c_REF_1 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_Irq_c_REF_3 MISRA 2012 Required 11.6*/
        VAR(uint32,AUTOMATIC) u32ErrorStatusChannelInstance0L = REG_READ32(DMAV2_EERL_ADDR32((uint32)(DMA_INSTANCE0))) ;
        

       if (((uint32)0U != u32ErrorStatus0)  && ((uint32)0U != (u32ErrorStatusChannelInstance0H | u32ErrorStatusChannelInstance0L)))
       {
            Mcl_DmaProcessErrorInterrupt(DMA_INSTANCE0);
       }
       else
       {
            /*Empty else to fix misra*/
       }

       if (((uint32)0U != u32ErrorStatus1) && ((uint32)0U != (u32ErrorStatusChannelInstance1H | u32ErrorStatusChannelInstance1L)))
       {
            Mcl_DmaProcessErrorInterrupt(DMA_INSTANCE1);
       }
       else
       {
         /*Empty else to fix misra*/
       }

        EXIT_INTERRUPT();
    }
    #endif /* MCL_DMA_ERROR_INTERRUPTS_USED */
#endif
#define MCL_STOP_SEC_CODE
/* @violates @ref Mcl_DMA_Irq_c_REF_2 MISRA 2012 Required 4.10*/
/* @violates @ref Mcl_DMA_Irq_c_REF_4 MISRA 2012 Advisory 20.1*/
#include "Mcl_MemMap.h"

#endif
#endif

#ifdef __cplusplus
}
#endif

/** @} */

