/**
*   @file    Can_Mcan.c
*   @implements MCan.c_Artifact
*   @version 1.0.0
*
*   @brief   AUTOSAR Can - IPW module implementation.
*   @details Low Level Driver implementation.
*
*   @addtogroup CAN_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : MCAN
*   Dependencies         : 
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/


#ifdef __cplusplus
extern "C"{
#endif

/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
*          The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space shall be distinct.
*          The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
*          The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
*          The used compilers use more than 31 chars for identifiers.
*
* @section Can_Mcan_c_REF_1
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Declaration is reserved for future feature.
*
* @section Can_Mcan_c_REF_2
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents
* of a header file being included more than once
* This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement [SWS_MemMap_00003].
*
* @section Can_Mcan_c_REF_3
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor directives or comments.
* <MA>_MemMap.h is included after each section define in order to set the current memory section as defined by AUTOSAR.
*
* @section Can_Mcan_c_REF_4
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer to object and an integer type.
* The cast is used to access memory mapped registers.
*
* @section Can_Mcan_c_REF_5
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void and an arithmetic type.
* This macro computes the address of any register by using the hardware offset of the controller. The address calculated as an unsigned int is passed to a macro for initializing the pointer with that address.
*
* @section Can_Mcan_c_REF_6
* Violates MISRA 2012 Required Rule 10.8, The value of a composite expression shall no be cast to a different essential type category or a wider essential type.
* This violation is due to the complex expression (macro) is given as parameter is not evaluated at preprocessing step.
*
* @section Can_Mcan_c_REF_7
* Violates MISRA 2012 Advisory Rule 8.7,  Functions and objects should not be defined with external 
* linkage if they are referenced in only one translation unit.
* These objects are used depending on user configuration.
*
* @section Can_Mcan_c_REF_8
* Violates MISRA 2012 Required Rule 18.1, A pointer resulting from arithmetic on a pointer operand shall address
* an element of the same array as that pointer operand
* This violation is not fixed since it was prevented by checking condition.
*/
/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Can_IPW.h"
#include "Can_Mcan.h"
#include "CanIf_Cbk.h"
#include "SchM_Can.h"
#include "Reg_eSys_MCan.h"
#include "StdRegMacros.h"

#if (CAN_DEV_ERROR_DETECT == STD_ON)
  #include "Det.h"
#endif

#ifndef CAN_TIMEOUT_AS_LOOP
    #include "Os.h"
#endif
/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/

/**
* @file           Can_Mcan.c
*/

#define CAN_VENDOR_ID_MCAN_C                    43
/* @violates @ref Can_Mcan_c_REF_1 MISRA 2012 Advisory Rule 2.5 */
#define CAN_MODULE_ID_MCAN_C                    80
#define CAN_AR_RELEASE_MAJOR_VERSION_MCAN_C     4
#define CAN_AR_RELEASE_MINOR_VERSION_MCAN_C     3
#define CAN_AR_RELEASE_REVISION_VERSION_MCAN_C  1
#define CAN_SW_MAJOR_VERSION_MCAN_C             1
#define CAN_SW_MINOR_VERSION_MCAN_C             0
#define CAN_SW_PATCH_VERSION_MCAN_C             0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/

/* Check if current file and Can_IPW header file are of the same vendor */
#if (CAN_VENDOR_ID_MCAN_C != CAN_IPW_VENDOR_ID_H)
    #error "Can_Mcan.c and Can_IPW.h have different vendor ids"
#endif
/* Check if current file and Can_IPW header file are of the same Autosar version */
#if ((CAN_AR_RELEASE_MAJOR_VERSION_MCAN_C    != CAN_IPW_AR_RELEASE_MAJOR_VERSION_H) || \
     (CAN_AR_RELEASE_MINOR_VERSION_MCAN_C    != CAN_IPW_AR_RELEASE_MINOR_VERSION_H) || \
     (CAN_AR_RELEASE_REVISION_VERSION_MCAN_C != CAN_IPW_AR_RELEASE_REVISION_VERSION_H))
    #error "AutoSar Version Numbers of Can_Mcan.c and Can_IPW.h are different"
#endif
/* Check if current file and Can_IPW header file are of the same Software version */
#if ((CAN_SW_MAJOR_VERSION_MCAN_C != CAN_IPW_SW_MAJOR_VERSION_H) || \
     (CAN_SW_MINOR_VERSION_MCAN_C != CAN_IPW_SW_MINOR_VERSION_H) || \
     (CAN_SW_PATCH_VERSION_MCAN_C != CAN_IPW_SW_PATCH_VERSION_H))
    #error "Software Version Numbers of Can_Mcan.c and Can_IPW.h are different"
#endif

/* Check if current file and Can_Mcan header file are of the same vendor */
#if (CAN_VENDOR_ID_MCAN_C != CAN_VENDOR_ID_MCAN_H)
    #error "Can_Mcan.c and Can_Mcan.h have different vendor ids"
#endif
/* Check if current file and Can_Mcan header file are of the same Autosar version */
#if ((CAN_AR_RELEASE_MAJOR_VERSION_MCAN_C    != CAN_AR_RELEASE_MAJOR_VERSION_MCAN_H) || \
     (CAN_AR_RELEASE_MINOR_VERSION_MCAN_C    != CAN_AR_RELEASE_MINOR_VERSION_MCAN_H) || \
     (CAN_AR_RELEASE_REVISION_VERSION_MCAN_C != CAN_AR_RELEASE_REVISION_VERSION_MCAN_H))
    #error "AutoSar Version Numbers of Can_Mcan.c and Can_Mcan.h are different"
#endif
/* Check if current file and Can_Mcan header file are of the same Software version */
#if ((CAN_SW_MAJOR_VERSION_MCAN_C != CAN_SW_MAJOR_VERSION_MCAN_H) || \
     (CAN_SW_MINOR_VERSION_MCAN_C != CAN_SW_MINOR_VERSION_MCAN_H) || \
     (CAN_SW_PATCH_VERSION_MCAN_C != CAN_SW_PATCH_VERSION_MCAN_H))
    #error "Software Version Numbers of Can_Mcan.c and Can_Mcan.h are different"
#endif

/* Check if current file and Reg_eSys_MCan header file are of the same vendor */
#if (CAN_VENDOR_ID_MCAN_C != CAN_VENDOR_ID_REGM)
    #error "Can_Mcan.c and Reg_eSys_MCan.h have different vendor ids"
#endif
/* Check if current file and Reg_eSys_MCan header file are of the same Autosar version */
#if ((CAN_AR_RELEASE_MAJOR_VERSION_MCAN_C != CAN_AR_RELEASE_MAJOR_VERSION_REGM) || \
     (CAN_AR_RELEASE_MINOR_VERSION_MCAN_C != CAN_AR_RELEASE_MINOR_VERSION_REGM) || \
     (CAN_AR_RELEASE_REVISION_VERSION_MCAN_C != CAN_AR_RELEASE_REVISION_VERSION_REGM))
    #error "AutoSar Version Numbers of Can_Mcan.c and Reg_eSys_MCan.h are different"
#endif
/* Check if current file and Reg_eSys_MCan header file are of the same Software version */
#if ((CAN_SW_MAJOR_VERSION_MCAN_C != CAN_SW_MAJOR_VERSION_REGM) || \
     (CAN_SW_MINOR_VERSION_MCAN_C != CAN_SW_MINOR_VERSION_REGM) || \
     (CAN_SW_PATCH_VERSION_MCAN_C != CAN_SW_PATCH_VERSION_REGM))
    #error "Software Version Numbers of Can_Mcan.c and Reg_eSys_MCan.h are different"
#endif

#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if current file and CanIf_Cbk header file are of the same version */
    #if ((CAN_AR_RELEASE_MAJOR_VERSION_MCAN_C != CANIF_CBK_AR_RELEASE_MAJOR_VERSION) || \
        (CAN_AR_RELEASE_MINOR_VERSION_MCAN_C != CANIF_CBK_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Can_Mcan.c and CanIf_Cbk.h are different"
    #endif
    
    /* Check if current file and Det header file are of the same version */
    #if (CAN_DEV_ERROR_DETECT == STD_ON)
        #if ((CAN_AR_RELEASE_MAJOR_VERSION_MCAN_C != DET_AR_RELEASE_MAJOR_VERSION) || \
             (CAN_AR_RELEASE_MINOR_VERSION_MCAN_C != DET_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Can_Mcan.c and Det.h are different"
        #endif
    #endif
#endif

/*==================================================================================================
*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/


/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/


/*==================================================================================================
*                                      LOCAL CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                      LOCAL VARIABLES
==================================================================================================*/


#define CAN_START_SEC_VAR_NO_INIT_32
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
#include "Can_MemMap.h"

/**
* @brief          Variable to hold the number of tick correspond to TimeOutDuration
* @details        Variable to hold the number of tick correspond to TimeOutDuration
*
*/
static VAR(uint32, CAN_VAR) u32CanTimeOutDuration;

#define CAN_STOP_SEC_VAR_NO_INIT_32
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

#define CAN_START_SEC_VAR_NO_INIT_8
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

static VAR(uint8, AUTOMATIC)u8MbSize[CAN_MAXCTRL_SUPPORTED];

#define CAN_STOP_SEC_VAR_NO_INIT_8
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

#define CAN_START_SEC_VAR_INIT_UNSPECIFIED
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

/**
* @brief          CAN Share Ram initialized state.
* @details        CAN Share Ram initialized state.
*
*/
static VAR(Can_SramStateType, CAN_VAR) Can_SramStatus = MCAN_SRAM_UNINITIALIZED;

/**
* @brief          Can Controller State Machine
* @details        Each CAN Controller has complex state machines implemented in hardware.
*                 For simplification, the number of states is reduced to the following four basic states in this
*                 description: UNINIT, STOPPED, STARTED and SLEEP.
*/
static VAR(Can_ControllerStateType, CAN_VAR) Can_ControllerState[CAN_MAXCTRL_SUPPORTED] = {CAN_CS_UNINIT};

#if (CAN_DUAL_CLOCK_MODE == STD_ON)
/**
* @brief          Can Controller clock mode
* @details        Represent the mode clock of Controller : NORMAL or ALTERNATE
*
*/
static VAR(Can_ClockModeType, CAN_VAR) Can_ClockMode[CAN_MAXCTRL_SUPPORTED] = {CAN_NORMAL};
#endif

#define CAN_STOP_SEC_VAR_INIT_UNSPECIFIED
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

#define CAN_START_SEC_VAR_INIT_16
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"
/**
* @brief          Can Controller Baudrate ID configured
* @details        Store the ID of Baudrate configuration. This is used during initialize Can Controller
*/
static VAR(uint16, CAN_VAR) u16Can_CtrlBaudrateID[CAN_MAXCTRL_SUPPORTED] = {0U};

#define CAN_STOP_SEC_VAR_INIT_16
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

#define CAN_START_SEC_CONST_32
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

/**
* @brief          Can Controller hardware address
* @details        Each Can Controller hardware has different base address. For simplification, 
*                 hardware address will be stroed in const variable as in order.
*/
static CONST(uint32, CAN_CONST) u32Mcan_BaseAddress[CAN_MAXCTRL_SUPPORTED] = {
#ifdef  MCAN1_BASEADDR
    MCAN1_BASEADDR
#endif /* MCAN1_BASEADDR */
#ifdef  MCAN2_BASEADDR
    ,MCAN2_BASEADDR
#endif /* MCAN2_BASEADDR */
#ifdef  MCAN3_BASEADDR
    ,MCAN3_BASEADDR
#endif /* MCAN3_BASEADDR */
#ifdef  MCAN4_BASEADDR
    ,MCAN4_BASEADDR
#endif /* MCAN4_BASEADDR */
#ifdef  TTCAN0_BASEADDR
    ,TTCAN0_BASEADDR
#endif /* TTCAN0_BASEADDR */
};

#define CAN_STOP_SEC_CONST_32
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

/*==================================================================================================
*                                      GLOBAL CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                      GLOBAL VARIABLES
==================================================================================================*/
#define CAN_START_SEC_VAR_NO_INIT_UNSPECIFIED
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

/**
* @brief          Array holding current status/run-time configuration of individual MCAN controllers
* @details        Array holding current status/run-time configuration of individual MCAN controllers
*                 - information like Guard bits, Pre-calculated MB INT masks, Storage space for id, INT nesting level,
*                 Index of MB buffer being cancelled, Index of the first MB used for Tx , Controller Options.
*
*
*/
static VAR(Can_ControllerStatusType, CAN_VAR) Can_ControllerStatuses[CAN_MAXCTRL_SUPPORTED];

#define CAN_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

/*==================================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/
#ifdef ERR_IPV_MCAN_0001 
    #if (ERR_IPV_MCAN_0001 == STD_ON)
        static FUNC(void,CAN_CODE) Can_Mcan_Implement_EARATA_8655(VAR(uint8, AUTOMATIC) u8HwOffset);
    #endif
#endif
#if (CAN_API_ENABLE_ABORT_MB == STD_ON)
    static FUNC (void, CAN_CODE) Can_MCan_Cancel( VAR(uint8, AUTOMATIC) controller, VAR(uint8, AUTOMATIC) mbindex);
#endif
static FUNC (uint8, CAN_CODE) Can_Mcan_DecodeLenghtData(VAR(uint8, AUTOMATIC) u8MbDataLength);
static FUNC (uint32, CAN_CODE) Can_Mcan_CalcDataLenghtCode(VAR(uint8, AUTOMATIC) u8MbDataLength);
static FUNC (Std_ReturnType, CAN_CODE) Can_MCan_ResetController( VAR(uint8, AUTOMATIC) controller);
static FUNC (void, CAN_CODE) Can_MCan_ChangeBaudrate( VAR(uint8, AUTOMATIC) controller);
static FUNC (void, CAN_CODE) Can_MCan_ProcessTx( VAR(uint8, AUTOMATIC) controller, VAR(uint8, AUTOMATIC) mbindex_start, VAR(uint8, AUTOMATIC) mbindex_end );
static FUNC (void, CAN_CODE) Can_MCan_ProcessRx( VAR(uint8, AUTOMATIC) controller, VAR(uint8, AUTOMATIC) u8BufferID);
/*==================================================================================================
*                                       LOCAL FUNCTIONS
==================================================================================================*/
#define CAN_START_SEC_CODE
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

/**
* @brief          Local function for canceling low priority msg during Can Write operation.
* @details        This routine is called by:
*                  - Can_MCan_Write() from Can_Mcan.c file.
*                  - Can_MCan_AbortMb() from Can_Mcan.c file.
*
* @param[in]      controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      mbindex index of the message buffer to be canceled
*
* @pre            A Tx message with a higher priority was requested for a MB.
* @post           Inform CanIf about cancellation in case of success.
*
*
*/
#if (CAN_API_ENABLE_ABORT_MB == STD_ON)
static FUNC (void, CAN_CODE) Can_MCan_Cancel( VAR(uint8, AUTOMATIC) controller, VAR(uint8, AUTOMATIC) mbindex)
{
    /* Hardware Can controller offset. */
    VAR(uint8, AUTOMATIC)    u8HwOffset = 0U;

    /* Read CAN controller offset */
    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    if ( ((uint32)(REG_READ32( MCAN_TXBRP_ADDR32(u8HwOffset)) & (uint32)((uint32)(1U) << mbindex))) == (uint32)((uint32)1U << mbindex ) )
    {
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Check transmission request pending of each Tx Buffer if have a request pending then cancellation pending */
        REG_WRITE32( MCAN_TXBCR_ADDR32(u8HwOffset), ((uint32)(1U) << (uint32)(mbindex)));
    }
}
#endif
/**
* @brief          Decode the length of the data bytes which are transmitted
* @details        Decode the length of the data bytes which are transmitted
*                 This routine is called by:
*                 - Can_MCan_ProcessTx() from Can_MCan.c file.
*
* @param[in]      The data length code of the MB
*
*
*/
static FUNC(uint8, CAN_CODE) Can_Mcan_DecodeLenghtData(VAR(uint8, AUTOMATIC) u8MbDataLength)
{
#if (CAN_FD_MODE_ENABLE == STD_ON)
    /* Initialize this variable as the maximum data length of the CAN FD module(64 bytes) */
    VAR(uint8, AUTOMATIC) u8ReturnValue = (uint8)MCAN_64_BYTES_U8;
#else
    /* Initialize this variable as the maximum data length of the CAN module(8 bytes) */
    VAR(uint8, AUTOMATIC) u8ReturnValue = (uint8)MCAN_8_BYTES_U8;
#endif
    
    if (u8MbDataLength <= 8U)
    {
        u8ReturnValue = u8MbDataLength;
    }
#if (CAN_FD_MODE_ENABLE == STD_ON)
    else
    {
        switch (u8MbDataLength)
        {
            case (9U):
            {
                u8ReturnValue = (uint8)MCAN_12_BYTES_U8;
                break;
            }
            case (10U):
            {
                u8ReturnValue = (uint8)MCAN_16_BYTES_U8;
                break;
            }
            case (11U):
            {
                u8ReturnValue = (uint8)MCAN_20_BYTES_U8;
                break;
            }
            case (12U):
            {
                u8ReturnValue = (uint8)MCAN_24_BYTES_U8;
                break;
            }
            case (13U):
            {
                u8ReturnValue = (uint8)MCAN_32_BYTES_U8;
                break;
            }
            case (14U):
            {
                u8ReturnValue = (uint8)MCAN_48_BYTES_U8;
                break;
            }
            default:
            {
                break;
            }
        }
    }
#endif

    return (u8ReturnValue);
}

/*================================================================================================*/
/**
* @brief          Calculate the data length code of MB
* @details        Calculate the data length code of MB
*                 This routine is called by:
*                 - Can_MCan_Write() from Can_MCan.c file.
*
* @param[in]      The length of the data bytes which are transmitted   
*
*
*/
static FUNC(uint32, CAN_CODE) Can_Mcan_CalcDataLenghtCode(VAR(uint8, AUTOMATIC) u8MbDataLength)
{
    VAR(uint32, AUTOMATIC) u32ReturnValue = (uint32)0U;   
    
    if (u8MbDataLength <= (uint8)MCAN_8_BYTES_U8)   
    {
        u32ReturnValue = (uint32)u8MbDataLength << MCAN_MB_DLC_SHIFT_U8;
    }
    else if (u8MbDataLength <= (uint8)MCAN_12_BYTES_U8)
    {
        u32ReturnValue = ((uint32)9U << MCAN_MB_DLC_SHIFT_U8);
    }
    else if (u8MbDataLength <= (uint8)MCAN_16_BYTES_U8)
    {
        u32ReturnValue = ((uint32)10U << MCAN_MB_DLC_SHIFT_U8);
    }
    else if (u8MbDataLength <= (uint8)MCAN_20_BYTES_U8)
    {
        u32ReturnValue = ((uint32)11U << MCAN_MB_DLC_SHIFT_U8);
    }
    else if (u8MbDataLength <= (uint8)MCAN_24_BYTES_U8)
    {
        u32ReturnValue = ((uint32)12U << MCAN_MB_DLC_SHIFT_U8);
    }
    else if (u8MbDataLength <= (uint8)MCAN_32_BYTES_U8)
    {
        u32ReturnValue = ((uint32)13U << MCAN_MB_DLC_SHIFT_U8);
    }
    else if (u8MbDataLength <= (uint8)MCAN_48_BYTES_U8)
    {
        u32ReturnValue = ((uint32)14U << MCAN_MB_DLC_SHIFT_U8);   
    }
    else
    {
        u32ReturnValue = ((uint32)15U << MCAN_MB_DLC_SHIFT_U8);
    }
    
    return (u32ReturnValue);
}

/*================================================================================================*/
#ifdef ERR_IPV_MCAN_0001 
    #if (ERR_IPV_MCAN_0001 == STD_ON)
        /**
        * @brief          Setting the Configuration Change Enable (CCE) bit during a transmission scan can halt CAN transmissions
        * @details        Setting the Configuration Change Enable (CCE) bit during a transmission scan can halt CAN transmissions
        *                 This routine is called by:
        *                 - Can_MCan_Init() from Can_MCan.c file.
        *                 - Can_MCan_SetControllerMode() from Can_MCan.c file.
        *
        * @param[in]      Hardware Can controller offset.  
        *
        *
        */
        static FUNC(void,CAN_CODE) Can_Mcan_Implement_EARATA_8655(VAR(uint8, AUTOMATIC) u8HwOffset)
        {
            VAR(uint32, AUTOMATIC) u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                static VAR(TickType, AUTOMATIC) CurrentValue = 0U;
                static VAR(TickType, AUTOMATIC) ElapsedValue = 0U;
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_TXBCR_ADDR32(u8HwOffset), (uint32)(MCAN_MASK_32BITS_U32));
            
            u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            while (( 0U != REG_READ32( MCAN_TXBRP_ADDR32(u8HwOffset))) && (u32TotalElapsedTime < u32CanTimeOutDuration))
            {
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                    u32TotalElapsedTime += (uint32)ElapsedValue;
                #else
                    u32TotalElapsedTime++;
                #endif
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /*Can enters into Initializaton mode & access to write protected registers is enabled */
            REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
            
            u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* wait until CCCR.INIT = '1'(Initialization is started) */
            while ((((REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) & (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) != (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) && (u32TotalElapsedTime < u32CanTimeOutDuration))
            {
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                    u32TotalElapsedTime += (uint32)ElapsedValue;
                #else
                    u32TotalElapsedTime++;
                #endif
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_INIT_U32);
            
            u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* wait until CCCR.INIT = '1'(Initialization is started) */
            while (((REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_INIT_U32) == MCAN_CCCR_INIT_U32) && (u32TotalElapsedTime < u32CanTimeOutDuration))
            {
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                    u32TotalElapsedTime += (uint32)ElapsedValue;
                #else
                    u32TotalElapsedTime++;
                #endif
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /*Can enters into Initializaton mode & access to write protected registers is enabled */
            REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
            
            u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* wait until CCCR.INIT = '1'(Initialization is started) */
            while ((((REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) & (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) != (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) && (u32TotalElapsedTime < u32CanTimeOutDuration))
            {
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                    u32TotalElapsedTime += (uint32)ElapsedValue;
                #else
                    u32TotalElapsedTime++;
                #endif
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Set CCE bit and clear CSR bit in CCCR */
            REG_RMW32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CCE_U32|MCAN_CCCR_CSR_U32,MCAN_CCCR_CCE_U32); 
        }
    #endif
#endif
/*==================================================================================================
*                                       GLOBAL FUNCTIONS
==================================================================================================*/
extern FUNC(boolean, COM_APPL_CODE) Can_LPduReceiveCalloutFunction(VAR(uint8, AUTOMATIC) Hrh,Can_IdType CanId,VAR(uint8, AUTOMATIC) CanDlc,const uint8 *CanSduPtr);
/*================================================================================================*/
#ifdef ERR_IPV_MCAN_0004
    #if (STD_ON == ERR_IPV_MCAN_0004)
/**
* @brief            This service obtains the communication state of the CAN controller
* @details          This service obtains the communication state of the CAN controller
*
* @param[in]        Controller    CAN controller for which is requested for communication states.
* @param[out]       ControllerCommunicationStatePtr Pointer to a memory location, where the communication state of 
*                       the CAN controller will be stored.
*
* @return           Std_ReturnType   Result of the operation.
* @retval           E_OK : Communication state request has been accepted.
* @retval           E_NOT_OK : Communication state request has not been accepted.
*
* @pre              Driver must be initialized.
*/

FUNC(uint8, CAN_CODE) Can_MCan_GetControllerCommunicationState(uint8 Controller)
{
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* Return actual communication state of Controller */
    return (uint8)(REG_BIT_GET32(MCAN_PSR_ADDR32(Controller), MCAN_PSR_ACT_U32) >> MCAN_PSR_ACT_SHIFT_U8);
}
    #endif
#endif

#if (CAN_SET_BAUDRATE_API == STD_ON)
/**
* @brief          Set Baudrate of Can Controller
*/
FUNC (Std_ReturnType, CAN_CODE) Can_MCan_SetBaudrate(VAR(uint8, AUTOMATIC) Controller, VAR(uint16, AUTOMATIC) BaudRateConfigID)
{
    u16Can_CtrlBaudrateID[Controller] = BaudRateConfigID;
    return (Std_ReturnType)E_OK;
}
#endif

#if (STD_ON == CAN_TRIGGER_TRANSMIT_EN)
/**
* @brief          The API is checking the Hardware Object is free
*
*/
FUNC(Std_ReturnType, CAN_CODE) Can_MCan_CheckBufferFree(Can_HwHandleType Hth)
{
    VAR(Std_ReturnType, AUTOMATIC) eRetVal = (Std_ReturnType)E_NOT_OK;
    VAR(uint8, AUTOMATIC) u8ControllerId = 0U;
    VAR(uint8, AUTOMATIC) u8TxBufferIdx = 0U;
    u8ControllerId = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[Hth].u8ControllerId;
    for (u8TxBufferIdx = 0; u8TxBufferIdx < CAN_MAX_TX_MB_CONFIG; u8TxBufferIdx++)
    {
        if (Hth == Can_ControllerStatuses[u8ControllerId].MbTxMapping[u8TxBufferIdx])
        {
            if (0U == (Can_ControllerStatuses[u8ControllerId].Tx_complete_guard & ((uint32)1U << u8TxBufferIdx)))
            {
                eRetVal = (Std_ReturnType)E_OK;
                break;
            }
        }
    }
    return eRetVal;
}
#endif

/**
* @brief          De-initialize CAN Controller
* @details        Bring CAN Controller registers into reset value
*                 This routine is called by:
*                 - Can_DeInit() from Can.c file.
*
*/
FUNC (void, CAN_CODE) Can_MCan_DeInitController(VAR(uint8, AUTOMATIC) Controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC) u8HwOffset = 0;
    
    /* Get the hardware offset of controller. */
    u8HwOffset = CanStatic_pControlerDescriptors[Controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* Take Controller into software initialization */
    REG_BIT_SET32(MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_INIT_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_BIT_SET32(MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CCE_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* Reset MCAN registers */
    REG_WRITE32(MCAN_NBTP_ADDR32(u8HwOffset), MCAN_NBTP_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_TDCR_ADDR32(u8HwOffset), MCAN_TDCR_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_IR_ADDR32(u8HwOffset), MCAN_IR_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_IE_ADDR32(u8HwOffset), MCAN_IE_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_ILS_ADDR32(u8HwOffset), MCAN_ILS_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_ILE_ADDR32(u8HwOffset), MCAN_ILE_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_GFC_ADDR32(u8HwOffset), MCAN_GFC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_SIDFC_ADDR32(u8HwOffset), MCAN_SIDFC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_XIDFC_ADDR32(u8HwOffset), MCAN_XIDFC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_XIDAM_ADDR32(u8HwOffset), MCAN_XIDAM_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_NDAT1_ADDR32(u8HwOffset), MCAN_NDAT1_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_NDAT2_ADDR32(u8HwOffset), MCAN_NDAT2_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_RXF0C_ADDR32(u8HwOffset), MCAN_RXF0C_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_RXBC_ADDR32(u8HwOffset), MCAN_RXBC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_RXF1C_ADDR32(u8HwOffset), MCAN_RXF1C_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_TXBC_ADDR32(u8HwOffset), MCAN_TXBC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_TXESC_ADDR32(u8HwOffset), MCAN_TXESC_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_TXBTIE_ADDR32(u8HwOffset), MCAN_TXBTIE_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_TXBCIE_ADDR32(u8HwOffset), MCAN_TXBCIE_RESET_VAL_U32);
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32(MCAN_TXEFC_ADDR32(u8HwOffset), MCAN_TXEFC_RESET_VAL_U32);
    
    /* Set Controller state to UNINIT */
    Can_ControllerState[Controller] = CAN_CS_UNINIT;
    Can_SramStatus = MCAN_SRAM_UNINITIALIZED;
}

/**
* @brief          Return the error status of the requested CAN Controller
* @details        Return the error status of the requested CAN Controller
*                 This routine is called by:
*                 - Can_GetControllerErrorState() from Can.c file.
*
*/
FUNC (Can_ErrorStateType, CAN_CODE)  Can_MCan_GetControllerErrorState(VAR(uint8, AUTOMATIC) Controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)   u8HwOffset = 0U;
    /* Update Error State of Controller */
    VAR(Can_ErrorStateType, AUTOMATIC)  eCtrlErrState = CAN_ERRORSTATE_BUSOFF;
    /* Get the hardware offset of controller. */
    u8HwOffset = CanStatic_pControlerDescriptors[Controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    if (MCAN_PSR_BO_U32 != REG_BIT_GET32(MCAN_PSR_ADDR32(u8HwOffset), MCAN_PSR_BO_U32))
    {
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if(MCAN_PSR_EP_U32 != REG_BIT_GET32(MCAN_PSR_ADDR32(u8HwOffset), MCAN_PSR_EP_U32))
        {
            eCtrlErrState = CAN_ERRORSTATE_ACTIVE;
        }
        else
        {
            eCtrlErrState = CAN_ERRORSTATE_PASSIVE;
        }
    }
    return eCtrlErrState;
}

/**
* @brief          Return the mode of the requested CAN Controller
* @details        Return the mode of the requested CAN Controller
*                 This routine is called by:
*                 - Can_GetControllerMode() from Can.c file.
*
*/
FUNC(Can_ControllerStateType, CAN_CODE) Can_MCan_GetControllerMode(VAR(uint8, AUTOMATIC) Controller)
{
    return Can_ControllerState[Controller];
}

/**
* @brief          Initialisation of indicator, statuses, etc.
* @details        Initialisation of indicator, statuses, etc.
*                 This routine is called by:
*                 - Can_Init() from Can.c file.
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           Set variables into a definite state.
*
*
*/
FUNC (void, CAN_CODE) Can_MCan_InitVariables( void )
{
    /* Index CAN controllers from configuration. */
    VAR(uint8, AUTOMATIC) u8CtrlIndex = 0U;
    /* Index of Can HwObject from configuration */
    VAR(Can_HwHandleType, AUTOMATIC) HwObjectIdx = 0U;
    /* Index of Hw buffer */
    VAR(uint16, AUTOMATIC) u16HwBufferIdx = 0U;
    VAR(uint16, AUTOMATIC) u16BufferCount = 0U;
#ifndef CAN_TIMEOUT_AS_LOOP
    VAR(float32, AUTOMATIC) f32TimeOutTemp;
  
    f32TimeOutTemp = (float32)(CAN_TIMEOUT_DURATION / (float32)CAN_TIMEOUT_COUNTER_TICK2NS());
    if ((f32TimeOutTemp - (float32)((uint32)f32TimeOutTemp)) > (float32)0)
    {
        u32CanTimeOutDuration = (uint32)f32TimeOutTemp + 1U;
    }
    else
    {
        u32CanTimeOutDuration = (uint32)f32TimeOutTemp;
    }
#else
    u32CanTimeOutDuration = CAN_TIMEOUT_DURATION;
#endif
    /* Init all global varibales/statuses for all controllers. */
    for ( u8CtrlIndex = 0U; u8CtrlIndex < (uint8)CanStatic_pCurrentConfig->u8ControllersConfigured; u8CtrlIndex++)
    {
        Can_ControllerStatuses[u8CtrlIndex].u32MBInterruptMask = 0U;
        /* Init INT Disable nesting indicator. It is incremented after every call of Can_DisableControllerInterrupts().
           The function Can_EnableControllerInterrupts() shall perform no action when Can_DisableControllerInterrupts() has not been called before. */
        Can_ControllerStatuses[u8CtrlIndex].s8IntDisableLevel = (sint8)0;
        /* Set  interrupt mode status to interrupt disabled mode. */
        Can_ControllerStatuses[u8CtrlIndex].eInterruptMode = CAN_INTERRUPT_ENABLED;
        /* Set the controller state to STOP after power-up */
        Can_ControllerState[u8CtrlIndex] = CAN_CS_STOPPED;
    #if (CAN_DUAL_CLOCK_MODE == STD_ON)
        /* Default Clock mode */
        Can_ClockMode[u8CtrlIndex] = CAN_NORMAL;
    #endif
        /* Set the controller current baudrate index as default */
        u16Can_CtrlBaudrateID[u8CtrlIndex] = Can_pControlerDescriptors[u8CtrlIndex].u16DefaultBaudRateId;
        /* Set default Tx mapping as max value type that represent of unused Object */
        for (u16HwBufferIdx = 0U; u16HwBufferIdx < (uint8)CAN_MAX_TX_MB_CONFIG; u16HwBufferIdx++)
        {
            Can_ControllerStatuses[u8CtrlIndex].MbTxMapping[u16HwBufferIdx] = (Can_HwHandleType)0xFFFFU;
        }
        u16BufferCount = 0U;
        /* Mapping HwObject Id for each hardware buffer */
        for (HwObjectIdx = 0U; HwObjectIdx < Can_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; HwObjectIdx++)
        {
            if ((u8CtrlIndex == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u8ControllerId) && \
                (CAN_TRANSMIT == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].eMBType)
                )
            {
                for (u16HwBufferIdx = 0U; u16HwBufferIdx < Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u16HwObjectCount; u16HwBufferIdx++)
                {
                    Can_ControllerStatuses[u8CtrlIndex].MbTxMapping[u16BufferCount] = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u32HWObjID;
                    if ((boolean)TRUE != Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].CanHwObjectUsesPolling)
                    {
                        Can_ControllerStatuses[u8CtrlIndex].u32MBInterruptMask |= (uint32)1U << u16BufferCount;
                    }
                    u16BufferCount++;
                }
            }
        }
        
    }
}

/*================================================================================================*/
/**
* @brief          Service for initializing the Can driver module according to a configuration set referenced by Config.
* @details        Driver Module Initialization - MCan Driver Module Initialization
*                 This routine is called by:
*                  - Can_Init() from Can.c file.
*
* @param[in]      Controller Can controller to be initialized
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           Controller is enabled and set into Stop mode.
*
*
*/

FUNC (void, CAN_CODE) Can_MCan_InitController( VAR(uint8, AUTOMATIC) controller )
{
    /* Hardware Can controller offset. */
    VAR(uint8, AUTOMATIC)  u8HwOffset = 0U;
    /* Address of Share Ram Message region */
    VAR(uint32, AUTOMATIC) u32OffsetShareRam;
    VAR(uint32, AUTOMATIC) u32TotalElapsedTime = 0U;
#ifndef CAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC) CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC) ElapsedValue = 0U;
#endif
    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
#ifdef ERR_IPV_MCAN_0001 
    #if (ERR_IPV_MCAN_0001 == STD_ON)
        Can_Mcan_Implement_EARATA_8655(u8HwOffset);
    #endif
#endif

#if((!defined(ERR_IPV_MCAN_0001)) && (defined (ERR_IPV_MCAN_0003))) 
    #if (ERR_IPV_MCAN_0003 == STD_ON)
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /*Can enters into Initializaton mode & access to write protected registers is enabled */
        REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
        
        u32TotalElapsedTime = 0U;
        #ifndef CAN_TIMEOUT_AS_LOOP
            (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
        #endif
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        while ((((REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) & (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) != (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) && (u32TotalElapsedTime < u32CanTimeOutDuration))
        {
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                u32TotalElapsedTime += (uint32)ElapsedValue;
            #else
                u32TotalElapsedTime++;
            #endif
        }
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
    #else
        #error: The define ERR_IPV_MCAN_0003 should not be STD_OFF
    #endif
#else
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* Set INIT bit to change controller mode to initialization state */
    REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_INIT_U32);
#endif
 
    u32TotalElapsedTime = 0U;
    #ifndef CAN_TIMEOUT_AS_LOOP
        (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
    #endif
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* wait until CCCR.INIT = '1'(Initialization is started) */
    while ((((REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) & MCAN_CCCR_INIT_U32) != MCAN_CCCR_INIT_U32) && (u32TotalElapsedTime < u32CanTimeOutDuration))
    {
        #ifndef CAN_TIMEOUT_AS_LOOP
            (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
            u32TotalElapsedTime += (uint32)ElapsedValue;
        #else
            u32TotalElapsedTime++;
        #endif
    }
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* Set CCCR.CCE bit (The CPU has write access to the protected configuration registers (while CCCR.INIT = 1))*/
    REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CCE_U32);
    /* Initializ Share Ram only once for all controllers */
    if(Can_SramStatus == MCAN_SRAM_UNINITIALIZED)
    {       
        /* clear Share RAM */
        u32OffsetShareRam = (uint32)( IPV_MCAN_START_ADDRESS_OFFSET_SHARE_RAM_U32 + SCM_RAM_BASEADDR);
        do
        {
            if ((u32OffsetShareRam < (IPV_MCAN_START_ADDRESS_OFFSET_TTCAN_U32 + SCM_RAM_BASEADDR)) || (u32OffsetShareRam > (IPV_MCAN_END_ADDRESS_OFFSET_TTCAN_U32 + SCM_RAM_BASEADDR)))
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(u32OffsetShareRam, MCAN_NOT_MASK_32BITS_U32);
            }
            u32OffsetShareRam = ((uint32)(u32OffsetShareRam + 4U));
        } while(u32OffsetShareRam <= (uint32)(IPV_MCAN_END_ADDRESS_OFFSET_USEABLE_SHARE_RAM_U32 + SCM_RAM_BASEADDR));
        Can_SramStatus = MCAN_SRAM_INITIALIZED;
    }
    Can_MCan_ChangeBaudrate(controller);
}

/*================================================================================================*/
/**
* @brief          Service for reset the controller.
* @details        Re-initialization must start with a reset (soft).
*                 This routine is called by:
*                  - Can_MCan_ChangeBaudrate() from Can_Mcan.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done (CAN_FCA_INDEX / CAN_FCB_INDEX).
*                 This ID depends by the order of the controller's definition in the Tresos 'CanController' list.
*                 If CanController_0 is assigned to CANB then CAN_FCB_INDEX is 0.
*                 These indexes are used for access inside 'Can_ControlerDescriptorType' structure.
*
* @post           Controller is enabled and reset.
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_MCan_ResetController( VAR(uint8, AUTOMATIC) controller)
{
    /* Variable store return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)          u8HwOffset = 0U;
    VAR(uint32, AUTOMATIC) u32TotalElapsedTime = 0U;
#ifndef CAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC) CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC) ElapsedValue = 0U;
#endif
    /* Get the hardware offset for this controller. */
    u8HwOffset =  CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* The re-initialization of controller start with a Soft-Reset. Test if Can is not ready -> can be in any of disable, Doze/Stop/Freeze modes. */
    /* Set the INIT & CCE bits of CCCR register,to enter CAN into reset mode. */
    REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_INIT_U32);
    
    u32TotalElapsedTime = 0U;
    #ifndef CAN_TIMEOUT_AS_LOOP
        (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
    #endif
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* wait until CCCR.INIT = '1'(Initialization is started) */
    while ((((REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) & MCAN_CCCR_INIT_U32) != MCAN_CCCR_INIT_U32) && (u32TotalElapsedTime < u32CanTimeOutDuration))
    {
        #ifndef CAN_TIMEOUT_AS_LOOP
            (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
            u32TotalElapsedTime += (uint32)ElapsedValue;
        #else
            u32TotalElapsedTime++;
        #endif
    }
    if(u32TotalElapsedTime < u32CanTimeOutDuration)
    {
        Can_ControllerState[controller] = CAN_CS_STOPPED;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Disable all interrupt flags by writing '0' in the all of bits */
        REG_WRITE32( MCAN_IE_ADDR32(u8HwOffset), MCAN_NOT_MASK_32BITS_U32);
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Clear all interrupt flags by writing '1' in the all of bits */
        REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_MASK_32BITS_U32);
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Clear all New Data 1 flags by writing '1' in the all of bits */
        REG_WRITE32( MCAN_NDAT1_ADDR32(u8HwOffset), MCAN_MASK_32BITS_U32);
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Clear all New Data 2 flags by writing '1' in the all of bits*/
        REG_WRITE32( MCAN_NDAT2_ADDR32(u8HwOffset), MCAN_MASK_32BITS_U32);
        
        eReturnValue = (Std_ReturnType)E_OK;
    }

    return eReturnValue;
}
/*================================================================================================*/
/**
* @brief          Service for (re)initializing only CAN controller specific settings.
* @details        CAN controller (re-)initialization.
*                 This routine is called by:
*                  - Can_Init() from Can.c file.
*                  - Can_ChangeBaudrate() from Can.c file.
*                  - Can_SetBaudrate() from Can.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           Set the MBs and interrupts into predefinite state for Can bus communication.
*
*
*/

static FUNC (void, CAN_CODE) Can_MCan_ChangeBaudrate( VAR(uint8, AUTOMATIC) controller)
{
    /* Local copy of pointer to the controller descriptor. */
    P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor = NULL_PTR;
    /* Local copy of pointer to the section address offset descriptor. */
    P2CONST(Can_ControllerSectionOffsetType, AUTOMATIC, CAN_APPL_CONST) pCanControllerSectionOffset = NULL_PTR;
    /* Local copy of pointer to the static controller descriptor. */
    P2CONST(CanStatic_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanStaticControlerDescriptor = NULL_PTR;
#if (CAN_RXFIFO_ENABLE == STD_ON)        
    /* Local copy of pointer to the Fifo configuration structure */        
    P2CONST(Can_ControllerRxFifoConfigType, AUTOMATIC, CAN_APPL_CONST) pCanControllerRxFifoConfig = NULL_PTR;
    /*Variable stores Shared RAM address offset of Rx FIFO 0 section */
    VAR(uint16, AUTOMATIC)            u32RxFifo0AddOffset = 0U;
    /*Variable stores Shared RAM address offset of Rx FIFO 1 section */
    VAR(uint16, AUTOMATIC)            u32RxFifo1AddOffset = 0U;
#endif
    /*Number of Standrad filter elements configured */
    VAR(uint8, AUTOMATIC)             u8NumberStdRxFilterCount = 0U;
    /*Number of Extended filter elements configured */
    VAR(uint8, AUTOMATIC)             u8NumberExtdRxFilterCount = 0U;
    /* Hardware Can controller offset. */
    volatile VAR(uint8, AUTOMATIC)             u8HwOffset = 0U;
    /*Stores the reset controller function status */
    VAR(Std_ReturnType, AUTOMATIC)    eResetReturn = (Std_ReturnType)E_OK;
    /* Variable to hold the index of the current baudrate */
    VAR(uint16, AUTOMATIC) u16BaudrateIndex = 0U;
    /* Used to access configured table id and filtermask. */
    VAR(uint8, AUTOMATIC)             u8TempIndex = 0U;
    /*Variable for offset Filter*/
    VAR(uint8, AUTOMATIC)             u8RxFilterOffset = 0U;
    /*Variable configuration Filter */
    VAR(uint8, AUTOMATIC)             u8RxFilterConfig = 0U;
    /*Variable for type Filer */
    VAR(uint8, AUTOMATIC)             u8RxFilterType = 0U;
    /*Variable stores value Filter ID1*/
    VAR(uint32, AUTOMATIC)            u32RxFilterId1Value = 0U;
    /*Variable stores value Filter ID2*/
    VAR(uint32, AUTOMATIC)            u32RxFilterId2Value = 0U;
    /*Variable stores Shared RAM address offset of standard filter section */
    VAR(uint32, AUTOMATIC)            u32StdRxFilterAddOffset = 0U;
    /*Variable stores Shared RAM address offset of standard filter section */
    VAR(uint32, AUTOMATIC)            u32ExtdRxFilterAddOffset = 0U;
    /*Variable stores Shared RAM address offset of Rx Buffer section */
    VAR(uint32, AUTOMATIC)            u32RxBufferAddOffset = 0U;
    /*Variable stores Shared RAM address offset of Tx Buffer section */
    VAR(uint32, AUTOMATIC)            u32TxBufferAddOffset = 0U;        
    VAR(uint8, AUTOMATIC)             u8NumTxBuffer = 0U;        
    VAR(uint8, AUTOMATIC)             u8NumRxBuffer = 0U;        
    VAR(uint32, AUTOMATIC)            u32TempReg = 0U;
#if (CAN_FD_MODE_ENABLE == STD_ON)
    VAR(uint32, AUTOMATIC)u32RxBufferDataSize = 0U;
    VAR(uint32, AUTOMATIC)u32TxDataSize = 0U;
#endif
    pCanControlerDescriptor = &(Can_pCurrentConfig->ControlerDescriptors[controller]);
    
    /* Get pointer to Section Address offset of this controller */
    pCanControllerSectionOffset = pCanControlerDescriptor->pControllerSectionOffsetPtr;
    pCanStaticControlerDescriptor = &(CanStatic_pCurrentConfig->StaticControlerDescriptors[controller]);
    /* Get the hardware offset for this controller. */
    u8HwOffset = pCanStaticControlerDescriptor->u8ControllerOffset;
    
    /* Get the shared RAM offset address of standard filter of this controller */
    u32StdRxFilterAddOffset = pCanControllerSectionOffset->StandardFilterOffset;
    
    /* Get the shared RAM offset address of extended filter of this controller */
    u32ExtdRxFilterAddOffset = pCanControllerSectionOffset->ExtendedFilterOffset;
#if (CAN_RXFIFO_ENABLE == STD_ON)          
    /* Get the shared RAM offset address of Rx FIFO 0 of this controller */
    u32RxFifo0AddOffset = pCanControllerSectionOffset->RxFifo0Offset;
    
    /* Get the shared RAM offset address of Rx FIFO 1 of this controller */
    u32RxFifo1AddOffset = pCanControllerSectionOffset->RxFifo1Offset;
#endif        
    /* Get the shared RAM offset address of Rx Buffer of this controller */
    u32RxBufferAddOffset = pCanControllerSectionOffset->RxBufferOffset;
    
    /* Get the shared RAM offset address of Tx Buffer of this controller */
    u32TxBufferAddOffset = pCanControllerSectionOffset->TxBufferOffset;
    
    u8NumTxBuffer = pCanControlerDescriptor->u8MaxMbTxCount;
    
    u8NumRxBuffer = pCanControlerDescriptor->u8MaxMbRxCount;

    eResetReturn = Can_MCan_ResetController( controller);

    /* Get the index of the current baudrate */
    u16BaudrateIndex = u16Can_CtrlBaudrateID[controller];

    if ((Std_ReturnType)E_OK == eResetReturn )
    {
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* set the can controller to initialisation mode */
        REG_WRITE32( MCAN_CCCR_ADDR32(u8HwOffset), (uint32)(MCAN_CCCR_INIT_U32 | MCAN_CCCR_CCE_U32));
        /*Set to ASM mode */
        if ( CAN_CONTROLLERCONFIG_CCCR_ASM_EN_U32 == (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_CCCR_ASM_EN_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /*Set the can controler restricted operation mode active */
            REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_ASM_U32);
        }
        else
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /*Set the can controler normal operation mode active */
            REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_ASM_U32);
        }
        /* Set to Bus Monitoring Mode */
        if ( CAN_CONTROLLERCONFIG_CCCR_MON_EN_U32 == (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_CCCR_MON_EN_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Bus Monitoring Mode is enabled */
            REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_MON_U32);
        }
        else
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Bus Monitoring Mode is disabled */
            REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_MON_U32);
        }
        
    #if (CAN_FD_MODE_ENABLE == STD_ON)
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Configure the FD feature */
        if( ((uint32)(MCAN_CCCR_INIT_U32 | MCAN_CCCR_CCE_U32)) == (((uint32)(REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)))) & ((uint32)(MCAN_CCCR_INIT_U32 | MCAN_CCCR_CCE_U32))))
        {
            /* Check the FD feature is enabled */
        #ifdef IPV_MCAN
        #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
            if ( MCAN_CCCR_CME_FDN_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdEnable) )
        #endif
        #if (IPV_MCAN == IPV_MCAN_00_00_00_21) 
            if ( MCAN_CCCR_FDOE_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdEnable) )
        #endif 
        #endif 
            {
                /* Check the switch rate feature */
            #ifdef IPV_MCAN
            #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
                if ( MCAN_CCCR_CME_BRS_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanControllerTxBitRateSwitch) )
            #endif
            #if (IPV_MCAN == IPV_MCAN_00_00_00_21) 
                if ( MCAN_CCCR_BRSE_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanControllerTxBitRateSwitch) )
            #endif
            #endif
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* In this case, CAN operate with the switch rate feature */
                    /* Write in the CME field */
                    REG_BIT_SET32(MCAN_CCCR_ADDR32(u8HwOffset),((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanControllerTxBitRateSwitch)));
                }
                /* Write baudrate in FBTP register */
            #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(MCAN_FBTP(u8HwOffset), (uint32)(((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdCbtRegister)) & MCAN_FBTP_MASK_U32));
            #endif
            #if (IPV_MCAN == IPV_MCAN_00_00_00_21)
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(MCAN_DBTP_ADDR32(u8HwOffset), (uint32)(((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdCbtRegister)) & MCAN_DBTP_MASK_U32));
            #endif
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_RMW32(MCAN_TDCR_ADDR32(u8HwOffset), MCAN_TDCR_TDCO_MASK_U32,(uint32)((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanControllerTrcvDelayCompensation)));
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                /* write data configuration into CCCR register */
                /* Enable FD feature */
                REG_BIT_SET32(MCAN_CCCR_ADDR32(u8HwOffset),pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdEnable);
            }
        }
        
        /* Calculate the MB size and the data lenght code for MB */
    #ifdef IPV_MCAN
    #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
        if ( MCAN_CCCR_CME_FDN_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdEnable) )
    #endif
    #if (IPV_MCAN == IPV_MCAN_00_00_00_21)
        if ( MCAN_CCCR_FDOE_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanFdEnable) )
    #endif 
    #endif 
        {                 
            switch ((uint8)CAN_REAL_PAYLOAD_U8)
            {
                case (MCAN_8_BYTES_U8):
                {
                    u8MbSize[controller] = 16U;
                    u32RxBufferDataSize = MCAN_RXESC_8_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_8_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_12_BYTES_U8):
                {
                    u8MbSize[controller] = 20U;
                    u32RxBufferDataSize = MCAN_RXESC_12_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_12_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_16_BYTES_U8):
                {
                    u8MbSize[controller] = 24U;
                    u32RxBufferDataSize = MCAN_RXESC_16_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_16_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_20_BYTES_U8):
                {
                    u8MbSize[controller] = 28U;
                    u32RxBufferDataSize = MCAN_RXESC_20_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_20_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_24_BYTES_U8):
                {
                    u8MbSize[controller] = 32U;
                    u32RxBufferDataSize = MCAN_RXESC_24_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_24_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_32_BYTES_U8):
                {
                    u8MbSize[controller] = 40U;
                    u32RxBufferDataSize = MCAN_RXESC_32_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_32_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_48_BYTES_U8):
                {
                    u8MbSize[controller] = 56U;
                    u32RxBufferDataSize = MCAN_RXESC_48_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_48_BYTES_DATA_SIZE_U32;
                    break;
                }
                case (MCAN_64_BYTES_U8):
                {
                    u8MbSize[controller] = 72U;
                    u32RxBufferDataSize = MCAN_RXESC_64_BYTES_DATA_SIZE_U32;
                    u32TxDataSize = MCAN_TXESC_64_BYTES_DATA_SIZE_U32;
                    break;
                }
                default :
                {
                    break;
                }
            }
        }
        else
        {
            u8MbSize[controller] = 16U;   
            u32RxBufferDataSize = MCAN_RXESC_8_BYTES_DATA_SIZE_U32;
            u32TxDataSize = MCAN_TXESC_8_BYTES_DATA_SIZE_U32;
        }
    #else
        u8MbSize[controller] = 16U;
    #endif
        /* Configure the Baud Rate settings for the CAN controller */
    #if (CAN_DUAL_CLOCK_MODE == STD_ON)
        if (Can_ClockMode[controller] != CAN_NORMAL)
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_NBTP_ADDR32(u8HwOffset), pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].u32ControlRegisterAlternate);         
        }
        else
        {
    #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_NBTP_ADDR32(u8HwOffset), pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].u32ControlRegister);
    #if (CAN_DUAL_CLOCK_MODE == STD_ON)
        }
    #endif
        /* configure the CAN controller into internal loop back mode */
        if ( CAN_CONTROLLERCONFIG_CCCR_TEST_EN_U32 == (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_CCCR_TEST_EN_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Test Mode, write access to register TEST enabled */
            REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_TEST_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Bus Monitoring Mode is enabled */
            REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_MON_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Loop Back mode is enabled */
            REG_BIT_SET32( MCAN_TEST_ADDR32(u8HwOffset), MCAN_TEST_LBCK_U32);
        }
        else
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Normal operation, register TEST holds reset values */
            REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_TEST_U32);
        }

        /* Init the Rx filter table. */                                   
        for ( u8TempIndex = 0U; u8TempIndex < (Can_pCurrentConfig->u8NumberRxFilterTable); u8TempIndex++)
        {
            if (u8HwOffset == (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].u8ControllerOffset)
            {
                /* Calculate the physical address for each table to write the Table ID and FilterMask. */
                u8RxFilterOffset = (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].u8RxFilterOffset;
                u8RxFilterConfig = (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].u8RxFilterConfig;
                u8RxFilterType = (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].u8RxFilterType;
                u32RxFilterId1Value = (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].u32RxFilterId1Value;
                u32RxFilterId2Value = (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].u32RxFilterId2Value;

                #if (CAN_EXTENDEDID == STD_ON)
                if ( CAN_STANDARD == (Can_pCurrentConfig->pRxFilterTableConfig)[u8TempIndex].eRxFilterMbType)
                {
                #endif /* (CAN_EXTENDEDID == STD_ON) */
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Clear the Standard Message ID Filter elements */
                    REG_WRITE32( (SCM_RAM_BASEADDR + ((uint32)u32StdRxFilterAddOffset << 2) + ((u8RxFilterOffset) * MCAN_SRAM_STD_FTR_LENGTH_U32)),0U);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32( (SCM_RAM_BASEADDR + ((uint32)u32StdRxFilterAddOffset << 2) + ((u8RxFilterOffset) * MCAN_SRAM_STD_FTR_LENGTH_U32)), \
                                    (uint32)MCAN_SRAM_SMIDFE_SFID2_MASK_U32,u32RxFilterId2Value); 
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32( (SCM_RAM_BASEADDR + ((uint32)u32StdRxFilterAddOffset  << 2) + ((u8RxFilterOffset) * MCAN_SRAM_STD_FTR_LENGTH_U32)), \
                                    MCAN_SRAM_SMIDFE_SFID1_MASK_U32,u32RxFilterId1Value << MCAN_SRAM_SMIDFE_SFID1_SHIFT_U8);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32( (SCM_RAM_BASEADDR + ((uint32)u32StdRxFilterAddOffset  << 2) + ((u8RxFilterOffset) * MCAN_SRAM_STD_FTR_LENGTH_U32)), \
                                   MCAN_SRAM_SMIDFE_SFEC_MASK_U32,(uint32)u8RxFilterConfig << MCAN_SRAM_SMIDFE_SFEC_SHIFT_U8) ;
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32( (SCM_RAM_BASEADDR + ((uint32)u32StdRxFilterAddOffset << 2) + ((u8RxFilterOffset) * MCAN_SRAM_STD_FTR_LENGTH_U32)), \
                                   MCAN_SRAM_SMIDFE_SFT_MASK_U32,(uint32)u8RxFilterType<< MCAN_SRAM_SMIDFE_SFT_SHIFT_U8);
                    u8NumberStdRxFilterCount++;
                #if (CAN_EXTENDEDID == STD_ON)
                }
                else
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Clear the Extended Message ID Filter elements */                
                    REG_WRITE32((SCM_RAM_BASEADDR+ ((uint32)u32ExtdRxFilterAddOffset << 2) + ((u8RxFilterOffset) * MCAN_SRAM_EXD_FTR_LENGTH_U32)), 0U);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Clear the Extended Message ID Filter elements */
                    REG_WRITE32((SCM_RAM_BASEADDR+ ((uint32)u32ExtdRxFilterAddOffset  << 2) + ((u8RxFilterOffset) * MCAN_SRAM_EXD_FTR_LENGTH_U32) + 4U), 0U);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32((SCM_RAM_BASEADDR+ ((uint32)u32ExtdRxFilterAddOffset  << 2) + (((u8RxFilterOffset) * MCAN_SRAM_EXD_FTR_LENGTH_U32)+4U)), \
                                  MCAN_SRAM_EMIDFE_EFID_MASK_U32,u32RxFilterId2Value );
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32((SCM_RAM_BASEADDR+ ((uint32)u32ExtdRxFilterAddOffset << 2) + ((u8RxFilterOffset) * MCAN_SRAM_EXD_FTR_LENGTH_U32)), \
                                   MCAN_SRAM_EMIDFE_EFID_MASK_U32,u32RxFilterId1Value);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32((SCM_RAM_BASEADDR+ ((uint32)u32ExtdRxFilterAddOffset << 2) + ((u8RxFilterOffset) * MCAN_SRAM_EXD_FTR_LENGTH_U32)), \
                                  MCAN_SRAM_EMIDFE_EFEC_MASK_U32,(uint32)u8RxFilterConfig << MCAN_SRAM_EMIDFE_EFEC_SHIFT_U8);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_RMW32((SCM_RAM_BASEADDR+ ((uint32)u32ExtdRxFilterAddOffset << 2)  + (((u8RxFilterOffset) * MCAN_SRAM_EXD_FTR_LENGTH_U32)+4U)), \
                                   MCAN_SRAM_EMIDFE_EFEC_MASK_U32,(uint32)u8RxFilterType << MCAN_SRAM_EMIDFE_EFT_SHIFT_U8);
                    u8NumberExtdRxFilterCount++;
                }
                #endif /* (CAN_EXTENDEDID == STD_ON) */
            }
        }
        
        /* Initialization of Standard ID filter section by writing value to SIDFC register */
        u32TempReg = (uint32)u32StdRxFilterAddOffset << MCAN_SIDFC_FLSSA_SHIFT_U8;
        
        u32TempReg |= (uint32)u8NumberStdRxFilterCount << MCAN_SIDFC_LSS_SHIFT_U8;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( MCAN_SIDFC_ADDR32(u8HwOffset), u32TempReg);
        
        /* Initialization of Extended ID filter section by writing value to XIDFC register */
        
        u32TempReg = (uint32)u32ExtdRxFilterAddOffset << MCAN_XIDFC_FLESA_SHIFT_U8;
        
        u32TempReg |= (uint32)u8NumberExtdRxFilterCount << MCAN_XIDFC_LSE_SHIFT_U8;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( MCAN_XIDFC_ADDR32(u8HwOffset), u32TempReg);
        /* Initialization of RxBuffer section */
        if(u8NumRxBuffer > 0U)
        {
            /*Initialization address offset section by writing value to RXBC register */
            u32TempReg = (uint32)u32RxBufferAddOffset << MCAN_RXBC_RBSA_SHIFT_U8;
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_RXBC_ADDR32(u8HwOffset), u32TempReg);
            /* Initialization of RxBuffer data payload size by writting value to RXESC */
        #if (CAN_FD_MODE_ENABLE == STD_ON)
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_RBDS_MASK_U32, (u32RxBufferDataSize << MCAN_RXESC_RBDS_SHIFT_U8));
        #else
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_RBDS_MASK_U32, ((uint32)0U << MCAN_RXESC_RBDS_SHIFT_U8));
        #endif
        }
        
        /* Initialization of TxBuffer section */
        if(u8NumTxBuffer > 0U)
        {
            /*Initialization address offset section by writing value to TXBC register */
            u32TempReg = (uint32)u32TxBufferAddOffset << MCAN_TXBC_TBSA_SHIFT_U8;
            
            /*Initialization number of Tx Buffer by writing value to TXBC register */
            u32TempReg |= (uint32)u8NumTxBuffer << MCAN_TXBC_NDTB_SHIFT_U8;
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_TXBC_ADDR32(u8HwOffset), u32TempReg & (MCAN_TXBC_MASK_U32) );
            
            /* Initialization of TxBuffer element size by writting value to TXESC */
        #if (CAN_FD_MODE_ENABLE == STD_ON)
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_TXESC_ADDR32(u8HwOffset), u32TxDataSize);
        #else
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_TXESC_ADDR32(u8HwOffset), 0U);
        #endif
        }
    #if (CAN_RXFIFO_ENABLE == STD_ON)
        /* Initialization of Rx FIFO 0 section */
        if( NULL_PTR != pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)
        {   
            /* Get the pointer to the FIFO 0 configuration structure */
            pCanControllerRxFifoConfig = pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr;
            /* Initialized FIFO address offset section */
            u32TempReg = (uint32)u32RxFifo0AddOffset << MCAN_RXF0C_F0SA_SHIFT_U8;
            /* Initialized FIFO Depth */
            u32TempReg |= (uint32)(pCanControllerRxFifoConfig->FIFODepth) << MCAN_RXF0C_F0S_SHIFT_U8;
        #if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)                
            /* Initialized FIFO Watermask Warning Level */
            u32TempReg |= (uint32)(pCanControllerRxFifoConfig->FIFOWaterMaskLevel) << MCAN_RXF0C_F0WM_SHIFT_U8;
        #else
            /* Disabled RX FIFO 0 Watermark interrupt  */
            u32TempReg &= ~(MCAN_RXF0C_F0WM_MASK_U32);
        #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Write value to RXF0C register */
            REG_WRITE32( MCAN_RXF0C_ADDR32(u8HwOffset), u32TempReg & (MCAN_RXF0C_MASK_U32) );
            /* Initialized Rx FIFO 0 data payload size */
        #if (CAN_FD_MODE_ENABLE == STD_ON)
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_F0DS_MASK_U32, (u32RxBufferDataSize << MCAN_RXESC_F0DS_SHIFT_U8));
        #else
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_F0DS_MASK_U32, ((uint32)0U << MCAN_RXESC_F0DS_SHIFT_U8));
        #endif
        }
        
        /* Initialization of Rx FIFO 1 section */
        if( NULL_PTR != pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr)
        {
            /* Get the pointer to the FIFO 1 configuration structure */
            pCanControllerRxFifoConfig = pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr;
            /* Initialized FIFO address offset section */
            u32TempReg = (uint32)u32RxFifo1AddOffset << MCAN_RXF1C_F1SA_SHIFT_U8;
            /* Initialized FIFO Depth */
            u32TempReg |= (uint32)(pCanControllerRxFifoConfig->FIFODepth) << MCAN_RXF1C_F1S_SHIFT_U8;
        #if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
            /* Initialized FIFO Watermask Warning Level */
            u32TempReg |= (uint32)(pCanControllerRxFifoConfig->FIFOWaterMaskLevel) << MCAN_RXF1C_F1WM_SHIFT_U8;
        #else
            /* Disabled RX FIFO 1 Watermark interrupt  */
            u32TempReg &= ~(MCAN_RXF1C_F1WM_MASK_U32);
        #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Write value to RXF1C register */
            REG_WRITE32( MCAN_RXF1C_ADDR32(u8HwOffset), u32TempReg & (MCAN_RXF1C_MASK_U32) );
            
            /* Initialized Rx FIFO 1 data payload size */
        #if (CAN_FD_MODE_ENABLE == STD_ON)
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_F1DS_MASK_U32, (u32RxBufferDataSize << MCAN_RXESC_F1DS_SHIFT_U8));
        #else
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(MCAN_RXESC_ADDR32(u8HwOffset), MCAN_RXESC_F1DS_MASK_U32, ((uint32)0U << MCAN_RXESC_F1DS_SHIFT_U8));
        #endif
        }
    #endif
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( MCAN_GFC_ADDR32(u8HwOffset), MCAN_GFC_MASK_U32);

        /*Configure the Interrupt line source */
    #if (CAN_INTERRUPT_SUPPORTED == STD_ON)
        if( CAN_CTLR_CONFIG_ILE_INTL0_EN_U32 == (CAN_CTLR_CONFIG_ILE_INTL0_EN_U32 & pCanControlerDescriptor->u32Options) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Interrupt assigned to interrupt line M_CAN INT0 */
            REG_WRITE32( MCAN_ILS_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Enable Interrupt Line 0 */
            REG_WRITE32( MCAN_ILE_ADDR32(u8HwOffset), (uint32)(MCAN_ILE_EINT0_U32));
        }

        if( CAN_CTLR_CONFIG_ILE_INTL1_EN_U32 == (CAN_CTLR_CONFIG_ILE_INTL1_EN_U32 & pCanControlerDescriptor -> u32Options) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Interrupt assigned to interrupt line M_CAN INT1 */
            REG_WRITE32( MCAN_ILS_ADDR32(u8HwOffset),(uint32)MCAN_MASK_32BITS_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Enable Interrupt Line 1 */
            REG_WRITE32( MCAN_ILE_ADDR32(u8HwOffset),(uint32)(MCAN_ILE_EINT1_U32));
        }
    #else
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Disable interrupt line when it is not used */
        REG_WRITE32( MCAN_ILE_ADDR32(u8HwOffset), MCAN_NOT_MASK_32BITS_U32);
    #endif
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /*clear the contents of IR register */
        REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset),(uint32)(MCAN_MASK_32BITS_U32));
    }
}
/*================================================================================================*/
/**
* @brief          Service to Perform software triggered state transitions of the CAN controller State machine.
* @details        Transition controller to another state/mode.
*                 This routine is called by:
*                  - Can_SetControllerMode() from Can.c file.
*                  - Can_MainFunction_BusOff() from Can.c file.
*                  - Can_MCan_SetControllerMode() from Can_MCan.c file.
*
* @param[in]      CAN controller for which mode has to be changed
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
* @param[in]      Transition Possible transitions
*
* @return         Std_ReturnType
* @retval         E_OK transition initiated
* @retval         E_NOT_OK development or production error
*
* @pre            Controller is configured and must be into a state that permit the valid transition to another different state.
* @post           Shall enable interrupts that are needed in the new state. Shall disable interrupts that are not allowed in the new state.
*
* @requirements   CAN283
*
*/


FUNC (Std_ReturnType, CAN_CODE) Can_MCan_SetControllerMode( VAR(uint8, AUTOMATIC) controller, \
                                                            P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor, \
                                                            VAR(Can_ControllerStateType, AUTOMATIC) Transition, \
                                                            VAR(boolean, AUTOMATIC) canif_notification_required
                                                          )
{
  /* Variable store return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    /* Template Variable */
    VAR(uint32, AUTOMATIC)          u32TempVar = 0U;
    
    VAR(uint32, AUTOMATIC) u32TotalElapsedTime = 0U;
#ifndef CAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC) CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC) ElapsedValue = 0U;
#endif

    P2CONST(CanStatic_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanStaticControlerDescriptor = NULL_PTR;
#if (CAN_RXFIFO_ENABLE == STD_ON)        
    P2CONST(Can_ControllerRxFifoConfigType, AUTOMATIC, CAN_APPL_CONST) pCanControllerRxFifoConfig = NULL_PTR;
#endif   
    pCanStaticControlerDescriptor = &(CanStatic_pCurrentConfig->StaticControlerDescriptors[controller]);
    
    /* Get the hardware offset for this controller. */
    u8HwOffset = pCanStaticControlerDescriptor->u8ControllerOffset;

    switch (Transition)
    {
        /* CANIF_CS_STARTED -> CANIF_CS_STOPPED. */
        case (CAN_CS_STOPPED):

            if ( CAN_CS_STOPPED == Can_ControllerState[controller])
            {
                eReturnValue = (Std_ReturnType)E_OK;
            }
            else
            {
                if ( CAN_CS_STARTED == Can_ControllerState[controller])
                {
                    /* Cancel the MB (just in case it is scheduled for Tx). This is a HARD ABORT, confirmation of whether the MB was transmitted or not is not required. */
                    /*
                        (CAN282) The function Can_SetControllerMode(CAN_CS_STOPPED) shall cancel pending messages.
                        (CAN273)After bus-off detection, the Can module shall cancel still pending messages without raising a cancellation notification.
                    */
                    /* Clear Tx_complete_guard flags, in this state driver does not allow transmit, but guard for sure. */
                    SchM_Enter_Can_CAN_EXCLUSIVE_AREA_03();
                    Can_ControllerStatuses[controller].Tx_complete_guard = (uint32)0x0UL;
                    SchM_Exit_Can_CAN_EXCLUSIVE_AREA_03();
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32( MCAN_TXBCR_ADDR32(u8HwOffset), (uint32)(MCAN_MASK_32BITS_U32)); 
                    
                #if((!defined (ERR_IPV_MCAN_0001 ))&& (defined (ERR_IPV_MCAN_0003)))
                    #if (ERR_IPV_MCAN_0003 == STD_ON)
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /*Can enters into Initializaton mode & access to write protected registers is enabled */
                        REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
                        
                        u32TotalElapsedTime = 0U;
                        #ifndef CAN_TIMEOUT_AS_LOOP
                            (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
                        #endif
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* wait until CCCR.INIT = '1'(Initialization is started) */
                        while ((((REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) & (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) != (MCAN_CCCR_INIT_U32|MCAN_CCCR_CSA_U32)) && (u32TotalElapsedTime < u32CanTimeOutDuration))
                        {
                            #ifndef CAN_TIMEOUT_AS_LOOP
                                (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                                u32TotalElapsedTime += (uint32)ElapsedValue;
                            #else
                                u32TotalElapsedTime++;
                            #endif
                        }
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CSR_U32);
                    #else
                        #error: The define ERR_IPV_MCAN_0003 should not be STD_OFF
                    #endif
                #else
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Set INIT bit to change controller mode to initialization state */
                        REG_BIT_SET32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_INIT_U32);
                #endif

                    /* if interrupt enable then reset interrupt */
                    if (CAN_INTERRUPT_ENABLED == Can_ControllerStatuses[controller].eInterruptMode )
                    {
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Disable all interrupt flags - reset interrupt */
                        REG_WRITE32( MCAN_IE_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Transmission interrupt disabled */
                        REG_WRITE32( MCAN_TXBTIE_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Cancellation finished interrupt disabled */
                        REG_WRITE32( MCAN_TXBCIE_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
                    }

                    u32TotalElapsedTime = 0U;
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
                #endif
                    u32TempVar = (uint32)0U;
                    do 
                    {
                    #ifndef CAN_TIMEOUT_AS_LOOP
                        (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                        u32TotalElapsedTime += (uint32)ElapsedValue;
                    #else
                        u32TotalElapsedTime++;
                    #endif
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        u32TempVar =  REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_INIT_U32;
                    } while ((u32TotalElapsedTime < u32CanTimeOutDuration) && (u32TempVar != MCAN_CCCR_INIT_U32));
                    
                    if(MCAN_CCCR_INIT_U32 == u32TempVar)
                    {
                        Can_ControllerState[controller] = CAN_CS_STOPPED;
                        eReturnValue = (Std_ReturnType)E_OK;
                    }
                }
                else
                {
                    /* Transit Controller state SLEEP to STOPPED*/
                    if (CAN_CS_SLEEP == Can_ControllerState[controller])
                    {
                        /* When Wakeup is not supported the driver should do nothing and return E_OK. */
                        eReturnValue = (Std_ReturnType)E_OK;
                    }
                #if (CAN_DEV_ERROR_DETECT == STD_ON)
                    else
                    {
                        (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_E_TRANSITION);
                    }
                #endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */
                }
            }
            if ((Std_ReturnType)E_OK == eReturnValue)
            {
                Can_ControllerState[controller] = CAN_CS_STOPPED;
                if ((boolean)TRUE == canif_notification_required)
                {
                    CanIf_ControllerModeIndication(controller, CANIF_CS_STOPPED);
                }
            }
            break;

        /* CANIF_CS_STOPPED -> CANIF_CS_STARTED. */
        case (CAN_CS_STARTED):

#if (CAN_DEV_ERROR_DETECT == STD_ON)
                if ( CAN_CS_STOPPED != Can_ControllerState[controller])
                {
                    (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_E_TRANSITION);
                }
                else
                {
#endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */

                #ifdef ERR_IPV_MCAN_0001 
                #if (ERR_IPV_MCAN_0001 == STD_ON)
                    Can_Mcan_Implement_EARATA_8655(u8HwOffset);
                #endif
                #endif 

                    Can_MCan_ChangeBaudrate(controller);
                    /* Clear Tx_complete_guard flags, in this state driver does not allow transmit, but guard for sure. */
                    SchM_Enter_Can_CAN_EXCLUSIVE_AREA_03();
                    Can_ControllerStatuses[controller].Tx_complete_guard = (uint32)0x0UL;
                    SchM_Exit_Can_CAN_EXCLUSIVE_AREA_03();
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Normal Operation */
                    REG_BIT_CLEAR32( MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_INIT_U32);
                    
                    u32TotalElapsedTime = 0U;
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
                #endif
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Wait until INIT bit is cleared, as there is delay in synchronisation between two clock domains */
                    while ((((REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset))) & MCAN_CCCR_INIT_U32) == MCAN_CCCR_INIT_U32) && (u32TotalElapsedTime < u32CanTimeOutDuration))
                    {
                    #ifndef CAN_TIMEOUT_AS_LOOP
                        (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                        u32TotalElapsedTime += (uint32)ElapsedValue;
                    #else
                        u32TotalElapsedTime++;
                    #endif
                    }

                    if(u32TotalElapsedTime < u32CanTimeOutDuration)
                    {             
                        /* Check interrupt enable */
                        if (CAN_INTERRUPT_ENABLED == Can_ControllerStatuses[controller].eInterruptMode )
                        {
                            /* Transmission select by interrupt */
                            if (0U != Can_ControllerStatuses[controller].u32MBInterruptMask)
                            {
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Transmission Completed Interrupt Enable */
                                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_TC_U32);
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Enable transmission interrupts respective with masks*/
                                REG_WRITE32( MCAN_TXBTIE_ADDR32(u8HwOffset), (uint32)(Can_ControllerStatuses[controller].u32MBInterruptMask));
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Enable cancellation finished interrupts respective with masks */
                                REG_WRITE32( MCAN_TXBCIE_ADDR32(u8HwOffset), (uint32)(Can_ControllerStatuses[controller].u32MBInterruptMask));
                            }
                        
                            /* Receive select by interrupt */
                            if(CAN_CONTROLLERCONFIG_RXPOL_EN_U32 != (CAN_CONTROLLERCONFIG_RXPOL_EN_U32 & pCanStaticControlerDescriptor->u32Options))
                            { 
                            #if (CAN_RXFIFO_ENABLE == STD_ON)
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Rx FIFO 1 New Message Interrupt Enable */
                                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1N_U32);
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Rx FIFO 0 New Message Interrupt Enable */
                                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0N_U32);
                            #endif
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Message stored to Dedicated Rx Buffer Interrupt Enable */
                                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_DRX_U32);
                            }
                        #if (CAN_RXFIFO_ENABLE == STD_ON)
                            /* Setup interrupt for Rx Fifo 0 */
                            if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)
                            {
                                pCanControllerRxFifoConfig = pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr;
                                if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOOverflowPolling)
                                {
                                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                    REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0F_U32);
                                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                    REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0L_U32);
                                }
                            #if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
                                if(pCanControllerRxFifoConfig->FIFOWaterMaskLevel > 0U)
                                {
                                    if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOWaterMaskPolling)
                                    {
                                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                        REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0W_U32);
                                    }
                                }
                            #endif
                            }
                            /* Setup interrupt for Rx Fifo 1 */
                            if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr)
                            {
                                pCanControllerRxFifoConfig = pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr;
                                if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOOverflowPolling)
                                {
                                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                    REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1F_U32);
                                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                    REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1L_U32);
                                }
                            #if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
                                if(pCanControllerRxFifoConfig->FIFOWaterMaskLevel > 0U)
                                {
                                    if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOWaterMaskPolling)
                                    {
                                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                        REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1W_U32);
                                    }
                                }
                            #endif
                            }
                        #endif
                            /* BusOff select by interrupt */
                            if ( CAN_CONTROLLERCONFIG_BOPOL_EN_U32 != (CAN_CONTROLLERCONFIG_BOPOL_EN_U32 & pCanStaticControlerDescriptor->u32Options))
                            {
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Bus_Off Status Interrupt Enable */
                                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_BO_U32);
                            }
                          #if (CAN_SUPPORT_MRAF_EVENT == STD_ON)
                            if ( CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32 != (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32) )
                            {
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_MRAF_U32);
                            }
                           #endif
                            /* Error Notification enabled */
                            if ( CAN_CONTROLLERCONFIG_ERR_EN_U32 == (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_ERR_EN_U32) )
                            {
                                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                                /* Stuff Error Interrupt Enable, Format Error Interrupt Enable, Acknowledge Error Interrupt Enable, Bit Error Interrupt Enable */
                                REG_RMW32(MCAN_IE_ADDR32(u8HwOffset), MCAN_ERR_INTERRUPT_U32, MCAN_ERR_INTERRUPT_U32);
                            }
                        }
                        /* Set the Start State. */
                        Can_ControllerState[controller] = CAN_CS_STARTED;
                        eReturnValue = (Std_ReturnType)E_OK;
                    }
#if (CAN_DEV_ERROR_DETECT == STD_ON)
                }
#endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */
            if ((Std_ReturnType)E_OK == eReturnValue)
            {
                CanIf_ControllerModeIndication(controller, CANIF_CS_STARTED);
            }
            break;

        /* CANIF_CS_STOPPED -> CANIF_CS_SLEEP. */
        case (CAN_CS_SLEEP):
        #if (CAN_DEV_ERROR_DETECT == STD_ON)
            /* (SWS_Can_00411) When the function Can_SetControllerMode(CAN_CS_SLEEP) is entered and the CAN controller is
            *    neither in state STOPPED nor in state SLEEP, it shall detect a invalid state transition
            */
            if ( CAN_CS_STARTED == Can_ControllerState[controller] )
            {
                (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_E_TRANSITION);
            }
            else
            {
        #endif
            /* (SWS_Can_00290) If the CAN HW does not support a sleep mode, the function Can_SetControllerMode(CAN_CS_SLEEP) 
            *   shall set the CAN controller to the logical sleep mode.
            */
                eReturnValue = (Std_ReturnType)E_OK;
                Can_ControllerState[controller] = CAN_CS_SLEEP;
                CanIf_ControllerModeIndication(controller, CANIF_CS_SLEEP);
        #if (CAN_DEV_ERROR_DETECT == STD_ON)
            }
        #endif
            break;

        default:
#if (CAN_DEV_ERROR_DETECT == STD_ON)
            /* (SWS_Can_00200) If development error detection for the Can module is enabled:
            *   if an invalid transition has been requested, the function Can_SetControllerMode shall
            *   raise the error CAN_E_TRANSITION and return E_NOT_OK.
            */
            (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_E_TRANSITION);
#endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */
            break;
    }

    return eReturnValue;
}

/*================================================================================================*/
/**
* @brief          Service disables all interrupts for the given CAN controller.
* @details        This routine is called by:
*                 - Can_DisableControllerInterrupts() from Can.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
*
* @pre            Disable interrupts must be called prior to enable interrupts.
* @post           Clear all flags/bits that are needed for disabling the interrupts.
*
*
*/
FUNC (void, CAN_CODE) Can_MCan_DisableControllerInterrupts( VAR(uint8, AUTOMATIC) controller )
{
    /* Hardware Can controller offset. */
    VAR(uint8, AUTOMATIC)   u8HwOffset = 0U;
    /* Allow CAN to enter the specific critical region */
    
    P2CONST(CanStatic_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanStaticControlerDescriptor = NULL_PTR;
    pCanStaticControlerDescriptor = &(CanStatic_pCurrentConfig->StaticControlerDescriptors[controller]);
    
    SchM_Enter_Can_CAN_EXCLUSIVE_AREA_00();
    
    Can_ControllerStatuses[controller].s8IntDisableLevel++;
    
    if ( (sint8)1 == Can_ControllerStatuses[controller].s8IntDisableLevel )
    {
        /* Allow CAN to exit the specific critical region */
        SchM_Exit_Can_CAN_EXCLUSIVE_AREA_00();
        Can_ControllerStatuses[controller].eInterruptMode = CAN_INTERRUPT_DISABLED;
        u8HwOffset = pCanStaticControlerDescriptor->u8ControllerOffset;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Disable all interrupt flags - reset interrupt */
        REG_WRITE32( MCAN_IE_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Transmission interrupt disabled */
        REG_WRITE32( MCAN_TXBTIE_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Cancellation finished interrupt disabled */
        REG_WRITE32( MCAN_TXBCIE_ADDR32(u8HwOffset), (uint32)(MCAN_NOT_MASK_32BITS_U32));
    }
    else
    {
        /* Allow CAN to exit the specific critical region */
        SchM_Exit_Can_CAN_EXCLUSIVE_AREA_00();
    }
}

/*================================================================================================*/
/**
* @brief          Service enables all interrupts that shall be enabled according the current software status.
* @details        This routine is called by:
*                  - Can_EnableControllerInterrupts() from Can.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
*
* @pre            Can be executed only if disable interrupts was called before.
* @post           Enable all interrupts that must be enabled according the current sw status.
*
*
*/
FUNC (void, CAN_CODE) Can_MCan_EnableControllerInterrupts( VAR(uint8, AUTOMATIC) controller,
                                                           P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor
                                                         )
{
    /* Hardware Can controller offset. */
    VAR(uint8, AUTOMATIC)   u8HwOffset = 0U;

    VAR(uint8, AUTOMATIC)   u8DisCalledBefore = 0U;
    
    P2CONST(CanStatic_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanStaticControlerDescriptor = NULL_PTR;
#if (CAN_RXFIFO_ENABLE == STD_ON) 
    /* Local copy of pointer to the Fifo configuration structure */
    P2CONST(Can_ControllerRxFifoConfigType, AUTOMATIC, CAN_APPL_CONST) pCanControllerRxFifoConfig = NULL_PTR;
#endif
    pCanStaticControlerDescriptor = &(CanStatic_pCurrentConfig->StaticControlerDescriptors[controller]);

    if ( Can_ControllerStatuses[controller].s8IntDisableLevel > (sint8)0 )
    {
        /* Allow CAN to enter the specific critical region */
        SchM_Enter_Can_CAN_EXCLUSIVE_AREA_01();

        Can_ControllerStatuses[controller].s8IntDisableLevel--;

        u8DisCalledBefore = (uint8)0x1U;
    }

    if ( ((sint8)0 == Can_ControllerStatuses[controller].s8IntDisableLevel) && ((uint8)0x1U == u8DisCalledBefore) )
    {
        /* Allow CAN to exit the specific critical region */
        SchM_Exit_Can_CAN_EXCLUSIVE_AREA_01();
        /* Check interrupt enable */
        Can_ControllerStatuses[controller].eInterruptMode = CAN_INTERRUPT_ENABLED;
        /* read CAN hardware offset  */
        u8HwOffset = pCanStaticControlerDescriptor->u8ControllerOffset;
        /* Transmission select by interrupt */
        if (0U != Can_ControllerStatuses[controller].u32MBInterruptMask)
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Transmission Completed Interrupt Enable */
            REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_TC_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Enable transmission interrupts respective with masks*/
            REG_WRITE32( MCAN_TXBTIE_ADDR32(u8HwOffset), (uint32)(Can_ControllerStatuses[controller].u32MBInterruptMask));
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Enable cancellation finished interrupts respective with masks */
            REG_WRITE32( MCAN_TXBCIE_ADDR32(u8HwOffset), (uint32)(Can_ControllerStatuses[controller].u32MBInterruptMask));
        }
        /* Receive select by interrupt */
        if(CAN_CONTROLLERCONFIG_RXPOL_EN_U32 != (CAN_CONTROLLERCONFIG_RXPOL_EN_U32 & pCanStaticControlerDescriptor->u32Options))
        {
#if (CAN_RXFIFO_ENABLE == STD_ON)
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Rx FIFO 1 New Message Interrupt Enable */
            REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1N_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Rx FIFO 0 New Message Interrupt Enable */
            REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0N_U32);
#endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Message stored to Dedicated Rx Buffer Interrupt Enable */
            REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_DRX_U32);
        }
#if (CAN_RXFIFO_ENABLE == STD_ON)
        /* Setup interrupt for Rx Fifo 0 */
        if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)
        {
            pCanControllerRxFifoConfig = pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr;
            if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOOverflowPolling)
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0F_U32);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0L_U32);
            }
#if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
            if(pCanControllerRxFifoConfig->FIFOWaterMaskLevel > 0U)
            {
                if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOWaterMaskPolling)
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0W_U32);
                }
            }
#endif
        }
        /* Setup interrupt for Rx Fifo 1 */
        if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr)
        {
            pCanControllerRxFifoConfig = pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr;
            if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOOverflowPolling)
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1F_U32);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1L_U32);
            }
#if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
            if(pCanControllerRxFifoConfig->FIFOWaterMaskLevel > 0U)
            {
                if((boolean)FALSE == pCanControllerRxFifoConfig->FIFOWaterMaskPolling)
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1W_U32);
                }
            }
#endif
        }
#endif
        /* BusOff select by interrupt */
        if ( CAN_CONTROLLERCONFIG_BOPOL_EN_U32 != (CAN_CONTROLLERCONFIG_BOPOL_EN_U32 & pCanStaticControlerDescriptor->u32Options))
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Bus_Off Status Interrupt Enable */
            REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_BO_U32);
        }
        /* Error Notification enabled */
        if ( CAN_CONTROLLERCONFIG_ERR_EN_U32 == (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_ERR_EN_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Stuff Error Interrupt Enable, Format Error Interrupt Enable, Acknowledge Error Interrupt Enable, Bit Error Interrupt Enable */
            REG_RMW32(MCAN_IE_ADDR32(u8HwOffset), MCAN_ERR_INTERRUPT_U32, MCAN_ERR_INTERRUPT_U32);
        }
      #if (CAN_SUPPORT_MRAF_EVENT == STD_ON)
        if ( CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32 != (pCanStaticControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_BIT_SET32( MCAN_IE_ADDR32(u8HwOffset), MCAN_INTERRUPT_MRAF_U32);
        }
      #endif
    }
    else
    {
        if ( Can_ControllerStatuses[controller].s8IntDisableLevel > (sint8)0 )
        {
            /* Allow CAN to exit the specific critical region */
            SchM_Exit_Can_CAN_EXCLUSIVE_AREA_01();
        }
    }
}


/**
* @brief          Process a message buffer abort
* @details        This function write a abort code (b'1001) to MBCS[CODE] field of the MB.
*                This routine is called by:
*                - CanIf or an upper layer according to Autosar requirements.
*
* @param[in]      Hth - HW-transmit handler
*
* @pre            Driver must be initialized and the current MB transmission should be ready for transmit.
*
*
*/

#if (CAN_API_ENABLE_ABORT_MB == STD_ON)
FUNC(void, CAN_CODE) Can_MCan_AbortMb( VAR(Can_HwHandleType, AUTOMATIC) Hth )
{
    VAR(uint8, AUTOMATIC) u8Controller;
    VAR(uint8, AUTOMATIC) u8MbTxIndex = 0U;

    u8Controller = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[Hth].u8ControllerId;

    while((u8MbTxIndex < Can_pCurrentConfig->ControlerDescriptors[u8Controller].u8MaxMbTxCount) && (Can_ControllerStatuses[u8Controller].MbTxMapping[u8MbTxIndex] != Hth))
    {
        u8MbTxIndex++;
    }

#if (CAN_DEV_ERROR_DETECT == STD_ON)
    /* Test if controller is in valid range. */
    if ( (u8Controller >= (uint8)CanStatic_pCurrentConfig->u8ControllersConfigured) || \
         (MCAN_NULL_OFFSET_U8 == (CanStatic_pControlerDescriptors[u8Controller].u8ControllerOffset)) 
       )
    {
        (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_ABORT_MB, (uint8)CAN_E_PARAM_CONTROLLER);
    }
    else
    {
#endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */

    #if(CAN_MULTIPLEXED_TRANSMISSION == STD_ON)
    /* Now we must search the MessageBuffer that has the code specific to a TX Activated MB(sending message in progress), in the range of the Hth.*/
    while( (Can_ControllerStatuses[u8Controller].MbTxMapping[u8MbTxIndex] == Hth) && (u8MbTxIndex < (Can_pControlerDescriptors[u8Controller].u8MaxMbTxCount)) )
    {
        Can_MCan_Cancel( u8Controller, u8MbTxIndex);
        u8MbTxIndex++;
    }
    #else
    if( (u8MbTxIndex < (Can_pControlerDescriptors[u8Controller].u8MaxMbTxCount)) && \
        (Can_ControllerStatuses[u8Controller].MbTxMapping[u8MbTxIndex] == Hth) 
      )
    {
        Can_MCan_Cancel( u8Controller, u8MbTxIndex);
    }
    #endif

#if (CAN_DEV_ERROR_DETECT == STD_ON)
    }
#endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */
}
#endif /* CAN_API_ENABLE_ABORT_MB == STD_ON */

/*================================================================================================*/
/**
* @brief          Can_MCan_Write checks if hardware transmit object that is identified by the HTH is free.
* @details        Can_MCan_Write checks if hardware transmit object that is identified by the HTH is free.
*                     Can_Write checks if another Can_Write is ongoing for the same HTH.
*                     a) hardware transmit object is free:
*                         The mutex for that HTH is set to 'signaled' the ID, DLC and SDU are put in a format appropriate for
*                           the hardware (if necessary) and copied in the appropriate hardware registers/buffers.
*                         All necessary control operations to initiate the transmit are done.
*                         The mutex for that HTH is released. The function returns with E_OK.
*                     b) hardware transmit object is busy with another transmit request.
*                         The function returns with CAN_BUSY.
*                     c) A preemptive call of Can_Write has been issued, that could not be handled reentrant (i.e. a call with the same HTH).
*                         The function returns with CAN_BUSY the function is non blocking
*                     d) The hardware transmit object is busy with another transmit request for an L-PDU that has lower priority than that for the current request
*                         The transmission of the previous L-PDU is cancelled (asynchronously).
*                         The function returns with CAN_BUSY.
*                         This routine is called by:
*                         - Can_Write() from Can.c file.
*                     Algorithm Description:
*                     Case1: TxMUX supported = ON
*                           Can_Write receive the Hth handle and the PduInfo for transmission. It starts to check from the first MBs of the
*                           current controller to search for a free MB. On the first free MB it stops and place the PduInfo and activate the transmission.
*                           In this case function set E_OK for return value and all other functionality is skipped.
*                           If no MB is finded as free then the lowest priority MB is selected for comparing with the priority of the current PduInfo.
*                           If the current PduInfo has a higher priority than the current lower priority (from all MBs) then this lower priority MB is canceled.
*                    Case2: TxMUX supported = OFF
*                          CanWrite() receive the Hth handle and the PduInfo for transmission. It checks if MB with the same index as Hth is free and if yes prepare
*                          and sends the current PduInfo data. If that MB is bussy with another data then it checks the priority between these 2 structures.
*                          Depending by the last evaluation it decides what MB data to cancel.
*
* @param[in]      Hth information which HW-transmit handle shall be used for transmit.
*                 Implicitly this is also the information about the controller to use
*                 because the Hth numbers are unique inside one hardware unit.
* @param[in]      PduInfo Pointer to SDU user memory, DLC and Identifier
*
* @return          Std_ReturnType
* @retval          E_OK write command has been accepted
* @retval          E_NOT_OK development error occured
* @retval          CAN_BUSY no TX hardware buffer available or preemtive call of Can_Write() that can't be implemented reentrant
*
* @pre            The MB must be configured for Tx.
* @post           Transmit the data or ignore it in case of MB is full with another task.
*
*
*/

FUNC (Std_ReturnType, CAN_CODE) Can_MCan_Write( Can_HwHandleType Hth, P2CONST(Can_PduType, AUTOMATIC, CAN_APPL_CONST) PduInfo )
{
    /* Local copy of pointer to the controller descriptor. */
    P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor = NULL_PTR;
    /* Local copy of pointer to the section address offset descriptor. */
    P2CONST(Can_ControllerSectionOffsetType, AUTOMATIC, CAN_APPL_CONST) pCanControllerSectionOffset = NULL_PTR;
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)CAN_BUSY; /* Variable store return status. */
    VAR(uint8, AUTOMATIC)          u8MbIndex = 0U;  /* Index CAN Message Buffers from configuration. */
    VAR(uint32, AUTOMATIC)          u32TxBufferAddOffset = 0U;
    VAR(uint8, AUTOMATIC)          u8HwOffset = 0U;  /* Hardware Can controller offset. */
    VAR(uint32, AUTOMATIC)         u32TempFlag = 0U;
    VAR(uint32, AUTOMATIC)         u32MbMessageId = 0U;
    VAR(uint8, AUTOMATIC)          u8MbDataByte = 0U;
    VAR(uint8, AUTOMATIC)          u8ByteIndex = 0U;
    VAR(uint32, AUTOMATIC)         u32BaseAddress = 0U;
    VAR(uint8, AUTOMATIC)          u8CtrlId = 0U;
    VAR(uint8, AUTOMATIC)          u8NumberWord = 0U;
    VAR(uint8, AUTOMATIC)          u8IndexWord = 0U;    
    VAR(uint32, AUTOMATIC)         u32DataWord = 0U;
    /*Variable stores value of data lenght code*/
    VAR(uint32, AUTOMATIC)         u32DataLengthCode = 0U;
#if (CAN_FD_MODE_ENABLE == STD_ON)
    #ifdef IPV_MCAN
        #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
            VAR(uint16, AUTOMATIC)         u16BaudrateIndex  = 0U;
        #endif
    #endif   
    VAR(uint8, AUTOMATIC)          u8PaddingValue;
    VAR(uint32, AUTOMATIC) u32TotalElapsedTime = 0U;
    #ifndef CAN_TIMEOUT_AS_LOOP
        static VAR(TickType, AUTOMATIC) CurrentValue = 0U;
        static VAR(TickType, AUTOMATIC) ElapsedValue = 0U;
    #endif
#endif
    u8CtrlId = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[Hth].u8ControllerId;
    u8HwOffset = CanStatic_pControlerDescriptors[u8CtrlId].u8ControllerOffset;
    pCanControlerDescriptor = &(Can_pCurrentConfig->ControlerDescriptors[u8CtrlId]);

#if (CAN_FD_MODE_ENABLE == STD_ON)
    #ifdef IPV_MCAN
        #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
            u16BaudrateIndex = u16Can_CtrlBaudrateID[u8CtrlId];
        #endif
    #endif
#endif
    pCanControllerSectionOffset = pCanControlerDescriptor->pControllerSectionOffsetPtr;
    /* Get the shared RAM offset address of Tx Buffer of this controller */
    u32TxBufferAddOffset = pCanControllerSectionOffset->TxBufferOffset;

/* Check the current mode: correct */
#if (CAN_FD_MODE_ENABLE == STD_ON)
    u32MbMessageId = (uint32)PduInfo->id;
    /* Check type of frame */
    if( ((uint32)CAN_FD_ID_DESCRIPTOR) == (((uint32)u32MbMessageId) & ((uint32)CAN_FD_ID_DESCRIPTOR)) )
    {
    #ifdef IPV_MCAN
    #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if(((uint32)MCAN_CCCR_FDO_CONFIGURATION) == (REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & ((uint32)MCAN_CCCR_FDO_CONFIGURATION)))
    #endif
    #if(IPV_MCAN == IPV_MCAN_00_00_00_21)
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if(MCAN_CCCR_FDOE_U32 == (REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_FDOE_U32))
    #endif
    #endif
        {
            eReturnValue = (Std_ReturnType)E_OK;
        }
        else
        {
            /* Wait all transmition finished in order to change mode for transmition */
            u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            while ((0U != REG_READ32( MCAN_TXBRP_ADDR32(u8HwOffset))) && (u32TotalElapsedTime < u32CanTimeOutDuration))
            {
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                    u32TotalElapsedTime += (uint32)ElapsedValue;
                #else
                    u32TotalElapsedTime++;
                #endif
            }
            if (u32TotalElapsedTime >= u32CanTimeOutDuration)
            {
                /* Have pedding in the CAN bus */
                eReturnValue = (Std_ReturnType)CAN_BUSY;
            }
            else
            {
            #ifdef IPV_MCAN
            #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
                if (MCAN_CCCR_CME_BRS_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u16BaudrateIndex].ControllerFD.u32CanControllerTxBitRateSwitch))
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Write in the CMR field */
                    REG_BIT_SET32(MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CMR_BRS_U32);
                }
                else
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Write in the CMR field */
                    REG_BIT_SET32(MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CMR_NOT_BRS_U32);
                }
            #endif
            #endif
                eReturnValue = (Std_ReturnType)E_OK;
            }
        }
    }
    else /* Not FD frame */
    {
    #ifdef IPV_MCAN
    #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if((uint32)0U == (REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & ((uint32)MCAN_CCCR_FDO_CONFIGURATION)))
    #endif
    #if(IPV_MCAN == IPV_MCAN_00_00_00_21)
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if((uint32)0U == (REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_FDOE_U32))
    #endif
    #endif
        {
            eReturnValue = (Std_ReturnType)E_OK;
        }
        else
        {
            /* Wait all transmition finished in order to change mode for transmition */
            u32TotalElapsedTime = 0U;
            #ifndef CAN_TIMEOUT_AS_LOOP
                (void)GetCounterValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue);
            #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            while ((0U != REG_READ32( MCAN_TXBRP_ADDR32(u8HwOffset))) && (u32TotalElapsedTime < u32CanTimeOutDuration))
            {
                #ifndef CAN_TIMEOUT_AS_LOOP
                    (void)GetElapsedValue((CounterType)CAN_TIMEOUT_COUNTER_NAME, &CurrentValue, &ElapsedValue);
                    u32TotalElapsedTime += (uint32)ElapsedValue;
                #else
                    u32TotalElapsedTime++;
                #endif
            }
            if (u32TotalElapsedTime >= u32CanTimeOutDuration)
            {
                /* Have pedding in the CAN bus */
                eReturnValue = (Std_ReturnType)CAN_BUSY;
            }
            else
            {
                /* Write in the CMR field */
            #ifdef IPV_MCAN
            #if ((IPV_MCAN == IPV_MCAN_00_01_00_03) || (IPV_MCAN == IPV_MCAN_01_00_01_61))
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_RMW32(MCAN_CCCR_ADDR32(u8HwOffset), MCAN_CCCR_CMR_FSTD_U32, MCAN_CCCR_CMR_FSTD_U32);
            #endif
            #endif
                eReturnValue = (Std_ReturnType)E_OK;
            }
        }
    }
#endif

#if (CAN_FD_MODE_ENABLE == STD_ON)
    if ((Std_ReturnType)E_OK == eReturnValue)
    {
#endif
        for (u8MbIndex = 0U; u8MbIndex < Can_pControlerDescriptors[u8CtrlId].u8MaxMbTxCount; u8MbIndex++)
        {
            if (Hth == Can_ControllerStatuses[u8CtrlId].MbTxMapping[u8MbIndex])
            {
                eReturnValue = (Std_ReturnType)E_OK;
                break;
            }
            else
            {
                eReturnValue = (Std_ReturnType)E_NOT_OK;
            }
        }
        if ((Std_ReturnType)E_NOT_OK != eReturnValue)
        {
        #if (CAN_MULTIPLEXED_TRANSMISSION == STD_ON)
            do
            {
        #endif /* (CAN_MULTIPLEXED_TRANSMISSION == STD_ON) */
                /* Calculate the real MBsize and DataLenghtCode for each MB */
                u32DataLengthCode = Can_Mcan_CalcDataLenghtCode(PduInfo->length);
                /* Calculate the base address for MB */
                u32BaseAddress = SCM_RAM_BASEADDR + (u32TxBufferAddOffset << 2) + ((uint32)(u8MbIndex) * (uint32)u8MbSize[u8CtrlId]);              
                u32TempFlag = (uint32)1U << u8MbIndex;
                /* Allow CAN to enter the specific critical region */
                SchM_Enter_Can_CAN_EXCLUSIVE_AREA_02();
        
                if ( (uint32)0U == (Can_ControllerStatuses[u8CtrlId].Tx_complete_guard & u32TempFlag) )
                {
                    /* No need to set the flag right now because there is mutex to prevent call with same HTH. 
                    Tx_complete_guard will be set after trigger transmit to synchronize with ProcessTx or Cancel */
                    /* Allow CAN to exit the specific critical region */
                    SchM_Exit_Can_CAN_EXCLUSIVE_AREA_02();
                    u32MbMessageId = PduInfo->id;
                    
                    /* Set-up the MB content for Tx. Remember the PduId for reporting when the frame is transmitted. */                    
                    /* @violates @ref Can_Mcan_c_REF_8 MISRA 2012 Required Rule 18.1 */
                    Can_ControllerStatuses[u8CtrlId].u32TxPduId[u8MbIndex] = PduInfo->swPduHandle;
                    
                #if (CAN_EXTENDEDID == STD_ON)
                    if ( MCAN_MBC_ID_IDE_U32 == (u32MbMessageId & MCAN_MBC_ID_IDE_U32))
                    {
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Extended ID - need to shift left 18 bits. */
                        REG_WRITE32( u32BaseAddress , (((u32MbMessageId & MCAN_TX_MB_ID_MASK_U32)| MCAN_MB_TYPE_XTD_U32)) );
                    }
                    else
                    {
                #endif /*(CAN_EXTENDEDID == STD_ON) */
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Standard ID - need to shift left 18 bits. */
                        REG_WRITE32( u32BaseAddress , ((u32MbMessageId << MCAN_STANDARD_ID_SHIFT_U8) & MCAN_MB_TYPE_STD_U32));
                #if (CAN_EXTENDEDID == STD_ON)
                    }
                #endif /*(CAN_EXTENDEDID == STD_ON) */
                
                #if (CAN_FD_MODE_ENABLE == STD_ON)
                    #ifdef IPV_MCAN
                    #if (IPV_MCAN == IPV_MCAN_00_00_00_21)
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        if (MCAN_CCCR_FDOE_U32 == (REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_FDOE_U32))
                        {
                            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                            if (MCAN_CCCR_BRSE_U32 == (REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_BRSE_U32))
                            {
                                u32DataLengthCode |= MCAN_TX_MB_BRS_MASK_U32;
                            }
                            u32DataLengthCode |= MCAN_TX_MB_FDF_MASK_U32;
                        }
                    #endif
                    #endif
                    /* Copy the padding data into the variable */
                    u8PaddingValue = ((uint8)(Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[Hth].u8FdPaddingValue));
                #endif
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32((u32BaseAddress + 4U ), u32DataLengthCode);
                    /* Calculate the number the word which uses to store the data of frame */
                    u8NumberWord = (u8MbSize[u8CtrlId] - 8U) >> 2U;
                    /* Increase the u32BaseAddress to the beginning of data section */
                    u32BaseAddress += 8U;
                    /* Access to each word anh each byte to arrange again the order layout of data */  
                    for(u8IndexWord = 0U; u8IndexWord < u8NumberWord; u8IndexWord ++)
                    {
                        u32DataWord = 0U;
                        for(u8MbDataByte = (uint8)0U; u8MbDataByte < 4U; u8MbDataByte++)
                        {
                            u8ByteIndex = u8MbDataByte + (u8IndexWord << 2U);
                        #if (CAN_FD_MODE_ENABLE == STD_ON)
                            if(u8ByteIndex >= PduInfo->length)
                            {
                                u32DataWord |= (uint32)u8PaddingValue << (u8MbDataByte << 3U);
                            }
                            else
                            {
                        #endif
                                u32DataWord |= (uint32)PduInfo->sdu[u8ByteIndex] << (u8MbDataByte << 3U);
                        #if (CAN_FD_MODE_ENABLE == STD_ON)
                            }
                        #endif
                        }
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        /* Write the data to data field of buffer */
                        REG_AWRITE32(u32BaseAddress, u8IndexWord, u32DataWord);
                    }
                    SchM_Enter_Can_CAN_EXCLUSIVE_AREA_02();
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    /* Trigger transmission by set correspond bit in TXBAR */
                    REG_WRITE32( MCAN_TXBAR_ADDR32(u8HwOffset), (uint32)((uint32)(1U) << (u8MbIndex)));
                    /* Set Tx_complete_guard bit */
                    Can_ControllerStatuses[u8CtrlId].Tx_complete_guard |= u32TempFlag;
                    SchM_Exit_Can_CAN_EXCLUSIVE_AREA_02();
                    eReturnValue = (Std_ReturnType)E_OK;
                }
                else /* else of "if ( (uint32)0x0U == (Can_ControllerStatuses[u8CtrlId].Tx_complete_guard & u32TempFlag) )" */
                {
                    /* Allow CAN to exit the specific critical region */
                    SchM_Exit_Can_CAN_EXCLUSIVE_AREA_02();
                    /* MB is not empty. */
                    eReturnValue = (Std_ReturnType)CAN_BUSY;
                }
                
        #if (CAN_MULTIPLEXED_TRANSMISSION == STD_ON)
                /* Increment the MB index. */
                u8MbIndex++;
                /* @violates @ref Can_Mcan_c_REF_8 MISRA 2012 Required Rule 18.1 */
            } while (((Std_ReturnType)CAN_BUSY == eReturnValue) && (u8MbIndex < Can_pControlerDescriptors[u8CtrlId].u8MaxMbTxCount) && (Can_ControllerStatuses[u8CtrlId].MbTxMapping[u8MbIndex] == Hth));
        #endif /* (CAN_MULTIPLEXED_TRANSMISSION == STD_ON) */
        }
#if (CAN_FD_MODE_ENABLE == STD_ON)
    }
#endif
    return eReturnValue;
}

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer during Can_MainFunction_Write if polling is selected or from ISR when Interrupt mode selected.
* @details        Processes Tx interrupt flags.
*               This routine is called by:
*                - Can_MCan_MainFunctionWrite() from Can_Mcan.c file.
*                - Can_MCan_MainFunctionMultipleWritePoll() from Can_Mcan.c file.
*                - Can_MCan_Isr_common_process_interrupt() from Can_Mcan.c file.
*                - Can_IsrFC##FC##_UNI() / Can_IsrFC##FC##_##Name() from Can_Irq.c file.
*
* @param[in]      controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      mbindex_start first MB to process.
* @param[in]      mbindex_end last MB to process.
*
* @pre            MB is configured for Tx.
* @post           CanIf is informed with cancellation or transmit success.
*
*
*/

static FUNC (void, CAN_CODE) Can_MCan_ProcessTx( VAR(uint8, AUTOMATIC) controller, VAR(uint8, AUTOMATIC) mbindex_start, VAR(uint8, AUTOMATIC) mbindex_end)
{
    VAR(uint8, AUTOMATIC)           u8MbIndex = 0U;
    /* Hardware Can controller offset. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    VAR(uint32, AUTOMATIC)          u32TempFlag = 0U;
    VAR(PduIdType, AUTOMATIC) u32PduId;

    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    for ( u8MbIndex = mbindex_start; u8MbIndex <= mbindex_end; u8MbIndex++)
    {
        u32TempFlag = (uint32)1U << u8MbIndex;
        u32PduId = Can_ControllerStatuses[controller].u32TxPduId[u8MbIndex];
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if ((REG_READ32( MCAN_TXBTO_ADDR32(u8HwOffset)) & u32TempFlag) == u32TempFlag)
        {
            SchM_Enter_Can_CAN_EXCLUSIVE_AREA_05();
            if((Can_ControllerStatuses[controller].Tx_complete_guard & u32TempFlag) != 0U )
            {
                Can_ControllerStatuses[controller].Tx_complete_guard &= (uint32)(~u32TempFlag);
                SchM_Exit_Can_CAN_EXCLUSIVE_AREA_05();
                CanIf_TxConfirmation(u32PduId);
            }
            else
            {
                SchM_Exit_Can_CAN_EXCLUSIVE_AREA_05();
            }
        }
    }
}

/*================================================================================================*/
/**
* @brief          Service to perform the polling of TX confirmation and TX cancellation confirmation
* @details        This routine is called by:
*               - Can_MainFunction_Write() from Can.c file.
*
* @pre            The controller must be configured for transmit in polling mode and at least one MB is configured for Tx.
* @post           Process the transmission data in case of availability.
*
*
*/
#if (CAN_TXPOLL_SUPPORTED == STD_ON)

FUNC (void, CAN_CODE) Can_MCan_MainFunctionWrite(void)
{
    /* Controller ID */
    VAR(uint8, AUTOMATIC) u8CtrlId = 0U;
    /* Hardware Object ID */
    VAR(Can_HwHandleType, AUTOMATIC) HwObjectIdx = 0U;
    /* Index of hw buffer for each Object ID */
    VAR(uint8, AUTOMATIC) u8HwBufferIdx = 0U;
    /* Keep the index of Tx buffer for each controller */
    VAR(uint16, AUTOMATIC) u16TxProcessIndex[CAN_MAXCTRL_SUPPORTED] = {0U};
    for (u8CtrlId = 0U; u8CtrlId < CAN_MAXCTRL_SUPPORTED; u8CtrlId++)
    {
        u16TxProcessIndex[u8CtrlId] = 0U;
    }
    for (HwObjectIdx = 0U; HwObjectIdx < Can_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; HwObjectIdx++)
    {
        u8CtrlId = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u8ControllerId;
        if ((MCAN_NULL_OFFSET_U8 != CanStatic_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
            (CAN_TRANSMIT == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].eMBType )
           )
        {
            if ((boolean)TRUE == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].CanHwObjectUsesPolling)
            {
                for (u8HwBufferIdx = 0U; u8HwBufferIdx < Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u16HwObjectCount; u8HwBufferIdx++)
                {
                    Can_MCan_ProcessTx( u8CtrlId, (uint8)(u16TxProcessIndex[u8CtrlId] + u8HwBufferIdx), (uint8)(u16TxProcessIndex[u8CtrlId] + u8HwBufferIdx));
                }
            }
            u16TxProcessIndex[u8CtrlId] += Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u16HwObjectCount;
        }
    }
}

/*================================================================================================*/
/**
* @brief          Function called at fixed cyclic time, with polling of all the MessageBuffer referenced to writepoll
* @details        Service for performs the polling of TX confirmation and TX cancellation confirmation when CAN_TX_PROCESSING is set to POLLING.
*                 This routine is called by:
*                 - CanIf or an upper layer according to Autosar requirements.
*
* @api
*
* @pre            Driver must be initialized.
* @post           Send the data from that MB that is configured for Tx.
*/
/* @violates @ref Can_Mcan_c_REF_7 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_MCan_MainFunctionMultipleWritePoll( VAR(uint8, AUTOMATIC) writepoll)
{
    /* Id CAN controllers from configuration. */
    VAR(uint8, AUTOMATIC)  u8CtrlId = 0U;
    /* Index hw bufer */
    VAR(uint8, AUTOMATIC)  u8HwBufferIdx = 0U;
    /* Index of Hw Object configured */
    VAR(Can_HwHandleType, AUTOMATIC)  HwObjectIdx = 0U;
    /* Keep the index of Tx buffer for each controller */
    VAR(uint16, AUTOMATIC)  u16TxProcessIndex[CAN_MAXCTRL_SUPPORTED] = {0U};
    
    if ( NULL_PTR != Can_pCurrentConfig )
    {
        for (u8CtrlId = 0U; u8CtrlId < CAN_MAXCTRL_SUPPORTED; u8CtrlId++)
        {
            u16TxProcessIndex[u8CtrlId] = 0U;
        }
    #if (CAN_DEV_ERROR_DETECT == STD_ON)
        if ( CAN_UNINIT == Can_eDriverStatus )
        {
            (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_MAIN_FUNCTION_WRITE, (uint8)CAN_E_UNINIT);
        }
        else
        {
    #endif /* (CAN_DEV_ERROR_DETECT == STD_ON) */
            
            for (HwObjectIdx = 0U; HwObjectIdx < Can_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; HwObjectIdx++)
            {
                u8CtrlId = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u8ControllerId;
                if ((MCAN_NULL_OFFSET_U8 != CanStatic_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
                    (CAN_TRANSMIT == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].eMBType )
                   )
                {
                    if ((writepoll == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u32CanMainFuncRWPeriodRef) && \
                        ((boolean)TRUE == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].CanHwObjectUsesPolling)
                        )
                    {
                        for (u8HwBufferIdx = 0U; u8HwBufferIdx < Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u16HwObjectCount; u8HwBufferIdx++)
                        {
                            Can_MCan_ProcessTx( u8CtrlId, (uint8)(u16TxProcessIndex[u8CtrlId] + u8HwBufferIdx), (uint8)(u16TxProcessIndex[u8CtrlId] + u8HwBufferIdx));
                        }
                    }
                    u16TxProcessIndex[u8CtrlId] += Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[HwObjectIdx].u16HwObjectCount;
                }
            }
    #if (CAN_DEV_ERROR_DETECT == STD_ON)
        }
    #endif
    }
}
#endif /* (CAN_TXPOLL_SUPPORTED == STD_ON) */

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer during Can_MainFunction_Read if polling is selected or from ISR when Interrupt mode selected.
* @details        Processes Rx interrupt flags.
                  This routine is called by:
                    - Can_MCan_MainFunctionRead() from Can_Mcan.c file
                    - Can_MCan_MainFunctionMultipleReadPoll() from Can_Mcan.c file.
                    - Can_MCan_Isr_common_process_interrupt() from Can_Mcan.c file.
                    - Can_IsrFC##MC##_##ILS() from Can_Irq.c file
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      mbindex_start first MB to process
* @param[in]      mbindex_end last MB to process
*
* @pre            MB is configured for Rx.
* @post           Inform CanIf in case a data frame was received.
*
*
*/

static FUNC (void, CAN_CODE) Can_MCan_ProcessRx( VAR(uint8, AUTOMATIC) controller, VAR(uint8, AUTOMATIC) u8BufferID)
{
    VAR(uint8, AUTOMATIC)       u8MbDataLength = 0U;
    #if (CAN_FD_MODE_ENABLE == STD_ON)
        static VAR(uint8, AUTOMATIC)   u8CanMbData[64]={0U};
    #else
        static VAR(uint8, AUTOMATIC)   u8CanMbData[8]={0U};
    #endif
    /* Identifies the HRH and its corresponding CAN Controller */
    static VAR(Can_HwType, AUTOMATIC) Mailbox;
    /* Pointer to the received L-PDU */
    static VAR(PduInfoType, AUTOMATIC) PduInfoPtr;
    
    VAR(uint8, AUTOMATIC)       u8DatabyteIndex = 0U;  
    VAR(uint32, AUTOMATIC)      u32BaseAddress = 0U;
    
    VAR(Can_HwHandleType, AUTOMATIC)      u32MbHrh = 0U;
    VAR(Can_IdType, AUTOMATIC) u32MbMessageId = 0U;
    VAR(uint8, AUTOMATIC)      u8HwOffset = 0U;
#if (CAN_RXFIFO_ENABLE == STD_ON)     
    VAR(uint8, AUTOMATIC)      u8FifoIndex = 0U;
    VAR(uint32, AUTOMATIC)     u32RxFifo0AddOffset = 0U;
    VAR(uint32, AUTOMATIC)     u32RxFifo1AddOffset = 0U;
#endif
    VAR(uint8, AUTOMATIC)      u8MbCtrlIndex = 0U;
    VAR(uint32, AUTOMATIC)     u32FlagRxBuffer = 0U; /* value 0 is don't has new message in Rx buffer */
    /* Pointer to the MB container structure. */
    P2CONST(Can_MBConfigContainerType, AUTOMATIC, CAN_APPL_CONST)   pCanMbConfigContainer = NULL_PTR;
    P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor = NULL_PTR;
    /* Local copy of pointer to the section address offset descriptor. */
    P2CONST(Can_ControllerSectionOffsetType, AUTOMATIC, CAN_APPL_CONST) pCanControllerSectionOffset = NULL_PTR;
    VAR(uint32, AUTOMATIC)     u32RxBufferAddOffset = 0U;
    VAR(uint8, AUTOMATIC)      u8TempVar = 0U;
    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    pCanControlerDescriptor = &Can_pCurrentConfig->ControlerDescriptors[controller];
    pCanControllerSectionOffset = pCanControlerDescriptor->pControllerSectionOffsetPtr;
    pCanMbConfigContainer   = &(Can_pCurrentConfig->MBConfigContainer);
#if (CAN_RXFIFO_ENABLE == STD_ON) 
    MCAL_FAULT_INJECTION_POINT(CAN_FIP_3_CHANGE_LENGTH_FIELD);
    if ((uint8)MCAN_STORE_RX_FIFO0_U8 == u8BufferID)
    {
        u32RxFifo0AddOffset = pCanControllerSectionOffset->RxFifo0Offset;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if(MCAN_RXFIFO0_OVFL_MASK_U32 == ((REG_READ32( MCAN_IR_ADDR32(u8HwOffset)))&( MCAN_INTERRUPT_RF0F_U32|MCAN_INTERRUPT_RF0L_U32)))
        {
            if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)
            {
                if ( NULL_PTR != (pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)->Can_RxFifoOverflowNotification)
                {
                    (pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)->Can_RxFifoOverflowNotification();
                }
            }
        #if (CAN_DEV_ERROR_DETECT == STD_ON)
            
            (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_MAIN_FUNCTION_READ, (uint8)CAN_E_DATALOST);
        #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0F_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0L_U32);
        }
        
    #if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if ( MCAN_INTERRUPT_RF0W_U32 == ((REG_READ32(MCAN_IR_ADDR32(u8HwOffset)))& MCAN_INTERRUPT_RF0W_U32) )
        {
            if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)
            {
                if ( NULL_PTR != (pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)->Can_RxFifoWarningNotification)
                {
                    (pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)->Can_RxFifoWarningNotification();
                }
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0W_U32) ;
        }
    #endif
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if ( MCAN_INTERRUPT_RF0N_U32 == ((REG_READ32( MCAN_IR_ADDR32(u8HwOffset))) & MCAN_INTERRUPT_RF0N_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0N_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            while ( ((REG_READ32( MCAN_RXF0S_ADDR32(u8HwOffset))) & MCAN_RXF0S_F0FL_U32)> 0U)
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u8FifoIndex = (uint8)(((REG_READ32( MCAN_RXF0S_ADDR32(u8HwOffset))) & MCAN_RXF0S_F0GI_U32) >> MCAN_RXF0S_F0GI_SHIFT_U8 );
                /* Calculate the base address for MB */
                u32BaseAddress = SCM_RAM_BASEADDR + (u32RxFifo0AddOffset << 2U) +((uint32)(u8FifoIndex) * u8MbSize[controller]);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u8MbDataLength = (uint8)(( REG_BIT_GET32( ( u32BaseAddress + 4U), MCAN_RX_MB_DLC_MASK_U32)) >> MCAN_RX_MB_DLC_SHIFT_U8);
                /* decode the length of the data buffer */
                u8MbDataLength = Can_Mcan_DecodeLenghtData(u8MbDataLength);
                /*Prevents that a buffer overflow to be generated by a CAN bus error affecting length field*/
            #if (CAN_FD_MODE_ENABLE == STD_ON)
                if (u8MbDataLength > CAN_REAL_PAYLOAD_U8)
                {
                    u8MbDataLength = CAN_REAL_PAYLOAD_U8;
                }
            #else
                if (u8MbDataLength > (uint8)8U)
                {
                    u8MbDataLength = (uint8)8U;
                }
            #endif
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                if ((uint32)MCAN_RX_MB_XTD_MASK_U32 == ((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_XTD_MASK_U32 ))) & (uint32)MCAN_RX_MB_XTD_MASK_U32))
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    u32MbMessageId = (Can_IdType)((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_ID_MASK_U32) )) | MCAN_MBC_ID_IDE_U32);
                }
                else
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    u32MbMessageId = (Can_IdType)(((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_ID_MASK_U32) )) & MCAN_MB_TYPE_STD_U32) >> MCAN_STANDARD_ID_SHIFT_U8);
                }
            #if (CAN_FD_MODE_ENABLE == STD_ON)
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                /* Check the frame, if frame is a FD frame */
                if (MCAN_EDL_MASK_U32 == (REG_BIT_GET32( u32BaseAddress + 4U , MCAN_EDL_MASK_U32)))
                {
                    u32MbMessageId |= CAN_FD_ID_DESCRIPTOR;
                }
                
            #endif
                /* Read data to aray */
                for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
                {
                    u8TempVar = (uint8)((u8DatabyteIndex & (uint8)0xFCU) + 3U) - (uint8)(u8DatabyteIndex & 3U);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    u8CanMbData[u8DatabyteIndex] =  ( REG_READ8( u32BaseAddress +8U + (uint32)u8TempVar));
                }
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_RXF0A_ADDR32(u8HwOffset), (uint32)(u8FifoIndex & MCAN_RXF0A_F0AI_U32));
                for (u8MbCtrlIndex = 0U; u8MbCtrlIndex < pCanMbConfigContainer->uMessageBufferConfigCount; u8MbCtrlIndex++)
                {
                    if (((uint8)MCAN_STORE_RX_FIFO0_U8 == pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u8StoredRxMb) && \
                        (controller == pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u8ControllerId))
                    {
                        u32MbHrh = (Can_HwHandleType)pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u32HWObjID;
                        #if (CAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                        if ((boolean)TRUE == Can_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
                        {
                        #endif
                            Mailbox.CanId = u32MbMessageId;
                            Mailbox.Hoh = u32MbHrh;
                            Mailbox.ControllerId = controller;
                            PduInfoPtr.SduDataPtr = u8CanMbData;
                            PduInfoPtr.SduLength = u8MbDataLength;
                            CanIf_RxIndication( &Mailbox, &PduInfoPtr);
                        #if (CAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                        }
                        #endif
                        break;
                    }
                }
            }
        }
    }
    else if((uint8)MCAN_STORE_RX_FIFO1_U8 == u8BufferID)
    {        
        u32RxFifo1AddOffset = pCanControllerSectionOffset->RxFifo1Offset;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if (MCAN_RXFIFO1_OVFL_MASK_U32 == ((REG_READ32( MCAN_IR_ADDR32(u8HwOffset)))&( MCAN_INTERRUPT_RF1F_U32|MCAN_INTERRUPT_RF1L_U32)))
        {
            if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)
            {
                if ( NULL_PTR != (pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)->Can_RxFifoOverflowNotification)
                {
                    (pCanControlerDescriptor->pControllerRxFifo0ConfigsPtr)->Can_RxFifoOverflowNotification();
                }
            }
        #if (CAN_DEV_ERROR_DETECT == STD_ON)
            
            (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_MAIN_FUNCTION_READ, (uint8)CAN_E_DATALOST);
        #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1F_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1L_U32);
        }
    
    #if (CAN_FIFO_WARNING_NOTIFICATION == STD_ON)
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if ( MCAN_INTERRUPT_RF1W_U32 == ((REG_READ32( MCAN_IR_ADDR32(u8HwOffset)))& MCAN_INTERRUPT_RF1W_U32) )
        {
            if(NULL_PTR != pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr)
            {
                if ( NULL_PTR != (pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr)->Can_RxFifoWarningNotification)
                {
                    (pCanControlerDescriptor->pControllerRxFifo1ConfigsPtr)->Can_RxFifoWarningNotification();
                }
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1W_U32);
        }
    #endif
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        if ( MCAN_INTERRUPT_RF1N_U32 == ((REG_READ32( MCAN_IR_ADDR32(u8HwOffset))) & MCAN_INTERRUPT_RF1N_U32) )
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1N_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            while ( ((REG_READ32( MCAN_RXF1S_ADDR32(u8HwOffset))) & MCAN_RXF1S_F1FL_U32)> 0U)
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u8FifoIndex = (uint8)(((REG_READ32( MCAN_RXF1S_ADDR32(u8HwOffset))) & MCAN_RXF1S_F1GI_U32) >> MCAN_RXF1S_F1GI_SHIFT_U8 );
                /* Calculate the base address for MB */
                u32BaseAddress = SCM_RAM_BASEADDR + (u32RxFifo1AddOffset << 2) +((uint32)(u8FifoIndex) * u8MbSize[controller]);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u8MbDataLength = (uint8)(( REG_BIT_GET32( ( u32BaseAddress + 4U), MCAN_RX_MB_DLC_MASK_U32)) >> MCAN_RX_MB_DLC_SHIFT_U8);
                /* decode the length of the data buffer */
                u8MbDataLength = Can_Mcan_DecodeLenghtData(u8MbDataLength);
                /*Prevents that a buffer overflow to be generated by a CAN bus error affecting length field*/
            #if (CAN_FD_MODE_ENABLE == STD_ON)
                if (u8MbDataLength > CAN_REAL_PAYLOAD_U8)
                {
                    u8MbDataLength = CAN_REAL_PAYLOAD_U8;
                }
            #else
                if (u8MbDataLength > (uint8)8U)
                {
                    u8MbDataLength = (uint8)8U;
                }
            #endif
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                if ((uint32)MCAN_RX_MB_XTD_MASK_U32 == ((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_XTD_MASK_U32 ))) & (uint32)MCAN_RX_MB_XTD_MASK_U32))
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    u32MbMessageId = (Can_IdType)((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_ID_MASK_U32 ) )) | MCAN_MBC_ID_IDE_U32);
                }
                else
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    u32MbMessageId = (Can_IdType)(((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_ID_MASK_U32 ) )) & MCAN_MB_TYPE_STD_U32) >> MCAN_STANDARD_ID_SHIFT_U8);
                }
                
            #if (CAN_FD_MODE_ENABLE == STD_ON)
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                /* Check the frame, if frame is a FD frame */
                if (MCAN_EDL_MASK_U32 == (REG_BIT_GET32( u32BaseAddress + 4U , MCAN_EDL_MASK_U32)))
                {
                    u32MbMessageId |= CAN_FD_ID_DESCRIPTOR;
                }
            #endif
                
                /* Read data to the aray */
                for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
                {
                    u8TempVar = (uint8)((u8DatabyteIndex & (uint8)0xFCU) + 3U) - (uint8)(u8DatabyteIndex & 3U);
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    u8CanMbData[u8DatabyteIndex] = ( REG_READ8( u32BaseAddress + 8U + (uint32)u8TempVar));
                }
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_RXF1A_ADDR32(u8HwOffset), (uint32)(u8FifoIndex & MCAN_RXF1A_F1AI_U32));
                for (u8MbCtrlIndex = 0U; u8MbCtrlIndex < pCanMbConfigContainer->uMessageBufferConfigCount; u8MbCtrlIndex++)
                {
                    if (((uint8)MCAN_STORE_RX_FIFO1_U8 == pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u8StoredRxMb) && \
                        (controller == pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u8ControllerId) \
                       )
                    {
                        u32MbHrh = (Can_HwHandleType)pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u32HWObjID;
                        #if (CAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                        /*[CAN444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */
                        if ((boolean)TRUE == Can_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
                        {
                        #endif
                            Mailbox.CanId = u32MbMessageId;
                            Mailbox.Hoh = u32MbHrh;
                            Mailbox.ControllerId = controller;
                            PduInfoPtr.SduDataPtr = u8CanMbData;
                            PduInfoPtr.SduLength = u8MbDataLength;
                            CanIf_RxIndication( &Mailbox, &PduInfoPtr);
                        #if (CAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                        }
                        #endif
                        break;
                    }
                }
            }
        }
    }
    else
    {
#endif
        u32RxBufferAddOffset = pCanControllerSectionOffset->RxBufferOffset;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        /* Clear DRX flag in interrupt mode */
        REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_DRX_U32);
     
        if (u8BufferID < 32U)
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            u32FlagRxBuffer = (uint32)(((uint32)((uint32)1U << (uint32)u8BufferID)) & (REG_READ32( MCAN_NDAT1_ADDR32(u8HwOffset))));
        }
        else
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            u32FlagRxBuffer = (uint32)(((uint32)((uint32)1U << (uint32)((uint32)u8BufferID - (uint32)32U))) & (REG_READ32( MCAN_NDAT2_ADDR32(u8HwOffset))));
        }
        if (0U != u32FlagRxBuffer)
        {
            u32BaseAddress = SCM_RAM_BASEADDR + (u32RxBufferAddOffset << 2) + ((uint32)(u8BufferID) * u8MbSize[controller]);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            u8MbDataLength = (uint8)((uint32)(REG_BIT_GET32(( u32BaseAddress + 4U), MCAN_RX_MB_DLC_MASK_U32)) >> MCAN_RX_MB_DLC_SHIFT_U8 );
            /* decode the length of the data buffer */
            u8MbDataLength = Can_Mcan_DecodeLenghtData(u8MbDataLength);
            /* Prevents that a buffer overflow to be generated by a CAN bus error affecting length field*/
        #if (CAN_FD_MODE_ENABLE == STD_ON)
            if (u8MbDataLength > CAN_REAL_PAYLOAD_U8)
            {
                u8MbDataLength = CAN_REAL_PAYLOAD_U8;
            }
        #else
            if (u8MbDataLength > (uint8)8U)
            {
                u8MbDataLength = (uint8)8U;
            }
        #endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            if ((uint32)MCAN_RX_MB_XTD_MASK_U32 == ((( REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_XTD_MASK_U32 ))) & (uint32)MCAN_RX_MB_XTD_MASK_U32) )
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u32MbMessageId = (Can_IdType)(((REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_ID_MASK_U32))) | MCAN_MBC_ID_IDE_U32 );
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u32MbMessageId = (Can_IdType)((((REG_BIT_GET32( u32BaseAddress , MCAN_RX_MB_ID_MASK_U32))) & MCAN_MB_TYPE_STD_U32) >> MCAN_STANDARD_ID_SHIFT_U8 );
            }
            
        #if (CAN_FD_MODE_ENABLE == STD_ON)
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Check the frame, if frame is a FD frame */
            if (MCAN_EDL_MASK_U32 == REG_BIT_GET32( u32BaseAddress + 4U , MCAN_EDL_MASK_U32))
            {
                u32MbMessageId |= CAN_FD_ID_DESCRIPTOR;
            }
        #endif
            /* Read data to the aray */
            for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
            {
                u8TempVar = (uint8)((u8DatabyteIndex & (uint8)0xFCU) + 3U) - (uint8)(u8DatabyteIndex & 3U);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                u8CanMbData[u8DatabyteIndex] = ( REG_READ8( u32BaseAddress + 8U + (uint32)u8TempVar ));
            }
            
            /* A flag is cleared by writing a 1 to the corresponding bit position */
            if (u8BufferID < 32U)
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_NDAT1_ADDR32(u8HwOffset), (uint32)((uint32)1U << (uint32)u8BufferID));
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_NDAT2_ADDR32(u8HwOffset), (uint32)((uint32)1U << ((uint32)u8BufferID - (uint32)32U)));
            }
            for (u8MbCtrlIndex = 0U; u8MbCtrlIndex < pCanMbConfigContainer->uMessageBufferConfigCount; u8MbCtrlIndex++)
            {
                if ( (u8BufferID == pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u8StoredRxMb) && \
                     (controller == pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u8ControllerId)\
                   )
                {
                    u32MbHrh = (Can_HwHandleType)pCanMbConfigContainer->pMessageBufferConfigsPtr[u8MbCtrlIndex].u32HWObjID;
                     
                    #if (CAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                    /*[CAN444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */
                    if ((boolean)TRUE == Can_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
                    {
                    #endif
                        Mailbox.CanId = u32MbMessageId;
                        Mailbox.Hoh = u32MbHrh;
                        Mailbox.ControllerId = controller;
                        PduInfoPtr.SduDataPtr = u8CanMbData;
                        PduInfoPtr.SduLength = u8MbDataLength;
                        CanIf_RxIndication( &Mailbox, &PduInfoPtr);
                    #if (CAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                    }
                    #endif
                    break;
                }
            }
        }
#if (CAN_RXFIFO_ENABLE == STD_ON)
    }
#endif
}

/*================================================================================================*/
/**
* @brief          Service to perform the polling of RX indications.
* @details        Processes Rx interrupt flags.
*                 This routine is called by:
*                    - Can_MainFunction_Read() from Can.c file.
*
* @pre            The controller must be configured for receive in polling mode and at least one MB is configured for Rx.
* @post           Process the reception data in case of availability.
*
*
*/

#if (CAN_RXPOLL_SUPPORTED == STD_ON)

FUNC (void, CAN_CODE) Can_MCan_MainFunctionRead( void)
{
    /* Index CAN controllers from configuration. */
    VAR(uint8, AUTOMATIC)       u8CtrlIndex = 0U;
    VAR(uint8, AUTOMATIC)       u8MBIndex = 0U;
    VAR(uint8, AUTOMATIC)       u8HwOffset = 0U;
    /* Local copy of pointer to the controller descriptor. */
    P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor = NULL_PTR;

    for ( u8CtrlIndex = (uint8)0U; u8CtrlIndex < (uint8)CanStatic_pCurrentConfig->u8ControllersConfigured; u8CtrlIndex++)
    {
        pCanControlerDescriptor = &(Can_pCurrentConfig->ControlerDescriptors[u8CtrlIndex]);
        u8HwOffset = CanStatic_pControlerDescriptors[u8CtrlIndex].u8ControllerOffset;
        if ( (MCAN_NULL_OFFSET_U8 != CanStatic_pControlerDescriptors[u8CtrlIndex].u8ControllerOffset) )
        {
#if (CAN_RXFIFO_ENABLE == STD_ON)
            Can_MCan_ProcessRx( (uint8)u8CtrlIndex, MCAN_STORE_RX_FIFO0_U8);
            Can_MCan_ProcessRx( (uint8)u8CtrlIndex, MCAN_STORE_RX_FIFO1_U8);
#endif
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            if ( MCAN_INTERRUPT_DRX_U32 == ((REG_READ32( MCAN_IR_ADDR32(u8HwOffset))) & MCAN_INTERRUPT_DRX_U32) )
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                /* clean flag rx buffer */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_DRX_U32);
                for (u8MBIndex = 0U; u8MBIndex < pCanControlerDescriptor->u8MaxMbRxCount; u8MBIndex++)
                {
                    Can_MCan_ProcessRx( (uint8)u8CtrlIndex, u8MBIndex);
                }
            }
        }
    }
}

/*================================================================================================*/
/**
* @brief          Function called at fixed cyclic time, with polling of all the MessageBuffer referenced to .readpoll
* @details        Service for performs the polling of RX indications when CAN_RX_PROCESSING is set to POLLING.
*                 This routine is called by:
*                 - CanIf or an upper layer according to Autosar requirements.
*
* @api
* @pre            Driver must be initialized.
* @post           Receive the data from that MB that is configured for Rx.
*/
/* @violates @ref Can_Mcan_c_REF_7 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_MCan_MainFunctionMultipleReadPoll( VAR(uint8, AUTOMATIC) readpoll)
{
    VAR(uint8, AUTOMATIC)  u8CtrlId = 0U;
    VAR(uint8, AUTOMATIC)  u8MbIdx = 0U;
    
    if ( NULL_PTR != Can_pCurrentConfig )
    {
      #if (CAN_DEV_ERROR_DETECT == STD_ON)
        if ( CAN_UNINIT == Can_eDriverStatus )
        {
            
            (void)Det_ReportError( (uint16)CAN_MODULE_ID, (uint8)CAN_INSTANCE, (uint8)CAN_SID_MAIN_FUNCTION_READ, (uint8)CAN_E_UNINIT);
        }
        else
        {
      #endif
            for ( u8MbIdx = (uint8)0U; u8MbIdx < (uint8)Can_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; u8MbIdx++)
            {
                u8CtrlId = Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u8MbIdx].u8ControllerId;
                if  ( (readpoll == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u8MbIdx].u32CanMainFuncRWPeriodRef) && \
                      (MCAN_NULL_OFFSET_U8 != CanStatic_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
                      ((uint32)0U != (CAN_CONTROLLERCONFIG_RXPOL_EN_U32 & (CanStatic_pControlerDescriptors[u8CtrlId].u32Options))) && \
                      (CAN_RECEIVE == Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u8MbIdx].eMBType ) \
                    ) 
                {
                    Can_MCan_ProcessRx( (uint8)u8CtrlId,(Can_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u8MbIdx].u8StoredRxMb));
                }
            }
      #if (CAN_DEV_ERROR_DETECT == STD_ON)
        }
      #endif
    }
}
#endif

/*================================================================================================*/
/**
* @brief          Service to perform the polling of CAN status register flags to detect transition of CAN Controller state
* @details        The function Can_MainFunction_Mode shall implement the polling of CAN status register flags to detect transition of CAN Controller state
*                 This routine is called by:
*                   - Can_MainFunction_Mode() from Can.c file.
*
* @pre
* @post
*
*/

FUNC (void, CAN_CODE) Can_MCan_MainFunctionMode( void)
{
    VAR(uint8, AUTOMATIC)  u8CtrlIndex = 0U;    /* Index CAN controllers from configuration. */
    VAR(uint8, AUTOMATIC)  u8HwOffset = 0U;     /* Controller hardware offset on chip. */
    VAR(uint32, AUTOMATIC)  u32NewMcr = 0U;
    P2CONST(CanStatic_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanStaticControlerDescriptor = NULL_PTR;

    for ( u8CtrlIndex = (uint8)0U; u8CtrlIndex < (uint8)CanStatic_pCurrentConfig->u8ControllersConfigured; u8CtrlIndex++)
    {
        if ( (MCAN_NULL_OFFSET_U8 != CanStatic_pCurrentConfig->StaticControlerDescriptors[u8CtrlIndex].u8ControllerOffset) )
        {
            if(CAN_CS_SLEEP != Can_ControllerState[u8CtrlIndex])
            { 
                pCanStaticControlerDescriptor = &CanStatic_pCurrentConfig->StaticControlerDescriptors[u8CtrlIndex];
                u8HwOffset = pCanStaticControlerDescriptor->u8ControllerOffset;
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                /* from CAN_CS_STARTED to CAN_CS_STOPPED (in CAN_CS_STOPPED,  CCCR[INIT] = 1)*/
                u32NewMcr = (uint32)(REG_READ32( MCAN_CCCR_ADDR32(u8HwOffset))) ;
                if( ((u32NewMcr & MCAN_CCCR_INIT_U32) == MCAN_CCCR_INIT_U32)&& (CAN_CS_STARTED == Can_ControllerState[u8CtrlIndex]))
                {
                    Can_ControllerState[u8CtrlIndex] = CAN_CS_STOPPED;
                    CanIf_ControllerModeIndication(u8CtrlIndex, CANIF_CS_STOPPED);
                }
                /* from CAN_CS_STOPPED to CAN_CS_STARTED (in CAN_CS_STARTED,  CCCR[INIT] = 0 and CCCR[CCE] = 0)*/
                if( ((u32NewMcr & MCAN_CCCR_INIT_U32) == 0U) &&(CAN_CS_STOPPED == Can_ControllerState[u8CtrlIndex]))
                {
                    Can_ControllerState[u8CtrlIndex] = CAN_CS_STARTED;
                    CanIf_ControllerModeIndication(u8CtrlIndex, CANIF_CS_STARTED);
                }
            }
        }
    }
}

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer during Can_MainFunction_BusOff if polling is selected or from ISR when Interrupt mode selected.
* @details        Local function for calling notification function to notify upper layer during
*                 Can_MainFunction_BusOff if polling is selected or from ISR when Interrupt mode selected.
*                 This routine is called by:
*                  - Can_MainFunction_BusOff() from Can.c file.
*                  - Can_MCan_Isr_common_process_interrupt() from Can_MCan.c file.
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @pre            A busoff condition must to be fulfilled.
* @post           Status flag is cleared.
*
*/
/* @violates @ref Can_Mcan_c_REF_7 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_MCan_ProcessBusOff( CONST(uint8, AUTOMATIC) controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC) u8HwOffset = 0U;
    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* Clear Bus_Off Status flag */
    REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_BO_U32);

}

/*================================================================================================*/
/**
* @brief          This function checks if a BusOff has occurred for the given controller.
* @details        This routine is called by:
*                  - Can_MainFunction_BusOff() from Can.c file.
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @return        Std_ReturnType
* @retval        E_OK wakeup detected
* @retval        E_NOT_OK wakeup not detected
*
* @pre            A request for busoff checking is required.
* @post           Report the occurence or not for an busoff event.
*
*/
/* @violates @ref Can_Mcan_c_REF_7 MISRA 2012 Advisory Rule 8.7 */
FUNC (Std_ReturnType, CAN_CODE) Can_MCan_CheckBusOff( VAR(uint8, AUTOMATIC) controller )
{
    /* Variable store return value */
    VAR(uint8, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC) u8HwOffset = 0U;
    /* Temporary variable */
    VAR(uint32, AUTOMATIC) u32TempVar = 0U;
    VAR(uint32, AUTOMATIC) u32TempVar1 = 0U;
    VAR(uint32, AUTOMATIC) u32TempVar2 = 0U;

    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    u32TempVar = REG_BIT_GET32( MCAN_PSR_ADDR32(u8HwOffset), MCAN_PSR_BO_U32 );
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    u32TempVar1 = REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset)) & MCAN_CCCR_INIT_U32;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    u32TempVar2 = REG_BIT_GET32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_BO_U32 );
    if ( ( MCAN_PSR_BO_U32 == u32TempVar) && ( MCAN_CCCR_INIT_U32 == u32TempVar1) && ( MCAN_INTERRUPT_BO_U32 == u32TempVar2))
    {
        eReturnValue = (Std_ReturnType)E_OK;
    }
    return eReturnValue;
}
/*================================================================================================*/
/*
* @brief          Process a transition from one clock source to another.
* @details        This function is configuring Can controllers to run on the same baudrate, but having a different MCU source clock.
*                 This routine is called by:
*                  - Can_SetClockMode() from Can.c file.
*
* @param[in]      u8CanController    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      can_clk_mode clock mode selection
*
* @return        Std_ReturnType Result of the clock switch operation.
* @retval        E_OK  Switch clock operation was ok.
* @retval        E_NOT_OK  Switch clock operation was not ok.
*
* @pre            Driver must be initialized and all the controllers must be in Stop state.
*
* @note           Not AUTOSAR required. This is user implementation.
*/

#if (CAN_DUAL_CLOCK_MODE == STD_ON)

FUNC(Std_ReturnType, CAN_CODE) Can_MCan_SetClockMode( VAR(uint8, AUTOMATIC) u8Controller, VAR(Can_ClockModeType, AUTOMATIC) can_clk_mode)
{
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;

    if ((can_clk_mode == CAN_NORMAL) || (can_clk_mode == CAN_ALTERNATE))
    {
        /* Set the controller clock mode*/
        Can_ClockMode[u8Controller] = can_clk_mode;
        eReturnValue = (Std_ReturnType)E_OK;
    }
    return eReturnValue;
}

#endif

#ifdef ERR_IPV_MCAN_0002 
    #if (ERR_IPV_MCAN_0002 == STD_ON)
        FUNC (void, CAN_CODE) Can_MCan_DummyRead(VAR(uint8, AUTOMATIC) u8Controller)
        {
            VAR(uint8, AUTOMATIC)      u8HwOffset = 0U;
            VAR(uint8, AUTOMATIC)      u8MbIndex = 0U;
            u8HwOffset = CanStatic_pControlerDescriptors[u8Controller].u8ControllerOffset;
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Clear all IRQs because they are invalid now */
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_MASK_32BITS_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Read out all message in FIFO0, actually just read the index and set acknowledgement for coresponde index */
            while ( (REG_READ32( MCAN_RXF0S_ADDR32(u8HwOffset)) & MCAN_RXF0S_F0FL_U32)> 0U)
            {
                u8MbIndex = (uint8)(((REG_READ32( MCAN_RXF0S_ADDR32(u8HwOffset))) & MCAN_RXF0S_F0GI_U32) >> 8U );
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_RXF0A_ADDR32(u8HwOffset), (uint32)(u8MbIndex & MCAN_RXF0A_F0AI_U32));
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Read out all message in FIFO1, actually just read the index and set acknowledgement for coresponde index */
            while ((REG_READ32( MCAN_RXF1S_ADDR32(u8HwOffset)) & MCAN_RXF1S_F1FL_U32)> 0U)
            {
                u8MbIndex = (uint8)(((REG_READ32( MCAN_RXF1S_ADDR32(u8HwOffset))) & MCAN_RXF1S_F1GI_U32) >> 8U );
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_RXF1A_ADDR32(u8HwOffset), (uint32)(u8MbIndex & MCAN_RXF1A_F1AI_U32));
            }
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /* Do not care about the data, just clear all the new message reported by NDATx */
            REG_WRITE32( MCAN_NDAT1_ADDR32(u8HwOffset), MCAN_MASK_32BITS_U32);
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( MCAN_NDAT2_ADDR32(u8HwOffset), MCAN_MASK_32BITS_U32);
        }
    #endif
#endif
#if (CAN_SUPPORT_MRAF_EVENT == STD_ON)
    #if (CAN_MRAFPOLL_SUPPORTED == STD_ON)
        FUNC (void, CAN_CODE) Can_MCan_MainFunction_CheckMRAF( void)
        {
            /* Variable for indexing the controllers. */
            VAR(uint8, AUTOMATIC) u8CanController = 0U;
            VAR(uint8, AUTOMATIC) u8HwOffset = 0U;
            
            for ( u8CanController = 0U; u8CanController < (uint8)CanStatic_pCurrentConfig->u8ControllersConfigured; u8CanController++)
            {
                if ( MCAN_NULL_OFFSET_U8 != (CanStatic_pControlerDescriptors[u8CanController].u8ControllerOffset))
                {
                    if ( CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32 == (CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32 & CanStatic_pControlerDescriptors[u8CanController].u32Options))
                    {
                        u8HwOffset = CanStatic_pControlerDescriptors[u8CanController].u8ControllerOffset;
                        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                        if (MCAN_INTERRUPT_MRAF_U32 == (REG_READ32( MCAN_IR_ADDR32(u8HwOffset)) & MCAN_INTERRUPT_MRAF_U32))
                        {
                            if ( NULL_PTR != CanStatic_pCurrentConfig->StaticControlerDescriptors[u8CanController].Can_SupportMRAFNotification)
                            {
                                CanStatic_pCurrentConfig->StaticControlerDescriptors[u8CanController].Can_SupportMRAFNotification();
                            }
                            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                            /* Clear flag any way */
                            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_MRAF_U32);
                        }
                    }
                }
            }
        }
    #endif
#endif /* (CAN_SUPPORT_MRAF_EVENT == STD_OFF) */ 

#if (STD_ON == CAN_INTERRUPT_SUPPORTED)
/*================================================================================================*/
/**
* @brief          This function is called from ISR service routine
* @details        This function is used to handle the Interrupts
* @param[in]u8CanController    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @return void
* @retval void
* @retval void
* @implements     Can_MCan_Isr_common_process_interrupt_Activity
*
*/
FUNC(void, CAN_CODE) Can_MCan_Isr_common_process_interrupt( CONST(uint8, AUTOMATIC) controller)
{
    volatile VAR(uint32, AUTOMATIC)  u32TempInterruptStatus = 0U;
    volatile VAR(uint32, AUTOMATIC)  u32TempInterruptEnable = 0U;
    VAR(uint8, AUTOMATIC)  u8HwOffset = 0U;
    VAR(uint8, AUTOMATIC)  u8MBIndex = 0U;
    /* Pointer to the MB container structure. */
    P2CONST(Can_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor = NULL_PTR;
    /* Temporary variable */
    VAR(uint32, AUTOMATIC) u32TempVar = 0U;
    VAR(uint32, AUTOMATIC) u32TempVar1 = 0U;
    /* Hardware Can controller offset. */
    u8HwOffset = CanStatic_pControlerDescriptors[controller].u8ControllerOffset;
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    /* To store the CAN Interrupt Status Register */
    u32TempInterruptStatus = REG_READ32( MCAN_IR_ADDR32(u8HwOffset));
    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
    u32TempInterruptEnable = REG_READ32( MCAN_IE_ADDR32(u8HwOffset));
    
    /* check any error bits are set & call error notification */
    if (NULL_PTR != Can_pCurrentConfig)
    {
        pCanControlerDescriptor = &Can_pCurrentConfig->ControlerDescriptors[controller];
        
    #if (CAN_ERROR_NOTIFICATION_ENABLE == STD_ON)
        if((u32TempInterruptStatus & MCAN_ERR_INTERRUPT_U32) != 0U)
        {
            /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
            /*Clear the Error Flags*/
            REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), (uint32) MCAN_ERR_INTERRUPT_U32);
            if ( NULL_PTR != CanStatic_pCurrentConfig->StaticControlerDescriptors[controller].Can_ErrorNotification)
            {
                /*call error notification */
                CanStatic_pCurrentConfig->StaticControlerDescriptors[controller].Can_ErrorNotification();
            }
        }
    #endif
    #if (CAN_MRAFINT_SUPPORTED == STD_ON)
        if(MCAN_INTERRUPT_MRAF_U32 == (u32TempInterruptStatus & MCAN_INTERRUPT_MRAF_U32))
        {
            if ( CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32 != (CAN_CONTROLLERCONFIG_MRAFPOL_EN_U32 & CanStatic_pControlerDescriptors[controller].u32Options))
            {
                if ( NULL_PTR != CanStatic_pCurrentConfig->StaticControlerDescriptors[controller].Can_SupportMRAFNotification)
                {
                    CanStatic_pCurrentConfig->StaticControlerDescriptors[controller].Can_SupportMRAFNotification();
                }
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_MRAF_U32);
            }
        }
    #endif
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        u32TempVar = REG_READ32(MCAN_CCCR_ADDR32(u8HwOffset))& MCAN_CCCR_INIT_U32;
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        u32TempVar1 = REG_BIT_GET32( MCAN_PSR_ADDR32(u8HwOffset), MCAN_PSR_BO_U32);
        
        if ( (u32TempInterruptStatus & MCAN_INTERRUPT_BO_U32) != 0U )
        {
            if ( ((u32TempInterruptEnable & MCAN_INTERRUPT_BO_U32) != 0U) \
                  && ( MCAN_CCCR_INIT_U32 == u32TempVar) \
                  && ( MCAN_PSR_BO_U32 ==  u32TempVar1) \
               )
            {
                if ( (Std_ReturnType)E_OK == Can_MCan_SetControllerMode( controller, &(Can_pCurrentConfig->ControlerDescriptors[controller]), \
                     CAN_CS_STOPPED,(boolean)FALSE) \
                   )
                {
                    Can_MCan_ProcessBusOff(controller);
                    CanIf_ControllerBusOff(controller);
                }
            }
         #if (CAN_BUSOFFPOLL_SUPPORTED == STD_OFF)
            else if(CAN_CONTROLLERCONFIG_BOPOL_EN_U32 != (CAN_CONTROLLERCONFIG_BOPOL_EN_U32 & CanStatic_pControlerDescriptors[controller].u32Options))
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_BO_U32);
            }
            else
            {
                /* Just for prevent misra */
            }
          #endif
        }
        if(0U != (u32TempInterruptStatus & MCAN_INTERRUPT_TC_U32))
        {
            if(0U != (u32TempInterruptEnable & MCAN_INTERRUPT_TC_U32))
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_TC_U32);
                for (u8MBIndex = 0U; u8MBIndex < Can_pControlerDescriptors[controller].u8MaxMbTxCount; u8MBIndex++)
                {
                    /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                    if (0U != REG_BIT_GET32(MCAN_TXBTIE_ADDR32(u8HwOffset),((uint32)1U << u8MBIndex)))
                    {
                        Can_MCan_ProcessTx( controller, u8MBIndex, u8MBIndex);
                    }
                }
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_TCF_U32);
            }
        }
    #if (CAN_RXFIFO_ENABLE == STD_ON)
        if(MCAN_INTERRUPT_RF0N_U32 == (u32TempInterruptStatus & MCAN_INTERRUPT_RF0N_U32))
        {
            if (MCAN_INTERRUPT_RF0N_U32 == (u32TempInterruptEnable & MCAN_INTERRUPT_RF0N_U32 ))
            {
                Can_MCan_ProcessRx(controller, (uint8)MCAN_STORE_RX_FIFO0_U8);
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0N_U32);
            }
        }
        if(MCAN_INTERRUPT_RF1N_U32 == (u32TempInterruptStatus & MCAN_INTERRUPT_RF1N_U32))
        {
            if (MCAN_INTERRUPT_RF1N_U32 == (u32TempInterruptEnable & MCAN_INTERRUPT_RF1N_U32 ))
            {
                Can_MCan_ProcessRx(controller, (uint8)MCAN_STORE_RX_FIFO1_U8);
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1N_U32);
            }
        }
    #endif
        if(MCAN_INTERRUPT_DRX_U32 == (u32TempInterruptStatus & MCAN_INTERRUPT_DRX_U32))
        {
            if (MCAN_INTERRUPT_DRX_U32 == (u32TempInterruptEnable & MCAN_INTERRUPT_DRX_U32))
            {
                for (u8MBIndex = 0U; u8MBIndex < pCanControlerDescriptor->u8MaxMbRxCount; u8MBIndex++)
                {
                    Can_MCan_ProcessRx(controller, u8MBIndex);
                }
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_DRX_U32);
            }
        }
    #if (CAN_RXFIFO_ENABLE == STD_ON)
        if(0U != (u32TempInterruptStatus & (MCAN_INTERRUPT_RF0F_U32 | MCAN_INTERRUPT_RF0L_U32)))
        {
            if(0U != (u32TempInterruptEnable & (MCAN_INTERRUPT_RF0F_U32 | MCAN_INTERRUPT_RF0L_U32)))
            {
                Can_MCan_ProcessRx( controller,(uint8)MCAN_STORE_RX_FIFO0_U8);
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0L_U32);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0F_U32);
            }
        }
        if(0U != (u32TempInterruptStatus & (MCAN_INTERRUPT_RF1F_U32 | MCAN_INTERRUPT_RF1L_U32)))
        {
            if(0U != (u32TempInterruptEnable & (MCAN_INTERRUPT_RF1F_U32 | MCAN_INTERRUPT_RF1L_U32)))
            {
                Can_MCan_ProcessRx(controller,(uint8)MCAN_STORE_RX_FIFO1_U8);
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1F_U32);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1L_U32);
            }
        }
        if(0U != (u32TempInterruptStatus & (MCAN_INTERRUPT_RF0W_U32 | MCAN_INTERRUPT_RF1W_U32)))
        {
            if(0U != (u32TempInterruptEnable & (MCAN_INTERRUPT_RF0W_U32 | MCAN_INTERRUPT_RF1W_U32)))
            {
                if ((uint8)MCAN_INTERRUPT_RF0W_U32 == (u32TempInterruptStatus & MCAN_INTERRUPT_RF0W_U32))
                {
                    Can_MCan_ProcessRx( controller,(uint8)MCAN_STORE_RX_FIFO0_U8);
                }
                if ((uint8)MCAN_INTERRUPT_RF1W_U32 == (u32TempInterruptStatus & MCAN_INTERRUPT_RF1W_U32))
                {
                    Can_MCan_ProcessRx(controller,(uint8)MCAN_STORE_RX_FIFO1_U8);
                }
            }
            else
            {
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF1W_U32);
                /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), MCAN_INTERRUPT_RF0W_U32);
            }
        }
    #endif
    }
    else
    {
        /* @violates @ref Can_Mcan_c_REF_4 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Mcan_c_REF_5 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Mcan_c_REF_6 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( MCAN_IR_ADDR32(u8HwOffset), u32TempInterruptStatus);
    }
}
#endif

#define CAN_STOP_SEC_CODE
/* @violates @ref Can_Mcan_c_REF_2 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Mcan_c_REF_3 MISRA 2012 Advisory Rule 20.1 */
#include "Can_MemMap.h"

#ifdef __cplusplus
}
#endif
/** @} */
