/**
*   @file    Gpt_Stm.c
*   @version 1.0.0
*
*   @brief   AUTOSAR Gpt - STM driver source file.
*   @details Containes the interface functions of the STM driver.
*
*   @addtogroup GPT_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eMios_Stm_Pit
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct. 
*     The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space
*     shall be distinct.
*     The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
*     The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
*     The used compilers use more than 31 chars for identifiers.
*
* @section GPT_STM_C_REF_1
*     Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent
*     the contents of a header file being included more than once.
*     This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement
*     [SWS_MemMap_00003].
*
* @section GPT_STM_C_REF_2
*     Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void
*     and an arithmetic type.
*     This macro computes the address of any register by using the hardware offset of the controller.
*     The address calculated as an unsigned INT is passed to a macro for initializing the pointer 
*     with that address
*
* @section GPT_STM_C_REF_3
*     Violates MISRA 2012 Advisory Rule 8.7, Functions and objects should not be defined with 
*     external linkage if they are referenced in only one translation unit.
*
* @section GPT_STM_C_REF_4
*     Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by
*     preprocessor directives or comments.
*     <MA>_MemMap.h is included after each section define in order to set the current memory section
*     as defined by AUTOSAR
*
* @section GPT_STM_C_REF_5
*     Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer
*     to object and an integer type.
*     The cast is used to access memory mapped registers.
*
* @section GPT_STM_C_REF_6
*     Violates MISRA 2012 Required Rule 10.8, The value of a composite expression shall not be cast
*     to a different essential type or a wider essential type.
*     The cast is used to access memory mapped registers.
*
* @section GPT_STM_C_REF_7
*     Violates MISRA 2012 Advisory Directive 4.9, A function should be used in preference to
*     a function-like macro where they are interchangeable.
*
* @section GPT_STM_C_REF_8
*     Violates MISRA 2012 Advisory Rule 12.3, The comma operator should not be used. 
*     The comma is used to abstract the trusted call function and to determine when the return into 
*     user mode is needed.
*
* @section GPT_STM_C_REF_9
*     Violates MISRA 2012 Required Rule 14.4, The controlling expression of an if statement and 
*     the controlling expression of an iteration-statement shall have essentially Boolean type.
*     Multi-statement macros shall be wrapped in a do–while loop, so the macro can appear safely inside if 
*     clauses or other places that expect a single statement or a statement block
*
*/
/*==================================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Std_Types.h"
#include "Gpt_Ipw_Irq.h"
#include "Gpt_Stm.h"
#include "Reg_eSys_Stm.h"
#include "SchM_Gpt.h"

#ifdef GPT_ENABLE_USER_MODE_SUPPORT
   #define USER_MODE_REG_PROT_ENABLED   GPT_ENABLE_USER_MODE_SUPPORT
   #include "RegLockMacros.h"
#endif

#include "SilRegMacros.h"

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/

#define GPT_STM_VENDOR_ID_C                    43
#define GPT_STM_AR_RELEASE_MAJOR_VERSION_C     4
#define GPT_STM_AR_RELEASE_MINOR_VERSION_C     3
#define GPT_STM_AR_RELEASE_REVISION_VERSION_C  1
#define GPT_STM_SW_MAJOR_VERSION_C             1
#define GPT_STM_SW_MINOR_VERSION_C             0
#define GPT_STM_SW_PATCH_VERSION_C             0
/** @} */
/*==================================================================================================
*                                      FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
     /* Check if header file and Std_Types.h file are of the same Autosar version */
    #if ((GPT_STM_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \
         (GPT_STM_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION) \
        )
        #error "AutoSar Version Numbers of Gpt_Stm.c and Std_Types.h are different"
    #endif

    /* Check if source file and SilRegMacros.h are of the same Autosar version */
    #if ((GPT_STM_AR_RELEASE_MAJOR_VERSION_C    != SILREGMACROS_AR_RELEASE_MAJOR_VERSION) || \
         (GPT_STM_AR_RELEASE_MINOR_VERSION_C    != SILREGMACROS_AR_RELEASE_MINOR_VERSION) || \
         (GPT_STM_AR_RELEASE_REVISION_VERSION_C != SILREGMACROS_AR_RELEASE_REVISION_VERSION) \
        )
        #error "AutoSar Version Numbers of Gpt_Stm.c and SilRegMacros.h are different"
    #endif
#endif

#if (GPT_STM_VENDOR_ID_C != GPT_IPW_IRQ_VENDOR_ID)
    #error "Gpt_Stm.c and Gpt_Ipw_Irq.h have different vendor ids"
#endif
/* Check if header file and Gpt header file are of the same Autosar version */
#if ((GPT_STM_AR_RELEASE_MAJOR_VERSION_C != GPT_IPW_IRQ_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_STM_AR_RELEASE_MINOR_VERSION_C != GPT_IPW_IRQ_AR_RELEASE_MINOR_VERSION) || \
     (GPT_STM_AR_RELEASE_REVISION_VERSION_C != GPT_IPW_IRQ_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Stm.c and Gpt_Ipw_Irq.h are different"
#endif
/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_STM_SW_MAJOR_VERSION_C != GPT_IPW_IRQ_SW_MAJOR_VERSION) || \
     (GPT_STM_SW_MINOR_VERSION_C != GPT_IPW_IRQ_SW_MINOR_VERSION) || \
     (GPT_STM_SW_PATCH_VERSION_C != GPT_IPW_IRQ_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Stm.c and Gpt_Ipw_Irq.h are different"
#endif

#if (GPT_STM_VENDOR_ID_C != GPT_STM_VENDOR_ID)
    #error "Gpt_Stm.c and Gpt_Stm.h have different vendor ids"
#endif
/* Check if header file and Gpt header file are of the same Autosar version */
#if ((GPT_STM_AR_RELEASE_MAJOR_VERSION_C != GPT_STM_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_STM_AR_RELEASE_MINOR_VERSION_C != GPT_STM_AR_RELEASE_MINOR_VERSION) || \
     (GPT_STM_AR_RELEASE_REVISION_VERSION_C != GPT_STM_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Stm.c and Gpt_Stm.h are different"
#endif
/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_STM_SW_MAJOR_VERSION_C != GPT_STM_SW_MAJOR_VERSION) || \
     (GPT_STM_SW_MINOR_VERSION_C != GPT_STM_SW_MINOR_VERSION) || \
     (GPT_STM_SW_PATCH_VERSION_C != GPT_STM_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Stm.c and Gpt_Stm.h are different"
#endif

#if (GPT_STM_VENDOR_ID_C != GPT_STM_TYPES_VENDOR_ID)
    #error "Gpt_Stm.c and Gpt_Stm_Types.h have different vendor ids"
#endif
/* Check if header file and Gpt header file are of the same Autosar version */
#if ((GPT_STM_AR_RELEASE_MAJOR_VERSION_C != GPT_STM_TYPES_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_STM_AR_RELEASE_MINOR_VERSION_C != GPT_STM_TYPES_AR_RELEASE_MINOR_VERSION) || \
     (GPT_STM_AR_RELEASE_REVISION_VERSION_C != GPT_STM_TYPES_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Stm.c and Gpt_Stm_Types.h are different"
#endif
/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_STM_SW_MAJOR_VERSION_C != GPT_STM_TYPES_SW_MAJOR_VERSION) || \
     (GPT_STM_SW_MINOR_VERSION_C != GPT_STM_TYPES_SW_MINOR_VERSION) || \
     (GPT_STM_SW_PATCH_VERSION_C != GPT_STM_TYPES_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Stm.c and Gpt_Stm_Types.h are different"
#endif

#if (GPT_STM_VENDOR_ID_C != REG_ESYS_STM_VENDOR_ID)
    #error "Gpt_Stm.c and Reg_eSys_Stm.h have different vendor ids"
#endif
/* Check if header file and Gpt header file are of the same Autosar version */
#if ((GPT_STM_AR_RELEASE_MAJOR_VERSION_C != REG_ESYS_STM_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_STM_AR_RELEASE_MINOR_VERSION_C != REG_ESYS_STM_AR_RELEASE_MINOR_VERSION) || \
     (GPT_STM_AR_RELEASE_REVISION_VERSION_C != REG_ESYS_STM_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Stm.c and Reg_eSys_Stm.h are different"
#endif
/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_STM_SW_MAJOR_VERSION_C != REG_ESYS_STM_SW_MAJOR_VERSION) || \
     (GPT_STM_SW_MINOR_VERSION_C != REG_ESYS_STM_SW_MINOR_VERSION) || \
     (GPT_STM_SW_PATCH_VERSION_C != REG_ESYS_STM_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Stm.c and Reg_eSys_Stm.h are different"
#endif

/*==================================================================================================
*                                          LOCAL DEFINIES
==================================================================================================*/
/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/
#if (GPT_STM_USED == STD_ON)
#if (defined (MCAL_STM_REG_PROT_AVAILABLE) && (STD_ON == GPT_ENABLE_USER_MODE_SUPPORT))
    /** @violates @ref GPT_STM_C_REF_7 MISRA 2012 Advisory Directive 4.9, Function like macro are
    *   used to reduce code complexity.*/ 
    #define Call_Gpt_Stm_SetUserAccessAllowed(StmBaseAddr) Mcal_Trusted_Call1param(Gpt_Stm_SetUserAccessAllowed,(StmBaseAddr))
#else
    /** @violates @ref GPT_STM_C_REF_7 MISRA 2012 Advisory Directive 4.9, Function like macro are
    *   used to reduce code complexity.*/ 
    #define Call_Gpt_Stm_SetUserAccessAllowed(StmBaseAddr)
#endif

/*==================================================================================================
*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/
/**
* @brief Number of counter cycles missed due to overflow
*/
#define STM_OVERFLOW_PAD_U32         ((uint32)1U)

/**
* @brief Highest possible value for STM channels
*/
#define STM_CNT_MAX_VALUE_U32        ((uint32)0xFFFFFFFFuL)

/*==================================================================================================
*                                       LOCAL CONSTANTS
==================================================================================================*/

#define GPT_START_SEC_CONST_32
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/**
* @brief base address array for STM
*/
/** @violates @ref GPT_STM_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
*   of the driver. External linkage is needed to "export" the API.*/
CONST(uint32, GPT_CONST) STM_BASE_ADDR32[STM_MODULE_NUM_MAX_U8] =
{
#ifdef STM_0_BASEADDR
     STM_0_BASEADDR
#else
    (uint32)(0x00000000UL)
#endif
#ifdef STM_1_BASEADDR
    ,STM_1_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef STM_2_BASEADDR
    ,STM_2_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef STM_3_BASEADDR
    ,STM_3_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef STM_4_BASEADDR
    ,STM_4_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef STM_5_BASEADDR
    ,STM_5_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef STM_6_BASEADDR
    ,STM_6_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef STM_7_BASEADDR
    ,STM_7_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
};

#define GPT_STOP_SEC_CONST_32
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/*==================================================================================================
*                                       LOCAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                       GLOBAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                       GLOBAL VARIABLES
==================================================================================================*/

#define GPT_START_SEC_VAR_NO_INIT_32
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/**
* @brief          Global array variable used to store the runtime target time value.
*/
/** @violates @ref GPT_STM_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
*   of the driver. External linkage is needed to "export" the API.*/
VAR(uint32, GPT_VAR) Gpt_Stm_u32TargetValue[GPT_STM_MODULES_NUM_U8][GPT_STM_CHANNELS_PER_MODULE_U8];

#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
/**
* @brief          Local array variable used to store the next target time value.
*/
/** @violates @ref GPT_STM_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
*   of the driver. External linkage is needed to "export" the API.*/
static VAR(uint32, GPT_VAR) Gpt_Stm_u32NextTargetValue[GPT_STM_MODULES_NUM_U8][GPT_STM_CHANNELS_PER_MODULE_U8];
#endif

#define GPT_STOP_SEC_VAR_NO_INIT_32
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#define GPT_START_SEC_VAR_INIT_8
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"
/**
* @brief          Global variable used to store which Stm modules are used for general GPT channel
* @details        Look from right side of this byte, each bit corresponding with each STM module. 
*                 The 0 value means this module is not used for general GPT channel and vice-versa
*/
/** @violates @ref GPT_STM_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
*   of the driver. External linkage is needed to "export" the API.*/
static VAR(uint8, GPT_VAR) Gpt_Stm_u8UsedForGeneralGptChannel = (uint8)0;

#define GPT_STOP_SEC_VAR_INIT_8
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"
/*==================================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/
#define GPT_START_SEC_CODE
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#if (GPT_STM_MODULE_SINGLE_INTERRUPT == STD_ON)

#ifdef GPT_STM_0_ISR_USED
ISR(Gpt_STM_0_ISR);
#endif

#ifdef GPT_STM_1_ISR_USED
ISR(Gpt_STM_1_ISR);
#endif

#ifdef GPT_STM_2_ISR_USED
ISR(Gpt_STM_2_ISR);
#endif

#ifdef GPT_STM_3_ISR_USED
ISR(Gpt_STM_3_ISR);
#endif

#ifdef GPT_STM_4_ISR_USED
ISR(Gpt_STM_4_ISR);
#endif

#ifdef GPT_STM_5_ISR_USED
ISR(Gpt_STM_5_ISR);
#endif

#ifdef GPT_STM_6_ISR_USED
ISR(Gpt_STM_6_ISR);
#endif

#ifdef GPT_STM_7_ISR_USED
ISR(Gpt_STM_7_ISR);
#endif

#else

#ifdef GPT_STM_0_CH_0_ISR_USED
ISR(Gpt_STM_0_Ch_0_ISR);
#endif

#if((defined GPT_STM_0_CH_1_ISR_USED) || (defined GPT_STM_ISR_1_SHARED))
ISR(Gpt_STM_0_Ch_1_ISR);
#endif

#ifdef GPT_STM_0_CH_2_ISR_USED
ISR(Gpt_STM_0_Ch_2_ISR);
#endif

#ifdef GPT_STM_0_CH_3_ISR_USED
ISR(Gpt_STM_0_Ch_3_ISR);
#endif
#ifdef GPT_STM_1_CH_0_ISR_USED
ISR(Gpt_STM_1_Ch_0_ISR);
#endif

#ifdef GPT_STM_1_CH_1_ISR_USED
ISR(Gpt_STM_1_Ch_1_ISR);
#endif

#ifdef GPT_STM_1_CH_2_ISR_USED
ISR(Gpt_STM_1_Ch_2_ISR);
#endif

#ifdef GPT_STM_1_CH_3_ISR_USED
ISR(Gpt_STM_1_Ch_3_ISR);
#endif
#ifdef GPT_STM_2_CH_0_ISR_USED
ISR(Gpt_STM_2_Ch_0_ISR);
#endif

#ifdef GPT_STM_2_CH_1_ISR_USED
ISR(Gpt_STM_2_Ch_1_ISR);
#endif

#ifdef GPT_STM_2_CH_2_ISR_USED
ISR(Gpt_STM_2_Ch_2_ISR);
#endif

#ifdef GPT_STM_2_CH_3_ISR_USED
ISR(Gpt_STM_2_Ch_3_ISR);
#endif

#ifdef GPT_STM_3_CH_0_ISR_USED
ISR(Gpt_STM_3_Ch_0_ISR);
#endif

#ifdef GPT_STM_3_CH_1_ISR_USED
ISR(Gpt_STM_3_Ch_1_ISR);
#endif

#ifdef GPT_STM_3_CH_2_ISR_USED
ISR(Gpt_STM_3_Ch_2_ISR);
#endif

#ifdef GPT_STM_3_CH_3_ISR_USED
ISR(Gpt_STM_3_Ch_3_ISR);
#endif

#ifdef GPT_STM_4_CH_0_ISR_USED
ISR(Gpt_STM_4_Ch_0_ISR);
#endif

#ifdef GPT_STM_4_CH_1_ISR_USED
ISR(Gpt_STM_4_Ch_1_ISR);
#endif

#ifdef GPT_STM_4_CH_2_ISR_USED
ISR(Gpt_STM_4_Ch_2_ISR);
#endif

#ifdef GPT_STM_4_CH_3_ISR_USED
ISR(Gpt_STM_4_Ch_3_ISR);
#endif

#ifdef GPT_STM_5_CH_0_ISR_USED
ISR(Gpt_STM_5_Ch_0_ISR);
#endif

#ifdef GPT_STM_5_CH_1_ISR_USED
ISR(Gpt_STM_5_Ch_1_ISR);
#endif

#ifdef GPT_STM_5_CH_2_ISR_USED
ISR(Gpt_STM_5_Ch_2_ISR);
#endif

#ifdef GPT_STM_5_CH_3_ISR_USED
ISR(Gpt_STM_5_Ch_3_ISR);
#endif

#ifdef GPT_STM_6_CH_0_ISR_USED
ISR(Gpt_STM_6_Ch_0_ISR);
#endif

#ifdef GPT_STM_6_CH_1_ISR_USED
ISR(Gpt_STM_6_Ch_1_ISR);
#endif

#ifdef GPT_STM_6_CH_2_ISR_USED
ISR(Gpt_STM_6_Ch_2_ISR);
#endif

#ifdef GPT_STM_6_CH_3_ISR_USED
ISR(Gpt_STM_6_Ch_3_ISR);
#endif

#ifdef GPT_STM_7_CH_0_ISR_USED
ISR(Gpt_STM_7_Ch_0_ISR);
#endif

#ifdef GPT_STM_7_CH_1_ISR_USED
ISR(Gpt_STM_7_Ch_1_ISR);
#endif

#ifdef GPT_STM_7_CH_2_ISR_USED
ISR(Gpt_STM_7_Ch_2_ISR);
#endif

#ifdef GPT_STM_7_CH_3_ISR_USED
ISR(Gpt_STM_7_Ch_3_ISR);
#endif

#endif /*GPT_STM_MODULE_SINGLE_INTERRUPT == STD_ON*/
/*==================================================================================================
*                                       LOCAL FUNCTIONS
==================================================================================================*/
#if ((defined GPT_STM_0_ISR_USED      ) ||(defined GPT_STM_1_ISR_USED      )||(defined GPT_STM_2_ISR_USED       )||(defined GPT_STM_ISR_1_SHARED     )|| \
     (defined GPT_STM_0_CH_0_ISR_USED ) ||(defined GPT_STM_0_CH_1_ISR_USED )||(defined GPT_STM_0_CH_2_ISR_USED  )||(defined GPT_STM_0_CH_3_ISR_USED  )|| \
     (defined GPT_STM_1_CH_0_ISR_USED ) ||(defined GPT_STM_1_CH_1_ISR_USED )||(defined GPT_STM_1_CH_2_ISR_USED  )||(defined GPT_STM_1_CH_3_ISR_USED  )|| \
     (defined GPT_STM_2_CH_0_ISR_USED ) ||(defined GPT_STM_2_CH_1_ISR_USED )||(defined GPT_STM_2_CH_2_ISR_USED  )||(defined GPT_STM_2_CH_3_ISR_USED  )   \
    )
/**
* @brief   Driver routine to process all the interrupts of STM.
* @details Support function used by interrupt service routines to implement STM specific operations
*          and call the GPT upper layer handler to implement non-hardware specific operations.
*
* @param[in]     u8HwChannel      hardware channel index
*
* @implements   Gpt_Stm_ProcessCommonInterrupt_Activity
*/

static FUNC(void, GPT_CODE) Gpt_Stm_ProcessCommonInterrupt(VAR(uint8, AUTOMATIC) u8HwChannel)\
{
    VAR(uint32, AUTOMATIC) u32OldCompare;
    VAR(uint32, AUTOMATIC) u32TargetTime;
    VAR(uint32,AUTOMATIC) u32Temp1;
    VAR(uint32,AUTOMATIC) u32Temp2;

    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)STM_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)STM_CHANNEL_INDEX_U32(u8HwChannel);
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32Temp1 = REG_BIT_GET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32);
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32Temp2 = REG_BIT_GET32(STM_CCR_ADDR32((uint32)u8HwChannel), STM_CCR_CEN_MASK_U32);

    /*Check if interrupt status flag is set and if channel is enabled*/
    if((STM_CIR_CIF_SET_U32 == u32Temp1) && (STM_CCR_CEN_ENABLE_U32 == u32Temp2))
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32OldCompare = REG_READ32(STM_CMP_ADDR32((uint32)u8HwChannel));

#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
        if(Gpt_Stm_u32NextTargetValue[u8ModuleIdx][u8ChannelIdx] != 0x0U)
        {
            Gpt_Stm_u32TargetValue[u8ModuleIdx][u8ChannelIdx] = Gpt_Stm_u32NextTargetValue[u8ModuleIdx][u8ChannelIdx];
            Gpt_Stm_u32NextTargetValue[u8ModuleIdx][u8ChannelIdx] = 0x0U;
        }
#endif
        /*read the current target time value*/
        u32TargetTime = Gpt_Stm_u32TargetValue[STM_MODULE_INDEX_U32((uint32)u8HwChannel)][STM_CHANNEL_INDEX_U32((uint32)u8HwChannel)];

        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_WRITE32((STM_CMP_ADDR32((uint32)u8HwChannel)), ((uint32)(u32OldCompare + u32TargetTime)));

        /* Call GPT upper layer handler */
        Gpt_Ipw_ProcessCommonInterrupt(u8ChannelIdx,(uint8)GPT_STM_MODULE + ((uint8)GPT_STM_CHANNELS_PER_MODULE_U8 * u8ModuleIdx));
        /* (uint8)GptStmChannelsPos[u8ModuleIdx]); */

    }/*Check spurious interrupt*/
    
    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_00();
    {
        /*Clear interrupt status flag*/
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_00();
}
#endif

/*==================================================================================================
*                                       GLOBAL FUNCTIONS
==================================================================================================*/
#ifdef MCAL_STM_REG_PROT_AVAILABLE
/**
* @brief        Enables STM registers writing in User Mode by configuring REG_PROT
* @details      Sets the UAA (User Access Allowed) bit of the STM IP allowing STM registers writing in User Mode
*
* @param[in]    none
*
* @return       none
*
* @pre          Should be executed in supervisor mode
* @post         none
*/
/** @violates @ref GPT_STM_C_REF_3 MISRA 2012 Advisory Rule 8.7, Functions and objects should not be defined with 
*   external linkage if they are referenced in only one translation unit.*/
FUNC( void, GPT_CODE) Gpt_Stm_SetUserAccessAllowed (VAR(uint32, AUTOMATIC) StmBaseAddr)
{
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    SET_USER_ACCESS_ALLOWED(StmBaseAddr, STM_PROT_MEM_U32);
}
#endif /* MCAL_STM_REG_PROT_AVAILABLE */
/*================================================================================================*/
/**
* @brief   Gpt driver initialization function for Stm module.
* @details This function is called separately for each STM hw channel corresponding to the configured
*          timer channels, and:
*          - sets the prescaler value
*          - configures the freeze mode (enabled/disabled)
*          - enables the STM counter
*          - disables the STM channel
*          - clears the (pending) interrupt flag corresponding to Stm channel
*          - clears the compare register corresponding to the Stm channel.
*
* @param[in]     u8HwChannel            Stm hw channel ID
* @param[in]     u8Prescaler            STM prescaler value
* @param[in]     bFreezeEnable          indicates if the Freeze mode is enabled
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_Init
(
    VAR(uint8, AUTOMATIC) u8HwChannel,
    VAR(uint8, AUTOMATIC) u8Prescaler,
#if (GPT_STM_ENABLECLOCKSWITCH == STD_ON)
    VAR(uint8, AUTOMATIC) u8ClockSource,
#endif
    VAR(boolean, AUTOMATIC) bFreezeEnable
)
{
     /** @violates @ref GPT_STM_C_REF_8 MISRA 2012 Advisory Rule 12.3, The comma operator should not be used.*/   
    /* Enable register access from user mode, if enabled from configuration file */ 
    Call_Gpt_Stm_SetUserAccessAllowed((uint32)STM_BASE_ADDR32[STM_MODULE_INDEX_U32((uint32)u8HwChannel)]);
    
    /* Timer Counter is enabled */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_SET32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_TEN_MASK_U32);

    /* STM channel disabled */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(STM_CCR_ADDR32((uint32)u8HwChannel), STM_CCR_CEN_MASK_U32);

    /* Clear interrupt request */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_SET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32);

    /* Set Compare Value to 0 */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_WRITE32(STM_CMP_ADDR32((uint32)u8HwChannel), (uint32)0U);
    
    /* Select Clock Source */
#if (GPT_STM_ENABLECLOCKSWITCH == STD_ON)
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_RMW32(STM_CR_ADDR32(u8HwChannel), STM_CR_CSL_MASK_U32, (uint32)u8ClockSource << STM_CR_CSL_SHIFT);
#endif
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    REG_RMW32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_CPS_MASK_U32, ((uint32)u8Prescaler << STM_CR_CPS_SHIFT));
    
    /* Check freeze enable*/
    if ((boolean)TRUE == bFreezeEnable)
    {
        /* Allow timer to be stopped when the device enters debug mode */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_FRZ_MASK_U32);
    }
    else
    {
        /* Stm counter continues to run in debug mode */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_FRZ_MASK_U32);
    }    
    /* Set the corresponding bit with STM module mark this module is used for general GPT channel */
    
    Gpt_Stm_u8UsedForGeneralGptChannel |= (uint8)((uint8)1 << STM_MODULE_INDEX_U32((uint32)u8HwChannel));

    Gpt_Stm_u32TargetValue[STM_MODULE_INDEX_U32((uint32)u8HwChannel)][STM_CHANNEL_INDEX_U32((uint32)u8HwChannel)] = 0U;

    return;
}
/*================================================================================================*/
#if (GPT_DEINIT_API == STD_ON)
/**
* @brief   Gpt driver de-initialization function for Stm module.
* @details This function is called separately for each STM hw channel corresponding to the configured
*          timer channels, and:
*          - disables the STM counter
*          - resets the prescaler bits in the control register
*          - disables the STM channel
*          - clears the (pending) interrupt flag corresponding to Stm channel
*          - clears the compare register corresponding to the Stm channel.
*
* @param[in]     u8HwChannel        Stm hw channel ID
*
* @pre     On/Off by the configuration parameter: GPT_DEINIT_API
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_DeInit(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    /* Timer Counter is disabled */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_TEN_MASK_U32);
    
    /* Disable channel configured */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(STM_CCR_ADDR32((uint32)u8HwChannel), STM_CCR_CEN_MASK_U32);
    
    /* Clear Interrupt Flag */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_SET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32);
    
    /* Set Compare Value to 0 */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_WRITE32(STM_CMP_ADDR32((uint32)u8HwChannel), (uint32)0U);
    
    /* Reset Prescaler */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    REG_RMW32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_CPS_MASK_U32, (uint32)0UL);

    Gpt_Stm_u32TargetValue[STM_MODULE_INDEX_U32((uint32)u8HwChannel)][STM_CHANNEL_INDEX_U32((uint32)u8HwChannel)] = 0U;
    
    /* Clear the corresponding bit with STM module */
    
    Gpt_Stm_u8UsedForGeneralGptChannel &= (uint8)(~((uint8)1 << STM_MODULE_INDEX_U32((uint32)u8HwChannel)));
    
    return;
}
#endif

/*================================================================================================*/
/**
* @brief   Gpt driver function for starting the Stm timer channel.
* @details This function:
*          - reads the current counter register value and sets the compare register to the sum of
*            counter register value plus the timeout value
*          - enables the STM channel
*
* @param[in]     u8HwChannel        Stm hw channel ID
* @param[in]     u32Value          channel timeout value
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_StartTimer(VAR(uint8, AUTOMATIC) u8HwChannel, VAR(uint32, AUTOMATIC) u32Value)
{
    VAR(uint32, AUTOMATIC) u32CounterValue;
    
    /* To update accurate value for STM_CMP_ADDR32, interrupts is suspended*/
    SuspendAllInterrupts();
    
    /* Configure channel compare register */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32CounterValue = REG_READ32(STM_CNT_ADDR32((uint32)u8HwChannel));
    
    /* Add period timer for the next cycle */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_WRITE32(STM_CMP_ADDR32((uint32)u8HwChannel), ((uint32)(u32CounterValue + u32Value)));
    
    ResumeAllInterrupts();
    
    /*Store the target time value as a memory copy*/
    Gpt_Stm_u32TargetValue[STM_MODULE_INDEX_U32((uint32)u8HwChannel)][STM_CHANNEL_INDEX_U32((uint32)u8HwChannel)] = u32Value;

    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_01();
    {
        /* Enable hardware channel */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(STM_CCR_ADDR32((uint32)u8HwChannel), STM_CCR_CEN_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_01();
    /* For STM, there is no need to enable the corresponding timer channel IRQ, as there is no HW
       support for enabling/disabling the STM IRQ */

    return;
}

/*================================================================================================*/
/**
* @brief   Gpt driver function for stopping the Stm timer channel.
* @details This function:
*          - disables the STM channel
*          - clears the (pending) interrupt flag corresponding to Stm channel
*
* @param[in]     u8HwChannel        Stm hw channel ID
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_StopTimer(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_02();
    {
        /* Disable hardware channel */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(STM_CCR_ADDR32((uint32)u8HwChannel), STM_CCR_CEN_MASK_U32);

        /* Clear interrupt status flag */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_02();

    return;
}

/*================================================================================================*/
/**
* @brief   Gpt driver function for getting the time elapsed for an Stm timer channel.
* @details This function:
*          - reads the STM channel compare register
*          - reads the STM counter register
*          - depending on above and on channel timeout value it calculates and returns the elapsed
*            time
*
* @param[in]     u8HwChannel                Stm hw channel ID
* @param[out]    pbReturnChannelRollover    Interrupt status flag representing the timer roll-over
* @param[out]    pu32TargetValue            current target time value
*
*/
FUNC(uint32, GPT_CODE) Gpt_Stm_GetTimeElapsed
(
    VAR(uint8, AUTOMATIC) u8HwChannel,
    P2VAR(boolean, AUTOMATIC, GPT_APPL_DATA) pbReturnChannelRollover,
    P2VAR(uint32, AUTOMATIC, GPT_APPL_DATA) pu32TargetValue
)
{
    VAR(uint32, AUTOMATIC) u32ReturnValue;
    VAR(uint32, AUTOMATIC) u32CompareValue;
    VAR(uint32, AUTOMATIC) u32CounterValue;
    VAR(uint32, AUTOMATIC) u32TempValue;

    *pu32TargetValue = Gpt_Stm_u32TargetValue[STM_MODULE_INDEX_U32((uint32)u8HwChannel)][STM_CHANNEL_INDEX_U32((uint32)u8HwChannel)];

    /* Read compare and counter registers */
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32CounterValue = REG_READ32(STM_CNT_ADDR32((uint32)u8HwChannel));
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32CompareValue = REG_READ32(STM_CMP_ADDR32((uint32)u8HwChannel));

    /* Calculate the elapsed time */
    if (u32CounterValue >= u32CompareValue)
    {
        u32TempValue = ((STM_CNT_MAX_VALUE_U32 - u32CounterValue) + u32CompareValue) + STM_OVERFLOW_PAD_U32;
    }
    else
    {
        u32TempValue = u32CompareValue - u32CounterValue;
    }

    if (u32TempValue > *pu32TargetValue)
    {
        u32ReturnValue = *pu32TargetValue;
    }
    else
    {
         u32ReturnValue = *pu32TargetValue - u32TempValue;
    }

    /*Check interrupt status flag*/
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    if (STM_CIR_CIF_SET_U32 == REG_BIT_GET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32))
    {
        /* Channel counter was rollover */
        *pbReturnChannelRollover = (boolean)TRUE;
    }
    else
    {
        /* Channel counter was not rollover */
        *pbReturnChannelRollover = (boolean)FALSE;
    }
    return(u32ReturnValue);
}

#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
/*================================================================================================*/
/**
* @brief      The function changes the Stm compare register value.
* @details This function:
*          - Write next timeout to local variable
*
* @param[in]     u8HwChannel        Stm hw channel ID
* @param[in]     u32Value           Channel timeout value
* @implements    Gpt_Stm_ChangeNextTimeoutValue_Activity
*/

FUNC(void, GPT_CODE) Gpt_Stm_ChangeNextTimeoutValue(VAR(uint8, AUTOMATIC) u8HwChannel, VAR(uint32, AUTOMATIC) u32Value)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)STM_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)STM_CHANNEL_INDEX_U32(u8HwChannel);

    /* Update the target time value to be used on next cycle */
    Gpt_Stm_u32NextTargetValue[u8ModuleIdx][u8ChannelIdx] = u32Value;
}
#endif /* GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON */

#if (GPT_SET_CLOCK_MODE == STD_ON)
/*================================================================================================*/
/**
* @brief      The function changes the STM prescaler value.
* @details    This function sets the STM prescaler based on the input mode.
*
* @param[in]  u8hwChannel      hardware channel
* @param[in]  u8chPrescale     prescaler value
*
* @pre     On/Off by the configuration parameter: GPT_DUAL_CLOCK_MODE
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_SetClockMode(VAR(uint8, AUTOMATIC) u8hwChannel, VAR(uint8, AUTOMATIC) u8chPrescale)
{
    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_03();
    {
        /* Set clock mode */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_RMW32(STM_CR_ADDR32(u8hwChannel), STM_CR_CPS_MASK_U32, ((uint32)u8chPrescale << STM_CR_CPS_SHIFT));
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_03();
}
#endif

#if(GPT_PREDEFTIMER_FUNCTIONALITY_API == STD_ON)
/*================================================================================================*/
/**
* @brief      The function start the STM channel.
* @details    This function start the STM channel the input mode.
*
* @param[in]  u8hwChannel      hardware channel
* @param[in]  u8Prescaler      prescaler value
* @param[in]  bFreezeEnable    Freeze value
* @param[in]  u8ClockSource    clock source
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_StartPredefTimer 
(
    VAR(uint8, AUTOMATIC) u8HwChannel,
    VAR(uint8, AUTOMATIC) u8Prescaler,
#if (GPT_STM_ENABLECLOCKSWITCH == STD_ON)
    VAR(uint8, AUTOMATIC) u8ClockSource,
#endif
    VAR(boolean, AUTOMATIC) bFreezeEnable    
)
{ 
    /** @violates @ref GPT_STM_C_REF_8 MISRA 2012 Advisory Rule 12.3, The comma operator should not be used.*/   
    /* Enable register access from user mode, if enabled from configuration file */ 
    Call_Gpt_Stm_SetUserAccessAllowed((uint32)STM_BASE_ADDR32[STM_MODULE_INDEX_U32((uint32)u8HwChannel)]);
    
    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    if(((uint32)STM_CR_TEN_MASK_U32) != (REG_READ32(STM_CR_ADDR32(u8HwChannel)) & STM_CR_TEN_MASK_U32))
    {
        /* clear counter */
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_WRITE32(STM_CNT_ADDR32((uint32)u8HwChannel), (uint32)0UL);

        SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_04();
        {
            /* Set prescaler for stm timer */
            /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
            *   of any register by using the hardware offset of the controller.*/
            /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
            *   memory mapped registers.*/
            /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
            *   memory mapped registers.*/
            REG_RMW32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_CPS_MASK_U32, ((uint32)u8Prescaler << STM_CR_CPS_SHIFT));
            
            if ((boolean)TRUE == bFreezeEnable)
            {
                /* Allow timer to be stopped when the device enters debug mode */
                /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
                *   of any register by using the hardware offset of the controller.*/
                /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
                *   memory mapped registers.*/
                /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
                *   memory mapped registers.*/
                REG_BIT_SET32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_FRZ_MASK_U32);
            }
            else
            {
                /* Stm counter continues to run in debug mode */
                /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
                *   of any register by using the hardware offset of the controller.*/
                /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
                *   memory mapped registers.*/
                /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
                *   memory mapped registers.*/
                REG_BIT_CLEAR32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_FRZ_MASK_U32);
            }
            
            /* Timer Counter is enabled */
            /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
            *   of any register by using the hardware offset of the controller.*/
            /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
            *   memory mapped registers.*/
            /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
            *   memory mapped registers.*/
            REG_BIT_SET32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_TEN_MASK_U32);
        }
        SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_04();
    }
}
/*================================================================================================*/
/**
* @brief      The function get time elapsed of the STM channel.
* @details    This function get time elapsed of the STM channel.
*
* @param[in]  u8hwChannel      hardware channel
* @param[in]  ePredefTimerType  Types of predef timer
*
*/
FUNC(uint32, GPT_CODE) Gpt_Stm_GetPredefTimerValue 
(
    VAR(uint8, AUTOMATIC) u8HwChannel,
    VAR(Gpt_PredefTimerType, AUTOMATIC) ePredefTimerType
)
{
    VAR(uint32, AUTOMATIC) u32ReturnValue;

    /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32ReturnValue = REG_READ32(STM_CNT_ADDR32((uint32)u8HwChannel));
    
    switch(ePredefTimerType)
    {
        case GPT_PREDEF_TIMER_1US_16BIT:
            u32ReturnValue = (0x0000FFFFU & u32ReturnValue);
        break;
        case GPT_PREDEF_TIMER_1US_24BIT:
            u32ReturnValue = (0x00FFFFFFU & u32ReturnValue);
        break;
        case GPT_PREDEF_TIMER_1US_32BIT:
        case GPT_PREDEF_TIMER_100US_32BIT:
        break;
        default:
            /* 32bit timer */
        break;
    } 
    
    return  u32ReturnValue;
}
/*================================================================================================*/
/**
* @brief      The function stop the STM channel.
* @details    This function stop the STM channel.
*
* @param[in]  u8hwChannel      hardware channel
*
*/
FUNC(void, GPT_CODE) Gpt_Stm_StopPredefTimer (VAR(uint8, AUTOMATIC) u8HwChannel)
{
    
    /* Only stop the STM module if it is not used for any general GPT channel */
    
    if(0U == (Gpt_Stm_u8UsedForGeneralGptChannel & ((uint8)1 << STM_MODULE_INDEX_U32((uint32)u8HwChannel))))
    {
        SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_05();
        {
            /* Timer Counter is disabled */
            /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
            *   of any register by using the hardware offset of the controller.*/
            /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
            *   memory mapped registers.*/
            /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
            *   memory mapped registers.*/
            REG_BIT_CLEAR32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_TEN_MASK_U32);

            /* clear counter */
            /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
            *   of any register by using the hardware offset of the controller.*/
            /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
            *   memory mapped registers.*/
            /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
            *   memory mapped registers.*/
            REG_WRITE32(STM_CNT_ADDR32((uint32)u8HwChannel), (uint32)0UL);

            /* Reset Pre-scaler */
            /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
            *   of any register by using the hardware offset of the controller.*/
            /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
            *   memory mapped registers.*/
            /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
            *   memory mapped registers.*/
            REG_RMW32(STM_CR_ADDR32((uint32)u8HwChannel), STM_CR_CPS_MASK_U32, (uint32)0UL);
        }
        SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_05();
    }

}
#endif

#if (GPT_STM_MODULE_SINGLE_INTERRUPT == STD_ON)
#ifdef GPT_STM_0_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_0 module.
*
* @isr
*/
ISR(Gpt_STM_0_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 0U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_0_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint32)(((uint32)u8ModuleIdx << STM_MOD_SHIFT)) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx<<STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_1_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_1 module.
*
* @isr
*/
ISR(Gpt_STM_1_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 1U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_1_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint32)((uint32)(u8ModuleIdx) << STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_2_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_2 module.
*
* @isr
*/
ISR(Gpt_STM_2_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 2U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_2_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_3_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_3 module.
*
* @isr
*/
ISR(Gpt_STM_3_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 3U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_3_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_4_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_4 module.
*
* @isr
*/
ISR(Gpt_STM_4_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 4U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_4_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint8)(u8ModuleIdx<<STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_5_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_5 module.
*
* @isr
*/
ISR(Gpt_STM_5_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 5U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_5_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_6_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_6 module.
*
* @isr
*/
ISR(Gpt_STM_6_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 6U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_6_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#ifdef GPT_STM_7_ISR_USED
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to common Gpt_STM_7 module.
*
* @isr
*/
ISR(Gpt_STM_7_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx = 7U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < (uint8)GPT_STM_7_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp = REG_BIT_GET32(STM_CIR_ADDR32((uint32)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx)), STM_CIR_CIF_MASK_U32);

        if (STM_CIR_CIF_SET_U32 == u32Temp)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << STM_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#else

#ifdef GPT_STM_0_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_0_Ch_0 hw channel.
*
* @isr
*
* @violates @ref GPT_STM_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*/
ISR(Gpt_STM_0_Ch_0_ISR)
{

    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_0_CH_0);

/** @violates @ref GPT_STM_C_REF_9 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_0_CH_0_ISR_USED */

#if((defined GPT_STM_0_CH_1_ISR_USED) || (defined GPT_STM_ISR_1_SHARED))
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_0_Ch_1 hw channel (or for shared ISR).
*
* @isr
*
* @violates @ref GPT_STM_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*
* @note    On some platforms there is only one interrupt line shared for channels 1, 2 and 3.
*/
ISR(Gpt_STM_0_Ch_1_ISR)
{
#ifndef GPT_STM_ISR_1_SHARED
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_0_CH_1);
#else
    VAR(uint8,  AUTOMATIC) u8HwChannel = 0U;
    VAR(uint32, AUTOMATIC) u32Temp1 = 0U;

    for(u8HwChannel = STM_0_CH_1; u8HwChannel <= STM_0_CH_3; u8HwChannel++)
    {
         /** @violates @ref GPT_STM_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_STM_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_STM_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/        
        u32Temp1 = REG_BIT_GET32(STM_CIR_ADDR32((uint32)u8HwChannel), STM_CIR_CIF_MASK_U32);
        if (STM_CIR_CIF_SET_U32 == u32Temp1)
        {
            Gpt_Stm_ProcessCommonInterrupt((uint8)u8HwChannel);
        }
    }
#endif

/** @violates @ref GPT_STM_C_REF_9 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_0_CH_1_ISR_USED */

#ifndef GPT_STM_ISR_1_SHARED
#ifdef GPT_STM_0_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_0_Ch_2 hw channel.
*
*
* @isr
*/
ISR(Gpt_STM_0_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_0_CH_2);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_0_CH_2_ISR_USED */

#ifdef GPT_STM_0_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_0_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_0_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_0_CH_3);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_0_CH_3_ISR_USED */
#endif /* GPT_STM_ISR_1_SHARED */

#ifdef GPT_STM_1_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_1_Ch_0 hw channel.
*
* @isr
*/
ISR(Gpt_STM_1_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_1_CH_0);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_1_CH_0_ISR_USED */

#ifdef GPT_STM_1_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_1_Ch_1 hw channel (or for shared ISR).
*
* @isr
*
* @note    On some platforms there is only one interrupt line shared for channels 1, 2 and 3.
*/
ISR(Gpt_STM_1_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_1_CH_1);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_1_CH_1_ISR_USED */

#ifdef GPT_STM_1_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_1_Ch_2 hw channel.
*
*
* @isr
*/
ISR(Gpt_STM_1_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_1_CH_2);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_1_CH_2_ISR_USED */

#ifdef GPT_STM_1_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_1_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_1_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_1_CH_3);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_1_CH_3_ISR_USED */

#ifdef GPT_STM_2_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_0 hw channel.
*
* @isr
*/
ISR(Gpt_STM_2_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_2_CH_0);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_2_CH_0_ISR_USED */

#ifdef GPT_STM_2_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_1 hw channel (or for shared ISR).
*
* @isr
*
* @note    On some platforms there is only one interrupt line shared for channels 1, 2 and 3.
*/
ISR(Gpt_STM_2_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_2_CH_1);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_2_CH_1_ISR_USED */

#ifdef GPT_STM_2_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_2 hw channel.
*
*
* @isr
*/
ISR(Gpt_STM_2_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_2_CH_2);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_2_CH_2_ISR_USED */

#ifdef GPT_STM_2_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_2_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_2_CH_3);
    
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_2_CH_3_ISR_USED */

#ifdef GPT_STM_3_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_3_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_3_CH_0);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_3_CH_0_ISR_USED */

#ifdef GPT_STM_3_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_3_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_3_CH_1);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_3_CH_1_ISR_USED */

#ifdef GPT_STM_3_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_3_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_3_CH_2);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_3_CH_2_ISR_USED */

#ifdef GPT_STM_3_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_3_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_3_CH_3);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_3_CH_3_ISR_USED */

#ifdef GPT_STM_4_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_4_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_4_CH_0);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_4_CH_0_ISR_USED */

#ifdef GPT_STM_4_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_4_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_4_CH_1);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_4_CH_1_ISR_USED */

#ifdef GPT_STM_4_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_4_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_4_CH_2);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_4_CH_2_ISR_USED */

#ifdef GPT_STM_4_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_4_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_4_CH_3);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_4_CH_3_ISR_USED */

#ifdef GPT_STM_5_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_5_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_5_CH_0);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_5_CH_0_ISR_USED */

#ifdef GPT_STM_5_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_5_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_5_CH_1);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_5_CH_1_ISR_USED */

#ifdef GPT_STM_5_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_5_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_5_CH_2);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_5_CH_2_ISR_USED */

#ifdef GPT_STM_5_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_5_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_5_CH_3);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_5_CH_3_ISR_USED */

#ifdef GPT_STM_6_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_6_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_6_CH_0);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_6_CH_0_ISR_USED */

#ifdef GPT_STM_6_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_6_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_6_CH_1);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_6_CH_1_ISR_USED */

#ifdef GPT_STM_6_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_6_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_6_CH_2);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_6_CH_2_ISR_USED */

#ifdef GPT_STM_6_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_6_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_6_CH_3);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_6_CH_3_ISR_USED */

#ifdef GPT_STM_7_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_7_Ch_0_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_7_CH_0);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_7_CH_0_ISR_USED */

#ifdef GPT_STM_7_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_7_Ch_1_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_7_CH_1);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_7_CH_1_ISR_USED */

#ifdef GPT_STM_7_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_7_Ch_2_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_7_CH_2);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_7_CH_2_ISR_USED */

#ifdef GPT_STM_7_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for STM channels.
* @details Interrupt Service Routine corresponding to Gpt_STM_2_Ch_3 hw channel.
*
* @isr
*/
ISR(Gpt_STM_7_Ch_3_ISR)
{
    Gpt_Stm_ProcessCommonInterrupt((uint8)STM_7_CH_3);
    EXIT_INTERRUPT();
}
#endif /* GPT_STM_7_CH_3_ISR_USED */

#endif /*GPT_STM_MODULE_SINGLE_INTERRUPT == STD_ON*/

#define GPT_STOP_SEC_CODE
/** @violates @ref GPT_STM_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_STM_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#endif /*GPT_STM_USED == STD_ON */

#ifdef __cplusplus
}
#endif

/** @} */
