#####################  mpc5775e_mapbga416 Adc module  ##########################
# Adc.AdcConfigSet.AdcHwUnit.AdcHwUnitId: List of SAR/SD ADC Hw Units
# Adc.AdcConfigSet.AdcHwUnit0.AdcChannel.AdcChannelId : List of Adc Physical Channels for SAR ADC HW Unit 0
# Adc.AdcConfigSet.AdcHwUnit1.AdcChannel.AdcChannelId : List of Adc Physical Channels for SAR ADC HW Unit 1
# Adc.AdcConfigSet.AdcHwUnit2.AdcChannel.AdcChannelId : List of Adc Physical Channels for SAR ADC HW Unit 2
# Adc.AdcConfigSet.AdcHwUnit3.AdcChannel.AdcChannelId : List of Adc Physical Channels for SAR ADC HW Unit 3
# Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo0.AdcHwTrigSrc: List of hardware trigger source channels for FIFO0
# Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo1.AdcHwTrigSrc: List of hardware trigger source channels for FIFO1
# Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo2.AdcHwTrigSrc: List of hardware trigger source channels for FIFO2
# Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo3.AdcHwTrigSrc: List of hardware trigger source channels for FIFO3
# Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo4.AdcHwTrigSrc: List of hardware trigger source channels for FIFO4
# Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo5.AdcHwTrigSrc: List of hardware trigger source channels for FIFO5
# Adc.AdcConfigSet.AdcHwUnit : Number of ADC HW Unit
# Adc.AdcConfigSet.MaxEqadc : Number of EQADC
# Adc.AdcConfigSet.MaxFifo : Number of FIFO per EQADC
# AdcDMAPresent : DMA Present
################################################################################
Adc.AdcConfigSet.AdcHwUnit.AdcHwUnitId:ADC0,ADC1,ADC2,ADC3
Adc.AdcConfigSet.AdcHwUnit.AdcChannel.AdcChannelId:AN_0,AN_1,AN_2,AN_3,AN_4,AN_5,AN_6,AN_7,AN_8,AN_9,AN_10,AN_11,AN_12,AN_13,AN_14,AN_15,AN_16,AN_17,AN_18,AN_19,AN_20,AN_21,AN_22,AN_23,AN_24,AN_25,AN_26,AN_27,AN_28,AN_29,AN_30,AN_31,AN_32,AN_33,AN_34,AN_35,AN_36,AN_37,AN_38,AN_39,AN_40,AN_41,AN_42,AN_43,AN_44,AN_45,AN_64,AN_65,AN_66,AN_67,AN_68,AN_69,AN_70,AN_71,AN_72,AN_73,AN_74,AN_75,AN_76,AN_77,AN_78,AN_79,AN_80,AN_81,AN_82,AN_83,AN_84,AN_85,AN_86,AN_87,AN_88,AN_89,AN_90,AN_91,AN_92,AN_93,AN_94,AN_95,AN_96,AN_97,AN_98,AN_99,AN_128,AN_129,AN_130,AN_131,AN_132,AN_133,AN_145,AN_224,AN_225,AN_226,AN_227,AN_228,AN_229,AN_230,AN_231,AN_232,AN_233,AN_234,AN_235,AN_236,AN_237,AN_238,AN_239,AN_240,AN_241,AN_242,AN_243,AN_244,AN_245,AN_246,AN_247,AN_248,AN_249,AN_250,AN_251,AN_252,AN_253,AN_254,AN_255
Adc.AdcConfigSet.AdcHwUnit0.AdcChannel.AdcChannelId:AN_0,AN_1,AN_2,AN_3,AN_4,AN_5,AN_6,AN_7,AN_8,AN_9,AN_10,AN_11,AN_12,AN_13,AN_14,AN_15,AN_16,AN_17,AN_18,AN_19,AN_20,AN_21,AN_22,AN_23,AN_24,AN_25,AN_26,AN_27,AN_28,AN_29,AN_30,AN_31,AN_32,AN_33,AN_34,AN_35,AN_36,AN_37,AN_38,AN_39,AN_40,AN_41,AN_42,AN_43,AN_44,AN_45,AN_64,AN_65,AN_66,AN_67,AN_68,AN_69,AN_70,AN_71,AN_72,AN_73,AN_74,AN_75,AN_76,AN_77,AN_78,AN_79,AN_80,AN_81,AN_82,AN_83,AN_84,AN_85,AN_86,AN_87,AN_88,AN_89,AN_90,AN_91,AN_92,AN_93,AN_94,AN_95,AN_96,AN_97,AN_98,AN_99,AN_128,AN_129,AN_145,AN_224,AN_225,AN_226,AN_227,AN_228,AN_229,AN_230,AN_231,AN_232,AN_233,AN_234,AN_235,AN_236,AN_237,AN_238,AN_239,AN_240,AN_241,AN_242,AN_243,AN_244,AN_245,AN_246,AN_247,AN_248,AN_249,AN_250,AN_251,AN_252,AN_253,AN_254,AN_255
Adc.AdcConfigSet.AdcHwUnit1.AdcChannel.AdcChannelId:AN_0,AN_1,AN_2,AN_3,AN_4,AN_5,AN_6,AN_7,AN_8,AN_9,AN_10,AN_11,AN_12,AN_13,AN_14,AN_15,AN_16,AN_17,AN_18,AN_19,AN_20,AN_21,AN_22,AN_23,AN_24,AN_25,AN_26,AN_27,AN_28,AN_29,AN_30,AN_31,AN_32,AN_33,AN_34,AN_35,AN_36,AN_37,AN_38,AN_39,AN_40,AN_41,AN_42,AN_43,AN_44,AN_45,AN_64,AN_65,AN_66,AN_67,AN_68,AN_69,AN_70,AN_71,AN_72,AN_73,AN_74,AN_75,AN_76,AN_77,AN_78,AN_79,AN_80,AN_81,AN_82,AN_83,AN_84,AN_85,AN_86,AN_87,AN_88,AN_89,AN_90,AN_91,AN_92,AN_93,AN_94,AN_95,AN_96,AN_97,AN_98,AN_99,AN_128,AN_129,AN_224,AN_225,AN_226,AN_227,AN_228,AN_229,AN_230,AN_231,AN_232,AN_233,AN_234,AN_235,AN_236,AN_237,AN_238,AN_239,AN_240,AN_241,AN_242,AN_243,AN_244,AN_245,AN_246,AN_247,AN_248,AN_249,AN_250,AN_251,AN_252,AN_253,AN_254,AN_255
Adc.AdcConfigSet.AdcHwUnit2.AdcChannel.AdcChannelId:AN_0,AN_1,AN_2,AN_3,AN_4,AN_5,AN_6,AN_7,AN_8,AN_9,AN_10,AN_11,AN_12,AN_13,AN_14,AN_15,AN_16,AN_17,AN_18,AN_19,AN_20,AN_21,AN_22,AN_23,AN_24,AN_25,AN_26,AN_27,AN_28,AN_29,AN_30,AN_31,AN_32,AN_33,AN_34,AN_35,AN_36,AN_37,AN_38,AN_39,AN_40,AN_41,AN_42,AN_43,AN_44,AN_64,AN_65,AN_66,AN_67,AN_68,AN_69,AN_70,AN_71,AN_72,AN_73,AN_74,AN_75,AN_76,AN_77,AN_78,AN_79,AN_80,AN_81,AN_82,AN_83,AN_84,AN_85,AN_86,AN_87,AN_88,AN_89,AN_90,AN_91,AN_92,AN_93,AN_94,AN_95,AN_96,AN_97,AN_98,AN_99,AN_128,AN_129,AN_130,AN_131,AN_132,AN_133,AN_224,AN_225,AN_226,AN_227,AN_228,AN_229,AN_230,AN_231,AN_232,AN_233,AN_234,AN_235,AN_236,AN_237,AN_238,AN_239,AN_240,AN_241,AN_242,AN_243,AN_244,AN_245,AN_246,AN_247,AN_248,AN_249,AN_250,AN_251,AN_252,AN_253,AN_254,AN_255
Adc.AdcConfigSet.AdcHwUnit3.AdcChannel.AdcChannelId:AN_0,AN_1,AN_2,AN_3,AN_4,AN_5,AN_6,AN_7,AN_8,AN_9,AN_10,AN_11,AN_12,AN_13,AN_14,AN_15,AN_16,AN_17,AN_18,AN_19,AN_20,AN_21,AN_22,AN_23,AN_24,AN_25,AN_26,AN_27,AN_28,AN_29,AN_30,AN_31,AN_32,AN_33,AN_34,AN_35,AN_36,AN_37,AN_38,AN_39,AN_40,AN_41,AN_42,AN_43,AN_44,AN_64,AN_65,AN_66,AN_67,AN_68,AN_69,AN_70,AN_71,AN_72,AN_73,AN_74,AN_75,AN_76,AN_77,AN_78,AN_79,AN_80,AN_81,AN_82,AN_83,AN_84,AN_85,AN_86,AN_87,AN_88,AN_89,AN_90,AN_91,AN_92,AN_93,AN_94,AN_95,AN_96,AN_97,AN_98,AN_99,AN_128,AN_129,AN_130,AN_131,AN_132,AN_133,AN_224,AN_225,AN_226,AN_227,AN_228,AN_229,AN_230,AN_231,AN_232,AN_233,AN_234,AN_235,AN_236,AN_237,AN_238,AN_239,AN_240,AN_241,AN_242,AN_243,AN_244,AN_245,AN_246,AN_247,AN_248,AN_249,AN_250,AN_251,AN_252,AN_253,AN_254,AN_255
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo.AdcHwTrigSrc:FIFO0_RTI,FIFO0_PIT0,FIFO0_PIT1,FIFO0_PIT2,FIFO0_PIT3,FIFO0_ETRIG1,FIFO0_eTPUA28,FIFO0_eTPUA29,FIFO0_eTPUA30,FIFO0_eTPUA31,FIFO0_eTPUB28,FIFO0_eTPUB29,FIFO0_eTPUB30,FIFO0_eTPUB31,FIFO0_eTPUC28,FIFO0_eTPUC29,FIFO0_eTPUC30,FIFO0_eTPUC31,FIFO0_eMIOS0_16,FIFO0_eMIOS0_17,FIFO0_eMIOS0_18,FIFO0_eMIOS0_19,FIFO0_eMIOS0_20,FIFO0_eMIOS0_21,FIFO0_eMIOS0_22,FIFO0_eMIOS0_23,FIFO0_eMIOS1_2,FIFO0_ETRIG0,FIFO1_RTI,FIFO1_PIT0,FIFO1_PIT1,FIFO1_PIT2,FIFO1_PIT3,FIFO1_eTPUA7,FIFO1_ETRIG0,FIFO1_eTPUA28,FIFO1_eTPUA29,FIFO1_eTPUA30,FIFO1_eTPUA31,FIFO1_eTPUB28,FIFO1_eTPUB29,FIFO1_eTPUB30,FIFO1_eTPUB31,FIFO1_eTPUC28,FIFO1_eTPUC29,FIFO1_eTPUC30,FIFO1_eTPUC31,FIFO1_eMIOS0_16,FIFO1_eMIOS0_17,FIFO1_eMIOS0_18,FIFO1_eMIOS0_19,FIFO1_eMIOS0_20,FIFO1_eMIOS0_21,FIFO1_eMIOS0_22,FIFO1_eMIOS0_23,FIFO1_eMIOS1_3,FIFO1_ETRIG1,FIFO2_RTI,FIFO2_PIT0,FIFO2_PIT1,FIFO2_PIT2,FIFO2_PIT3,FIFO2_eTPUA14,FIFO2_ETRIG1,FIFO2_eTPUA28,FIFO2_eTPUA29,FIFO2_eTPUA30,FIFO2_eTPUA31,FIFO2_eTPUB28,FIFO2_eTPUB29,FIFO2_eTPUB30,FIFO2_eTPUB31,FIFO2_eTPUC28,FIFO2_eTPUC29,FIFO2_eTPUC30,FIFO2_eTPUC31,FIFO2_eMIOS0_16,FIFO2_eMIOS0_17,FIFO2_eMIOS0_18,FIFO2_eMIOS0_19,FIFO2_eMIOS0_20,FIFO2_eMIOS0_21,FIFO2_eMIOS0_22,FIFO2_eMIOS0_23,FIFO2_eMIOS1_7,FIFO2_ETRIG0,FIFO3_RTI,FIFO3_PIT0,FIFO3_PIT1,FIFO3_PIT2,FIFO3_PIT3,FIFO3_eTPUA22,FIFO3_ETRIG0,FIFO3_eTPUA28,FIFO3_eTPUA29,FIFO3_eTPUA30,FIFO3_eTPUA31,FIFO3_eTPUB28,FIFO3_eTPUB29,FIFO3_eTPUB30,FIFO3_eTPUB31,FIFO3_eTPUC28,FIFO3_eTPUC29,FIFO3_eTPUC30,FIFO3_eTPUC31,FIFO3_eMIOS0_16,FIFO3_eMIOS0_17,FIFO3_eMIOS0_18,FIFO3_eMIOS0_19,FIFO3_eMIOS0_20,FIFO3_eMIOS0_21,FIFO3_eMIOS0_22,FIFO3_eMIOS0_23,FIFO3_eMIOS1_6,FIFO3_ETRIG1,FIFO4_RTI,FIFO4_PIT0,FIFO4_PIT1,FIFO4_PIT2,FIFO4_PIT3,FIFO4_eTPUA30,FIFO4_ETRIG1,FIFO4_eTPUA28,FIFO4_eTPUA29,FIFO4_eTPUA31,FIFO4_eTPUB28,FIFO4_eTPUB29,FIFO4_eTPUB30,FIFO4_eTPUB31,FIFO4_eTPUC28,FIFO4_eTPUC29,FIFO4_eTPUC30,FIFO4_eTPUC31,FIFO4_eMIOS0_16,FIFO4_eMIOS0_17,FIFO4_eMIOS0_18,FIFO4_eMIOS0_19,FIFO4_eMIOS0_20,FIFO4_eMIOS0_21,FIFO4_eMIOS0_22,FIFO4_eMIOS0_23,FIFO4_eTPUA27,FIFO4_eMIOS1_5,FIFO4_ETRIG0,FIFO5_RTI,FIFO5_PIT0,FIFO5_PIT1,FIFO5_PIT2,FIFO5_PIT3,FIFO5_ETRIG0,FIFO5_eTPUA28,FIFO5_eTPUA29,FIFO5_eTPUA30,FIFO5_eTPUA31,FIFO5_eTPUB28,FIFO5_eTPUB29,FIFO5_eTPUB30,FIFO5_eTPUB31,FIFO5_eTPUC28,FIFO5_eTPUC29,FIFO5_eTPUC30,FIFO5_eTPUC31,FIFO5_eMIOS0_16,FIFO5_eMIOS0_17,FIFO5_eMIOS0_18,FIFO5_eMIOS0_19,FIFO5_eMIOS0_20,FIFO5_eMIOS0_21,FIFO5_eMIOS0_22,FIFO5_eMIOS0_23,FIFO5_eTPUA26,FIFO5_eMIOS1_4,FIFO5_ETRIG1
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo0.AdcHwTrigSrc:FIFO0_RTI,FIFO0_PIT0,FIFO0_PIT1,FIFO0_PIT2,FIFO0_PIT3,FIFO0_ETRIG1,FIFO0_eTPUA28,FIFO0_eTPUA29,FIFO0_eTPUA30,FIFO0_eTPUA31,FIFO0_eTPUB28,FIFO0_eTPUB29,FIFO0_eTPUB30,FIFO0_eTPUB31,FIFO0_eTPUC28,FIFO0_eTPUC29,FIFO0_eTPUC30,FIFO0_eTPUC31,FIFO0_eMIOS0_16,FIFO0_eMIOS0_17,FIFO0_eMIOS0_18,FIFO0_eMIOS0_19,FIFO0_eMIOS0_20,FIFO0_eMIOS0_21,FIFO0_eMIOS0_22,FIFO0_eMIOS0_23,FIFO0_eMIOS1_2,FIFO0_ETRIG0
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo1.AdcHwTrigSrc:FIFO1_RTI,FIFO1_PIT0,FIFO1_PIT1,FIFO1_PIT2,FIFO1_PIT3,FIFO1_eTPUA7,FIFO1_ETRIG0,FIFO1_eTPUA28,FIFO1_eTPUA29,FIFO1_eTPUA30,FIFO1_eTPUA31,FIFO1_eTPUB28,FIFO1_eTPUB29,FIFO1_eTPUB30,FIFO1_eTPUB31,FIFO1_eTPUC28,FIFO1_eTPUC29,FIFO1_eTPUC30,FIFO1_eTPUC31,FIFO1_eMIOS0_16,FIFO1_eMIOS0_17,FIFO1_eMIOS0_18,FIFO1_eMIOS0_19,FIFO1_eMIOS0_20,FIFO1_eMIOS0_21,FIFO1_eMIOS0_22,FIFO1_eMIOS0_23,FIFO1_eMIOS1_3,FIFO1_ETRIG1
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo2.AdcHwTrigSrc:FIFO2_RTI,FIFO2_PIT0,FIFO2_PIT1,FIFO2_PIT2,FIFO2_PIT3,FIFO2_eTPUA14,FIFO2_ETRIG1,FIFO2_eTPUA28,FIFO2_eTPUA29,FIFO2_eTPUA30,FIFO2_eTPUA31,FIFO2_eTPUB28,FIFO2_eTPUB29,FIFO2_eTPUB30,FIFO2_eTPUB31,FIFO2_eTPUC28,FIFO2_eTPUC29,FIFO2_eTPUC30,FIFO2_eTPUC31,FIFO2_eMIOS0_16,FIFO2_eMIOS0_17,FIFO2_eMIOS0_18,FIFO2_eMIOS0_19,FIFO2_eMIOS0_20,FIFO2_eMIOS0_21,FIFO2_eMIOS0_22,FIFO2_eMIOS0_23,FIFO2_eMIOS1_7,FIFO2_ETRIG0
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo3.AdcHwTrigSrc:FIFO3_RTI,FIFO3_PIT0,FIFO3_PIT1,FIFO3_PIT2,FIFO3_PIT3,FIFO3_eTPUA22,FIFO3_ETRIG0,FIFO3_eTPUA28,FIFO3_eTPUA29,FIFO3_eTPUA30,FIFO3_eTPUA31,FIFO3_eTPUB28,FIFO3_eTPUB29,FIFO3_eTPUB30,FIFO3_eTPUB31,FIFO3_eTPUC28,FIFO3_eTPUC29,FIFO3_eTPUC30,FIFO3_eTPUC31,FIFO3_eMIOS0_16,FIFO3_eMIOS0_17,FIFO3_eMIOS0_18,FIFO3_eMIOS0_19,FIFO3_eMIOS0_20,FIFO3_eMIOS0_21,FIFO3_eMIOS0_22,FIFO3_eMIOS0_23,FIFO3_eMIOS1_6,FIFO3_ETRIG1
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo4.AdcHwTrigSrc:FIFO4_RTI,FIFO4_PIT0,FIFO4_PIT1,FIFO4_PIT2,FIFO4_PIT3,FIFO4_eTPUA30,FIFO4_ETRIG1,FIFO4_eTPUA28,FIFO4_eTPUA29,FIFO4_eTPUA31,FIFO4_eTPUB28,FIFO4_eTPUB29,FIFO4_eTPUB30,FIFO4_eTPUB31,FIFO4_eTPUC28,FIFO4_eTPUC29,FIFO4_eTPUC30,FIFO4_eTPUC31,FIFO4_eMIOS0_16,FIFO4_eMIOS0_17,FIFO4_eMIOS0_18,FIFO4_eMIOS0_19,FIFO4_eMIOS0_20,FIFO4_eMIOS0_21,FIFO4_eMIOS0_22,FIFO4_eMIOS0_23,FIFO4_eTPUA27,FIFO4_eMIOS1_5,FIFO4_ETRIG0
Adc.AdcConfigSet.AdcHwUnit.AdcGroup.Fifo5.AdcHwTrigSrc:FIFO5_RTI,FIFO5_PIT0,FIFO5_PIT1,FIFO5_PIT2,FIFO5_PIT3,FIFO5_ETRIG0,FIFO5_eTPUA28,FIFO5_eTPUA29,FIFO5_eTPUA30,FIFO5_eTPUA31,FIFO5_eTPUB28,FIFO5_eTPUB29,FIFO5_eTPUB30,FIFO5_eTPUB31,FIFO5_eTPUC28,FIFO5_eTPUC29,FIFO5_eTPUC30,FIFO5_eTPUC31,FIFO5_eMIOS0_16,FIFO5_eMIOS0_17,FIFO5_eMIOS0_18,FIFO5_eMIOS0_19,FIFO5_eMIOS0_20,FIFO5_eMIOS0_21,FIFO5_eMIOS0_22,FIFO5_eMIOS0_23,FIFO5_eTPUA26,FIFO5_eMIOS1_4,FIFO5_ETRIG1
Adc.AdcConfigSet.AdcHwUnit:4
Adc.AdcConfigSet.MaxEqadc:2
Adc.AdcConfigSet.MaxFifo:6
AdcDMAPresent:TRUE
######################  mpc5775e_mapbga416 Adc module: END  #####################
######################  Can_mpc5745c_mapbga100  Can module  ##########################
# 
# Can.CanConfigSet.CanHwChannelList.MSCAN               : list of available FlexCan controllers
# Can.CanConfigSet.CanRamBlockList                      : list of available RamBlocks
# Can.CanConfigSet.CanExpandedMBMemoryList              : List of controller support Expanded Message Buffer Memory
# Can.CanConfigSet.CanController                        : number of available FlexCan controllers
# Can.CanConfigSet.CanMB                                : number of Message Buffers for every controller
# Can.CanConfigSet.CanController.NoMB:                  : number of maximum MBs supported in hardware for every controller
# Can.CanConfigSet.RxFifoEventsUnified                  : separate interrupts handlers or not will be used for the 3 events of the RxFifo.
# Can.CanConfig.InternalWakeupSupport                   : support for Wakeup with Can controller capability (MCR_WAK_MSK, ESR_WAK_INT, .. bits
# Can.CanConfig.DualClockMode                           : support for switch Can controller to another clk value.
# Can.CanConfig.MemoryECC                               : platform support for Flexcan internal memory error detection and correction
# Can.CanConfigSet.CanFdEnable                          : Enable the FD feature if CanFdEnable is STD_ON
# Can.CanConfig.CtrlClksrcAvailable                     : On some platforms CLKSRC bit it is reserved. On this case  CtrlClksrcAvailable  should be STD_OFF
# Can.CanConfig.MultipleInterrupts                      : Regulary for PPC there are groups of events mapped to one interrupt. For ARM all events are using one single interrupt(exception KFA which is ARM and 
#                                                            use multiple interupts).  For PPC and KFA this should be STD_ON 
# Can.CanConfigSet.CanRxFiFoEnhancedEnableList          : List of controller support Enhanced Rx FIFO
# Can.CanConfigSet.CanRxFiFoEnhancedNumFilterElement    : number of maximum Enhanced RxFiFo Elements
# Can.CanConfigSet.CanPretendedNetworkingList           : List of controller support Pretended Networking
# Can.CanConfig.SwichingIsoMode                         : add support for the platsforms select between iso od non-iso for CAN FD.
# Can.CanConfigSet.CBTSupport                           : Add support the selection the CBT register
# Can.CanConfig.SupvAvailable                           : Add support the selection supervisor - user mode or no.
# Can.CanConfig.TimeStampSupport                        : Add support TimeStamp feature.
################################################################################

Can.CanConfigSet.CanHwChannelList.MSCAN:FlexCAN_A,FlexCAN_B,FlexCAN_C,FlexCAN_D
Can.CanConfigSet.CanRamBlockList:NONE
Can.CanConfigSet.CanExpandedMBMemoryList:NONE
Can.CanConfigSet.CanController:4
Can.CanConfigSet.CanMB:64
Can.CanConfigSet.CanController.NoMB:64, 64, 64, 64
Can.CanConfigSet.FlexCAN_A:64
Can.CanConfigSet.FlexCAN_B:64
Can.CanConfigSet.FlexCAN_C:64
Can.CanConfigSet.FlexCAN_D:64
Can.CanConfigSet.RxFifoEventsUnified:STD_OFF
Can.CanConfig.InternalWakeupSupport:STD_OFF
Can.CanConfig.DualClockMode:STD_ON
Can.CanConfig.CanController.WakeUpSourceFilter:STD_OFF
Can.CanConfig.MemoryECC:STD_ON
Can.CanConfig.CtrlClksrcAvailable:STD_ON
Can.CanConfigSet.CanFdEnable:STD_OFF
Can.CanConfigSet.CanRxFiFoEnhancedEnableList:NONE
Can.CanConfigSet.CanRxFiFoEnhancedNumFilterElement:0
Can.CanConfigSet.CanRxFiFoEnhancedDeep:0
Can.CanConfigSet.CanPretendedNetworking:STD_OFF
Can.CanConfigSet.CanPretendedNetworkingList:NONE
Can.CanConfig.SwichingIsoMode:STD_OFF
Can.CanConfigSet.CBTSupport:STD_OFF
Can.CanConfigSet.ProtocolException:STD_OFF
Can.CanConfigSet.EdgeFilter:STD_OFF
Can.CanConfigSet.TimeStampSupport:STD_OFF
# MaxFdBaudrateValue is needed due to errata e7845 on Rainier cut 2.0
Can.CanConfigSet.MaxFdBaudrateValue:8000
Can.CanConfig.MultipleInterrupts: STD_ON
Can.CanConfig.SupvAvailable:STD_ON

######################  Can_mpc5775e_mapbga416  Can module: END  #####################
######################  mpc5775e_mapbga416 Can module  ##########################
# MCan.CanConfigSet.CanHwChannelList               : list of available MCan controllers
# MCan.CanConfigSet.CanController                  : number of  available MCan controllers
# MCan.CanConfigSet.CanRxMbList                    : list of available receive MB
# MCan.CanConfigSet.CanMB.RxFifo                   : number of maximum Message Buffers for Rx Fifo
# MCan.CanConfigSet.CanMB.RxBuffer                 : number of maximum Message Buffers for Rx Buffer
# MCan.CanConfigSet.CanMB.TxBuffer                 : number of maximum Message Buffers for Tx Buffer
# MCan.CanConfigSet.CanFilterStd                   : number of maximum Filter Standand
# MCan.CanConfigSet.CanFilterExtd                  : number of maximum Filter Extended
# MCan.CanConfigSet.RxFifoEventsUnified            : Rx Fifo events (Warning/Overflow/FrameAvailable) are configured on the same int on INTC vector table
# MCan.CanConfig.InternalWakeupSupport             : support for Wakeup with Can controller capability (MCR_WAK_MSK, ESR_WAK_INT, .. bits
# MCan.CanConfig.ExternalWakeupSupport             : support for Wakeup using WKPU module (map RX signal to a WKPU line)
# MCan.CanConfig.ExternalWakeupSignal              : all possible WKPU lines for this derivative
# MCan.CanConfig.DefaultWakeupSignal               : default values for WKPU line sfor controllers in case Wxternal Wakeup is used
# MCan.CanConfig.DualClockMode                     : support for switch Can controller to another clk value.
# MCan.CanConfig.CanController.WakeUpSourceFilter  : Defines whether the integrated low-pass filter is applied to protect the Rx Can input from spurious wake up
# MCan.CanConfig.TTCanSRamOffSetStart              : Define the address offset start of SRAM region which is not be able to used by MCAN module [words]
# MCan.CanConfig.TTCANSRamOffsetEnd                : Define the address offset end of SRAM region which is not be able to used by MCAN module [words]
# MCan.Canconfig.SRamSize                          : Define the SRAM region size [words]
# MCan.CanConfig.MixMB                             : platform support controller with different number of MBs in hardware 
# MCan.CanConfig.CombinedInterrupt                 : Support Combined ISR for Controllers or not.
# MCan.CanConfigSet.CanPretendedNetworking         : Specify which platform support Pretended Networking
# MCan.CanConfigSet.CanPretendedNetworkingList     : The list of controller which Pretended Networking is supported. 'STD_OFF' which platform does not supported
################################################################################
MCan.CanConfigSet.CanHwChannelList:MCAN_1,MCAN_2
MCan.CanConfigSet.CanController:2
MCan.CanConfigSet.CanRxMbList:FIFO_0,FIFO_1,BUFFER_0,BUFFER_1,BUFFER_2,BUFFER_3,BUFFER_4,BUFFER_5,BUFFER_6,BUFFER_7,BUFFER_8,BUFFER_9,BUFFER_10,BUFFER_11,BUFFER_12,BUFFER_13,BUFFER_14,BUFFER_15,BUFFER_16,BUFFER_17,BUFFER_18,BUFFER_19,BUFFER_20,BUFFER_21,BUFFER_22,BUFFER_23,BUFFER_24,BUFFER_25,BUFFER_26,BUFFER_27,BUFFER_28,BUFFER_29,BUFFER_30,BUFFER_31,BUFFER_32,BUFFER_33,BUFFER_34,BUFFER_35,BUFFER_36,BUFFER_37,BUFFER_38,BUFFER_39,BUFFER_40,BUFFER_41,BUFFER_42,BUFFER_43,BUFFER_44,BUFFER_45,BUFFER_46,BUFFER_47,BUFFER_48,BUFFER_49,BUFFER_50,BUFFER_51,BUFFER_52,BUFFER_53,BUFFER_54,BUFFER_55,BUFFER_56,BUFFER_57,BUFFER_58,BUFFER_59,BUFFER_60,BUFFER_61,BUFFER_62,BUFFER_63
MCan.CanConfigSet.CanRxMbTypeList:FIFO_0,FIFO_1,RX_BUFFER
MCan.CanConfigSet.CanMB.RxFifo:64
MCan.CanConfigSet.CanMB.RxBuffer:64
MCan.CanConfigSet.CanMB.TxBuffer:32
MCan.CanConfigSet.CanFilterStd:128
MCan.CanConfigSet.CanFilterExtd:64
MCan.CanConfigSet.RxFifoEventsUnified:STD_ON
MCan.CanConfig.InternalWakeupSupport:STD_OFF
MCan.CanConfig.ExternalWakeupSupport:STD_OFF
MCan.CanConfig.DualClockMode:STD_ON
MCan.CanConfig.CanController.WakeUpSourceFilter:STD_OFF
MCan.CanConfigSet.MaxFdBaudrateValue:8000
MCan.CanConfigSet.CanFdEnable:STD_ON
MCan.CanConfigSet.CanPretendedNetworking:STD_OFF
MCan.CanConfigSet.CanPretendedNetworkingList:STD_OFF
MCan.CanConfigSet.TTCanSRamOffsetStart:2880
MCan.CanConfigSet.TTCanSRamOffsetEnd:3008
MCan.CanConfigSet.SRamSize:5120
MCan.CanConfig.MixMB:STD_OFF 
MCan.CanConfig.CombinedInterrupt:STD_ON
######################  mpc5775e_mapbga416 Can module: END  ############################################# mpc5775e_mapbga416  Dio module ##################################
#                                                                                        #
# DioPackage               : Dio package name                                            #
# Dio.AvailablePortPins    : Describes the pins that are available on each port          #
#                            using bit masks. A 16 bit value describes each port.        # 
#                            A bit value of one in the bit mask means that               # 
#                            the corresponding pin from that port is available           #
#                            in the current package .                                    #
#                                                                                        #
##########################################################################################

DioPackage:Dio_mpc5775e_mapbga416
Dio.AvailablePortPinsForRead:0x0000,0x0000,0x0000,0x0000,0x001F,0xFFFF,0xFFFE,0x7FFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFF8,0xEC0F,0x01FF,0xFFFC,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFCFF,0xFFFF,0xFFBF,0xFFF0
Dio.AvailablePortPinsForReadReversedBits:0x0000,0x0000,0x0000,0x0000,0xF800,0xFFFF,0x7FFF,0xFFFE,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0x1FFF,0xF037,0xFF80,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFF3F,0xFFFF,0xFDFF,0x0FFF
Dio.AvailablePortPinsForWrite:0x0000,0x0000,0x0000,0x0000,0x001F,0xFFFF,0xFFFE,0x7FFF,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0xFFF8,0xEC0F,0x01FF,0xFFFC,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xFC17,0xDFFF,0xFF80,0x0000
Dio.AvailablePortPinsForWriteReversedBits:0x0000,0x0000,0x0000,0x0000,0xF800,0xFFFF,0x7FFF,0xFFFE,0xFFFF,0xFFFF,0xFFFF,0xFFFF,0x1FFF,0xF037,0xFF80,0x3FFF,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0xE83F,0xFFFB,0x01FF,0x0000

######################  mpc5775e_mapbga416 Dio module: END  #################################################### mpc5775e mapbga416 Fls module ###########################
#
# Fls.Sector.Physical.List    :list of available Flash physical sectors
#
################################################################################

Fls.Sector.Physical.List:4000_FLS_UTEST_ARRAY_0_PART_0_U00,\
                        10000_FLS_DATA_ARRAY_0_PART_0_L00,\
                        10000_FLS_DATA_ARRAY_0_PART_1_L01,\
                        10000_FLS_DATA_ARRAY_0_PART_2_M00,\
                        10000_FLS_DATA_ARRAY_0_PART_3_M01,\
                         4000_FLS_CSE_ARRAY_0_PART_4_H00,\
                         4000_FLS_CSE_ARRAY_0_PART_5_H01,\
                        40000_FLS_BOOT_ARRAY_0_PART_6_LG00,\
                        40000_FLS_CAL_ARRAY_0_PART_6_LG01,\
                        40000_FLS_CAL_ARRAY_0_PART_6_LG02,\
                        40000_FLS_CAL_ARRAY_0_PART_6_LG03,\
                        40000_FLS_CAL_ARRAY_0_PART_6_LG04,\
                        40000_FLS_CODE_ARRAY_0_PART_6_LG05,\
                        40000_FLS_CODE_ARRAY_0_PART_6_LG06,\
                        40000_FLS_CODE_ARRAY_0_PART_6_LG07,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG08,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG09,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG10,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG11,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG12,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG13,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG14,\
                        40000_FLS_CODE_ARRAY_0_PART_7_LG15

Fls.Sector.Program.List:8_FLS_WRITE_DOUBLE_WORD,\
                       32_FLS_WRITE_PAGE,\
                      128_FLS_WRITE_QUAD_PAGE
                      
Fls.DataFlashExists:true
Fls.ECCSyndrome:0x00088008
Fls.ECCSyndromeCache:0x00080008

#Fls.UserModeSupport : Paramater to determine platform support run FLS driver in User Mode or not
#       - true : Support running FLS driver in User Mode
#       - false: Not support running FLS driver in User Mode
#
Fls.UserModeSupport: true
#This parameter to check the availability of the register protection in user mode (FLS_FLASH_REG_PROT_AVAILABLE)
Fls.C55fmcOrC40asfRegisterProtectionAvailable:false
Fls.SupportSynchronizeCacheFeature: false
Fls.SupportMultiCoreFeature: false
Fls.FlsUseInterrupts: false

Fls.Internal.Flash.Available:STD_ON
Fls.External.Qspi.Available:STD_OFF
Fls.External.HwUnit:

# Listed in QuadSPI chapter, each one has a QSPI_BUFxCR register associated. Used to store read data when using AHB read mode.
Fls.External.HwUnit.Ahb.Buffers:AHB_BUFFER_0,AHB_BUFFER_1,AHB_BUFFER_2,AHB_BUFFER_3

# Master IDs, listed in Peripheral Bridge(AIPS) chapter, 'Master ID assignments' table. Used to assign each buffer to a specific master access.
Fls.External.HwUnit.Ahb.MasterID.List:  FLS_CORTEX_R52_C0_AXI_M,\
                                        FLS_CORTEX_R52_C1_AXI_M,\
                                        FLS_CORTEX_R52_C2_AXI_M,\
                                        FLS_CORTEX_R52_C3_AXI_M,\
                                        FLS_STAM,\
                                        FLS_EDMA_0,\
                                        FLS_EDMA_1,\
                                        FLS_CORTEX_R52_C0_AXI_F,\
                                        FLS_CORTEX_R52_C1_AXI_F,\
                                        FLS_DEBUG_TRACE,\
                                        FLS_HSE,\
                                        FLS_GMAC_0,\
                                        FLS_OTC_LL,\
                                        FLS_OTC_HT,\
                                        FLS_FLEXRAY_0,\
                                        FLS_CORTEX_R52_C2_AXI_F,\
                                        FLS_CORTEX_R52_C3_AXI_F,\
                                        FLS_DEBUG_ETR,\
                                        FLS_USDHC
                                    
# AHB buffers total size, in bytes.                                       
Fls.External.HwUnit.Ahb.BufferSize:1024

#
Fls.HwUnit.Channel.List:    FLS_CH_INTERN
                        
Fls.Qspi.Channel.List:      FLS_CH_EXTERN_QSPI_0_A1,\
                            FLS_CH_EXTERN_QSPI_0_A2,\
                            FLS_CH_EXTERN_QSPI_0_B1,\
                            FLS_CH_EXTERN_QSPI_0_B2,\
                            FLS_CH_EXTERN_QSPI_0_PARALLEL_A1B1,\
                            FLS_CH_EXTERN_QSPI_0_PARALLEL_A2B2,\
                            NOT_QSPI_CHANNEL
                        
# Default register values, device specific. If a register is not available, the value should be set to zero.                        
Fls.External.HwUnit.Qspi0.SFA1AD.Default:0x10000
Fls.External.HwUnit.Qspi0.SFA2AD.Default:0x20000
Fls.External.HwUnit.Qspi0.SFB1AD.Default:0x30000
Fls.External.HwUnit.Qspi0.SFB2AD.Default:0x40000
Fls.External.HwUnit.Qspi1.SFA1AD.Default:0
Fls.External.HwUnit.Qspi1.SFA2AD.Default:0
Fls.External.HwUnit.Qspi1.SFB1AD.Default:0
Fls.External.HwUnit.Qspi1.SFB2AD.Default:0

###################### mpc5775e mapbga416 Fls module: END  ######################
#####################  Gpt_mpc5775e_mapbga416 Gpt module  ##########################
#
# Gpt.GptChannelConfigSet.GptChannelConfiguration.GptHwChannel : Selects the physical GPT Channel.
#
################################################################################
Gpt.Num_eMios_Hw_Modules:2
Gpt.Num_Pit_Hw_Modules:1
Gpt.Num_Stm_Hw_Modules:1
Gpt.Num_Channels_Per_Module:16,16,5,4
Gpt.GptChannelConfigSet.GptChannelConfiguration.GptHwChannel:EMIOS_0_CH_0,EMIOS_0_CH_1,EMIOS_0_CH_2,EMIOS_0_CH_3,EMIOS_0_CH_4,EMIOS_0_CH_5,EMIOS_0_CH_6,EMIOS_0_CH_7,EMIOS_0_CH_16,EMIOS_0_CH_17,EMIOS_0_CH_18,EMIOS_0_CH_19,EMIOS_0_CH_20,EMIOS_0_CH_21,EMIOS_0_CH_22,EMIOS_0_CH_23,EMIOS_1_CH_0,EMIOS_1_CH_1,EMIOS_1_CH_2,EMIOS_1_CH_3,EMIOS_1_CH_4,EMIOS_1_CH_5,EMIOS_1_CH_6,EMIOS_1_CH_7,EMIOS_1_CH_16,EMIOS_1_CH_17,EMIOS_1_CH_18,EMIOS_1_CH_19,EMIOS_1_CH_20,EMIOS_1_CH_21,EMIOS_1_CH_22,EMIOS_1_CH_23,PIT_0_CH_RTI,PIT_0_CH_0,PIT_0_CH_1,PIT_0_CH_2,PIT_0_CH_3,STM_0_CH_0,STM_0_CH_1,STM_0_CH_2,STM_0_CH_3,STM_0_PREDEF
Gpt.GptConfig.Gpt_PIT_ModuleSingleInterrupt:STD_OFF
Gpt.GptConfig.Gpt_STM_ModuleSingleInterrupt:STD_OFF
######################  Gpt_mpc5775e_mapbga416: END  ##########################################  mpc5775e_mapbga416 Icu module  ##########################
#
# Icu.IcuConfigSet.IcuChannel.IcuHwChannel : list of available ICU HW channels
#
################################################################################
Icu.Num_eMios_Hw_Modules:2
Icu.eMios_Hw_Modules:EMIOS_0,EMIOS_1
Icu.IcuConfigSet.IcuChannel.IcuHwChannel.IcueMiosHw:CH_0,CH_1,CH_2,CH_3,CH_4,CH_5,CH_6,CH_7,CH_16,CH_17,CH_18,CH_19,CH_20,CH_21,CH_22,CH_23
Icu.eMios_Hw_MasterBuses:CH_0,CH_16,CH_23
Icu.Num_Siu_Hw_Modules:1
Icu.IcuConfigSet.IcuChannel.IcuHwChannel.IcuSiuHw:IRQ_CH_0,IRQ_CH_1,IRQ_CH_2,IRQ_CH_3,IRQ_CH_4,IRQ_CH_5,IRQ_CH_6,IRQ_CH_7,IRQ_CH_8,IRQ_CH_9,IRQ_CH_10,IRQ_CH_11,IRQ_CH_12,IRQ_CH_13,IRQ_CH_14,IRQ_CH_15
Icu.IcuConfigSet.IcuChannel.IcuHwChannel:EMIOS_0_CH_0,EMIOS_0_CH_1,EMIOS_0_CH_2,EMIOS_0_CH_3,EMIOS_0_CH_4,EMIOS_0_CH_5,EMIOS_0_CH_6,EMIOS_0_CH_7,EMIOS_0_CH_16,EMIOS_0_CH_17,EMIOS_0_CH_18,EMIOS_0_CH_19,EMIOS_0_CH_20,EMIOS_0_CH_21,EMIOS_0_CH_22,EMIOS_0_CH_23,EMIOS_1_CH_0,EMIOS_1_CH_1,EMIOS_1_CH_2,EMIOS_1_CH_3,EMIOS_1_CH_4,EMIOS_1_CH_5,EMIOS_1_CH_6,EMIOS_1_CH_7,EMIOS_1_CH_16,EMIOS_1_CH_17,EMIOS_1_CH_18,EMIOS_1_CH_19,EMIOS_1_CH_20,EMIOS_1_CH_21,EMIOS_1_CH_22,EMIOS_1_CH_23,IRQ_CH_0,IRQ_CH_1,IRQ_CH_2,IRQ_CH_3,IRQ_CH_4,IRQ_CH_5,IRQ_CH_6,IRQ_CH_7,IRQ_CH_8,IRQ_CH_9,IRQ_CH_10,IRQ_CH_11,IRQ_CH_12,IRQ_CH_13,IRQ_CH_14,IRQ_CH_15

Icu.ChannelType.EMIOS_0_CH_0:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_1:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_2:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_3:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_4:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_5:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_0_CH_6:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_7:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_16:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_17:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_18:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_19:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_0_CH_20:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_0_CH_21:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_0_CH_22:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_0_CH_23:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_0:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_1_CH_1:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_1_CH_2:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_1_CH_3:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM, DMA
Icu.ChannelType.EMIOS_1_CH_4:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_5:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_6:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_7:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_16:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_17:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_18:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_19:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_20:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_21:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_22:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.EMIOS_1_CH_23:ICU_MODE_EDGE_COUNTER,ICU_MODE_SIGNAL_EDGE_DETECT,ICU_MODE_SIGNAL_MEASUREMENT,ICU_MODE_TIMESTAMP, EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER, SAIC, IPM, IPWM
Icu.ChannelType.IRQ_CH_0:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_1:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_2:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_3:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_4:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_5:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_6:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_7:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_8:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_9:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_10:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_11:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_12:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_13:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_14:ICU_MODE_SIGNAL_EDGE_DETECT
Icu.ChannelType.IRQ_CH_15:ICU_MODE_SIGNAL_EDGE_DETECT

######################   mpc5775e_mapbga416 Icu module: END  ##########################################  mpc5777c_mapbga516 Lin module  ##########################
#
# Lin.LinGlobalConfig.LinChannel              : Total Number of eSCI Channels
# Lin.LinGlobalConfig.LinChannel.LinHwChannel : List of eSCI channels
# LinExternalWKPUSupport                      : TRUE if wake up support needs to be configured
# LinExternalWKPUChannelID                    : External Wake up channel(s) assigned for each LIN HW channel
# LinDMAPresent                               : DMA support for LIN peripheral(s)
# LinDMAChannelForeSCI0TX                     : DMA channel was used for transmit data by channel eSCI_0
# LinDMAChannelForeSCI0RX                     : DMA channel was used for receive data by channel eSCI_0
# LinDMAChannelForeSCI1TX                     : DMA channel was used for transmit data by channel eSCI_1
# LinDMAChannelForeSCI1RX                     : DMA channel was used for receive data by channel eSCI_1
#
################################################################################

Lin.LinGlobalConfig.LinChannel:6
Lin.LinGlobalConfig.LinChannel.LinHwChannel:eSCI_0,eSCI_1,eSCI_2,eSCI_3,eSCI_4,eSCI_5
LinExternalWKPUSupport:FALSE
LinDMAPresent:TRUE
LinDMAChannelForeSCI0TX:18
LinDMAChannelForeSCI0RX:19
LinDMAChannelForeSCI1TX:34
LinDMAChannelForeSCI1RX:35

######################  mpc5775ec_mapbga416 Lin module: END  ##########################################  mpc5775e_mapbga416 Mcu module  ##########################
# Values according to SIU_SYSDIV[SYSCLKSEL] field description
MCU.SystemClkSource.List:IRC,XOSC,PLL0_PHI,PLL1_PHI
MCU.SystemClkSource.Default:IRC

#Values according to SIU_SYSDIV[PLL0SEL]
MCU.Pll0ClockSource.List:XOSC,IRC
MCU.Pll0ClockSource.Default:XOSC

#Values according to SIU_SYSDIV[PLL1SEL]
MCU.Pll1ClockSource.List:XOSC,PLL0_PHI1
MCU.Pll1ClockSource.Default:XOSC

#Values according to SIU_SYSDIV[PERCLKSEL]
MCU.PeripheralClockSource.List:PLL0_PHI,SYSTEM_CLK
MCU.PeripheralClockSource.Default:SYSTEM_CLK

#Values according to SIU_SYSDIV[MCANSEL]
MCU.MCANClockSource.List:XOSC,PER_CLK
MCU.MCANClockSource.Default:XOSC

#Values according to SIU_ECCR[ECCS]
MCU.EngineeringClockSource.List:PLAT_CLK,XOSC
MCU.EngineeringClockSource.Default:PLAT_CLK

#Values according to SIU_LFCLKCFG[LFCLKSEL]
MCU.LFASTClockSource.List:None
MCU.LFASTClockSource.Default:None

#List of AuxClock:
MCU.AuxClock.List:SD_CLK,ENGINEERING_CLK

# MCU.PerReset.List:F_VOR_DEST,F_TSR_DEST,F_FIF,F_EDR,F_SUF,F_FFRR,F_SOFT_DEST,F_POR,F_VOR_FUNC,F_TSR_FUNC,F_JTAG_FUNC,F_FCCU_SOFT,F_FCCU_HARD,F_SOFT_FUNC,F_ST_DONE,F_EXR
# MCU.PerSource.List:PCTL9_LFAST_0,PCTL11_SIPI_0,PCTL12_ENET_0,PCTL30_PIT_0,PCTL36_DMAMUX_0,PCTL38_CRC_0,PCTL77_CAN_2,PCTL78_CAN_1,PCTL79_CAN_0,PCTL91_LINFLEX_1,PCTL98_DSPI_1,PCTL99_DSPI_0,PCTL104_SENT_0,PCTL107_FLEXRAY,PCTL124_ADC_3,PCTL126_ADC_1,PCTL137_ETIMER_1,PCTL141_CTU_1,PCTL144_PWM_1,PCTL146_DMAMUX_1,PCTL204_LINFLEX_0,PCTL208_DSPI_3,PCTL209_DSPI_2,PCTL214_SENT_1,PCTL235_ADC_2,PCTL237_ADC_0,PCTL239_SGEN_0,PCTL245_ETIMER_2,PCTL247_ETIMER_0,PCTL251_CTU_0,PCTL255_PWM_0
# MCU.PerSource.Default:PCTL9_LFAST_0
# MCU.ResetEnable.Default:1
#List of Clock Reference Point
MCU.ClockReferencePoint.List:CUSTOM,IRC_CLK,XOSC_CLK,SYS_CLK,CORE_CLK,PLAT_CLK,FM_PER_CLK,PER_CLK,ETPU_CLK,MCAN_CLK,ENG_CLK,CLKOUT_CLK,SD_CLK,EMIOS0,EMIOS1


#list of PCS
MCU.Pcs.List:PCS_1,PCS_2,PCS_3

#######################################################
################# CLOCKING LIMITS #####################
#######################################################
MCU.CORE_CLK.Limits.High:264000000
MCU.CORE_CLK.Limits.Low:500000

MCU.ETPU_CLK.Limits.High:200000000
MCU.ETPU_CLK.Limits.Low:250000

MCU.PLAT_CLK.Limits.High:132000000
MCU.PLAT_CLK.Limits.Low:250000

MCU.FM_PER_CLK.Limits.High:132000000
MCU.FM_PER_CLK.Limits.Low:62500

MCU.PER_CLK.Limits.High:132000000
MCU.PER_CLK.Limits.Low:62500

#######################################################
#################       CMU      ######################
#######################################################
MCU.CMU.List:CMU_0_XOSC_AND_PLL_PHI0_CLK,CMU_1_CORE_CLK,CMU_2_PLAT_CLK,CMU_3_FM_PER_CLK,CMU_4_ETPU_CLK,CMU_5_PER_CLK,CMU_6_SD_CLK
MCU.CMU.Default:CMU_0_XOSC_AND_PLL_PHI0_CLK
#The CMU having RCDIV(i.e 0 is CMU0, 1 is CMU1...)
MCU.CMU.RCDIV.AVAILABLE.LIST:0
#CMU_x_CSR[RCDIV] field needs to be updated independent of CMU_x_CSR[CME]
MCU.CMU.RCDIV.Independent:true

MCU.NumberOfPcsRegs:9

MCU.eMIOS.List:eMIOS_0,eMIOS_1

#######################################################
#################        PRAMC      ###################
#######################################################
#PRAMC is/not available on the platform.
MCU.PRAMC.AVAILABLE:true

#######################################################
#################       PFLASH      ###################
#######################################################
#PFLASH is/not available on the platform.
MCU.PFLASH.AVAILABLE:true

################################################################################
MCU.McuRamSectorSettingConf.McuRamSectionBaseAddress.low:1073741824
MCU.McuRamSectorSettingConf.McuRamSectionBaseAddress.high:1074266111
MCU.McuRamSectorSettingConf.McuRamSectionSize:524288

######################  mpc5775e_mapbga416 Mcu module: END  ##########################################  mpc5775e_mapbga416 Mcl module  ##########################
#
# Mcl.MclConfigSet.DmaChannels             : Selects the physical DMA channel
# Mcl.MclConfigSet.DmaInstances            : Selects the physical DMA instance
# Mcl.MclConfigSet.DmaMux0.Sources         : Selects the sources of DmaMux0
# Mcl.MclConfigSet.DmaMux1.Sources         : Selects the sources of DmaMux1
# Mcl.eDMA.TransferSizeInBytes             : SSIZE and DSIZE possible values in bytes to transfer
# Mcl.eDMA.ChannelNumber                   : Number of eDma channels 
# Mcl.eDMA.ChannelNumberPerGroup           : Number of eDma channels per eDma Group
# Mcl.eDMA.ChannelNumberPerDmaInstance     : Number of eDma channels per eDma instance
# Mcl.eDMA.MaxPriorityGroupId              : The maximum group priority number needed to configure eDMA_CR group priorities
# Mcl.eDMA.PriorityGroup0Exists            : if Group0 exists in eDMA_CR configuration
# Mcl.eDMA.PriorityGroup1Exists            : if Group1 exists in eDMA_CR configuration
# Mcl.eDMA.PriorityGroup2Exists            : if Group2 exists in eDMA_CR configuration
# Mcl.eDMA.PriorityGroup3Exists            : if Group3 exists in eDMA_CR configuration

# Mcl.eDMA.TransferSizeInBytes:            : TransferSizeInBytes should be a reunion of DMA2 and DMA3 ssize options
# Mcl.eDMA.ChannelNumberMain:              : Total Number of DMA channels per Main. For Supernova there are 2xDMA3, 32 channels each=> Hence 64 channels.
# Mcl.eDMA.ChannelNumberAcd:               : Number of channels  per DMA of the ACD. For Supernova there is 1xDMA2, 16 channels =>16 channels

# Mcl.eDMA.CombinedErrorIsr                : Specifies if there is one error ISR for multiple DMA instances
# Mcl.eDMA.CombinedTrCompletionIsr         : Specifies if there is one combined transfer ISR for all channels within a DMA instance
# Mcl.eDMA.CombinedTrComplMixedIsr         : Specifies if inside a DMA instance some channels have the same transfer completion ISR assigned,
#                                            and other channels have their own transfer completion ISR. 
# Mcl.eDMA.CombinedErrCompletion           : Specifies if there is one combined ISR for both Completion and Error
# Mcl.eDMA.EccErrorReportingEnabled        : Specifies if there is Ecc error reporting available
# Mcl.eDMA.EnableInitDMA_DCHMID            : Specifies enable or disable initialization of DCHMID register in DMA
# Mcl.eDMA.EnableInitDMA_EARS              : Specifies if the platforms has the EARS configurable registers(DMA V2)
# Mcl.eDMA.TCD.GapBetweenChannel           : The Gap between 2 channels. For S32K2XX is 0x4000(16384), other platform are 0x1000(4096)
# Mcl.eDMA.TCD.GapBetweenGroupChannel      : The Gap between 2 group channels(16 channel in one group).For S32K2XX is 0x0x1BC000(1818624) = offset_TCD_channel_16 - offset_TCD_channel_15 - Mcl.eDMA.TCD.GapBetweenChannel
#                                          : Another platform are 0.
# Mcl.DmaMux.DmaMuxInstances               : Number of DmaMux instances 
# Mcl.DmaMux.ChannelNumberPerDmaMuxLarge   : Number of DmaMux channels for a large DmaMux instance
# Mcl.DmaMux.ChannelNumberPerDmaMuxSmall   : Number of DmaMux channels for a small DmaMux instance
# Mcl.DmaMux.NumberOfSmallDmaMuxInstances  : Number of small DmaMux instances
# Mcl.DmaMux.ChCfgAddressesLittleEndianOrder: specifies endianess of accessing to register CHCFG

# Mcl.DmaCrc.DmaCrcInstances               : Number of DmaCrc instances 
# Mcl.DmaCrc.ChannelNumberPerDmaCrc        : Number of DmaCrc channels per module
# Mcl.Crossbar.CrossbarInstances           : Number of AXBS instances
# Mcl.Crossbar.CrossbarMasters             : Number of Master in AXBS interfaces
# Mcl.Crossbar.EnableInitAXBS_MGPCR        : Specifies enable or disable initialization of AXBS_MGPCR register in AXBS
# Mcl.Crossbar.AXBS0.Slave                 : Number of Slave port in AXBS0 interfaces
# Mcl.Crossbar.AXBS1.Slave                 : Number of Slave port in AXBS1 interfaces

#Mcl.MclConfigSet.TrgMux0.Sources                           :   Selects the sources of TrgMux0
#Mcl.MclConfigSet.TrgMux0.MaximumIndexRegs                  :   Maximum of index of trgmux register which based on offset address
#Mcl.MclConfigSet.TrgMux0.NumberRegMissingSelField          :   Number of register which have missing 3 SEL field
#Mcl.MclConfigSet.TrgMux0.MaximumValueTrigger               :   Maximum of value to write into SEL field
                                           
# Mcl.Sema4.NoOfSemaphores                 : Number of Semaphores present on the platform

# Mcl.Lmem.CachePSAvailable                : Information available in LMEM IP. On some platforms, PS cache instance is available alongside with the PC cache instance.
# Mcl.Lmem.SupportSynchronizeCacheFeature  : If set to true and if the MCAL_CACHE_MANAGEMENT is also enabled in Base module, the MCL driver will Invalidate and Flush the entire cache before and after each DMA operation. (Requires the LMEM Cache APIs to be enabled)
# Mcl.Lmem.SupportWriteBufferFeature       : If set to true, whenever the cache is enable/disabled, the Write Buffer is also enabled/disabled alongside with it. This feature is usable only if the platform has cacheable writable memory (cacheable RAM). 
# Mcl.Lmem.CachePCSize                     : The entire size of the PC cache instance, in bytes.
# Mcl.Lmem.CachePSSize                     : The entire size of the PS cache instance, in bytes.
# Mcl.Lmem.CacheLineSize                   : The size of the cache line, in bytes.
################################################################################

Mcl.MclConfigSet.DmaChannels:
Mcl.MclConfigSet.DmaChannels.ACD:eDMA_0,eDMA_1,eDMA_2,eDMA_3,eDMA_4,eDMA_5,eDMA_6,eDMA_7,eDMA_8,eDMA_9,eDMA_10,eDMA_11,eDMA_12,eDMA_13,eDMA_14,eDMA_15,eDMA_16,eDMA_17,eDMA_18,eDMA_19,eDMA_20,eDMA_21,eDMA_22,eDMA_23,eDMA_24,eDMA_25,eDMA_26,eDMA_27,eDMA_28,eDMA_29,eDMA_30,eDMA_31,eDMA_32,eDMA_33,eDMA_34,eDMA_35,eDMA_36,eDMA_37,eDMA_38,eDMA_39,eDMA_40,eDMA_41,eDMA_42,eDMA_43,eDMA_44,eDMA_45,eDMA_46,eDMA_47,eDMA_48,eDMA_49,eDMA_50,eDMA_51,eDMA_52,eDMA_53,eDMA_54,eDMA_55,eDMA_56,eDMA_57,eDMA_58,eDMA_59,eDMA_60,eDMA_61,eDMA_62,eDMA_63,eDMA_64,eDMA_65,eDMA_66,eDMA_67,eDMA_68,eDMA_69,eDMA_70,eDMA_71,eDMA_72,eDMA_73,eDMA_74,eDMA_75,eDMA_76,eDMA_77,eDMA_78,eDMA_79,eDMA_80,eDMA_81,eDMA_82,eDMA_83,eDMA_84,eDMA_85,eDMA_86,eDMA_87,eDMA_88,eDMA_89,eDMA_90,eDMA_91,eDMA_92,eDMA_93,eDMA_94,eDMA_95,eDMA_96,eDMA_97,eDMA_98,eDMA_99,eDMA_100,eDMA_101,eDMA_102,eDMA_103,eDMA_104,eDMA_105,eDMA_106,eDMA_107,eDMA_108,eDMA_109,eDMA_110,eDMA_111,eDMA_112,eDMA_113,eDMA_114,eDMA_115,eDMA_116,eDMA_117,eDMA_118,eDMA_119,eDMA_120,eDMA_121,eDMA_122,eDMA_123,eDMA_124,eDMA_125,eDMA_126,eDMA_127
Mcl.MclConfigSet.DmaInstances:eDMA_Instance0,eDMA_Instance1
Mcl.MclConfigSet.DmaInstancesV3:0
Mcl.MclConfigSet.DmaInstancesV2:2
Mcl.MclConfigSet.DmaInstances.Version:eDMA_v2,eDMA_v2
Mcl.MclConfigSet.DmaInstances.Type:eDMA_v2
Mcl.MclConfigSet.DmaMux0.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux1.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux2.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux3.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux4.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux5.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux6.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux7.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux8.Sources:NOT_USED
Mcl.MclConfigSet.DmaMux9.Sources:NOT_USED
Mcl.eDMA.MaxPriorityGroupId:3
Mcl.eDMA.PriorityGroup0Exists:true
Mcl.eDMA.PriorityGroup1Exists:true
Mcl.eDMA.PriorityGroup2Exists:true
Mcl.eDMA.PriorityGroup3Exists:true

Mcl.eDMA.TransferSizeInBytes:1,2,4,8,16,32,64
Mcl.eDMA.ChannelNumberMain:0
Mcl.eDMA.ChannelNumberAcd:128
Mcl.eDMA.ChannelNumberPerDmaInstance:64
Mcl.eDMA.ChannelNumberPerDmaInstanceMain:0
Mcl.eDMA.ChannelNumberPerDmaInstanceAcd:64
Mcl.eDMA.ChannelNumberPerGroup:16
Mcl.eDma.Group:8

Mcl.eDMA.OffsetAEAreaAcd:0
Mcl.eDMA.CombinedErrorIsr:1
Mcl.eDMA.CombinedErrCompletion:1
Mcl.eDMA.CombinedTrCompletionIsr:0
Mcl.eDMA.CombinedGroupCompletionIsr:1
Mcl.eDMA.CombinedTrComplMixedIsr:0
Mcl.eDMA.GroupAcdIsr:1

Mcl.eDMA.EccErrorReportingEnabled:1
Mcl.eDMA.EnableInitDMA_DCHMID:0
Mcl.eDMA.EnableInitDMA_EARS:0
Mcl.eDMA.TCD.GapBetweenChannel:4096
Mcl.eDMA.TCD.GapBetweenGroupChannel:0

Mcl.DmaMux.DmaMuxInstances:0
Mcl.DmaMux.ChannelNumberPerDmaMuxLarge:
Mcl.DmaMux.ChannelNumberPerDmaMuxSmall:
Mcl.DmaMux.NumberOfSmallDmaMuxInstances:
Mcl.DmaMux.ChCfgAddressesLittleEndianOrder:
Mcl.DmaMux.TriggerEnableHwChannel:

Mcl.DmaCrc.DmaCrcInstances:0
Mcl.DmaCrc.ChannelNumberPerDmaCrc:0

Mcl.Sema4.NoOfSemaphores:64
Mcl.Sema42.Support:0


Mcl.MclConfigSet.TrgMux0.Sources:None
Mcl.MclConfigSet.TrgMux0.MaximumIndexRegs:0
Mcl.MclConfigSet.TrgMux0.NumberRegMissingSelField:0
Mcl.MclConfigSet.TrgMux0.MaximumValueTrigger:0
Mcl.MclConfigSet.TrgMux0.RegOneInput:None
Mcl.MclConfigSet.TrgMux0.RegTwoInput:None
Mcl.MclConfigSet.TrgMux0.RegThreeInput:None
Mcl.MclConfigSet.TrgMux0.ListOfReg:None

Mcl.Crossbar.CrossbarNumInstances:1
Mcl.Crossbar.PRS.IsReadOnly:0
Mcl.Crossbar.CrossbarInstances:AXBS_0
Mcl.Crossbar.CrossbarMasters:Master0,Master1,Master2,Master3,Master4,Master5,Master6,Master7
Mcl.Crossbar.AXBS0.Masters:Master0,Master1,Master2,Master3,Master4,Master5,Master6,Master7
Mcl.Crossbar.AXBS1.Masters:NaN
Mcl.Crossbar.EnableInitAXBS_MGPCR:0
Mcl.Crossbar.AXBS0.Slave:0,2,3,4,6,7
Mcl.Crossbar.AXBS1.Slave:NaN
Mcl.CrossbarInstance0.PRS.PRSResetValue:0x76543210
Mcl.CrossbarInstance0.CRS.CRSResetValue:0x00FF0000
Mcl.CrossbarInstance0.PRS.MaxlevelPriority:7
Mcl.Crossbar.HaltLowPrioritySupport:1

Mcl.Ipv.UserMode.Available:DMA_MUX,AXBS,LMEM,TRGMUX,M7
Mcl.Ipv.RegProt.Available:DMA_MUX,DMA

#User need to specify which core mcl currently run on, this spec define core specs according to core ID 
#for example: Core0 is M33_0 Core1 is M33_1 Core 2 is M7 so we will have Mcl.CoreInfo:M33_0,M33_1,M7,HSE

Mcl.CacheCoreAvailable:None

Mcl.Lmem.CachePSAvailable:None
Mcl.Lmem.SupportSynchronizeCacheFeature:None
Mcl.Lmem.SupportWriteBufferFeature:None
Mcl.Lmem.CachePCSize:0
Mcl.Lmem.CachePSSize:0
Mcl.Lmem.CacheLineSize:0

Mcl.M7.CacheAvailable:None
Mcl.M7.CacheDataSize:0
Mcl.M7.CacheInstructionSize:0
Mcl.M7.CacheLineSize:0
######################  mpc5775e_mapbga416 Mcl module: END  ###########################################  mpc5777e_mapbga416 Port module  ##########################################
#
# PortPackage                       : Port Package
# PortMaxPinNumber                  : The index of the last supported pin
# PortNotAvailablePins              : List of pins that cannot be configured for this derivative
# PortPin16BlocksNo                 : Number of ports (lenght 16 units) in the platform
# PortPadModeNumber                 : Number of alternative functions for a pad
# PortMaxInmuxRegs                  : Number of Inmux regs
# PortUnimplementedPads             : List of the pins not implemented on the platform
# PortOnlyInputPins                 : List of the pins used as GPI
# PortNoGpioPins                    : List of the pins that do not have GPIO functionality
# PortPcrIdxStart                   : List with first PCR indexes
# PortPcrIdxEnd                     : List with last PCR indexes
################################################################################################
PortPackage:Port_mapbga416
PortMaxPinNumber:491
PortNotAvailablePins:0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,111,112,205,206,207,211,215,216,217,218,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,438,439,473
PortPin16BlocksNo:31
PortPadModeNumber:10
PortMaxInmuxRegs:195
PortUnimplementedPads:0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,111,112,205,206,207,215,216,217,218,254,255,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,438,439,473
PortOnlyInputPins:440,441,442,444,450,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491
PortNoGpioPins:214,219,224,225,226,227,228,229,230
PortPcrIdxStart                     : 75
PortPcrIdxEnd                       : 491

######################  mpc5777e_mapbga416 Port module: END  #####################################
#####################   mpc5775e_mapbga416 Pwm module   ##########################

Pwm.Num_eMios_Hw_Modules: 2
Pwm.eMios_Hw_Modules: eMios_0, eMios_1
Pwm.Num_eMios_Hw_Channels: 32
Pwm.eMios_Hw_Channels: Channel_0, Channel_1, Channel_2, Channel_3, Channel_4, Channel_5, Channel_6, Channel_7, Channel_16, Channel_17, Channel_18, Channel_19, Channel_20, Channel_21, Channel_22, Channel_23
Pwm.eMios_Hw_MasterBuses: Channel_0, Channel_16, Channel_23
Pwm.OperationModes: PWM_MODE_OPWFMB_U32, PWM_MODE_OPWFM_U32, PWM_MODE_OPWMB_U32, PWM_MODE_OPWM_U32, PWM_MODE_OPWMCB_LEAD_DEADTIME_U32, PWM_MODE_OPWMCB_TRAIL_DEADTIME_U32, PWM_MODE_DAOC_U32
Pwm.TimerPrecision: PWM_16BIT, PWM_24BIT

Pwm.HwChannel_List:EMIOS_0_CH_0,EMIOS_0_CH_1,EMIOS_0_CH_2,EMIOS_0_CH_3,EMIOS_0_CH_4,EMIOS_0_CH_5,EMIOS_0_CH_6,EMIOS_0_CH_7,EMIOS_0_CH_16,EMIOS_0_CH_17,EMIOS_0_CH_18,EMIOS_0_CH_19,EMIOS_0_CH_20,EMIOS_0_CH_21,EMIOS_0_CH_22,EMIOS_0_CH_23,EMIOS_1_CH_0,EMIOS_1_CH_1,EMIOS_1_CH_2,EMIOS_1_CH_3,EMIOS_1_CH_4,EMIOS_1_CH_5,EMIOS_1_CH_6,EMIOS_1_CH_7,EMIOS_1_CH_16,EMIOS_1_CH_17,EMIOS_1_CH_18,EMIOS_1_CH_19,EMIOS_1_CH_20,EMIOS_1_CH_21,EMIOS_1_CH_22,EMIOS_1_CH_23



###################   mpc5775e_mapbga416 Pwm module: END  #############################################  mpc5777c_mapbga516 Spi module  ##########################
#
# Spi.SpiGeneral.SpiPhyUnit.SpiPhyUnitMapping       : list of available DSPI
# Spi.SpiGeneral.SpiPhyUnit.TSBSupportedUnits       : the list of TSB-supported DSPIs
# Spi.SpiGeneral.SpiPhyUnit.NrCTAR                  : number of CTAR registers available for the DSPI units
# SpiDMAPresent                                     : DMA support for SPI peripheral(s)
# Spi.SpiDriver.SpiExternalDevice.SpiHwUnit         : the list of AUTOSAR comaptible pheripherals present
# SpiNumberOfUnits                                  : Number of available SPI HW units on this derivative
# SpiFifoSize                                       : TX/RX FIFO with depth of 4 entries
# SpiPCSNumber                                      : Number of peripheral chip selects
# SpiTSBSupport                                     : Support for Timed Serial Bus
# SpiITSBSupport                                    : Support for Interleaved TSB (ITSB) Mode
# SpiITSBTimeSlotSupport                            : Support configuration Time Slot mode in ITSB
#
################################################################################

Spi.SpiGeneral.SpiPhyUnit.SpiPhyUnitMapping:DSPI_A,DSPI_B,DSPI_C,DSPI_D,DSPI_E
Spi.SpiGeneral.SpiPhyUnit.TSBSupportedUnits:DSPI_A,DSPI_B,DSPI_C,DSPI_D
Spi.SpiGeneral.SpiPhyUnit.NrCTAR:8,8,8,8,8
Spi.SpiDriver.SpiExternalDevice.SpiHwUnit:CSIB0,CSIB1,CSIB2,CSIB3,CSIB4
SpiDMAPresent:TRUE
SpiNumberOfUnits:5
SpiFifoSize:4
SpiPCSNumber:6
SpiTSBSupport:TRUE
SpiITSBSupport:FALSE
SpiITSBTimeSlotSupport:FALSE

######################  mpc5777c_mapbga516 Spi module: END  ##########################################  mpc5775e_mapbga416 Wdg module  ##########################
#
# Wdg.WdgInstance : list of available HW instances
# Wdg.DebugMode : list of HW instances have debug mode support
# Wdg.StopMode : list of HW instances have stop mode support
#
################################################################################

Wdg.WdgInstance:SWT0,SWT1
Wdg.DebugMode:NaN
Wdg.StopMode:SWT0,SWT1

Swt.MinVal.TimeOut:256
######################  mpc5775e_mapbga416 Wdg module: END  ###########################################  Eth_mpc5775e_mapbga416  Eth module  ##########################
# 
# Eth.EthGeneral.MaxControllerSupport               : number of available ENET controllers
# Eth.EthConfigSet.EthCtrlConfig.SupportRMIIList    : Support RMII on each ENET controller
# Eth.EthConfigSet.EthCtrlConfig.SupportMDIOList    : Support MDIO on each ENET controller
#
################################################################################

Eth.EthGeneral.MaxControllerSupport:1

Eth.EthGeneral.BufferDescriptorSize:8

Eth.EthGeneral.GigabitSupport:STD_OFF

Eth.EthGeneral.MaxTxQueueSupport:1

Eth.EthGeneral.MaxRxQueueSupport:1

######################  Eth_mpc5775e_mapbga416  Eth module: END  #####################
#####################  mpc5777e_mapbga416 Mcem module  ##########################
#
# Mcem.McemConfigSet.Fault.SignalDesc : List of Mcem Non-critical Faults
# Mcem.McemGeneral.FccuUnderRegPotList: Define only when FCCU register is protected by REGPROT
#
################################################################################

Mcem.McemConfigSet.Fault.SignalDesc:\
    MCEM_FCCU_TEMP_ERROR,\
    MCEM_FCCU_LVD_ERROR,\
    MCEM_FCCU_HVD_ERROR,\
    MCEM_FCCU_DPMC_SELF_TEST,\
    MCEM_FCCU_MEMORY_DCF_SAFETY_ERR,\
    MCEM_FCCU_SSCM_XFER_ERR,\
    MCEM_FCCU_STCU_UF,\
    MCEM_FCCU_STCU_RF,\
    MCEM_FCCU_STCU_LMBIST_USR_ERR,\
    MCEM_FCCU_SPURIOUS_DEBUG_SSCM_ACTIVATION,\
    MCEM_FCCU_RCCU_0,\
    MCEM_FCCU_RCCU_1,\
    MCEM_FCCU_WDRS_DBRC0,\
    MCEM_FCCU_WDRS_DBRC1,\
    MCEM_FCCU_SWTRS0,\
    MCEM_FCCU_SWTRS1,\
    MCEM_FCCU_SWTINT0,\
    MCEM_FCCU_FLASH_INIT,\
    MCEM_FCCU_SSCM_INIT,\
    MCEM_FCCU_PER_CE,\
    MCEM_FCCU_PER_UCE,\
    MCEM_FCCU_FLS_CE,\
    MCEM_FCCU_FLS_UCE,\
    MCEM_FCCU_PLL_0,\
    MCEM_FCCU_PLL_1,\
    MCEM_FCCU_CMU_0_OSC,\
    MCEM_FCCU_CMU_0_PLL,\
    MCEM_FCCU_CMU_COMP,\
    MCEM_FCCU_CMU_OTHER,\
    MCEM_FCCU_EDC_ECC_FLASH,\
    MCEM_FCCU_EDC_ECC_FLASH_C,\
    MCEM_FCCU_ENC_ERR_FLASH,\
    MCEM_FCCU_ADDR_FDBK_ERR_FLASH_C,\
    MCEM_FCCU_XBAR_TRANSACTION_MONITOR,\
    MCEM_FCCU_ADDR_FDBK_ERR_PRAM_RAM_LWB_ERR,\
    MCEM_FCCU_SSCM_PASS_ECC_ERR,\
    MCEM_FCCU_EDC_ERR_PRAM,\
    MCEM_FCCU_DFT1,\
    MCEM_FCCU_DFT2,\
    MCEM_FCCU_DFT3,\
    MCEM_FCCU_DFT4,\
    MCEM_FCCU_SAFETY_CORE_MACHINE_CHECK_EXCEPTION,\
    MCEM_FCCU_LOCKSTEP_MODE,\
    MCEM_FCCU_ERROR_IN_ERR,\
    MCEM_FCCU_RESERVED_44,\
    MCEM_FCCU_ERM_CE,\
    MCEM_FCCU_ERM_UCE
Mcem.McemGeneral.FccuSupport:STD_ON
Mcem.McemGeneral.FccuUnderRegPotList:STD_OFF
Mcem.McemGeneral.FaultReservedMasks:0xFFFFFFFFU, 0x00006FFFU, 0x00000000U, 0x00000000U, 0x00000000U
######################  mpc5777e_mapbga416 Mcem module: END  #####################
######################  Ocu_mpc5775e_mapbga416 Ocu module  ##############################
# Ocu.Num_eMios_Hw_Modules:   Number of eMios modules
# Ocu.Num_eMios_Hw_Channels:  Number of eMios channels per module
# Ocu.eMios_Hw_Modules:       List of names for of eMios modules
# Ocu.eMios_Hw_Channels:      List of names for of eMios channels
# Ocu.eMios_Hw_Channels_List: List of all HW channels to be referenced for logical level
# Ocu.ISR_List:               List of all available interrupts. 
#########################################################################################
Ocu.Num_eMios_Hw_Modules:2
Ocu.Num_eMios_Hw_Channels:32
Ocu.eMios_Hw_Modules:EMIOS_0, EMIOS_1
Ocu.eMios_Hw_Channels:CH_0,CH_1,CH_2,CH_3,CH_4,CH_5,CH_6,CH_7,CH_16,CH_17,CH_18,CH_19,CH_20,CH_21,CH_22,CH_23
Ocu.eMios_Hw_MasterBuses:CH_0,CH_16,CH_23
Ocu.eMios_Hw_Channels_List:EMIOS_0_CH_0,EMIOS_0_CH_1,EMIOS_0_CH_2,EMIOS_0_CH_3,EMIOS_0_CH_4,EMIOS_0_CH_5,EMIOS_0_CH_6,EMIOS_0_CH_7,EMIOS_0_CH_16,EMIOS_0_CH_17,EMIOS_0_CH_18,EMIOS_0_CH_19,EMIOS_0_CH_20,EMIOS_0_CH_21,EMIOS_0_CH_22,EMIOS_0_CH_23,EMIOS_1_CH_0,EMIOS_1_CH_1,EMIOS_1_CH_2,EMIOS_1_CH_3,EMIOS_1_CH_4,EMIOS_1_CH_5,EMIOS_1_CH_6,EMIOS_1_CH_7,EMIOS_1_CH_16,EMIOS_1_CH_17,EMIOS_1_CH_18,EMIOS_1_CH_19,EMIOS_1_CH_20,EMIOS_1_CH_21,EMIOS_1_CH_22,EMIOS_1_CH_23
Ocu.ISR_List:EMIOS_0_CH_0_ISR, EMIOS_0_CH_1_ISR, EMIOS_0_CH_2_ISR, EMIOS_0_CH_3_ISR, EMIOS_0_CH_4_ISR, EMIOS_0_CH_5_ISR, EMIOS_0_CH_6_ISR, EMIOS_0_CH_7_ISR, EMIOS_0_CH_16_ISR, EMIOS_0_CH_17_ISR, EMIOS_0_CH_18_ISR, EMIOS_0_CH_19_ISR, EMIOS_0_CH_20_ISR, EMIOS_0_CH_21_ISR, EMIOS_0_CH_22_ISR, EMIOS_0_CH_23_ISR, EMIOS_1_CH_0_ISR, EMIOS_1_CH_1_ISR, EMIOS_1_CH_2_ISR, EMIOS_1_CH_3_ISR, EMIOS_1_CH_4_ISR, EMIOS_1_CH_5_ISR, EMIOS_1_CH_6_ISR, EMIOS_1_CH_7_ISR, EMIOS_1_CH_16_ISR, EMIOS_1_CH_17_ISR, EMIOS_1_CH_18_ISR, EMIOS_1_CH_19_ISR, EMIOS_1_CH_20_ISR, EMIOS_1_CH_21_ISR, EMIOS_1_CH_22_ISR, EMIOS_1_CH_23_ISR
Ocu.ChannelType.EMIOS_0_CH_0: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_1: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_2: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_3: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_4: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_5: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_6: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_7: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_16: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_17: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_18: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_19: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_20: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_21: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_22: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_0_CH_23: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_0: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_1: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_2: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_3: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_4: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_5: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_6: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_7: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_16: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_17: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_18: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_19: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_20: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_21: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_22: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
Ocu.ChannelType.EMIOS_1_CH_23: EMIOS_BUS_A, EMIOS_BUS_DIVERSE, EMIOS_BUS_INTERNAL_COUNTER
######################  Ocu_mpc5775e_mapbga416 Ocu module: END  #####################
