/**************************************************************************/
/* FILE NAME: mpc577xC.h                     COPYRIGHT (c) Freescale 2013 */
/* VERSION:  1.3                                  All Rights Reserved     */
/*                                                                        */
/* DESCRIPTION:                                                           */
/* This file contains all of the register and bit field definitions for   */
/* MPC577xC.                                                              */
/*========================================================================*/
/* UPDATE HISTORY                                                         */
/* REV     AUTHOR      DATE      DESCRIPTION OF CHANGE                    */
/* ---  -----------  ---------   ---------------------                    */
/* 0.1  D. Erazmus   08/Jan/2013 Initial revision based on MPC567xR and   */
/*                               MPC57xx family header files.             */
/* 0.2  D. Erazmus   17/Apr/2013 Added changes to SIU for MPC577xC.       */
/* 0.3  D. Erazmus   29/Apr/2013 Added FEC.                               */
/* 0.4  D. Erazmus   23/Aug/2013 Added remaining modules except for CSE2, */
/*                               SSCM, PASS, LFAST, EIM/ERM, PMC, PCM,    */
/*                               and TDM.                                 */
/* 0.5  D. Erazmus   30/Aug/2013 Added CSE2, PASS, LFAST, EIM/ERM, and TDM*/
/* 0.6  D. Erazmus   05/Sep/2013 Added all remaining modules.             */
/* 0.7  D. Erazmus   09/Sep/2013 Fixes for EIM/ERM and PCM.               */
/* 0.8  D. Erazmus   13/Sep/2013 Changed numbering of PCM registers to    */
/*                               match documentation.                     */
/* 0.9  D. Erazmus   19/Nov/2013 Added missing HLTACK2 register name.     */
/* 1.0  D. Erazmus   16/Dec/2013 Updated STCU2 definition for MPC577xC.   */
/* 1.1  D. Erazmus   18/Feb/2014 Added missing SIU_ECCEIR and SIU_FECCR   */
/* 1.2  D. Erazmus   27/Feb/2014 Added missing EMIOS_UCDIS                */
/* 1.3  D. Erazmus   28/Mar/2014 Updated SRX from newer RM source.        */
/**************************************************************************/

#ifndef _MPC577xC_H_
#define _MPC577xC_H_

#include "typedefs.h"

#ifdef  __cplusplus
extern "C" {
#endif

#ifdef __MWERKS__
#pragma push
#pragma ANSI_strict off
#endif

/****************************************************************************/
/*            MODULE : Platform Configuration Module (PCM)                  */
/****************************************************************************/
struct PCM_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t  :21;          /*  */
        vuint32_t ACCERR:1;          /*  */
        vuint32_t WBEN:1;          /*  */
        vuint32_t RBEN:1;          /*  */
        vuint32_t FXSBE:8;           /*  */
    } B;
  } FBOMCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :5;           /*  */
        vuint32_t PRE_CORE1_D:1;     /* Pending read enable (PRE) Core 1 Data */
        vuint32_t BRE_CORE1_D:1;     /* Burst read enable (BRE) Core 1 Data */
        vuint32_t BWE_CORE1_D:1;     /* Burst write enable (BWE) Core 1 Data */
        vuint32_t  :5;           /*  */
        vuint32_t PRE_CORE1_I:1;     /* Pending read enable (PRE) Core 1 Instruction */
        vuint32_t BRE_CORE1_I:1;     /* Burst read enable (BRE) Core 1 Instruction */
        vuint32_t BWE_CORE1_I:1;     /* Burst write enable (BWE) Core 1 Instruction */
        vuint32_t  :5;           /*  */
        vuint32_t PRE_CORE0_D:1;     /* Pending read enable (PRE) Core 0 Data */
        vuint32_t BRE_CORE0_D:1;     /* Burst read enable (BRE) Core 0 Data */
        vuint32_t BWE_CORE0_D:1;     /* Burst write enable (BWE) Core 0 Data */
        vuint32_t  :5;           /*  */
        vuint32_t PRE_CORE0_I:1;     /* Pending read enable (PRE) Core 0 Instruction */
        vuint32_t BRE_CORE0_I:1;     /* Burst read enable (BRE) Core 0 Instruction */
        vuint32_t BWE_CORE0_I:1;     /* Burst write enable (BWE) Core 0 Instruction */
    } B;
  } IAHB_BE1;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :5;           /*  */
        vuint32_t PRE_FEC:1;       /* Pending read enable (PRE) FEC */
        vuint32_t BRE_FEC:1;       /* Burst read enable (BRE) FEC */
        vuint32_t BWE_FEC:1;       /* Burst write enable (BWE) FEC */
        vuint32_t  :5;           /*  */
        vuint32_t PRE_M6:1;        /* Pending read enable (PRE) M6 Concentrator */
        vuint32_t BRE_M6:1;        /* Burst read enable (BRE) M6 Concentrator */
        vuint32_t BWE_M6:1;        /* Burst write enable (BWE) M6 Concentrator */
        vuint32_t  :5;           /*  */
        vuint32_t PRE_DMA_B:1;     /* Pending read enable (PRE) DMA B */
        vuint32_t BRE_DMA_B:1;     /* Burst read enable (BRE) DMA B */
        vuint32_t BWE_DMA_B:1;     /* Burst write enable (BWE) DMA B */
        vuint32_t  :5;           /*  */
        vuint32_t PRE_DMA_A:1;     /* Pending read enable (PRE) DMA A */
        vuint32_t BRE_DMA_A:1;     /* Burst read enable (BRE) DMA A */
        vuint32_t BWE_DMA_A:1;     /* Burst write enable (BWE) DMA A */
    } B;
  } IAHB_BE2;
};

/****************************************************************************/
/*        MODULE : System Status and Configuration Module (SSCM)            */
/****************************************************************************/
struct SSCM_tag {
  union {
    vuint16_t R;
      struct {
        vuint16_t  :1;           /*  */
        vuint16_t CER:1;           /* Configuration Error */
        vuint16_t  :1;           /*  */
        vuint16_t NXEN1:1;           /* Processor 1 Nexus enable status */
        vuint16_t NXEN:1;          /* Processor 0 Nexus enable status */
        vuint16_t  :11;          /*  */
    } B;
  } STATUS;

  uint8_t SSCM_reserved0[4];
  union {
    vuint16_t R;
      struct {
        vuint16_t  :14;          
        vuint16_t PAE:1;           
        vuint16_t RAE:1;           
    } B;
  } ERROR;

  uint8_t SSCM_reserved1[44];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :22;          /*  */
        vuint32_t PLC:2;           /* Pre-Life Cycle */
        vuint32_t  :5;           /*  */
        vuint32_t LC:3;          /* Life Cycle */
    } B;
  } LCSTAT;

};

/****************************************************************************/
/*            MODULE : Password and Device Security Module (PASS)           */
/****************************************************************************/
struct PASS_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t CNS:1;           /*  */
        vuint32_t JUN:1;           /*  */
        vuint32_t  :27;          /*  */
        vuint32_t LIFE:3;          /*  */
    } B;
  } LCSTAT;

  uint8_t PASS_reserved0[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :30;          /*  */
        vuint32_t GRP:2;           /*  */
    } B;
  } CHSEL;

  uint8_t PASS_reserved1[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :28;          /*  */
        vuint32_t CMST:4;          /*  */
    } B;
  } CSTAT;

  uint8_t PASS_reserved2[12];
  union {
    vuint32_t R;
      struct {
        vuint32_t PW32:32;           /*  */
    } B;
  } CIN[8];

  uint8_t PASS_reserved3[192];
  struct {
    union {
      vuint32_t R;
        struct {
          vuint32_t TSLOCK:1;          /*  */
          vuint32_t:1;           /*  */
          vuint32_t LOWLOCK:14;          /*  */
          vuint32_t MIDLOCK:16;          /*  */
      } B;
    } LOCK0;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :16;          /*  */
          vuint32_t HIGHLOCK:16;           /*  */
      } B;
    } LOCK1;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t L_256LCK:32;           /*  */
      } B;
    } LOCK2;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t PGL:1;           /*  */
          vuint32_t DBL:1;           /*  */
          vuint32_t MO:1;          /*  */
          vuint32_t  :1;           /*  */
          vuint32_t MSTR:4;          /*  */
          vuint32_t  :4;           /*  */
          vuint32_t RL3:1;           /*  */
          vuint32_t RL2:1;           /*  */
          vuint32_t RL1:1;           /*  */
          vuint32_t RL0:1;           /*  */
          vuint32_t U_256LCK:16;           /*  */
      } B;
    } LOCK3;
  } PG[4];
};

/****************************************************************************/
/*        MODULE : LVDS Fast Asynchronous Serial Transmission (LFAST)       */
/****************************************************************************/
struct LFAST_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t MSEN:1;          
        vuint32_t  :6;           
        vuint32_t IPGDBG:1;          
        vuint32_t  :7;           
        vuint32_t LSSEL:1;           
        vuint32_t DRFEN:1;           
        vuint32_t RXEN:1;          
        vuint32_t TXEN:1;          
        vuint32_t  :8;           
        vuint32_t TXARBD:1;          
        vuint32_t CTSEN:1;           
        vuint32_t  :1;           
        vuint32_t DRFRST:1;          
        vuint32_t DATAEN:1;          
    } B;
  } MCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t DRMD:1;          
        vuint32_t  :7;           
        vuint32_t RDR:1;           
        vuint32_t  :7;           
        vuint32_t TDR:1;           
    } B;
  } SCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t SMPSEL:8;          
        vuint32_t  :6;           
        vuint32_t  :2;           
        vuint32_t  :12;          
        vuint32_t CORRTH:3;          
        vuint32_t PHSSEL:1;          
    } B;
  } COCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :6;           
        vuint32_t CLKTST:1;          
        vuint32_t LPON:1;          
        vuint32_t  :5;           
        vuint32_t LPMOD:3;           
        vuint32_t LPFRMTH:16;          
    } B;
  } TMCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t LPCNTEN:1;           
        vuint32_t LPFMCNT:16;          
    } B;
  } ALCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DRCNT:4;           
        vuint32_t  :16;          
    } B;
  } RCDCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t HSCNT:8;           
        vuint32_t  :4;           
        vuint32_t LSCNT:4;           
        vuint32_t HWKCNT:8;          
        vuint32_t  :4;           
        vuint32_t LWKCNT:4;          
    } B;
  } SLCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :14;          
        vuint32_t ICLCSEQ:1;           
        vuint32_t SNDICLC:1;           
        vuint32_t  :8;           
        vuint32_t ICLCPLD:8;           
    } B;
  } ICR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t PNGREQ:1;          
        vuint32_t PNGAUTO:1;           
        vuint32_t  :7;           
        vuint32_t PNGPYLD:8;           
    } B;
  } PICR;

  uint8_t LFAST_reserved0[8];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :10;          
        vuint32_t RCTSMX:6;          
        vuint32_t  :10;          
        vuint32_t RCTSMN:6;          
    } B;
  } RFCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :14;          
        vuint32_t TXIIE:1;           
        vuint32_t TXOVIE:1;          
        vuint32_t  :11;          
        vuint32_t TXPNGIE:1;           
        vuint32_t  :1;           
        vuint32_t TXUNSIE:1;           
        vuint32_t TXICLCIE:1;          
        vuint32_t TXDTIE:1;          
    } B;
  } TIER;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :8;           
        vuint32_t RXUOIE:1;          
        vuint32_t RXMNIE:1;          
        vuint32_t RXMXIE:1;          
        vuint32_t RXUFIE:1;          
        vuint32_t RXOFIE:1;          
        vuint32_t RXSZIE:1;          
        vuint32_t RXICIE:1;          
        vuint32_t RXLCEIE:1;           
        vuint32_t  :12;          
        vuint32_t RXCTSIE:1;           
        vuint32_t RXDIE:1;           
        vuint32_t RXUNSIE:1;           
        vuint32_t  :1;           
    } B;
  } RIER;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :18;          
        vuint32_t ICPFIE:1;          
        vuint32_t ICPSIE:1;          
        vuint32_t ICPRIE:1;          
        vuint32_t ICTOIE:1;          
        vuint32_t ICLPIE:1;          
        vuint32_t ICCTIE:1;          
        vuint32_t ICTDIE:1;          
        vuint32_t ICTEIE:1;          
        vuint32_t ICRFIE:1;          
        vuint32_t ICRSIE:1;          
        vuint32_t ICTFIE:1;          
        vuint32_t ICTSIE:1;          
        vuint32_t ICPOFIE:1;           
        vuint32_t ICPONIE:1;           
    } B;
  } RIIER;

  union {
    vuint32_t R;
      struct {
        vuint32_t IPTMOD:3;          
        vuint32_t  :11;          
        vuint32_t SWPOFF:1;          
        vuint32_t SWPON:1;           
        vuint32_t REFINV:1;          
        vuint32_t LPCFG:2;           
        vuint32_t  :2;           
        vuint32_t PLCKCW:2;          
        vuint32_t FDIVEN:1;          
        vuint32_t FBDIV:6;           
        vuint32_t PREDIV:2;          
    } B;
  } PLLCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :8;           
        vuint32_t SWWKLD:1;          
        vuint32_t SWSLPLD:1;           
        vuint32_t SWWKLR:1;          
        vuint32_t SWSLPLR:1;           
        vuint32_t SWOFFLD:1;           
        vuint32_t SWONLD:1;          
        vuint32_t SWOFFLR:1;           
        vuint32_t SWONLR:1;          
        vuint32_t LVRXOFF:1;           
        vuint32_t LVTXOE:1;          
        vuint32_t TXCMUX:1;          
        vuint32_t LVRFEN:1;          
        vuint32_t LVLPEN:1;          
        vuint32_t  :5;           
        vuint32_t LVRXOP:3;          
        vuint32_t LVTXOP:1;          
        vuint32_t LVCKSS:1;          
        vuint32_t LVCKP:1;           
    } B;
  } LCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t USNDRQ:1;          
        vuint32_t  :9;           
        vuint32_t UNSHDR:7;          
    } B;
  } UNSTCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t UNTXD:32;          
    } B;
  } UNSTDR[9];

  uint8_t LFAST_reserved1[20];
  union {
    vuint32_t R;
      struct {
        vuint32_t DUALMD:1;          
        vuint32_t  :12;          
        vuint32_t LRMD:1;          
        vuint32_t LDSM:1;          
        vuint32_t DRSM:1;          
        vuint32_t  :11;          
        vuint32_t LPTXDN:1;          
        vuint32_t LPFPDV:1;          
        vuint32_t LPCPDV:1;          
        vuint32_t LPCHDV:1;          
        vuint32_t LPCSDV:1;          
    } B;
  } GSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t RXPNGD:8;          
    } B;
  } PISR;

  uint8_t LFAST_reserved2[12];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :2;           
        vuint32_t RXDCNT:6;          
        vuint32_t  :5;           
        vuint32_t RXFCNT:3;          
        vuint32_t  :2;           
        vuint32_t TXDCNT:6;          
        vuint32_t  :5;           
        vuint32_t TXFCNT:3;          
    } B;
  } DFSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :14;          
        vuint32_t TXIEF:1;           
        vuint32_t TXOVF:1;           
        vuint32_t  :11;          
        vuint32_t TXPNGF:1;          
        vuint32_t  :1;           
        vuint32_t TXUNSF:1;          
        vuint32_t TXICLCF:1;           
        vuint32_t TXDTF:1;           
    } B;
  } TISR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :8;           
        vuint32_t RXUOF:1;           
        vuint32_t RXMNF:1;           
        vuint32_t RXMXF:1;           
        vuint32_t RXUFF:1;           
        vuint32_t RXOFF:1;           
        vuint32_t RXSZF:1;           
        vuint32_t RXICF:1;           
        vuint32_t RXLCEF:1;          
        vuint32_t  :12;          
        vuint32_t RXCTSF:1;          
        vuint32_t RXDF:1;          
        vuint32_t RXUNSF:1;          
        vuint32_t  :1;           
    } B;
  } RISR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :18;          
        vuint32_t ICPFF:1;           
        vuint32_t ICPSF:1;           
        vuint32_t ICPRF:1;           
        vuint32_t ICTOF:1;           
        vuint32_t ICLPF:1;           
        vuint32_t ICCTF:1;           
        vuint32_t ICTDF:1;           
        vuint32_t ICTEF:1;           
        vuint32_t ICRFF:1;           
        vuint32_t ICRSF:1;           
        vuint32_t ICTFF:1;           
        vuint32_t ICTSF:1;           
        vuint32_t ICPOFF:1;          
        vuint32_t ICPONF:1;          
    } B;
  } RIISR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :14;          
        vuint32_t PLLDIS:1;          
        vuint32_t PLDCR:1;           
        vuint32_t  :12;          
        vuint32_t LDSLPS:1;          
        vuint32_t LRSLPS:1;          
        vuint32_t LDPDS:1;           
        vuint32_t LRPDS:1;           
    } B;
  } PLLLSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :23;          
        vuint32_t URXDV:1;           
        vuint32_t  :5;           
        vuint32_t URPCNT:3;          
    } B;
  } UNSRSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t UNRXD:32;          
    } B;
  } UNSRDR[9];

};

/****************************************************************************/
/*                     MODULE : Error Reporting Module (ERM)                */
/****************************************************************************/
struct ERM_tag {
  union {
    vuint32_t R;
    struct {
      vuint32_t ESCIE0:1;
      vuint32_t ENCIE0:1;
      vuint32_t:2;
      vuint32_t ESCIE1:1;
      vuint32_t ENCIE1:1;
      vuint32_t:2;
      vuint32_t ESCIE2:1;
      vuint32_t ENCIE2:1;
      vuint32_t:2;
      vuint32_t ESCIE3:1;
      vuint32_t ENCIE3:1;
      vuint32_t:2;
      vuint32_t ESCIE4:1;
      vuint32_t ENCIE4:1;
      vuint32_t:2;
      vuint32_t ESCIE5:1;
      vuint32_t ENCIE5:1;
      vuint32_t:2;
      vuint32_t ESCIE6:1;
      vuint32_t ENCIE6:1;
      vuint32_t:2;
      vuint32_t ESCIE7:1;
      vuint32_t ENCIE7:1;
      vuint32_t:2;
    } B;
  } CR0;

  union {
    vuint32_t R;
    struct {
      vuint32_t ESCIE8:1;
      vuint32_t ENCIE8:1;
      vuint32_t:2;
      vuint32_t ESCIE9:1;
      vuint32_t ENCIE9:1;
      vuint32_t:2;
      vuint32_t ESCIE10:1;
      vuint32_t ENCIE10:1;
      vuint32_t:2;
      vuint32_t ESCIE11:1;
      vuint32_t ENCIE11:1;
      vuint32_t:2;
      vuint32_t ESCIE12:1;
      vuint32_t ENCIE12:1;
      vuint32_t:2;
      vuint32_t ESCIE13:1;
      vuint32_t ENCIE13:1;
      vuint32_t:2;
      vuint32_t ESCIE14:1;
      vuint32_t ENCIE14:1;
      vuint32_t:2;
      vuint32_t ESCIE15:1;
      vuint32_t ENCIE15:1;
      vuint32_t:2;
    } B;
  } CR1;

  union {
    vuint32_t R;
    struct {
      vuint32_t ESCIE16:1;
      vuint32_t ENCIE16:1;
      vuint32_t:2;
      vuint32_t ESCIE17:1;
      vuint32_t ENCIE17:1;
      vuint32_t:2;
      vuint32_t ESCIE18:1;
      vuint32_t ENCIE18:1;
      vuint32_t:2;
      vuint32_t ESCIE19:1;
      vuint32_t ENCIE19:1;
      vuint32_t:18;
    } B;
  } CR2;

  uint8_t ERM_reserved0[4];

  union {
    vuint32_t R;
    struct {
      vuint32_t SBC0:1;
      vuint32_t NCE0:1;
      vuint32_t:2;
      vuint32_t SBC1:1;
      vuint32_t NCE1:1;
      vuint32_t:2;
      vuint32_t SBC2:1;
      vuint32_t NCE2:1;
      vuint32_t:2;
      vuint32_t SBC3:1;
      vuint32_t NCE3:1;
      vuint32_t:2;
      vuint32_t SBC4:1;
      vuint32_t NCE4:1;
      vuint32_t:2;
      vuint32_t SBC5:1;
      vuint32_t NCE5:1;
      vuint32_t:2;
      vuint32_t SBC6:1;
      vuint32_t NCE6:1;
      vuint32_t:2;
      vuint32_t SBC7:1;
      vuint32_t NCE7:1;
      vuint32_t:2;
    } B;
  } SR0;

  union {
    vuint32_t R;
    struct {
      vuint32_t SBC8:1;
      vuint32_t NCE8:1;
      vuint32_t:2;
      vuint32_t SBC9:1;
      vuint32_t NCE9:1;
      vuint32_t:2;
      vuint32_t SBC10:1;
      vuint32_t NCE10:1;
      vuint32_t:2;
      vuint32_t SBC11:1;
      vuint32_t NCE11:1;
      vuint32_t:2;
      vuint32_t SBC12:1;
      vuint32_t NCE12:1;
      vuint32_t:2;
      vuint32_t SBC13:1;
      vuint32_t NCE13:1;
      vuint32_t:2;
      vuint32_t SBC14:1;
      vuint32_t NCE14:1;
      vuint32_t:2;
      vuint32_t SBC15:1;
      vuint32_t NCE15:1;
      vuint32_t:2;
    } B;
  } SR1;

  union {
    vuint32_t R;
    struct {
      vuint32_t SBC16:1;
      vuint32_t NCE16:1;
      vuint32_t:2;
      vuint32_t SBC17:1;
      vuint32_t NCE17:1;
      vuint32_t:2;
      vuint32_t SBC18:1;
      vuint32_t NCE18:1;
      vuint32_t:2;
      vuint32_t SBC19:1;
      vuint32_t NCE19:1;
      vuint32_t:18;
    } B;
  } SR2;

  uint8_t ERM_reserved1[228];

  struct {
    union {
      vuint32_t R;
      struct {
        vuint32_t EAR:32;
      } B;
    } EAR;
  
    union {
      vuint32_t R;
      struct {
        vuint32_t SYNDROME:8;
        vuint32_t:24;
      } B;
    } SYN;

    uint8_t ERM_reserved2[8];
  
  } MEMORY[20];
};

/****************************************************************************/
/*                     MODULE : Error Injection Module (EIM)                */
/****************************************************************************/
struct EIM_tag {
  union {
    vuint32_t R;
    struct {
      vuint32_t:31;
      vuint32_t GEIEN:1;
    } B;
  } EIMCR;

  union {
    vuint32_t R;
    struct {
      vuint32_t EICH0EN:1;
      vuint32_t EICH1EN:1;
      vuint32_t EICH2EN:1;
      vuint32_t EICH3EN:1;
      vuint32_t EICH4EN:1;
      vuint32_t EICH5EN:1;
      vuint32_t:26;
    } B;
  } EICHEN;

  uint8_t EIM_reserved0[248];

  struct {
    union {
      vuint32_t R;
      struct {
        vuint32_t CHKBIT_MASK:8;
        vuint32_t:24;
      } B;
    } EICHD_WORD0;
  
    union {
      vuint32_t R;
      struct {
        vuint32_t UDATA_MASK:32;
      } B;
    } EICHD_WORD1;
  
    union {
      vuint32_t R;
      struct {
        vuint32_t LDATA_MASK:32;
      } B;
    } EICHD_WORD2;
    
    uint8_t EIM_reserved1[244];
    
  } CH[6];
};

/****************************************************************************/
/*                     MODULE : Tamper Detect Module (TDM)                  */
/****************************************************************************/
struct TDM_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          /*  */
        vuint32_t TDRSR5:1;          /*  */
        vuint32_t TDRSR4:1;          /*  */
        vuint32_t TDRSR3:1;          /*  */
        vuint32_t TDRSR2:1;          /*  */
        vuint32_t TDRSR1:1;          /*  */
        vuint32_t TDRSR0:1;          /*  */
    } B;
  } TDRSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :8;           /*  */
        vuint32_t LFPAR:24;          /*  */
    } B;
  } LFPAR;
};

/****************************************************************************/
/*                     MODULE : Cryptographic Services Engine (CSE)         */
/****************************************************************************/
struct CSE_tag {
  union {
    vuint32_t R;
    struct {
      vuint32_t:16;
      vuint32_t DIV:8;
      vuint32_t:2;
      vuint32_t KBS:1;
      vuint32_t SFE:1;
      vuint32_t MDIS:1;
      vuint32_t SUB:1;
      vuint32_t DRE:1;
      vuint32_t CIE:1;
    } B;
  } CR;

  union {
    vuint32_t R;
    struct {
      vuint32_t:23;
      vuint32_t EX:1;
      vuint32_t IDB:1;
      vuint32_t EDB:1;
      vuint32_t RIN:1;
      vuint32_t BOK:1;
      vuint32_t BFN:1;
      vuint32_t BIN:1;
      vuint32_t SB:1;
      vuint32_t BSY:1;
    } B;
  } SR;

  union {
    vuint32_t R;
    struct {
      vuint32_t:31;
      vuint32_t CIF:1;
    } B;
  } IR;

  union {
    vuint32_t R;
    struct {
      vuint32_t:27;
      vuint32_t EC:5;
    } B;
  } ECR;

  uint8_t CSE_reserved0[16];

  union {
    vuint32_t R;
    struct {
      vuint32_t:27;
      vuint32_t CMD:5;
    } B;
  } CMD;

  union {
    vuint32_t R;
    struct {
      vuint32_t PARM:32;
    } B;
  } P1;

  union {
    vuint32_t R;
    struct {
      vuint32_t PARM:32;
    } B;
  } P2;

  union {
    vuint32_t R;
    struct {
      vuint32_t PARM:32;
    } B;
  } P3;

  union {
    vuint32_t R;
    struct {
      vuint32_t PARM:32;
    } B;
  } P4;

  union {
    vuint32_t R;
    struct {
      vuint32_t PARM:32;
    } B;
  } P5;
};

/****************************************************************************/
/*                     MODULE : JTAG Data Communication (JDC)               */
/****************************************************************************/
struct JDC_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t JIN_IEN:1;           
        vuint32_t  :15;          
        vuint32_t JOUT_IEN:1;          
    } B;
  } MCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :13;          
        vuint32_t JIN_RDY:1;           
        vuint32_t  :1;           
        vuint32_t JIN_INT:1;           
        vuint32_t  :13;          
        vuint32_t JOUT_RDY:1;          
        vuint32_t  :1;           
        vuint32_t JOUT_INT:1;          
    } B;
  } MSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t JOUT_IPSData:32;           
    } B;
  } JOUT_IPS;

  union {
    vuint32_t R;
      struct {
        vuint32_t JIN_IPSData:32;          
    } B;
  } JIN_IPS;

};

/****************************************************************************/
/*                     MODULE : Progressive Clock Switch (PCS)              */
/****************************************************************************/
struct PCS_tag {
  union {
    vuint8_t R;
      struct {
        vuint8_t SDUR:8;           
    } B;
  } PCS_SDUR;

  uint8_t PCS_reserved1[3];
  union {
    vuint32_t R;
      struct {
        vuint32_t INIT:16;           
        vuint32_t  :8;           
        vuint32_t RATE:8;          
    } B;
  } PCS_DIVC1;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DIVS:20;           
    } B;
  } PCS_DIVS1;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DIVE:20;           
    } B;
  } PCS_DIVE1;

  union {
    vuint32_t R;
      struct {
        vuint32_t INIT:16;           
        vuint32_t  :8;           
        vuint32_t RATE:8;          
    } B;
  } PCS_DIVC2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DIVS:20;           
    } B;
  } PCS_DIVS2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DIVE:20;           
    } B;
  } PCS_DIVE2;

  union {
    vuint32_t R;
      struct {
        vuint32_t INIT:16;           
        vuint32_t  :8;           
        vuint32_t RATE:8;          
    } B;
  } PCS_DIVC3;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DIVS:20;           
    } B;
  } PCS_DIVS3;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t DIVE:20;           
    } B;
  } PCS_DIVE3;

};

/****************************************************************************/
/*                     MODULE : SIPI                                        */
/****************************************************************************/
struct SIPI_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t TC:1;          
        vuint32_t  :8;           
        vuint32_t WL:2;          
        vuint32_t CHEN:1;          
        vuint32_t ST:1;          
        vuint32_t IDT:1;           
        vuint32_t RRT:1;           
        vuint32_t WRT:1;           
        vuint32_t DEN:1;           
    } B;
  } CCR0;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t RAR:1;           
        vuint32_t TID:3;           
        vuint32_t ACKR:1;          
        vuint32_t CB:1;          
        vuint32_t  :2;           
    } B;
  } CSR0;

  uint8_t SIPI_reserved0[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t WAIE:1;          
        vuint32_t RAIE:1;          
        vuint32_t TCIE:1;          
        vuint32_t TOIE:1;          
        vuint32_t TIDIE:1;           
        vuint32_t ACKIE:1;           
    } B;
  } CIR0;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t TOR:8;           
    } B;
  } CTOR0;

  union {
    vuint32_t R;
      struct {
        vuint32_t CRCI:16;           
        vuint32_t CRCT:16;           
    } B;
  } CCRC0;

  union {
    vuint32_t R;
      struct {
        vuint32_t CAR:32;          
    } B;
  } CAR0;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR:32;          
    } B;
  } CDR0;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t TC:1;          
        vuint32_t  :8;           
        vuint32_t WL:2;          
        vuint32_t CHEN:1;          
        vuint32_t ST:1;          
        vuint32_t IDT:1;           
        vuint32_t RRT:1;           
        vuint32_t WRT:1;           
        vuint32_t DEN:1;           
    } B;
  } CCR1;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t RAR:1;           
        vuint32_t TID:3;           
        vuint32_t ACKR:1;          
        vuint32_t CB:1;          
        vuint32_t  :2;           
    } B;
  } CSR1;

  uint8_t SIPI_reserved1[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t WAIE:1;          
        vuint32_t RAIE:1;          
        vuint32_t TCIE:1;          
        vuint32_t TOIE:1;          
        vuint32_t TIDIE:1;           
        vuint32_t ACKIE:1;           
    } B;
  } CIR1;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t TOR:8;           
    } B;
  } CTOR1;

  union {
    vuint32_t R;
      struct {
        vuint32_t CRCI:16;           
        vuint32_t CRCT:16;           
    } B;
  } CCRC1;

  union {
    vuint32_t R;
      struct {
        vuint32_t CAR:32;          
    } B;
  } CAR1;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR:32;          
    } B;
  } CDR1;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t TC:1;          
        vuint32_t  :8;           
        vuint32_t WL:2;          
        vuint32_t CHEN:1;          
        vuint32_t ST:1;          
        vuint32_t IDT:1;           
        vuint32_t RRT:1;           
        vuint32_t WRT:1;           
        vuint32_t DEN:1;           
    } B;
  } CCR2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t RAR:1;           
        vuint32_t TID:3;           
        vuint32_t ACKR:1;          
        vuint32_t CB:1;          
        vuint32_t  :2;           
    } B;
  } CSR2;

  uint8_t SIPI_reserved2[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t WAIE:1;          
        vuint32_t RAIE:1;          
        vuint32_t TCIE:1;          
        vuint32_t TOIE:1;          
        vuint32_t TIDIE:1;           
        vuint32_t ACKIE:1;           
    } B;
  } CIR2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t TOR:8;           
    } B;
  } CTOR2;

  union {
    vuint32_t R;
      struct {
        vuint32_t CRCI:16;           
        vuint32_t CRCT:16;           
    } B;
  } CCRC2;

  union {
    vuint32_t R;
      struct {
        vuint32_t CAR:32;          
    } B;
  } CAR2;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR20;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR21;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR22;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR23;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR24;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR25;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR26;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR2:32;           
    } B;
  } CDR27;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :15;          
        vuint32_t TC:1;          
        vuint32_t  :8;           
        vuint32_t WL:2;          
        vuint32_t CHEN:1;          
        vuint32_t ST:1;          
        vuint32_t IDT:1;           
        vuint32_t RRT:1;           
        vuint32_t WRT:1;           
        vuint32_t DEN:1;           
    } B;
  } CCR3;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t RAR:1;           
        vuint32_t TID:3;           
        vuint32_t ACKR:1;          
        vuint32_t CB:1;          
        vuint32_t  :2;           
    } B;
  } CSR3;

  uint8_t SIPI_reserved3[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t WAIE:1;          
        vuint32_t RAIE:1;          
        vuint32_t TCIE:1;          
        vuint32_t TOIE:1;          
        vuint32_t TIDIE:1;           
        vuint32_t ACKIE:1;           
    } B;
  } CIR3;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t TOR:8;           
    } B;
  } CTOR3;

  union {
    vuint32_t R;
      struct {
        vuint32_t CRCI:16;           
        vuint32_t CRCT:16;           
    } B;
  } CCRC3;

  union {
    vuint32_t R;
      struct {
        vuint32_t CAR:32;          
    } B;
  } CAR3;

  union {
    vuint32_t R;
      struct {
        vuint32_t CDR:32;          
    } B;
  } CDR3;

  union {
    vuint32_t R;
      struct {
        vuint32_t FRZ:1;           
        vuint32_t  :1;           
        vuint32_t HALT:1;          
        vuint32_t  :2;           
        vuint32_t PRSCLR:11;           
        vuint32_t AID:2;           
        vuint32_t  :3;           
        vuint32_t CRCIE:1;           
        vuint32_t MCRIE:1;           
        vuint32_t  :5;           
        vuint32_t TEN:1;           
        vuint32_t INIT:1;          
        vuint32_t MOEN:1;          
        vuint32_t SR:1;          
    } B;
  } MCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t FRZACK:1;          
        vuint32_t LPMACK:1;          
        vuint32_t  :19;          
        vuint32_t GCRCE:1;           
        vuint32_t MCR:1;           
        vuint32_t  :1;           
        vuint32_t TE:4;          
        vuint32_t STATE:4;           
    } B;
  } SR;

  union {
    vuint32_t R;
      struct {
        vuint32_t MXCNT:30;          
        vuint32_t  :2;           
    } B;
  } MAXCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t ADRLD:30;          
        vuint32_t  :2;           
    } B;
  } ARR;

  union {
    vuint32_t R;
      struct {
        vuint32_t ADCNT:30;          
        vuint32_t  :2;           
    } B;
  } ACR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :5;           
        vuint32_t TOE3:1;          
        vuint32_t TIDE3:1;           
        vuint32_t ACKE3:1;           
        vuint32_t  :5;           
        vuint32_t TOE2:1;          
        vuint32_t TIDE2:1;           
        vuint32_t ACKE2:1;           
        vuint32_t  :5;           
        vuint32_t TOE1:1;          
        vuint32_t TIDE1:1;           
        vuint32_t ACKE1:1;           
        vuint32_t  :5;           
        vuint32_t TOE0:1;          
        vuint32_t TIDE0:1;           
        vuint32_t ACKE0:1;           
    } B;
  } ERR;

};

/****************************************************************************/
/*                     MODULE : Input Glitch Filter                         */
/****************************************************************************/
struct IGF_tag {
  struct {
    union {
      vuint32_t R;
        struct {
          vuint32_t  :1;           /*  */
          vuint32_t MDIS:1;          /* Module Disable */
          vuint32_t FRZ:1;           /* Freeze bit for debug operation */
          vuint32_t FBP:1;           /* Force Bypass */
          vuint32_t FOH:1;           /* Force filter output high */
          vuint32_t FOL:1;           /* Force filter output low */
          vuint32_t  :16;          /*  */
          vuint32_t IMM:1;           /* Immediate edge propagation control bit */
          vuint32_t PSSEL:1;           /* Prescaler selection bit */
          vuint32_t POL:1;           /* Output polarity bit */
          vuint32_t FGEN:1;          /* Filter global enable */
          vuint32_t  :1;           /*  */
          vuint32_t FFM:2;           /* Falling edge filter type selection */
          vuint32_t  :1;           /*  */
          vuint32_t RFM:2;           /* Rising edge filter type selection */
      } B;
    } MCR;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :26;          /*  */
          vuint32_t WEDGE:1;           /* Filter is active waiting for an edge */
          vuint32_t FEDGE:1;           /* Filter is active processing an edge */
          vuint32_t RNDET:1;           /* Rise noise detected bit */
          vuint32_t FNDET:1;           /* Fall noise detected bit */
          vuint32_t FLI:1;           /* Filter input */
          vuint32_t FLO:1;           /* Filter output */
      } B;
    } MSR;
  
    uint8_t IGF_reserved0[8];
    union {
      vuint32_t R;
        struct {
          vuint32_t  :23;          /*  */
          vuint32_t FPRE:9;          /* Filter prescaler */
      } B;
    } PRESR;
  
    uint8_t IGF_reserved1[8];
    union {
      vuint32_t R;
        struct {
          vuint32_t  :8;           /*  */
          vuint32_t RTH:24;          /* Rising edge threshold */
      } B;
    } RTHR;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :8;           /*  */
          vuint32_t FTH:24;          /* Falling edge threshold */
      } B;
    } FTHR;
  
    uint8_t IGF_reserved2[28];
  } FILTER[32];
};

/****************************************************************************/
/*                     MODULE : PLLDIG                                      */
/****************************************************************************/
struct PLLDIG_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t  :22;          
        vuint32_t CLKCFG:2;          
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t LOLIE:1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
    } B;
  } PLL0CR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t LOLF:1;          
        vuint32_t LOCK:1;          
        vuint32_t  :1;           
        vuint32_t  :1;           
    } B;
  } PLL0SR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :1;           
        vuint32_t RFDPHI1:4;           
        vuint32_t  :5;           
        vuint32_t RFDPHI:6;          
        vuint32_t  :1;           
        vuint32_t PREDIV:3;          
        vuint32_t  :5;           
        vuint32_t MFD:7;           
    } B;
  } PLL0DV;

  uint8_t PLLDIG_reserved0[20];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :22;          
        vuint32_t CLKCFG:2;          
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t LOLIE:1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
    } B;
  } PLL1CR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t LOLF:1;          
        vuint32_t LOCK:1;          
        vuint32_t  :1;           
        vuint32_t  :1;           
    } B;
  } PLL1SR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :10;          
        vuint32_t RFDPHI:6;          
        vuint32_t  :9;           
        vuint32_t MFD:7;           
    } B;
  } PLL1DV;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :1;           
        vuint32_t MODEN:1;           
        vuint32_t MODSEL:1;          
        vuint32_t MODPRD:13;           
        vuint32_t  :1;           
        vuint32_t INCSTP:15;           
    } B;
  } PLL1FM;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :1;           
        vuint32_t FDEN:1;          
        vuint32_t  :12;          
        vuint32_t DTHDIS:2;          
        vuint32_t  :4;           
        vuint32_t FRCDIV:12;           
    } B;
  } PLL1FD;

};

/****************************************************************************/
/*                     MODULE : MCAN                                        */
/****************************************************************************/
struct MCAN_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t REL:4;           
        vuint32_t STEP:4;          
        vuint32_t SUBSTEP:4;           
        vuint32_t YEAR:4;          
        vuint32_t MON:8;           
        vuint32_t DAY:8;           
    } B;
  } CREL;

  union {
    vuint32_t R;
      struct {
        vuint32_t ETV:32;          
    } B;
  } ENDN;

  uint8_t MCAN_reserved0[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t TDCO:3;          /* Transceiver Delay Compensation Offset */
        vuint32_t TDC:1;           /* Transceiver Delay Compensation */
        vuint32_t  :1;           
        vuint32_t FBRP:12;           /* Fast Baud Rate Prescaler */
        vuint32_t  :3;           
        vuint32_t FTSEG1:4;          /* Fast time segment before sample point */
        vuint32_t  :1;           
        vuint32_t FTSEG2:3;          /* Fast time segment before sample point */
        vuint32_t  :2;           
        vuint32_t FSJW:2;          /* Fast (Re) Synchronization Jump Width */
    } B;
  } FBTP;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :19;          
        vuint32_t TDCV:5;          /* Transceiver Delay Compensation Value */
        vuint32_t RX:1;          
        vuint32_t TX:2;          
        vuint32_t LBCK:1;          
        vuint32_t  :4;           
    } B;
  } TEST;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t WDV:8;           
        vuint32_t WDC:8;           
    } B;
  } RWD;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t LONG:1;          /* Long Frame Mode Enable Protected write (P) bit(s) which means that the write access to this field is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to "1". */
        vuint32_t FAST:1;          /* Fast Frame Mode Enable Protected write (P) bit(s) which means that the write access to this field is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to "1". */
        vuint32_t LACT:1;          /* Long Frame Mode Active */
        vuint32_t FACT:1;          /* Fast Frame Mode Active */
        vuint32_t CLRL:1;          /* Clear Long Frame Mode */
        vuint32_t SETL:1;          /* Set Long Frame Mode */
        vuint32_t CLRF:1;          /* Clear Fast Bit Rate Mode */
        vuint32_t SETF:1;          /* Set Fast Bit Rate Mode */
        vuint32_t TEST:1;          
        vuint32_t DAR:1;           
        vuint32_t MON:1;           
        vuint32_t CSR:1;           
        vuint32_t CSA:1;           
        vuint32_t ASM:1;           
        vuint32_t CCE:1;           
        vuint32_t INIT:1;          
    } B;
  } CCCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :6;           
        vuint32_t BRP:10;          /* Baud Rate Prescaler */
        vuint32_t  :2;           
        vuint32_t TSEG1:6;           
        vuint32_t TSEG2:4;           
        vuint32_t SJW:4;           
    } B;
  } BTP;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :12;          
        vuint32_t TCP:4;           
        vuint32_t  :14;          
        vuint32_t TSS:2;           
    } B;
  } TSCC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t TSC:16;          
    } B;
  } TSCV;

  union {
    vuint32_t R;
      struct {
        vuint32_t TOP:16;          
        vuint32_t  :13;          
        vuint32_t TOS:2;           
        vuint32_t ETOC:1;          
    } B;
  } TOCC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t TOC:16;          
    } B;
  } TOCV;

  uint8_t MCAN_reserved1[16];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :8;           
        vuint32_t CEL:8;           
        vuint32_t RP:1;          
        vuint32_t REC:7;           
        vuint32_t TEC:8;           
    } B;
  } ECR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :18;          
        vuint32_t REDL:1;          /* Received CAN FD Message with EDL flag */
        vuint32_t RBRS:1;          /* BRS flag of last received CAN FD Message */
        vuint32_t RESI:1;          /* ESI CAN FD Message with ESI flag */
        vuint32_t FLEC:3;          /* Fast Last Error Code */
        vuint32_t BO:1;          
        vuint32_t EW:1;          
        vuint32_t EP:1;          
        vuint32_t ACT:2;           
        vuint32_t LEC:3;           
    } B;
  } PSR;

  uint8_t MCAN_reserved2[8];
  union {
    vuint32_t R;
      struct {
        vuint32_t STE:1;           
        vuint32_t FOE:1;           
        vuint32_t ACKE:1;          
        vuint32_t BE:1;          
        vuint32_t CRCE:1;          
        vuint32_t WDI:1;           
        vuint32_t BO:1;          
        vuint32_t EW:1;          
        vuint32_t EP:1;          
        vuint32_t ELO:1;           
        vuint32_t BEU:1;           
        vuint32_t BEC:1;           
        vuint32_t DRX:1;           /* Message stored to Dedicated Rx Buffer */
        vuint32_t TOO:1;           
        vuint32_t UMD:1;           
        vuint32_t TSW:1;           
        vuint32_t TEFL:1;          
        vuint32_t TEFF:1;          
        vuint32_t TEFW:1;          
        vuint32_t TEFN:1;          
        vuint32_t TFE:1;           
        vuint32_t TCF:1;           
        vuint32_t TC:1;          
        vuint32_t HPM:1;           
        vuint32_t RF1L:1;          
        vuint32_t RF1F:1;          
        vuint32_t RF1W:1;          
        vuint32_t RF1N:1;          
        vuint32_t RF0L:1;          
        vuint32_t RF0F:1;          
        vuint32_t RF0W:1;          
        vuint32_t RF0N:1;          
    } B;
  } IR;

  union {
    vuint32_t R;
      struct {
        vuint32_t STEE:1;          
        vuint32_t FOEE:1;          
        vuint32_t ACKEE:1;           
        vuint32_t BEE:1;           
        vuint32_t CRCEE:1;           
        vuint32_t WDIE:1;          
        vuint32_t BOE:1;           
        vuint32_t EWE:1;           
        vuint32_t EPE:1;           
        vuint32_t ELOE:1;          
        vuint32_t BEUE:1;          
        vuint32_t BECE:1;          
        vuint32_t DRXE:1;          /* Message stored to Dedicated Rx Buffer Interrupt Enable */
        vuint32_t TOOE:1;          
        vuint32_t UMDE:1;          
        vuint32_t TSWE:1;          
        vuint32_t TEFLE:1;           
        vuint32_t TEFFE:1;           
        vuint32_t TEFWE:1;           
        vuint32_t TEFNE:1;           
        vuint32_t TFEE:1;          
        vuint32_t TCFE:1;          
        vuint32_t TCE:1;           
        vuint32_t HPME:1;          
        vuint32_t RF1LE:1;           
        vuint32_t RF1FE:1;           
        vuint32_t RF1WE:1;           
        vuint32_t RF1NE:1;           
        vuint32_t RF0LE:1;           
        vuint32_t RF0FE:1;           
        vuint32_t RF0WE:1;           
        vuint32_t RF0NE:1;           
    } B;
  } IE;

  union {
    vuint32_t R;
      struct {
        vuint32_t STEL:1;          
        vuint32_t FOEL:1;          
        vuint32_t ACKEL:1;           
        vuint32_t BEL:1;           
        vuint32_t CRCEL:1;           
        vuint32_t WDIL:1;          
        vuint32_t BOL:1;           
        vuint32_t EWL:1;           
        vuint32_t EPL:1;           
        vuint32_t ELOL:1;          
        vuint32_t BEUL:1;          
        vuint32_t BECL:1;          
        vuint32_t DRXL:1;          /* Message stored to Dedicated Rx Buffer Interrupt Line */
        vuint32_t TOOL:1;          
        vuint32_t UMDL:1;          
        vuint32_t TSWL:1;          
        vuint32_t TEFLL:1;           
        vuint32_t TEFFL:1;           
        vuint32_t TEFWL:1;           
        vuint32_t TEFNL:1;           
        vuint32_t TFEL:1;          
        vuint32_t TCFL:1;          
        vuint32_t TCL:1;           
        vuint32_t HPML:1;          
        vuint32_t RF1LL:1;           
        vuint32_t RF1FL:1;           
        vuint32_t RF1WL:1;           
        vuint32_t RF1NL:1;           
        vuint32_t RF0LL:1;           
        vuint32_t RF0FL:1;           
        vuint32_t RF0WL:1;           
        vuint32_t RF0NL:1;           
    } B;
  } ILS;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :30;          
        vuint32_t EINT1:1;           
        vuint32_t EINT0:1;           
    } B;
  } ILE;

  uint8_t MCAN_reserved3[32];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t ANFS:2;          
        vuint32_t ANFE:2;          
        vuint32_t RRFS:1;          
        vuint32_t RRFE:1;          
    } B;
  } GFC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :8;           
        vuint32_t LSS:8;           
        vuint32_t FLSSA:14;          
        vuint32_t  :2;           
    } B;
  } SIDFC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :9;           
        vuint32_t LSE:7;           
        vuint32_t FLESA:14;          
        vuint32_t  :2;           
    } B;
  } XIDFC;

  uint8_t MCAN_reserved4[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :3;           
        vuint32_t EIDM:29;           
    } B;
  } XIDAM;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t FLST:1;          
        vuint32_t FIDX:7;          
        vuint32_t MSI:2;           
        vuint32_t BIDX:6;          
    } B;
  } HPMS;

  union {
    vuint32_t R;
      struct {
        vuint32_t ND:32;           /* New Data[31:0] */
    } B;
  } NDAT1;

  union {
    vuint32_t R;
      struct {
        vuint32_t ND:32;           /* The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard reset will clear the register. */
    } B;
  } NDAT2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :1;           
        vuint32_t F0WM:7;          
        vuint32_t  :2;           
        vuint32_t F0S:6;           
        vuint32_t F0SA:14;           
        vuint32_t  :2;           
    } B;
  } RXF0C;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :6;           
        vuint32_t RF0L:1;          
        vuint32_t F0F:1;           
        vuint32_t  :10;          
        vuint32_t F0GI:6;          
        vuint32_t  :1;           
        vuint32_t F0FL:7;          
    } B;
  } RXF0S;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t F0AI:6;          
    } B;
  } RXF0A;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t RBSA:14;           /* Rx Buffer Start Address */
        vuint32_t  :2;           
    } B;
  } RXBC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :1;           
        vuint32_t F1WM:7;          
        vuint32_t  :1;           
        vuint32_t F1S:7;           
        vuint32_t F1SA:14;           
        vuint32_t  :2;           
    } B;
  } RXF1C;

  union {
    vuint32_t R;
      struct {
        vuint32_t DMS:2;           
        vuint32_t  :4;           
        vuint32_t RF1L:1;          
        vuint32_t F1F:1;           
        vuint32_t  :10;          
        vuint32_t F1G1:6;          
        vuint32_t  :1;           
        vuint32_t F1FL:7;          
    } B;
  } RXF1S;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          
        vuint32_t F1AI:6;          
    } B;
  } RXF1A;

  uint8_t MCAN_reserved5[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :1;           
        vuint32_t TQFM:1;          
        vuint32_t TQFS:6;          
        vuint32_t  :2;           
        vuint32_t NDTB:6;          
        vuint32_t TBSA:14;           
        vuint32_t  :2;           
    } B;
  } TXBC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :10;          
        vuint32_t TFQF:1;          
        vuint32_t TFQPI:5;           
        vuint32_t  :10;          
        vuint32_t TFFL:6;          
    } B;
  } TXFQS;

  uint8_t MCAN_reserved6[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t TRP:32;          
    } B;
  } TXBRP;

  union {
    vuint32_t R;
      struct {
        vuint32_t AR:32;           
    } B;
  } TXBAR;

  union {
    vuint32_t R;
      struct {
        vuint32_t CR:32;           
    } B;
  } TXBCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t TO:32;           
    } B;
  } TXBTO;

  union {
    vuint32_t R;
      struct {
        vuint32_t CF:32;           
    } B;
  } TXBCF;

  union {
    vuint32_t R;
      struct {
        vuint32_t TIE:32;          
    } B;
  } TXBTIE;

  union {
    vuint32_t R;
      struct {
        vuint32_t CFIE:32;           
    } B;
  } TXBCIE;

  uint8_t MCAN_reserved7[8];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :2;           
        vuint32_t EFWM:6;          
        vuint32_t  :2;           
        vuint32_t EFS:6;           
        vuint32_t EFSA:14;           
        vuint32_t  :2;           
    } B;
  } TXEFC;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :6;           
        vuint32_t TEFL:1;          
        vuint32_t EFF:1;           
        vuint32_t  :11;          
        vuint32_t EFGI:5;          
        vuint32_t  :2;           
        vuint32_t EFFL:6;          
    } B;
  } TXEFS;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :27;          
        vuint32_t EFAI:5;          
    } B;
  } TXEFA;

};

/****************************************************************************/
/*                     MODULE : XBIC                                        */
/****************************************************************************/
struct XBIC_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t SE0:1;           
        vuint32_t SE1:1;           
        vuint32_t SE2:1;           
        vuint32_t SE3:1;           
        vuint32_t SE4:1;           
        vuint32_t SE5:1;           
        vuint32_t SE6:1;           
        vuint32_t SE7:1;           
        vuint32_t  :24;          
    } B;
  } MCR;

  union {
    vuint32_t R;
      struct {
        vuint32_t EIE:1;           
        vuint32_t  :16;          
        vuint32_t SLV:3;           
        vuint32_t MST:4;           
        vuint32_t SYN:8;           
    } B;
  } EIR;

  union {
    vuint32_t R;
      struct {
        vuint32_t VLD:1;           
        vuint32_t  :16;          
        vuint32_t SLV:3;           
        vuint32_t MST:4;           
        vuint32_t SYN:8;           
    } B;
  } ESR;

  union {
    vuint32_t R;
      struct {
        vuint32_t ADDR:32;           
    } B;
  } EAR;
};

/****************************************************************************/
/*                     MODULE : Fast Ethernet Controller (FEC)              */
/****************************************************************************/
struct FEC_tag {
  uint8_t FEC_reserved0[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t HBERR:1;           
        vuint32_t BABR:1;          
        vuint32_t BABT:1;          
        vuint32_t GRA:1;           
        vuint32_t TXF:1;           
        vuint32_t TXB:1;           
        vuint32_t RXF:1;           
        vuint32_t RXB:1;           
        vuint32_t MII:1;           
        vuint32_t EBERR:1;           
        vuint32_t LC:1;          
        vuint32_t RL:1;          
        vuint32_t UN:1;          
        vuint32_t  :19;          
    } B;
  } EIR;

  union {
    vuint32_t R;
      struct {
        vuint32_t HBERR:1;           
        vuint32_t BABR:1;          
        vuint32_t BABT:1;          
        vuint32_t GRA:1;           
        vuint32_t TXF:1;           
        vuint32_t TXB:1;           
        vuint32_t RXF:1;           
        vuint32_t RXB:1;           
        vuint32_t MII:1;           
        vuint32_t EBERR:1;           
        vuint32_t LC:1;          
        vuint32_t RL:1;          
        vuint32_t UN:1;          
        vuint32_t  :19;          
    } B;
  } EIMR;

  uint8_t FEC_reserved1[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :7;           
        vuint32_t RDAR:1;          
        vuint32_t  :24;          
    } B;
  } RDAR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :7;           
        vuint32_t TDAR:1;          
        vuint32_t  :24;          
    } B;
  } TDAR;

  uint8_t FEC_reserved2[12];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :4;           
        vuint32_t  :1;           
        vuint32_t  :1;           
        vuint32_t  :23;          
        vuint32_t  :1;           
        vuint32_t ETHER_EN:1;          
        vuint32_t RESET:1;           
    } B;
  } ECR;

  uint8_t FEC_reserved3[24];
  union {
    vuint32_t R;
      struct {
        vuint32_t ST:2;          
        vuint32_t OP:2;          
        vuint32_t PA:5;          
        vuint32_t RA:5;          
        vuint32_t TA:2;          
        vuint32_t DATA:16;           
    } B;
  } MMFR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          
        vuint32_t DIS_PRE:1;           
        vuint32_t MII_SPEED:6;           
        vuint32_t  :1;           
    } B;
  } MSCR;

  uint8_t FEC_reserved4[28];
  union {
    vuint32_t R;
      struct {
        vuint32_t MIB_DIS:1;           
        vuint32_t MIB_IDLE:1;          
        vuint32_t  :30;          
    } B;
  } MIBC;

  uint8_t FEC_reserved5[28];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :5;           
        vuint32_t MAX_FL:11;           
        vuint32_t  :4;           
        vuint32_t RMII_ECHO:1;           
        vuint32_t RMII_LOOP:1;           
        vuint32_t RMII_10T:1;          
        vuint32_t RMII_MODE:1;           
        vuint32_t  :2;           
        vuint32_t FCE:1;           
        vuint32_t BC_REJ:1;          
        vuint32_t PROM:1;          
        vuint32_t MII_MODE:1;          
        vuint32_t DRT:1;           
        vuint32_t LOOP:1;          
    } B;
  } RCR;

  uint8_t FEC_reserved6[60];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :27;          
        vuint32_t RFC_PAUSE:1;           
        vuint32_t TFC_PAUSE:1;           
        vuint32_t FDEN:1;          
        vuint32_t HBC:1;           
        vuint32_t GTS:1;           
    } B;
  } TCR;

  uint8_t FEC_reserved7[28];
  union {
    vuint32_t R;
      struct {
        vuint32_t PADDR1:32;           
    } B;
  } PALR;

  union {
    vuint32_t R;
      struct {
        vuint32_t PADDR2:16;           
        vuint32_t TYPE:16;           
    } B;
  } PAUR;

  union {
    vuint32_t R;
      struct {
        vuint32_t OPCODE:16;           
        vuint32_t PAUSE_DUR:16;          
    } B;
  } OPD;

  uint8_t FEC_reserved8[40];
  union {
    vuint32_t R;
      struct {
        vuint32_t IADDR1:32;           
    } B;
  } IAUR;

  union {
    vuint32_t R;
      struct {
        vuint32_t IADDR2:32;           
    } B;
  } IALR;

  union {
    vuint32_t R;
      struct {
        vuint32_t GADDR1:32;           
    } B;
  } GAUR;

  union {
    vuint32_t R;
      struct {
        vuint32_t GADDR2:32;           
    } B;
  } GALR;

  uint8_t FEC_reserved9[28];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :30;          
        vuint32_t TFWR:2;          
    } B;
  } TFWR;

  uint8_t FEC_reserved10[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :21;          
        vuint32_t  :1;           
        vuint32_t R_BOUND:8;           
        vuint32_t  :2;           
    } B;
  } FRBR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :21;          
        vuint32_t  :1;           
        vuint32_t R_FSTART:8;          
        vuint32_t  :2;           
    } B;
  } FRSR;

  uint8_t FEC_reserved11[44];
  union {
    vuint32_t R;
      struct {
        vuint32_t R_DES_START:30;          
        vuint32_t  :2;           
    } B;
  } ERDSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t X_DES_START:30;          
        vuint32_t  :2;           
    } B;
  } ETDSR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :21;          
        vuint32_t R_BUF_SIZE:7;          
        vuint32_t  :4;           
    } B;
  } EMRBR;

  uint8_t FEC_reserved12[116];
  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_DROP:32;          
    } B;
  } RMON_T_DROP;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_PACKETS:32;           
    } B;
  } RMON_T_PACKETS;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_BC_PKT:32;          
    } B;
  } RMON_T_BC_PKT;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_MC_PKT:32;          
    } B;
  } RMON_T_MC_PKT;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_CRC_ALIGN:32;           
    } B;
  } RMON_T_CRC_ALIGN;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_UNDERSIZE:32;           
    } B;
  } RMON_T_UNDERSIZE;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_OVERSIZE:32;          
    } B;
  } RMON_T_OVERSIZE;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_FRAG:32;          
    } B;
  } RMON_T_FRAG;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_JAB:32;           
    } B;
  } RMON_T_JAB;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_COL:32;           
    } B;
  } RMON_T_COL;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P64:32;           
    } B;
  } RMON_T_P64;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P65TO127:32;          
    } B;
  } RMON_T_P65TO127;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P128TO255:32;           
    } B;
  } RMON_T_P128TO255;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P256TO511:32;           
    } B;
  } RMON_T_P256TO511;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P512TO1023:32;          
    } B;
  } RMON_T_P512TO1023;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P1024TO2047:32;           
    } B;
  } RMON_T_P1024TO2047;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_P_GTE2048:32;           
    } B;
  } RMON_T_P_GTE2048;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_T_OCTETS:32;          
    } B;
  } RMON_T_OCTETS;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_DROP:32;          
    } B;
  } IEEE_T_DROP;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_FRAME_OK:32;          
    } B;
  } IEEE_T_FRAME_OK;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_1COL:32;          
    } B;
  } IEEE_T_1COL;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_MCOL:32;          
    } B;
  } IEEE_T_MCOL;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_DEF:32;           
    } B;
  } IEEE_T_DEF;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_LCOL:32;          
    } B;
  } IEEE_T_LCOL;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_EXCOL:32;           
    } B;
  } IEEE_T_EXCOL;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_MACERR:32;          
    } B;
  } IEEE_T_MACERR;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_CSERR:32;           
    } B;
  } IEEE_T_CSERR;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_SQE:32;           
    } B;
  } IEEE_T_SQE;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_FDXFC:32;           
    } B;
  } IEEE_T_FDXFC;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_T_OCTETS_OK:32;           
    } B;
  } IEEE_T_OCTETS_OK;

  uint8_t FEC_reserved13[8];
  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_DROP:32;          
    } B;
  } RMON_R_DROP;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_PACKETS:32;           
    } B;
  } RMON_R_PACKETS;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_BC_PKT:32;          
    } B;
  } RMON_R_BC_PKT;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_MC_PKT:32;          
    } B;
  } RMON_R_MC_PKT;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_CRC_ALIGN:32;           
    } B;
  } RMON_R_CRC_ALIGN;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_UNDERSIZE:32;           
    } B;
  } RMON_R_UNDERSIZE;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_OVERSIZE:32;          
    } B;
  } RMON_R_OVERSIZE;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_FRAG:32;          
    } B;
  } RMON_R_FRAG;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_JAB:32;           
    } B;
  } RMON_R_JAB;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_RESVD_0:32;           
    } B;
  } RMON_R_RESVD_0;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P64:32;           
    } B;
  } RMON_R_P64;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P65TO127:32;          
    } B;
  } RMON_R_P65TO127;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P128TO255:32;           
    } B;
  } RMON_R_P128TO255;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P256TO511:32;           
    } B;
  } RMON_R_P256TO511;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P512TO1023:32;          
    } B;
  } RMON_R_P512TO1023;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P1024TO2047:32;           
    } B;
  } RMON_R_P1024TO2047;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_P_GTE2048:32;           
    } B;
  } RMON_R_P_GTE2048;

  union {
    vuint32_t R;
      struct {
        vuint32_t RMON_R_OCTETS:32;          
    } B;
  } RMON_R_OCTETS;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_DROP:32;          
    } B;
  } IEEE_R_DROP;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_FRAME_OK:32;          
    } B;
  } IEEE_R_FRAME_OK;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_CRC:32;           
    } B;
  } IEEE_R_CRC;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_ALIGN:32;           
    } B;
  } IEEE_R_ALIGN;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_MACERR:32;          
    } B;
  } IEEE_R_MACERR;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_FDXFC:32;           
    } B;
  } IEEE_R_FDXFC;

  union {
    vuint32_t R;
      struct {
        vuint32_t IEEE_R_OCTETS_OK:32;           
    } B;
  } IEEE_R_OCTETS_OK;

};

/****************************************************************************/
/*                     MODULE : Main Flash Control (c55fmc)                 */
/****************************************************************************/
struct C55FMC_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t RVE:1;           /* Read Voltage Error */
        vuint32_t RRE:1;           /* Read Reference Error */
        vuint32_t AEE:1;           /* Address Encode Error */
        vuint32_t EEE:1;           /* ECC after ECC Error */
        vuint32_t  :12;          
        vuint32_t EER:1;           /* ECC Event Error */
        vuint32_t RWE:1;           /* Read-While-Write Event Error */
        vuint32_t SBC:1;           /* Single Bit Correction */
        vuint32_t  :1;           
        vuint32_t PEAS:1;          /* Program Access Space */
        vuint32_t DONE:1;          /* State Machine Status */
        vuint32_t PEG:1;           /* Program/Erase Good */
        vuint32_t PECIE:1;           /* Program/Erase Complete Interrupt Enable */
        vuint32_t  :1;           
        vuint32_t  :2;           
        vuint32_t PGM:1;           /* Program */
        vuint32_t PSUS:1;          /* Program Suspend */
        vuint32_t ERS:1;           /* Erase */
        vuint32_t ESUS:1;          /* Erase Suspend */
        vuint32_t EHV:1;           /* Enable High Voltage */
    } B;
  } MCR;

  uint8_t C55FMC_reserved0[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t HT:1;          /* High Temperature Enabled. */
        vuint32_t  :2;           
        vuint32_t n256K:5;           
        vuint32_t n64Kh:3;           
        vuint32_t n32Kh:2;           
        vuint32_t n16Kh:3;           
        vuint32_t n64Km:3;           
        vuint32_t n32Km:2;           
        vuint32_t n16Km:3;           
        vuint32_t n64Kl:3;           
        vuint32_t n32Kl:2;           
        vuint32_t n16Kl:3;           
    } B;
  } MCRE;

  uint8_t C55FMC_reserved1[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t TSLOCK:1;          /* UTest NVM Lock. */
        vuint32_t  :1;           
        vuint32_t LOWLOCK:14;          /* Low Block Lock */
        vuint32_t MIDLOCK:16;          /* Mid Block Lock */
    } B;
  } LOCK0;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t HIGHLOCK:16;           /* High Block Lock */
    } B;
  } LOCK1;

  union {
    vuint32_t R;
      struct {
        vuint32_t A256KLOCK:32;          /* 256 KB Block Lock */
    } B;
  } LOCK2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t A256KLOCK:16;          /* 256 KB Block Lock */
    } B;
  } LOCK3;

  uint8_t C55FMC_reserved2[24];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :2;           
        vuint32_t LOWSEL:14;           /* LOW Block Select. */
        vuint32_t MIDSEL:16;           /* Mid Block Select. */
    } B;
  } SEL0;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t HIGHSEL:16;          /* High Block Select. */
    } B;
  } SEL1;

  union {
    vuint32_t R;
      struct {
        vuint32_t A256KSEL:32;           /* 256 KB Block Select. */
    } B;
  } SEL2;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          
        vuint32_t A256KSEL:16;           /* 256 KB Block Select. */
    } B;
  } SEL3;

  uint8_t C55FMC_reserved3[8];
  union {
    vuint32_t R;
      struct {
        vuint32_t SAD:1;           
        vuint32_t aH:1;          
        vuint32_t aM:1;          
        vuint32_t aL:1;          
        vuint32_t a256k:1;           
        vuint32_t a64k:1;          
        vuint32_t a32k:1;          
        vuint32_t a16k:1;          
        vuint32_t ADDR:21;           
        vuint32_t  :3;           
    } B;
  } ADR;

  union {
    vuint32_t R;
      struct {
        vuint32_t UTE:1;           
        vuint32_t SBCE:1;          
        vuint32_t  :11;          
        vuint32_t CPR:1;           
        vuint32_t CPA:1;           
        vuint32_t CPE:1;           
        vuint32_t  :6;           
        vuint32_t NAIBP:1;           
        vuint32_t AIBPE:1;           
        vuint32_t  :1;           
        vuint32_t AISUS:1;           
        vuint32_t MRE:1;           
        vuint32_t MRV:1;           
        vuint32_t  :1;           
        vuint32_t AIS:1;           
        vuint32_t AIE:1;           
        vuint32_t AID:1;           
    } B;
  } UT0;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM0;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM1;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM2;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM3;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM4;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM5;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM6;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM7;

  union {
    vuint32_t R;
      struct {
        vuint32_t MISR:32;           
    } B;
  } UM8;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :31;          
        vuint32_t MISR:1;          /* MISR[288]. */
    } B;
  } UM9;

};

/****************************************************************************/
/*                     MODULE : Platform Flash BIU (PFLASH)                 */
/****************************************************************************/
struct PFLASH_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t P0_M15PFE:1;           
        vuint32_t P0_M14PFE:1;           
        vuint32_t P0_M13PFE:1;           
        vuint32_t P0_M12PFE:1;           
        vuint32_t P0_M11PFE:1;           
        vuint32_t P0_M10PFE:1;           
        vuint32_t P0_M9PFE:1;          
        vuint32_t P0_M8PFE:1;          
        vuint32_t P0_M7PFE:1;          
        vuint32_t P0_M6PFE:1;          
        vuint32_t P0_M5PFE:1;          
        vuint32_t P0_M4PFE:1;          
        vuint32_t P0_M3PFE:1;          
        vuint32_t P0_M2PFE:1;          
        vuint32_t P0_M1PFE:1;          
        vuint32_t P0_M0PFE:1;          
        vuint32_t APC:3;           
        vuint32_t RWSC:5;          
        vuint32_t  :1;           
        vuint32_t P0_DPFEN:1;          
        vuint32_t  :1;           
        vuint32_t P0_IPFEN:1;          
        vuint32_t  :1;           
        vuint32_t P0_PFLIM:2;          
        vuint32_t P0_BFEN:1;           
    } B;
  } PFCR1;

  union {
    vuint32_t R;
      struct {
        vuint32_t P1_M15PFE:1;           
        vuint32_t P1_M14PFE:1;           
        vuint32_t P1_M13PFE:1;           
        vuint32_t P1_M12PFE:1;           
        vuint32_t P1_M11PFE:1;           
        vuint32_t P1_M10PFE:1;           
        vuint32_t P1_M9PFE:1;          
        vuint32_t P1_M8PFE:1;          
        vuint32_t P1_M7PFE:1;          
        vuint32_t P1_M6PFE:1;          
        vuint32_t P1_M5PFE:1;          
        vuint32_t P1_M4PFE:1;          
        vuint32_t P1_M3PFE:1;          
        vuint32_t P1_M2PFE:1;          
        vuint32_t P1_M1PFE:1;          
        vuint32_t P1_M0PFE:1;          
        vuint32_t  :9;           
        vuint32_t P1_DPFEN:1;          
        vuint32_t  :1;           
        vuint32_t P1_IPFEN:1;          
        vuint32_t  :1;           
        vuint32_t P1_PFLIM:2;          
        vuint32_t P1_BFEN:1;           
    } B;
  } PFCR2;

  union {
    vuint32_t R;
      struct {
        vuint32_t P0_WCFG:2;           
        vuint32_t P1_WCFG:2;           
        vuint32_t  :2;           
        vuint32_t  :5;           
        vuint32_t BDRM:1;          
        vuint32_t  :3;           
        vuint32_t BAF_DIS:1;           
        vuint32_t ARBM:2;          
        vuint32_t  :2;           
        vuint32_t  :12;          
    } B;
  } PFCR3;

  union {
    vuint32_t R;
      struct {
        vuint32_t M0AP:2;          
        vuint32_t M1AP:2;          
        vuint32_t M2AP:2;          
        vuint32_t M3AP:2;          
        vuint32_t M4AP:2;          
        vuint32_t M5AP:2;          
        vuint32_t M6AP:2;          
        vuint32_t M7AP:2;          
        vuint32_t M8AP:2;          
        vuint32_t M9AP:2;          
        vuint32_t M10AP:2;           
        vuint32_t M11AP:2;           
        vuint32_t M12AP:2;           
        vuint32_t M13AP:2;           
        vuint32_t M14AP:2;           
        vuint32_t M15AP:2;           
    } B;
  } PFAPR;

};
/* ============================================================================
   =============================== Module: FCCU ===============================
   ============================================================================ */

struct FCCU_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t FILTER_BYPASS:1;
      vuint32_t FILTER_WIDTH:2;
      vuint32_t  :19;
      vuint32_t DEBUG:1;
      vuint32_t NVML:1;
      vuint32_t OPS:2;
      vuint32_t  :1;
      vuint32_t OPR:5;
    } B;
  } CTRL;

  union {                              /* CTRL Key Register */
    vuint32_t R;
    struct {
      vuint32_t CTRLK:32;
    } B;
  } CTRLK;

  union {                              /* Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t FCCU_SET_AFTER_RESET:1;
      vuint32_t FCCU_SET_CLEAR:2;
      vuint32_t RCCE1:1;
      vuint32_t RCCE0:1;
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t SM:1;
      vuint32_t PS:1;
      vuint32_t FOM:3;
      vuint32_t  :6;
    } B;
  } CFG;

  uint8_t FCCU_reserved0[16];
  union {                              /* NCF Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t NCFC31:1;
      vuint32_t NCFC30:1;
      vuint32_t NCFC29:1;
      vuint32_t NCFC28:1;
      vuint32_t NCFC27:1;
      vuint32_t NCFC26:1;
      vuint32_t NCFC25:1;
      vuint32_t NCFC24:1;
      vuint32_t NCFC23:1;
      vuint32_t NCFC22:1;
      vuint32_t NCFC21:1;
      vuint32_t NCFC20:1;
      vuint32_t NCFC19:1;
      vuint32_t NCFC18:1;
      vuint32_t NCFC17:1;
      vuint32_t NCFC16:1;
      vuint32_t NCFC15:1;
      vuint32_t NCFC14:1;
      vuint32_t NCFC13:1;
      vuint32_t NCFC12:1;
      vuint32_t NCFC11:1;
      vuint32_t NCFC10:1;
      vuint32_t NCFC9:1;
      vuint32_t NCFC8:1;
      vuint32_t NCFC7:1;
      vuint32_t NCFC6:1;
      vuint32_t NCFC5:1;
      vuint32_t NCFC4:1;
      vuint32_t NCFC3:1;
      vuint32_t NCFC2:1;
      vuint32_t NCFC1:1;
      vuint32_t NCFC0:1;
    } B;
  } NCF_CFG[2];

  uint8_t FCCU_reserved1[40];
  union {                              /* NCFS Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t NCFSC31:1;
      vuint32_t NCFSC30:1;
      vuint32_t NCFSC29:1;
      vuint32_t NCFSC28:1;
      vuint32_t NCFSC27:1;
      vuint32_t NCFSC26:1;
      vuint32_t NCFSC25:1;
      vuint32_t NCFSC24:1;
      vuint32_t NCFSC23:1;
      vuint32_t NCFSC22:1;
      vuint32_t NCFSC21:1;
      vuint32_t NCFSC20:1;
      vuint32_t NCFSC19:1;
      vuint32_t NCFSC18:1;
      vuint32_t NCFSC17:1;
      vuint32_t NCFSC16:1;
      vuint32_t NCFSC15:1;
      vuint32_t NCFSC14:1;
      vuint32_t NCFSC13:1;
      vuint32_t NCFSC12:1;
      vuint32_t NCFSC11:1;
      vuint32_t NCFSC10:1;
      vuint32_t NCFSC9:1;
      vuint32_t NCFSC8:1;
      vuint32_t NCFSC7:1;
      vuint32_t NCFSC6:1;
      vuint32_t NCFSC5:1;
      vuint32_t NCFSC4:1;
      vuint32_t NCFSC3:1;
      vuint32_t NCFSC2:1;
      vuint32_t NCFSC1:1;
      vuint32_t NCFSC0:1;
    } B;
  } NCFS_CFG[3];

  uint8_t FCCU_reserved2[40];
  union {                              /* NCF Status Register */
    vuint32_t R;
    struct {
      vuint32_t NCFS31:1;
      vuint32_t NCFS30:1;
      vuint32_t NCFS29:1;
      vuint32_t NCFS28:1;
      vuint32_t NCFS27:1;
      vuint32_t NCFS26:1;
      vuint32_t NCFS25:1;
      vuint32_t NCFS24:1;
      vuint32_t NCFS23:1;
      vuint32_t NCFS22:1;
      vuint32_t NCFS21:1;
      vuint32_t NCFS20:1;
      vuint32_t NCFS19:1;
      vuint32_t NCFS18:1;
      vuint32_t NCFS17:1;
      vuint32_t NCFS16:1;
      vuint32_t NCFS15:1;
      vuint32_t NCFS14:1;
      vuint32_t NCFS13:1;
      vuint32_t NCFS12:1;
      vuint32_t NCFS11:1;
      vuint32_t NCFS10:1;
      vuint32_t NCFS9:1;
      vuint32_t NCFS8:1;
      vuint32_t NCFS7:1;
      vuint32_t NCFS6:1;
      vuint32_t NCFS5:1;
      vuint32_t NCFS4:1;
      vuint32_t NCFS3:1;
      vuint32_t NCFS2:1;
      vuint32_t NCFS1:1;
      vuint32_t NCFS0:1;
    } B;
  } NCF_S[2];

  uint8_t FCCU_reserved3[8];
  union {                              /* NCF Key Register */
    vuint32_t R;
    struct {
      vuint32_t NCFK:32;
    } B;
  } NCFK;

  union {                              /* NCF Enable Register */
    vuint32_t R;
    struct {
      vuint32_t NCFE31:1;
      vuint32_t NCFE30:1;
      vuint32_t NCFE29:1;
      vuint32_t NCFE28:1;
      vuint32_t NCFE27:1;
      vuint32_t NCFE26:1;
      vuint32_t NCFE25:1;
      vuint32_t NCFE24:1;
      vuint32_t NCFE23:1;
      vuint32_t NCFE22:1;
      vuint32_t NCFE21:1;
      vuint32_t NCFE20:1;
      vuint32_t NCFE19:1;
      vuint32_t NCFE18:1;
      vuint32_t NCFE17:1;
      vuint32_t NCFE16:1;
      vuint32_t NCFE15:1;
      vuint32_t NCFE14:1;
      vuint32_t NCFE13:1;
      vuint32_t NCFE12:1;
      vuint32_t NCFE11:1;
      vuint32_t NCFE10:1;
      vuint32_t NCFE9:1;
      vuint32_t NCFE8:1;
      vuint32_t NCFE7:1;
      vuint32_t NCFE6:1;
      vuint32_t NCFE5:1;
      vuint32_t NCFE4:1;
      vuint32_t NCFE3:1;
      vuint32_t NCFE2:1;
      vuint32_t NCFE1:1;
      vuint32_t NCFE0:1;
    } B;
  } NCF_E[2];

  uint8_t FCCU_reserved4[8];
  union {                              /* NCF Time-out Enable Register */
    vuint32_t R;
    struct {
      vuint32_t NCFTOE31:1;
      vuint32_t NCFTOE30:1;
      vuint32_t NCFTOE29:1;
      vuint32_t NCFTOE28:1;
      vuint32_t NCFTOE27:1;
      vuint32_t NCFTOE26:1;
      vuint32_t NCFTOE25:1;
      vuint32_t NCFTOE24:1;
      vuint32_t NCFTOE23:1;
      vuint32_t NCFTOE22:1;
      vuint32_t NCFTOE21:1;
      vuint32_t NCFTOE20:1;
      vuint32_t NCFTOE19:1;
      vuint32_t NCFTOE18:1;
      vuint32_t NCFTOE17:1;
      vuint32_t NCFTOE16:1;
      vuint32_t NCFTOE15:1;
      vuint32_t NCFTOE14:1;
      vuint32_t NCFTOE13:1;
      vuint32_t NCFTOE12:1;
      vuint32_t NCFTOE11:1;
      vuint32_t NCFTOE10:1;
      vuint32_t NCFTOE9:1;
      vuint32_t NCFTOE8:1;
      vuint32_t NCFTOE7:1;
      vuint32_t NCFTOE6:1;
      vuint32_t NCFTOE5:1;
      vuint32_t NCFTOE4:1;
      vuint32_t NCFTOE3:1;
      vuint32_t NCFTOE2:1;
      vuint32_t NCFTOE1:1;
      vuint32_t NCFTOE0:1;
    } B;
  } NCF_TOE[2];

  uint8_t FCCU_reserved5[8];
  union {                              /* NCF Time-out Register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;
    } B;
  } NCF_TO;

  union {                              /* CFG Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TO:3;
    } B;
  } CFG_TO;

  union {                              /* IO Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t EIN1:1;
      vuint32_t EIN0:1;
      vuint32_t  :2;
      vuint32_t EOUT1:1;
      vuint32_t EOUT0:1;
    } B;
  } EINOUT;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t PhysicErrorPin:2;
      vuint32_t ESTAT:1;
      vuint32_t STATUS:3;
    } B;
  } STAT;

  union {                              /* NA Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t NAFS:8;
    } B;
  } N2AF_STATUS;

  union {                              /* AF Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t AF_SRC:2;
      vuint32_t AFFS:8;
    } B;
  } A2FF_STATUS;

  union {                              /* NF Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t NF_SRC:2;
      vuint32_t NFFS:8;
    } B;
  } N2FF_STATUS;

  union {                              /* FA Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t FAFS:9;
    } B;
  } F2A_STATUS;

  union {                              /* SC Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t RCCS1:1;
      vuint32_t RCCS0:1;
    } B;
  } SCFS;

  uint8_t FCCU_reserved6[4];
  union {                              /* NCF Fake Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FNCFC:7;
    } B;
  } NCFF;

  union {                              /* IRQ Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t NMI_STAT:1;
      vuint32_t ALRM_STAT:1;
      vuint32_t CFG_TO_STAT:1;
    } B;
  } IRQ_STAT;

  union {                              /* IRQ Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t CFG_TO_IEN:1;
    } B;
  } IRQ_EN;

  union {                              /* XTMR Register */
    vuint32_t R;
    struct {
      vuint32_t XTMR:32;
    } B;
  } XTMR;

  union {                              /* MCS Register */
    vuint32_t R;
    struct {
      vuint32_t VL3:1;
      vuint32_t FS3:1;
      vuint32_t  :2;
      vuint32_t MCS3:4;
      vuint32_t VL2:1;
      vuint32_t FS2:1;
      vuint32_t  :2;
      vuint32_t MCS2:4;
      vuint32_t VL1:1;
      vuint32_t FS1:1;
      vuint32_t  :2;
      vuint32_t MCS1:4;
      vuint32_t VL0:1;
      vuint32_t FS0:1;
      vuint32_t  :2;
      vuint32_t MCS0:4;
    } B;
  } MCS;

  union {                              /* Transient Lock Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t TRANSKEY:9;
    } B;
  } TRANS_LOCK;

  union {                              /* Permanent Lock Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t PERMNTKEY:9;
    } B;
  } PERMNT_LOCK;

  union {                              /* Delta T Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t  :14;
      vuint32_t  :2;
      vuint32_t DELTA_T:14;
    } B;
  } DELTA_T;

  union {                              /* IRQ Alarm Enable Register */
    vuint32_t R;
    struct {
      vuint32_t IRQEN31:1;
      vuint32_t IRQEN30:1;
      vuint32_t IRQEN29:1;
      vuint32_t IRQEN28:1;
      vuint32_t IRQEN27:1;
      vuint32_t IRQEN26:1;
      vuint32_t IRQEN25:1;
      vuint32_t IRQEN24:1;
      vuint32_t IRQEN23:1;
      vuint32_t IRQEN22:1;
      vuint32_t IRQEN21:1;
      vuint32_t IRQEN20:1;
      vuint32_t IRQEN19:1;
      vuint32_t IRQEN18:1;
      vuint32_t IRQEN17:1;
      vuint32_t IRQEN16:1;
      vuint32_t IRQEN15:1;
      vuint32_t IRQEN14:1;
      vuint32_t IRQEN13:1;
      vuint32_t IRQEN12:1;
      vuint32_t IRQEN11:1;
      vuint32_t IRQEN10:1;
      vuint32_t IRQEN9:1;
      vuint32_t IRQEN8:1;
      vuint32_t IRQEN7:1;
      vuint32_t IRQEN6:1;
      vuint32_t IRQEN5:1;
      vuint32_t IRQEN4:1;
      vuint32_t IRQEN3:1;
      vuint32_t IRQEN2:1;
      vuint32_t IRQEN1:1;
      vuint32_t IRQEN0:1;
    } B;
  } IRQ_ALARM_EN[2];

  uint8_t FCCU_reserved7[8];
  union {                              /* NMI Enable Register */
    vuint32_t R;
    struct {
      vuint32_t NMIEN31:1;
      vuint32_t NMIEN30:1;
      vuint32_t NMIEN29:1;
      vuint32_t NMIEN28:1;
      vuint32_t NMIEN27:1;
      vuint32_t NMIEN26:1;
      vuint32_t NMIEN25:1;
      vuint32_t NMIEN24:1;
      vuint32_t NMIEN23:1;
      vuint32_t NMIEN22:1;
      vuint32_t NMIEN21:1;
      vuint32_t NMIEN20:1;
      vuint32_t NMIEN19:1;
      vuint32_t NMIEN18:1;
      vuint32_t NMIEN17:1;
      vuint32_t NMIEN16:1;
      vuint32_t NMIEN15:1;
      vuint32_t NMIEN14:1;
      vuint32_t NMIEN13:1;
      vuint32_t NMIEN12:1;
      vuint32_t NMIEN11:1;
      vuint32_t NMIEN10:1;
      vuint32_t NMIEN9:1;
      vuint32_t NMIEN8:1;
      vuint32_t NMIEN7:1;
      vuint32_t NMIEN6:1;
      vuint32_t NMIEN5:1;
      vuint32_t NMIEN4:1;
      vuint32_t NMIEN3:1;
      vuint32_t NMIEN2:1;
      vuint32_t NMIEN1:1;
      vuint32_t NMIEN0:1;
    } B;
  } NMI_EN[2];

  uint8_t FCCU_reserved8[8];
  union {                              /* EOUT Signaling Enable Register */
    vuint32_t R;
    struct {
      vuint32_t EOUTEN31:1;
      vuint32_t EOUTEN30:1;
      vuint32_t EOUTEN29:1;
      vuint32_t EOUTEN28:1;
      vuint32_t EOUTEN27:1;
      vuint32_t EOUTEN26:1;
      vuint32_t EOUTEN25:1;
      vuint32_t EOUTEN24:1;
      vuint32_t EOUTEN23:1;
      vuint32_t EOUTEN22:1;
      vuint32_t EOUTEN21:1;
      vuint32_t EOUTEN20:1;
      vuint32_t EOUTEN19:1;
      vuint32_t EOUTEN18:1;
      vuint32_t EOUTEN17:1;
      vuint32_t EOUTEN16:1;
      vuint32_t EOUTEN15:1;
      vuint32_t EOUTEN14:1;
      vuint32_t EOUTEN13:1;
      vuint32_t EOUTEN12:1;
      vuint32_t EOUTEN11:1;
      vuint32_t EOUTEN10:1;
      vuint32_t EOUTEN9:1;
      vuint32_t EOUTEN8:1;
      vuint32_t EOUTEN7:1;
      vuint32_t EOUTEN6:1;
      vuint32_t EOUTEN5:1;
      vuint32_t EOUTEN4:1;
      vuint32_t EOUTEN3:1;
      vuint32_t EOUTEN2:1;
      vuint32_t EOUTEN1:1;
      vuint32_t EOUTEN0:1;
    } B;
  } EOUT_SIG_EN[2];
};


/****************************************************************************/
/*                     MODULE : Clock Monitor Unit (CMU)                    */
/****************************************************************************/
struct CMU_tag {
    union {
      vuint32_t R;
        struct {
          vuint32_t  :8;           
          vuint32_t SFM:1;           
          vuint32_t  :13;          
          vuint32_t CKSEL1:2;          
          vuint32_t  :5;           
          vuint32_t RCDIV:2;           
          vuint32_t CME:1;           
      } B;
    } CSR;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :12;          
          vuint32_t FD:20;           
      } B;
    } FDR;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :20;          
          vuint32_t HFREF:12;          
      } B;
    } HFREFR;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :20;          
          vuint32_t LFREF:12;          
      } B;
    } LFREFR;
  
    union {
      vuint32_t R;
        struct {
          vuint32_t  :28;          
          vuint32_t FLCI:1;          
          vuint32_t FHHI:1;          
          vuint32_t FLLI:1;          
          vuint32_t OLRI:1;          
      } B;
    } ISR;
  
    uint8_t CMU_reserved0[4];
    union {
      vuint32_t R;
        struct {
          vuint32_t  :12;          
          vuint32_t MD:20;           
      } B;
    } MDR;
};

/****************************************************************************/
/*                     MODULE : PSI5                                        */
/****************************************************************************/
    struct PSI5_tag {
      union {
        vuint16_t R;
          struct {
            vuint16_t  :14;          
            vuint16_t CTC_GED:1;           
            vuint16_t GLOBAL_DISABLE_REQ:1;          
        } B;
      } GCR;
    
      uint8_t PSI5_reserved0[6];
      union {
        vuint32_t R;
          struct {
            vuint32_t CTC_GED_SEL:1;           
            vuint32_t CTC_ED:1;          
            vuint32_t  :1;           
            vuint32_t MEM_DEPTH:5;           
            vuint32_t  :3;           
            vuint32_t ERROR_SELECT4:1;           
            vuint32_t ERROR_SELECT3:1;           
            vuint32_t ERROR_SELECT2:1;           
            vuint32_t ERROR_SELECT1:1;           
            vuint32_t ERROR_SELECT0:1;           
            vuint32_t  :1;           
            vuint32_t GTM_RESET_ASYNC_EN:1;          
            vuint32_t  :3;           
            vuint32_t  :1;           
            vuint32_t DEBUG_FREEZE_CTRL:1;           
            vuint32_t SP_TS_CLK_SEL:1;           
            vuint32_t  :2;           
            vuint32_t FAST_CLR_SMC:1;          
            vuint32_t FAST_CLR_PSI5:1;           
            vuint32_t BIT_RATE:1;          
            vuint32_t MODE:1;          
            vuint32_t PSI5_CH_CONFIG:1;          
            vuint32_t PSI5_CH_EN:1;          
        } B;
      } CH0_PCCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :3;           
            vuint32_t DMA_PM_DS_WM:5;          
            vuint32_t  :5;           
            vuint32_t IE_DMA_TF_SF:1;          
            vuint32_t IE_DMA_TF_PM_DS:1;           
            vuint32_t  :5;           
            vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;          
            vuint32_t IE_DMA_SFUF:1;           
            vuint32_t  :1;           
            vuint32_t IE_DMA_PM_DS_UF:1;           
            vuint32_t  :5;           
            vuint32_t DMA_EN_SF:1;           
            vuint32_t DMA_PM_DS_CONFIG:2;          
        } B;
      } CH0_DCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t IS_DMA_TF_SF:1;          
            vuint32_t IS_DMA_TF_PM_DS:1;           
            vuint32_t  :5;           
            vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;          
            vuint32_t IS_DMA_SFUF:1;           
            vuint32_t  :1;           
            vuint32_t IS_DMA_PM_DS_UF:1;           
            vuint32_t  :8;           
        } B;
      } CH0_DSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :2;           
            vuint32_t IE_CESM:6;           
            vuint32_t IE_STS:1;          
            vuint32_t IE_DTS:1;          
            vuint32_t IE_DSROW:1;          
            vuint32_t IE_BROW:1;           
            vuint32_t IE_PROW:1;           
            vuint32_t IE_DSRR:1;           
            vuint32_t IE_BRR:1;          
            vuint32_t IE_PRR:1;          
            vuint32_t  :2;           
            vuint32_t IE_OWSM:6;           
            vuint32_t  :2;           
            vuint32_t IE_NVSM:6;           
        } B;
      } CH0_GICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t IE_ND:32;          
        } B;
      } CH0_NDICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t IE_OW:32;          
        } B;
      } CH0_OWICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t IE_ERROR:32;           
        } B;
      } CH0_EICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :2;           
            vuint32_t IS_CESM:6;           
            vuint32_t IS_STS:1;          
            vuint32_t IS_DTS:1;          
            vuint32_t IS_DSROW:1;          
            vuint32_t IS_BROW:1;           
            vuint32_t IS_PROW:1;           
            vuint32_t DSR_RDY:1;           
            vuint32_t DBR_RDY:1;           
            vuint32_t DPR_RDY:1;           
            vuint32_t  :2;           
            vuint32_t IS_OWSM:6;           
            vuint32_t  :2;           
            vuint32_t IS_NVSM:6;           
        } B;
      } CH0_GISR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t PSI5_RXDATA:32;          
        } B;
      } CH0_DPMR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SMC_RXDATA:32;           
        } B;
      } CH0_DSFR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DDS:32;          
        } B;
      } CH0_DDSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRC:3;           
            vuint32_t C:1;           
        } B;
      } CH0_PMRRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t SlotCounter:3;           
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRRH;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL0;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH0;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL1;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH1;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL2;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH2;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL3;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH3;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL4;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH4;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL5;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH5;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL6;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH6;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL7;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH7;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL8;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH8;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL9;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH9;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL10;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH10;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL11;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH11;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL12;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH12;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL13;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH13;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL14;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH14;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL15;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH15;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL16;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH16;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL17;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH17;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL18;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH18;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL19;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH19;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL20;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH20;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL21;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH21;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL22;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH22;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL23;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH23;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL24;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH24;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL25;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH25;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL26;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH26;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL27;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH27;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL28;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH28;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL29;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH29;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL30;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH30;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH0_PMRL31;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH0_PMRH31;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH0_SFR1;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH0_SFR2;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH0_SFR3;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH0_SFR4;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH0_SFR5;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH0_SFR6;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t NDS:32;          
        } B;
      } CH0_NDSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t OWS:32;          
        } B;
      } CH0_OWSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t ERROR:32;          
        } B;
      } CH0_EISR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SNDS:32;           
        } B;
      } CH0_SNDSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SOWS:32;           
        } B;
      } CH0_SOWSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SERROR:32;           
        } B;
      } CH0_SEISR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :2;           
            vuint32_t SCESM:6;           
            vuint32_t  :10;          
            vuint32_t SOWSM:6;           
            vuint32_t  :2;           
            vuint32_t SNVSM:6;           
        } B;
      } CH0_SSESR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :8;           
            vuint32_t STSV:24;           
        } B;
      } CH0_STSRR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :5;           
            vuint32_t SLOT_COUNTER:3;          
            vuint32_t DTSV:24;           
        } B;
      } CH0_DTSRR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH0_S1FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH0_S2FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH0_S3FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH0_S4FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH0_S5FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH0_S6FCR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S1SBT:15;          
        } B;
      } CH0_S1SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S2SBT:15;          
        } B;
      } CH0_S2SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S3SBT:15;          
        } B;
      } CH0_S3SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S4SBT:15;          
        } B;
      } CH0_S4SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S5SBT:15;          
        } B;
      } CH0_S5SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S6SBT:15;          
        } B;
      } CH0_S6SBR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_NO:3;           
            vuint32_t  :1;           
            vuint32_t SnEBT:15;          
        } B;
      } CH0_SnEBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t DATA_LENGTH:6;           
            vuint16_t DBR_RST:1;           
            vuint16_t DSR_RST:1;           
            vuint16_t CMD_TYPE:3;          
            vuint16_t DEFAULT_SYNC:1;          
            vuint16_t GTM_TRIG_SEL:1;          
            vuint16_t SP_PULSE_SEL:1;          
            vuint16_t OP_SEL:1;          
            vuint16_t SW_READY:1;          
        } B;
      } CH0_DOBCR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :9;           
            vuint16_t MDDIS_OFF:7;           
        } B;
      } CH0_MDDIS_OFF;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :9;           
            vuint16_t Pulse_Width0:7;          
        } B;
      } CH0_PW0D;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :9;           
            vuint16_t Pulse_Width1:7;          
        } B;
      } CH0_PW1D;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t CTPR:16;           
        } B;
      } CH0_CTPR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t CIPR:16;           
        } B;
      } CH0_CIPR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :8;           
            vuint32_t DPR:24;          
        } B;
      } CH0_DPRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t dummy :32;          
        } B;
      } CH0_DPRH;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DBR:32;          
        } B;
      } CH0_DBRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DBR:32;          
        } B;
      } CH0_DBRH;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DSR:32;          
        } B;
      } CH0_DSRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DSR:32;          
        } B;
      } CH0_DSRH;
    
      uint8_t PSI5_reserved1[4];
      union {
        vuint32_t R;
          struct {
            vuint32_t CTC_GED_SEL:1;           
            vuint32_t CTC_ED:1;          
            vuint32_t  :1;           
            vuint32_t MEM_DEPTH:5;           
            vuint32_t  :3;           
            vuint32_t ERROR_SELECT4:1;           
            vuint32_t ERROR_SELECT3:1;           
            vuint32_t ERROR_SELECT2:1;           
            vuint32_t ERROR_SELECT1:1;           
            vuint32_t ERROR_SELECT0:1;           
            vuint32_t  :1;           
            vuint32_t GTM_RESET_ASYNC_EN:1;          
            vuint32_t  :3;           
            vuint32_t  :1;           
            vuint32_t DEBUG_FREEZE_CTRL:1;           
            vuint32_t SP_TS_CLK_SEL:1;           
            vuint32_t  :2;           
            vuint32_t FAST_CLR_SMC:1;          
            vuint32_t FAST_CLR_PSI5:1;           
            vuint32_t BIT_RATE:1;          
            vuint32_t MODE:1;          
            vuint32_t PSI5_CH_CONFIG:1;          
            vuint32_t PSI5_CH_EN:1;          
        } B;
      } CH1_PCCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :3;           
            vuint32_t DMA_PM_DS_WM:5;          
            vuint32_t  :5;           
            vuint32_t IE_DMA_TF_SF:1;          
            vuint32_t IE_DMA_TF_PM_DS:1;           
            vuint32_t  :5;           
            vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;          
            vuint32_t IE_DMA_SFUF:1;           
            vuint32_t  :1;           
            vuint32_t IE_DMA_PM_DS_UF:1;           
            vuint32_t  :5;           
            vuint32_t DMA_EN_SF:1;           
            vuint32_t DMA_PM_DS_CONFIG:2;          
        } B;
      } CH1_DCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t IS_DMA_TF_SF:1;          
            vuint32_t IS_DMA_TF_PM_DS:1;           
            vuint32_t  :5;           
            vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;          
            vuint32_t IS_DMA_SFUF:1;           
            vuint32_t  :1;           
            vuint32_t IS_DMA_PM_DS_UF:1;           
            vuint32_t  :8;           
        } B;
      } CH1_DSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :2;           
            vuint32_t IE_CESM:6;           
            vuint32_t IE_STS:1;          
            vuint32_t IE_DTS:1;          
            vuint32_t IE_DSROW:1;          
            vuint32_t IE_BROW:1;           
            vuint32_t IE_PROW:1;           
            vuint32_t IE_DSRR:1;           
            vuint32_t IE_BRR:1;          
            vuint32_t IE_PRR:1;          
            vuint32_t  :2;           
            vuint32_t IE_OWSM:6;           
            vuint32_t  :2;           
            vuint32_t IE_NVSM:6;           
        } B;
      } CH1_GICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t IE_ND:32;          
        } B;
      } CH1_NDICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t IE_OW:32;          
        } B;
      } CH1_OWICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t IE_ERROR:32;           
        } B;
      } CH1_EICR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :2;           
            vuint32_t IS_CESM:6;           
            vuint32_t IS_STS:1;          
            vuint32_t IS_DTS:1;          
            vuint32_t IS_DSROW:1;          
            vuint32_t IS_BROW:1;           
            vuint32_t IS_PROW:1;           
            vuint32_t DSR_RDY:1;           
            vuint32_t DBR_RDY:1;           
            vuint32_t DPR_RDY:1;           
            vuint32_t  :2;           
            vuint32_t IS_OWSM:6;           
            vuint32_t  :2;           
            vuint32_t IS_NVSM:6;           
        } B;
      } CH1_GISR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t PSI5_RXDATA:32;          
        } B;
      } CH1_DPMR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SMC_RXDATA:32;           
        } B;
      } CH1_DSFR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DDS:32;          
        } B;
      } CH1_DDSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRC:3;           
            vuint32_t C:1;           
        } B;
      } CH1_PMRRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t SlotCounter:3;           
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRRH;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL0;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH0;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL1;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH1;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL2;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH2;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL3;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH3;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL4;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH4;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL5;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH5;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL6;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH6;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL7;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH7;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL8;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH8;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL9;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH9;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL10;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH10;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL11;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH11;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL12;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH12;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL13;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH13;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL14;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH14;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL15;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH15;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL16;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH16;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL17;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH17;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL18;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH18;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL19;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH19;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL20;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH20;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL21;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH21;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL22;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH22;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL23;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH23;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL24;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH24;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL25;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH25;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL26;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH26;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL27;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH27;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL28;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH28;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL29;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH29;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL30;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH30;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DATA_REGION:28;          
            vuint32_t CRCP:3;          
            vuint32_t C:1;           
        } B;
      } CH1_PMRL31;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t O:1;           
            vuint32_t F:1;           
            vuint32_t EM:1;          
            vuint32_t E:1;           
            vuint32_t T:1;           
            vuint32_t Slot_Counter:3;          
            vuint32_t TimeStampValue:24;           
        } B;
      } CH1_PMRH31;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH1_SFR1;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH1_SFR2;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH1_SFR3;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH1_SFR4;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH1_SFR5;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SLOT_NO:3;           
            vuint32_t CER:1;           
            vuint32_t OW:1;          
            vuint32_t CRC:6;           
            vuint32_t C:1;           
            vuint32_t ID:4;          
            vuint32_t IDDATA:4;          
            vuint32_t DATA:12;           
        } B;
      } CH1_SFR6;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t NDS:32;          
        } B;
      } CH1_NDSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t OWS:32;          
        } B;
      } CH1_OWSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t ERROR:32;          
        } B;
      } CH1_EISR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SNDS:32;           
        } B;
      } CH1_SNDSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SOWS:32;           
        } B;
      } CH1_SOWSR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t SERROR:32;           
        } B;
      } CH1_SEISR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :2;           
            vuint32_t SCESM:6;           
            vuint32_t  :10;          
            vuint32_t SOWSM:6;           
            vuint32_t  :2;           
            vuint32_t SNVSM:6;           
        } B;
      } CH1_SSESR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :8;           
            vuint32_t STSV:24;           
        } B;
      } CH1_STSRR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :5;           
            vuint32_t SLOT_COUNTER:3;          
            vuint32_t DTSV:24;           
        } B;
      } CH1_DTSRR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH1_S1FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH1_S2FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH1_S3FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH1_S4FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH1_S5FCR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_EN:1;           
            vuint32_t TS_CAPT:1;           
            vuint32_t  :1;           
            vuint32_t SMCL:1;          
            vuint32_t  :9;           
            vuint32_t DRL:5;           
            vuint32_t CRCP:1;          
        } B;
      } CH1_S6FCR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S1SBT:15;          
        } B;
      } CH1_S1SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S2SBT:15;          
        } B;
      } CH1_S2SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S3SBT:15;          
        } B;
      } CH1_S3SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S4SBT:15;          
        } B;
      } CH1_S4SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S5SBT:15;          
        } B;
      } CH1_S5SBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :1;           
            vuint16_t S6SBT:15;          
        } B;
      } CH1_S6SBR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :13;          
            vuint32_t SLOT_NO:3;           
            vuint32_t  :1;           
            vuint32_t SnEBT:15;          
        } B;
      } CH1_SnEBR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t DATA_LENGTH:6;           
            vuint16_t DBR_RST:1;           
            vuint16_t DSR_RST:1;           
            vuint16_t CMD_TYPE:3;          
            vuint16_t DEFAULT_SYNC:1;          
            vuint16_t GTM_TRIG_SEL:1;          
            vuint16_t SP_PULSE_SEL:1;          
            vuint16_t OP_SEL:1;          
            vuint16_t SW_READY:1;          
        } B;
      } CH1_DOBCR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :9;           
            vuint16_t MDDIS_OFF:7;           
        } B;
      } CH1_MDDIS_OFF;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :9;           
            vuint16_t Pulse_Width0:7;          
        } B;
      } CH1_PW0D;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t  :9;           
            vuint16_t Pulse_Width1:7;          
        } B;
      } CH1_PW1D;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t CTPR:16;           
        } B;
      } CH1_CTPR;
    
      union {
        vuint16_t R;
          struct {
            vuint16_t CIPR:16;           
        } B;
      } CH1_CIPR;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  :8;           
            vuint32_t DPR:24;          
        } B;
      } CH1_DPRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t  dummy :32;          
        } B;
      } CH1_DPRH;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DBR:32;          
        } B;
      } CH1_DBRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DBR:32;          
        } B;
      } CH1_DBRH;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DSR:32;          
        } B;
      } CH1_DSRL;
    
      union {
        vuint32_t R;
          struct {
            vuint32_t DSR:32;          
        } B;
      } CH1_DSRH;

};

/****************************************************************************/
/*                     MODULE : Sigma-Delta ADC (SDADC)                     */
/****************************************************************************/
    struct SDADC_tag {
        union {
            vuint32_t R;
            struct {
                vuint32_t:3;
                vuint32_t PDR:5;
                  vuint32_t:1;
                vuint32_t PGAN:3;
                vuint32_t ODF:1;
                vuint32_t ODA:1;
                vuint32_t EMSEL:1;
                vuint32_t HPFEN:1;
                  vuint32_t:1;
                vuint32_t TRIGEDSEL:2;
                vuint32_t TRIGEN:1;
                vuint32_t TRIGSEL:4;
                vuint32_t FRZ:1;
                  vuint32_t:2;
                vuint32_t VCOMSEL:1;
                  vuint32_t:1;
                vuint32_t GECEN:1;
                vuint32_t MODE:1;
                vuint32_t EN:1;
            } B;
        } MCR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t BIASEN:8;
                  vuint32_t:13;
                vuint32_t ANCHSEL:3;
            } B;
        } CSR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t RESET_KEY:16;
            } B;
        } RKR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:23;
                vuint32_t DFEF:1;
                  vuint32_t:5;
                vuint32_t CDVF:1;
                vuint32_t DFORF:1;
                vuint32_t DFFF:1;
            } B;
        } SFR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:15;
                vuint32_t DFFDIRS:1;
                vuint32_t GDIGE:1;
                  vuint32_t:12;
                vuint32_t CDVEE:1;
                vuint32_t DFORIE:1;
                vuint32_t DFFDIRE:1;
            } B;
        } RSER;

        union {
            vuint32_t R;
            struct {
                vuint32_t:24;
                vuint32_t OSD:8;
            } B;
        } OSDR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:20;
                vuint32_t FTHLD:4;
                  vuint32_t:5;
                vuint32_t FSIZE:2;
                vuint32_t FE:1;
            } B;
        } FCR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t ST_KEY:16;
            } B;
        } STKR;

        union {
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t CDATA:16;     /* ODA=0 */
                /* vuint32_t CDATA:14; */ /* ODA=1 */
                /* vuint32_t:2; */        /* ODA=1 */
            } B;
        } CDR;
    };

/****************************************************************************/
/*                     MODULE : SENT Receiver (SRX)                         */
/****************************************************************************/
struct SRX_tag {
  union {                              /* Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t TSPRSC:8;
      vuint32_t  :3;
      vuint32_t FIFOWM:5;
      vuint32_t NIB_LEN_VAR_LIMIT:1;   /* Decides the allowable jitter/clock drift limit for nibble length measurement. */
      vuint32_t  :4;
      vuint32_t FMFOIE:1;
      vuint32_t FMDUIE:1;
      vuint32_t SMDUIE:1;
      vuint32_t  :1;
      vuint32_t FIFO_EN:1;
      vuint32_t  :1;
      vuint32_t FAST_CLR:1;
      vuint32_t  :1;
      vuint32_t DBG_FRZ:1;
      vuint32_t  :1;
      vuint32_t SENT_EN:1;
    } B;
  } GBL_CTRL;

  union {                              /* Channel Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t EN_CH:6;
    } B;
  } CHNL_EN;

  union {                              /* Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t FMFO:1;
      vuint32_t FDMU:1;
      vuint32_t SMDU:1;
      vuint32_t  :8;
    } B;
  } GBL_STATUS;

  union {                              /* Fast Message Ready Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F_RDY:6;
    } B;
  } FMSG_RDY;

  union {                              /* Slow Serial Message Ready Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t S_RDY:6;
    } B;
  } SMSG_RDY;

  uint8_t SRX_reserved0[4];
  union {                              /* Data Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t NIBBCH0:3;
      vuint32_t  :1;
      vuint32_t NIBBCH1:3;
      vuint32_t  :1;
      vuint32_t NIBBCH2:3;
      vuint32_t  :1;
      vuint32_t NIBBCH3:3;
      vuint32_t  :1;
      vuint32_t NIBBCH4:3;
      vuint32_t  :1;
      vuint32_t NIBBCH5:3;
      vuint32_t  :1;
      vuint32_t  :3;
      vuint32_t  :1;
      vuint32_t  :3;
    } B;
  } DATA_CTRL1;

  uint8_t SRX_reserved1[12];
  union {                              /* Fast Message DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t FDMA_EN:6;
    } B;
  } FDMA_CTRL;

  union {                              /* Slow Serial Message DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t SDMA_EN:6;
    } B;
  } SDMA_CTRL;

  uint8_t SRX_reserved2[4];
  union {                              /* Fast Message Ready Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t FRDY_IE:6;
    } B;
  } FRDY_IE;

  union {                              /* Slow Serial Message Ready Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t SRDY_IE:6;
    } B;
  } SRDY_IE;

  uint8_t SRX_reserved3[4];
  union {                              /* DMA Fast Message Data Read Register */
    vuint32_t R;
    struct {
      vuint32_t CHNUM:4;
      vuint32_t SCNIB:4;
      vuint32_t DNIB1:4;
      vuint32_t DNIB2:4;
      vuint32_t DNIB3:4;
      vuint32_t DNIB4:4;
      vuint32_t DNIB5:4;
      vuint32_t DNIB6:4;
    } B;
  } DMA_FMSG_DATA;

  union {                              /* DMA Fast Message CRC Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t CRC4b:4;
      vuint32_t  :16;
    } B;
  } DMA_FMSG_CRC;

  union {                              /* DMA Fast Message Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t TS:32;
    } B;
  } DMA_FMSG_TS;

  uint8_t SRX_reserved4[4];
  union {                              /* DMA Slow Serial Message Bit3 Read Register */
    vuint32_t R;
    struct {
      vuint32_t CHNUM:4;
      vuint32_t TYPE:1;
      vuint32_t  :16;
      vuint32_t CFG:1;
      vuint32_t ID7_4_D3_0:4;
      vuint32_t  :1;
      vuint32_t ID3_0_DATA15_12:4;
      vuint32_t  :1;
    } B;
  } DMA_SMSG_BIT3;

  union {                              /* DMA Slow Serial Message Bit2 Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t SMCRC:6;
      vuint32_t  :4;
      vuint32_t DATA:12;
    } B;
  } DMA_SMSG_BIT2;

  union {                              /* DMA Slow Serial Message Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t TS:32;
    } B;
  } DMA_SMSG_TS;

  uint8_t SRX_reserved5[4];
  struct {
    union {                            /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t CM_PRSC:15;
        vuint32_t COMP_EN:1;
        vuint32_t  :1;
        vuint32_t PRSC:14;
      } B;
    } CLK_CTRL;
    union {                            /* Channel 'n' Status Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t BUS_IDLE:1;
        vuint32_t  :3;
        vuint32_t CAL_RESYNC:1;
        vuint32_t CAL_20_25:1;
        vuint32_t SMSG_OFLW:1;
        vuint32_t FMSG_OFLW:1;
        vuint32_t  :1;
        vuint32_t PP_DIAG_ERR:1;
        vuint32_t CAL_LEN_ERR:1;
        vuint32_t CAL_DIAG_ERR:1;
        vuint32_t NIB_VAL_ERR:1;
        vuint32_t SMSG_CRC_ERR:1;
        vuint32_t FMSG_CRC_ERR:1;
        vuint32_t NUM_EDGES_ERR:1;
        vuint32_t  :16;
      } B;
    } STATUS;
    union {                            /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t BUS_IDLE_CNT:4;
        vuint32_t IE_CAL_RESYNC:1;
        vuint32_t IE_CAL_20_25:1;
        vuint32_t IE_SMSG_OFLW:1;
        vuint32_t IE_FMSG_OFLW:1;
        vuint32_t FCRC_CHK_OFF:1;
        vuint32_t IE_PP_DIAG_ERR:1;
        vuint32_t IE_CAL_LEN_ERR:1;
        vuint32_t IE_CAL_DIAG_ERR:1;
        vuint32_t IE_NIB_VAL_ERR:1;
        vuint32_t IE_SMSG_CRC_ERR:1;
        vuint32_t IE_FMSG_CRC_ERR:1;
        vuint32_t IE_NUM_EDGES_ERR:1;
        vuint32_t DCHNG_INT:1;
        vuint32_t CAL_RNG:1;
        vuint32_t PP_CHKSEL:1;
        vuint32_t FCRC_TYPE:1;
        vuint32_t FCRC_SC_EN:1;
        vuint32_t SCRC_TYPE:1;
        vuint32_t PAUSE_EN:1;
        vuint32_t SUCC_CAL_CHK:1;
        vuint32_t FIL_CNT:8;
      } B;
    } CONFIG;
    uint8_t CH_reserved0[4];
  } CH[6];

  uint8_t SRX_reserved6[160];
  struct {
    union {                            /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t CHNUM:4;
        vuint32_t SCNIB:4;
        vuint32_t DNIB1:4;
        vuint32_t DNIB2:4;
        vuint32_t DNIB3:4;
        vuint32_t DNIB4:4;
        vuint32_t DNIB5:4;
        vuint32_t DNIB6:4;
      } B;
    } FMSG_DATA;
    union {                            /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :12;
        vuint32_t CRC4b:4;
        vuint32_t  :16;
      } B;
    } FMSG_CRC;
    union {                            /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t TS:32;
      } B;
    } FMSG_TS;
    union {                            /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t CHNUM:4;
        vuint32_t TYPE:1;
        vuint32_t  :16;
        vuint32_t CFG:1;
        vuint32_t ID7_4_ID3_0:4;
        vuint32_t  :1;
        vuint32_t ID3_0_DATA15_12:4;
        vuint32_t  :1;
      } B;
    } SMSG_BIT3;
    union {                            /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :10;
        vuint32_t SMCRC:6;
        vuint32_t  :4;
        vuint32_t DATA:12;
      } B;
    } SMSG_BIT2;
    union {                            /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t TS:32;
      } B;
    } SMSG_TS;
  } CHANNEL[6];
};

/****************************************************************************/
/*                     MODULE : External Bus Interface (EBI)                */
/****************************************************************************/

    struct CAL_CS_tag {
        union {                 /* Calibration Base Register Bank */
            vuint32_t R;
            struct {
                vuint32_t BA:17;
                vuint32_t:2;
                vuint32_t LWRN:1;
                vuint32_t PS:1;
                vuint32_t EOE:2;
                vuint32_t SBL:1;
                vuint32_t AD_MUX:1;
                vuint32_t BL:1;
                vuint32_t WEBS:1;
                vuint32_t TBDIP:1;
                vuint32_t GCSN:1;
                vuint32_t SETA:1;
                vuint32_t BI:1;
                vuint32_t V:1;
            } B;
        } BR;
        
        union {                 /* Calibration Option Register Bank */
            vuint32_t R;
            struct {
                vuint32_t AM:17;
                vuint32_t:7;
                vuint32_t SCY:4;
                vuint32_t:1;
                vuint32_t BSCY:2;
                vuint32_t:1;
            } B;
        } OR;
    };

    struct EBI_tag {
    
        union {                 /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t ACGE:1;
                vuint32_t:8;
                vuint32_t MDIS:1;
                vuint32_t:3;
                vuint32_t D16_31:1;
                vuint32_t AD_MUX:1;
                vuint32_t DBM:1;
            } B;
        } MCR;
        
        uint32_t EBI_reserved0004;  /* 0x0004-0x0007 */
        
        union {                 /* Transfer Error Status Register */
            vuint32_t R;
            struct {
                vuint32_t:30;
                vuint32_t TEAF:1;
                vuint32_t BMTF:1;
            } B;
        } TESR;
        
        union {                 /* Bus Monitor Control Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t BMT:8;
                vuint32_t BME:1;
                  vuint32_t:7;
            } B;
        } BMCR;
        
        /* Base/Option registers */
        uint32_t EBI_reserved0010[8];  /* 0x0010-0x002F */
        
        uint32_t EBI_reserved0030[4];  /* 0x0030-0x003F */
        
        /* Calibration registers */
        struct CAL_CS_tag CS[4];
        
        uint32_t EBI_reserved0060[4000];  /* 0x0060-0x3FFF */
    
    };

/****************************************************************************/
/*                     MODULE : SIU                                         */
/****************************************************************************/

    struct SIU_tag {
        union {                 /* MCU ID Register 2 */
          vuint32_t R;
            struct {
              vuint32_t SF:1;          
              vuint32_t FLASH_SIZE_1:4;          
              vuint32_t FLASH_SIZE_2:4;          
              vuint32_t  :7;           
              vuint32_t FAMILYNUM:8;           
              vuint32_t  :8;           
          } B;
        } MIDR2;

        union {                 /* MCU ID Register */
            vuint32_t R;
            struct {
                vuint32_t PARTNUM:16;
                vuint32_t PKG:4;
                vuint32_t:4;
                vuint32_t MAJOR_REV:4;
                vuint32_t MINOR_REV:4;
            } B;
        } MIDR;
        
        int32_t SIU_reserved0008;  /* 0x0008-0x000B */
        
        union {                 /* Reset Status Register */
            vuint32_t R;
            struct {
                vuint32_t PORS:1;
                vuint32_t ERS:1;
                vuint32_t:1;
                vuint32_t:1;
                vuint32_t:1;
                vuint32_t:1;    /* CRS - Checkstop reset not supported on e200z7 cores */
                vuint32_t:1;
                vuint32_t:1;
                vuint32_t:1;
                vuint32_t CPURS:1;
                vuint32_t:1;
                vuint32_t FOSURS:1;
                vuint32_t FCCURS:1;
                vuint32_t STCURS:1;
                vuint32_t SSRS:1;
                vuint32_t SERF:1;
                vuint32_t WKPCFG:1;
                vuint32_t:7;
                vuint32_t XOSC:1;
                vuint32_t:2;
                vuint32_t XOSC40:1;
                vuint32_t ABR:1;
                vuint32_t BOOTCFG:2;
                vuint32_t RGF:1;
            } B;
        } RSR;
        
        union {                 /* System Reset Control Register */
            vuint32_t R;
            struct {
                vuint32_t SSR:1;
                vuint32_t SER:1;
                vuint32_t DUMMY:30;   /* Removed CRE bit */
            } B;
        } SRCR;
        
        union {                 /* External Interrupt Status Register */
            vuint32_t R;
            struct {
                vuint32_t NMI0:1;
                vuint32_t NMI1:1;
                vuint32_t:14;
                vuint32_t EIF15:1;
                vuint32_t EIF14:1;
                vuint32_t EIF13:1;
                vuint32_t EIF12:1;
                vuint32_t EIF11:1;
                vuint32_t EIF10:1;
                vuint32_t EIF9:1;
                vuint32_t EIF8:1;
                vuint32_t EIF7:1;
                vuint32_t EIF6:1;
                vuint32_t EIF5:1;
                vuint32_t EIF4:1;
                vuint32_t EIF3:1;
                vuint32_t EIF2:1;
                vuint32_t EIF1:1;
                vuint32_t EIF0:1;
            } B;
        } EISR;
        
        union {                 /* DMA/Interrupt Request Enable Register */
            vuint32_t R;
            struct {
                vuint32_t NMISEL8:1;
                vuint32_t NMISEL9:1;
                vuint32_t:6;
                vuint32_t NMISEL0:1;
                vuint32_t NMISEL1:1;
                vuint32_t:6;
                vuint32_t EIRE15:1;
                vuint32_t EIRE14:1;
                vuint32_t EIRE13:1;
                vuint32_t EIRE12:1;
                vuint32_t EIRE11:1;
                vuint32_t EIRE10:1;
                vuint32_t EIRE9:1;
                vuint32_t EIRE8:1;
                vuint32_t EIRE7:1;
                vuint32_t EIRE6:1;
                vuint32_t EIRE5:1;
                vuint32_t EIRE4:1;
                vuint32_t EIRE3:1;
                vuint32_t EIRE2:1;
                vuint32_t EIRE1:1;
                vuint32_t EIRE0:1;
            } B;
        } DIRER;
        
        union {                 /* DMA/Interrupt Request Select Register */
            vuint32_t R;
            struct {
                vuint32_t:28;
                vuint32_t DIRS3:1;
                vuint32_t DIRS2:1;
                vuint32_t DIRS1:1;
                vuint32_t DIRS0:1;
            } B;
        } DIRSR;
        
        union {                 /* Overrun Status Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t OVF15:1;
                vuint32_t OVF14:1;
                vuint32_t OVF13:1;
                vuint32_t OVF12:1;
                vuint32_t OVF11:1;
                vuint32_t OVF10:1;
                vuint32_t OVF9:1;
                vuint32_t OVF8:1;
                vuint32_t OVF7:1;
                vuint32_t OVF6:1;
                vuint32_t OVF5:1;
                vuint32_t OVF4:1;
                vuint32_t OVF3:1;
                vuint32_t OVF2:1;
                vuint32_t OVF1:1;
                vuint32_t OVF0:1;
            } B;
        } OSR;
        
        union {                 /* Overrun Request Enable Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t ORE15:1;
                vuint32_t ORE14:1;
                vuint32_t ORE13:1;
                vuint32_t ORE12:1;
                vuint32_t ORE11:1;
                vuint32_t ORE10:1;
                vuint32_t ORE9:1;
                vuint32_t ORE8:1;
                vuint32_t ORE7:1;
                vuint32_t ORE6:1;
                vuint32_t ORE5:1;
                vuint32_t ORE4:1;
                vuint32_t ORE3:1;
                vuint32_t ORE2:1;
                vuint32_t ORE1:1;
                vuint32_t ORE0:1;
            } B;
        } ORER;
        
        union {                 /* External IRQ Rising-Edge Event Enable Register */
            vuint32_t R;
            struct {
                vuint32_t IREE_NMI8:1;
                vuint32_t:15;
                vuint32_t IREE15:1;
                vuint32_t IREE14:1;
                vuint32_t IREE13:1;
                vuint32_t IREE12:1;
                vuint32_t IREE11:1;
                vuint32_t IREE10:1;
                vuint32_t IREE9:1;
                vuint32_t IREE8:1;
                vuint32_t IREE7:1;
                vuint32_t IREE6:1;
                vuint32_t IREE5:1;
                vuint32_t IREE4:1;
                vuint32_t IREE3:1;
                vuint32_t IREE2:1;
                vuint32_t IREE1:1;
                vuint32_t IREE0:1;
            } B;
        } IREER;
        
        union {                 /* External IRQ Falling-Edge Event Enable Register */
            vuint32_t R;
            struct {
                vuint32_t IFEE_NMI8:1;
                vuint32_t:15;
                vuint32_t IFEE15:1;
                vuint32_t IFEE14:1;
                vuint32_t IFEE13:1;
                vuint32_t IFEE12:1;
                vuint32_t IFEE11:1;
                vuint32_t IFEE10:1;
                vuint32_t IFEE9:1;
                vuint32_t IFEE8:1;
                vuint32_t IFEE7:1;
                vuint32_t IFEE6:1;
                vuint32_t IFEE5:1;
                vuint32_t IFEE4:1;
                vuint32_t IFEE3:1;
                vuint32_t IFEE2:1;
                vuint32_t IFEE1:1;
                vuint32_t IFEE0:1;
            } B;
        } IFEER;
        
        union {                 /* External IRQ Digital Filter Register */
            vuint32_t R;
            struct {
                vuint32_t:28;
                vuint32_t DFL:4;
            } B;
        } IDFR;

        union {                 /* External IRQ Filtered Input Register */
            vuint32_t R;
            struct {
                vuint32_t FI31:1; /* Legacy name. Refer to IFI_NMI in the manual */
                vuint32_t FI30:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI29:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI28:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI27:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI26:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI25:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI24:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI23:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI22:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI21:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI20:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI19:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI18:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI17:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI16:1; /* Legacy name. Unused/Reserved on MPC577xC */
                vuint32_t FI15:1; /* Legacy name. Refer to IFI15 in the manual */
                vuint32_t FI14:1; /* Legacy name. Refer to IFI14 in the manual */
                vuint32_t FI13:1; /* Legacy name. Refer to IFI13 in the manual */
                vuint32_t FI12:1; /* Legacy name. Refer to IFI12 in the manual */
                vuint32_t FI11:1; /* Legacy name. Refer to IFI11 in the manual */
                vuint32_t FI10:1; /* Legacy name. Refer to IFI10 in the manual */
                vuint32_t FI9:1;  /* Legacy name. Refer to IFI9 in the manual */
                vuint32_t FI8:1;  /* Legacy name. Refer to IFI8 in the manual */
                vuint32_t FI7:1;  /* Legacy name. Refer to IFI7 in the manual */
                vuint32_t FI6:1;  /* Legacy name. Refer to IFI6 in the manual */
                vuint32_t FI5:1;  /* Legacy name. Refer to IFI5 in the manual */
                vuint32_t FI4:1;  /* Legacy name. Refer to IFI4 in the manual */
                vuint32_t FI3:1;  /* Legacy name. Refer to IFI3 in the manual */
                vuint32_t FI2:1;  /* Legacy name. Refer to IFI2 in the manual */
                vuint32_t FI1:1;  /* Legacy name. Refer to IFI1 in the manual */
                vuint32_t FI0:1;  /* Legacy name. Refer to IFI0 in the manual */
            } B;
        } IFIR;
        
        int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */
        
        union {                 /* Pad Configuration Registers */
            vuint16_t R;
            struct {
                vuint16_t:3;
                vuint16_t PA:3;
                vuint16_t OBE:1;
                vuint16_t IBE:1;
                vuint16_t DSC:2;
                vuint16_t ODE:1;
                vuint16_t HYS:1;
                vuint16_t SRC:2;
                vuint16_t WPE:1;
                vuint16_t WPS:1;
            } B;
        } PCR[512];
        
        int16_t SIU_reserved0440[224];  /* 0x0440-0x05FF */
        
        union {                 /* GPIO Pin Data Output Registers */
            vuint8_t R;
            struct {
                vuint8_t:7;
                vuint8_t PDO:1;
            } B;
        } GPDO[512];
        
        union {                 /* GPIO Pin Data Input Registers */
            vuint8_t R;
            struct {
                vuint8_t:7;
                vuint8_t PDI:1;
            } B;
        } GPDI[256];
        
        uint32_t SIU_reserved0900;  /* 0x0900-0x0903 */
        
        union {                 /* External IRQ Input Select Register */
            vuint32_t R;
            struct {
                vuint32_t ESEL15:2;
                vuint32_t ESEL14:2;
                vuint32_t ESEL13:2;
                vuint32_t ESEL12:2;
                vuint32_t ESEL11:2;
                vuint32_t ESEL10:2;
                vuint32_t ESEL9:2;
                vuint32_t ESEL8:2;
                vuint32_t ESEL7:2;
                vuint32_t ESEL6:2;
                vuint32_t ESEL5:2;
                vuint32_t ESEL4:2;
                vuint32_t ESEL3:2;
                vuint32_t ESEL2:2;
                vuint32_t ESEL1:2;
                vuint32_t ESEL0:2;
            } B;
        } EIISR;
        
        union {                 /* DSPI Input Select Register */
            vuint32_t R;
            struct {
                vuint32_t SINSELA:2;
                vuint32_t SSSELA:2;
                vuint32_t SCKSELA:2;
                vuint32_t TRIGSELA:2;
                vuint32_t SINSELB:2;
                vuint32_t SSSELB:2;
                vuint32_t SCKSELB:2;
                vuint32_t TRIGSELB:2;
                vuint32_t SINSELC:2;
                vuint32_t SSSELC:2;
                vuint32_t SCKSELC:2;
                vuint32_t TRIGSELC:2;
                vuint32_t SINSELD:2;
                vuint32_t SSSELD:2;
                vuint32_t SCKSELD:2;
                vuint32_t TRIGSELD:2;
            } B;
        } DISR;
        
        int32_t SIU_reserved090C;  /* 0x090C-0x090F */
        
        union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t CTSEL5_0:7;  /* Legacy name. All CTSELn_0 fields are now CTSELn_A in the manual */
                vuint32_t:1;
                vuint32_t CTSEL4_0:7;
                vuint32_t:1;
                vuint32_t CTSEL3_0:7;
                vuint32_t:1;
                vuint32_t CTSEL2_0:7;
            } B;
        } ISEL4;
        
        union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t CTSEL1_0:7;
                vuint32_t:1;
                vuint32_t CTSEL0_0:7;
                vuint32_t:16;
            } B;
        } ISEL5;
        
        union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t CTSEL5_1:7;  /* Legacy name. All CTSELn_1 fields are now CTSELn_B in the manual */
                vuint32_t:1;
                vuint32_t CTSEL4_1:7;
                vuint32_t:1;
                vuint32_t CTSEL3_1:7;
                vuint32_t:1;
                vuint32_t CTSEL2_1:7;
            } B;
        } ISEL6;
        
        union {                 /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t CTSEL1_1:7;
                vuint32_t:1;
                vuint32_t CTSEL0_1:7;
                vuint32_t:16;
            } B;
        } ISEL7;

        union {                 /* eTPU Input Select Register */
            vuint32_t R;
            struct {
                vuint32_t:11;
                vuint32_t ETPU29:1;
                vuint32_t:3;
                vuint32_t ETPU28:1;
                vuint32_t:3;
                vuint32_t ETPU27:1;
                vuint32_t:3;
                vuint32_t ETPU26:1;
                vuint32_t:3;
                vuint32_t ETPU25:1;
                vuint32_t:3;
                vuint32_t ETPU24:1;
             } B;
        } ISEL8;
        
        union {                 /* eQADC Advanced Trigger Select  */
            vuint32_t R;
            struct {
                vuint32_t:11;
                vuint32_t ETSEL0ADV_A:5;
                vuint32_t:11;
                vuint32_t ETSEL0A:5; /* Legacy name. Refer to eTSEL0ADV_B in the manual */ 
            } B;
        } ISEL9;
        
        union {                 /* DecFilter Integrator Control  */
            vuint32_t R;
            struct {
                vuint32_t HSELD:4;
                vuint32_t ZSELD:4;
                vuint32_t HSELC:4;
                vuint32_t ZSELC:4;
                vuint32_t HSELB:4;
                vuint32_t ZSELB:4;
                vuint32_t HSELA:4;
                vuint32_t ZSELA:4;
            } B;
        } DECFIL1;
        
        union {                 /* DecFilter Integrator Control */
            vuint32_t R;
            struct {
                vuint32_t HSELH:4;
                vuint32_t ZSELH:4;
                vuint32_t HSELG:4;
                vuint32_t ZSELG:4;
                vuint32_t HSELF:4;
                vuint32_t ZSELF:4;
                vuint32_t HSELE:4;
                vuint32_t ZSELE:4;
            } B;
        } DECFIL2;
        
        union {                 /* DecFilter Integrator Control */
            vuint32_t R;
            struct {
                vuint32_t HSELL:4;
                vuint32_t ZSELL:4;
                vuint32_t HSELK:4;
                vuint32_t ZSELK:4;
                vuint32_t HSELJ:4;
                vuint32_t ZSELJ:4;
                vuint32_t HSELI:4;
                vuint32_t ZSELI:4;
            } B;
        } DECFIL3;
        
        union {                 /* DecFilter Triggered Output Source Select */
            vuint32_t R;
            struct {
                vuint32_t TRIG_SRCH:4;
                vuint32_t TRIG_SRCG:4;
                vuint32_t TRIG_SRCF:4;
                vuint32_t TRIG_SRCE:4;
                vuint32_t TRIG_SRCD:4;
                vuint32_t TRIG_SRCC:4;
                vuint32_t TRIG_SRCB:4;
                vuint32_t TRIG_SRCA:4;
            } B;
        } DECFIL4;
        
        union {                 /* DecFilter Triggered Output Source Select */
            vuint32_t R;
            struct {
                vuint32_t TRIG_SRCL:4;
                vuint32_t TRIG_SRCK:4;
                vuint32_t TRIG_SRCJ:4;
                vuint32_t TRIG_SRCI:4;
                vuint32_t:16;
            } B;
        } DECFIL5;
        
        int32_t SIU_reserved093C;   /* 0x093C-0x093F */
        
        union {                 /* Sigma-Delta Gate Selection Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t SD_D_GATE_SEL:4;
                vuint32_t SD_C_GATE_SEL:4;
                vuint32_t SD_B_GATE_SEL:4;
                vuint32_t SD_A_GATE_SEL:4;
            } B;
        } SDGATE_SEL;
        
        union {                 /* Sigma-Delta to eTPU_A Connection Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t CH1:1;
                vuint32_t CH2:1;
                vuint32_t:1;
                vuint32_t CH4:1;
                vuint32_t CH5:1;
                vuint32_t CH6:1;
                vuint32_t CH7:1;
                vuint32_t:1;
                vuint32_t CH9:1;
                vuint32_t CH10:1;
                vuint32_t CH11:1;
                vuint32_t CH12:1;
                vuint32_t:1;
                vuint32_t CH14:1;
                vuint32_t CH15:1;
                vuint32_t CH16:1;
                vuint32_t CH17:1;
                vuint32_t:1;
                vuint32_t CH19:1;
                vuint32_t:10;
                vuint32_t CH30:1;
                vuint32_t:1;
            } B;
        } SDETPUA;
        
        union {                 /* Sigma-Delta to eTPU_B Connection Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t CH1:1;
                vuint32_t CH2:1;
                vuint32_t:1;
                vuint32_t CH4:1;
                vuint32_t CH5:1;
                vuint32_t CH6:1;
                vuint32_t CH7:1;
                vuint32_t:1;
                vuint32_t CH9:1;
                vuint32_t CH10:1;
                vuint32_t CH11:1;
                vuint32_t CH12:1;
                vuint32_t:1;
                vuint32_t CH14:1;
                vuint32_t CH15:1;
                vuint32_t CH16:1;
                vuint32_t CH17:1;
                vuint32_t:1;
                vuint32_t CH19:1;
                vuint32_t:10;
                vuint32_t CH30:1;
                vuint32_t:1;
            } B;
        } SDETPUB;
        
        union {                 /* Sigma-Delta to eTPU_C Connection Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t:1;
                vuint32_t CH2:1;
                vuint32_t CH3:1;
                vuint32_t CH4:1;
                vuint32_t CH5:1;
                vuint32_t:1;
                vuint32_t CH7:1;
                vuint32_t CH8:1;
                vuint32_t CH9:1;
                vuint32_t CH10:1;
                vuint32_t:1;
                vuint32_t CH12:1;
                vuint32_t CH13:1;
                vuint32_t CH14:1;
                vuint32_t:10;
                vuint32_t CH25:1;
                vuint32_t:1;
                vuint32_t CH27:1;
                vuint32_t CH28:1;
                vuint32_t CH29:1;
                vuint32_t CH30:1;
                vuint32_t:1;
            } B;
        } SDETPUC;
        
        union {                 /* Trigger Burst Generator Control Registers for eQADC_A */
            vuint32_t R;
            struct {
                vuint32_t GEN:1;
                vuint32_t:3;
                vuint32_t CLKSEL:2;
                vuint32_t:2;
                vuint32_t TRIGPER:24;
            } B;
        } TBG_CR_A[6];
        
        union {                 /* Trigger Burst Generator Control Registers for eQADC_B */
            vuint32_t R;
            struct {
                vuint32_t GEN:1;
                vuint32_t:3;
                vuint32_t CLKSEL:2;
                vuint32_t:2;
                vuint32_t TRIGPER:24;
            } B;
        } TBG_CR_B[6];
        
        union {                 /* Chip Configuration Register Register */
            vuint32_t R;
            struct {
                vuint32_t:14;
                vuint32_t:1;  /* Previously MATCH field.  No longer used.  Do not write. */
                vuint32_t:1;  /* Previously DISNEX field.  No longer used.  Do not write. */
                vuint32_t:8;
                vuint32_t TESTLOCK:1;
                vuint32_t:7;
            } B;
        } CCR;
        
        union {                 /* External Clock Configuration Register Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t ENGDIV:8;
                vuint32_t ECSS:1;
                vuint32_t:3;
                vuint32_t EBTS:1;
                vuint32_t:1;
                vuint32_t EBDF:2;
            } B;
        } ECCR;

        int32_t SIU_reserved0988[6];  /* 0x0988-0x099F */
        
        union {                 /* System Clock Register */
            vuint32_t R;
            struct {
                vuint32_t LCK:1;
                vuint32_t:2;
                vuint32_t PLL0SEL:1;
                vuint32_t:1;
                vuint32_t PLL1SEL:1;
                vuint32_t:1;
                vuint32_t PERCLKSEL:1;
                vuint32_t:2;
                vuint32_t FMPERDIV:2;
                vuint32_t:2;
                vuint32_t PERDIV:2;
                vuint32_t MCANSEL:1;
                vuint32_t:1;
                vuint32_t SYSCLKSEL:2;
                vuint32_t:3;
                vuint32_t ETPUDIV:1;
                vuint32_t:3;
                vuint32_t SYSCLKDIV:3;
                vuint32_t:1;
                vuint32_t PCSEN:1;
            } B;
        } SYSDIV;
        
        union {                 /* Halt Register */
            vuint32_t R;
            struct {
                vuint32_t CPUSTP:1;     /* Core 0 stop request (Legacy name. Refer to CORE0 in the manual) */
                vuint32_t CPU1STP:1;    /* Core 1 stop request (Legacy name. Refer to CORE1 in the manual) */
                vuint32_t:1;            /* Reserved */
                vuint32_t CSE2:1;       /* CSE2 stop request */
                vuint32_t TPUCSTP:1;    /* eTPU_C stop request (Legacy name. Refer to ETPUC in the manual) */
                vuint32_t TPUSTP:1;     /* eTPU_A and eTPU_B stop request (Legacy name. Refer to ETPUA in the manual) */
                vuint32_t NPCSTP:1;     /* Nexus stop request (Legacy name. Refer to NPC in the manual) */
                vuint32_t EBISTP:1;     /* EBI stop request (Legacy name. Refer to EBI in the manual) */
                vuint32_t EQADCB:1;     /* eQADC_B stop request */
                vuint32_t EQADCA:1;     /* eQADC_A stop request */
                vuint32_t EMIOS0:1;     /* eMIOS 0 stop request */
                vuint32_t DFILSTP:1;    /* Decimation filter stop request (Legacy name. Refer to DECFIL in the manual) */
                vuint32_t EMIOS1:1;     /* eMIOS 1 stop request */
                vuint32_t PITSTP:1;     /* PIT stop request (Legacy name. Refer to PIT in the manual) */
                vuint32_t:2;            /* Reserved */
                vuint32_t CNDSTP:1;     /* FlexCAN D stop request (Legacy name. Refer to FLEXCAND in the manual) */
                vuint32_t CNCSTP:1;     /* FlexCAN C stop request (Legacy name. Refer to FLEXCANC in the manual) */
                vuint32_t CNBSTP:1;     /* FlexCAN B stop request (Legacy name. Refer to FLEXCANB in the manual) */
                vuint32_t CNASTP:1;     /* FlexCAN A stop request (Legacy name. Refer to FLEXCANA in the manual) */
                vuint32_t SPIDSTP:1;    /* DSPI D stop request (Legacy name. Refer to DSPID in the manual) */
                vuint32_t SPICSTP:1;    /* DSPI C stop request (Legacy name. Refer to DSPIC in the manual) */
                vuint32_t SPIBSTP:1;    /* DSPI B stop request (Legacy name. Refer to DSPIB in the manual) */
                vuint32_t SPIASTP:1;    /* DSPI A stop request (Legacy name. Refer to DSPIA in the manual) */
                vuint32_t SPIESTP:1;    /* DSPI E stop request (Legacy name. Refer to DSPIE in the manual) */
                vuint32_t:1;            /* Reserved */
                vuint32_t ESCIF:1;      /* eSCI F stop request */
                vuint32_t ESCIE:1;      /* eSCI E stop request */
                vuint32_t ESCID:1;      /* eSCI D stop request */
                vuint32_t SCICSTP:1;    /* eSCI C stop request (Legacy name. Refer to ESCIC in the manual) */
                vuint32_t SCIBSTP:1;    /* eSCI B stop request (Legacy name. Refer to ESCIB in the manual) */
                vuint32_t SCIASTP:1;    /* eSCI A stop request (Legacy name. Refer to ESCIA in the manual) */
            } B;
        } HLT; /* Legacy name.  Refer to SIU_HLT1 in the manual. */
        
        union {                 /* Halt Acknowledge Register */
            vuint32_t R;
            struct {
                vuint32_t CPUACK:1;     /* Core 0 stop acknowledge (Legacy name. Refer to CORE0 in the manual) */
                vuint32_t CPU1ACK:1;    /* Core 1 stop acknowledge (Legacy name. Refer to CORE1 in the manual) */
                vuint32_t:1;            /* Reserved */
                vuint32_t CSE2:1;       /* CSE2 stop acknowledge */
                vuint32_t TPUCACK:1;    /* eTPU_C stop acknowledge (Legacy name. Refer to ETPUC in the manual) */
                vuint32_t TPUACK:1;     /* eTPU_A & eTPU_B stop acknowledge (Legacy name. Refer to ETPUA in the manual) */
                vuint32_t NPCACK:1;     /* Nexus stop acknowledge (Legacy name. Refer to NPC in the manual) */
                vuint32_t EBIACK:1;     /* EBI stop acknowledge (Legacy name. Refer to EBI in the manual) */
                vuint32_t EQADCB:1;     /* eQADC_B stop acknowledge */
                vuint32_t EQADCA:1;     /* eQADC_A stop acknowledge */
                vuint32_t EMIOS0:1;     /* eMIOS 0 stop acknowledge */
                vuint32_t DFILACK:1;    /* Decimation filter stop acknowledge (Legacy name. Refer to DECFIL in the manual) */
                vuint32_t EMIOS1:1;     /* eMIOS 1 stop acknowledge */
                vuint32_t PITACK:1;     /* PIT stop acknowledge (Legacy name. Refer to PIT in the manual) */
                vuint32_t:2;            /* Reserved */
                vuint32_t CNDACK:1;     /* FlexCAN D stop acknowledge (Legacy name. Refer to FLEXCAND in the manual) */
                vuint32_t CNCACK:1;     /* FlexCAN C stop acknowledge (Legacy name. Refer to FLEXCANC in the manual) */
                vuint32_t CNBACK:1;     /* FlexCAN B stop acknowledge (Legacy name. Refer to FLEXCANB in the manual) */
                vuint32_t CNAACK:1;     /* FlexCAN A stop acknowledge (Legacy name. Refer to FLEXCANA in the manual) */
                vuint32_t SPIDACK:1;    /* DSPI D stop acknowledge (Legacy name. Refer to DSPID in the manual) */
                vuint32_t SPICACK:1;    /* DSPI C stop acknowledge (Legacy name. Refer to DSPIC in the manual) */
                vuint32_t SPIBACK:1;    /* DSPI B stop acknowledge (Legacy name. Refer to DSPIB in the manual) */
                vuint32_t SPIAACK:1;    /* DSPI A stop acknowledge (Legacy name. Refer to DSPIA in the manual) */
                vuint32_t SPIEACK:1;    /* DSPI E stop acknowledge (Legacy name. Refer to DSPIE in the manual) */
                vuint32_t:1;            /* Reserved */
                vuint32_t ESCIF:1;      /* eSCI F stop acknowledge */
                vuint32_t ESCIE:1;      /* eSCI E stop acknowledge */
                vuint32_t ESCID:1;      /* eSCI D stop acknowledge */
                vuint32_t SCICACK:1;    /* eSCI C stop acknowledge (Legacy name. Refer to ESCIC in the manual) */
                vuint32_t SCIBACK:1;    /* eSCI B stop acknowledge (Legacy name. Refer to ESCIB in the manual) */
                vuint32_t SCIAACK:1;    /* eSCI A stop acknowledge (Legacy name. Refer to ESCIA in the manual) */
            } B;
        } HLTACK; /* Legacy name.  Refer to SIU_HLTACK1 in the manual. */

        union {                  /* Core 0 Reset Vector Register */
            vuint32_t R;
            struct {
                vuint32_t RSTVEC:30;  /* Legacy name. Refer to RSTVEC0 in the manual. */
                vuint32_t RST:1;      /* Legacy name. Refer to RST0 in the manual. */
                vuint32_t VLE:1;      /* Legacy name. Refer to VLE0 in the manual. */
            } B;
        } RSTVEC0;

        union {                  /* Core 0 Reset Vector Register */
            vuint32_t R;
            struct {
                vuint32_t RSTVEC:30;  /* Legacy name. Refer to RSTVEC0 in the manual. */
                vuint32_t RST:1;      /* Legacy name. Refer to RST0 in the manual. */
                vuint32_t VLE:1;      /* Legacy name. Refer to VLE0 in the manual. */
            } B;
        } RSTVEC1;

        /* MMU PID Control Registers */
        union {                  /* Core 0 PID Mapping Control Register */
            vuint32_t R;
            struct {
                vuint32_t EXT_PID_EN:1;
                vuint32_t EXT_PID_SYNC0:1; /* Legacy name. Refer to EXT_PID_SYNC in the manual. */
                vuint32_t:28;
                vuint32_t EXT_PID:2;
            } B;
        } EMPCR_A;   /* Legacy name. Refer to C0PID in the manual */

        union {                  /* Core 1 PID Mapping Control Register */
            vuint32_t R;
            struct {
                vuint32_t EXT_PID_EN:1;
                vuint32_t EXT_PID_SYNC0:1; /* Legacy name. Refer to EXT_PID_SYNC in the manual. */
                vuint32_t:28;
                vuint32_t EXT_PID:2;
            } B;
        } EMPCR_B;   /* Legacy name. Refer to C1PID in the manual */

        union {                 /* Halt Register 2 */
            vuint32_t R;
            struct {
                vuint32_t FEC:1;
                vuint32_t:11;
                vuint32_t SDD:1;
                vuint32_t SDC:1;
                vuint32_t SDB:1;
                vuint32_t SDA:1;
                vuint32_t SIPI:1;
                vuint32_t CRC:1;
                vuint32_t STCU:1;
                vuint32_t:3;
                vuint32_t SRX1:1;
                vuint32_t SRX0:1;
                vuint32_t:2;
                vuint32_t PSI5B:1;
                vuint32_t PSI5A:1;
                vuint32_t:2;
                vuint32_t MCANB:1;
                vuint32_t MCANA:1;
            } B;
        } HLT2;
        
        union {                 /* Halt Acknowledge Register 2 */
            vuint32_t R;
            struct {
                vuint32_t FEC:1;
                vuint32_t:11;
                vuint32_t SDD:1;
                vuint32_t SDC:1;
                vuint32_t SDB:1;
                vuint32_t SDA:1;
                vuint32_t SIPI:1;
                vuint32_t CRC:1;
                vuint32_t STCU:1;
                vuint32_t:3;
                vuint32_t SRX1:1;
                vuint32_t SRX0:1;
                vuint32_t:2;
                vuint32_t PSI5B:1;
                vuint32_t PSI5A:1;
                vuint32_t:2;
                vuint32_t MCANB:1;
                vuint32_t MCANA:1;
            } B;
        } HLTACK2;
        
        union {                 /* Sigma-Delta Clock Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t LCK:1;
                vuint32_t:24;
                vuint32_t SDDIV:7;
            } B;
        } SDCLKCFG;
        
        union {                 /* LFAST Clock Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t LCK:1;
                vuint32_t:17;
                vuint32_t LFCLKSEL:2;
                vuint32_t:5;
                vuint32_t LFDIV:7;
            } B;
        } LFCLKCFG;
        
        union {                 /* PSI5 Clock Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t LCK:1;
                vuint32_t:7;
                vuint32_t PSDIV:8;
                vuint32_t:6;
                vuint32_t PSDIV1M:10;
            } B;
        } PSCLKCFG;
        
        union {                 /* Reset Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:28;
                vuint32_t RET:4;
            } B;
        } RCR;
        
        union {                 /* Lock-Step Status Register */
            vuint32_t R;
            struct {
                vuint32_t:31;
                vuint32_t LSE:1;
            } B;
        } LOCKSTEP;
        
        union {                 /* Progressive Clock Switch Interrupt Enable Register */
            vuint32_t R;
            struct {
                vuint32_t:31;
                vuint32_t PCSE:1;
            } B;
        } PCSER;
        
        union {                 /* Progressive Clock Switch Interrupt Flag Register */
            vuint32_t R;
            struct {
                vuint32_t:31;
                vuint32_t PCSI:1;
            } B;
        } PCSIFR;
        
        union {                              /* Fast Ethernet Controller Control Register */
         vuint32_t R;
         struct {
           vuint32_t  :31;
           vuint32_t FM:1;
         } B;
       } FECCR;
      
       union {                              /* ECC Error Injection Register */
         vuint32_t R;
         struct {
           vuint32_t  :24;
           vuint32_t INVC:1;
           vuint32_t CHKINVM:7;
         } B;
       } ECCEIR;
        
        int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */
        
        union {               /* Parallel GPIO Pin Data Output Register */
            vuint32_t R;
            struct {
                vuint32_t PGPDO0:1;
                vuint32_t PGPDO1:1;
                vuint32_t PGPDO2:1;
                vuint32_t PGPDO3:1;
                vuint32_t PGPDO4:1;
                vuint32_t PGPDO5:1;
                vuint32_t PGPDO6:1;
                vuint32_t PGPDO7:1;
                vuint32_t PGPDO8:1;
                vuint32_t PGPDO9:1;
                vuint32_t PGPDO10:1;
                vuint32_t PGPDO11:1;
                vuint32_t PGPDO12:1;
                vuint32_t PGPDO13:1;
                vuint32_t PGPDO14:1;
                vuint32_t PGPDO15:1;
                vuint32_t PGPDO16:1;
                vuint32_t PGPDO17:1;
                vuint32_t PGPDO18:1;
                vuint32_t PGPDO19:1;
                vuint32_t PGPDO20:1;
                vuint32_t PGPDO21:1;
                vuint32_t PGPDO22:1;
                vuint32_t PGPDO23:1;
                vuint32_t PGPDO24:1;
                vuint32_t PGPDO25:1;
                vuint32_t PGPDO26:1;
                vuint32_t PGPDO27:1;
                vuint32_t PGPDO28:1;
                vuint32_t PGPDO29:1;
                vuint32_t PGPDO30:1;
                vuint32_t PGPDO31:1;
            } B;
        } PGPDO[16];
        
        union {               /* Parallel GPIO Pin Data Input Register */
            vuint32_t R;
            struct {
                vuint32_t PGPDI0:1;
                vuint32_t PGPDI1:1;
                vuint32_t PGPDI2:1;
                vuint32_t PGPDI3:1;
                vuint32_t PGPDI4:1;
                vuint32_t PGPDI5:1;
                vuint32_t PGPDI6:1;
                vuint32_t PGPDI7:1;
                vuint32_t PGPDI8:1;
                vuint32_t PGPDI9:1;
                vuint32_t PGPDI10:1;
                vuint32_t PGPDI11:1;
                vuint32_t PGPDI12:1;
                vuint32_t PGPDI13:1;
                vuint32_t PGPDI14:1;
                vuint32_t PGPDI15:1;
                vuint32_t PGPDI16:1;
                vuint32_t PGPDI17:1;
                vuint32_t PGPDI18:1;
                vuint32_t PGPDI19:1;
                vuint32_t PGPDI20:1;
                vuint32_t PGPDI21:1;
                vuint32_t PGPDI22:1;
                vuint32_t PGPDI23:1;
                vuint32_t PGPDI24:1;
                vuint32_t PGPDI25:1;
                vuint32_t PGPDI26:1;
                vuint32_t PGPDI27:1;
                vuint32_t PGPDI28:1;
                vuint32_t PGPDI29:1;
                vuint32_t PGPDI30:1;
                vuint32_t PGPDI31:1;
            } B;
        } PGPDI[16];
        
        union {              /* Masked Parallel GPIO Pin Data Input Register */
            vuint32_t R;
            struct {
                vuint32_t MASK0:1;
                vuint32_t MASK1:1;
                vuint32_t MASK2:1;
                vuint32_t MASK3:1;
                vuint32_t MASK4:1;
                vuint32_t MASK5:1;
                vuint32_t MASK6:1;
                vuint32_t MASK7:1;
                vuint32_t MASK8:1;
                vuint32_t MASK9:1;
                vuint32_t MASK10:1;
                vuint32_t MASK11:1;
                vuint32_t MASK12:1;
                vuint32_t MASK13:1;
                vuint32_t MASK14:1;
                vuint32_t MASK15:1;
                vuint32_t DATA0:1;
                vuint32_t DATA1:1;
                vuint32_t DATA2:1;
                vuint32_t DATA3:1;
                vuint32_t DATA4:1;
                vuint32_t DATA5:1;
                vuint32_t DATA6:1;
                vuint32_t DATA7:1;
                vuint32_t DATA8:1;
                vuint32_t DATA9:1;
                vuint32_t DATA10:1;
                vuint32_t DATA11:1;
                vuint32_t DATA12:1;
                vuint32_t DATA13:1;
                vuint32_t DATA14:1;
                vuint32_t DATA15:1;
            } B;
        } MPGPDO[32];
        
        union {              /* DSPI_A Mask Output High Register */
            vuint32_t R;
            struct {
                vuint32_t MASK0:1;
                vuint32_t MASK1:1;
                vuint32_t MASK2:1;
                vuint32_t MASK3:1;
                vuint32_t MASK4:1;
                vuint32_t MASK5:1;
                vuint32_t MASK6:1;
                vuint32_t MASK7:1;
                vuint32_t MASK8:1;
                vuint32_t MASK9:1;
                vuint32_t MASK10:1;
                vuint32_t MASK11:1;
                vuint32_t MASK12:1;
                vuint32_t MASK13:1;
                vuint32_t MASK14:1;
                vuint32_t MASK15:1;
                vuint32_t DATA0:1;
                vuint32_t DATA1:1;
                vuint32_t DATA2:1;
                vuint32_t DATA3:1;
                vuint32_t DATA4:1;
                vuint32_t DATA5:1;
                vuint32_t DATA6:1;
                vuint32_t DATA7:1;
                vuint32_t DATA8:1;
                vuint32_t DATA9:1;
                vuint32_t DATA10:1;
                vuint32_t DATA11:1;
                vuint32_t DATA12:1;
                vuint32_t DATA13:1;
                vuint32_t DATA14:1;
                vuint32_t DATA15:1;
            } B;
        } DSPIAH;
        
        union {              /* DSPI_A Mask Output Low Register */
            vuint32_t R;
            struct {
                vuint32_t MASK16:1;
                vuint32_t MASK17:1;
                vuint32_t MASK18:1;
                vuint32_t MASK19:1;
                vuint32_t MASK20:1;
                vuint32_t MASK21:1;
                vuint32_t MASK22:1;
                vuint32_t MASK23:1;
                vuint32_t MASK24:1;
                vuint32_t MASK25:1;
                vuint32_t MASK26:1;
                vuint32_t MASK27:1;
                vuint32_t MASK28:1;
                vuint32_t MASK29:1;
                vuint32_t MASK30:1;
                vuint32_t MASK31:1;
                vuint32_t DATA16:1;
                vuint32_t DATA17:1;
                vuint32_t DATA18:1;
                vuint32_t DATA19:1;
                vuint32_t DATA20:1;
                vuint32_t DATA21:1;
                vuint32_t DATA22:1;
                vuint32_t DATA23:1;
                vuint32_t DATA24:1;
                vuint32_t DATA25:1;
                vuint32_t DATA26:1;
                vuint32_t DATA27:1;
                vuint32_t DATA28:1;
                vuint32_t DATA29:1;
                vuint32_t DATA30:1;
                vuint32_t DATA31:1;
            } B;
        } DSPIAL;
        
        union {              /* DSPI_B Mask Output High Register */
            vuint32_t R;
            struct {
                vuint32_t MASK0:1;
                vuint32_t MASK1:1;
                vuint32_t MASK2:1;
                vuint32_t MASK3:1;
                vuint32_t MASK4:1;
                vuint32_t MASK5:1;
                vuint32_t MASK6:1;
                vuint32_t MASK7:1;
                vuint32_t MASK8:1;
                vuint32_t MASK9:1;
                vuint32_t MASK10:1;
                vuint32_t MASK11:1;
                vuint32_t MASK12:1;
                vuint32_t MASK13:1;
                vuint32_t MASK14:1;
                vuint32_t MASK15:1;
                vuint32_t DATA0:1;
                vuint32_t DATA1:1;
                vuint32_t DATA2:1;
                vuint32_t DATA3:1;
                vuint32_t DATA4:1;
                vuint32_t DATA5:1;
                vuint32_t DATA6:1;
                vuint32_t DATA7:1;
                vuint32_t DATA8:1;
                vuint32_t DATA9:1;
                vuint32_t DATA10:1;
                vuint32_t DATA11:1;
                vuint32_t DATA12:1;
                vuint32_t DATA13:1;
                vuint32_t DATA14:1;
                vuint32_t DATA15:1;
            } B;
        } DSPIBH;
        
        union {              /* DSPI_B Mask Output Low Register */
            vuint32_t R;
            struct {
                vuint32_t MASK16:1;
                vuint32_t MASK17:1;
                vuint32_t MASK18:1;
                vuint32_t MASK19:1;
                vuint32_t MASK20:1;
                vuint32_t MASK21:1;
                vuint32_t MASK22:1;
                vuint32_t MASK23:1;
                vuint32_t MASK24:1;
                vuint32_t MASK25:1;
                vuint32_t MASK26:1;
                vuint32_t MASK27:1;
                vuint32_t MASK28:1;
                vuint32_t MASK29:1;
                vuint32_t MASK30:1;
                vuint32_t MASK31:1;
                vuint32_t DATA16:1;
                vuint32_t DATA17:1;
                vuint32_t DATA18:1;
                vuint32_t DATA19:1;
                vuint32_t DATA20:1;
                vuint32_t DATA21:1;
                vuint32_t DATA22:1;
                vuint32_t DATA23:1;
                vuint32_t DATA24:1;
                vuint32_t DATA25:1;
                vuint32_t DATA26:1;
                vuint32_t DATA27:1;
                vuint32_t DATA28:1;
                vuint32_t DATA29:1;
                vuint32_t DATA30:1;
                vuint32_t DATA31:1;
            } B;
        } DSPIBL;
        
        union {              /* DSPI_C Mask Output High Register */
            vuint32_t R;
            struct {
                vuint32_t MASK0:1;
                vuint32_t MASK1:1;
                vuint32_t MASK2:1;
                vuint32_t MASK3:1;
                vuint32_t MASK4:1;
                vuint32_t MASK5:1;
                vuint32_t MASK6:1;
                vuint32_t MASK7:1;
                vuint32_t MASK8:1;
                vuint32_t MASK9:1;
                vuint32_t MASK10:1;
                vuint32_t MASK11:1;
                vuint32_t MASK12:1;
                vuint32_t MASK13:1;
                vuint32_t MASK14:1;
                vuint32_t MASK15:1;
                vuint32_t DATA0:1;
                vuint32_t DATA1:1;
                vuint32_t DATA2:1;
                vuint32_t DATA3:1;
                vuint32_t DATA4:1;
                vuint32_t DATA5:1;
                vuint32_t DATA6:1;
                vuint32_t DATA7:1;
                vuint32_t DATA8:1;
                vuint32_t DATA9:1;
                vuint32_t DATA10:1;
                vuint32_t DATA11:1;
                vuint32_t DATA12:1;
                vuint32_t DATA13:1;
                vuint32_t DATA14:1;
                vuint32_t DATA15:1;
            } B;
        } DSPICH;
        
        union {              /* DSPI_C Mask Output Low Register */
            vuint32_t R;
            struct {
                vuint32_t MASK16:1;
                vuint32_t MASK17:1;
                vuint32_t MASK18:1;
                vuint32_t MASK19:1;
                vuint32_t MASK20:1;
                vuint32_t MASK21:1;
                vuint32_t MASK22:1;
                vuint32_t MASK23:1;
                vuint32_t MASK24:1;
                vuint32_t MASK25:1;
                vuint32_t MASK26:1;
                vuint32_t MASK27:1;
                vuint32_t MASK28:1;
                vuint32_t MASK29:1;
                vuint32_t MASK30:1;
                vuint32_t MASK31:1;
                vuint32_t DATA16:1;
                vuint32_t DATA17:1;
                vuint32_t DATA18:1;
                vuint32_t DATA19:1;
                vuint32_t DATA20:1;
                vuint32_t DATA21:1;
                vuint32_t DATA22:1;
                vuint32_t DATA23:1;
                vuint32_t DATA24:1;
                vuint32_t DATA25:1;
                vuint32_t DATA26:1;
                vuint32_t DATA27:1;
                vuint32_t DATA28:1;
                vuint32_t DATA29:1;
                vuint32_t DATA30:1;
                vuint32_t DATA31:1;
            } B;
        } DSPICL;
        
        union {              /* DSPI_D Mask Output High Register */
            vuint32_t R;
            struct {
                vuint32_t MASK0:1;
                vuint32_t MASK1:1;
                vuint32_t MASK2:1;
                vuint32_t MASK3:1;
                vuint32_t MASK4:1;
                vuint32_t MASK5:1;
                vuint32_t MASK6:1;
                vuint32_t MASK7:1;
                vuint32_t MASK8:1;
                vuint32_t MASK9:1;
                vuint32_t MASK10:1;
                vuint32_t MASK11:1;
                vuint32_t MASK12:1;
                vuint32_t MASK13:1;
                vuint32_t MASK14:1;
                vuint32_t MASK15:1;
                vuint32_t DATA0:1;
                vuint32_t DATA1:1;
                vuint32_t DATA2:1;
                vuint32_t DATA3:1;
                vuint32_t DATA4:1;
                vuint32_t DATA5:1;
                vuint32_t DATA6:1;
                vuint32_t DATA7:1;
                vuint32_t DATA8:1;
                vuint32_t DATA9:1;
                vuint32_t DATA10:1;
                vuint32_t DATA11:1;
                vuint32_t DATA12:1;
                vuint32_t DATA13:1;
                vuint32_t DATA14:1;
                vuint32_t DATA15:1;
            } B;
        } DSPIDH;
        
        union {              /* DSPI_D Mask Output Low Register */
            vuint32_t R;
            struct {
                vuint32_t MASK16:1;
                vuint32_t MASK17:1;
                vuint32_t MASK18:1;
                vuint32_t MASK19:1;
                vuint32_t MASK20:1;
                vuint32_t MASK21:1;
                vuint32_t MASK22:1;
                vuint32_t MASK23:1;
                vuint32_t MASK24:1;
                vuint32_t MASK25:1;
                vuint32_t MASK26:1;
                vuint32_t MASK27:1;
                vuint32_t MASK28:1;
                vuint32_t MASK29:1;
                vuint32_t MASK30:1;
                vuint32_t MASK31:1;
                vuint32_t DATA16:1;
                vuint32_t DATA17:1;
                vuint32_t DATA18:1;
                vuint32_t DATA19:1;
                vuint32_t DATA20:1;
                vuint32_t DATA21:1;
                vuint32_t DATA22:1;
                vuint32_t DATA23:1;
                vuint32_t DATA24:1;
                vuint32_t DATA25:1;
                vuint32_t DATA26:1;
                vuint32_t DATA27:1;
                vuint32_t DATA28:1;
                vuint32_t DATA29:1;
                vuint32_t DATA30:1;
                vuint32_t DATA31:1;
            } B;
        } DSPIDL;
        
        int32_t SIU_reserved0D20[8];  /* 0x0D20-0x0D3F */
        
        union {               /* ETPU B Select Register */
            vuint32_t R;
            struct {
                vuint32_t ETPUB15:1;
                vuint32_t ETPUB14:1;
                vuint32_t ETPUB13:1;
                vuint32_t ETPUB12:1;
                vuint32_t ETPUB11:1;
                vuint32_t ETPUB10:1;
                vuint32_t ETPUB9:1;
                vuint32_t ETPUB8:1;
                vuint32_t ETPUB7:1;
                vuint32_t ETPUB6:1;
                vuint32_t ETPUB5:1;
                vuint32_t ETPUB4:1;
                vuint32_t ETPUB3:1;
                vuint32_t ETPUB2:1;
                vuint32_t ETPUB1:1;
                vuint32_t ETPUB0:1;
                vuint32_t ETPUB31:1;
                vuint32_t ETPUB30:1;
                vuint32_t ETPUB29:1;
                vuint32_t ETPUB28:1;
                vuint32_t ETPUB27:1;
                vuint32_t ETPUB26:1;
                vuint32_t ETPUB25:1;
                vuint32_t ETPUB24:1;
                vuint32_t ETPUB23:1;
                vuint32_t ETPUB22:1;
                vuint32_t ETPUB21:1;
                vuint32_t ETPUB20:1;
                vuint32_t ETPUB19:1;
                vuint32_t ETPUB18:1;
                vuint32_t ETPUB17:1;
                vuint32_t ETPUB16:1;
            } B ;
        } ETPUBA;
        
        union {               /* EMIOS A Select Register */
            vuint32_t R;
            struct {
                vuint32_t EMIOS7:1;
                vuint32_t EMIOS6:1;
                vuint32_t EMIOS5:1;
                vuint32_t EMIOS4:1;
                vuint32_t EMIOS3:1;
                vuint32_t EMIOS2:1;
                vuint32_t EMIOS1:1;
                vuint32_t EMIOS0:1;
                vuint32_t EMIOS8:1;
                vuint32_t EMIOS9:1;
                vuint32_t EMIOS10:1;
                vuint32_t EMIOS11:1;
                vuint32_t EMIOS12:1;
                vuint32_t EMIOS13:1;
                vuint32_t EMIOS14:1;
                vuint32_t EMIOS15:1;
                vuint32_t EMIOS16:1;
                vuint32_t EMIOS17:1;
                vuint32_t EMIOS18:1;
                vuint32_t EMIOS19:1;
                vuint32_t EMIOS20:1;
                vuint32_t EMIOS21:1;
                vuint32_t EMIOS22:1;
                vuint32_t EMIOS23:1;
                vuint32_t EMIOS0_0:1;
                vuint32_t EMIOS1_1:1;
                vuint32_t EMIOS2_2:1;
                vuint32_t EMIOS3_3:1;
                vuint32_t EMIOS4_4:1;
                vuint32_t EMIOS5_5:1;
                vuint32_t EMIOS6_6:1;
                vuint32_t EMIOS7_7:1;
            } B;
        } EMIOSA;
        
        union {             /* DSPIAH/L Select Register for DSPI A */
            vuint32_t R;
            struct {
                vuint32_t DSPIAH0:1;
                vuint32_t DSPIAH1:1;
                vuint32_t DSPIAH2:1;
                vuint32_t DSPIAH3:1;
                vuint32_t DSPIAH4:1;
                vuint32_t DSPIAH5:1;
                vuint32_t DSPIAH6:1;
                vuint32_t DSPIAH7:1;
                vuint32_t DSPIAH8:1;
                vuint32_t DSPIAH9:1;
                vuint32_t DSPIAH10:1;
                vuint32_t DSPIAH11:1;
                vuint32_t DSPIAH12:1;
                vuint32_t DSPIAH13:1;
                vuint32_t DSPIAH14:1;
                vuint32_t DSPIAH15:1;
                vuint32_t DSPIAL16:1;
                vuint32_t DSPIAL17:1;
                vuint32_t DSPIAL18:1;
                vuint32_t DSPIAL19:1;
                vuint32_t DSPIAL20:1;
                vuint32_t DSPIAL21:1;
                vuint32_t DSPIAL22:1;
                vuint32_t DSPIAL23:1;
                vuint32_t DSPIAL24:1;
                vuint32_t DSPIAL25:1;
                vuint32_t DSPIAL26:1;
                vuint32_t DSPIAL27:1;
                vuint32_t DSPIAL28:1;
                vuint32_t DSPIAL29:1;
                vuint32_t DSPIAL30:1;
                vuint32_t DSPIAL31:1;
            } B;
        } DSPIAHLA;
        
        int32_t SIU_reserved0D4C;  /* 0x0D4C-0x0D4F */
        
        union {               /* ETPU A Select Register */
            vuint32_t R;
            struct {
                vuint32_t ETPUA23:1;
                vuint32_t ETPUA22:1;
                vuint32_t ETPUA21:1;
                vuint32_t ETPUA20:1;
                vuint32_t ETPUA19:1;
                vuint32_t ETPUA18:1;
                vuint32_t ETPUA17:1;
                vuint32_t ETPUA16:1;
                vuint32_t ETPUA29:1;
                vuint32_t ETPUA28:1;
                vuint32_t ETPUA27:1;
                vuint32_t ETPUA26:1;
                vuint32_t ETPUA25:1;
                vuint32_t ETPUA24:1;
                vuint32_t ETPUA31:1;
                vuint32_t ETPUA30:1;
                vuint32_t ETPUA12:1;
                vuint32_t ETPUA13:1;
                vuint32_t ETPUA14:1;
                vuint32_t ETPUA15:1;
                vuint32_t ETPUA0:1;
                vuint32_t ETPUA1:1;
                vuint32_t ETPUA2:1;
                vuint32_t ETPUA3:1;
                vuint32_t ETPUA4:1;
                vuint32_t ETPUA5:1;
                vuint32_t ETPUA6:1;
                vuint32_t ETPUA7:1;
                vuint32_t ETPUA8:1;
                vuint32_t ETPUA9:1;
                vuint32_t ETPUA10:1;
                vuint32_t ETPUA11:1;
            } B ;
        } ETPUAB;
        
        union {               /* EMIOS B Select Register */
            vuint32_t R;
            struct {
                vuint32_t EMIOS11:1;
                vuint32_t EMIOS10:1;
                vuint32_t EMIOS9:1;
                vuint32_t EMIOS8:1;
                vuint32_t EMIOS6:1;
                vuint32_t EMIOS5:1;
                vuint32_t EMIOS4:1;
                vuint32_t EMIOS3:1;
                vuint32_t EMIOS2:1;
                vuint32_t EMIOS1:1;
                vuint32_t EMIOS0:1;
                vuint32_t EMIOS23:1;
                vuint32_t EMIOS15:1;
                vuint32_t EMIOS14:1;
                vuint32_t EMIOS13:1;
                vuint32_t EMIOS12:1;
                vuint32_t EMIOS23_23:1;
                vuint32_t EMIOS15_15:1;
                vuint32_t EMIOS14_14:1;
                vuint32_t EMIOS13_13:1;
                vuint32_t EMIOS12_12:1;
                vuint32_t EMIOS11_11:1;
                vuint32_t EMIOS10_10:1;
                vuint32_t EMIOS9_9:1;
                vuint32_t EMIOS8_8:1;
                vuint32_t EMIOS6_6:1;
                vuint32_t EMIOS5_5:1;
                vuint32_t EMIOS4_4:1;
                vuint32_t EMIOS3_3:1;
                vuint32_t EMIOS2_2:1;
                vuint32_t EMIOS1_1:1;
                vuint32_t EMIOS0_0:1;
            } B;
        } EMIOSB;
        
        union {             /* DSPIBH/L Select Register for DSPI B */
            vuint32_t R;
            struct {
                vuint32_t DSPIBH0:1;
                vuint32_t DSPIBH1:1;
                vuint32_t DSPIBH2:1;
                vuint32_t DSPIBH3:1;
                vuint32_t DSPIBH4:1;
                vuint32_t DSPIBH5:1;
                vuint32_t DSPIBH6:1;
                vuint32_t DSPIBH7:1;
                vuint32_t DSPIBH8:1;
                vuint32_t DSPIBH9:1;
                vuint32_t DSPIBH10:1;
                vuint32_t DSPIBH11:1;
                vuint32_t DSPIBH12:1;
                vuint32_t DSPIBH13:1;
                vuint32_t DSPIBH14:1;
                vuint32_t DSPIBH15:1;
                vuint32_t DSPIBL16:1;
                vuint32_t DSPIBL17:1;
                vuint32_t DSPIBL18:1;
                vuint32_t DSPIBL19:1;
                vuint32_t DSPIBL20:1;
                vuint32_t DSPIBL21:1;
                vuint32_t DSPIBL22:1;
                vuint32_t DSPIBL23:1;
                vuint32_t DSPIBL24:1;
                vuint32_t DSPIBL25:1;
                vuint32_t DSPIBL26:1;
                vuint32_t DSPIBL27:1;
                vuint32_t DSPIBL28:1;
                vuint32_t DSPIBL29:1;
                vuint32_t DSPIBL30:1;
                vuint32_t DSPIBL31:1;
            } B;
        } DSPIBHLB;
        
        int32_t SIU_reserved0D5C;  /* 0x0D5C-0x0D5F */
        
        union {               /* ETPU A Select Register */
            vuint32_t R;
            struct {
                vuint32_t ETPUA12:1;
                vuint32_t ETPUA13:1;
                vuint32_t ETPUA14:1;
                vuint32_t ETPUA15:1;
                vuint32_t ETPUA0:1;
                vuint32_t ETPUA1:1;
                vuint32_t ETPUA2:1;
                vuint32_t ETPUA3:1;
                vuint32_t ETPUA4:1;
                vuint32_t ETPUA5:1;
                vuint32_t ETPUA6:1;
                vuint32_t ETPUA7:1;
                vuint32_t ETPUA8:1;
                vuint32_t ETPUA9:1;
                vuint32_t ETPUA10:1;
                vuint32_t ETPUA11:1;
                vuint32_t ETPUA23:1;
                vuint32_t ETPUA22:1;
                vuint32_t ETPUA21:1;
                vuint32_t ETPUA20:1;
                vuint32_t ETPUA19:1;
                vuint32_t ETPUA18:1;
                vuint32_t ETPUA17:1;
                vuint32_t ETPUA16:1;
                vuint32_t ETPUA29:1;
                vuint32_t ETPUA28:1;
                vuint32_t ETPUA27:1;
                vuint32_t ETPUA26:1;
                vuint32_t ETPUA25:1;
                vuint32_t ETPUA24:1;
                vuint32_t ETPUA31:1;
                vuint32_t ETPUA30:1;
            } B ;
        } ETPUAC;
        
        union {               /* EMIOS C Select Register */
            vuint32_t R;
            struct {
                vuint32_t EMIOS12:1;
                vuint32_t EMIOS13:1;
                vuint32_t EMIOS14:1;
                vuint32_t EMIOS15:1;
                vuint32_t EMIOS23:1;
                vuint32_t EMIOS0:1;
                vuint32_t EMIOS1:1;
                vuint32_t EMIOS2:1;
                vuint32_t EMIOS3:1;
                vuint32_t EMIOS4:1;
                vuint32_t EMIOS5:1;
                vuint32_t EMIOS6:1;
                vuint32_t EMIOS8:1;
                vuint32_t EMIOS9:1;
                vuint32_t EMIOS10:1;
                vuint32_t EMIOS11:1;
                vuint32_t EMIOS23_23:1;
                vuint32_t EMIOS22:1;
                vuint32_t EMIOS21:1;
                vuint32_t EMIOS20:1;
                vuint32_t EMIOS19:1;
                vuint32_t EMIOS18:1;
                vuint32_t EMIOS17:1;
                vuint32_t EMIOS16:1;
                vuint32_t EMIOS29:1;
                vuint32_t EMIOS28:1;
                vuint32_t EMIOS27:1;
                vuint32_t EMIOS26:1;
                vuint32_t EMIOS25:1;
                vuint32_t EMIOS24:1;
                vuint32_t EMIOS31:1;
                vuint32_t EMIOS30:1;
            } B;
        } EMIOSC;
        
        union {             /* DSPICH/L Select Register for DSPI C */
            vuint32_t R;
            struct {
                vuint32_t DSPICH0:1;
                vuint32_t DSPICH1:1;
                vuint32_t DSPICH2:1;
                vuint32_t DSPICH3:1;
                vuint32_t DSPICH4:1;
                vuint32_t DSPICH5:1;
                vuint32_t DSPICH6:1;
                vuint32_t DSPICH7:1;
                vuint32_t DSPICH8:1;
                vuint32_t DSPICH9:1;
                vuint32_t DSPICH10:1;
                vuint32_t DSPICH11:1;
                vuint32_t DSPICH12:1;
                vuint32_t DSPICH13:1;
                vuint32_t DSPICH14:1;
                vuint32_t DSPICH15:1;
                vuint32_t DSPICL16:1;
                vuint32_t DSPICL17:1;
                vuint32_t DSPICL18:1;
                vuint32_t DSPICL19:1;
                vuint32_t DSPICL20:1;
                vuint32_t DSPICL21:1;
                vuint32_t DSPICL22:1;
                vuint32_t DSPICL23:1;
                vuint32_t DSPICL24:1;
                vuint32_t DSPICL25:1;
                vuint32_t DSPICL26:1;
                vuint32_t DSPICL27:1;
                vuint32_t DSPICL28:1;
                vuint32_t DSPICL29:1;
                vuint32_t DSPICL30:1;
                vuint32_t DSPICL31:1;
            } B;
        } DSPICHLC;
        
        int32_t SIU_reserved0D6C;  /* 0x0D6C-0x0D6F */
        
        union {               /* ETPU B Select Register */
            vuint32_t R;
            struct {
                vuint32_t ETPUB21:1;
                vuint32_t ETPUB20:1;
                vuint32_t ETPUB19:1;
                vuint32_t ETPUB18:1;
                vuint32_t ETPUB17:1;
                vuint32_t ETPUB16:1;
                vuint32_t:4;
                vuint32_t ETPUB29:1;
                vuint32_t ETPUB28:1;
                vuint32_t ETPUB27:1;
                vuint32_t ETPUB26:1;
                vuint32_t ETPUB25:1;
                vuint32_t ETPUB24:1;
                vuint32_t:16;
            } B ;
        } ETPUBD;
        
        union {               /* EMIOS D Select Register */
            vuint32_t R;
            struct {
                vuint32_t:6;
                vuint32_t EMIOS11:1;
                vuint32_t EMIOS10:1;
                vuint32_t EMIOS13:1;
                vuint32_t EMIOS12:1;
                vuint32_t:22;
            } B;
        } EMIOSD;
        
        union {             /* DSPIDH/L Select Register for DSPI D */
            vuint32_t R;
        } DSPIDHLD;
        
        int32_t SIU_reserved0D7C;  /* 0x0D7C-0x0D7F */
        
        int32_t SIU_reserved0D80[32];  /* 0x0D80-0x0DFF */
        
        union {                 /* GPIO Pin Data Input Registers */
            vuint8_t R;
            struct {
                vuint8_t:7;
                vuint8_t PDI:1;
            } B;
        } GPDI0_511[512];
        
        uint32_t SIU_reserved1000[128];  /* 0x1000-0x11FF */

        union {                 /*  */
            vuint32_t R;
            struct {
                vuint32_t dummy:32;
            } B;
        } IMUX[16];
        
        uint32_t SIU_reserved1240[2928];  /* 0x1240-0x3FFF */

    };

/****************************************************************************/
/*                     MODULE : SIU_B                                       */
/****************************************************************************/

    struct SIU_B_tag {
        int32_t SIU_B_reserved0000[16];  /* 0x0000-0x003F */
        
        union {                 /* Mirrored Pad Configuration Registers */
            vuint16_t R;
            struct {
                vuint16_t:3;
                vuint16_t PA:3;
                vuint16_t OBE:1;
                vuint16_t IBE:1;
                vuint16_t DSC:2;
                vuint16_t ODE:1;
                vuint16_t HYS:1;
                vuint16_t SRC:2;
                vuint16_t WPE:1;
                vuint16_t WPS:1;
            } B;
        } PCR[512]; /* NOTE: Only PCR[240] through PCR[243] are valid. All others are reserved. Do not access. */
        
        int16_t SIU_B_reserved0440[224];  /* 0x0440-0x05FF */
        
        union {                 /* GPIO Pin Data Output Registers */
            vuint8_t R;
            struct {
                vuint8_t:7;
                vuint8_t PDO:1;
            } B;
        } GPDO[512];/* NOTE: Only GPDO[240] through GPDO[243] are valid. All others are reserved. Do not access. */
        
        union {                 /* GPIO Pin Data Input Registers */
            vuint8_t R;
            struct {
                vuint8_t:7;
                vuint8_t PDI:1;
            } B;
        } GPDI[256];/* NOTE: Only GPDI[240] through GPDI[243] are valid. All others are reserved. Do not access. */
        
        uint32_t SIU_B_reserved0900[3520];  /* 0x0900-0x3FFF */
    };

/****************************************************************************/
/*                          MODULE : EMIOS                                  */
/****************************************************************************/

    struct EMIOS_tag {
    
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MDIS:1;
                vuint32_t FRZ:1;
                vuint32_t GTBE:1;
                vuint32_t ETB:1;
                vuint32_t GPREN:1;
                vuint32_t:6;
                vuint32_t SRV:4;
                vuint32_t GPRE:8;
                vuint32_t:8;
            } B;
        } MCR;
        
        union {                  /* Global FLAG Register */
            vuint32_t R;
            struct {
                vuint32_t F31:1;
                vuint32_t F30:1;
                vuint32_t F29:1;
                vuint32_t F28:1;
                vuint32_t F27:1;
                vuint32_t F26:1;
                vuint32_t F25:1;
                vuint32_t F24:1;
                vuint32_t F23:1;
                vuint32_t F22:1;
                vuint32_t F21:1;
                vuint32_t F20:1;
                vuint32_t F19:1;
                vuint32_t F18:1;
                vuint32_t F17:1;
                vuint32_t F16:1;
                vuint32_t F15:1;
                vuint32_t F14:1;
                vuint32_t F13:1;
                vuint32_t F12:1;
                vuint32_t F11:1;
                vuint32_t F10:1;
                vuint32_t F9:1;
                vuint32_t F8:1;
                vuint32_t F7:1;
                vuint32_t F6:1;
                vuint32_t F5:1;
                vuint32_t F4:1;
                vuint32_t F3:1;
                vuint32_t F2:1;
                vuint32_t F1:1;
                vuint32_t F0:1;
            } B;
        } GFR;
        
        union {                 /* Output Update Disable Register */
            vuint32_t R;
            struct {
                vuint32_t OU31:1;
                vuint32_t OU30:1;
                vuint32_t OU29:1;
                vuint32_t OU28:1;
                vuint32_t OU27:1;
                vuint32_t OU26:1;
                vuint32_t OU25:1;
                vuint32_t OU24:1;
                vuint32_t OU23:1;
                vuint32_t OU22:1;
                vuint32_t OU21:1;
                vuint32_t OU20:1;
                vuint32_t OU19:1;
                vuint32_t OU18:1;
                vuint32_t OU17:1;
                vuint32_t OU16:1;
                vuint32_t OU15:1;
                vuint32_t OU14:1;
                vuint32_t OU13:1;
                vuint32_t OU12:1;
                vuint32_t OU11:1;
                vuint32_t OU10:1;
                vuint32_t OU9:1;
                vuint32_t OU8:1;
                vuint32_t OU7:1;
                vuint32_t OU6:1;
                vuint32_t OU5:1;
                vuint32_t OU4:1;
                vuint32_t OU3:1;
                vuint32_t OU2:1;
                vuint32_t OU1:1;
                vuint32_t OU0:1;
            } B;
        } OUDR;
        
        union {                  /* Disable Channel Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t CHDIS23:1;
                vuint32_t CHDIS22:1;
                vuint32_t CHDIS21:1;
                vuint32_t CHDIS20:1;
                vuint32_t CHDIS19:1;
                vuint32_t CHDIS18:1;
                vuint32_t CHDIS17:1;
                vuint32_t CHDIS16:1;
                vuint32_t CHDIS15:1;
                vuint32_t CHDIS14:1;
                vuint32_t CHDIS13:1;
                vuint32_t CHDIS12:1;
                vuint32_t CHDIS11:1;
                vuint32_t CHDIS10:1;
                vuint32_t CHDIS9:1;
                vuint32_t CHDIS8:1;
                vuint32_t CHDIS7:1;
                vuint32_t CHDIS6:1;
                vuint32_t CHDIS5:1;
                vuint32_t CHDIS4:1;
                vuint32_t CHDIS3:1;
                vuint32_t CHDIS2:1;
                vuint32_t CHDIS1:1;
                vuint32_t CHDIS0:1;
            } B;
        } UCDIS;
        
        uint32_t eMIOS_reserved0010[4]; /* 0x0010-0x001F */
        
        struct {
            union {              /* Channel A Data Register */
                vuint32_t R;
            } CADR;
            
            union {              /* Channel B Data Register */
                vuint32_t R;
            } CBDR;
            
            union {              /* Channel Counter Register */
                vuint32_t R;
            } CCNTR;
            
            union {              /* Channel Control Register */
                vuint32_t R;
                struct {
                    vuint32_t FREN:1;
                    vuint32_t ODIS:1;
                    vuint32_t ODISSL:2;
                    vuint32_t UCPRE:2;
                    vuint32_t UCPREN:1;
                    vuint32_t DMA:1;
                    vuint32_t:1;
                    vuint32_t IF:4;
                    vuint32_t FCK:1;
                    vuint32_t FEN:1;
                    vuint32_t:3;
                    vuint32_t FORCMA:1;
                    vuint32_t FORCMB:1;
                    vuint32_t:1;
                    vuint32_t BSL:2;
                    vuint32_t EDSEL:1;
                    vuint32_t EDPOL:1;
                    vuint32_t MODE:7;
                } B;
            } CCR;
            
            union {              /* Channel Status Register */
                vuint32_t R;
                struct {
                    vuint32_t OVR:1;
                    vuint32_t:15;
                    vuint32_t OVFL:1;
                    vuint32_t:12;
                    vuint32_t UCIN:1;
                    vuint32_t UCOUT:1;
                    vuint32_t FLAG:1;
                } B;
            } CSR;
            
            union {              /* Alternate Channel A Data Register */
                vuint32_t R;
            } ALTA;
            
            uint32_t eMIOS_channel_reserved0018[2];  /* 0x0018-0x001F */
            
        } CH[32];
        
        uint32_t eMIOS_reserved0420[3832];  /* 0x0420-0x3FFF */
    
    };

/****************************************************************************/
/*                          MODULE : PMC                                    */
/****************************************************************************/

struct PMC_tag {
  uint8_t PMC_reserved0[136];
  union {
    vuint32_t R;
      struct {
        vuint32_t TS_EN:1;           /* Temperature Sensor interrupts Enable */
        vuint32_t  :25;          /*  */
        vuint32_t TS1_3IE:1;           /* Temperature Sensor 1 input 3 Interrupt Enable. */
        vuint32_t TS1_2IE:1;           /* Temperature Sensor 1 input 2 Interrupt Enable. */
        vuint32_t TS1_0IE:1;           /* Temperature Sensor 1 input 0 Interrupt Enable. */
        vuint32_t TS0_3IE:1;           /* Temperature Sensor 0 input 3 Interrupt Enable. */
        vuint32_t TS0_2IE:1;           /* Temperature Sensor 0 input 2 Interrupt Enable. */
        vuint32_t TS0_0IE:1;           /* Temperature Sensor 0 input 0 Interrupt Enable. */
    } B;
  } TS_IER;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          /*  */
        vuint32_t TEMP1_3:1;           /*  */
        vuint32_t TEMP1_2:1;           /*  */
        vuint32_t TEMP1_0:1;           /*  */
        vuint32_t TEMP0_3:1;           /*  */
        vuint32_t TEMP0_2:1;           /*  */
        vuint32_t TEMP0_0:1;           /*  */
    } B;
  } ESR_TD;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          /*  */
        vuint32_t TEMP1_3:1;           /*  */
        vuint32_t TEMP1_2:1;           /*  */
        vuint32_t TEMP1_0:1;           /*  */
        vuint32_t TEMP0_3:1;           /*  */
        vuint32_t TEMP0_2:1;           /*  */
        vuint32_t TEMP0_0:1;           /*  */
    } B;
  } REE_TD;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :26;          /*  */
        vuint32_t TEMP1_3:1;           /* TEMP1_3 Reset Event Select. */
        vuint32_t TEMP1_2:1;           /* TEMP1_2 Reset Event Select. */
        vuint32_t TEMP1_0:1;           /* TEMP1_0 Reset Event Select. */
        vuint32_t TEMP0_3:1;           /* TEMP0_3 Reset Event Select. */
        vuint32_t TEMP0_2:1;           /* TEMP0_2 Reset Event Select. */
        vuint32_t TEMP0_0:1;           /* TEMP0_0 Reset Event Select. */
    } B;
  } RES_TD;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :17;          /*  */
        vuint32_t TS1_TRIM_ADJ:5;          /*  */
        vuint32_t TS1_DOUT_EN:1;           /*  */
        vuint32_t TS1_AOUT_EN:1;           /*  */
        vuint32_t  :1;           /*  */
        vuint32_t TS0_TRIM_ADJ:5;          /*  */
        vuint32_t TS0_DOUT_EN:1;           /*  */
        vuint32_t TS0_AOUT_EN:1;           /*  */
    } B;
  } CTL_TD;

  uint8_t PMC_reserved1[8];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :31;          /*  */
        vuint32_t TSNS_FAULT:1;          /* Temperature Sensor Fault injection. */
    } B;
  } TS_FIR;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;          /*  */
        vuint32_t TS1_SELTSH:1;          /* Temperature Sensor 1 Select Threshold. */
        vuint32_t TS1MODE:3;           /* Temperature Sensor 1 test Mode. */
        vuint32_t TS0_SELTSH:1;          /* Temperature Sensor 0 Select Threshold. */
        vuint32_t TS0MODE:3;           /* Temperature Sensor 0 test Mode. */
    } B;
  } TS_TMC;

  union {
    vuint32_t R;
      struct {
        vuint32_t PMC_ENABLE:1;
        vuint32_t  :22;
        vuint32_t VREG_LFAST_ENB:1;
        vuint32_t LVD_PMC:1;
        vuint32_t LVD_IO:1;
        vuint32_t HVD_FLASH:1;
        vuint32_t LVD_FLASH:1;
        vuint32_t HVD600_CORE:1;
        vuint32_t HVD_CORE:1;
        vuint32_t LVD_CORE_HOT:1;
        vuint32_t LVD_CORE_COLD:1;
    } B;
  } VD_CTRL_ENB;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :20;          /*  */
        vuint32_t STTW:12;           /*  */
    } B;
  } STTW;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :14;          /*  */
        vuint32_t ST_RESULT:1;           /*  */
        vuint32_t ST_DONE:1;           /*  */
        vuint32_t  :8;           /*  */
        vuint32_t ST_MODE:2;           /* Self Test mode bits for testing of LVDs and HVDs. */
        vuint32_t VD_ST_CTRL:6;          /*  */
    } B;
  } SELF_TEST_UM_VD_REG;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :28;          /*  */
        vuint32_t STEST_FAULT:1;           /*  */
        vuint32_t  :1;           /*  */
        vuint32_t HVD_FAULT:1;           /* High Voltage Detect Fault injection. */
        vuint32_t LVD_FAULT:1;           /* Low Voltage Detect Fault injection. */
    } B;
  } FIR;

  union {
    vuint32_t R;
      struct {
        vuint32_t PMC_ENABLE:1;
        vuint32_t  :23;
        vuint32_t LVD_PMC:1;
        vuint32_t LVD_IO:1;
        vuint32_t HVD_FLASH:1;
        vuint32_t LVD_FLASH:1;
        vuint32_t HVD600_CORE:1;
        vuint32_t HVD_CORE:1;
        vuint32_t LVD_CORE_HOT:1;
        vuint32_t LVD_CORE_COLD:1;
    } B;
  } LVD_HVD_INTR_ENB;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;
        vuint32_t LVD_PMC:1;
        vuint32_t LVD_IO:1;
        vuint32_t HVD_FLASH:1;
        vuint32_t LVD_FLASH:1;
        vuint32_t HVD600_CORE:1;
        vuint32_t HVD_CORE:1;
        vuint32_t LVD_CORE_HOT:1;
        vuint32_t LVD_CORE_COLD:1;
    } B;
  } LVD_HVD_EVENT_STATUS;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :22;          /*  */
        vuint32_t STND_BY_RAM_BO_CLR:1;          /*  */
        vuint32_t STND_BY_RAM_BR_DETCT:1;          /*  */
        vuint32_t  :2;           /*  */
        vuint32_t ADC_CS:6;          /*  */
    } B;
  } ADC_CS;

  uint8_t PMC_reserved2[4];
  union {
    vuint32_t R;
      struct {
        vuint32_t  :16;          /*  */
        vuint32_t PMC_RD_WR:16;          /*  */
    } B;
  } SMPS;

  union {
    vuint32_t R;
      struct {
        vuint32_t  :24;
        vuint32_t LVD_PMC:1;
        vuint32_t LVD_IO:1;
        vuint32_t HVD_FLASH:1;
        vuint32_t LVD_FLASH:1;
        vuint32_t HVD600_CORE:1;
        vuint32_t HVD_CORE:1;
        vuint32_t LVD_CORE_HOT:1;
        vuint32_t LVD_CORE_COLD:1;
    } B;
  } REE;

};

/****************************************************************************/
/*                              MODULE :ETPU                                */
/****************************************************************************/
/***************************Configuration Registers**************************/

    struct ETPU_tag {
        union {                 /* MODULE CONFIGURATION REGISTER */
            vuint32_t R;
            struct {
                vuint32_t GEC:1;        /* Global Exception Clear */
                vuint32_t SDMERR:1;     /* SDM Read Error */
                vuint32_t WDTOA:1;      /* Watchdog Timeout-eTPU_A (WDTO1 in reference manual) */
                vuint32_t WDTOB:1;      /* Watchdog Timeout-eTPU_B (WDTO2 in reference manual) */
                vuint32_t MGE1:1;       /* Microcode Global Exception-ETPU_A */
                vuint32_t MGE2:1;       /* Microcode Global Exception-ETPU_B */
                vuint32_t ILF1:1;       /* Illegal Instruction Flag-ETPU_A */
                vuint32_t ILF2:1;       /* Illegal Instruction Flag-ETPU_B */
                vuint32_t:3;
                vuint32_t SCMSIZE:5;    /* Shared Code Memory size */
                vuint32_t:4;
                vuint32_t SCMMISC:1;    /* SCM MISC Complete/Clear */
                vuint32_t SCMMISF:1;    /* SCM MISC Flag */
                vuint32_t SCMMISEN:1;   /* SCM MISC Enable */
                vuint32_t:2;
                vuint32_t VIS:1;        /* SCM Visability */
                vuint32_t:5;
                vuint32_t GTBE:1;       /* Global Time Base Enable */
            } B;
        } MCR;
        
        union {                 /* COHERENT DUAL-PARAMETER CONTROL */
            vuint32_t R;
            struct {
                vuint32_t STS:1;        /* Start Status bit */
                vuint32_t CTBASE:5;     /* Channel Transfer Base */
                vuint32_t PBASE:10;     /* Parameter Buffer Base Address (PBBASE in reference manual) */
                vuint32_t PWIDTH:1;     /* Parameter Width */
                vuint32_t PARAM0:7;     /* Channel Parameter 0 */
                vuint32_t WR:1;         /* Read/Write selection */
                vuint32_t PARAM1:7;     /* Channel Parameter 1 */
            } B;
        } CDCR;
        
        uint32_t eTPU_reserved0008;  /* 0x0008-0x000B */
        
        union {                 /* MISC Compare Register */
            uint32_t R;
            struct {
                vuint32_t ETPUMISCCMP:32;   
            } B;
        } MISCCMPR;
        
        union {                 /* SCM off-range Date Register */
            uint32_t R;
            struct {
                vuint32_t ETPUSCMOFFDATA:32;   
            } B;
        } SCMOFFDATAR;
        
        union {                 /* ETPU_A Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t FEND:1;       /* Force END */
                vuint32_t MDIS:1;       /* Low power Stop */
                vuint32_t:1;
                vuint32_t STF:1;        /* Stop Flag */
                vuint32_t:4;
                vuint32_t HLTF:1;       /* Halt Mode Flag */
                vuint32_t:3;
                vuint32_t FCSS:1;       /* Filter Clock Source Select */
                vuint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
                vuint32_t CDFC:2;
                vuint32_t:1;
                vuint32_t ERBA:5;       /* Engine Relative Base Address */
                vuint32_t SPPDIS:1;     /* Schedule Priority Passing Disable */
                vuint32_t:2;
                vuint32_t ETB:5;        /* Entry Table Base */
            } B;
        } ECR_A;
        
        union {                 /* ETPU_B Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t FEND:1;       /* Force END */
                vuint32_t MDIS:1;       /* Low power Stop */
                vuint32_t:1;
                vuint32_t STF:1;        /* Stop Flag */
                vuint32_t:4;
                vuint32_t HLTF:1;       /* Halt Mode Flag */
                vuint32_t:3;
                vuint32_t FCSS:1;       /* Filter Clock Source Select */
                vuint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
                vuint32_t CDFC:2;
                vuint32_t:1;
                vuint32_t ERBA:5;       /* Engine Relative Base Address */
                vuint32_t SPPDIS:1;     /* Schedule Priority Passing Disable */
                vuint32_t:2;
                vuint32_t ETB:5;        /* Entry Table Base */
            } B;
        } ECR_B;
        
        uint32_t eTPU_reserved001C;  /* 0x001C-0x001F */
        
        union {                 /* ETPU_A Timebase Configuration Register */
            uint32_t R;
            struct {
                vuint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
                vuint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
                vuint32_t AM:2;          /* Angle Mode */
                vuint32_t:3;
                vuint32_t TCR2P:6;       /* TCR2 Prescaler Control */
                vuint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
                vuint32_t TCR1CS:1;      /* TCR1 Clock Source */ 
                vuint32_t:5;
                vuint32_t TCR1P:8;       /* TCR1 Prescaler Control */
            } B;
        } TBCR_A;

        union {                 /* ETPU_A TCR1 Visibility Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t TCR1:24;
            } B;
        } TB1R_A;
        
        union {                 /* ETPU_A TCR2 Visibility Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t TCR2:24;
            } B;
        } TB2R_A;
        
        union {                 /* ETPU_A STAC Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t REN1:1;       /* Resource Enable TCR1 */
                vuint32_t RSC1:1;       /* Resource Control TCR1 */
                vuint32_t:2;
                vuint32_t SERVER_ID1:4;   /* TCR1 Server ID */
                vuint32_t:4;
                vuint32_t SRV1:4;       /* Resource Server Slot */
                vuint32_t REN2:1;       /* Resource Enable TCR2 */
                vuint32_t RSC2:1;       /* Resource Control TCR2 */
                vuint32_t:2;
                vuint32_t SERVER_ID2:4;   /* TCR2 Server ID */
                vuint32_t:4;
                vuint32_t SRV2:4;       /* Resource Server Slot */
            } B;
        } REDCR_A;
        
        uint32_t eTPU_reserved0030[4];  /* 0x0030-0x003F */
        
        union {                 /* ETPU_B Timebase Configuration Register */
            uint32_t R;
            struct {
                vuint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
                vuint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
                vuint32_t AM:2;          /* Angle Mode */
                vuint32_t:3;
                vuint32_t TCR2P:6;       /* TCR2 Prescaler Control */
                vuint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
                vuint32_t TCR1CS:1;      /* TCR1 Clock Source */ 
                vuint32_t:5;
                vuint32_t TCR1P:8;       /* TCR1 Prescaler Control */
            } B;
        } TBCR_B;
        
        union {                 /* ETPU_B TCR1 Visibility Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t TCR1:24;
            } B;
        } TB1R_B;
        
        union {                 /* ETPU_B TCR2 Visibility Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t TCR2:24;
            } B;
        } TB2R_B;
        
        union {                 /* ETPU_B STAC Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t REN1:1;       /* Resource Enable TCR1 */
                vuint32_t RSC1:1;       /* Resource Control TCR1 */
                vuint32_t:2;
                vuint32_t SERVER_ID1:4;   /* TCR1 Server ID */
                vuint32_t:4;
                vuint32_t SRV1:4;       /* Resource Server Slot */
                vuint32_t REN2:1;       /* Resource Enable TCR2 */
                vuint32_t RSC2:1;       /* Resource Control TCR2 */
                vuint32_t:2;
                vuint32_t SERVER_ID2:4;   /* TCR2 Server ID */
                vuint32_t:4;
                vuint32_t SRV2:4;       /* Resource Server Slot */
            } B;
        } REDCR_B;
        
        uint32_t eTPU_reserved0050[4];  /* 0x0050-0x005F */
        
        union {                 /* Watchdog Timer Register A */
            vuint32_t R;
            struct {
                vuint32_t WDM:2;          /* Watchdog Mode */
                vuint32_t:14;
                vuint32_t WDCNT:16;       /* Watchdog Count */
            } B;
        } WDTR_A;
        
        uint32_t eTPU_reserved0064;  /* 0x0064-0x0067 */
        
        union {                 /* Idle Counter Register A*/
            vuint32_t R;
            struct {
                vuint32_t IDLE_CNT:31;
                vuint32_t ICLR:1;       /* Idle Clear */
            } B;
            
        } IDLE_A;
        
        uint32_t eTPU_reserved006C;  /* 0x006C-0x006F */
        
        union {                 /* Watchdog Timer Register B */
            vuint32_t R;
            struct {
                vuint32_t WDM:2;          /* Watchdog Mode */
                vuint32_t:14;
                vuint32_t WDCNT:16;       /* Watchdog Count */
            } B;
        } WDTR_B;
        
        uint32_t eTPU_reserved0074;  /* 0x0074-0x0077 */
        
        union {                 /* Idle Counter Register B*/
            vuint32_t R;
            struct {
                vuint32_t IDLE_CNT:31;
                vuint32_t ICLR:1;       /* Idle Clear */
            } B;
        } IDLE_B;
        
        uint32_t eTPU_reserved007C;  /* 0x007C-0x007F */
        
        uint32_t eTPU_reserved0080[32];  /* 0x0080-0x00FF */

        union {                 /* Memory Error Control Register */
            vuint32_t R;
            struct {
                vuint32_t FME:1;
                vuint32_t:14;
                vuint32_t MECIE:1;
                vuint32_t HDEIE:1;
                vuint32_t MDEIE:1;
                vuint32_t:3;
                vuint32_t DTEND:1;
                vuint32_t DRDIS:1;
                vuint32_t DEDD:1;
                vuint32_t CEIE:1;
                vuint32_t:4;
                vuint32_t CTEND:1;
                vuint32_t CRDIS:1;
                vuint32_t CEDD:1;
            } B;
        } MECR;

        union {                 /* Data Error Injection Address Register */
            vuint32_t R;
            struct {
                vuint32_t:18;
                vuint32_t INJ_ADDR:12;
                vuint32_t:2;
            } B;
        } DEIAR;

        union {                 /* Data Error Injection Data Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t DFLIP:32;
            } B;
        } DEIDPR;

        union {                 /* Data Error Injection Parity Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t:3;
                vuint32_t PFLIP3:5;
                vuint32_t:3;
                vuint32_t PFLIP2:5;
                vuint32_t:3;
                vuint32_t PFLIP1:5;
                vuint32_t:3;
                vuint32_t PFLIP0:5;
            } B;
        } DEIPPR;

        union {                 /* Data Error Report Address Register */
            vuint32_t R;
            struct {
                vuint32_t ERR_ACC:2;
                vuint32_t:1;
                vuint32_t ERR_CHANNEL:5;
                vuint32_t:10;
                vuint32_t ERR_ADDR:12;
                vuint32_t:2;
            } B;
        } DERAR;

        union {                 /* Data Error Report Data Register */
            vuint32_t R;
            struct {
                vuint32_t DATA:32;
            } B;
        } DERDR;

        union {                 /* Data Error Report Syndrome Register */
            vuint32_t R;
            struct {
                vuint32_t BE3:1;
                vuint32_t:2;
                vuint32_t SYND3:5;
                vuint32_t BE2:1;
                vuint32_t:2;
                vuint32_t SYND2:5;
                vuint32_t BE1:1;
                vuint32_t:2;
                vuint32_t SYND1:5;
                vuint32_t BE0:1;
                vuint32_t:2;
                vuint32_t SYND0:5;
            } B;
        } DERSR;

        uint32_t eTPU_reserved011C;  /* 0x011C-0x011F */

        union {                 /* Memory Error Status Register */
            vuint32_t R;
            struct {
                vuint32_t DCERR:1;
                vuint32_t:6;
                vuint32_t DCOVR:1;
                vuint32_t CCERR:1;
                vuint32_t:6;
                vuint32_t CCOVR:1;
                vuint32_t DNCERR:1;
                vuint32_t:6;
                vuint32_t DNCOVR:1;
                vuint32_t CNCERR:1;
                vuint32_t:6;
                vuint32_t CNCOVR:1;
            } B;
        } MESR;

        union {                 /* Code Error Injection Address Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t INJ_ADDR:14;
                vuint32_t:2;
            } B;
        } CEIAR;

        union {                 /* Code Error Injection Data Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t DFLIP:32;
            } B;
        } CEIDPR;

        union {                 /* Code Error Injection Parity Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t:25;
                vuint32_t PFLIP:7;
            } B;
        } CEIPPR;

        union {                 /* Code Error Report Address Register */
            vuint32_t R;
            struct {
                vuint32_t ERR_ACC:2;
                vuint32_t:1;
                vuint32_t ERR_CHANNEL:5;
                vuint32_t:8;
                vuint32_t ERR_ADDR:14;
                vuint32_t:2;
            } B;
        } CERAR;

        union {                 /* Code Error Report Data Register */
            vuint32_t R;
            struct {
                vuint32_t CODE:32;
            } B;
        } CERDR;

        union {                 /* Code Error Report Syndrome Register */
            vuint32_t R;
            struct {
                vuint32_t:25;
                vuint32_t SYND:7;
            } B;
        } CERSR;

        uint32_t eTPU_reserved013C[49];  /* 0x013C-0x01FF */

/*****************************Status and Control Registers**************************/

        union {                 /* ETPU_A Channel Interrut Status */
            vuint32_t R;
            struct {
                vuint32_t CIS31:1;      /* Channel 31 Interrut Status */
                vuint32_t CIS30:1;      /* Channel 30 Interrut Status */
                vuint32_t CIS29:1;      /* Channel 29 Interrut Status */
                vuint32_t CIS28:1;      /* Channel 28 Interrut Status */
                vuint32_t CIS27:1;      /* Channel 27 Interrut Status */
                vuint32_t CIS26:1;      /* Channel 26 Interrut Status */
                vuint32_t CIS25:1;      /* Channel 25 Interrut Status */
                vuint32_t CIS24:1;      /* Channel 24 Interrut Status */
                vuint32_t CIS23:1;      /* Channel 23 Interrut Status */
                vuint32_t CIS22:1;      /* Channel 22 Interrut Status */
                vuint32_t CIS21:1;      /* Channel 21 Interrut Status */
                vuint32_t CIS20:1;      /* Channel 20 Interrut Status */
                vuint32_t CIS19:1;      /* Channel 19 Interrut Status */
                vuint32_t CIS18:1;      /* Channel 18 Interrut Status */
                vuint32_t CIS17:1;      /* Channel 17 Interrut Status */
                vuint32_t CIS16:1;      /* Channel 16 Interrut Status */
                vuint32_t CIS15:1;      /* Channel 15 Interrut Status */
                vuint32_t CIS14:1;      /* Channel 14 Interrut Status */
                vuint32_t CIS13:1;      /* Channel 13 Interrut Status */
                vuint32_t CIS12:1;      /* Channel 12 Interrut Status */
                vuint32_t CIS11:1;      /* Channel 11 Interrut Status */
                vuint32_t CIS10:1;      /* Channel 10 Interrut Status */
                vuint32_t CIS9:1;       /* Channel 9 Interrut Status */
                vuint32_t CIS8:1;       /* Channel 8 Interrut Status */
                vuint32_t CIS7:1;       /* Channel 7 Interrut Status */
                vuint32_t CIS6:1;       /* Channel 6 Interrut Status */
                vuint32_t CIS5:1;       /* Channel 5 Interrut Status */
                vuint32_t CIS4:1;       /* Channel 4 Interrut Status */
                vuint32_t CIS3:1;       /* Channel 3 Interrut Status */
                vuint32_t CIS2:1;       /* Channel 2 Interrut Status */
                vuint32_t CIS1:1;       /* Channel 1 Interrut Status */
                vuint32_t CIS0:1;       /* Channel 0 Interrut Status */
            } B;
        } CISR_A;
        
        union {                 /* ETPU_B Channel Interruput Status */
            vuint32_t R;
            struct {
                vuint32_t CIS31:1;      /* Channel 31 Interrut Status */
                vuint32_t CIS30:1;      /* Channel 30 Interrut Status */
                vuint32_t CIS29:1;      /* Channel 29 Interrut Status */
                vuint32_t CIS28:1;      /* Channel 28 Interrut Status */
                vuint32_t CIS27:1;      /* Channel 27 Interrut Status */
                vuint32_t CIS26:1;      /* Channel 26 Interrut Status */
                vuint32_t CIS25:1;      /* Channel 25 Interrut Status */
                vuint32_t CIS24:1;      /* Channel 24 Interrut Status */
                vuint32_t CIS23:1;      /* Channel 23 Interrut Status */
                vuint32_t CIS22:1;      /* Channel 22 Interrut Status */
                vuint32_t CIS21:1;      /* Channel 21 Interrut Status */
                vuint32_t CIS20:1;      /* Channel 20 Interrut Status */
                vuint32_t CIS19:1;      /* Channel 19 Interrut Status */
                vuint32_t CIS18:1;      /* Channel 18 Interrut Status */
                vuint32_t CIS17:1;      /* Channel 17 Interrut Status */
                vuint32_t CIS16:1;      /* Channel 16 Interrut Status */
                vuint32_t CIS15:1;      /* Channel 15 Interrut Status */
                vuint32_t CIS14:1;      /* Channel 14 Interrut Status */
                vuint32_t CIS13:1;      /* Channel 13 Interrut Status */
                vuint32_t CIS12:1;      /* Channel 12 Interrut Status */
                vuint32_t CIS11:1;      /* Channel 11 Interrut Status */
                vuint32_t CIS10:1;      /* Channel 10 Interrut Status */
                vuint32_t CIS9:1;       /* Channel 9 Interrut Status */
                vuint32_t CIS8:1;       /* Channel 8 Interrut Status */
                vuint32_t CIS7:1;       /* Channel 7 Interrut Status */
                vuint32_t CIS6:1;       /* Channel 6 Interrut Status */
                vuint32_t CIS5:1;       /* Channel 5 Interrut Status */
                vuint32_t CIS4:1;       /* Channel 4 Interrut Status */
                vuint32_t CIS3:1;       /* Channel 3 Interrut Status */
                vuint32_t CIS2:1;       /* Channel 2 Interrut Status */
                vuint32_t CIS1:1;       /* Channel 1 Interrupt Status */
                vuint32_t CIS0:1;       /* Channel 0 Interrupt Status */
            } B;
        } CISR_B;
        
        uint32_t eTPU_reserved0208[2];  /* 0x0208-0x020F */
        
        union {                 /* ETPU_A Data Transfer Request Status */
            vuint32_t R;
            struct {
                vuint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
                vuint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
                vuint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
                vuint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
                vuint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
                vuint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
                vuint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
                vuint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
                vuint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
                vuint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
                vuint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
                vuint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
                vuint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
                vuint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
                vuint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
                vuint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
                vuint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
                vuint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
                vuint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
                vuint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
                vuint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
                vuint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
                vuint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
                vuint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
                vuint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
                vuint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
                vuint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
                vuint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
                vuint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
                vuint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
                vuint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
                vuint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
            } B;
        } CDTRSR_A;
        
        union {                 /* ETPU_B Data Transfer Request Status */
            vuint32_t R;
            struct {
                vuint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
                vuint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
                vuint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
                vuint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
                vuint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
                vuint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
                vuint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
                vuint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
                vuint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
                vuint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
                vuint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
                vuint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
                vuint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
                vuint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
                vuint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
                vuint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
                vuint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
                vuint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
                vuint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
                vuint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
                vuint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
                vuint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
                vuint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
                vuint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
                vuint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
                vuint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
                vuint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
                vuint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
                vuint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
                vuint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
                vuint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
                vuint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
            } B;
        } CDTRSR_B;
        
        uint32_t eTPU_reserved0218[2];  /* 0x0218-0x021F */
        
        union {                 /* ETPU_A Interruput Overflow Status */
            vuint32_t R;
            struct {
                vuint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
                vuint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
                vuint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
                vuint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
                vuint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
                vuint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
                vuint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
                vuint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
                vuint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
                vuint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
                vuint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
                vuint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
                vuint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
                vuint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
                vuint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
                vuint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
                vuint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
                vuint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
                vuint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
                vuint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
                vuint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
                vuint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
                vuint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
                vuint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
                vuint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
                vuint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
                vuint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
                vuint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
                vuint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
                vuint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
                vuint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
                vuint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
            } B;
        } CIOSR_A;
        
        union {                 /* ETPU_B Interruput Overflow Status */
            vuint32_t R;
            struct {
                vuint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
                vuint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
                vuint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
                vuint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
                vuint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
                vuint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
                vuint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
                vuint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
                vuint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
                vuint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
                vuint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
                vuint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
                vuint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
                vuint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
                vuint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
                vuint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
                vuint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
                vuint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
                vuint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
                vuint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
                vuint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
                vuint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
                vuint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
                vuint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
                vuint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
                vuint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
                vuint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
                vuint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
                vuint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
                vuint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
                vuint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
                vuint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
            } B;
        } CIOSR_B;
        
        uint32_t eTPU_reserved0228[2];  /* 0x0228-0x022F */
        
        union {                 /* ETPU_A Data Transfer Overflow Status */
            vuint32_t R;
            struct {
                vuint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
                vuint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
                vuint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
                vuint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
                vuint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
                vuint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
                vuint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
                vuint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
                vuint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
                vuint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
                vuint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
                vuint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
                vuint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
                vuint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
                vuint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
                vuint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
                vuint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
                vuint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
                vuint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
                vuint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
                vuint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
                vuint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
                vuint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
                vuint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
                vuint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
                vuint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
                vuint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
                vuint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
                vuint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
                vuint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
                vuint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
                vuint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
            } B;
        } CDTROSR_A;
        
        union {                 /* ETPU_B Data Transfer Overflow Status */
            vuint32_t R;
            struct {
                vuint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
                vuint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
                vuint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
                vuint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
                vuint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
                vuint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
                vuint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
                vuint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
                vuint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
                vuint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
                vuint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
                vuint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
                vuint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
                vuint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
                vuint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
                vuint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
                vuint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
                vuint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
                vuint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
                vuint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
                vuint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
                vuint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
                vuint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
                vuint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
                vuint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
                vuint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
                vuint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
                vuint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
                vuint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
                vuint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
                vuint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
                vuint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
            } B;
        } CDTROSR_B;
        
        uint32_t eTPU_reserved0238[2];  /* 0x0238-0x023F */
        
        union {                 /* ETPU_A Channel Interruput Enable */
            vuint32_t R;
            struct {
                vuint32_t CIE31:1;      /* Channel 31 Interruput Enable */
                vuint32_t CIE30:1;      /* Channel 30 Interruput Enable */
                vuint32_t CIE29:1;      /* Channel 29 Interruput Enable */
                vuint32_t CIE28:1;      /* Channel 28 Interruput Enable */
                vuint32_t CIE27:1;      /* Channel 27 Interruput Enable */
                vuint32_t CIE26:1;      /* Channel 26 Interruput Enable */
                vuint32_t CIE25:1;      /* Channel 25 Interruput Enable */
                vuint32_t CIE24:1;      /* Channel 24 Interruput Enable */
                vuint32_t CIE23:1;      /* Channel 23 Interruput Enable */
                vuint32_t CIE22:1;      /* Channel 22 Interruput Enable */
                vuint32_t CIE21:1;      /* Channel 21 Interruput Enable */
                vuint32_t CIE20:1;      /* Channel 20 Interruput Enable */
                vuint32_t CIE19:1;      /* Channel 19 Interruput Enable */
                vuint32_t CIE18:1;      /* Channel 18 Interruput Enable */
                vuint32_t CIE17:1;      /* Channel 17 Interruput Enable */
                vuint32_t CIE16:1;      /* Channel 16 Interruput Enable */
                vuint32_t CIE15:1;      /* Channel 15 Interruput Enable */
                vuint32_t CIE14:1;      /* Channel 14 Interruput Enable */
                vuint32_t CIE13:1;      /* Channel 13 Interruput Enable */
                vuint32_t CIE12:1;      /* Channel 12 Interruput Enable */
                vuint32_t CIE11:1;      /* Channel 11 Interruput Enable */
                vuint32_t CIE10:1;      /* Channel 10 Interruput Enable */
                vuint32_t CIE9:1;       /* Channel 9 Interruput Enable */
                vuint32_t CIE8:1;       /* Channel 8 Interruput Enable */
                vuint32_t CIE7:1;       /* Channel 7 Interruput Enable */
                vuint32_t CIE6:1;       /* Channel 6 Interruput Enable */
                vuint32_t CIE5:1;       /* Channel 5 Interruput Enable */
                vuint32_t CIE4:1;       /* Channel 4 Interruput Enable */
                vuint32_t CIE3:1;       /* Channel 3 Interruput Enable */
                vuint32_t CIE2:1;       /* Channel 2 Interruput Enable */
                vuint32_t CIE1:1;       /* Channel 1 Interruput Enable */
                vuint32_t CIE0:1;       /* Channel 0 Interruput Enable */
            } B;
        } CIER_A;
        
        union {                 /* ETPU_B Channel Interruput Enable */
            vuint32_t R;
            struct {
                vuint32_t CIE31:1;      /* Channel 31 Interruput Enable */
                vuint32_t CIE30:1;      /* Channel 30 Interruput Enable */
                vuint32_t CIE29:1;      /* Channel 29 Interruput Enable */
                vuint32_t CIE28:1;      /* Channel 28 Interruput Enable */
                vuint32_t CIE27:1;      /* Channel 27 Interruput Enable */
                vuint32_t CIE26:1;      /* Channel 26 Interruput Enable */
                vuint32_t CIE25:1;      /* Channel 25 Interruput Enable */
                vuint32_t CIE24:1;      /* Channel 24 Interruput Enable */
                vuint32_t CIE23:1;      /* Channel 23 Interruput Enable */
                vuint32_t CIE22:1;      /* Channel 22 Interruput Enable */
                vuint32_t CIE21:1;      /* Channel 21 Interruput Enable */
                vuint32_t CIE20:1;      /* Channel 20 Interruput Enable */
                vuint32_t CIE19:1;      /* Channel 19 Interruput Enable */
                vuint32_t CIE18:1;      /* Channel 18 Interruput Enable */
                vuint32_t CIE17:1;      /* Channel 17 Interruput Enable */
                vuint32_t CIE16:1;      /* Channel 16 Interruput Enable */
                vuint32_t CIE15:1;      /* Channel 15 Interruput Enable */
                vuint32_t CIE14:1;      /* Channel 14 Interruput Enable */
                vuint32_t CIE13:1;      /* Channel 13 Interruput Enable */
                vuint32_t CIE12:1;      /* Channel 12 Interruput Enable */
                vuint32_t CIE11:1;      /* Channel 11 Interruput Enable */
                vuint32_t CIE10:1;      /* Channel 10 Interruput Enable */
                vuint32_t CIE9:1;       /* Channel 9 Interruput Enable */
                vuint32_t CIE8:1;       /* Channel 8 Interruput Enable */
                vuint32_t CIE7:1;       /* Channel 7 Interruput Enable */
                vuint32_t CIE6:1;       /* Channel 6 Interruput Enable */
                vuint32_t CIE5:1;       /* Channel 5 Interruput Enable */
                vuint32_t CIE4:1;       /* Channel 4 Interruput Enable */
                vuint32_t CIE3:1;       /* Channel 3 Interruput Enable */
                vuint32_t CIE2:1;       /* Channel 2 Interruput Enable */
                vuint32_t CIE1:1;       /* Channel 1 Interruput Enable */
                vuint32_t CIE0:1;       /* Channel 0 Interruput Enable */
            } B;
        } CIER_B;
        
        uint32_t eTPU_reserved0248[2];  /* 0x0248-0x024F */
        
        union {                 /* ETPU_A Channel Data Transfer Request Enable */
            vuint32_t R;
            struct {
                vuint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
                vuint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
                vuint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
                vuint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
                vuint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
                vuint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
                vuint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
                vuint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
                vuint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
                vuint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
                vuint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
                vuint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
                vuint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
                vuint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
                vuint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
                vuint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
                vuint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
                vuint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
                vuint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
                vuint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
                vuint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
                vuint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
                vuint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
                vuint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
                vuint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
                vuint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
                vuint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
                vuint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
                vuint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
                vuint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
                vuint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
                vuint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
            } B;
        } CDTRER_A;
        
        union {                 /* ETPU_B Channel Data Transfer Request Enable */
            vuint32_t R;
            struct {
                vuint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
                vuint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
                vuint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
                vuint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
                vuint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
                vuint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
                vuint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
                vuint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
                vuint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
                vuint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
                vuint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
                vuint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
                vuint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
                vuint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
                vuint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
                vuint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
                vuint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
                vuint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
                vuint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
                vuint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
                vuint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
                vuint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
                vuint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
                vuint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
                vuint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
                vuint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
                vuint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
                vuint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
                vuint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
                vuint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
                vuint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
                vuint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
            } B;
        } CDTRER_B;
        
        uint32_t eTPU_reserved0258[2];  /* 0x0258-0x025F */
        
        union {                 /* Watchdog Status Register A */
            vuint32_t R;
            struct {
                vuint32_t WDS31:1;
                vuint32_t WDS30:1;
                vuint32_t WDS29:1;
                vuint32_t WDS28:1;
                vuint32_t WDS27:1;
                vuint32_t WDS26:1;
                vuint32_t WDS25:1;
                vuint32_t WDS24:1;
                vuint32_t WDS23:1;
                vuint32_t WDS22:1;
                vuint32_t WDS21:1;
                vuint32_t WDS20:1;
                vuint32_t WDS19:1;
                vuint32_t WDS18:1;
                vuint32_t WDS17:1;
                vuint32_t WDS16:1;
                vuint32_t WDS15:1;
                vuint32_t WDS14:1;
                vuint32_t WDS13:1;
                vuint32_t WDS12:1;
                vuint32_t WDS11:1;
                vuint32_t WDS10:1;
                vuint32_t WDS9:1;
                vuint32_t WDS8:1;
                vuint32_t WDS7:1;
                vuint32_t WDS6:1;
                vuint32_t WDS5:1;
                vuint32_t WDS4:1;
                vuint32_t WDS3:1;
                vuint32_t WDS2:1;
                vuint32_t WDS1:1;
                vuint32_t WDS0:1;
            } B;
        } WDSR_A;
        
        union {                 /* Watchdog Status Register B */
            vuint32_t R;
            struct {
                vuint32_t WDS31:1;
                vuint32_t WDS30:1;
                vuint32_t WDS29:1;
                vuint32_t WDS28:1;
                vuint32_t WDS27:1;
                vuint32_t WDS26:1;
                vuint32_t WDS25:1;
                vuint32_t WDS24:1;
                vuint32_t WDS23:1;
                vuint32_t WDS22:1;
                vuint32_t WDS21:1;
                vuint32_t WDS20:1;
                vuint32_t WDS19:1;
                vuint32_t WDS18:1;
                vuint32_t WDS17:1;
                vuint32_t WDS16:1;
                vuint32_t WDS15:1;
                vuint32_t WDS14:1;
                vuint32_t WDS13:1;
                vuint32_t WDS12:1;
                vuint32_t WDS11:1;
                vuint32_t WDS10:1;
                vuint32_t WDS9:1;
                vuint32_t WDS8:1;
                vuint32_t WDS7:1;
                vuint32_t WDS6:1;
                vuint32_t WDS5:1;
                vuint32_t WDS4:1;
                vuint32_t WDS3:1;
                vuint32_t WDS2:1;
                vuint32_t WDS1:1;
                vuint32_t WDS0:1;
            } B;
        } WDSR_B;
        
        uint32_t eTPU_reserved0268[6];  /* 0x0268-0x027F */
        
        union {                 /* ETPU_A Channel Pending Service Status */
            vuint32_t R;
            struct {
                vuint32_t SR31:1;       /* Channel 31 Pending Service Status */
                vuint32_t SR30:1;       /* Channel 30 Pending Service Status */
                vuint32_t SR29:1;       /* Channel 29 Pending Service Status */
                vuint32_t SR28:1;       /* Channel 28 Pending Service Status */
                vuint32_t SR27:1;       /* Channel 27 Pending Service Status */
                vuint32_t SR26:1;       /* Channel 26 Pending Service Status */
                vuint32_t SR25:1;       /* Channel 25 Pending Service Status */
                vuint32_t SR24:1;       /* Channel 24 Pending Service Status */
                vuint32_t SR23:1;       /* Channel 23 Pending Service Status */
                vuint32_t SR22:1;       /* Channel 22 Pending Service Status */
                vuint32_t SR21:1;       /* Channel 21 Pending Service Status */
                vuint32_t SR20:1;       /* Channel 20 Pending Service Status */
                vuint32_t SR19:1;       /* Channel 19 Pending Service Status */
                vuint32_t SR18:1;       /* Channel 18 Pending Service Status */
                vuint32_t SR17:1;       /* Channel 17 Pending Service Status */
                vuint32_t SR16:1;       /* Channel 16 Pending Service Status */
                vuint32_t SR15:1;       /* Channel 15 Pending Service Status */
                vuint32_t SR14:1;       /* Channel 14 Pending Service Status */
                vuint32_t SR13:1;       /* Channel 13 Pending Service Status */
                vuint32_t SR12:1;       /* Channel 12 Pending Service Status */
                vuint32_t SR11:1;       /* Channel 11 Pending Service Status */
                vuint32_t SR10:1;       /* Channel 10 Pending Service Status */
                vuint32_t SR9:1;        /* Channel 9 Pending Service Status */
                vuint32_t SR8:1;        /* Channel 8 Pending Service Status */
                vuint32_t SR7:1;        /* Channel 7 Pending Service Status */
                vuint32_t SR6:1;        /* Channel 6 Pending Service Status */
                vuint32_t SR5:1;        /* Channel 5 Pending Service Status */
                vuint32_t SR4:1;        /* Channel 4 Pending Service Status */
                vuint32_t SR3:1;        /* Channel 3 Pending Service Status */
                vuint32_t SR2:1;        /* Channel 2 Pending Service Status */
                vuint32_t SR1:1;        /* Channel 1 Pending Service Status */
                vuint32_t SR0:1;        /* Channel 0 Pending Service Status */
            } B;
        } CPSSR_A;
        
        union {                 /* ETPU_B Channel Pending Service Status */
            vuint32_t R;
            struct {
                vuint32_t SR31:1;       /* Channel 31 Pending Service Status */
                vuint32_t SR30:1;       /* Channel 30 Pending Service Status */
                vuint32_t SR29:1;       /* Channel 29 Pending Service Status */
                vuint32_t SR28:1;       /* Channel 28 Pending Service Status */
                vuint32_t SR27:1;       /* Channel 27 Pending Service Status */
                vuint32_t SR26:1;       /* Channel 26 Pending Service Status */
                vuint32_t SR25:1;       /* Channel 25 Pending Service Status */
                vuint32_t SR24:1;       /* Channel 24 Pending Service Status */
                vuint32_t SR23:1;       /* Channel 23 Pending Service Status */
                vuint32_t SR22:1;       /* Channel 22 Pending Service Status */
                vuint32_t SR21:1;       /* Channel 21 Pending Service Status */
                vuint32_t SR20:1;       /* Channel 20 Pending Service Status */
                vuint32_t SR19:1;       /* Channel 19 Pending Service Status */
                vuint32_t SR18:1;       /* Channel 18 Pending Service Status */
                vuint32_t SR17:1;       /* Channel 17 Pending Service Status */
                vuint32_t SR16:1;       /* Channel 16 Pending Service Status */
                vuint32_t SR15:1;       /* Channel 15 Pending Service Status */
                vuint32_t SR14:1;       /* Channel 14 Pending Service Status */
                vuint32_t SR13:1;       /* Channel 13 Pending Service Status */
                vuint32_t SR12:1;       /* Channel 12 Pending Service Status */
                vuint32_t SR11:1;       /* Channel 11 Pending Service Status */
                vuint32_t SR10:1;       /* Channel 10 Pending Service Status */
                vuint32_t SR9:1;        /* Channel 9 Pending Service Status */
                vuint32_t SR8:1;        /* Channel 8 Pending Service Status */
                vuint32_t SR7:1;        /* Channel 7 Pending Service Status */
                vuint32_t SR6:1;        /* Channel 6 Pending Service Status */
                vuint32_t SR5:1;        /* Channel 5 Pending Service Status */
                vuint32_t SR4:1;        /* Channel 4 Pending Service Status */
                vuint32_t SR3:1;        /* Channel 3 Pending Service Status */
                vuint32_t SR2:1;        /* Channel 2 Pending Service Status */
                vuint32_t SR1:1;        /* Channel 1 Pending Service Status */
                vuint32_t SR0:1;        /* Channel 0 Pending Service Status */
            } B;
        } CPSSR_B;
        
        uint32_t eTPU_reserved0288[2];  /* 0x0288-0x028F */
        
        union {                 /* ETPU_A Channel Service Status */
            vuint32_t R;
            struct {
                vuint32_t SS31:1;       /* Channel 31 Service Status */
                vuint32_t SS30:1;       /* Channel 30 Service Status */
                vuint32_t SS29:1;       /* Channel 29 Service Status */
                vuint32_t SS28:1;       /* Channel 28 Service Status */
                vuint32_t SS27:1;       /* Channel 27 Service Status */
                vuint32_t SS26:1;       /* Channel 26 Service Status */
                vuint32_t SS25:1;       /* Channel 25 Service Status */
                vuint32_t SS24:1;       /* Channel 24 Service Status */
                vuint32_t SS23:1;       /* Channel 23 Service Status */
                vuint32_t SS22:1;       /* Channel 22 Service Status */
                vuint32_t SS21:1;       /* Channel 21 Service Status */
                vuint32_t SS20:1;       /* Channel 20 Service Status */
                vuint32_t SS19:1;       /* Channel 19 Service Status */
                vuint32_t SS18:1;       /* Channel 18 Service Status */
                vuint32_t SS17:1;       /* Channel 17 Service Status */
                vuint32_t SS16:1;       /* Channel 16 Service Status */
                vuint32_t SS15:1;       /* Channel 15 Service Status */
                vuint32_t SS14:1;       /* Channel 14 Service Status */
                vuint32_t SS13:1;       /* Channel 13 Service Status */
                vuint32_t SS12:1;       /* Channel 12 Service Status */
                vuint32_t SS11:1;       /* Channel 11 Service Status */
                vuint32_t SS10:1;       /* Channel 10 Service Status */
                vuint32_t SS9:1;        /* Channel 9 Service Status */
                vuint32_t SS8:1;        /* Channel 8 Service Status */
                vuint32_t SS7:1;        /* Channel 7 Service Status */
                vuint32_t SS6:1;        /* Channel 6 Service Status */
                vuint32_t SS5:1;        /* Channel 5 Service Status */
                vuint32_t SS4:1;        /* Channel 4 Service Status */
                vuint32_t SS3:1;        /* Channel 3 Service Status */
                vuint32_t SS2:1;        /* Channel 2 Service Status */
                vuint32_t SS1:1;        /* Channel 1 Service Status */
                vuint32_t SS0:1;        /* Channel 0 Service Status */
            } B;
        } CSSR_A;
        
        union {                 /* ETPU_B Channel Service Status */
            vuint32_t R;
            struct {
                vuint32_t SS31:1;       /* Channel 31 Service Status */
                vuint32_t SS30:1;       /* Channel 30 Service Status */
                vuint32_t SS29:1;       /* Channel 29 Service Status */
                vuint32_t SS28:1;       /* Channel 28 Service Status */
                vuint32_t SS27:1;       /* Channel 27 Service Status */
                vuint32_t SS26:1;       /* Channel 26 Service Status */
                vuint32_t SS25:1;       /* Channel 25 Service Status */
                vuint32_t SS24:1;       /* Channel 24 Service Status */
                vuint32_t SS23:1;       /* Channel 23 Service Status */
                vuint32_t SS22:1;       /* Channel 22 Service Status */
                vuint32_t SS21:1;       /* Channel 21 Service Status */
                vuint32_t SS20:1;       /* Channel 20 Service Status */
                vuint32_t SS19:1;       /* Channel 19 Service Status */
                vuint32_t SS18:1;       /* Channel 18 Service Status */
                vuint32_t SS17:1;       /* Channel 17 Service Status */
                vuint32_t SS16:1;       /* Channel 16 Service Status */
                vuint32_t SS15:1;       /* Channel 15 Service Status */
                vuint32_t SS14:1;       /* Channel 14 Service Status */
                vuint32_t SS13:1;       /* Channel 13 Service Status */
                vuint32_t SS12:1;       /* Channel 12 Service Status */
                vuint32_t SS11:1;       /* Channel 11 Service Status */
                vuint32_t SS10:1;       /* Channel 10 Service Status */
                vuint32_t SS9:1;        /* Channel 9 Service Status */
                vuint32_t SS8:1;        /* Channel 8 Service Status */
                vuint32_t SS7:1;        /* Channel 7 Service Status */
                vuint32_t SS6:1;        /* Channel 6 Service Status */
                vuint32_t SS5:1;        /* Channel 5 Service Status */
                vuint32_t SS4:1;        /* Channel 4 Service Status */
                vuint32_t SS3:1;        /* Channel 3 Service Status */
                vuint32_t SS2:1;        /* Channel 2 Service Status */
                vuint32_t SS1:1;        /* Channel 1 Service Status */
                vuint32_t SS0:1;        /* Channel 0 Service Status */
            } B;
        } CSSR_B;
        
        uint32_t eTPU_reserved0298[2];  /* 0x0298-0x029F */
        
        uint32_t eTPU_reserved02A0[88];  /* 0x02A0-0x03FF */

/*****************************Channels********************************/

        struct {
            union {    /* Channel Configuration Register */
                vuint32_t R;
                struct {
                    vuint32_t CIE:1;    /* Channel Interruput Enable */
                    vuint32_t DTRE:1;   /* Data Transfer Request Enable */
                    vuint32_t CPR:2;    /* Channel Priority */
                    vuint32_t:2;
                    vuint32_t ETPD:1;
                    vuint32_t ETCS:1;   /* Entry Table Condition Select */
                    vuint32_t:3;
                    vuint32_t CFS:5;    /* Channel Function Select */
                    vuint32_t ODIS:1;   /* Output disable */
                    vuint32_t OPOL:1;   /* output polarity */
                    vuint32_t:3;
                    vuint32_t CPBA:11;  /* Channel Parameter Base Address */
                } B;
            } CR;
            
            union {    /* Channel Status Control Register */
                vuint32_t R;
                struct {
                    vuint32_t CIS:1;    /* Channel Interruput Status */
                    vuint32_t CIOS:1;   /* Channel Interruput Overflow Status */
                    vuint32_t:6;
                    vuint32_t DTRS:1;   /* Data Transfer Status */
                    vuint32_t DTROS:1;  /* Data Transfer Overflow Status */
                    vuint32_t:6;
                    vuint32_t IPS:1;    /* Input Pin State */
                    vuint32_t OPS:1;    /* Output Pin State */
                    vuint32_t OBE:1;    /* Output Buffer Enable */
                    vuint32_t:11;
                    vuint32_t FM1:1;    /* Function mode */
                    vuint32_t FM0:1;    /* Function mode */
                } B;
            } SCR;
            
            union {    /* Channel Host Service Request Register */
                vuint32_t R;
                struct {
                    vuint32_t:29;       /* Host Service Request */
                    vuint32_t HSR:3;
                } B;
            } HSRR;
            
            uint32_t eTPU_ch_reserved00C;  /* channel offset 0x00C-0x00F */
            
        } CHAN[127];
        
        uint32_t eTPU_reserved1000[7168];  /* 0x1000-0x7FFF */
        
    };
    
/****************************************************************************/
/*                              MODULE :ETPU_C                              */
/****************************************************************************/

/***************************Configuration Registers**************************/

    struct ETPU_C_tag {
        union {                 /* MODULE CONFIGURATION REGISTER */
            vuint32_t R;
            struct {
                vuint32_t GEC:1;        /* Global Exception Clear */
                vuint32_t SDMERR:1;     /* SDM Read Error */
                vuint32_t WDTOC:1;      /* Watchdog Timeout-eTPU_C (WDTO1 in reference manual) */
                vuint32_t:1;
                vuint32_t MGE1:1;       /* Microcode Global Exception-ETPU_C */
                vuint32_t:1;
                vuint32_t ILF1:1;       /* Illegal Instruction Flag-ETPU_C */
                vuint32_t:1;
                vuint32_t SCMERR:1;     /* SCM Read Error */
                vuint32_t:2;
                vuint32_t SCMSIZE:5;    /* Shared Code Memory size */
                vuint32_t:4;
                vuint32_t SCMMISC:1;    /* SCM MISC Complete/Clear */
                vuint32_t SCMMISF:1;    /* SCM MISC Flag */
                vuint32_t SCMMISEN:1;   /* SCM MISC Enable */
                vuint32_t:2;
                vuint32_t VIS:1;        /* SCM Visability */
                vuint32_t:5;
                vuint32_t GTBE:1;       /* Global Time Base Enable */
            } B;
        } MCR;
        
        union {                 /* COHERENT DUAL-PARAMETER CONTROL */
            vuint32_t R;
            struct {
                vuint32_t STS:1;        /* Start Status bit */
                vuint32_t CTBASE:5;     /* Channel Transfer Base */
                vuint32_t PBASE:10;     /* Parameter Buffer Base Address (PBBASE in reference manual) */
                vuint32_t PWIDTH:1;     /* Parameter Width */
                vuint32_t PARAM0:7;     /* Channel Parameter 0 */
                vuint32_t WR:1;         /* Read/Write selection */
                vuint32_t PARAM1:7;     /* Channel Parameter 1 */
            } B;
        } CDCR;
        
        uint32_t eTPU_C_reserved0008;  /* 0x0008-0x000B */
        
        union {                 /* MISC Compare Register */
            uint32_t R;
            struct {
                vuint32_t ETPUMISCCMP:32;   
            } B;
        } MISCCMPR;
        
        union {                 /* SCM off-range Date Register */
            uint32_t R;
            struct {
                vuint32_t ETPUSCMOFFDATA:32;   
            } B;
        } SCMOFFDATAR;
        
        union {                 /* ETPU_C Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t FEND:1;       /* Force END */
                vuint32_t MDIS:1;       /* Low power Stop */
                vuint32_t:1;
                vuint32_t STF:1;        /* Stop Flag */
                vuint32_t:4;
                vuint32_t HLTF:1;       /* Halt Mode Flag */
                vuint32_t:3;
                vuint32_t FCSS:1;       /* Filter Clock Source Select */
                vuint32_t FPSCK:3;      /* Filter Prescaler Clock Control */
                vuint32_t CDFC:2;
                vuint32_t:1;
                vuint32_t ERBA:5;       /* Engine Relative Base Address */
                vuint32_t SPPDIS:1;     /* Schedule Priority Passing Disable */
                vuint32_t:2;
                vuint32_t ETB:5;        /* Entry Table Base */
            } B;
        } ECR_C;
        uint32_t eTPU_C_reserved0018;  /* 0x0018-0x001B */

        uint32_t eTPU_C_reserved001C;  /* 0x001C-0x001F */

        union {                 /* ETPU_C Timebase Configuration Register */
            uint32_t R;
            struct {
                vuint32_t TCR2CTL:3;     /* TCR2 Clock/Gate Control */
                vuint32_t TCRCF:2;       /* TCRCLK Signal Filter Control */
                vuint32_t AM:2;          /* Angle Mode */
                vuint32_t:3;
                vuint32_t TCR2P:6;       /* TCR2 Prescaler Control */
                vuint32_t TCR1CTL:2;     /* TCR1 Clock/Gate Control */
                vuint32_t TCR1CS:1;      /* TCR1 Clock Source */ 
                vuint32_t:5;
                vuint32_t TCR1P:8;       /* TCR1 Prescaler Control */
            } B;
        } TBCR_C;

        union {                 /* ETPU_C TCR1 Visibility Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t TCR1:24;
            } B;
        } TB1R_C;
        
        union {                 /* ETPU_C TCR2 Visibility Register */
            vuint32_t R;
            struct {
                vuint32_t:8;
                vuint32_t TCR2:24;
            } B;
        } TB2R_C;
        
        union {                 /* ETPU_C STAC Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t REN1:1;       /* Resource Enable TCR1 */
                vuint32_t RSC1:1;       /* Resource Control TCR1 */
                vuint32_t:2;
                vuint32_t SERVER_ID1:4;   /* TCR1 Server ID */
                vuint32_t:4;
                vuint32_t SRV1:4;       /* Resource Server Slot */
                vuint32_t REN2:1;       /* Resource Enable TCR2 */
                vuint32_t RSC2:1;       /* Resource Control TCR2 */
                vuint32_t:2;
                vuint32_t SERVER_ID2:4;   /* TCR2 Server ID */
                vuint32_t:4;
                vuint32_t SRV2:4;       /* Resource Server Slot */
            } B;
        } REDCR_C;

        uint32_t eTPU_C_reserved0030[4];  /* 0x0030-0x003F */
        uint32_t etpu_C_reserved0040[4];  /* 0x0040-0x004F */

        uint32_t eTPU_C_reserved0050[4];  /* 0x0050-0x005F */
        
        union {                 /* Watchdog Timer Register A */
            vuint32_t R;
            struct {
                vuint32_t WDM:2;          /* Watchdog Mode */
                vuint32_t:14;
                vuint32_t WDCNT:16;       /* Watchdog Count */
            } B;
        } WDTR_C;
        
        uint32_t eTPU_C_reserved0064;  /* 0x0064-0x0067 */
        
        union {                 /* Idle Counter Register A*/
            vuint32_t R;
            struct {
                vuint32_t IDLE_CNT:31;
                vuint32_t ICLR:1;       /* Idle Clear */
            } B;
            
        } IDLE_C;
        
        uint32_t eTPU_C_reserved006C;     /* 0x006C-0x006F */
        uint32_t eTPU_C_reserved0070[4];  /* 0x0070-0x007F */
        uint32_t eTPU_C_reserved0080[32]; /* 0x0080-0x00FF */
    
        union {                 /* Error Correction Status and Control Register */
            vuint32_t R;
            struct {
                vuint32_t FME:1;
                vuint32_t:14;
                vuint32_t MECIE:1;
                vuint32_t HDEIE:1;
                vuint32_t MDEIE:1;
                vuint32_t:3;
                vuint32_t DTEND:1;
                vuint32_t DRDIS:1;
                vuint32_t DEDD:1;
                vuint32_t CEIE:1;
                vuint32_t:4;
                vuint32_t CTEND:1;
                vuint32_t CRDIS:1;
                vuint32_t CEDD:1;
            } B;
        } MECR;

        union {                 /* Data Error Injection Address Register */
            vuint32_t R;
            struct {
                vuint32_t:18;
                vuint32_t INJ_ADDR:12;
                vuint32_t:2;
            } B;
        } DEIAR;

        union {                 /* Data Error Injection Data Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t DFLIP:32;
            } B;
        } DEIDPR;

        union {                 /* Data Error Injection Parity Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t:3;
                vuint32_t PFLIP3:5;
                vuint32_t:3;
                vuint32_t PFLIP2:5;
                vuint32_t:3;
                vuint32_t PFLIP1:5;
                vuint32_t:3;
                vuint32_t PFLIP0:5;
            } B;
        } DEIPPR;

        union {                 /* Data Error Report Address Register */
            vuint32_t R;
            struct {
                vuint32_t ERR_ACC:2;
                vuint32_t:1;
                vuint32_t ERR_CHANNEL:5;
                vuint32_t:10;
                vuint32_t ERR_ADDR:12;
                vuint32_t:2;
            } B;
        } DERAR;

        union {                 /* Data Error Report Data Register */
            vuint32_t R;
            struct {
                vuint32_t DATA:32;
            } B;
        } DERDR;

        union {                 /* Data Error Report Syndrome Register */
            vuint32_t R;
            struct {
                vuint32_t BE3:1;
                vuint32_t:2;
                vuint32_t SYND3:5;
                vuint32_t BE2:1;
                vuint32_t:2;
                vuint32_t SYND2:5;
                vuint32_t BE1:1;
                vuint32_t:2;
                vuint32_t SYND1:5;
                vuint32_t BE0:1;
                vuint32_t:2;
                vuint32_t SYND0:5;
            } B;
        } DERSR;

        uint32_t eTPU_C_reserved011C;  /* 0x011C-0x011F */

        union {                 /* Memory Error Status Register */
            vuint32_t R;
            struct {
                vuint32_t DCERR:1;
                vuint32_t:6;
                vuint32_t DCOVR:1;
                vuint32_t CCERR:1;
                vuint32_t:6;
                vuint32_t CCOVR:1;
                vuint32_t DNCERR:1;
                vuint32_t:6;
                vuint32_t DNCOVR:1;
                vuint32_t CNCERR:1;
                vuint32_t:6;
                vuint32_t CNCOVR:1;
            } B;
        } MESR;

        union {                 /* Code Error Injection Address Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t INJ_ADDR:14;
                vuint32_t:2;
            } B;
        } CEIAR;

        union {                 /* Code Error Injection Data Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t DFLIP:32;
            } B;
        } CEIDPR;

        union {                 /* Code Error Injection Parity Pattern Register */
            vuint32_t R;
            struct {
                vuint32_t:25;
                vuint32_t PFLIP:7;
            } B;
        } CEIPPR;

        union {                 /* Code Error Report Address Register */
            vuint32_t R;
            struct {
                vuint32_t ERR_ACC:2;
                vuint32_t:1;
                vuint32_t ERR_CHANNEL:5;
                vuint32_t:8;
                vuint32_t ERR_ADDR:14;
                vuint32_t:2;
            } B;
        } CERAR;

        union {                 /* Code Error Report Data Register */
            vuint32_t R;
            struct {
                vuint32_t CODE:32;
            } B;
        } CERDR;

        union {                 /* Code Error Report Syndrome Register */
            vuint32_t R;
            struct {
                vuint32_t:25;
                vuint32_t SYND:7;
            } B;
        } CERSR;

        uint32_t eTPU_C_reserved013C[49];  /* 0x013C-0x01FF */

/*****************************Status and Control Registers**************************/

        union {                 /* ETPU_C Channel Interrut Status */
            vuint32_t R;
            struct {
                vuint32_t CIS31:1;      /* Channel 31 Interrut Status */
                vuint32_t CIS30:1;      /* Channel 30 Interrut Status */
                vuint32_t CIS29:1;      /* Channel 29 Interrut Status */
                vuint32_t CIS28:1;      /* Channel 28 Interrut Status */
                vuint32_t CIS27:1;      /* Channel 27 Interrut Status */
                vuint32_t CIS26:1;      /* Channel 26 Interrut Status */
                vuint32_t CIS25:1;      /* Channel 25 Interrut Status */
                vuint32_t CIS24:1;      /* Channel 24 Interrut Status */
                vuint32_t CIS23:1;      /* Channel 23 Interrut Status */
                vuint32_t CIS22:1;      /* Channel 22 Interrut Status */
                vuint32_t CIS21:1;      /* Channel 21 Interrut Status */
                vuint32_t CIS20:1;      /* Channel 20 Interrut Status */
                vuint32_t CIS19:1;      /* Channel 19 Interrut Status */
                vuint32_t CIS18:1;      /* Channel 18 Interrut Status */
                vuint32_t CIS17:1;      /* Channel 17 Interrut Status */
                vuint32_t CIS16:1;      /* Channel 16 Interrut Status */
                vuint32_t CIS15:1;      /* Channel 15 Interrut Status */
                vuint32_t CIS14:1;      /* Channel 14 Interrut Status */
                vuint32_t CIS13:1;      /* Channel 13 Interrut Status */
                vuint32_t CIS12:1;      /* Channel 12 Interrut Status */
                vuint32_t CIS11:1;      /* Channel 11 Interrut Status */
                vuint32_t CIS10:1;      /* Channel 10 Interrut Status */
                vuint32_t CIS9:1;       /* Channel 9 Interrut Status */
                vuint32_t CIS8:1;       /* Channel 8 Interrut Status */
                vuint32_t CIS7:1;       /* Channel 7 Interrut Status */
                vuint32_t CIS6:1;       /* Channel 6 Interrut Status */
                vuint32_t CIS5:1;       /* Channel 5 Interrut Status */
                vuint32_t CIS4:1;       /* Channel 4 Interrut Status */
                vuint32_t CIS3:1;       /* Channel 3 Interrut Status */
                vuint32_t CIS2:1;       /* Channel 2 Interrut Status */
                vuint32_t CIS1:1;       /* Channel 1 Interrut Status */
                vuint32_t CIS0:1;       /* Channel 0 Interrut Status */
            } B;
        } CISR_C;
        uint32_t eTPU_C_reserved0204;     /* 0x0204-0x0207 */

        uint32_t eTPU_C_reserved0208[2];  /* 0x0208-0x020F */
        
        union {                 /* ETPU_C Data Transfer Request Status */
            vuint32_t R;
            struct {
                vuint32_t DTRS31:1;     /* Channel 31 Data Transfer Request Status */
                vuint32_t DTRS30:1;     /* Channel 30 Data Transfer Request Status */
                vuint32_t DTRS29:1;     /* Channel 29 Data Transfer Request Status */
                vuint32_t DTRS28:1;     /* Channel 28 Data Transfer Request Status */
                vuint32_t DTRS27:1;     /* Channel 27 Data Transfer Request Status */
                vuint32_t DTRS26:1;     /* Channel 26 Data Transfer Request Status */
                vuint32_t DTRS25:1;     /* Channel 25 Data Transfer Request Status */
                vuint32_t DTRS24:1;     /* Channel 24 Data Transfer Request Status */
                vuint32_t DTRS23:1;     /* Channel 23 Data Transfer Request Status */
                vuint32_t DTRS22:1;     /* Channel 22 Data Transfer Request Status */
                vuint32_t DTRS21:1;     /* Channel 21 Data Transfer Request Status */
                vuint32_t DTRS20:1;     /* Channel 20 Data Transfer Request Status */
                vuint32_t DTRS19:1;     /* Channel 19 Data Transfer Request Status */
                vuint32_t DTRS18:1;     /* Channel 18 Data Transfer Request Status */
                vuint32_t DTRS17:1;     /* Channel 17 Data Transfer Request Status */
                vuint32_t DTRS16:1;     /* Channel 16 Data Transfer Request Status */
                vuint32_t DTRS15:1;     /* Channel 15 Data Transfer Request Status */
                vuint32_t DTRS14:1;     /* Channel 14 Data Transfer Request Status */
                vuint32_t DTRS13:1;     /* Channel 13 Data Transfer Request Status */
                vuint32_t DTRS12:1;     /* Channel 12 Data Transfer Request Status */
                vuint32_t DTRS11:1;     /* Channel 11 Data Transfer Request Status */
                vuint32_t DTRS10:1;     /* Channel 10 Data Transfer Request Status */
                vuint32_t DTRS9:1;      /* Channel 9 Data Transfer Request Status */
                vuint32_t DTRS8:1;      /* Channel 8 Data Transfer Request Status */
                vuint32_t DTRS7:1;      /* Channel 7 Data Transfer Request Status */
                vuint32_t DTRS6:1;      /* Channel 6 Data Transfer Request Status */
                vuint32_t DTRS5:1;      /* Channel 5 Data Transfer Request Status */
                vuint32_t DTRS4:1;      /* Channel 4 Data Transfer Request Status */
                vuint32_t DTRS3:1;      /* Channel 3 Data Transfer Request Status */
                vuint32_t DTRS2:1;      /* Channel 2 Data Transfer Request Status */
                vuint32_t DTRS1:1;      /* Channel 1 Data Transfer Request Status */
                vuint32_t DTRS0:1;      /* Channel 0 Data Transfer Request Status */
            } B;
        } CDTRSR_C;
        uint32_t eTPU_C_reserved0214;     /* 0x0214-0x0217 */

        uint32_t eTPU_C_reserved0218[2];  /* 0x0218-0x021F */
        
        union {                 /* ETPU_C Interruput Overflow Status */
            vuint32_t R;
            struct {
                vuint32_t CIOS31:1;     /* Channel 31 Interruput Overflow Status */
                vuint32_t CIOS30:1;     /* Channel 30 Interruput Overflow Status */
                vuint32_t CIOS29:1;     /* Channel 29 Interruput Overflow Status */
                vuint32_t CIOS28:1;     /* Channel 28 Interruput Overflow Status */
                vuint32_t CIOS27:1;     /* Channel 27 Interruput Overflow Status */
                vuint32_t CIOS26:1;     /* Channel 26 Interruput Overflow Status */
                vuint32_t CIOS25:1;     /* Channel 25 Interruput Overflow Status */
                vuint32_t CIOS24:1;     /* Channel 24 Interruput Overflow Status */
                vuint32_t CIOS23:1;     /* Channel 23 Interruput Overflow Status */
                vuint32_t CIOS22:1;     /* Channel 22 Interruput Overflow Status */
                vuint32_t CIOS21:1;     /* Channel 21 Interruput Overflow Status */
                vuint32_t CIOS20:1;     /* Channel 20 Interruput Overflow Status */
                vuint32_t CIOS19:1;     /* Channel 19 Interruput Overflow Status */
                vuint32_t CIOS18:1;     /* Channel 18 Interruput Overflow Status */
                vuint32_t CIOS17:1;     /* Channel 17 Interruput Overflow Status */
                vuint32_t CIOS16:1;     /* Channel 16 Interruput Overflow Status */
                vuint32_t CIOS15:1;     /* Channel 15 Interruput Overflow Status */
                vuint32_t CIOS14:1;     /* Channel 14 Interruput Overflow Status */
                vuint32_t CIOS13:1;     /* Channel 13 Interruput Overflow Status */
                vuint32_t CIOS12:1;     /* Channel 12 Interruput Overflow Status */
                vuint32_t CIOS11:1;     /* Channel 11 Interruput Overflow Status */
                vuint32_t CIOS10:1;     /* Channel 10 Interruput Overflow Status */
                vuint32_t CIOS9:1;      /* Channel 9 Interruput Overflow Status */
                vuint32_t CIOS8:1;      /* Channel 8 Interruput Overflow Status */
                vuint32_t CIOS7:1;      /* Channel 7 Interruput Overflow Status */
                vuint32_t CIOS6:1;      /* Channel 6 Interruput Overflow Status */
                vuint32_t CIOS5:1;      /* Channel 5 Interruput Overflow Status */
                vuint32_t CIOS4:1;      /* Channel 4 Interruput Overflow Status */
                vuint32_t CIOS3:1;      /* Channel 3 Interruput Overflow Status */
                vuint32_t CIOS2:1;      /* Channel 2 Interruput Overflow Status */
                vuint32_t CIOS1:1;      /* Channel 1 Interruput Overflow Status */
                vuint32_t CIOS0:1;      /* Channel 0 Interruput Overflow Status */
            } B;
        } CIOSR_C;
        uint32_t eTPU_C_reserved0224;     /* 0x0224-0x0227 */

        uint32_t eTPU_C_reserved0228[2];  /* 0x0228-0x022F */
        
        union {                 /* ETPU_C Data Transfer Overflow Status */
            vuint32_t R;
            struct {
                vuint32_t DTROS31:1;    /* Channel 31 Data Transfer Overflow Status */
                vuint32_t DTROS30:1;    /* Channel 30 Data Transfer Overflow Status */
                vuint32_t DTROS29:1;    /* Channel 29 Data Transfer Overflow Status */
                vuint32_t DTROS28:1;    /* Channel 28 Data Transfer Overflow Status */
                vuint32_t DTROS27:1;    /* Channel 27 Data Transfer Overflow Status */
                vuint32_t DTROS26:1;    /* Channel 26 Data Transfer Overflow Status */
                vuint32_t DTROS25:1;    /* Channel 25 Data Transfer Overflow Status */
                vuint32_t DTROS24:1;    /* Channel 24 Data Transfer Overflow Status */
                vuint32_t DTROS23:1;    /* Channel 23 Data Transfer Overflow Status */
                vuint32_t DTROS22:1;    /* Channel 22 Data Transfer Overflow Status */
                vuint32_t DTROS21:1;    /* Channel 21 Data Transfer Overflow Status */
                vuint32_t DTROS20:1;    /* Channel 20 Data Transfer Overflow Status */
                vuint32_t DTROS19:1;    /* Channel 19 Data Transfer Overflow Status */
                vuint32_t DTROS18:1;    /* Channel 18 Data Transfer Overflow Status */
                vuint32_t DTROS17:1;    /* Channel 17 Data Transfer Overflow Status */
                vuint32_t DTROS16:1;    /* Channel 16 Data Transfer Overflow Status */
                vuint32_t DTROS15:1;    /* Channel 15 Data Transfer Overflow Status */
                vuint32_t DTROS14:1;    /* Channel 14 Data Transfer Overflow Status */
                vuint32_t DTROS13:1;    /* Channel 13 Data Transfer Overflow Status */
                vuint32_t DTROS12:1;    /* Channel 12 Data Transfer Overflow Status */
                vuint32_t DTROS11:1;    /* Channel 11 Data Transfer Overflow Status */
                vuint32_t DTROS10:1;    /* Channel 10 Data Transfer Overflow Status */
                vuint32_t DTROS9:1;     /* Channel 9 Data Transfer Overflow Status */
                vuint32_t DTROS8:1;     /* Channel 8 Data Transfer Overflow Status */
                vuint32_t DTROS7:1;     /* Channel 7 Data Transfer Overflow Status */
                vuint32_t DTROS6:1;     /* Channel 6 Data Transfer Overflow Status */
                vuint32_t DTROS5:1;     /* Channel 5 Data Transfer Overflow Status */
                vuint32_t DTROS4:1;     /* Channel 4 Data Transfer Overflow Status */
                vuint32_t DTROS3:1;     /* Channel 3 Data Transfer Overflow Status */
                vuint32_t DTROS2:1;     /* Channel 2 Data Transfer Overflow Status */
                vuint32_t DTROS1:1;     /* Channel 1 Data Transfer Overflow Status */
                vuint32_t DTROS0:1;     /* Channel 0 Data Transfer Overflow Status */
            } B;
        } CDTROSR_C;
        uint32_t eTPU_C_reserved0234;     /* 0x0234-0x0237 */

        uint32_t eTPU_C_reserved0238[2];  /* 0x0238-0x023F */
        
        union {                 /* ETPU_C Channel Interruput Enable */
            vuint32_t R;
            struct {
                vuint32_t CIE31:1;      /* Channel 31 Interruput Enable */
                vuint32_t CIE30:1;      /* Channel 30 Interruput Enable */
                vuint32_t CIE29:1;      /* Channel 29 Interruput Enable */
                vuint32_t CIE28:1;      /* Channel 28 Interruput Enable */
                vuint32_t CIE27:1;      /* Channel 27 Interruput Enable */
                vuint32_t CIE26:1;      /* Channel 26 Interruput Enable */
                vuint32_t CIE25:1;      /* Channel 25 Interruput Enable */
                vuint32_t CIE24:1;      /* Channel 24 Interruput Enable */
                vuint32_t CIE23:1;      /* Channel 23 Interruput Enable */
                vuint32_t CIE22:1;      /* Channel 22 Interruput Enable */
                vuint32_t CIE21:1;      /* Channel 21 Interruput Enable */
                vuint32_t CIE20:1;      /* Channel 20 Interruput Enable */
                vuint32_t CIE19:1;      /* Channel 19 Interruput Enable */
                vuint32_t CIE18:1;      /* Channel 18 Interruput Enable */
                vuint32_t CIE17:1;      /* Channel 17 Interruput Enable */
                vuint32_t CIE16:1;      /* Channel 16 Interruput Enable */
                vuint32_t CIE15:1;      /* Channel 15 Interruput Enable */
                vuint32_t CIE14:1;      /* Channel 14 Interruput Enable */
                vuint32_t CIE13:1;      /* Channel 13 Interruput Enable */
                vuint32_t CIE12:1;      /* Channel 12 Interruput Enable */
                vuint32_t CIE11:1;      /* Channel 11 Interruput Enable */
                vuint32_t CIE10:1;      /* Channel 10 Interruput Enable */
                vuint32_t CIE9:1;       /* Channel 9 Interruput Enable */
                vuint32_t CIE8:1;       /* Channel 8 Interruput Enable */
                vuint32_t CIE7:1;       /* Channel 7 Interruput Enable */
                vuint32_t CIE6:1;       /* Channel 6 Interruput Enable */
                vuint32_t CIE5:1;       /* Channel 5 Interruput Enable */
                vuint32_t CIE4:1;       /* Channel 4 Interruput Enable */
                vuint32_t CIE3:1;       /* Channel 3 Interruput Enable */
                vuint32_t CIE2:1;       /* Channel 2 Interruput Enable */
                vuint32_t CIE1:1;       /* Channel 1 Interruput Enable */
                vuint32_t CIE0:1;       /* Channel 0 Interruput Enable */
            } B;
        } CIER_C;
        uint32_t eTPU_C_reserved0244;     /* 0x0244-0x0247 */

        uint32_t eTPU_C_reserved0248[2];  /* 0x0248-0x024F */
        
        union {                 /* ETPU_C Channel Data Transfer Request Enable */
            vuint32_t R;
            struct {
                vuint32_t DTRE31:1;     /* Channel 31 Data Transfer Request Enable */
                vuint32_t DTRE30:1;     /* Channel 30 Data Transfer Request Enable */
                vuint32_t DTRE29:1;     /* Channel 29 Data Transfer Request Enable */
                vuint32_t DTRE28:1;     /* Channel 28 Data Transfer Request Enable */
                vuint32_t DTRE27:1;     /* Channel 27 Data Transfer Request Enable */
                vuint32_t DTRE26:1;     /* Channel 26 Data Transfer Request Enable */
                vuint32_t DTRE25:1;     /* Channel 25 Data Transfer Request Enable */
                vuint32_t DTRE24:1;     /* Channel 24 Data Transfer Request Enable */
                vuint32_t DTRE23:1;     /* Channel 23 Data Transfer Request Enable */
                vuint32_t DTRE22:1;     /* Channel 22 Data Transfer Request Enable */
                vuint32_t DTRE21:1;     /* Channel 21 Data Transfer Request Enable */
                vuint32_t DTRE20:1;     /* Channel 20 Data Transfer Request Enable */
                vuint32_t DTRE19:1;     /* Channel 19 Data Transfer Request Enable */
                vuint32_t DTRE18:1;     /* Channel 18 Data Transfer Request Enable */
                vuint32_t DTRE17:1;     /* Channel 17 Data Transfer Request Enable */
                vuint32_t DTRE16:1;     /* Channel 16 Data Transfer Request Enable */
                vuint32_t DTRE15:1;     /* Channel 15 Data Transfer Request Enable */
                vuint32_t DTRE14:1;     /* Channel 14 Data Transfer Request Enable */
                vuint32_t DTRE13:1;     /* Channel 13 Data Transfer Request Enable */
                vuint32_t DTRE12:1;     /* Channel 12 Data Transfer Request Enable */
                vuint32_t DTRE11:1;     /* Channel 11 Data Transfer Request Enable */
                vuint32_t DTRE10:1;     /* Channel 10 Data Transfer Request Enable */
                vuint32_t DTRE9:1;      /* Channel 9 Data Transfer Request Enable */
                vuint32_t DTRE8:1;      /* Channel 8 Data Transfer Request Enable */
                vuint32_t DTRE7:1;      /* Channel 7 Data Transfer Request Enable */
                vuint32_t DTRE6:1;      /* Channel 6 Data Transfer Request Enable */
                vuint32_t DTRE5:1;      /* Channel 5 Data Transfer Request Enable */
                vuint32_t DTRE4:1;      /* Channel 4 Data Transfer Request Enable */
                vuint32_t DTRE3:1;      /* Channel 3 Data Transfer Request Enable */
                vuint32_t DTRE2:1;      /* Channel 2 Data Transfer Request Enable */
                vuint32_t DTRE1:1;      /* Channel 1 Data Transfer Request Enable */
                vuint32_t DTRE0:1;      /* Channel 0 Data Transfer Request Enable */
            } B;
        } CDTRER_C;
        uint32_t etpu_C_reserved0254;     /* 0x0254-0x0257 */

        uint32_t eTPU_C_reserved0258[2];  /* 0x0258-0x025F */
        
        union {                 /* Watchdog Status Register A */
            vuint32_t R;
            struct {
                vuint32_t WDS31:1;
                vuint32_t WDS30:1;
                vuint32_t WDS29:1;
                vuint32_t WDS28:1;
                vuint32_t WDS27:1;
                vuint32_t WDS26:1;
                vuint32_t WDS25:1;
                vuint32_t WDS24:1;
                vuint32_t WDS23:1;
                vuint32_t WDS22:1;
                vuint32_t WDS21:1;
                vuint32_t WDS20:1;
                vuint32_t WDS19:1;
                vuint32_t WDS18:1;
                vuint32_t WDS17:1;
                vuint32_t WDS16:1;
                vuint32_t WDS15:1;
                vuint32_t WDS14:1;
                vuint32_t WDS13:1;
                vuint32_t WDS12:1;
                vuint32_t WDS11:1;
                vuint32_t WDS10:1;
                vuint32_t WDS9:1;
                vuint32_t WDS8:1;
                vuint32_t WDS7:1;
                vuint32_t WDS6:1;
                vuint32_t WDS5:1;
                vuint32_t WDS4:1;
                vuint32_t WDS3:1;
                vuint32_t WDS2:1;
                vuint32_t WDS1:1;
                vuint32_t WDS0:1;
            } B;
        } WDSR_C;
        
        uint32_t eTPU_C_reserved0264;     /* 0x0264-0x0267 */
        
        uint32_t eTPU_C_reserved0268[6];  /* 0x0268-0x027F */
        
        union {                 /* ETPU_C Channel Pending Service Status */
            vuint32_t R;
            struct {
                vuint32_t SR31:1;       /* Channel 31 Pending Service Status */
                vuint32_t SR30:1;       /* Channel 30 Pending Service Status */
                vuint32_t SR29:1;       /* Channel 29 Pending Service Status */
                vuint32_t SR28:1;       /* Channel 28 Pending Service Status */
                vuint32_t SR27:1;       /* Channel 27 Pending Service Status */
                vuint32_t SR26:1;       /* Channel 26 Pending Service Status */
                vuint32_t SR25:1;       /* Channel 25 Pending Service Status */
                vuint32_t SR24:1;       /* Channel 24 Pending Service Status */
                vuint32_t SR23:1;       /* Channel 23 Pending Service Status */
                vuint32_t SR22:1;       /* Channel 22 Pending Service Status */
                vuint32_t SR21:1;       /* Channel 21 Pending Service Status */
                vuint32_t SR20:1;       /* Channel 20 Pending Service Status */
                vuint32_t SR19:1;       /* Channel 19 Pending Service Status */
                vuint32_t SR18:1;       /* Channel 18 Pending Service Status */
                vuint32_t SR17:1;       /* Channel 17 Pending Service Status */
                vuint32_t SR16:1;       /* Channel 16 Pending Service Status */
                vuint32_t SR15:1;       /* Channel 15 Pending Service Status */
                vuint32_t SR14:1;       /* Channel 14 Pending Service Status */
                vuint32_t SR13:1;       /* Channel 13 Pending Service Status */
                vuint32_t SR12:1;       /* Channel 12 Pending Service Status */
                vuint32_t SR11:1;       /* Channel 11 Pending Service Status */
                vuint32_t SR10:1;       /* Channel 10 Pending Service Status */
                vuint32_t SR9:1;        /* Channel 9 Pending Service Status */
                vuint32_t SR8:1;        /* Channel 8 Pending Service Status */
                vuint32_t SR7:1;        /* Channel 7 Pending Service Status */
                vuint32_t SR6:1;        /* Channel 6 Pending Service Status */
                vuint32_t SR5:1;        /* Channel 5 Pending Service Status */
                vuint32_t SR4:1;        /* Channel 4 Pending Service Status */
                vuint32_t SR3:1;        /* Channel 3 Pending Service Status */
                vuint32_t SR2:1;        /* Channel 2 Pending Service Status */
                vuint32_t SR1:1;        /* Channel 1 Pending Service Status */
                vuint32_t SR0:1;        /* Channel 0 Pending Service Status */
            } B;
        } CPSSR_C;
        uint32_t eTPU_C_reserved0284;     /* 0x0284-0x0287 */

        uint32_t eTPU_C_reserved0288[2];  /* 0x0288-0x028F */
        
        union {                 /* ETPU_C Channel Service Status */
            vuint32_t R;
            struct {
                vuint32_t SS31:1;       /* Channel 31 Service Status */
                vuint32_t SS30:1;       /* Channel 30 Service Status */
                vuint32_t SS29:1;       /* Channel 29 Service Status */
                vuint32_t SS28:1;       /* Channel 28 Service Status */
                vuint32_t SS27:1;       /* Channel 27 Service Status */
                vuint32_t SS26:1;       /* Channel 26 Service Status */
                vuint32_t SS25:1;       /* Channel 25 Service Status */
                vuint32_t SS24:1;       /* Channel 24 Service Status */
                vuint32_t SS23:1;       /* Channel 23 Service Status */
                vuint32_t SS22:1;       /* Channel 22 Service Status */
                vuint32_t SS21:1;       /* Channel 21 Service Status */
                vuint32_t SS20:1;       /* Channel 20 Service Status */
                vuint32_t SS19:1;       /* Channel 19 Service Status */
                vuint32_t SS18:1;       /* Channel 18 Service Status */
                vuint32_t SS17:1;       /* Channel 17 Service Status */
                vuint32_t SS16:1;       /* Channel 16 Service Status */
                vuint32_t SS15:1;       /* Channel 15 Service Status */
                vuint32_t SS14:1;       /* Channel 14 Service Status */
                vuint32_t SS13:1;       /* Channel 13 Service Status */
                vuint32_t SS12:1;       /* Channel 12 Service Status */
                vuint32_t SS11:1;       /* Channel 11 Service Status */
                vuint32_t SS10:1;       /* Channel 10 Service Status */
                vuint32_t SS9:1;        /* Channel 9 Service Status */
                vuint32_t SS8:1;        /* Channel 8 Service Status */
                vuint32_t SS7:1;        /* Channel 7 Service Status */
                vuint32_t SS6:1;        /* Channel 6 Service Status */
                vuint32_t SS5:1;        /* Channel 5 Service Status */
                vuint32_t SS4:1;        /* Channel 4 Service Status */
                vuint32_t SS3:1;        /* Channel 3 Service Status */
                vuint32_t SS2:1;        /* Channel 2 Service Status */
                vuint32_t SS1:1;        /* Channel 1 Service Status */
                vuint32_t SS0:1;        /* Channel 0 Service Status */
            } B;
        } CSSR_C;
        uint32_t eTPU_C_reserved0294;     /* 0x0294-0x0297 */

        uint32_t eTPU_C_reserved0298[2];  /* 0x0298-0x029F */
        
        uint32_t eTPU_C_reserved02A0[88];  /* 0x02A0-0x03FF */

/*****************************Channels********************************/

        struct {
            union {    /* Channel Configuration Register */
                vuint32_t R;
                struct {
                    vuint32_t CIE:1;    /* Channel Interruput Enable */
                    vuint32_t DTRE:1;   /* Data Transfer Request Enable */
                    vuint32_t CPR:2;    /* Channel Priority */
                    vuint32_t:2;
                    vuint32_t ETPD:1;
                    vuint32_t ETCS:1;   /* Entry Table Condition Select */
                    vuint32_t:3;
                    vuint32_t CFS:5;    /* Channel Function Select */
                    vuint32_t ODIS:1;   /* Output disable */
                    vuint32_t OPOL:1;   /* output polarity */
                    vuint32_t:3;
                    vuint32_t CPBA:11;  /* Channel Parameter Base Address */
                } B;
            } CR;
            
            union {    /* Channel Status Control Register */
                vuint32_t R;
                struct {
                    vuint32_t CIS:1;    /* Channel Interruput Status */
                    vuint32_t CIOS:1;   /* Channel Interruput Overflow Status */
                    vuint32_t:6;
                    vuint32_t DTRS:1;   /* Data Transfer Status */
                    vuint32_t DTROS:1;  /* Data Transfer Overflow Status */
                    vuint32_t:6;
                    vuint32_t IPS:1;    /* Input Pin State */
                    vuint32_t OPS:1;    /* Output Pin State */
                    vuint32_t OBE:1;    /* Output Buffer Enable */
                    vuint32_t:11;
                    vuint32_t FM1:1;    /* Function mode */
                    vuint32_t FM0:1;    /* Function mode */
                } B;
            } SCR;
            
            union {    /* Channel Host Service Request Register */
                vuint32_t R;
                struct {
                    vuint32_t:29;       /* Host Service Request */
                    vuint32_t HSR:3;
                } B;
            } HSRR;
            
            uint32_t eTPU_C_ch_reserved00C;  /* channel offset 0x00C-0x00F */
            
        } CHAN[127];
        
        uint32_t eTPU_C_reserved1000[7168];  /* 0x1000-0x7FFF */
        
    };


/****************************************************************************/
/*                          MODULE : PIT / RTI                              */
/****************************************************************************/

    struct PIT_tag {
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:29;
                vuint32_t MDIS_RTI:1;
                vuint32_t MDIS:1;
                vuint32_t FRZ:1;
            } B;
        } MCR;
   
        uint32_t PIT_reserved0004[59];  /* 0x0004-0x00EF */
        
        struct {
            union {
                vuint32_t R;    /* <URM>TSVn</URM> */
            } LDVAL;            /* Timer Load Value Register */

            union {
                vuint32_t R;    /* <URM>TVLn</URM> */
            } CVAL;             /* Current Timer Value Register */

            union {
                vuint32_t R;
                struct {
                    vuint32_t:30;
                    vuint32_t TIE:1;
                    vuint32_t TEN:1;
                } B;
            } TCTRL;            /* Timer Control Register */

            union {
                vuint32_t R;
                struct {
                    vuint32_t:31;
                    vuint32_t TIF:1;
                } B;
            } TFLG;             /* Timer Flag Register */
        } RTI;                  /* RTI Channel */

        struct {
            union {
                vuint32_t R;
                struct {
                    vuint32_t TSV:32;
                } B;
            } LDVAL;
            
            union {
                vuint32_t R;
                struct {
                    vuint32_t TVL:32;
                } B;
            } CVAL;
            
            union {
                vuint32_t R;
                struct {
                    vuint32_t:30;
                    vuint32_t TIE:1;
                    vuint32_t TEN:1;
                } B;
            } TCTRL;
            
            union {
                vuint32_t R;
                struct {
                    vuint32_t:31;
                    vuint32_t TIF:1;
                } B;
            } TFLG;
        } CH[4];

        uint32_t PIT_reserved00140[4016];  /* 0x0140-0x3FFF */
    };

/****************************************************************************/
/*                          MODULE : XBAR CrossBar                          */
/****************************************************************************/

    struct XBAR_tag {
    
        union {                 /* Master Priority Register for Slave Port 0 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR0; /* Legacy naming - refer to PRS0 in Reference Manual */
        
        uint32_t XBAR_reserved0004[3];  /* 0x0004-0x000F */
        
        union {               /* General Purpose Control Register for Slave Port 0 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                vuint32_t:21;
                vuint32_t ARB:2;
                vuint32_t:2;
                vuint32_t PCTL:2;
                vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR0; /* Legacy naming - refer to CRS0 in Reference Manual */
        
        uint32_t XBAR_reserved0014[59];  /* 0x0014-0x00FF */
        
        union {                 /* Master Priority Register for Slave Port 1 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR1; /* Legacy naming - refer to PRS1 in Reference Manual */
        
        uint32_t XBAR_reserved0104[3];  /* 0x0104-0x010F */
        
        union {               /* General Purpose Control Register for Slave Port 1 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                vuint32_t:21;
                vuint32_t ARB:2;
                vuint32_t:2;
                vuint32_t PCTL:2;
                vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR1; /* Legacy naming - refer to CRS1 in Reference Manual */
        
        uint32_t XBAR_reserved0114[59];  /* 0x0114-0x01FF */
        
        union {                 /* Master Priority Register for Slave Port 2 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR2; /* Legacy naming - refer to PRS2 in Reference Manual */
        
        uint32_t XBAR_reserved0204[3];  /* 0x0204-0x020F */
        
        union {               /* General Purpose Control Register for Slave Port 2 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                vuint32_t:21;
                vuint32_t ARB:2;
                vuint32_t:2;
                vuint32_t PCTL:2;
                vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR2; /* Legacy naming - refer to CRS2 in Reference Manual */
        
        uint32_t XBAR_reserved0214[59];  /* 0x0214-0x02FF */
        
        union {                 /* Master Priority Register for Slave Port 3 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR3; /* Legacy naming - refer to PRS3 in Reference Manual */
        
        uint32_t XBAR_reserved0304[3];  /* 0x0304-0x030F */
        
        union {               /* General Purpose Control Register for Slave Port 3 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                vuint32_t:21;
                vuint32_t ARB:2;
                vuint32_t:2;
                vuint32_t PCTL:2;
                vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR3; /* Legacy naming - refer to CRS3 in Reference Manual */
        
        uint32_t XBAR_reserved0314[59];  /* 0x0314-0x03FF */
        
        union {                 /* Master Priority Register for Slave Port 4 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR4; /* Legacy naming - refer to PRS4 in Reference Manual */
        
        uint32_t XBAR_reserved0404[3];  /* 0x0404-0x040F */
        
        union {               /* General Purpose Control Register for Slave Port 4 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                vuint32_t:21;
                vuint32_t ARB:2;
                vuint32_t:2;
                vuint32_t PCTL:2;
                vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR4; /* Legacy naming - refer to CRS4 in Reference Manual */
        
        uint32_t XBAR_reserved0414[59];  /* 0x0414-0x04FF */
        
        uint32_t XBAR_reserved0500[64];  /* 0x0500-0x05FF */
        
        union {                 /* Master Priority Register for Slave Port 6 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR6; /* Legacy naming - refer to PRS6 in Reference Manual */
        
        uint32_t XBAR_reserved604[3];  /* 0x0604-0x060F */
        
        union {               /* General Purpose Control Register for Slave Port 6 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                vuint32_t:21;
                vuint32_t ARB:2;
                vuint32_t:2;
                vuint32_t PCTL:2;
                vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR6; /* Legacy naming - refer to CRS6 in Reference Manual */
        
        uint32_t XBAR_reserved0614[59];  /* 0x0614-0x06FF */
        
        union {                 /* Master Priority Register for Slave Port 7 */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t MSTR7:3; /* FEC */
                vuint32_t:1;
                vuint32_t MSTR6:3; /* CSE and SIPI */
                vuint32_t:1;
                vuint32_t MSTR5:3; /* eDMA_B */
                vuint32_t:1;
                vuint32_t MSTR4:3; /* eDMA_A */
                vuint32_t:1;
                vuint32_t MSTR3:3; /* e200z7 core 1 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR2:3; /* e200z7 core 1 CPU Instruction */
                vuint32_t:1;
                vuint32_t MSTR1:3; /* e200z7 core 0 Data, and Nexus 3 */
                vuint32_t:1;
                vuint32_t MSTR0:3; /* e200z7 core 0 CPU Instruction */
            } B;
        } MPR7; /* Legacy naming - refer to PRS7 in Reference Manual */
        
        uint32_t XBAR_reserved704[3];  /* 0x0704-0x070F */
        
        union {              /* General Purpose Control Register for Slave Port 7 */
            vuint32_t R;
            struct {
                vuint32_t RO:1;
                  vuint32_t:21;
                vuint32_t ARB:2;
                  vuint32_t:2;
                vuint32_t PCTL:2;
                  vuint32_t:1;
                vuint32_t PARK:3;
            } B;
        } SGPCR7; /* Legacy naming - refer to CRS7 in Reference Manual */ 
        
        uint32_t XBAR_reserved0714[59];  /* 0x0714-0x07FF */
        
        uint32_t XBAR_reserved0800[3584];  /* 0x0800-0x3FFF */
    };

/****************************************************************************/
/*                          MODULE : MPU                                    */
/****************************************************************************/

    struct MPU_tag {
    
        union {                 /* Module Control/Error Status Register */
            vuint32_t R;
            struct {
                vuint32_t SPERR:8;
                  vuint32_t:4;
                vuint32_t HRL:4;
                vuint32_t NSP:4;
                vuint32_t NRGD:4;
                  vuint32_t:7;
                vuint32_t VLD:1;
            } B;
        } CESR;
        
        uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */
        
        struct {
            union {             /* MPU Error Address Registers */
                vuint32_t R;
                struct {
                    vuint32_t EADDR:32;
                } B;
            } EAR;
            
            union {             /* MPU Error Detail Registers */
                vuint32_t R;
                struct {
                    vuint32_t EACD:16;
                    vuint32_t EPID:8;
                    vuint32_t EMN:4;
                    vuint32_t EATTR:3;
                    vuint32_t ERW:1;
                } B;
            } EDR;
        } PORT[4];
        
        uint32_t MPU_reserved0030[244];  /* 0x0028-0x03FF */
        
        struct {
            union {            /* Region Descriptor n Word 0 */
                vuint32_t R;
                struct {
                    vuint32_t SRTADDR:27;
                    vuint32_t:5;
                } B;
            } WORD0;
            
            union {            /* Region Descriptor n Word 1 */
                vuint32_t R;
                struct {
                    vuint32_t ENDADDR:27;
                    vuint32_t:5;
                } B;
            } WORD1;
            
            union {            /* Region Descriptor n Word 2 */
                vuint32_t R;
                struct {
                    vuint32_t M7RE:1;   /* Reserved */
                    vuint32_t M7WE:1;   /* Reserved */
                    vuint32_t M6RE:1;   /* FlexRay Read Enable */
                    vuint32_t M6WE:1;   /* FlexRay Write Enable */
                    vuint32_t M5RE:1;   /* eDMA_B Read Enable */
                    vuint32_t M5WE:1;   /* eDMA_B Write Enable */
                    vuint32_t M4RE:1;   /* eDMA_A Read Enable */
                    vuint32_t M4WE:1;   /* eDMA_A Write Enable */
                    vuint32_t M3PE:1;   /* Reserved */
                    vuint32_t M3SM:2;   /* Reserved */
                    vuint32_t M3UM:3;   /* Reserved */
                    vuint32_t M2PE:1;   /* Reserved */
                    vuint32_t M2SM:2;   /* Reserved */
                    vuint32_t M2UM:3;   /* Reserved */
                    vuint32_t M1PE:1;   /* Core 1 PID Enable */
                    vuint32_t M1SM:2;   /* Core 1 Supervisor Mode Access */
                    vuint32_t M1UM:3;   /* Core 1 User Mode Access */
                    vuint32_t M0PE:1;   /* Core 0 PID Enable */
                    vuint32_t M0SM:2;   /* Core 0 Supervisor Mode Access */
                    vuint32_t M0UM:3;   /* Core 0 User Mode Access */
                } B;
            } WORD2;
            
            union {            /* Region Descriptor n Word 3 */
                vuint32_t R;
                struct {
                    vuint32_t PID:8;
                    vuint32_t PIDMASK:8;
                      vuint32_t:15;
                    vuint32_t VLD:1;
                } B;
            } WORD3;
        } RGD[16];
        
        uint32_t MPU_reserved0500[192];  /* 0x0500-0x07FF */
        
        union {           /* Region Descriptor Alternate Access Control n */
            vuint32_t R;
            struct {
                vuint32_t M7RE:1;   /* Reserved */
                vuint32_t M7WE:1;   /* Reserved */
                vuint32_t M6RE:1;   /* FlexRay Read Enable */
                vuint32_t M6WE:1;   /* FlexRay Write Enable */
                vuint32_t M5RE:1;   /* eDMA_B Read Enable */
                vuint32_t M5WE:1;   /* eDMA_B Write Enable */
                vuint32_t M4RE:1;   /* eDMA_A Read Enable */
                vuint32_t M4WE:1;   /* eDMA_A Write Enable */
                vuint32_t M3PE:1;   /* Reserved */
                vuint32_t M3SM:2;   /* Reserved */
                vuint32_t M3UM:3;   /* Reserved */
                vuint32_t M2PE:1;   /* Reserved */
                vuint32_t M2SM:2;   /* Reserved */
                vuint32_t M2UM:3;   /* Reserved */
                vuint32_t M1PE:1;   /* Core 1 PID Enable */
                vuint32_t M1SM:2;   /* Core 1 Supervisor Mode Access */
                vuint32_t M1UM:3;   /* Core 1 User Mode Access */
                vuint32_t M0PE:1;   /* Core 0 PID Enable */
                vuint32_t M0SM:2;   /* Core 0 Supervisor Mode Access */
                vuint32_t M0UM:3;   /* Core 0 User Mode Access */
            } B;
        } RGDAAC[16];
        
        uint32_t MPU_reserved0840[3568];  /* 0x0840-0x3FFF */
    
    };

/****************************************************************************/
/*                     MODULE : SWT                                         */
/****************************************************************************/

    struct SWT_tag {
    
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t MAP0:1;
                vuint32_t MAP1:1;
                vuint32_t:1;
                vuint32_t:1;
                vuint32_t MAP4:1;
                vuint32_t MAP5:1;
                vuint32_t MAP6:1;
                vuint32_t MAP7:1;
                vuint32_t:14;
                vuint32_t KEY:1;
                vuint32_t RIA:1;
                vuint32_t WND:1;
                vuint32_t ITR:1;
                vuint32_t HLK:1;
                vuint32_t SLK:1;
                vuint32_t CSL:1;
                vuint32_t STP:1;
                vuint32_t FRZ:1;
                vuint32_t WEN:1;
            } B;
        } MCR;
        
        union {                /* Interrupt register */
            vuint32_t R;
            struct {
                vuint32_t :31;
                vuint32_t TIF:1;
            } B;
        } IR;
        
        union {                /* Timeout register */
            vuint32_t R;
            struct {
                vuint32_t WTO:32;
            } B;
        } TO;
        
        union {                /* Window register */
            vuint32_t R;
            struct {
                vuint32_t WST:32;
            } B;
        } WN;
        
        union {                /* Service register */
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t WSC:16;
            } B;
        } SR;
        
        union {                /* Counter output register */
            vuint32_t R;
            struct {
                vuint32_t CNT:32;
            } B;
        } CO;
        
        union {                /* Service key register */
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t SK:16;
            } B;
        } SK;
        
        uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */
    
    };

/****************************************************************************/
/*                     MODULE : STM                                         */
/****************************************************************************/

    struct STM_tag {
    
        union {                  /* Control Register */
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t CPS:8;
                vuint32_t :6;
                vuint32_t FRZ:1;
                vuint32_t TEN:1;
            } B;
        } CR;
        
        union {                /* STM Counter */
            vuint32_t R;
        } CNT;
        
        uint32_t STM_reserved0008[2];  /* 0x0008-0x000F */
        
        /* channel 0 registers */
        union {
            vuint32_t R;
            struct {
                vuint32_t :31;
              vuint32_t CEN:1;        
            } B;
        } CCR0;                /* Chan 0 Control Register */
        
        union {
          vuint32_t R;
            struct {
                vuint32_t :31;
                vuint32_t CIF:1;
          } B;
        } CIR0;                /* Chan 0 Interrupt Register */
  
        union {
          vuint32_t R;
        } CMP0;                /* Chan 0 Compare Register */

        uint32_t STM_reserved2[1];
  
        /* channel 1 registers */
        union {
            vuint32_t R;
            struct {
                vuint32_t :31;
              vuint32_t CEN:1;        
            } B;
        } CCR1;                /* Chan 1 Control Register */
        
        union {
          vuint32_t R;
            struct {
                vuint32_t :31;
                vuint32_t CIF:1;
          } B;
        } CIR1;                /* Chan 1 Interrupt Register */
  
        union {
          vuint32_t R;
        } CMP1;                /* Chan 1 Compare Register */

        uint32_t STM_reserved3[1];
        
        /* channel 2 registers */
        union {
            vuint32_t R;
            struct {
                vuint32_t :31;
              vuint32_t CEN:1;        
            } B;
        } CCR2;                /* Chan 2 Control Register */
        
        union {
          vuint32_t R;
            struct {
                vuint32_t :31;
                vuint32_t CIF:1;
          } B;
        } CIR2;                /* Chan 2 Interrupt Register */
  
        union {
          vuint32_t R;
        } CMP2;                /* Chan 2 Compare Register */

        uint32_t STM_reserved4[1];

        /* channel 3 registers */
        union {
            vuint32_t R;
            struct {
                vuint32_t :31;
              vuint32_t CEN:1;        
            } B;
        } CCR3;                /* Chan 3 Control Register */
        
        union {
          vuint32_t R;
            struct {
                vuint32_t :31;
                vuint32_t CIF:1;
          } B;
        } CIR3;                /* Chan 3 Interrupt Register */
  
        union {
          vuint32_t R;
        } CMP3;                /* Chan 3 Compare Register */
        
        uint32_t STM_reserved0050[4076];  /* 0x0050-0x3FFF */
    
    };

/****************************************************************************/
/*                     MODULE : ECSM                                        */
/****************************************************************************/

    struct ECSM_tag {
    
        union {                /* Processor core type */
            vuint16_t R;
        } PCT;
        
        union {                /* Platform revision */
            vuint16_t R;
        } REV;
        
        union {                /* Platform AXBS Master Configuration */
            vuint16_t R;
        } PLAMC;
        
        union {                /* Platform AXBS Slave Configuration */
            vuint16_t R;
        } PLASC;
        
        union {                 /* IPS Module Configuration */
            vuint32_t R;
        } IMC;
        
        uint8_t ECSM_reserved000C[3];  /* 0x000C-0x000E */
        
        union {                 /* Miscellaneous Reset Status Register */
            vuint8_t R;
            struct {
                vuint8_t POR:1;
                vuint8_t DIR:1;
                vuint8_t SWTR:1;
                vuint8_t:5;
            } B;
        } MRSR;
        
        uint8_t ECSM_reserved0010[20]; /* 0x0010-0x0023 */
        
        union {                 /* Miscellaneous User-Defined Control Register */
            vuint32_t R;
            struct {
                vuint32_t:1;
                vuint32_t SRAM_WS:1;
                vuint32_t:30;
            } B;
        } MUDCR;
        
        uint8_t ECSM_reserved0028[27]; /* 0x0028-0x0042 */

        union {                  /* ECC Configuration Register */
            vuint8_t R;
            struct {
                vuint8_t:2;
                vuint8_t ER1BR:1;
                vuint8_t EF1BR:1;
                vuint8_t:2;
                vuint8_t ERNCR:1;
                vuint8_t EFNCR:1;
            } B;
        } ECR;
        
        uint8_t ECSM_reserved0044[3];  /* 0x0044-0x0046 */
        
        union {                  /* ECC Status Register */
            vuint8_t R;
            struct {
                vuint8_t:2;
                vuint8_t R1BC:1;
                vuint8_t F1BC:1;
                vuint8_t:2;
                vuint8_t RNCE:1;
                vuint8_t FNCE:1;
            } B;
        } ESR;
        
        uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */
        
        union {                 /* ECC Error Generation Register */
            vuint16_t R;
            struct {
                vuint16_t:2;
                vuint16_t FRC1BI:1;
                vuint16_t FR11BI:1;
                vuint16_t:2;
                vuint16_t FRCNCI:1;
                vuint16_t FR1NCI:1;
                vuint16_t:1;
                vuint16_t ERRBIT:7;
            } B;
        } EEGR;
        
        uint32_t ECSM_reserved004C; /* 0x004C-0x004F */
        
        union {                 /* Flash ECC Address Register */
            vuint32_t R;
            struct {
                vuint32_t FEAR:32;
            } B;
        } FEAR;
        
        uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */
        
        union {                 /* Flash ECC Master Number Register */
            vuint8_t R;
            struct {
                vuint8_t:4;
                vuint8_t FEMR:4;
            } B;
        } FEMR;
        
        union {                 /* Flash ECC Attributes Register */
            vuint8_t R;
            struct {
                vuint8_t WRITE:1;
                vuint8_t SIZE:3;
                vuint8_t PROT0:1;
                vuint8_t PROT1:1;
                vuint8_t PROT2:1;
                vuint8_t PROT3:1;
            } B;
        } FEAT;
        
        union {                /* Flash ECC Data Register High */
            vuint32_t R;
            struct {
                vuint32_t FEDH:32;
            } B;
        } FEDRH;
        
        union {                /* Flash ECC Data Register Low */
            vuint32_t R;
            struct {
                vuint32_t FEDL:32;
            } B;
        } FEDRL;
        
        union {                /* RAM ECC Address Register */
            vuint32_t R;
            struct {
                vuint32_t REAR:32;
            } B;
        } REAR;
        
        uint8_t ECSM_reserved0064; /* 0x0064 */
                
        union {                /* RAM ECC Syndrome Register */
            vuint8_t R;
            struct {
                vuint8_t RESR:8;
            } B;
        } RESR;
        
        union {                 /* RAM ECC Master Number Register */
            vuint8_t R;
            struct {
                vuint8_t:4;
                vuint8_t REMR:4;
            } B;
        } REMR;
        
        union {                 /* RAM ECC Attributes Register */
            vuint8_t R;
            struct {
                vuint8_t WRITE:1;
                vuint8_t SIZE:3;
                vuint8_t PROT0:1;
                vuint8_t PROT1:1;
                vuint8_t PROT2:1;
                vuint8_t PROT3:1;
            } B;
        } REAT;
        
        union {                /* RAM ECC Data Register */
            vuint32_t R;
            struct {
                vuint32_t REDH:32;
            } B;
        } REDRH;
        
        union {                /* RAM ECC Data Register */
            vuint32_t R;
            struct {
                vuint32_t REDL:32;
            } B;
        } REDRL;
        
        uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */
    
    };

/****************************************************************************/
/*                          MODULE : eDMA                                   */
/****************************************************************************/

    struct EDMA_tag {
    
        union {                   /* Control Register */
            vuint32_t R;
            struct {
                vuint32_t:14;
                vuint32_t CX:1;     /* Legacy name. CXFR in reference manual */
                vuint32_t ECX:1;
                vuint32_t GRP3PRI:2;
                vuint32_t GRP2PRI:2;
                vuint32_t GRP1PRI:2;
                vuint32_t GRP0PRI:2;
                vuint32_t EMLM:1;
                vuint32_t CLM:1;
                vuint32_t HALT:1;
                vuint32_t HOE:1;
                vuint32_t ERGA:1;
                vuint32_t ERCA:1;
                vuint32_t EDBG:1;
                vuint32_t:1;
            } B;
        } CR; /* Legacy naming - refer to MCR in Reference Manual */
        
        union {                  /* Error Status Register */
            vuint32_t R;
            struct {
                vuint32_t VLD:1;
                vuint32_t:14;
                vuint32_t ECX:1;
                vuint32_t GPE:1;
                vuint32_t CPE:1;
                vuint32_t ERRCHN:6;
                vuint32_t SAE:1;
                vuint32_t SOE:1;
                vuint32_t DAE:1;
                vuint32_t DOE:1;
                vuint32_t NCE:1;
                vuint32_t SGE:1;
                vuint32_t SBE:1;
                vuint32_t DBE:1;
            } B;
        } ESR;
        
        union {                /* DMA Enable Request Register High */
            vuint32_t R;
            struct {
                vuint32_t ERQ63:1;
                vuint32_t ERQ62:1;
                vuint32_t ERQ61:1;
                vuint32_t ERQ60:1;
                vuint32_t ERQ59:1;
                vuint32_t ERQ58:1;
                vuint32_t ERQ57:1;
                vuint32_t ERQ56:1;
                vuint32_t ERQ55:1;
                vuint32_t ERQ54:1;
                vuint32_t ERQ53:1;
                vuint32_t ERQ52:1;
                vuint32_t ERQ51:1;
                vuint32_t ERQ50:1;
                vuint32_t ERQ49:1;
                vuint32_t ERQ48:1;
                vuint32_t ERQ47:1;
                vuint32_t ERQ46:1;
                vuint32_t ERQ45:1;
                vuint32_t ERQ44:1;
                vuint32_t ERQ43:1;
                vuint32_t ERQ42:1;
                vuint32_t ERQ41:1;
                vuint32_t ERQ40:1;
                vuint32_t ERQ39:1;
                vuint32_t ERQ38:1;
                vuint32_t ERQ37:1;
                vuint32_t ERQ36:1;
                vuint32_t ERQ35:1;
                vuint32_t ERQ34:1;
                vuint32_t ERQ33:1;
                vuint32_t ERQ32:1;
            } B;
        } ERQRH;
        
        union {                /* DMA Enable Request Register Low */
            vuint32_t R;
            struct {
                vuint32_t ERQ31:1;
                vuint32_t ERQ30:1;
                vuint32_t ERQ29:1;
                vuint32_t ERQ28:1;
                vuint32_t ERQ27:1;
                vuint32_t ERQ26:1;
                vuint32_t ERQ25:1;
                vuint32_t ERQ24:1;
                vuint32_t ERQ23:1;
                vuint32_t ERQ22:1;
                vuint32_t ERQ21:1;
                vuint32_t ERQ20:1;
                vuint32_t ERQ19:1;
                vuint32_t ERQ18:1;
                vuint32_t ERQ17:1;
                vuint32_t ERQ16:1;
                vuint32_t ERQ15:1;
                vuint32_t ERQ14:1;
                vuint32_t ERQ13:1;
                vuint32_t ERQ12:1;
                vuint32_t ERQ11:1;
                vuint32_t ERQ10:1;
                vuint32_t ERQ09:1;
                vuint32_t ERQ08:1;
                vuint32_t ERQ07:1;
                vuint32_t ERQ06:1;
                vuint32_t ERQ05:1;
                vuint32_t ERQ04:1;
                vuint32_t ERQ03:1;
                vuint32_t ERQ02:1;
                vuint32_t ERQ01:1;
                vuint32_t ERQ00:1;
            } B;
        } ERQRL;
        
        union {                /* DMA Enable Error Interrupt Register High */
            vuint32_t R;
            struct {
                
                vuint32_t EEI63:1;
                vuint32_t EEI62:1;
                vuint32_t EEI61:1;
                vuint32_t EEI60:1;
                vuint32_t EEI59:1;
                vuint32_t EEI58:1;
                vuint32_t EEI57:1;
                vuint32_t EEI56:1;
                vuint32_t EEI55:1;
                vuint32_t EEI54:1;
                vuint32_t EEI53:1;
                vuint32_t EEI52:1;
                vuint32_t EEI51:1;
                vuint32_t EEI50:1;
                vuint32_t EEI49:1;
                vuint32_t EEI48:1;
                vuint32_t EEI47:1;
                vuint32_t EEI46:1;
                vuint32_t EEI45:1;
                vuint32_t EEI44:1;
                vuint32_t EEI43:1;
                vuint32_t EEI42:1;
                vuint32_t EEI41:1;
                vuint32_t EEI40:1;
                vuint32_t EEI39:1;
                vuint32_t EEI38:1;
                vuint32_t EEI37:1;
                vuint32_t EEI36:1;
                vuint32_t EEI35:1;
                vuint32_t EEI34:1;
                vuint32_t EEI33:1;
                vuint32_t EEI32:1;
            } B;
        } EEIRH;
        
        union {                /* DMA Enable Error Interrupt Register Low */
            vuint32_t R;
            struct {
                vuint32_t EEI31:1;
                vuint32_t EEI30:1;
                vuint32_t EEI29:1;
                vuint32_t EEI28:1;
                vuint32_t EEI27:1;
                vuint32_t EEI26:1;
                vuint32_t EEI25:1;
                vuint32_t EEI24:1;
                vuint32_t EEI23:1;
                vuint32_t EEI22:1;
                vuint32_t EEI21:1;
                vuint32_t EEI20:1;
                vuint32_t EEI19:1;
                vuint32_t EEI18:1;
                vuint32_t EEI17:1;
                vuint32_t EEI16:1;
                vuint32_t EEI15:1;
                vuint32_t EEI14:1;
                vuint32_t EEI13:1;
                vuint32_t EEI12:1;
                vuint32_t EEI11:1;
                vuint32_t EEI10:1;
                vuint32_t EEI09:1;
                vuint32_t EEI08:1;
                vuint32_t EEI07:1;
                vuint32_t EEI06:1;
                vuint32_t EEI05:1;
                vuint32_t EEI04:1;
                vuint32_t EEI03:1;
                vuint32_t EEI02:1;
                vuint32_t EEI01:1;
                vuint32_t EEI00:1;
            } B;
        } EEIRL;
        
        union {                /* DMA Set Enable Request Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t SERQ:7;
            } B;
        } SERQR;
        
        union {                /* DMA Clear Enable Request Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t CERQ:7;
            } B;
        } CERQR;
        
        union {                /* DMA Set Enable Error Interrupt Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t SEEI:7;
            } B;
        } SEEIR;
        
        union {                /* DMA Clear Enable Error Interrupt Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t CEEI:7;
            } B;
        } CEEIR;
        
        union {                /* DMA Clear Interrupt Request Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t CINT:7;
            } B;
        } CIRQR;
        
        union {                  /* DMA Clear error Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t CERR:7;
            } B;
        } CER;
        
        union {                 /* Set Start Bit Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t SSB:7;
            } B;
        } SSBR;
        
        union {                /* Clear Done Status Bit Register */
            vuint8_t R;
            struct {
                vuint8_t NOP:1;
                vuint8_t CDSB:7;
            } B;
        } CDSBR;
        
        union {                /* DMA Interrupt Request High */
            vuint32_t R;
            struct {
                vuint32_t INT63:1;
                vuint32_t INT62:1;
                vuint32_t INT61:1;
                vuint32_t INT60:1;
                vuint32_t INT59:1;
                vuint32_t INT58:1;
                vuint32_t INT57:1;
                vuint32_t INT56:1;
                vuint32_t INT55:1;
                vuint32_t INT54:1;
                vuint32_t INT53:1;
                vuint32_t INT52:1;
                vuint32_t INT51:1;
                vuint32_t INT50:1;
                vuint32_t INT49:1;
                vuint32_t INT48:1;
                vuint32_t INT47:1;
                vuint32_t INT46:1;
                vuint32_t INT45:1;
                vuint32_t INT44:1;
                vuint32_t INT43:1;
                vuint32_t INT42:1;
                vuint32_t INT41:1;
                vuint32_t INT40:1;
                vuint32_t INT39:1;
                vuint32_t INT38:1;
                vuint32_t INT37:1;
                vuint32_t INT36:1;
                vuint32_t INT35:1;
                vuint32_t INT34:1;
                vuint32_t INT33:1;
                vuint32_t INT32:1;
            } B;
        } IRQRH;
        
        union {                /* DMA Interrupt Request Low */
            vuint32_t R;
            struct {
                vuint32_t INT31:1;
                vuint32_t INT30:1;
                vuint32_t INT29:1;
                vuint32_t INT28:1;
                vuint32_t INT27:1;
                vuint32_t INT26:1;
                vuint32_t INT25:1;
                vuint32_t INT24:1;
                vuint32_t INT23:1;
                vuint32_t INT22:1;
                vuint32_t INT21:1;
                vuint32_t INT20:1;
                vuint32_t INT19:1;
                vuint32_t INT18:1;
                vuint32_t INT17:1;
                vuint32_t INT16:1;
                vuint32_t INT15:1;
                vuint32_t INT14:1;
                vuint32_t INT13:1;
                vuint32_t INT12:1;
                vuint32_t INT11:1;
                vuint32_t INT10:1;
                vuint32_t INT09:1;
                vuint32_t INT08:1;
                vuint32_t INT07:1;
                vuint32_t INT06:1;
                vuint32_t INT05:1;
                vuint32_t INT04:1;
                vuint32_t INT03:1;
                vuint32_t INT02:1;
                vuint32_t INT01:1;
                vuint32_t INT00:1;
            } B;
        } IRQRL;
        
        union {                  /* DMA Error High */
            vuint32_t R;
            struct {
                vuint32_t ERR63:1;
                vuint32_t ERR62:1;
                vuint32_t ERR61:1;
                vuint32_t ERR60:1;
                vuint32_t ERR59:1;
                vuint32_t ERR58:1;
                vuint32_t ERR57:1;
                vuint32_t ERR56:1;
                vuint32_t ERR55:1;
                vuint32_t ERR54:1;
                vuint32_t ERR53:1;
                vuint32_t ERR52:1;
                vuint32_t ERR51:1;
                vuint32_t ERR50:1;
                vuint32_t ERR49:1;
                vuint32_t ERR48:1;
                vuint32_t ERR47:1;
                vuint32_t ERR46:1;
                vuint32_t ERR45:1;
                vuint32_t ERR44:1;
                vuint32_t ERR43:1;
                vuint32_t ERR42:1;
                vuint32_t ERR41:1;
                vuint32_t ERR40:1;
                vuint32_t ERR39:1;
                vuint32_t ERR38:1;
                vuint32_t ERR37:1;
                vuint32_t ERR36:1;
                vuint32_t ERR35:1;
                vuint32_t ERR34:1;
                vuint32_t ERR33:1;
                vuint32_t ERR32:1;
            } B;
        } ERH;
        
        union {                  /* DMA Error Low */
            vuint32_t R;
            struct {
                vuint32_t ERR31:1;
                vuint32_t ERR30:1;
                vuint32_t ERR29:1;
                vuint32_t ERR28:1;
                vuint32_t ERR27:1;
                vuint32_t ERR26:1;
                vuint32_t ERR25:1;
                vuint32_t ERR24:1;
                vuint32_t ERR23:1;
                vuint32_t ERR22:1;
                vuint32_t ERR21:1;
                vuint32_t ERR20:1;
                vuint32_t ERR19:1;
                vuint32_t ERR18:1;
                vuint32_t ERR17:1;
                vuint32_t ERR16:1;
                vuint32_t ERR15:1;
                vuint32_t ERR14:1;
                vuint32_t ERR13:1;
                vuint32_t ERR12:1;
                vuint32_t ERR11:1;
                vuint32_t ERR10:1;
                vuint32_t ERR09:1;
                vuint32_t ERR08:1;
                vuint32_t ERR07:1;
                vuint32_t ERR06:1;
                vuint32_t ERR05:1;
                vuint32_t ERR04:1;
                vuint32_t ERR03:1;
                vuint32_t ERR02:1;
                vuint32_t ERR01:1;
                vuint32_t ERR00:1;
            } B;
        } ERL;
        
        union {                  /* hardware request status high */
            vuint32_t R;
            struct {
                vuint32_t HRS63:1;
                vuint32_t HRS62:1;
                vuint32_t HRS61:1;
                vuint32_t HRS60:1;
                vuint32_t HRS59:1;
                vuint32_t HRS58:1;
                vuint32_t HRS57:1;
                vuint32_t HRS56:1;
                vuint32_t HRS55:1;
                vuint32_t HRS54:1;
                vuint32_t HRS53:1;
                vuint32_t HRS52:1;
                vuint32_t HRS51:1;
                vuint32_t HRS50:1;
                vuint32_t HRS49:1;
                vuint32_t HRS48:1;
                vuint32_t HRS47:1;
                vuint32_t HRS46:1;
                vuint32_t HRS45:1;
                vuint32_t HRS44:1;
                vuint32_t HRS43:1;
                vuint32_t HRS42:1;
                vuint32_t HRS41:1;
                vuint32_t HRS40:1;
                vuint32_t HRS39:1;
                vuint32_t HRS38:1;
                vuint32_t HRS37:1;
                vuint32_t HRS36:1;
                vuint32_t HRS35:1;
                vuint32_t HRS34:1;
                vuint32_t HRS33:1;
                vuint32_t HRS32:1;
            } B;
        } HRSH;
        
        union {                  /* hardware request status low */
            vuint32_t R;
            struct {
                vuint32_t HRS31:1;
                vuint32_t HRS30:1;
                vuint32_t HRS29:1;
                vuint32_t HRS28:1;
                vuint32_t HRS27:1;
                vuint32_t HRS26:1;
                vuint32_t HRS25:1;
                vuint32_t HRS24:1;
                vuint32_t HRS23:1;
                vuint32_t HRS22:1;
                vuint32_t HRS21:1;
                vuint32_t HRS20:1;
                vuint32_t HRS19:1;
                vuint32_t HRS18:1;
                vuint32_t HRS17:1;
                vuint32_t HRS16:1;
                vuint32_t HRS15:1;
                vuint32_t HRS14:1;
                vuint32_t HRS13:1;
                vuint32_t HRS12:1;
                vuint32_t HRS11:1;
                vuint32_t HRS10:1;
                vuint32_t HRS09:1;
                vuint32_t HRS08:1;
                vuint32_t HRS07:1;
                vuint32_t HRS06:1;
                vuint32_t HRS05:1;
                vuint32_t HRS04:1;
                vuint32_t HRS03:1;
                vuint32_t HRS02:1;
                vuint32_t HRS01:1;
                vuint32_t HRS00:1;
            } B;
        } HRSL;
        
        union {                  /* Global Write Register High */
            vuint32_t R;
            struct {
                vuint32_t GWEN63:1;
                vuint32_t GWEN62:1;
                vuint32_t GWEN61:1;
                vuint32_t GWEN60:1;
                vuint32_t GWEN59:1;
                vuint32_t GWEN58:1;
                vuint32_t GWEN57:1;
                vuint32_t GWEN56:1;
                vuint32_t GWEN55:1;
                vuint32_t GWEN54:1;
                vuint32_t GWEN53:1;
                vuint32_t GWEN52:1;
                vuint32_t GWEN51:1;
                vuint32_t GWEN50:1;
                vuint32_t GWEN49:1;
                vuint32_t GWEN48:1;
                vuint32_t GWEN47:1;
                vuint32_t GWEN46:1;
                vuint32_t GWEN45:1;
                vuint32_t GWEN44:1;
                vuint32_t GWEN43:1;
                vuint32_t GWEN42:1;
                vuint32_t GWEN41:1;
                vuint32_t GWEN40:1;
                vuint32_t GWEN39:1;
                vuint32_t GWEN38:1;
                vuint32_t GWEN37:1;
                vuint32_t GWEN36:1;
                vuint32_t GWEN35:1;
                vuint32_t GWEN34:1;
                vuint32_t GWEN33:1;
                vuint32_t GWEN32:1;
            } B;
        } GWRH;
        
        union {                  /* hardware request status low */
            vuint32_t R;
            struct {
                vuint32_t GWEN31:1;
                vuint32_t GWEN30:1;
                vuint32_t GWEN29:1;
                vuint32_t GWEN28:1;
                vuint32_t GWEN27:1;
                vuint32_t GWEN26:1;
                vuint32_t GWEN25:1;
                vuint32_t GWEN24:1;
                vuint32_t GWEN23:1;
                vuint32_t GWEN22:1;
                vuint32_t GWEN21:1;
                vuint32_t GWEN20:1;
                vuint32_t GWEN19:1;
                vuint32_t GWEN18:1;
                vuint32_t GWEN17:1;
                vuint32_t GWEN16:1;
                vuint32_t GWEN15:1;
                vuint32_t GWEN14:1;
                vuint32_t GWEN13:1;
                vuint32_t GWEN12:1;
                vuint32_t GWEN11:1;
                vuint32_t GWEN10:1;
                vuint32_t GWEN09:1;
                vuint32_t GWEN08:1;
                vuint32_t GWEN07:1;
                vuint32_t GWEN06:1;
                vuint32_t GWEN05:1;
                vuint32_t GWEN04:1;
                vuint32_t GWEN03:1;
                vuint32_t GWEN02:1;
                vuint32_t GWEN01:1;
                vuint32_t GWEN00:1;
            } B;
        } GWRL;
        
        uint32_t eDMA_reserved0040[48];  /* 0x0040-0x00FF */
        
        union {              /* Channel n Priority */
            vuint8_t R;
            struct {
                vuint8_t ECP:1;
                vuint8_t DPA:1;
                vuint8_t GRPPRI:2;
                vuint8_t CHPRI:4;
            } B;
        } CPR[64];
        
        uint32_t eDMA_reserved0140[944];  /* 0x0140-0x0FFF */

/****************************************************************************/
/*       DMA2 Transfer Control Descriptor                                   */
/****************************************************************************/

        struct tcd_t {          /* for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
            /* 00 */
            vuint32_t SADDR;    /* Source Address */
            
            /* 04 */            /* Transfer Attributes */
            vuint16_t SMOD:5;   /* Source Address Modulo */
            vuint16_t SSIZE:3;  /* Source Data Transfer Size */
            vuint16_t DMOD:5;   /* Destination Address Modulo */
            vuint16_t DSIZE:3;  /* Destination Data Transfer Size */
            
            /* 06 */
            vint16_t SOFF;      /* Signed Source Address Offset */
            
            /* 08 */
            vuint32_t NBYTES;   /* Inner ("Minor") Byte Transfer Count */
            
            /* 0C */
            vint32_t SLAST;     /* Last Source Address Adjustment */
            
            /* 10 */
            vuint32_t DADDR;    /* Destination Address */
            
            /* 14 */
            vuint16_t CITERE_LINK:1;     /* Enable Channel-to-Channel        */
                                         /* Linking on Minor Loop Completion */
            vuint16_t CITER:15;          /* Current Major Iteration Count    */
            
            /* 16 */
            vint16_t DOFF;      /* Signed Destination Address Offset */
            
            /* 18 */
            vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or  */
                                /* Scatter/Gather Address (if E_SG = 1)     */
            
            /* 1C */
            vuint16_t BITERE_LINK:1;    /* Enable Channel-to-Channel           */
                                        /* Linking on Minor Loop Complete      */
            vuint16_t BITER:15;         /* Starting ("Major") Iteration Count */
            
            /* 1E */                    /* Channel Control/Status */
            vuint16_t BWC:2;            /* Bandwidth Control */
            vuint16_t MAJORLINKCH:6;    /* Link Channel Number */
            vuint16_t DONE:1;           /* Channel Done */
      vuint16_t ACTIVE:1;
            vuint16_t MAJORE_LINK:1;    /* Enable Channel-to-Channel Link */
            vuint16_t E_SG:1;           /* Enable Scatter/Gather Descriptor */
            vuint16_t D_REQ:1;          /* Disable IPD_REQ When Done */
            vuint16_t INT_HALF:1;       /* Interrupt on CITER = (BITER >> 1) */
            vuint16_t INT_MAJ:1;        /* Interrupt on Major Loop Completion */
            vuint16_t START:1;          /* Explicit Channel Start */
        } TCD[64];                      /* Transfer_Control_Descriptor */
    
    };

    struct EDMA_TCD_alt1_tag {  /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
    
        struct tcd_alt1_t {
            /* 00 */
            vuint32_t SADDR;    /* Source Address */
            
            /* 04 */            /* Transfer Attributes */
            vuint16_t SMOD:5;   /* Source Address Modulo */
            vuint16_t SSIZE:3;  /* Source Data Transfer Size */
            vuint16_t DMOD:5;   /* Destination Address Modulo */
            vuint16_t DSIZE:3;  /* Destination Data Transfer Size */
            
            /* 06 */
            vint16_t SOFF;      /* Signed Source Address Offset */
            
            /* 08 */
            vuint32_t NBYTES;   /* Inner ("Minor") Byte Transfer Count */
            
            /* 0C */
            vint32_t SLAST;     /* Last Source Address Adjustment */
            
            /* 10 */
            vuint32_t DADDR;    /* Destination Address */
            
            /* 14 */
            vuint16_t CITERE_LINK:1;     /* Enable Channel-to-Channel        */
                                         /* Linking on Minor Loop Completion */
            vuint16_t CITERLINKCH:6;     /* Link Channel Number              */
            vuint16_t CITER:9;           /* Current Major Iteration Count    */
            
            /* 16 */
            vint16_t DOFF;      /* Signed Destination Address Offset */
            
            /* 18 */
            vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or  */
                                /* Scatter/Gather Address (if E_SG = 1)     */
            
            /* 1C */
            vuint16_t BITERE_LINK:1;    /* Enable Channel-to-Channel           */
                                        /* Linking on Minor Loop Complete      */
            vuint16_t BITERLINKCH:6;    /* Link Channel Number                 */
            vuint16_t BITER:9;          /* Starting ("Major") Iteration Count  */
            
            /* 1E */                    /* Channel Control/Status */
            vuint16_t BWC:2;            /* Bandwidth Control */
            vuint16_t MAJORLINKCH:6;    /* Link Channel Number */
            vuint16_t DONE:1;           /* Channel Done */
            vuint16_t ACTIVE:1;         /* Channel Active */
            vuint16_t MAJORE_LINK:1;    /* Enable Channel-to-Channel Link */
            vuint16_t E_SG:1;           /* Enable Scatter/Gather Descriptor */
            vuint16_t D_REQ:1;          /* Disable IPD_REQ When Done */
            vuint16_t INT_HALF:1;       /* Interrupt on CITER = (BITER >> 1) */
            vuint16_t INT_MAJ:1;        /* Interrupt on Major Loop Completion */
            vuint16_t START:1;          /* Explicit Channel Start */
        } TCD[64];              /* transfer_control_descriptor */
    };

/****************************************************************************/
/*                          MODULE : INTC                                   */
/****************************************************************************/

    struct INTC_tag {
    
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:18;
                vuint32_t VTES_PRC1:1;
                vuint32_t:4;
                vuint32_t HVEN_PRC1:1;
                vuint32_t:2;
                vuint32_t VTES:1; /* Legacy naming. Refer to VTES_PRC0 in the reference manual */
                vuint32_t:4;
                vuint32_t HVEN:1; /* Legacy naming. Refer to HVEN_PRC0 in the reference manual */
            } B;
        } MCR;
        
        uint32_t INTC_reserved0004;  /* 0x0004-0x0007 */
        
        union {                  /* Current Priority Register (core 0). Refer to CPR_PRC0 in the reference manual. */
            vuint32_t R;
            struct {
                vuint32_t:28;
                vuint32_t PRI:4;
            } B;
        } CPR;
        
        union {                  /* Current Priority Register (core 1) */
            vuint32_t R;
            struct {
                vuint32_t:28;
                vuint32_t PRI:4;
            } B;
        } CPR_PRC1;
        
        union {                /* Interrupt Acknowledge Register (core 0). Refer to IACKR_PRC0 in the reference manual. */
            vuint32_t R;
            struct {
                vuint32_t VTBA:21;
                vuint32_t INTVEC:9;
                vuint32_t:2;
            } B;
        } IACKR;
        
        union {                /* Interrupt Acknowledge Register (core 1). */
            vuint32_t R;
            struct {
                vuint32_t VTBA:21;
                vuint32_t INTVEC:9;
                vuint32_t:2;
            } B;
        } IACKR_PRC1;
        
        union {                 /* End of Interrupt Register (core 0). Refer to EOIR_PRC0 in the reference manual. */
            vuint32_t R;
            struct {
                vuint32_t EOIR:32;
            } B;
        } EOIR;
        
        union {                 /* End of Interrupt Register (core 1). */
            vuint32_t R;
            struct {
                vuint32_t EOIR:32;
            } B;
        } EOIR_PRC1;
        
        union {             /* Software Set/Clear Interruput Register */
            vuint8_t R;
            struct {
                vuint8_t:6;
                vuint8_t SET:1;
                vuint8_t CLR:1;
            } B;
        } SSCIR[8];
        
        uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */
        
        union {             /* Priority Select Registers */
            vuint8_t R;
            struct {
                vuint8_t PRC_SEL:2;
                vuint8_t:2;
                vuint8_t PRI:4;
            } B;
        } PSR[512];
        
        uint16_t INTC_reserved0240[7904]; /* 0x0240-0x3FFF */
    
    };
    
/****************************************************************************/
/*                          MODULE : EQADC                                  */
/****************************************************************************/

    struct EQADC_tag {
    
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:24;
                vuint32_t ICEA0:1;
                vuint32_t ICEA1:1;
                vuint32_t:1;
                vuint32_t:2;
                vuint32_t:1;
                vuint32_t DBG:2;
            } B;
        } MCR;
        
        uint32_t eQADC_reserved0004;  /* 0x0004-0x0007 */
        
        uint32_t eQADC_reserved0008;  /* 0x0008-0x000B */
        
        union {                /* External Trigger Digital Filter Register */
            vuint32_t R;
            struct {
                vuint32_t:28;
                vuint32_t DFL:4;
            } B;
        } ETDFR;
        
        union {              /* CFIFO Push Registers */
            vuint32_t R;
            struct {
                vuint32_t CFPUSH:32;
            } B;
        } CFPR[6];
        
        uint32_t eQADC_reserved0028[2];  /* 0x0028-0x002F */
        
        union {              /* Result FIFO Pop Registers */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t RFPOP:16;
            } B;
        } RFPR[6];
        
        uint32_t eQADC_reserved0048[2];  /* 0x0048-0x004F */
        
        union {              /* CFIFO Control Registers */
            vuint16_t R;
            struct {
                vuint16_t:3;
                vuint16_t CFEEE:1; /* ONLY valid for CFCR[0] */
                vuint16_t STRME:1; /* ONLY valid for CFCR[0] */
                vuint16_t SSE:1;
                vuint16_t CFINV:1;
                vuint16_t:1;
                vuint16_t MODE:4;
                vuint16_t AMODE:4; /* ONLY valid for CFCR[0] */
            } B;
        } CFCR[6];
        
        uint32_t eQADC_reserved005C;  /* 0x005C-0x005F */
        
        union {              /* Interrupt and DMA Control Registers */
            vuint16_t R;
            struct {
                vuint16_t NCIE:1;
                vuint16_t TORIE:1;
                vuint16_t PIE:1;
                vuint16_t EOQIE:1;
                vuint16_t CFUIE:1;
                vuint16_t:1;
                vuint16_t CFFE:1;
                vuint16_t CFFS:1;
                vuint16_t:4;
                vuint16_t RFOIE:1;
                vuint16_t:1;
                vuint16_t RFDE:1;
                vuint16_t RFDS:1;
            } B;
        } IDCR[6];
        
        uint32_t eQADC_reserved006C;  /* 0x006C-0x006F */
        
        union {              /* FIFO and Interrupt Status Registers */
            vuint32_t R;
            struct {
                vuint32_t NCF:1;
                vuint32_t TORF:1;
                vuint32_t PF:1;
                vuint32_t EOQF:1;
                vuint32_t CFUF:1;
                vuint32_t SSS:1;
                vuint32_t CFFF:1;
                vuint32_t:5;
                vuint32_t RFOF:1;
                vuint32_t:1;
                vuint32_t RFDF:1;
                vuint32_t:1;
                vuint32_t CFCTR:4;
                vuint32_t TNXTPTR:4;
                vuint32_t RFCTR:4;
                vuint32_t POPNXTPTR:4;
            } B;
        } FISR[6];
        
        uint32_t eQADC_reserved0088[2];  /* 0x0088-0x008F */
        
        union {             /* CFIFO Transfer Counter Registers */
            vuint16_t R;
            struct {
                vuint16_t:5;
                vuint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */
            } B;
        } CFTCR[6];
        
        uint32_t eQADC_reserved009C[1];  /* 0x009F */
        
        union {               /* CFIFO Status Register 0 */
            vuint32_t R;
            struct {
                vuint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */
                vuint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */
                vuint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */
                vuint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */
                vuint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */
                vuint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */
                vuint32_t:5;
                vuint32_t LCFTCB0:4;
                vuint32_t TC_LCFTCB0:11;
            } B;
        } CFSSR0;
        
        union {               /* CFIFO Status Register 1 */
            vuint32_t R;
            struct {
                vuint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */
                vuint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */
                vuint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */
                vuint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */
                vuint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */
                vuint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */
                vuint32_t:5;
                vuint32_t LCFTCB1:4;
                vuint32_t TC_LCFTCB1:11;
            } B;
        } CFSSR1;
        
        union {               /* CFIFO Status Register 2 */
            vuint32_t R;      /* Deprecated.  This register is no longer documented or supported. */
            struct {
                vuint32_t CFS0:2;
                vuint32_t CFS1:2;
                vuint32_t CFS2:2;
                vuint32_t CFS3:2;
                vuint32_t CFS4:2;
                vuint32_t CFS5:2;
                vuint32_t:4;
                vuint32_t ECBNI:1;
                vuint32_t LCFTSSI:4;
                vuint32_t TC_LCFTSSI:11;
            } B;
        } CFSSR2;
        
        union {                 /* CFIFO Status Register */
            vuint32_t R;
            struct {
                vuint32_t CFS0:2;
                vuint32_t CFS1:2;
                vuint32_t CFS2:2;
                vuint32_t CFS3:2;
                vuint32_t CFS4:2;
                vuint32_t CFS5:2;
                vuint32_t:20;
            } B;
        } CFSR;
        
        uint32_t eQADC_reserved00B0;  /* 0x00B0-0x00B3 */
        uint32_t eQADC_reserved00B4;  /* 0x00B4-0x00B7 */
        uint32_t eQADC_reserved00B8;  /* 0x00B8-0x00BB */

        uint32_t eQADC_reserved00BC[5];  /* 0x00BC-0x00CF */
        
        union {                 /* EQADC Red Line Client Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t REDBS2:4;
                vuint32_t SRV2:4;
                vuint32_t REDBS1:4;
                vuint32_t SRV1:4;
            } B;
        } REDLCCR;

        uint32_t eQADC_reserved00D4[11];  /* 0x00D4-0x00FF */
        
        struct {
            union {
                vuint32_t R;
                struct {
                    vuint32_t CFIFO_DATA:32;
                } B;
            } R[4];
            
            union {             /* NOTE: ER registers valid only for CF[0]. */
                vuint32_t R;
                struct {
                    vuint32_t CFIFO_EDATA:32;
                } B;
            } ER[4];

            uint32_t eQADC_cf_reserved020[8];  /* CFIFO offset 0x020-0x03F */
            
        } CF[6];
        
        uint32_t eQADC_reserved0280[32];  /* 0x0280-0x02FF */
        
        struct {
            union {
                vuint32_t R;
                struct {
                    vuint32_t RFIFO_DATA:32;
                } B;
            } R[4];
            
            uint32_t eQADC_rf_reserved010[12];  /* RFIFO offset 0x010-0x03F */
            
        } RF[6];
    
        uint32_t eQADC_reserved0480[3808];  /* 0x0480-0x3FFF */
    };

/****************************************************************************/
/*                          MODULE : Decimation Filter                      */
/****************************************************************************/

    struct DECFIL_tag {
    
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t MDIS:1;
                vuint32_t FREN:1;
                vuint32_t :1;
                vuint32_t FRZ:1;
                vuint32_t SRES:1;
                vuint32_t CASCD:2;
                vuint32_t IDEN:1;
                vuint32_t ODEN:1;
                vuint32_t ERREN:1;
                vuint32_t :1;
                vuint32_t FTYPE:2;
                vuint32_t :1;
                vuint32_t SCAL:2;
                vuint32_t IDIS:1;
                vuint32_t SAT:1;
                vuint32_t IO_SEL:2;

                vuint32_t DEC_RATE:4;
                vuint32_t SDIE:1;
                vuint32_t DSEL:1;
                vuint32_t IBIE:1;
                vuint32_t OBIE:1;
                vuint32_t EDME:1;
                vuint32_t TORE:1;
                vuint32_t TMODE:2;
            } B;
        } MCR;
        
        union {                  /* Module Status Register */
            vuint32_t R;
            struct {
                vuint32_t BSY:1;
                vuint32_t:1;
                vuint32_t DEC_COUNTER:4;
                vuint32_t IDFC:1;
                vuint32_t ODFC:1;
                vuint32_t:1;
                vuint32_t IBIC:1;
                vuint32_t OBIC:1;
                vuint32_t:1;
                vuint32_t DIVRC:1;
                vuint32_t OVFC:1;
                vuint32_t OVRC:1;
                vuint32_t IVRC:1;
                vuint32_t:6;
                vuint32_t IDF:1;
                vuint32_t ODF:1;
                vuint32_t:1;
                vuint32_t IBIF:1;
                vuint32_t OBIF:1;
                vuint32_t:1;
                vuint32_t DIVR:1;
                vuint32_t OVF:1;
                vuint32_t OVR:1;
                vuint32_t IVR:1;
            } B;
        } SR;
        
        union {                  /* Module Extended Config Register */
            vuint32_t R;
            struct {
                vuint32_t SDMAE:1;
                vuint32_t SSIG:1;
                vuint32_t SSAT:1;
                vuint32_t SCSAT:1;
                vuint32_t:10;
                vuint32_t SRQ:1;
                vuint32_t SZR0:1;
                vuint32_t SISEL:1;
                vuint32_t:1;
                vuint32_t SZROSEL:2;
                vuint32_t:2;
                vuint32_t SHLTSEL:2;
                vuint32_t:1;
                vuint32_t SRQSEL:3;
                vuint32_t:2;
                vuint32_t SENSEL:2;
            } B;
        } MXCR;
        
        union {                  /* Module Extended Status Register */
            vuint32_t R;
            struct {
                vuint32_t:7;
                vuint32_t SDFC:1;
                vuint32_t:2;
                vuint32_t SSEC:1;
                vuint32_t SCEC:1;
                vuint32_t:1;
                vuint32_t SSOVFC:1;
                vuint32_t SCOVFC:1;
                vuint32_t SVRC:1;
                vuint32_t:7;
                vuint32_t SDF:1;
                vuint32_t:2;
                vuint32_t SSE:1;
                vuint32_t SCE:1;
                vuint32_t:1;
                vuint32_t SSOVF:1;
                vuint32_t SCOVF:1;
                vuint32_t SVR:1;
            } B;
        } MXSR;
        
        union {                  /* Interface Input Buffer Register */
            vuint32_t R;
            struct {
                vuint32_t:3;
                vuint32_t OSEL:1;
                vuint32_t INTAG:4;
                vuint32_t:6;
                vuint32_t PREFILL:1;
                vuint32_t FLUSH:1;
                vuint32_t INPBUF:16;
            } B;
        } IB;
        
        union {                  /* Interface Output Buffer Register */
            vuint32_t R;
            struct {
                vuint32_t:11;
                vuint32_t OSEL:1;
                vuint32_t OUTTAG:4;
                vuint32_t OUTBUF:16;
            } B;
        } OB;
        
        uint32_t DFILT_reserved0018[2];  /* 0x0018-0x001F */
        
        union {                  /* Coefficient n Register */
            vint32_t R;
            struct {
                vint32_t:8;
                vint32_t COEF:24;
            } B;
        } COEF[9];
        
        uint32_t DFILT_reserved0044[13];  /* 0x0044-0x0077 */
        
        union {                  /* TAP n Register */
            vint32_t R;
            struct {
                vint32_t:8;
                vint32_t TAP:24;
            } B;
        } TAP[8];
        
        uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */
        
        union {                  /* EDID Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t SAMP_DATA:16;
            } B;
        } EDID;
        
        uint32_t DFILT_reserved00D4[3]; /* 0x00D4-0x00DF */
        
        union {                  /* FINTVAL Register */
            vuint32_t R;
            struct {
                vuint32_t SUM_VALUE:32;
            } B;
        } FINTVAL;
        
        union {                  /* FINTCNT Register */
            vuint32_t R;
            struct {
                vuint32_t COUNT:32;
            } B;
        } FINTCNT;
        
        union {                  /* CINTVAL Register */
            vuint32_t R;
            struct {
                vuint32_t SUM_VALUE:32;
            } B;
        } CINTVAL;
        
        union {                  /* CINTCNT Register */
            vuint32_t R;
            struct {
                vuint32_t COUNT:32;
            } B;
        } CINTCNT;
        
        
    
    };

/****************************************************************************/
/*                          MODULE : DSPI                                   */
/****************************************************************************/

    struct DSPI_tag {
    
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t MSTR:1;
                vuint32_t CONT_SCKE:1;
                vuint32_t DCONF:2;
                vuint32_t FRZ:1;
                vuint32_t MTFE:1;
                vuint32_t PCSSE:1;
                vuint32_t ROOE:1;
                vuint32_t PCSIS7:1;     /* Reserved */
                vuint32_t PCSIS6:1;     /* Reserved */
                vuint32_t PCSIS5:1;
                vuint32_t PCSIS4:1;
                vuint32_t PCSIS3:1;
                vuint32_t PCSIS2:1;
                vuint32_t PCSIS1:1;
                vuint32_t PCSIS0:1;
                vuint32_t DOZE:1;
                vuint32_t MDIS:1;
                vuint32_t DIS_TXF:1;
                vuint32_t DIS_RXF:1;
                vuint32_t CLR_TXF:1;
                vuint32_t CLR_RXF:1;
                vuint32_t SMPL_PT:2;
                vuint32_t:6;
                vuint32_t PES:1;
                vuint32_t HALT:1;
            } B;
        } MCR;
        
        uint32_t DSPI_reserved0004;  /* 0x0004-0x0007 */
        
        union {              /* Transfer Count Register */
            vuint32_t R;
            struct {
                vuint32_t TCNT:16;
                vuint32_t:16;
            } B;
        } TCR;
        
        union {              /* Clock and Transfer Attributes Registers */
            vuint32_t R;
            struct {                    /* Bit definitions for Master Mode */
                vuint32_t DBR:1;
                vuint32_t FMSZ:4;
                vuint32_t CPOL:1;
                vuint32_t CPHA:1;
                vuint32_t LSBFE:1;
                vuint32_t PCSSCK:2;
                vuint32_t PASC:2;
                vuint32_t PDT:2;
                vuint32_t PBR:2;
                vuint32_t CSSCK:4;
                vuint32_t ASC:4;
                vuint32_t DT:4;
                vuint32_t BR:4;
            } B;
            struct {                    /* Bit definitions for Slave Mode */
                vuint32_t FMSZ:5;
                vuint32_t CPOL:1;
                vuint32_t CPHA:1;
                vuint32_t PE:1;
                vuint32_t PP:1;
                vuint32_t:23;
            } B_SLAVE;
        } CTAR[8];
        
        union {                   /* Status Register */
            vuint32_t R;
            struct {
                vuint32_t TCF:1;
                vuint32_t TXRXS:1;
                vuint32_t:1;
                vuint32_t EOQF:1;
                vuint32_t TFUF:1;
                vuint32_t:1;
                vuint32_t TFFF:1;
                vuint32_t:2;
                vuint32_t DPEF:1;
                vuint32_t SPEF:1;
                vuint32_t DDIF:1;
                vuint32_t RFOF:1;
                vuint32_t:1;
                vuint32_t RFDF:1;
                vuint32_t:1;
                vuint32_t TXCTR:4;
                vuint32_t TXNXTPTR:4;
                vuint32_t RXCTR:4;
                vuint32_t POPNXTPTR:4;
            } B;
        } SR;
        
        union {                 /* DMA/Interrupt Request Select and Enable Register */
            vuint32_t R;
            struct {
                vuint32_t TCFRE:1;
                vuint32_t:2;
                vuint32_t EOQFRE:1;
                vuint32_t TFUFRE:1;
                vuint32_t:1;
                vuint32_t TFFFRE:1;
                vuint32_t TFFFDIRS:1;
                vuint32_t:1;
                vuint32_t DPEFRE:1;
                vuint32_t SPEFRE:1;
                vuint32_t DDIFRE:1;
                vuint32_t RFOFRE:1;
                vuint32_t:1;
                vuint32_t RFDFRE:1;
                vuint32_t RFDFDIRS:1;
                vuint32_t:16;
            } B;
        } RSER;
        
        union {                /* PUSH TX FIFO Register */
            vuint32_t R;
            struct {                    /* Bit definitions for Master Mode */
                vuint32_t CONT:1;
                vuint32_t CTAS:3;
                vuint32_t EOQ:1;
                vuint32_t CTCNT:1;
                vuint32_t PE:1;
                vuint32_t PP:1;
                vuint32_t PCS7:1;     /* Reserved */
                vuint32_t PCS6:1;     /* Reserved */
                vuint32_t PCS5:1;
                vuint32_t PCS4:1;
                vuint32_t PCS3:1;
                vuint32_t PCS2:1;
                vuint32_t PCS1:1;
                vuint32_t PCS0:1;
                vuint32_t TXDATA:16;
            } B;
            struct {                    /* Bit definitions for Slave Mode */
                vuint32_t TXDATA:32;
            } B_SLAVE;
        } PUSHR;
        
        union {                 /* POP RX FIFO Register */
            vuint32_t R;
            struct {
                vuint32_t RXDATA:32;
            } B;
        } POPR;
        
        union {              /* Transmit FIFO Registers */
            vuint32_t R;
            struct {                    /* Bit definitions for Master Mode */
                vuint32_t TXCMD:16;
                vuint32_t TXDATA:16;
            } B;
            struct {                    /* Bit definitions for Slave Mode */
                vuint32_t TXDATA:32;
            } B_SLAVE;
        } TXFR[4];
        
        uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */
        
        union {              /* Receive FIFO Registers */
            vuint32_t R;
            struct {
                vuint32_t RXDATA:32;
            } B;
        } RXFR[4];
        
        uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */
        
        union {                /* DSI Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t MTOE:1;
                vuint32_t FMSZ4:1;
                vuint32_t MTOCNT:6;
                vuint32_t:3;
                vuint32_t TSBC:1;
                vuint32_t TXSS:1;
                vuint32_t TPOL:1;
                vuint32_t TRRE:1;
                vuint32_t CID:1;
                vuint32_t DCONT:1;
                vuint32_t DSICTAS:3;
                vuint32_t:4;
                vuint32_t DPCS7:1;      /* Reserved */
                vuint32_t DPCS6:1;      /* Reserved */
                vuint32_t DPCS5:1;
                vuint32_t DPCS4:1;
                vuint32_t DPCS3:1;
                vuint32_t DPCS2:1;
                vuint32_t DPCS1:1;
                vuint32_t DPCS0:1;
            } B;
        } DSICR;
        
        union {                  /* DSI Serialization Data Register */
            vuint32_t R;
            struct {
                vuint32_t SER_DATA:32;
            } B;
        } SDR;
        
        union {                 /* DSI Alternate Serialization Data Register */
            vuint32_t R;
            struct {
                vuint32_t ASER_DATA:32;
            } B;
        } ASDR;
        
        union {                /* DSI Transmit Comparison Register */
            vuint32_t R;
            struct {
                vuint32_t COMP_DATA:32;
            } B;
        } COMPR;
        
        union {                  /* DSI deserialization Data Register */
            vuint32_t R;
            struct {
                vuint32_t DESER_DATA:32;
            } B;
        } DDR;
        
        union {                 /* DSI Configuration Register 1 */
            vuint32_t R;
            struct {
                vuint32_t:3;
                vuint32_t TSBCNT:5;
                vuint32_t:6;
                vuint32_t DSE1:1;
                vuint32_t DSE0:1;
                vuint32_t:8;
                vuint32_t DPCS1_7:1;      /* Reserved */
                vuint32_t DPCS1_6:1;      /* Reserved */
                vuint32_t DPCS1_5:1;
                vuint32_t DPCS1_4:1;
                vuint32_t DPCS1_3:1;
                vuint32_t DPCS1_2:1;
                vuint32_t DPCS1_1:1;
                vuint32_t DPCS1_0:1;
            } B;
        } DSICR1;    

        union {                  /* DSI Serialization Source Select Register */
            vuint32_t R;
            struct {
                vuint32_t SS:32;
            } B;
        } SSR;    

        union {                  /* DSI Parallel Input Select Register 0 */
            vuint32_t R;
            struct {
                vint32_t IPS24:4;
                vint32_t IPS25:4;
                vint32_t IPS26:4;
                vint32_t IPS27:4;
                vint32_t IPS28:4;
                vint32_t IPS29:4;
                vint32_t IPS30:4;
                vint32_t IPS31:4;
            } B;
        } PISR0;    

        union {                  /* DSI Parallel Input Select Register 1 */                       
            vuint32_t R;
            struct {
                vint32_t IPS16:4;
                vint32_t IPS17:4;
                vint32_t IPS18:4;
                vint32_t IPS19:4;
                vint32_t IPS20:4;
                vint32_t IPS21:4;
                vint32_t IPS22:4;
                vint32_t IPS23:4;
            } B;
        } PISR1;    

        union {                  /* DSI Parallel Input Select Register 2 */
            vuint32_t R;
            struct {
                vint32_t IPS8:4;
                vint32_t IPS9:4;
                vint32_t IPS10:4;
                vint32_t IPS11:4;
                vint32_t IPS12:4;
                vint32_t IPS13:4;
                vint32_t IPS14:4;
                vint32_t IPS15:4;
            } B;
        } PISR2;    

        union {                  /* DSI Parallel Input Select Register 3 */
            vuint32_t R;
            struct {
                vint32_t IPS0:4;
                vint32_t IPS1:4;
                vint32_t IPS2:4;
                vint32_t IPS3:4;
                vint32_t IPS4:4;
                vint32_t IPS5:4;
                vint32_t IPS6:4;
                vint32_t IPS7:4;
            } B;
        } PISR3;    

        union {                  /* DSI Deserialized Data Interrupt Mask Register */
            vuint32_t R;
            struct {
                vuint32_t MASK:32;
            } B;
        } DIMR;    

        union {                  /* DSI Deserialized Data Polarity Interrupt Register */
            vuint32_t R;
            struct {
                vuint32_t DP:32;
            } B;
        } DPIR;    

        uint32_t DSPI_reserved00F0[4036];  /* 0x00F0-0x3FFF */
    
    };

/****************************************************************************/
/*                          MODULE : eSCI                                   */
/****************************************************************************/

    struct ESCI_tag {
        union {                  /* Control Register 1 */
            vuint32_t R;         /* Note: In the reference manual this is   */
            struct {             /* documented as two 16-bit registers:     */
                vuint32_t:3;     /* eSCI_BRR and eSCI_CR1.                  */
                vuint32_t SBR:13;
                vuint32_t LOOPS:1;
                vuint32_t:1;
                vuint32_t RSRC:1;
                vuint32_t M:1;
                vuint32_t WAKE:1;
                vuint32_t:1;
                vuint32_t PE:1;
                vuint32_t PT:1;
                vuint32_t TIE:1;
                vuint32_t TCIE:1;
                vuint32_t RIE:1;
                vuint32_t ILIE:1;
                vuint32_t TE:1;
                vuint32_t RE:1;
                vuint32_t RWU:1;
                vuint32_t SBK:1;
            } B;
        } CR1;
        
        union {                  /* Control Register 2 */
            vuint16_t R;
            struct {
                vuint16_t MDIS:1;
                vuint16_t FBR:1;
                vuint16_t BSTP:1;
                vuint16_t IEBERR:1; /* Legacy name: Refer to BERRIE in the reference manual */
                vuint16_t RXDMA:1;
                vuint16_t TXDMA:1;
                vuint16_t BRK13:1;  /* Legacy name: Refer to BRCL in the reference manual */
                vuint16_t TXDIR:1;
                vuint16_t BESM13:1; /* Legacy name: Refer to BESM in the reference manual */
                vuint16_t SBSTP:1;  /* Legacy name: Refer to BESTP in the reference manual */
                vuint16_t RXPOL:1;
                vuint16_t PMSK:1;
                vuint16_t ORIE:1;
                vuint16_t NFIE:1;
                vuint16_t FEIE:1;
                vuint16_t PFIE:1;
            } B;
        } CR2;
        
        union {                   /* Data Register */
            vuint16_t R;

            struct {
                vuint16_t RN:1;
                vuint16_t TN:1;
                vuint16_t ERR:1;
                vuint16_t:1;
                vuint16_t RD_11:4; 
                vuint16_t D:8;
            } B;
        } DR; /* Legacy naming - refer to SDR in Reference Manual */

        union {                   /* Status Register */
            vuint32_t R;
            struct {
                vuint32_t TDRE:1;
                vuint32_t TC:1;
                vuint32_t RDRF:1;
                vuint32_t IDLE:1;
                vuint32_t OR:1;
                vuint32_t NF:1;
                vuint32_t FE:1;
                vuint32_t PF:1;
                vuint32_t:2;
                vuint32_t DACT:1;
                vuint32_t BERR:1;
                vuint32_t WACT:1;
                vuint32_t LACT:1;
                vuint32_t TACT:1;
                vuint32_t RAF:1;   /* Legacy name: Refer to RACT in the reference manual */
                vuint32_t RXRDY:1;
                vuint32_t TXRDY:1;
                vuint32_t LWAKE:1;
                vuint32_t STO:1;
                vuint32_t PBERR:1;
                vuint32_t CERR:1;
                vuint32_t CKERR:1;
                vuint32_t FRC:1;
                vuint32_t:6;
                vuint32_t UREQ:1;
                vuint32_t OVFL:1;
            } B;
        } SR;  /* Legacy naming - refer to IFSR1 and IFSR2 in Reference Manual */
        
        union {                  /* LIN Control Register */
            vuint32_t R;
            struct {
                vuint32_t LRES:1;
                vuint32_t WU:1;
                vuint32_t WUD0:1;
                vuint32_t WUD1:1;
                vuint32_t :2;
                vuint32_t PRTY:1;
                vuint32_t LIN:1;
                vuint32_t RXIE:1;
                vuint32_t TXIE:1;
                vuint32_t WUIE:1;
                vuint32_t STIE:1;
                vuint32_t PBIE:1;
                vuint32_t CIE:1;
                vuint32_t CKIE:1;
                vuint32_t FCIE:1;
                vuint32_t:6;
                vuint32_t UQIE:1;
                vuint32_t OFIE:1;
                vuint32_t:8;
            } B;
        } LCR;
        
        union {                  /* LIN Transmit Register */
            vuint8_t R;
        } LTR;
        
        vuint8_t eSCI_reserved0011[3];  /* 0x0011-0x0013 */
        
        union {                  /* LIN Recieve Register */
            vuint8_t R;
            struct {
                vuint8_t D:8;
            } B;
        } LRR;
        
        vuint8_t eSCI_reserved0015[3];  /* 0x0015-0x0017 */
        
        union {                  /* LIN CRC Polynom Register  */
            vuint16_t R;
            struct {
                vuint16_t P:16;
            } B;
        } LPR;
        
        union {                  /* Control Register 3 */
            vuint16_t R;
            struct {
                vuint16_t:3;
                vuint16_t:1;
                vuint16_t EROE:1;
                vuint16_t ERFE:1;
                vuint16_t ERPE:1;
                vuint16_t M2:1;
                vuint16_t:8;
            } B;
        } CR3;

        uint32_t eSCI_reserved001C; /* 0x001C-0x001F */
        
        uint32_t eSCI_reserved0020[4088];  /* 0x0020-0x3FFF */
    
    };

/****************************************************************************/
/*                          MODULE : FlexCAN                                */
/****************************************************************************/
  struct canbuf_t {
            union {
                vuint32_t R;
                struct {
                    vuint32_t:4;
                    vuint32_t CODE:4;
                    vuint32_t:1;
                    vuint32_t SRR:1;
                    vuint32_t IDE:1;
                    vuint32_t RTR:1;
                    vuint32_t LENGTH:4;
                    vuint32_t TIMESTAMP:16;
                } B;
            } CS;
            
            union {
                vuint32_t R;
                struct {
                    vuint32_t PRIO:3;
                    vuint32_t STD_ID:11;
                    vuint32_t EXT_ID:18;
                } B;
            } ID;
            
            union {
                vuint8_t B[8];  /* Data buffer in Bytes (8 bits) */
                vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
                vuint32_t W[2]; /* Data buffer in words (32 bits) */
                vuint32_t R[2]; /* Data buffer in words (32 bits) */
            } DATA;
            
        };
    
    struct FLEXCAN_RXFIFO_t {
        union {
            vuint32_t R;
            struct {
                vuint32_t:9;
                vuint32_t SRR:1;
                vuint32_t IDE:1;
                vuint32_t RTR:1;
                vuint32_t LENGTH:4;
                vuint32_t TIMESTAMP:16;
            } B;
        } CS;

        union {
            vuint32_t R;
            struct {
                vuint32_t:3;
                vuint32_t STD_ID:11;
                vuint32_t EXT_ID:18;
            } B;
        } ID;

        union {
            vuint8_t B[8];      /* Data buffer in Bytes (8 bits) */
            vuint16_t H[4];     /* Data buffer in Half-words (16 bits) */
            vuint32_t W[2];     /* Data buffer in words (32 bits) */
            vuint32_t R[2];     /* Data buffer in words (32 bits) */
        } DATA;

        uint32_t FLEXCAN_RXFIFO_reserved[20];   /* {0x00E0-0x0090}/0x4 = 0x14 */

        union {
            vuint32_t R;
        } IDTABLE[8];

    };                          /* end of FLEXCAN_RXFIFO_t */
  
    struct FLEXCAN3_tag {
        union {                  /* Module Configuration Register */
            vuint32_t R;
            struct {
                vuint32_t MDIS:1;
                vuint32_t FRZ:1;
                vuint32_t FEN:1;
                vuint32_t HALT:1;
                vuint32_t NOTRDY:1;
                vuint32_t:1;
                vuint32_t SOFTRST:1;
                vuint32_t FRZACK:1;
                vuint32_t SUPV:1;
                vuint32_t:1;
                vuint32_t WRNEN:1;
                vuint32_t MDISACK:1; /* Legacy name: Refer to LPMACK in the reference manual */
                vuint32_t:1;
                vuint32_t DOZE:1;
                vuint32_t SRXDIS:1;
                vuint32_t BCC:1;   /* Legacy name: Refer to IRMQ in the reference manual */
                vuint32_t:2;
                vuint32_t LPRIO_EN:1;
                vuint32_t AEN:1;
                vuint32_t:2;
                vuint32_t IDAM:2;
                vuint32_t:1;
                vuint32_t MAXMB:7;
            } B;
        } MCR;
        
        union {                   /* Control Register */
            vuint32_t R;
            struct {
                vuint32_t PRESDIV:8;
                vuint32_t RJW:2;
                vuint32_t PSEG1:3;
                vuint32_t PSEG2:3;
                vuint32_t BOFFMSK:1;
                vuint32_t ERRMSK:1;
                vuint32_t CLKSRC:1;
                vuint32_t LPB:1;
                vuint32_t TWRNMSK:1;
                vuint32_t RWRNMSK:1;
                vuint32_t:2;
                vuint32_t SMP:1;
                vuint32_t BOFFREC:1;
                vuint32_t TSYN:1;
                vuint32_t LBUF:1;
                vuint32_t LOM:1;
                vuint32_t PROPSEG:3;
            } B;
        } CR; /* Legacy naming - refer to CTRL in Reference Manual */
        
        union {                /* Free Running Timer */
            vuint32_t R;
        } TIMER;
        
        int32_t FLEXCAN_reserved000C;  /* 0x000C-0x000F */
        
        union {              /* RX Global Mask */
            vuint32_t R;
            struct {
                vuint32_t MI31:1;
                vuint32_t MI30:1;
                vuint32_t MI29:1;
                vuint32_t MI28:1;
                vuint32_t MI27:1;
                vuint32_t MI26:1;
                vuint32_t MI25:1;
                vuint32_t MI24:1;
                vuint32_t MI23:1;
                vuint32_t MI22:1;
                vuint32_t MI21:1;
                vuint32_t MI20:1;
                vuint32_t MI19:1;
                vuint32_t MI18:1;
                vuint32_t MI17:1;
                vuint32_t MI16:1;
                vuint32_t MI15:1;
                vuint32_t MI14:1;
                vuint32_t MI13:1;
                vuint32_t MI12:1;
                vuint32_t MI11:1;
                vuint32_t MI10:1;
                vuint32_t MI9:1;
                vuint32_t MI8:1;
                vuint32_t MI7:1;
                vuint32_t MI6:1;
                vuint32_t MI5:1;
                vuint32_t MI4:1;
                vuint32_t MI3:1;
                vuint32_t MI2:1;
                vuint32_t MI1:1;
                vuint32_t MI0:1;
            } B;
        } RXGMASK; /* Legacy naming - refer to RXMGMASK in Reference Manual */
        
        union {             /* RX 14 Mask */
            vuint32_t R;
            struct {
                vuint32_t MI31:1;
                vuint32_t MI30:1;
                vuint32_t MI29:1;
                vuint32_t MI28:1;
                vuint32_t MI27:1;
                vuint32_t MI26:1;
                vuint32_t MI25:1;
                vuint32_t MI24:1;
                vuint32_t MI23:1;
                vuint32_t MI22:1;
                vuint32_t MI21:1;
                vuint32_t MI20:1;
                vuint32_t MI19:1;
                vuint32_t MI18:1;
                vuint32_t MI17:1;
                vuint32_t MI16:1;
                vuint32_t MI15:1;
                vuint32_t MI14:1;
                vuint32_t MI13:1;
                vuint32_t MI12:1;
                vuint32_t MI11:1;
                vuint32_t MI10:1;
                vuint32_t MI9:1;
                vuint32_t MI8:1;
                vuint32_t MI7:1;
                vuint32_t MI6:1;
                vuint32_t MI5:1;
                vuint32_t MI4:1;
                vuint32_t MI3:1;
                vuint32_t MI2:1;
                vuint32_t MI1:1;
                vuint32_t MI0:1;
            } B;
        } RX14MASK;
        
        union {             /* RX 15 Mask */
            vuint32_t R;
            struct {
                vuint32_t MI31:1;
                vuint32_t MI30:1;
                vuint32_t MI29:1;
                vuint32_t MI28:1;
                vuint32_t MI27:1;
                vuint32_t MI26:1;
                vuint32_t MI25:1;
                vuint32_t MI24:1;
                vuint32_t MI23:1;
                vuint32_t MI22:1;
                vuint32_t MI21:1;
                vuint32_t MI20:1;
                vuint32_t MI19:1;
                vuint32_t MI18:1;
                vuint32_t MI17:1;
                vuint32_t MI16:1;
                vuint32_t MI15:1;
                vuint32_t MI14:1;
                vuint32_t MI13:1;
                vuint32_t MI12:1;
                vuint32_t MI11:1;
                vuint32_t MI10:1;
                vuint32_t MI9:1;
                vuint32_t MI8:1;
                vuint32_t MI7:1;
                vuint32_t MI6:1;
                vuint32_t MI5:1;
                vuint32_t MI4:1;
                vuint32_t MI3:1;
                vuint32_t MI2:1;
                vuint32_t MI1:1;
                vuint32_t MI0:1;
            } B;
        } RX15MASK;
        
        union {                  /* Error Counter Register */
            vuint32_t R;
            struct {
                vuint32_t:16;
                vuint32_t RXECNT:8; /* Legacy naming - refer to RXERRCNT in Reference Manual */
                vuint32_t TXECNT:8; /* Legacy naming - refer to TXERRCNT in Reference Manual */
            } B;
        } ECR;
        
        union {                  /* Error and Status Register */
            vuint32_t R;
            struct {
                vuint32_t:13;
                vuint32_t SYNCH:1;
                vuint32_t TWRNINT:1;
                vuint32_t RWRNINT:1;
                vuint32_t BIT1ERR:1;
                vuint32_t BIT0ERR:1;
                vuint32_t ACKERR:1;
                vuint32_t CRCERR:1;
                vuint32_t FRMERR:1;
                vuint32_t STFERR:1;
                vuint32_t TXWRN:1;
                vuint32_t RXWRN:1;
                vuint32_t IDLE:1;
                vuint32_t TX:1;
                vuint32_t FLTCONF:2;
                vuint32_t RX:1;
                vuint32_t BOFFINT:1;
                vuint32_t ERRINT:1;
                vuint32_t:1;
            } B;
        } ESR; /* Legacy naming - refer to ESR1 in Reference Manual */
        
        union {                 /* Interruput Masks Register */
            vuint32_t R;
            struct {
                vuint32_t BUF63M:1;
                vuint32_t BUF62M:1;
                vuint32_t BUF61M:1;
                vuint32_t BUF60M:1;
                vuint32_t BUF59M:1;
                vuint32_t BUF58M:1;
                vuint32_t BUF57M:1;
                vuint32_t BUF56M:1;
                vuint32_t BUF55M:1;
                vuint32_t BUF54M:1;
                vuint32_t BUF53M:1;
                vuint32_t BUF52M:1;
                vuint32_t BUF51M:1;
                vuint32_t BUF50M:1;
                vuint32_t BUF49M:1;
                vuint32_t BUF48M:1;
                vuint32_t BUF47M:1;
                vuint32_t BUF46M:1;
                vuint32_t BUF45M:1;
                vuint32_t BUF44M:1;
                vuint32_t BUF43M:1;
                vuint32_t BUF42M:1;
                vuint32_t BUF41M:1;
                vuint32_t BUF40M:1;
                vuint32_t BUF39M:1;
                vuint32_t BUF38M:1;
                vuint32_t BUF37M:1;
                vuint32_t BUF36M:1;
                vuint32_t BUF35M:1;
                vuint32_t BUF34M:1;
                vuint32_t BUF33M:1;
                vuint32_t BUF32M:1;
            } B;
        } IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */
        
        union {                 /* Interruput Masks Register */
            vuint32_t R;
            struct {
                vuint32_t BUF31M:1;
                vuint32_t BUF30M:1;
                vuint32_t BUF29M:1;
                vuint32_t BUF28M:1;
                vuint32_t BUF27M:1;
                vuint32_t BUF26M:1;
                vuint32_t BUF25M:1;
                vuint32_t BUF24M:1;
                vuint32_t BUF23M:1;
                vuint32_t BUF22M:1;
                vuint32_t BUF21M:1;
                vuint32_t BUF20M:1;
                vuint32_t BUF19M:1;
                vuint32_t BUF18M:1;
                vuint32_t BUF17M:1;
                vuint32_t BUF16M:1;
                vuint32_t BUF15M:1;
                vuint32_t BUF14M:1;
                vuint32_t BUF13M:1;
                vuint32_t BUF12M:1;
                vuint32_t BUF11M:1;
                vuint32_t BUF10M:1;
                vuint32_t BUF09M:1;
                vuint32_t BUF08M:1;
                vuint32_t BUF07M:1;
                vuint32_t BUF06M:1;
                vuint32_t BUF05M:1;
                vuint32_t BUF04M:1;
                vuint32_t BUF03M:1;
                vuint32_t BUF02M:1;
                vuint32_t BUF01M:1;
                vuint32_t BUF00M:1;
            } B;
        } IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */
        
        union {                 /* Interruput Flag Register */
            vuint32_t R;
            struct {
                vuint32_t BUF63I:1;
                vuint32_t BUF62I:1;
                vuint32_t BUF61I:1;
                vuint32_t BUF60I:1;
                vuint32_t BUF59I:1;
                vuint32_t BUF58I:1;
                vuint32_t BUF57I:1;
                vuint32_t BUF56I:1;
                vuint32_t BUF55I:1;
                vuint32_t BUF54I:1;
                vuint32_t BUF53I:1;
                vuint32_t BUF52I:1;
                vuint32_t BUF51I:1;
                vuint32_t BUF50I:1;
                vuint32_t BUF49I:1;
                vuint32_t BUF48I:1;
                vuint32_t BUF47I:1;
                vuint32_t BUF46I:1;
                vuint32_t BUF45I:1;
                vuint32_t BUF44I:1;
                vuint32_t BUF43I:1;
                vuint32_t BUF42I:1;
                vuint32_t BUF41I:1;
                vuint32_t BUF40I:1;
                vuint32_t BUF39I:1;
                vuint32_t BUF38I:1;
                vuint32_t BUF37I:1;
                vuint32_t BUF36I:1;
                vuint32_t BUF35I:1;
                vuint32_t BUF34I:1;
                vuint32_t BUF33I:1;
                vuint32_t BUF32I:1;
            } B;
        } IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */
        
        union {                 /* Interruput Flag Register */
            vuint32_t R;
            struct {
                vuint32_t BUF31I:1;
                vuint32_t BUF30I:1;
                vuint32_t BUF29I:1;
                vuint32_t BUF28I:1;
                vuint32_t BUF27I:1;
                vuint32_t BUF26I:1;
                vuint32_t BUF25I:1;
                vuint32_t BUF24I:1;
                vuint32_t BUF23I:1;
                vuint32_t BUF22I:1;
                vuint32_t BUF21I:1;
                vuint32_t BUF20I:1;
                vuint32_t BUF19I:1;
                vuint32_t BUF18I:1;
                vuint32_t BUF17I:1;
                vuint32_t BUF16I:1;
                vuint32_t BUF15I:1;
                vuint32_t BUF14I:1;
                vuint32_t BUF13I:1;
                vuint32_t BUF12I:1;
                vuint32_t BUF11I:1;
                vuint32_t BUF10I:1;
                vuint32_t BUF09I:1;
                vuint32_t BUF08I:1;
                vuint32_t BUF07I:1;
                vuint32_t BUF06I:1;
                vuint32_t BUF05I:1;
                vuint32_t BUF04I:1;
                vuint32_t BUF03I:1;
                vuint32_t BUF02I:1;
                vuint32_t BUF01I:1;
                vuint32_t BUF00I:1;
            } B;
        } IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */
        
        union {                   /* Control Register 2 */
            vuint32_t R;
              struct {
                vuint32_t:2;
                vuint32_t ECRWRE:1;
                vuint32_t WRMFRZ:1;
                vuint32_t RFFN:4;
                vuint32_t TASD:5;
                vuint32_t MRP:1;
                vuint32_t RRS:1;
                vuint32_t EACEN:1;
                vuint32_t:16;
            } B;
        } CTRL2;
        
        union {                   /* Error and Status Register 2 */
            vuint32_t R;
              struct {
                vuint32_t:9;
                vuint32_t LPTM:7;
                vuint32_t:1;
                vuint32_t VPS:1;
                vuint32_t IMB:1;
                vuint32_t:13;
            } B;
        } ESR2;
        
        uint32_t FLEXCAN_reserved003C[2];  /* 0x003C-0x0043 */

        union {                   /* CRC Register */
            vuint32_t R;
              struct {
                vuint32_t:9;
                vuint32_t MBCRC:7;
                vuint32_t:1;
                vuint32_t TXCRC:15;
            } B;
        } CRCR;
        
        union {                   /* Rx FIFO Global Mask Register */
            vuint32_t R;
              struct {
                vuint32_t FGM:32;
            } B;
        } RXFGMASK;
        
        union {                   /* Rx FIFO Information Register */
            vuint32_t R;
              struct {
                vuint32_t:23;
                vuint32_t IDHIT:9;
            } B;
        } RXFIR;
        
        int32_t FLEXCAN_reserved0050[12]; /* 0x0050-0x007F */

        struct canbuf_t BUF[64];
    
        int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */
        
        union {            /* RX Individual Mask Registers */
            vuint32_t R;
            struct {
                vuint32_t MI31:1;
                vuint32_t MI30:1;
                vuint32_t MI29:1;
                vuint32_t MI28:1;
                vuint32_t MI27:1;
                vuint32_t MI26:1;
                vuint32_t MI25:1;
                vuint32_t MI24:1;
                vuint32_t MI23:1;
                vuint32_t MI22:1;
                vuint32_t MI21:1;
                vuint32_t MI20:1;
                vuint32_t MI19:1;
                vuint32_t MI18:1;
                vuint32_t MI17:1;
                vuint32_t MI16:1;
                vuint32_t MI15:1;
                vuint32_t MI14:1;
                vuint32_t MI13:1;
                vuint32_t MI12:1;
                vuint32_t MI11:1;
                vuint32_t MI10:1;
                vuint32_t MI9:1;
                vuint32_t MI8:1;
                vuint32_t MI7:1;
                vuint32_t MI6:1;
                vuint32_t MI5:1;
                vuint32_t MI4:1;
                vuint32_t MI3:1;
                vuint32_t MI2:1;
                vuint32_t MI1:1;
                vuint32_t MI0:1;
            } B;
        } RXIMR[64];
        
        int32_t FLEXCAN_reserved0980[88]; /* 0x0980-0x0ADF */

        union {
            vuint32_t R;
              struct {
                vuint32_t ECRWRDIS:1;
                vuint32_t:11;
                vuint32_t HANCEI_MSK:1;            
                vuint32_t FANCEI_MSK:1;
                vuint32_t:1;
                vuint32_t CEI_MSK:1;
                vuint32_t HAERRIE:1;
                vuint32_t FAERRIE:1;
                vuint32_t EXTERRIE:1;
                vuint32_t:3;
                vuint32_t RERRDIS:1;
                vuint32_t ECCDIS:1;
                vuint32_t NCEFAFRZ:1;
                vuint32_t:7;
            } B;
        } MECR;

        union {
            vuint32_t R;
              struct {
                vuint32_t:18;
                vuint32_t INJADDR:14;
            } B;
        } ERRIAR;
        
        union {
            vuint32_t R;
              struct {
                vuint32_t DFLIP:32;
            } B;
        } ERRIDPR;

        union {
            vuint32_t R;
              struct {
                vuint32_t:3;
                vuint32_t PFLIP3:5;
                vuint32_t:3;
                vuint32_t PFLIP2:5;
                vuint32_t:3;
                vuint32_t PFLIP1:5;
                vuint32_t:3;
                vuint32_t PFLIP0:5;
            } B;
        } ERRIPPR;
        
        union {
            vuint32_t R;
              struct {
                vuint32_t:7;
                vuint32_t NCE:1;
                vuint32_t:5;
                vuint32_t SAID:3;
                vuint32_t:2;
                vuint32_t ERRADDR:14;
            } B;
        } RERRAR;
        
        union {
            vuint32_t R;
              struct {
                vuint32_t RDATA:32;
            } B;
        } RERRDR;
        
        union {
            vuint32_t R;
              struct {
                vuint32_t BE3:1;
                vuint32_t:2;
                vuint32_t SYND3:5;
                vuint32_t BE2:1;
                vuint32_t:2;
                vuint32_t SYND2:5;
                vuint32_t BE1:1;
                vuint32_t:2;
                vuint32_t SYND1:5;
                vuint32_t BE0:1;
                vuint32_t:2;
                vuint32_t SYND0:5;
            } B;
        } RERRSYNR;
        
        union {
            vuint32_t R;
              struct {
                vuint32_t:12;
                vuint32_t HANCEIF:1;
                vuint32_t FANCEIF:1;
                vuint32_t:1;
                vuint32_t CEIF:1;
                vuint32_t:12;
                vuint32_t HANCEIOF:1;
                vuint32_t FANCEIOF:1;
                vuint32_t:1;
                vuint32_t CEIOF:1;
            } B;
        } ERRSR;

       int32_t FLEXCAN_reserved0B00[3392]; /* 0x0B00-0x3FFF */
    
    };

/****************************************************************************/
/*                          MODULE : DTS                                    */
/****************************************************************************/

    struct DTS_tag {
        union {
            vuint32_t R;
            struct {
                vuint32_t:30;          /*  */
                vuint32_t DTS_EN_B:1; /* Enable for the DTS Semaphore B */
                vuint32_t DTS_EN:1;   /* Enable for the DTS Semaphore */
            } B;
        } ENABLE;                /* DTS_ENABLE @baseaddress */

        union 
        {
          vuint32_t R;
            struct {
                vuint32_t AD31:1;       /* Startup register MSB */
                vuint32_t AD30:1;       /* */
                vuint32_t AD29:1;       /* */
                vuint32_t AD28:1;       /* */
                vuint32_t AD27:1;       /* */
                vuint32_t AD26:1;       /* */
                vuint32_t AD25:1;       /* */
                vuint32_t AD24:1;       /* */
                vuint32_t AD23:1;       /* */
                vuint32_t AD22:1;       /* */
                vuint32_t AD21:1;       /* */
                vuint32_t AD20:1;       /* */
                vuint32_t AD19:1;       /* */
                vuint32_t AD18:1;       /* */
                vuint32_t AD17:1;       /* */
                vuint32_t AD16:1;       /* */
                vuint32_t AD15:1;       /* */
                vuint32_t AD14:1;       /* */
                vuint32_t AD13:1;       /* */
                vuint32_t AD12:1;       /* */
                vuint32_t AD11:1;       /* */
                vuint32_t AD10:1;       /* */
                vuint32_t AD9:1;       /* */
                vuint32_t AD8:1;       /* */
                vuint32_t AD7:1;       /* */
                vuint32_t AD6:1;       /* */
                vuint32_t AD5:1;       /* */
                vuint32_t AD4:1;       /* */
                vuint32_t AD3:1;       /* */
                vuint32_t AD2:1;       /* */
                vuint32_t AD1:1;       /* */
                vuint32_t AD0:1;       /* Startup Register LSB */
            } B;
        } STARTUP;                /* DTS_STARTUP @baseaddress + 0x4*/

        union 
        {
          vuint32_t R;
            struct {
                vuint32_t ST31:1;       /* Semaphore register MSB */
                vuint32_t ST30:1;       /* */
                vuint32_t ST29:1;       /* */
                vuint32_t ST28:1;       /* */
                vuint32_t ST27:1;       /* */
                vuint32_t ST26:1;       /* */
                vuint32_t ST25:1;       /* */
                vuint32_t ST24:1;       /* */
                vuint32_t ST23:1;       /* */
                vuint32_t ST22:1;       /* */
                vuint32_t ST21:1;       /* */
                vuint32_t ST20:1;       /* */
                vuint32_t ST19:1;       /* */
                vuint32_t ST18:1;       /* */
                vuint32_t ST17:1;       /* */
                vuint32_t ST16:1;       /* */
                vuint32_t ST15:1;       /* */
                vuint32_t ST14:1;       /* */
                vuint32_t ST13:1;       /* */
                vuint32_t ST12:1;       /* */
                vuint32_t ST11:1;       /* */
                vuint32_t ST10:1;       /* */
                vuint32_t ST9:1;       /* */
                vuint32_t ST8:1;       /* */
                vuint32_t ST7:1;       /* */
                vuint32_t ST6:1;       /* */
                vuint32_t ST5:1;       /* */
                vuint32_t ST4:1;       /* */
                vuint32_t ST3:1;       /* */
                vuint32_t ST2:1;       /* */
                vuint32_t ST1:1;       /* */
                vuint32_t ST0:1;       /* Semaphore Register LSB */
            } B;
        } SEMAPHORE;                /* DTS_STEMAPHORE @BaseAddress + 0x8 */        

        union 
        {
          vuint32_t R;
            struct {
                vuint32_t ST_B31:1;       /* Semaphore B register MSB */
                vuint32_t ST_B30:1;       /* */
                vuint32_t ST_B29:1;       /* */
                vuint32_t ST_B28:1;       /* */
                vuint32_t ST_B27:1;       /* */
                vuint32_t ST_B26:1;       /* */
                vuint32_t ST_B25:1;       /* */
                vuint32_t ST_B24:1;       /* */
                vuint32_t ST_B23:1;       /* */
                vuint32_t ST_B22:1;       /* */
                vuint32_t ST_B21:1;       /* */
                vuint32_t ST_B20:1;       /* */
                vuint32_t ST_B19:1;       /* */
                vuint32_t ST_B18:1;       /* */
                vuint32_t ST_B17:1;       /* */
                vuint32_t ST_B16:1;       /* */
                vuint32_t ST_B15:1;       /* */
                vuint32_t ST_B14:1;       /* */
                vuint32_t ST_B13:1;       /* */
                vuint32_t ST_B12:1;       /* */
                vuint32_t ST_B11:1;       /* */
                vuint32_t ST_B10:1;       /* */
                vuint32_t ST_B9:1;       /* */
                vuint32_t ST_B8:1;       /* */
                vuint32_t ST_B7:1;       /* */
                vuint32_t ST_B6:1;       /* */
                vuint32_t ST_B5:1;       /* */
                vuint32_t ST_B4:1;       /* */
                vuint32_t ST_B3:1;       /* */
                vuint32_t ST_B2:1;       /* */
                vuint32_t ST_B1:1;       /* */
                vuint32_t ST_B0:1;       /* Semaphore B Register LSB */
            } B;
        } SEMAPHORE_B;                /* DTS_STEMAPHORE @BaseAddress + 0xC */        
    }; /* End of DTS Module */

/****************************************************************************/
/*                          MODULE : CCU                                    */
/****************************************************************************/

    struct CCU_tag {
    
        union {                 /* CCU Configuration/Error Status Register */
            vuint32_t R;
            struct {
                vuint32_t CP1ERR:2;
                vuint32_t CP0ERR:2;
                vuint32_t SRSTFLAG:1;
                vuint32_t:1;
                vuint32_t CP1IDLE:1;
                vuint32_t CP0IDLE:1;
                vuint32_t:2;
                vuint32_t CP1IEN:1;
                vuint32_t CP0IEN:1;
                vuint32_t:4;
                vuint32_t M3WMEN:1;
                vuint32_t M2WMEN:1;
                vuint32_t M1WMEN:1;
                vuint32_t M0WMEN:1;
                vuint32_t:10;
                vuint32_t SRSTEN:1;
                vuint32_t ENB:1;
            } B;
        } CESR;
        
        uint32_t CCU_reserved0004[3]; /* 0x0004-0x000F */
        
        struct {
            union {             /* CCU Error Address Registers */
                vuint32_t R;
                struct {
                    vuint32_t EADDR:32;
                } B;
            } EAR;
            
            union {             /* CCU Error Detail Registers */
                vuint32_t R;
                struct {
                    vuint32_t EMSTR:4;
                    vuint32_t:4;
                    vuint32_t ESTAMP:8;
                    vuint32_t:2;
                    vuint32_t EPROT:6;
                    vuint32_t ERESP:5;
                    vuint32_t:3;
                } B;
            } EDR;
            
            uint32_t CCU_CORE_reserved0008[2]; /* 0x0008-0x000F */
            
        } CORE[2];
        
        union {           /* CCU Interrupt Registers */
            vuint32_t R;
            struct {
                vuint32_t:30;
                vuint32_t OIF:1;
                vuint32_t EIF:1;
            } B;
        } IR[2];
        
        uint32_t CCU_reserved0038[4082];  /* 0x0038-0x3FFF */
    
    };

/****************************************************************************/
/*                    MODULE : SEMA4 (Semaphores)                           */
/****************************************************************************/

struct SEMA4_tag {

    union { /* Gate 0..15 (Base+0x0000-0x000F) */
        vuint8_t R;
        struct {
            vuint8_t:6;
            vuint8_t GTFSM:2;
        } B;
    } GATE[16];

    vuint8_t SEMA4_reserved0010[48]; /* Reserved 48 Bytes (Base+0x0010-0x003F) */

    union { /* CP0 IRQ Notification enable (Base+0x0040) */
        vuint16_t R;
        struct {
            vuint16_t INE0:1;
            vuint16_t INE1:1;
            vuint16_t INE2:1;
            vuint16_t INE3:1;
            vuint16_t INE4:1;
            vuint16_t INE5:1;
            vuint16_t INE6:1;
            vuint16_t INE7:1;
            vuint16_t INE8:1;
            vuint16_t INE9:1;
            vuint16_t INE10:1;
            vuint16_t INE11:1;
            vuint16_t INE12:1;
            vuint16_t INE13:1;
            vuint16_t INE14:1;
            vuint16_t INE15:1;
        } B;
    } CP0INE;

    vuint8_t SEMA4_reserved0042[6]; /* Reserved 6 Bytes (Base+0x0042-0x0047) */

    union { /* CP1 IRQ Notification enable (Base+0x0048) */
        vuint16_t R;
        struct {
            vuint16_t INE0:1;
            vuint16_t INE1:1;
            vuint16_t INE2:1;
            vuint16_t INE3:1;
            vuint16_t INE4:1;
            vuint16_t INE5:1;
            vuint16_t INE6:1;
            vuint16_t INE7:1;
            vuint16_t INE8:1;
            vuint16_t INE9:1;
            vuint16_t INE10:1;
            vuint16_t INE11:1;
            vuint16_t INE12:1;
            vuint16_t INE13:1;
            vuint16_t INE14:1;
            vuint16_t INE15:1;
        } B;
    } CP1INE;

    vuint8_t SEMA4_reserved004A[54]; /* Reserved 54 Bytes (Base+0x004A-0x007F) */

    union { /* CP0 IRQ Notification (Base+0x0080) */
        vuint16_t R;
        struct {
            vuint16_t GN0:1;
            vuint16_t GN1:1;
            vuint16_t GN2:1;
            vuint16_t GN3:1;
            vuint16_t GN4:1;
            vuint16_t GN5:1;
            vuint16_t GN6:1;
            vuint16_t GN7:1;
            vuint16_t GN8:1;
            vuint16_t GN9:1;
            vuint16_t GN10:1;
            vuint16_t GN11:1;
            vuint16_t GN12:1;
            vuint16_t GN13:1;
            vuint16_t GN14:1;
            vuint16_t GN15:1;
        } B;
    } CP0NTF;

    vuint8_t SEMA4_reserved0082[6]; /* Reserved 6 Bytes (Base+0x0082-0x0087) */

    union { /* CP1 IRQ Notification (Base+0x0088) */
        vuint16_t R;
        struct {
            vuint16_t GN0:1;
            vuint16_t GN1:1;
            vuint16_t GN2:1;
            vuint16_t GN3:1;
            vuint16_t GN4:1;
            vuint16_t GN5:1;
            vuint16_t GN6:1;
            vuint16_t GN7:1;
            vuint16_t GN8:1;
            vuint16_t GN9:1;
            vuint16_t GN10:1;
            vuint16_t GN11:1;
            vuint16_t GN12:1;
            vuint16_t GN13:1;
            vuint16_t GN14:1;
            vuint16_t GN15:1;
        } B;
    } CP1NTF;

    vuint8_t SEMA4_reserved008A[118]; /* Reserved 118 Bytes (+0x008A-0x00FF) */

    union { /* Reset gate (Base+0x0100) */
        vuint16_t R;
        struct {
            vuint16_t:2;
            vuint16_t RSTGSM:2;
            vuint16_t:1;
            vuint16_t RSTGMS:3;
            vuint16_t RSTGTN:8;
        } B;
    } RSTGT;

    vuint8_t SEMA4_reserved0102[2]; /* Reserved 2 Bytes (Base+0x0102-0x0103) */

    union {
        vuint16_t R;
        struct {
            vuint16_t:2;
            vuint16_t RSTNSM:2;
            vuint16_t:1;
            vuint16_t RSTNMS:3;
            vuint16_t RSTNTN:8;
        } B;
    } RSTNTF;

    vuint8_t SEMA4_reserved0106[16122]; /* Reserved 16122 (Base+0x0106-0x3FFF) */

}; /* end of SEMA4_tag */

/****************************************************************************/
/*                          MODULE : CRC                                    */
/****************************************************************************/
struct CRC_SUB_tag {
    union {
        vuint32_t R;      /* CRC Configuration Register */
        struct {
            vuint32_t:28;
            vuint32_t POLYG:2;
            vuint32_t SWAP:1;
            vuint32_t INV:1;
        } B;
    } CRC_CFG;

    union {               /* CRC Input Register */
        vuint8_t BYTE[4];       /* Data buffer in Bytes (8 bits) */
        vuint16_t HALFWORD[2];  /* Data buffer in Half-words (16 bits) */
        vuint32_t WORD;         /* Data buffer in words (32 bits) */
        vuint32_t R;            /* Data buffer in words (32 bits) */
    } CRC_INP;

    union {               /*CRC Current Status Register */
        vuint8_t BYTE[4];       /* Data buffer in Bytes (8 bits) */
        vuint16_t HALFWORD[2];  /* Data buffer in Half-words (16 bits) */
        vuint32_t WORD;         /* Data buffer in words (32 bits) */
        vuint32_t R;            /* Data buffer in words (32 bits) */
    } CRC_CSTAT;

    union {                /* CRC Output Register */
        vuint8_t BYTE[4];       /* Data buffer in Bytes (8 bits) */
        vuint16_t HALFWORD[2];  /* Data buffer in Half-words (16 bits) */
        vuint32_t WORD;         /* Data buffer in words (32 bits) */
        vuint32_t R;            /* Data buffer in words (32 bits) */
    } CRC_OUTP;
}; /* end of CRC_SUB_tag */

struct CRC_tag {
    struct CRC_SUB_tag CNTX[3];
}; /* end of CRC_tag */

/****************************************************************************/
/*                          MODULE : STCU2                                  */
/****************************************************************************/
struct STCU2_tag {
  union {                              /* STCU2 Run Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t BYP:1;
      vuint32_t MBPLLEN:1;
      vuint32_t LBPLLEN:1;
      vuint32_t  :7;
      vuint32_t RUN:1;
    } B;
  } RUN;

  union {                              /* STCU2 Run Software Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t MBSWPLLEN:1;
      vuint32_t LBSWPLLEN:1;
      vuint32_t  :6;
      vuint32_t  :1;
      vuint32_t RUNSW:1;
    } B;
  } RUNSW;

  union {                              /* STCU2 SK Code Register */
    vuint32_t R;
    struct {
      vuint32_t SKC:32;
    } B;
  } SKC;

  union {                              /* STCU2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PTR:7;
      vuint32_t  :8;
      vuint32_t  :7;
      vuint32_t WRP:1;
      vuint32_t  :2;
      vuint32_t CRCEN:1;
      vuint32_t PMOSEN:1;
      vuint32_t MBU:1;
      vuint32_t CLK_CFG:3;
    } B;
  } CFG;

  union {                              /* STCU2 PLL Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t PLLODF:6;
      vuint32_t  :5;
      vuint32_t PLLIDF:3;
      vuint32_t  :9;
      vuint32_t PLLLDF:7;
    } B;
  } PLL_CFG;

  union {                              /* STCU2 Watchdog Register Granularity */
    vuint32_t R;
    struct {
      vuint32_t WDGEOC:32;
    } B;
  } WDG;

  uint8_t STCU2_reserved0[4];
  union {                              /* STCU2 CRC Expected Status Register */
    vuint32_t R;
    struct {
      vuint32_t CRCE:32;
    } B;
  } CRCE;

  union {                              /* STCU2 CRC Read Status Register */
    vuint32_t R;
    struct {
      vuint32_t CRCR:32;
    } B;
  } CRCR;

  union {                              /* STCU2 Error Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :3;
      vuint32_t LOCKESW:1;
      vuint32_t WDTOSW:1;
      vuint32_t CRCSSW:1;
      vuint32_t ENGESW:1;
      vuint32_t INVPSW:1;
      vuint32_t  :6;
      vuint32_t UFSF:1;
      vuint32_t RFSF:1;
      vuint32_t  :3;
      vuint32_t LOCKE:1;
      vuint32_t WDTO:1;
      vuint32_t CRCS:1;
      vuint32_t ENGE:1;
      vuint32_t INVP:1;
    } B;
  } ERR_STAT;

  union {                              /* STCU2 Error FM Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t LOCKEUFM:1;
      vuint32_t WDTOUFM:1;
      vuint32_t CRCSUFM:1;
      vuint32_t ENGEUFM:1;
      vuint32_t INVPUFM:1;
    } B;
  } ERR_FM;

  union {                              /* STCU2 Off-Line LBIST Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t LBS5:1;
      vuint32_t LBS4:1;
      vuint32_t LBS3:1;
      vuint32_t LBS2:1;
      vuint32_t LBS1:1;
      vuint32_t LBS0:1;
    } B;
  } LBS;

  union {                              /* STCU2 Off-Line LBIST End Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t LBE5:1;
      vuint32_t LBE4:1;
      vuint32_t LBE3:1;
      vuint32_t LBE2:1;
      vuint32_t LBE1:1;
      vuint32_t LBE0:1;
    } B;
  } LBE;

  union {                              /* STCU2 On-Line LBIST Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t LBSSW5:1;
      vuint32_t LBSSW4:1;
      vuint32_t LBSSW3:1;
      vuint32_t LBSSW2:1;
      vuint32_t LBSSW1:1;
      vuint32_t LBSSW0:1;
    } B;
  } LBSSW;

  union {                              /* STCU2 On-Line LBIST End Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t LBESW5:1;
      vuint32_t LBESW4:1;
      vuint32_t LBESW3:1;
      vuint32_t LBESW2:1;
      vuint32_t LBESW1:1;
      vuint32_t LBESW0:1;
    } B;
  } LBESW;

  union {                              /* STCU2 On-Line LBIST Reset Management */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t LBRMSW5:1;
      vuint32_t LBRMSW4:1;
      vuint32_t LBRMSW3:1;
      vuint32_t LBRMSW2:1;
      vuint32_t LBRMSW1:1;
      vuint32_t LBRMSW0:1;
    } B;
  } LBRMSW;

  union {                              /* STCU2 LBIST Unrecoverable FM Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t LBUFM5:1;
      vuint32_t LBUFM4:1;
      vuint32_t LBUFM3:1;
      vuint32_t LBUFM2:1;
      vuint32_t LBUFM1:1;
      vuint32_t LBUFM0:1;
    } B;
  } LBUFM;

  union {                              /* STCU2 Off-Line MBIST Status Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBS31:1;
      vuint32_t MBS30:1;
      vuint32_t MBS29:1;
      vuint32_t MBS28:1;
      vuint32_t MBS27:1;
      vuint32_t MBS26:1;
      vuint32_t MBS25:1;
      vuint32_t MBS24:1;
      vuint32_t MBS23:1;
      vuint32_t MBS22:1;
      vuint32_t MBS21:1;
      vuint32_t MBS20:1;
      vuint32_t MBS19:1;
      vuint32_t MBS18:1;
      vuint32_t MBS17:1;
      vuint32_t MBS16:1;
      vuint32_t MBS15:1;
      vuint32_t MBS14:1;
      vuint32_t MBS13:1;
      vuint32_t MBS12:1;
      vuint32_t MBS11:1;
      vuint32_t MBS10:1;
      vuint32_t MBS9:1;
      vuint32_t MBS8:1;
      vuint32_t MBS7:1;
      vuint32_t MBS6:1;
      vuint32_t MBS5:1;
      vuint32_t MBS4:1;
      vuint32_t MBS3:1;
      vuint32_t MBS2:1;
      vuint32_t MBS1:1;
      vuint32_t MBS0:1;
    } B;
  } MBSL;

  union {                              /* STCU2 Off-Line MBIST Status Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBS63:1;
      vuint32_t MBS62:1;
      vuint32_t MBS61:1;
      vuint32_t MBS60:1;
      vuint32_t MBS59:1;
      vuint32_t MBS58:1;
      vuint32_t MBS57:1;
      vuint32_t MBS56:1;
      vuint32_t MBS55:1;
      vuint32_t MBS54:1;
      vuint32_t MBS53:1;
      vuint32_t MBS52:1;
      vuint32_t MBS51:1;
      vuint32_t MBS50:1;
      vuint32_t MBS49:1;
      vuint32_t MBS48:1;
      vuint32_t MBS47:1;
      vuint32_t MBS46:1;
      vuint32_t MBS45:1;
      vuint32_t MBS44:1;
      vuint32_t MBS43:1;
      vuint32_t MBS42:1;
      vuint32_t MBS41:1;
      vuint32_t MBS40:1;
      vuint32_t MBS39:1;
      vuint32_t MBS38:1;
      vuint32_t MBS37:1;
      vuint32_t MBS36:1;
      vuint32_t MBS35:1;
      vuint32_t MBS34:1;
      vuint32_t MBS33:1;
      vuint32_t MBS32:1;
    } B;
  } MBSM;

  union {                              /* STCU2 Off-Line MBIST Status High Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MBS64:1;
    } B;
  } MBSH;

  union {                              /* STCU2 Off-Line MBIST End Flag Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBE31:1;
      vuint32_t MBE30:1;
      vuint32_t MBE29:1;
      vuint32_t MBE28:1;
      vuint32_t MBE27:1;
      vuint32_t MBE26:1;
      vuint32_t MBE25:1;
      vuint32_t MBE24:1;
      vuint32_t MBE23:1;
      vuint32_t MBE22:1;
      vuint32_t MBE21:1;
      vuint32_t MBE20:1;
      vuint32_t MBE19:1;
      vuint32_t MBE18:1;
      vuint32_t MBE17:1;
      vuint32_t MBE16:1;
      vuint32_t MBE15:1;
      vuint32_t MBE14:1;
      vuint32_t MBE13:1;
      vuint32_t MBE12:1;
      vuint32_t MBE11:1;
      vuint32_t MBE10:1;
      vuint32_t MBE9:1;
      vuint32_t MBE8:1;
      vuint32_t MBE7:1;
      vuint32_t MBE6:1;
      vuint32_t MBE5:1;
      vuint32_t MBE4:1;
      vuint32_t MBE3:1;
      vuint32_t MBE2:1;
      vuint32_t MBE1:1;
      vuint32_t MBE0:1;
    } B;
  } MBEL;

  union {                              /* STCU2 Off-Line MBIST End Flag Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBE63:1;
      vuint32_t MBE62:1;
      vuint32_t MBE61:1;
      vuint32_t MBE60:1;
      vuint32_t MBE59:1;
      vuint32_t MBE58:1;
      vuint32_t MBE57:1;
      vuint32_t MBE56:1;
      vuint32_t MBE55:1;
      vuint32_t MBE54:1;
      vuint32_t MBE53:1;
      vuint32_t MBE52:1;
      vuint32_t MBE51:1;
      vuint32_t MBE50:1;
      vuint32_t MBE49:1;
      vuint32_t MBE48:1;
      vuint32_t MBE47:1;
      vuint32_t MBE46:1;
      vuint32_t MBE45:1;
      vuint32_t MBE44:1;
      vuint32_t MBE43:1;
      vuint32_t MBE42:1;
      vuint32_t MBE41:1;
      vuint32_t MBE40:1;
      vuint32_t MBE39:1;
      vuint32_t MBE38:1;
      vuint32_t MBE37:1;
      vuint32_t MBE36:1;
      vuint32_t MBE35:1;
      vuint32_t MBE34:1;
      vuint32_t MBE33:1;
      vuint32_t MBE32:1;
    } B;
  } MBEM;

  union {                              /* STCU2 Off-Line MBIST End Flag High Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MBE64:1;
    } B;
  } MBEH;

  union {                              /* STCU2 On-Line MBIST Status Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBSSW31:1;
      vuint32_t MBSSW30:1;
      vuint32_t MBSSW29:1;
      vuint32_t MBSSW28:1;
      vuint32_t MBSSW27:1;
      vuint32_t MBSSW26:1;
      vuint32_t MBSSW25:1;
      vuint32_t MBSSW24:1;
      vuint32_t MBSSW23:1;
      vuint32_t MBSSW22:1;
      vuint32_t MBSSW21:1;
      vuint32_t MBSSW20:1;
      vuint32_t MBSSW19:1;
      vuint32_t MBSSW18:1;
      vuint32_t MBSSW17:1;
      vuint32_t MBSSW16:1;
      vuint32_t MBSSW15:1;
      vuint32_t MBSSW14:1;
      vuint32_t MBSSW13:1;
      vuint32_t MBSSW12:1;
      vuint32_t MBSSW11:1;
      vuint32_t MBSSW10:1;
      vuint32_t MBSSW9:1;
      vuint32_t MBSSW8:1;
      vuint32_t MBSSW7:1;
      vuint32_t MBSSW6:1;
      vuint32_t MBSSW5:1;
      vuint32_t MBSSW4:1;
      vuint32_t MBSSW3:1;
      vuint32_t MBSSW2:1;
      vuint32_t MBSSW1:1;
      vuint32_t MBSSW0:1;
    } B;
  } MBSLSW;

  union {                              /* STCU2 On-Line MBIST Status Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBSSW63:1;
      vuint32_t MBSSW62:1;
      vuint32_t MBSSW61:1;
      vuint32_t MBSSW60:1;
      vuint32_t MBSSW59:1;
      vuint32_t MBSSW58:1;
      vuint32_t MBSSW57:1;
      vuint32_t MBSSW56:1;
      vuint32_t MBSSW55:1;
      vuint32_t MBSSW54:1;
      vuint32_t MBSSW53:1;
      vuint32_t MBSSW52:1;
      vuint32_t MBSSW51:1;
      vuint32_t MBSSW50:1;
      vuint32_t MBSSW49:1;
      vuint32_t MBSSW48:1;
      vuint32_t MBSSW47:1;
      vuint32_t MBSSW46:1;
      vuint32_t MBSSW45:1;
      vuint32_t MBSSW44:1;
      vuint32_t MBSSW43:1;
      vuint32_t MBSSW42:1;
      vuint32_t MBSSW41:1;
      vuint32_t MBSSW40:1;
      vuint32_t MBSSW39:1;
      vuint32_t MBSSW38:1;
      vuint32_t MBSSW37:1;
      vuint32_t MBSSW36:1;
      vuint32_t MBSSW35:1;
      vuint32_t MBSSW34:1;
      vuint32_t MBSSW33:1;
      vuint32_t MBSSW32:1;
    } B;
  } MBSMSW;

  union {                              /* STCU2 On-Line MBIST Status High Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MBSSW64:1;
    } B;
  } MBSHSW;

  union {                              /* STCU2 On-Line MBIST End Flag Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBESW31:1;
      vuint32_t MBESW30:1;
      vuint32_t MBESW29:1;
      vuint32_t MBESW28:1;
      vuint32_t MBESW27:1;
      vuint32_t MBESW26:1;
      vuint32_t MBESW25:1;
      vuint32_t MBESW24:1;
      vuint32_t MBESW23:1;
      vuint32_t MBESW22:1;
      vuint32_t MBESW21:1;
      vuint32_t MBESW20:1;
      vuint32_t MBESW19:1;
      vuint32_t MBESW18:1;
      vuint32_t MBESW17:1;
      vuint32_t MBESW16:1;
      vuint32_t MBESW15:1;
      vuint32_t MBESW14:1;
      vuint32_t MBESW13:1;
      vuint32_t MBESW12:1;
      vuint32_t MBESW11:1;
      vuint32_t MBESW10:1;
      vuint32_t MBESW9:1;
      vuint32_t MBESW8:1;
      vuint32_t MBESW7:1;
      vuint32_t MBESW6:1;
      vuint32_t MBESW5:1;
      vuint32_t MBESW4:1;
      vuint32_t MBESW3:1;
      vuint32_t MBESW2:1;
      vuint32_t MBESW1:1;
      vuint32_t MBESW0:1;
    } B;
  } MBELSW;

  union {                              /* STCU2 On-Line MBIST End Flag Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBESW63:1;
      vuint32_t MBESW62:1;
      vuint32_t MBESW61:1;
      vuint32_t MBESW60:1;
      vuint32_t MBESW59:1;
      vuint32_t MBESW58:1;
      vuint32_t MBESW57:1;
      vuint32_t MBESW56:1;
      vuint32_t MBESW55:1;
      vuint32_t MBESW54:1;
      vuint32_t MBESW53:1;
      vuint32_t MBESW52:1;
      vuint32_t MBESW51:1;
      vuint32_t MBESW50:1;
      vuint32_t MBESW49:1;
      vuint32_t MBESW48:1;
      vuint32_t MBESW47:1;
      vuint32_t MBESW46:1;
      vuint32_t MBESW45:1;
      vuint32_t MBESW44:1;
      vuint32_t MBESW43:1;
      vuint32_t MBESW42:1;
      vuint32_t MBESW41:1;
      vuint32_t MBESW40:1;
      vuint32_t MBESW39:1;
      vuint32_t MBESW38:1;
      vuint32_t MBESW37:1;
      vuint32_t MBESW36:1;
      vuint32_t MBESW35:1;
      vuint32_t MBESW34:1;
      vuint32_t MBESW33:1;
      vuint32_t MBESW32:1;
    } B;
  } MBEMSW;

  union {                              /* STCU2 On-Line MBIST End Flag High Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MBESW64:1;
    } B;
  } MBEHSW;

  union {                              /* STCU2 MBIST Unrecoverable FM Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBUFM31:1;
      vuint32_t MBUFM30:1;
      vuint32_t MBUFM29:1;
      vuint32_t MBUFM28:1;
      vuint32_t MBUFM27:1;
      vuint32_t MBUFM26:1;
      vuint32_t MBUFM25:1;
      vuint32_t MBUFM24:1;
      vuint32_t MBUFM23:1;
      vuint32_t MBUFM22:1;
      vuint32_t MBUFM21:1;
      vuint32_t MBUFM20:1;
      vuint32_t MBUFM19:1;
      vuint32_t MBUFM18:1;
      vuint32_t MBUFM17:1;
      vuint32_t MBUFM16:1;
      vuint32_t MBUFM15:1;
      vuint32_t MBUFM14:1;
      vuint32_t MBUFM13:1;
      vuint32_t MBUFM12:1;
      vuint32_t MBUFM11:1;
      vuint32_t MBUFM10:1;
      vuint32_t MBUFM9:1;
      vuint32_t MBUFM8:1;
      vuint32_t MBUFM7:1;
      vuint32_t MBUFM6:1;
      vuint32_t MBUFM5:1;
      vuint32_t MBUFM4:1;
      vuint32_t MBUFM3:1;
      vuint32_t MBUFM2:1;
      vuint32_t MBUFM1:1;
      vuint32_t MBUFM0:1;
    } B;
  } MBUFML;

  union {                              /* STCU2 MBIST Unrecoverable FM Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBUFM63:1;
      vuint32_t MBUFM62:1;
      vuint32_t MBUFM61:1;
      vuint32_t MBUFM60:1;
      vuint32_t MBUFM59:1;
      vuint32_t MBUFM58:1;
      vuint32_t MBUFM57:1;
      vuint32_t MBUFM56:1;
      vuint32_t MBUFM55:1;
      vuint32_t MBUFM54:1;
      vuint32_t MBUFM53:1;
      vuint32_t MBUFM52:1;
      vuint32_t MBUFM51:1;
      vuint32_t MBUFM50:1;
      vuint32_t MBUFM49:1;
      vuint32_t MBUFM48:1;
      vuint32_t MBUFM47:1;
      vuint32_t MBUFM46:1;
      vuint32_t MBUFM45:1;
      vuint32_t MBUFM44:1;
      vuint32_t MBUFM43:1;
      vuint32_t MBUFM42:1;
      vuint32_t MBUFM41:1;
      vuint32_t MBUFM40:1;
      vuint32_t MBUFM39:1;
      vuint32_t MBUFM38:1;
      vuint32_t MBUFM37:1;
      vuint32_t MBUFM36:1;
      vuint32_t MBUFM35:1;
      vuint32_t MBUFM34:1;
      vuint32_t MBUFM33:1;
      vuint32_t MBUFM32:1;
    } B;
  } MBUFMM;

  union {                              /* STCU2 MBIST Unrecoverable FM High Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MBUFM64:1;
    } B;
  } MBUFMH;

  uint8_t STCU2_reserved1[128];
  struct {
    union {                            /* STCU2 LBIST Control Register */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t PTR:7;
        vuint32_t  :4;
        vuint32_t PRPGEN:1;
        vuint32_t SHS:3;
        vuint32_t SCEN_OFF:4;
        vuint32_t SCEN_ON:4;
        vuint32_t  :4;
        vuint32_t PFT:1;
        vuint32_t CWS:3;
      } B;
    } LB_CTRL;
    union {                            /* STCU2 LBIST PC Stop Register */
      vuint32_t R;
      struct {
        vuint32_t  :6;
        vuint32_t PCS:26;
      } B;
    } LB_PCS;
    union {                            /* STCU2 LBIST PRPG Low Register */
      vuint32_t R;
      struct {
        vuint32_t PRPGx:32;
      } B;
    } LB_PRPGL;
    union {                            /* STCU2 LBIST PRPG High Register */
      vuint32_t R;
      struct {
        vuint32_t PRPGx:32;
      } B;
    } LB_PRPGH;
    union {                            /* STCU2 Off-Line LBIST MISR Expected Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISREx:32;
      } B;
    } LB_MISREL;
    union {                            /* STCU2 Off-Line LBIST MISR Expected High Register */
      vuint32_t R;
      struct {
        vuint32_t MISREx:32;
      } B;
    } LB_MISREH;
    union {                            /* STCU2 Off-Line LBIST MISR Read Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRx:32;
      } B;
    } LB_MISRRL;
    union {                            /* STCU2 Off-Line LBIST MISR Read High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRx:32;
      } B;
    } LB_MISRRH;
    union {                            /* STCU2 On-Line LBIST MISR Expected Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRESWx:32;
      } B;
    } LB_MISRELSW;
    union {                            /* STCU2 On-Line LBIST MISR Expected High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRESWx:32;
      } B;
    } LB_MISREHSW;
    union {                            /* STCU2 On-Line LBIST MISR Read Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRSWx:32;
      } B;
    } LB_MISRRLSW;
    union {                            /* STCU2 On-Line LBIST MISR Read High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRSWx:32;
      } B;
    } LB_MISRRHSW;
    uint8_t LB_reserved0[16];
  } LB[6];

  uint8_t STCU2_reserved2[896];
  union {                              /* STCU2 MBIST Control Register */
    vuint32_t R;
    struct {
      vuint32_t CSM:1;
      vuint32_t PTR:7;
      vuint32_t  :24;
    } B;
  } MB_CTRL[65];
};

/****************************************************************************/
/* Define memories */

#define SRAM_START    0x40000000
#define SRAM_SIZE        0x80000
#define SRAM_END      0x4007FFFF

#define FLASH_START   0x00000000
#define FLASH_SIZE      0x800000
#define FLASH_END     0x00DFFFFF

/* Define instances of modules */

#define IGF_1     (*( volatile struct IGF_tag *)        0xC3E04000)        

#define PSI5_1    (*( volatile struct PSI5_tag *)       0xC3E14000)        
#define SDADC_0   (*( volatile struct SDADC_tag *)      0xC3E44000)
#define SDADC_2   (*( volatile struct SDADC_tag *)      0xC3E48000)
#define EQADC_B   (*( volatile struct EQADC_tag *)      0xC3E54000)
#define SRX_1     (*( volatile struct SRX_tag *)        0xC3E5C000)
#define CAN_C     (*( volatile struct FLEXCAN3_tag *)   0xC3E60000)
#define CAN_D     (*( volatile struct FLEXCAN3_tag *)   0xC3E64000)
#define MCAN_1    (*( volatile struct MCAN_tag *)       0xC3E68000)

#define CMU_0     (*( volatile struct CMU_tag *)        0xC3E6C200)
#define CMU_1     (*( volatile struct CMU_tag *)        0xC3E6C240)
#define CMU_2     (*( volatile struct CMU_tag *)        0xC3E6C280)
#define CMU_3     (*( volatile struct CMU_tag *)        0xC3E6C2C0)
#define CMU_4     (*( volatile struct CMU_tag *)        0xC3E6C300)
#define CMU_5     (*( volatile struct CMU_tag *)        0xC3E6C340)
#define CMU_6     (*( volatile struct CMU_tag *)        0xC3E6C380)
#define CMU_7     (*( volatile struct CMU_tag *)        0xC3E6C3C0)
#define CMU_8     (*( volatile struct CMU_tag *)        0xC3E6C400)

#define FCCU      (*( volatile struct FCCU_tag *)       0xC3F80000)
#define EBI       (*( volatile struct EBI_tag *)        0xC3F84000)
#define SIU       (*( volatile struct SIU_tag *)        0xC3F90000)
#define SIU_B     (*( volatile struct SIU_B_tag *)      0xC3F98000)

#define EMIOS_1   (*( volatile struct EMIOS_tag *)      0xC3FA0000)

#define ESCI_D    (*( volatile struct ESCI_tag *)       0xC3FB0000)
#define ESCI_E    (*( volatile struct ESCI_tag *)       0xC3FB4000)
#define ESCI_F    (*( volatile struct ESCI_tag *)       0xC3FB8000)

#define PMC       (*( volatile struct PMC_tag *)        0xC3FBC000)

#define ETPU         (*( volatile struct ETPU_tag *)       0xC3FC0000)
#define ETPU_AB      (*( volatile struct ETPU_tag *)       0xC3FC0000)
#define ETPU_DATA_RAM         (*( uint32_t *)              0xC3FC8000)
#define ETPU_AB_DATA_RAM      (*( uint32_t *)              0xC3FC8000)
#define ETPU_DATA_RAM_END                                  0xC3FC97FC 
#define ETPU_AB_DATA_RAM_END                               0xC3FC97FC 
#define ETPU_DATA_RAM_EXT     (*( uint32_t *)              0xC3FCC000)
#define ETPU_AB_DATA_RAM_EXT  (*( uint32_t *)              0xC3FCC000)
#define CODE_RAM              (*( uint32_t *)              0xC3FD0000)
#define AB_CODE_RAM           (*( uint32_t *)              0xC3FD0000)
#define ETPU_CODE_RAM         (*( uint32_t *)              0xC3FD0000)
#define ETPU_AB_CODE_RAM      (*( uint32_t *)              0xC3FD0000)

#define DSPI_D    (*( volatile struct DSPI_tag *)       0xC3FDC000)
#define DSPI_E    (*( volatile struct DSPI_tag *)       0xC3FE0000)

#define PIT       (*( volatile struct PIT_tag *)        0xC3FF0000)
#define STCU2     (*( volatile struct STCU2_tag *)      0xC3FF4000)

#define ETPU_C      (*( volatile struct ETPU_C_tag *)     0xFFE00000)
#define ETPU_C_DATA_RAM      (*( uint32_t *)              0xFFE08000)
#define ETPU_C_DATA_RAM_END                               0xFFE08BFC 
#define ETPU_C_DATA_RAM_EXT  (*( uint32_t *)              0xFFE0C000)
#define C_CODE_RAM           (*( uint32_t *)              0xFFE10000)
#define ETPU_C_CODE_RAM      (*( uint32_t *)              0xFFE10000)

#define IGF_0     (*( volatile struct IGF_tag *)        0xFFE20000)        

#define MCAN_0    (*( volatile struct MCAN_tag *)       0xFFE30000)
#define PSI5_0    (*( volatile struct PSI5_tag *)       0xFFE3C000)        

#define SDADC_1   (*( volatile struct SDADC_tag *)      0xFFE44000)
#define SDADC_3   (*( volatile struct SDADC_tag *)      0xFFE48000)

#define SRX_0     (*( volatile struct SRX_tag *)        0xFFE5C000)

#define EMIOS_0   (*( volatile struct EMIOS_tag *)      0xFFE64000)
#define CRC       (*( volatile struct CRC_tag *)        0xFFE68000)
#define SIPI      (*( volatile struct CRC_tag *)        0xFFE6C000)

#define PCS       (*( volatile struct PCS_tag *)        0xFFE70700)
#define PLLDIG    (*( volatile struct PLLDIG_tag *)     0xFFE74000)
#define DTS       (*( volatile struct DTS_tag *)        0xFFE78000)
#define JDC       (*( volatile struct JDC_tag *)        0xFFE7C000)

#define XBAR      (*( volatile struct XBAR_tag *)       0xFFF04000)
#define XBIC      (*( volatile struct XBIC_tag *)       0xFFF08000)
#define MPU_1     (*( volatile struct MPU_tag *)        0xFFF0C000)
#define MPU_0     (*( volatile struct MPU_tag *)        0xFFF10000)
#define MPU       (*( volatile struct MPU_tag *)        0xFFF10000)
#define CSE       (*( volatile struct CSE_tag *)        0xFFF14000)
#define TDM       (*( volatile struct TDM_tag *)        0xFFF18000)
#define SEMA4     (*( volatile struct SEMA4_tag *)      0xFFF24000)
#define SWT_B     (*( volatile struct SWT_tag *)        0xFFF34000)
#define SWT       (*( volatile struct SWT_tag *)        0xFFF38000)
#define SWT_A     (*( volatile struct SWT_tag *)        0xFFF38000)
#define STM       (*( volatile struct STM_tag *)        0xFFF3C000)
#define ECSM      (*( volatile struct ECSM_tag *)       0xFFF40000)
#define EDMA_A    (*( volatile struct EDMA_tag *)       0xFFF44000)
#define INTC      (*( volatile struct INTC_tag *)       0xFFF48000)
#define FEC       (*( volatile struct FEC_tag *)        0xFFF4C000)
#define CCU       (*( volatile struct CCU_tag *)        0xFFF50000)
#define EDMA_B    (*( volatile struct EDMA_tag *)       0xFFF54000)

#define ERM       (*( volatile struct ERM_tag *)        0xFFF60000)
#define EIM       (*( volatile struct EIM_tag *)        0xFFF64000)
#define PFLASH    (*( volatile struct PFLASH_tag *)     0xFFF68000)
#define PCM       (*( volatile struct PCM_tag *)        0xFFF6C000)

#define EQADC_A   (*( volatile struct EQADC_tag *)      0xFFF80000)

#define DECFIL_A   (*( volatile struct DECFIL_tag *)      0xFFF88000)
#define DECFIL_B   (*( volatile struct DECFIL_tag *)      0xFFF88800)
#define DECFIL_C   (*( volatile struct DECFIL_tag *)      0xFFF89000)
#define DECFIL_D   (*( volatile struct DECFIL_tag *)      0xFFF89800)
#define DECFIL_E   (*( volatile struct DECFIL_tag *)      0xFFF8A000)
#define DECFIL_F   (*( volatile struct DECFIL_tag *)      0xFFF8A800)
#define DECFIL_G   (*( volatile struct DECFIL_tag *)      0xFFF8B000)
#define DECFIL_H   (*( volatile struct DECFIL_tag *)      0xFFF8B800)
#define DECFIL_I   (*( volatile struct DECFIL_tag *)      0xFFF8C000)
#define DECFIL_J   (*( volatile struct DECFIL_tag *)      0xFFF8C800)
#define DECFIL_K   (*( volatile struct DECFIL_tag *)      0xFFF8D000)
#define DECFIL_L   (*( volatile struct DECFIL_tag *)      0xFFF8D800)

#define DSPI_A    (*( volatile struct DSPI_tag *)       0xFFF90000)
#define DSPI_B    (*( volatile struct DSPI_tag *)       0xFFF94000)
#define DSPI_C    (*( volatile struct DSPI_tag *)       0xFFF98000)

#define ESCI_A    (*( volatile struct ESCI_tag *)       0xFFFB0000)
#define ESCI_B    (*( volatile struct ESCI_tag *)       0xFFFB4000)
#define ESCI_C    (*( volatile struct ESCI_tag *)       0xFFFB8000)

#define CAN_A     (*( volatile struct FLEXCAN3_tag *)   0xFFFC0000)
#define CAN_B     (*( volatile struct FLEXCAN3_tag *)   0xFFFC4000)

#define LFAST     (*( volatile struct LFAST_tag *)      0xFFFD8000)
#define LFAST_0   (*( volatile struct LFAST_tag *)      0xFFFD8000)

#define C55FMC    (*( volatile struct C55FMC_tag *)     0xFFFE8000)
#define TSENS     (*( volatile struct TSENS_tag *)      0xFFFEC000)

#define PASS      (*( volatile struct PASS_tag *)       0xFFFF4000)
#define SSCM      (*( volatile struct SSCM_tag *)       0xFFFF8000)

#ifdef __MWERKS__
#pragma pop
#endif

#ifdef  __cplusplus
}
#endif
#endif                          /* ifdef _MPC567xR_H */
/*********************************************************************
 *
 * Copyright:
 *  Freescale Semiconductor, INC. All Rights Reserved.
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Freescale
 *  Semiconductor, Inc. This software is provided on an "AS IS"
 *  basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, Freescale
 *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
 *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
 *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
 *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
 *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
 *
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
 *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
 *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
 *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
 *
 *  Freescale Semiconductor assumes no responsibility for the
 *  maintenance and support of this software
 *
 ********************************************************************/