/**
*   @file           Mcl_Dma_Types.h
*   @version        1.0.0
*
*   @brief          AUTOSAR Mcl - Dma data types header file.
*   @details        Dma defines, types used by MCL driver.
*
*   @addtogroup     MCL_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifndef MCL_DMA_TYPES_H
#define MCL_DMA_TYPES_H

#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section Mcl_Dma_Types_h_REF_1
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Macros are used only in some configurations or for future releases or for the client.
*/

/*===============================================================================================
                                         INCLUDE FILES
 1) system and project includes
 2) needed interfaces from external units
 3) internal and external interfaces from this unit
===============================================================================================*/
#include "Std_Types.h"
#include "CDD_Mcl_Cfg.h"

#include "Soc_Ips.h"
/*===============================================================================================
                               SOURCE FILE VERSION INFORMATION
===============================================================================================*/
/**
* @{
* @file           Mcl_Dma_Types.h
* @requirements
*/
#define MCL_DMA_TYPES_VENDOR_ID                        43
#define MCL_DMA_TYPES_AR_RELEASE_MAJOR_VERSION         4
#define MCL_DMA_TYPES_AR_RELEASE_MINOR_VERSION         3
#define MCL_DMA_TYPES_AR_RELEASE_REVISION_VERSION      1
#define MCL_DMA_TYPES_SW_MAJOR_VERSION                 1
#define MCL_DMA_TYPES_SW_MINOR_VERSION                 0
#define MCL_DMA_TYPES_SW_PATCH_VERSION                 0
/** @} */
/*===============================================================================================
                                      FILE VERSION CHECKS
===============================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if source file and Std_Types.h are of the same Autosar version */
    #if ((MCL_DMA_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
         (MCL_DMA_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Mcl_Dma_Types.h and Std_Types.h are different"
    #endif
#endif

/* Check if header file and CDD_Mcl_Cfg.h header file are of the same vendor */
#if (MCL_DMA_TYPES_VENDOR_ID != MCL_VENDOR_ID_CFG)
    #error "Mcl_Dma_Types.h and CDD_Mcl_Cfg.h have different vendor ids"
#endif
/* Check if header file and CDD_Mcl_Cfg.h header file are of the same Autosar version */
#if ((MCL_DMA_TYPES_AR_RELEASE_MAJOR_VERSION    != MCL_AR_RELEASE_MAJOR_VERSION_CFG) || \
     (MCL_DMA_TYPES_AR_RELEASE_MINOR_VERSION    != MCL_AR_RELEASE_MINOR_VERSION_CFG) || \
     (MCL_DMA_TYPES_AR_RELEASE_REVISION_VERSION != MCL_AR_RELEASE_REVISION_VERSION_CFG))
    #error "AutoSar Version Numbers of Mcl_Dma_Types.h and CDD_Mcl_Cfg.h are different"
#endif
/* Check if header file and CDD_Mcl_Cfg.h header file are of the same software version */
#if ((MCL_DMA_TYPES_SW_MAJOR_VERSION != MCL_SW_MAJOR_VERSION_CFG) || \
     (MCL_DMA_TYPES_SW_MINOR_VERSION != MCL_SW_MINOR_VERSION_CFG) || \
     (MCL_DMA_TYPES_SW_PATCH_VERSION != MCL_SW_PATCH_VERSION_CFG))
    #error "Software Version Numbers of Mcl_Dma_Types.h and CDD_Mcl_Cfg.h are different"
#endif

#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if header file and Soc_Ips.h header file are of the same Autosar version */
    #if ((SOC_IPS_AR_RELEASE_MAJOR_VERSION != MCL_DMA_TYPES_AR_RELEASE_MAJOR_VERSION) || \
         (SOC_IPS_AR_RELEASE_MINOR_VERSION != MCL_DMA_TYPES_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Soc_Ips.h and Mcl_Dma_Types.h are different"
    #endif
#endif
/*===============================================================================================
                                           CONSTANTS
===============================================================================================*/


/*===============================================================================================
                                       DEFINES AND MACROS
===============================================================================================*/

#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)
/**
* @{
* @brief          defines used for Mcl_DmaInstanceType
*/
#define DMA_INSTANCE0        (0U)
#define DMA_INSTANCE1        (1U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_INSTANCE2        (2U)

/**
* @{
* @brief          defines used for Mcl_DmaChannelType
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_0       (0U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_1       (1U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_2       (2U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_3       (3U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_4       (4U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_5       (5U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_6       (6U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_7       (7U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_8       (8U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_9       (9U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_10      (10U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_11      (11U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_12      (12U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_13      (13U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_14      (14U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_15      (15U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_16      (16U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_17      (17U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_18      (18U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_19      (19U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_20      (20U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_21      (21U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_22      (22U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_23      (23U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_24      (24U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_25      (25U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_26      (26U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_27      (27U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_28      (28U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_29      (29U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_30      (30U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_31      (31U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_32      (32U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_33      (33U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_34      (34U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_35      (35U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_36      (36U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_37      (37U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_38      (38U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_39      (39U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_40      (40U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_41      (41U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_42      (42U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_43      (43U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_44      (44U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_45      (45U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_46      (46U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_47      (47U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_48      (48U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_49      (49U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_50      (50U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_51      (51U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_52      (52U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_53      (53U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_54      (54U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_55      (55U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_56      (56U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_57      (57U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_58      (58U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_59      (59U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_60      (60U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_61      (61U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_62      (62U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_63      (63U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_64      (64U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_65      (65U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_66      (66U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_67      (67U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_68      (68U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_69      (69U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_70      (70U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_71      (71U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_72      (72U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_73      (73U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_74      (74U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_75      (75U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_76      (76U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_77      (77U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_78      (78U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_79      (79U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_80      (80U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_81      (81U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_82      (82U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_83      (83U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_84      (84U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_85      (85U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_86      (86U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_87      (87U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_88      (88U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_89      (89U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_90      (90U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_91      (91U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_92      (92U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_93      (93U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_94      (94U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_95      (95U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_96      (96U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_97      (97U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_98      (98U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_99      (99U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_100      (100U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_101      (101U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_102      (102U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_103      (103U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_104      (104U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_105      (105U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_106      (106U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_107      (107U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_108      (108U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_109      (109U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_110      (110U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_111      (111U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_112      (112U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_113      (113U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_114      (114U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_115      (115U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_116      (116U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_117      (117U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_118      (118U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_119      (119U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_120      (120U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_121      (121U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_122      (122U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_123      (123U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_124      (124U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_125     (125U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_126     (126U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HW_CHANNEL_127     (127U)

/** 
* @brief DMA_CR[EMLM] possible values.
*/ 
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_MINOR_LOOP_MAPPING_EN_U32              ((uint32)(0x00000080U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_MINOR_LOOP_MAPPING_DIS_U32             ((uint32)(0x00000000U))

/**
* @brief define the DMA usage
*/
#define DMA_INSTANCE_USED         (0x1U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_INSTANCE_NOT_USED     (0x0U)
/**
* @brief  offsets used to increment the source and destination addresses
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_OFFSET_8_BITS       (0x00000001UL)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_OFFSET_16_BITS      (0x00000002UL)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_OFFSET_32_BITS      (0x00000004UL)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_OFFSET_64_BITS      (0x00000008UL)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_OFFSET_128_BITS     (0x00000010UL)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_OFFSET_256_BITS     (0x00000020UL)

/**
* @brief define the DMA MODULES
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MODULE0     (0x0UL)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MODULE1     (0x1UL)


#define DMA_SMOD_MASK_U32           ((uint32)(0x1FUL))
#define DMA_SSIZE_MASK_U32          ((uint32)(0x7UL))
#define DMA_DMOD_MASK_U32           ((uint32)(0x1FUL))
#define DMA_DSIZE_MASK_U32          ((uint32)(0x7UL))
#define DMA_SOFF_MASK_U32           ((uint32)(0xFFFFUL))
#define DMA_CITER_MASK_U32          ((uint32)(0xFFFFUL))

#define DMA_CITER_MASK_ON_U16       ((uint16)(0x01FFU))
#define DMA_CITER_MASK_ON_U32       ((uint32)(0x01FFUL))
#define DMA_CITER_MASK_OFF_U16      ((uint16)(0x7FFFU))
#define DMA_CITER_MASK_OFF_U32      ((uint32)(0x7FFFUL))

#define DMA_DOFF_MASK_U32           ((uint32)(0xFFFFUL))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_BITER_MASK_U32          ((uint32)(0xFFFFUL))
#define DMA_BITER_MASK_ON_U32       ((uint32)(0x01FFUL))
#define DMA_BITER_MASK_OFF_U32      ((uint32)(0x7FFFUL))
#if (MCL_DMA_INSTANCE_CHANNELS_NO == 0x40U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MAJOR_LINKCH_MASK_U32   ((uint32)(0x3FUL))
#else
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MAJOR_LINKCH_MASK_U32   ((uint32)(0x1FUL))
#endif
#define DMAV2_PRIORITY_MASK_U8        ((uint8)(0xFUL))
#define DMAV3_PRIORITY_MASK_U32       ((uint32)(0xC0000007UL))

/**
* @brief TCD fields shift masks
*/
#define DMA_SMOD_SHIFT_MASK_U32         ((uint32)(27UL))
#define DMA_SSIZE_SHIFT_MASK_U32        ((uint32)(24UL))
#define DMA_DMOD_SHIFT_MASK_U32         ((uint32)(19UL))
#define DMA_DSIZE_SHIFT_MASK_U32        ((uint32)(16UL))
#define DMA_ITER_SHIFT_MASK_U32         ((uint32)(16UL))

/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MAJOR_LINKCH_SHIFT_MASK_U32 ((uint32)(8UL))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_ITER_LINKCH_SHIFT_MASK_U32  ((uint32)(25UL))

/**
* @brief this is the implicit value of DMACR register, after a reset.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMACR_RESET_VALUE_U32       ((uint32)(0x00000400UL))

/**
* @brief DMA_CR[CX] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_CANCEL_TRANSFER_EN_U32                 ((uint32)(0x00020000U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CANCEL_TRANSFER_EN_U32                 ((uint32)(0x00000200U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_CANCEL_TRANSFER_DIS_U32                  ((uint32)(0x00000000U))

/**
* @brief DMA_CR[ECX] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ERROR_CANCEL_TRANSFER_EN_U32           ((uint32)(0x00010000U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_ERROR_CANCEL_TRANSFER_EN_U32           ((uint32)(0x00000100U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_ERROR_CANCEL_TRANSFER_DIS_U32            ((uint32)(0x00000000U))

/**
* @brief DMA_CSR[EBW] possible values. Available only for eDMAv3 instances.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_BUFFER_WRITES_EN_U32                   ((uint32)(0x00000001U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_BUFFER_WRITES_DIS_U32                  ((uint32)(0x00000000U))

/**
* @brief DMA_CSR[GMRC] possible values. Available only for eDMAv3 instances.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_GMRC_EN_U32                            ((uint32)(0x00000080U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_GMRC_DIS_U32                           ((uint32)(0x00000000U))

/**
* @brief DMA_CR[GRP0PRI] shift value.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_CHANNEL_GROUP_0_PRIORITY_SHIFT_U8        ((uint8)(8))
/**
* @brief DMA_CR[GRP1PRI] shift value.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_CHANNEL_GROUP_1_PRIORITY_SHIFT_U8        ((uint8)(10))


#if (MCL_DMA_INSTANCE_CHANNELS_NO == 0x40U)
/**
* @brief DMA_CR[GRP2PRI] shift value.
*/
#define DMA_CHANNEL_GROUP_2_PRIORITY_SHIFT_U8        ((uint8)(12))
/**
* @brief DMA_CR[GRP3PRI] shift value.
*/
#define DMA_CHANNEL_GROUP_3_PRIORITY_SHIFT_U8        ((uint8)(14))
#endif

/**
* @brief DMA_CR[EMLM] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MINOR_LOOP_MAPPING_EN_U32                ((uint32)(0x00000080U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MINOR_LOOP_MAPPING_DIS_U32               ((uint32)(0x00000000U))

/**
* @brief Channel linking - DMA_CR[CLM] for eDMA2 or DMA_CSR[GCLC] for eDMA3 possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_CH_LINK_EN_U32                           ((uint32)(0x00000040U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_CH_LINK_DIS_U32                          ((uint32)(0x00000000U))

/**
* @brief DMA_CR[HALT] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HALT_OPERATIONS_EN_U32                   ((uint32)(0x00000020U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HALT_OPERATIONS_DIS_U32                  ((uint32)(0x00000000U))

/**
* @brief DMA_CR[HOE] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HALT_ON_ERROR_EN_U32                     ((uint32)(0x00000010U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_HALT_ON_ERROR_DIS_U32                    ((uint32)(0x00000000U))

/**
* @brief DMA_CR[ERGA] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_ROUND_ROBIN_GROUP_ARB_EN_U32             ((uint32)(0x00000008U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_ROUND_ROBIN_GROUP_ARB_DIS_U32            ((uint32)(0x00000000U))

/**
* @brief DMA_CR[ERCA] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_ROUND_ROBIN_ARB_EN_U32                   ((uint32)(0x00000004U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_ROUND_ROBIN_ARB_DIS_U32                  ((uint32)(0x00000000U))

/**
* @brief DMA_CR[EDBG] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_DEBUG_EN_U32                             ((uint32)(0x00000002U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_DEBUG_DIS_U32                            ((uint32)(0x00000000U))

/**
* @brief DMA_CR[EBW] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_BUFFERED_WRITE_EN_U32                    ((uint32)(0x00000001U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_BUFFERED_WRITE_DIS_U32                   ((uint32)(0x00000000U))

/**
* @brief DMAV2_DCHPRIn[ECP] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ECP_EN_U32                             ((uint32)(0x80U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_ECP_DIS_U32                            ((uint32)(0x00U))
/**
* @brief DMAV3_CHnPRI[ECP] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_ECP_EN_U32                             ((uint32)(0x80000000U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_ECP_DIS_U32                            ((uint32)(0x00000000U))

/**
* @brief DMAV2_DCHPRIn[DPA] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_DPA_EN_U32                             ((uint32)(0x40U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_DPA_DIS_U32                            ((uint32)(0x00U))

/**
* @brief DMAV3_CHnPRI[DPA] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_DPA_EN_U32                             ((uint32)(0x40000000U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_DPA_DIS_U32                            ((uint32)(0x00000000U))

/**
* @brief DMAV2_DCHMIDn[EMI] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_EMI_EN_U8                              ((uint8)(0x80U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV2_EMI_DIS_U8                             ((uint8)(0x00U))

/**
* @brief DMAV3_CHnPRI[EMI] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_EMI_EN_U32                             ((uint32)(0x00010000U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_EMI_DIS_U32                            ((uint32)(0x00000000U))

/**
* @brief DMAV2_EARS[EDREQx] possible values.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_EDREQ_EN_U32                             ((uint32)(0x01UL))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_EDREQ_DIS_U32                            ((uint32)(0x00UL))
/**
* @brief Priority Values
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_0_U8                            ((uint8)(0x00U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_1_U8                            ((uint8)(0x01U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_2_U8                            ((uint8)(0x02U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_3_U8                            ((uint8)(0x03U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_4_U8                            ((uint8)(0x04U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_5_U8                            ((uint8)(0x05U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_6_U8                            ((uint8)(0x06U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_7_U8                            ((uint8)(0x07U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_8_U8                            ((uint8)(0x08U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_9_U8                            ((uint8)(0x09U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_10_U8                           ((uint8)(0x0aU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_11_U8                           ((uint8)(0x0bU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_12_U8                           ((uint8)(0x0cU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_13_U8                           ((uint8)(0x0dU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_14_U8                           ((uint8)(0x0eU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_15_U8                           ((uint8)(0x0fU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_16_U8                           ((uint8)(0x10U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_17_U8                           ((uint8)(0x11U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_18_U8                           ((uint8)(0x12U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_19_U8                           ((uint8)(0x13U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_20_U8                           ((uint8)(0x14U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_21_U8                           ((uint8)(0x15U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_22_U8                           ((uint8)(0x16U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_23_U8                           ((uint8)(0x17U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_24_U8                           ((uint8)(0x18U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_25_U8                           ((uint8)(0x19U))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_26_U8                           ((uint8)(0x1aU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_27_U8                           ((uint8)(0x1bU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_28_U8                           ((uint8)(0x1cU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_29_U8                           ((uint8)(0x1dU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_30_U8                           ((uint8)(0x1eU))
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_PRIORITY_31_U8                           ((uint8)(0x1fU))

/**
* @{
* @brief TCD Word8 bit masks for flags.
*/

#define DMA_TCD_ACTIVE_U8           ((uint8)0x40U)
#define DMA_TCD_ACTIVE_U32          ((uint32)DMA_TCD_ACTIVE_U8)

/**
* @{
* @brief flag for TCD Word8 bit DONE, it only exist on DMAV2
*/
#define DMA_TCD_DONE_U8             ((uint8)0x80U)
#define DMA_TCD_DONE_U32            ((uint32)DMA_TCD_DONE_U8)

#define DMA_TCD_MAJOR_E_LINK_U8     ((uint8)0x20U)
#define DMA_TCD_MAJOR_E_LINK_U32    ((uint32)DMA_TCD_MAJOR_E_LINK_U8)

#define DMA_TCD_E_SG_U8             ((uint8)0x10U)
#define DMA_TCD_E_SG_U32            ((uint32)DMA_TCD_E_SG_U8)

/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DISABLE_REQ_U8      ((uint8)0x08U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_DISABLE_REQ_U32     ((uint32)DMA_TCD_DISABLE_REQ_U8)

#define DMA_TCD_INT_HALF_U8         ((uint8)0x04U)
#define DMA_TCD_INT_HALF_U32        ((uint32)DMA_TCD_INT_HALF_U8)

#define DMA_TCD_INT_MAJOR_U8        ((uint8)0x02U)
#define DMA_TCD_INT_MAJOR_U32       ((uint32)DMA_TCD_INT_MAJOR_U8)

#define DMA_TCD_START_U8            ((uint8)0x01U)
#define DMA_TCD_START_U32           ((uint32)DMA_TCD_START_U8)
/**
* @{
* @brief flag for TCD Word8 bit ESDA, it only exist on DMAV3
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_ESDA_U8             ((uint8)0x80U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_ESDA_U32            ((uint32)DMA_TCD_ESDA_U8)

/**
* @{
* @brief flag for TCD Word8 bit EEOP, it only exist on DMAV3
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_EEOP_U8             ((uint8)0x40U)
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_EEOP_U32            ((uint32)DMA_TCD_EEOP_U8)

/**
* @brief For DMA TCDs which do not use e_link field, major loop iteration count is on 15 bits.
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MAX_UNLINKED_ITER_CNT_U16       (0x7FFFu)
/**
* @brief For DMA TCDs using e_link field, major loop iteration count is on 9 bits
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMA_MAX_LINKED_ITER_CNT_U16         (0x1FFu)

#if ((MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON) || (MCL_DMA_GET_CH_ERR_STATUS_API == STD_ON))
/**
* @brief For getting the DMA error status,the define is used when no channel should be reported
*/
#define MCL_DMA_NO_CHANNEL_U16              (65535U)
#endif
/**
* @brief For getting the DMA error status,the define is used when no channel should be reported
*/
/* @violates @ref Mcl_Dma_Types_h_REF_1 MISRA 2012 Advisory 2.5*/
#define MCL_DMA_CHANNEL_NOT_CONFIGURED_U8   (255U)
/*===============================================================================================
                                             ENUMS
===============================================================================================*/
/**
* @brief      Dma notification configuration structure
*/
typedef enum
{
    /** @brief A notification will be generated when major iteration count completes */
    MCL_DMA_TRANSFER_COMPLETE = 0,
    /** @brief A notification will be generated when major counter is half complete */
    MCL_DMA_TRANSFER_HALF_COMPLETE
} Mcl_DmaTransferNotifType;

/**
* @brief      Dma transfer size structure
*/
typedef enum
{
#ifdef MCL_TRANSFER_SIZE_1_BYTE
    DMA_SIZE_1BYTE = 0 /** @brief Transfer size 1 byte */
#endif
#ifdef MCL_TRANSFER_SIZE_2_BYTE
    ,DMA_SIZE_2BYTES = 1 /** @brief Transfer size 2 bytes */
#endif
#ifdef MCL_TRANSFER_SIZE_4_BYTE
    ,DMA_SIZE_4BYTES = 2 /** @brief Transfer size 4 bytes */
#endif
#ifdef MCL_TRANSFER_SIZE_8_BYTE
    ,DMA_SIZE_8BYTES = 3 /** @brief Transfer size 8 bytes */
#endif
#ifdef MCL_TRANSFER_SIZE_16_BYTE
    ,DMA_SIZE_16BYTES = 4 /** @brief Transfer size 16 bytes */
#endif
#ifdef MCL_TRANSFER_SIZE_32_BYTE
    ,DMA_SIZE_32BYTES = 5 /** @brief Transfer size 32 bytes */
#endif
#ifdef MCL_TRANSFER_SIZE_64_BYTE
    ,DMA_SIZE_64BYTES = 6 /** @brief Transfer size 64 bytes */
#endif
} Mcl_DmaSizeType;

/*===============================================================================================
                                 STRUCTURES AND OTHER TYPEDEFS
===============================================================================================*/
#if (MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON)
/**
 * @brief          Mcl_DmaErroneousChannelType the numeric ID of a Mcl logic channel
 * */
typedef uint16  Mcl_DmaErroneousChannelType;
#endif
/**
 * @brief          Mcl_DmaChannelErrorStatusType provides the numeric ID of a Mcl DMA error
 * */
typedef enum
{
    MCL_DMA_NO_ERROR = 0,
    MCL_DMA_HW_INCONSISTENCY_ERROR = 1,
    MCL_DMA_ECC_ERROR = 2,
    MCL_DMA_BUS_ERROR = 3,
    MCL_DMA_DESCRIPTOR_ERROR = 4,
    MCL_DMA_PRIORITY_ERROR = 5,
    MCL_DMA_UNRECOGNIZED_ERROR = 6,
    MCL_DMA_MEM_SYNC_ERROR = 7
}Mcl_DmaChannelErrorStatusType;
/**
 * @brief          Mcl_DmaRequestType provides the request for AAPIs which get info from hardware
 * */
typedef enum
{
    MCL_DMA_GET_ERR = 0,
    MCL_DMA_GET_INT
}Mcl_DmaRequestType;
/**
* @brief      Mcl high level report error structure
*
*/
#if (MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON)
typedef struct {
    Mcl_DmaErroneousChannelType    erroneousChannel;
    Mcl_DmaChannelErrorStatusType  errorId;
}Mcl_DmaGlobalErrorStatusType;
#endif
/**
 * @brief          The Mcl_DmaVersionType contains the DMA version information
 *                 (whether eDMA2 or eDMA3 IP version is used) */
typedef enum
{
    MCL_EDMA_V2 = 2U,
    MCL_EDMA_V3 = 3U
}Mcl_DmaVersionType;

/**
 * @brief          Type for specifing the DMA channel's priority
 */
typedef uint32              Mcl_DmaPriorityType;
/**
 * @brief          This gives the numeric ID (hardware channel number) of an DMA channel
 * */
typedef uint8               Mcl_DmaChannelType;

/**
 * @brief          The Mcl_DmaMasterIdType contains DMA_SBR EMI configuration
 * */
typedef uint32              Mcl_DmaMasterIdType;

/**
 * @brief          The Dma_ControlType contains DMA CR configuration
 * */
typedef uint32              Mcl_DmaControlType;

/**
 * @brief          The DMA_TCDType contains combined bit fields for the channel's TCD
 *
 * */
typedef uint32              Mcl_DmaTcdType;
/**
 * @brief          The Mcl_DmaInstanceType contains he DMA instance number
 *
 * */
typedef uint8               Mcl_DmaInstanceType;
/**
 * @brief          The Mcl_DmaUsedType contains the DMA usage information (whether DMA is used in configuration or not)
 *
 * */
typedef uint8               Mcl_DmaUsedType;

/**
* @brief      Dma channel configuration structure
*/
typedef struct
{
    /** @brief Channel ECP, DPA and Priority */
    CONST(Mcl_DmaPriorityType, MCL_CONST) Dma_ChannelPriority;
    /** @brief Channel ECP, DPA and Priority */
    CONST(Mcl_DmaPriorityType, MCL_CONST) Dma_ChannelGroupPriority;
    /** @brief eDma channel used */
    CONST(Mcl_DmaChannelType,  MCL_CONST) Dma_Channel;
    /** @brief eDma channel master ID replication */
    CONST(Mcl_DmaMasterIdType, MCL_CONST) Dma_MasterId;
#ifdef MCL_DMA_SETUP_EARS
#if (MCL_DMA_SETUP_EARS == STD_ON)
    /** @brief Enable Asynchronous Request in Stop Register */
    CONST(uint32,  MCL_CONST) Dma_AsynchronousRequest;
#endif
#endif
} Mcl_DmaChannelConfigType;

typedef struct
{
    /** @brief Dma CR Configuration */
    CONST(Mcl_DmaControlType, MCL_CONST)         pDmaControl;
    /** @brief version of the Dma hardware IP */
    CONST(Mcl_DmaVersionType, MCL_CONST)         dmaVersion;
    /** @brief Dma Usage in Configuration */
    CONST(Mcl_DmaUsedType, MCL_CONST)            pDmaUsed;
} Mcl_DmaConfigInstanceType;

#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
typedef struct
{
    CONST(uint32,  MCL_CONST)                   MclLogicalAddrStart;
    CONST(uint32,  MCL_CONST)                   MclLogicalAddrEnd;
    CONST(uint32,  MCL_CONST)                   MclPhysicalAddrStart;
    CONST(uint32,  MCL_CONST)                   MclPhysicalAddrEnd;
} Mcl_LogicalMemorySectionConfigType;

typedef struct
{
    CONST(uint16,  MCL_CONST)                               NumOfSection;
    CONST(Mcl_LogicalMemorySectionConfigType, MCL_CONST)    (* const pSectionConfig)[];
} Mcl_LogicalMemoryConfigType;
#endif /*MCL_LOGICAL_ADDRESS_USED == STD_ON*/

/**
* @brief      Dma configuration structure
*/

typedef struct
{
    /** @brief Number of eDma channels in the Mcl configuration */
    CONST(Mcl_DmaChannelType, MCL_CONST)        NumChannels;
    /** @brief Pointer to the configured channels for eDma */
    CONST(Mcl_DmaConfigInstanceType, MCL_CONST) (* const pDmaConfigInstance)[];
    /** @brief Pointer to the configured channels for eDma */
    CONST(Mcl_DmaChannelConfigType, MCL_CONST)  (* const pChannelsConfig)[];
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    P2CONST( Mcl_LogicalMemoryConfigType, MCL_VAR, MCL_APPL_CONST)       pMclLogicalMemoryConfig;
#endif
} Mcl_DmaConfigType;


/**
* @brief structure used for a basic configuration of a TCD
*/
typedef struct
{
    VAR(uint32, AUTOMATIC) u32saddr;                     /** @brief source address */
    VAR(uint32, AUTOMATIC) u32daddr;                     /** @brief destination address */
    VAR(uint32, AUTOMATIC) u32ssize;                     /** @brief source transfer size */
    VAR(uint32, AUTOMATIC) u32dsize;                     /** @brief destination transfer size */
    VAR(uint32, AUTOMATIC) u32soff;                      /** @brief source address offset */
    VAR(uint32, AUTOMATIC) u32doff;                      /** @brief destination address offset */
    VAR(uint32, AUTOMATIC) u32smod;                      /** @brief source address modulo */
    VAR(uint32, AUTOMATIC) u32dmod;                      /** @brief destination address modulo */
    VAR(uint32, AUTOMATIC) u32num_bytes;                 /** @brief number of bytes to be transferred */
    VAR(uint32, AUTOMATIC) u32iter;                      /** @brief iteration count */
}Mcl_DmaTcdAttributesType;

#endif
#endif
/*===============================================================================================
                                 GLOBAL VARIABLE DECLARATIONS
===============================================================================================*/

/*===============================================================================================
*                                     FUNCTION PROTOTYPES
===============================================================================================*/

#ifdef __cplusplus
}
#endif

#endif /* MCL_DMA_TYPES_H */
/** @} */
