/**
*   @ file    Cobra55_Resource.m
*   @ version 1.0.0
*
*   @ brief   AUTOSAR Port - Resource for this platform
*   @ details Resource for this platform
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : SIU,IGF
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
[!IF "not(var:defined('PORT_RESOURCE_M'))"!]
[!VAR "PORT_RESOURCE_M"="'true'"!]
[!VAR "PinMap"!]
FlexCAN_A_CNTXA_PORT83;1:OUT@[!//
eSCI_A_TXDA_PORT83;6:INOUT@[!//
MCAN_0_TX_OUT_PORT83;3:OUT@[!//
FlexCAN_A_CNRXA_PORT84;1:IN@[!//
eSCI_A_RXDA_PORT84;6:IN@[!//
MCAN_0_RX_IN_PORT84;7:IN@[!//
FlexCAN_B_CNTXB_PORT85;1:OUT@[!//
DSPI_C_PCSC3_PORT85;2:OUT@[!//
FlexCAN_B_CNRXB_PORT86;1:IN@[!//
DSPI_C_PCSC4_PORT86;2:OUT@[!//
FlexCAN_C_CNTXC_PORT87;1:OUT@[!//
DSPI_D_PCSD3_PORT87;2:OUT@[!//
FlexCAN_C_CNRXC_PORT88;1:IN@[!//
DSPI_D_PCSD4_PORT88;2:OUT@[!//
eSCI_E_RXDE_PORT88;3:IN@[!//
eSCI_A_TXDA_PORT89;5:INOUT@[!//
eSCI_A_RXDA_IN_PORT90;5:IN@[!//
eSCI_B_TXDB_PORT91;5:INOUT@[!//
DSPI_D_PCSD1_PORT91;2:OUT@[!//
MCAN_0_RX_IN_PORT91;7:IN@[!//
eSCI_B_RXDB_PORT92;5:IN@[!//
DSPI_D_PCSD5_PORT92;2:OUT@[!//
DSPI_A_SCKA_OUT_PORT93;1:OUT@[!//
DSPI_A_SCKA_IN_PORT93;1:IN@[!//
DSPI_A_SCKA_INOUT_PORT93;1:INOUT@[!//
DSPI_C_PCSC1_PORT93;2:OUT@[!//
MCAN_0_TX_OUT_PORT93;3:OUT@[!//
SENT_B_SENT1_B_IN_PORT93;8:IN@[!//
DSPI_A_SINA_PORT94;1:IN@[!//
DSPI_C_PCSC2_PORT94;2:OUT@[!//
DSPI_A_SOUTA_PORT95;1:OUT@[!//
DSPI_C_PCSC5_PORT95;2:OUT@[!//
DSPI_A_PCSA0_OUT_PORT96;1:OUT@[!//
DSPI_A_PCSA0_IN_PORT96;1:IN@[!//
DSPI_A_PCSA0_INOUT_PORT96;1:INOUT@[!//
DSPI_D_PCSD2_PORT96;2:OUT@[!//
DSPI_A_PCSA1_PORT97;1:OUT@[!//
DSPI_E_PCSE0_OUT_PORT97;2:OUT@[!//
DSPI_E_PCSE0_IN_PORT97;2:IN@[!//
DSPI_E_PCSE0_INOUT_PORT97;2:INOUT@[!//
DSPI_A_PCSA2_PORT98;1:OUT@[!//
DSPI_E_SOUTE_PORT98;2:OUT@[!//
FEC_FEC_TXD2_OUT_PORT98;3:OUT@[!//
FEC_FEC_RXER_IN_PORT98;4:IN@[!//
DSPI_A_PCSA3_PORT99;1:OUT@[!//
DSPI_E_SINE_PORT99;2:IN@[!//
FEC_FEC_MDIO_PORT99;3:INOUT@[!//
eSCI_D_TXDD_PORT99;4:OUT@[!//
DSPI_A_PCSA4_PORT100;1:OUT@[!//
DSPI_E_SCKE_OUT_PORT100;2:OUT@[!//
DSPI_E_SCKE_IN_PORT100;2:IN@[!//
DSPI_E_SCKE_INOUT_PORT100;2:INOUT@[!//
eSCI_E_TXDE_PORT100;7:INOUT@[!//
FEC_FEC_RXCLK_IN_PORT100;4:IN@[!//
DSPI_A_PCSA5_PORT101;1:OUT@[!//
eQADC_A_eQADC_B_ETRIG1_PORT101;2:IN@[!//
eSCI_D_RXDD_PORT101;3:IN@[!//
FEC_FEC_TXD3_OUT_PORT101;4:OUT@[!//
DSPI_B_SCKB_INOUT_PORT102;1:INOUT@[!//
DSPI_B_SCKB_OUT_PORT102;1:OUT@[!//
DSPI_B_SCKB_IN_PORT102;1:IN@[!//
DSPI_B_SINB_PORT103;1:IN@[!//
DSPI_B_SOUTB_PORT104;1:OUT@[!//
DSPI_B_PCSB0_INOUT_PORT105;5:INOUT@[!//
DSPI_D_PCSD2_PORT105;2:OUT@[!//
DSPI_B_PCSB0_OUT_PORT105;1:OUT@[!//
DSPI_B_PCSB0_IN_PORT105;5:IN@[!//
DSPI_B_PCSB1_PORT106;1:OUT@[!//
DSPI_D_PCSD0_INOUT_PORT106;6:INOUT@[!//
DSPI_D_PCSD0_OUT_PORT106;2:OUT@[!//
DSPI_D_PCSD0_IN_PORT106;6:IN@[!//
DSPI_B_PCSB2_PORT107;1:OUT@[!//
DSPI_C_SOUTC_PORT107;2:OUT@[!//
SENT_B_SENT2_B_IN_PORT107;7:IN@[!//
FEC_FEC_RXD3_IN_PORT107;4:IN@[!//
DSPI_B_PCSB3_PORT108;1:OUT@[!//
DSPI_C_SINC_PORT108;6:IN@[!//
SENT_B_SENT3_B_IN_PORT108;7:IN@[!//
DSPI_B_PCSB4_PORT109;1:OUT@[!//
DSPI_C_SCKC_INOUT_PORT109;6:INOUT@[!//
SENT_B_SENT4_B_IN_PORT109;7:IN@[!//
FEC_FEC_MDC_OUT_PORT109;4:OUT@[!//
DSPI_C_SCKC_OUT_PORT109;2:OUT@[!//
DSPI_C_SCKC_IN_PORT109;6:IN@[!//
DSPI_B_PCSB5_PORT110;1:OUT@[!//
DSPI_C_PCSC0_INOUT_PORT110;6:INOUT@[!//
SENT_B_SENT5_B_IN_PORT110;7:IN@[!//
FEC_FEC_RXD2_IN_PORT110;4:IN@[!//
DSPI_C_PCSC0_OUT_PORT110;2:OUT@[!//
DSPI_C_PCSC0_IN_PORT110;6:IN@[!//
eTPU_A_TCRCLKA_PORT113;1:IN@[!//
SIU_A_IRQ7_PORT113;2:IN@[!//
eTPU_A_ETPUA0_INOUT_PORT114;1:INOUT@[!//
eTPU_A_ETPUA12_PORT114;2:OUT@[!//
eTPU_A_ETPUA0_OUT_PORT114;1:OUT@[!//
eTPU_A_ETPUA0_IN_PORT114;1:IN@[!//
eTPU_A_ETPUA1_INOUT_PORT115;1:INOUT@[!//
eTPU_A_ETPUA13_PORT115;2:OUT@[!//
eTPU_A_ETPUA1_OUT_PORT115;1:OUT@[!//
eTPU_A_ETPUA1_IN_PORT115;1:IN@[!//
eTPU_A_ETPUA2_INOUT_PORT116;1:INOUT@[!//
eTPU_A_ETPUA14_PORT116;2:OUT@[!//
REACM_RCH0_A_OUT_PORT116;3:OUT@[!//
eTPU_A_ETPUA2_OUT_PORT116;1:OUT@[!//
eTPU_A_ETPUA2_IN_PORT116;1:IN@[!//
eTPU_A_ETPUA3_INOUT_PORT117;1:INOUT@[!//
eTPU_A_ETPUA15_PORT117;2:OUT@[!//
REACM_RCH1_A_OUT_PORT117;3:OUT@[!//
FCCU_ERROR0_PORT117;4:INOUT@[!//
eTPU_A_ETPUA3_OUT_PORT117;1:OUT@[!//
eTPU_A_ETPUA3_IN_PORT117;1:IN@[!//
eTPU_A_ETPUA4_INOUT_PORT118;1:INOUT@[!//
eTPU_A_ETPUA16_PORT118;2:OUT@[!//
REACM_RCH2_A_OUT_PORT118;3:OUT@[!//
eTPU_A_ETPUA4_OUT_PORT118;1:OUT@[!//
eTPU_A_ETPUA4_IN_PORT118;1:IN@[!//
eTPU_A_ETPUA5_INOUT_PORT119;1:INOUT@[!//
eTPU_A_ETPUA17_PORT119;2:OUT@[!//
REACM_RCH3_A_OUT_PORT119;3:OUT@[!//
eTPU_A_ETPUA5_OUT_PORT119;1:OUT@[!//
eTPU_A_ETPUA5_IN_PORT119;1:IN@[!//
eTPU_A_ETPUA6_INOUT_PORT120;1:INOUT@[!//
eTPU_A_ETPUA18_PORT120;2:OUT@[!//
REACM_RCH4_A_OUT_PORT120;3:OUT@[!//
eTPU_A_ETPUA6_OUT_PORT120;1:OUT@[!//
eTPU_A_ETPUA6_IN_PORT120;1:IN@[!//
eTPU_A_ETPUA7_INOUT_PORT121;1:INOUT@[!//
eTPU_A_ETPUA19_PORT121;2:OUT@[!//
REACM_RCH5_A_OUT_PORT121;3:OUT@[!//
eTPU_A_ETPUA7_OUT_PORT121;1:OUT@[!//
eTPU_A_ETPUA7_IN_PORT121;1:IN@[!//
eTPU_A_ETPUA8_INOUT_PORT122;1:INOUT@[!//
eTPU_A_ETPUA20_PORT122;2:OUT@[!//
REACM_RCH6_A_OUT_PORT122;3:OUT@[!//
eTPU_A_ETPUA8_OUT_PORT122;1:OUT@[!//
eTPU_A_ETPUA8_IN_PORT122;1:IN@[!//
eTPU_A_ETPUA9_INOUT_PORT123;1:INOUT@[!//
eTPU_A_ETPUA21_PORT123;2:OUT@[!//
REACM_RCH7_A_OUT_PORT123;3:OUT@[!//
eTPU_A_ETPUA9_OUT_PORT123;1:OUT@[!//
eTPU_A_ETPUA9_IN_PORT123;1:IN@[!//
eTPU_A_ETPUA10_INOUT_PORT124;1:INOUT@[!//
eTPU_A_ETPUA22_PORT124;2:OUT@[!//
REACM_RCH8_A_OUT_PORT124;3:OUT@[!//
FCCU_ERRORIN_PORT124;4:IN@[!//
eTPU_A_ETPUA10_OUT_PORT124;1:OUT@[!//
eTPU_A_ETPUA10_IN_PORT124;1:IN@[!//
eTPU_A_ETPUA11_INOUT_PORT125;1:INOUT@[!//
eTPU_A_ETPUA23_PORT125;2:OUT@[!//
REACM_RCH9_A_OUT_PORT125;3:OUT@[!//
FCCU_ERROR1_PORT125;4:INOUT@[!//
eTPU_A_ETPUA11_OUT_PORT125;1:OUT@[!//
eTPU_A_ETPUA11_IN_PORT125;1:IN@[!//
eTPU_A_ETPUA12_INOUT_PORT126;1:INOUT@[!//
DSPI_B_PCSB1_PORT126;2:OUT@[!//
eTPU_A_ETPUA12_OUT_PORT126;1:OUT@[!//
eTPU_A_ETPUA12_IN_PORT126;1:IN@[!//
eTPU_A_ETPUA13_INOUT_PORT127;1:INOUT@[!//
DSPI_B_PCSB3_PORT127;2:OUT@[!//
eTPU_A_ETPUA13_OUT_PORT127;1:OUT@[!//
eTPU_A_ETPUA13_IN_PORT127;1:IN@[!//
eTPU_A_ETPUA14_INOUT_PORT128;1:INOUT@[!//
DSPI_B_PCSB4_PORT128;2:OUT@[!//
eTPU_A_ETPUA14_OUT_PORT128;1:OUT@[!//
eTPU_A_ETPUA14_IN_PORT128;1:IN@[!//
eTPU_A_ETPUA15_INOUT_PORT129;1:INOUT@[!//
DSPI_B_PCSB5_PORT129;2:OUT@[!//
MCAN_0_TX_OUT_PORT129;3:OUT@[!//
eTPU_A_ETPUA15_OUT_PORT129;1:OUT@[!//
eTPU_A_ETPUA15_IN_PORT129;1:IN@[!//
eTPU_A_ETPUA16_INOUT_PORT130;1:INOUT@[!//
DSPI_D_PCSD1_PORT130;2:OUT@[!//
eTPU_A_ETPUA16_OUT_PORT130;1:OUT@[!//
eTPU_A_ETPUA16_IN_PORT130;1:IN@[!//
eTPU_A_ETPUA17_INOUT_PORT131;1:INOUT@[!//
DSPI_D_PCSD2_PORT131;2:OUT@[!//
eTPU_A_ETPUA17_OUT_PORT131;1:OUT@[!//
eTPU_A_ETPUA17_IN_PORT131;1:IN@[!//
eTPU_A_ETPUA18_INOUT_PORT132;1:INOUT@[!//
DSPI_D_PCSD3_PORT132;2:OUT@[!//
eTPU_A_ETPUA18_OUT_PORT132;1:OUT@[!//
eTPU_A_ETPUA18_IN_PORT132;1:IN@[!//
eTPU_A_ETPUA19_INOUT_PORT133;1:INOUT@[!//
DSPI_D_PCSD4_PORT133;2:OUT@[!//
MCAN_0_RX_IN_PORT133;7:IN@[!//
eTPU_A_ETPUA19_OUT_PORT133;1:OUT@[!//
eTPU_A_ETPUA19_IN_PORT133;1:IN@[!//
eTPU_A_ETPUA20_INOUT_PORT134;1:INOUT@[!//
SIU_A_IRQ8_PORT134;2:IN@[!//
eTPU_A_ETPUA20_OUT_PORT134;1:OUT@[!//
eTPU_A_ETPUA20_IN_PORT134;1:IN@[!//
eTPU_A_ETPUA21_INOUT_PORT135;1:INOUT@[!//
SIU_A_IRQ9_PORT135;2:IN@[!//
eTPU_A_ETPUA21_OUT_PORT135;1:OUT@[!//
eTPU_A_ETPUA21_IN_PORT135;1:IN@[!//
eTPU_A_ETPUA22_INOUT_PORT136;1:INOUT@[!//
SIU_A_IRQ10_PORT136;2:IN@[!//
REACM_RCH0_A_OUT_PORT136;3:OUT@[!//
eTPU_A_ETPUA22_OUT_PORT136;1:OUT@[!//
eTPU_A_ETPUA22_IN_PORT136;1:IN@[!//
eTPU_A_ETPUA23_INOUT_PORT137;1:INOUT@[!//
SIU_A_IRQ11_PORT137;2:IN@[!//
REACM_RCH1_A_OUT_PORT137;3:OUT@[!//
eTPU_A_ETPUA23_OUT_PORT137;1:OUT@[!//
eTPU_A_ETPUA23_IN_PORT137;1:IN@[!//
eTPU_A_ETPUA24_INOUT_PORT138;5:INOUT@[!//
SIU_A_IRQ12_PORT138;2:IN@[!//
REACM_RCH2_A_OUT_PORT138;3:OUT@[!//
eTPU_A_ETPUA24_OUT_PORT138;1:OUT@[!//
eTPU_A_ETPUA24_IN_PORT138;5:IN@[!//
eTPU_A_ETPUA25_INOUT_PORT139;5:INOUT@[!//
SIU_A_IRQ13_PORT139;2:IN@[!//
REACM_RCH3_A_OUT_PORT139;3:OUT@[!//
eTPU_A_ETPUA25_OUT_PORT139;1:OUT@[!//
eTPU_A_ETPUA25_IN_PORT139;5:IN@[!//
eTPU_A_ETPUA26_INOUT_PORT140;5:INOUT@[!//
SIU_A_IRQ14_PORT140;2:IN@[!//
REACM_RCH4_A_OUT_PORT140;3:OUT@[!//
eTPU_A_ETPUA26_OUT_PORT140;1:OUT@[!//
eTPU_A_ETPUA26_IN_PORT140;5:IN@[!//
eTPU_A_ETPUA27_INOUT_PORT141;5:INOUT@[!//
SIU_A_IRQ15_PORT141;2:IN@[!//
REACM_RCH5_A_OUT_PORT141;3:OUT@[!//
eTPU_A_ETPUA27_OUT_PORT141;1:OUT@[!//
eTPU_A_ETPUA27_IN_PORT141;5:IN@[!//
eTPU_A_ETPUA28_INOUT_PORT142;5:INOUT@[!//
DSPI_C_PCSC1_PORT142;2:OUT@[!//
REACM_RCH6_A_OUT_PORT142;3:OUT@[!//
eTPU_A_ETPUA28_OUT_PORT142;1:OUT@[!//
eTPU_A_ETPUA28_IN_PORT142;5:IN@[!//
eTPU_A_ETPUA29_INOUT_PORT143;5:INOUT@[!//
DSPI_C_PCSC2_PORT143;2:OUT@[!//
REACM_RCH7_A_OUT_PORT143;3:OUT@[!//
eTPU_A_ETPUA29_OUT_PORT143;1:OUT@[!//
eTPU_A_ETPUA29_IN_PORT143;5:IN@[!//
eTPU_A_ETPUA30_INOUT_PORT144;5:INOUT@[!//
DSPI_C_PCSC3_PORT144;2:OUT@[!//
REACM_RCH8_A_OUT_PORT144;3:OUT@[!//
eTPU_A_ETPUA30_OUT_PORT144;1:OUT@[!//
eTPU_A_ETPUA30_IN_PORT144;5:IN@[!//
eTPU_A_ETPUA31_INOUT_PORT145;5:INOUT@[!//
DSPI_C_PCSC4_PORT145;2:OUT@[!//
REACM_RCH9_A_OUT_PORT145;3:OUT@[!//
eTPU_A_ETPUA31_OUT_PORT145;1:OUT@[!//
eTPU_A_ETPUA31_IN_PORT145;5:IN@[!//
eTPU_B_TCRCLKB_PORT146;1:IN@[!//
SIU_A_IRQ6_PORT146;6:IN@[!//
eTPU_B_ETPUB0_INOUT_PORT147;1:INOUT@[!//
eTPU_B_ETPUB16_PORT147;2:OUT@[!//
eTPU_B_ETPUB0_OUT_PORT147;1:OUT@[!//
eTPU_B_ETPUB0_IN_PORT147;1:IN@[!//
eTPU_B_ETPUB1_INOUT_PORT148;1:INOUT@[!//
eTPU_B_ETPUB17_PORT148;2:OUT@[!//
eTPU_B_ETPUB1_OUT_PORT148;1:OUT@[!//
eTPU_B_ETPUB1_IN_PORT148;1:IN@[!//
eTPU_B_ETPUB2_INOUT_PORT149;1:INOUT@[!//
eTPU_B_ETPUB18_PORT149;2:OUT@[!//
eTPU_B_ETPUB2_OUT_PORT149;1:OUT@[!//
eTPU_B_ETPUB2_IN_PORT149;1:IN@[!//
eTPU_B_ETPUB3_INOUT_PORT150;1:INOUT@[!//
eTPU_B_ETPUB19_PORT150;2:OUT@[!//
eTPU_B_ETPUB3_OUT_PORT150;1:OUT@[!//
eTPU_B_ETPUB3_IN_PORT150;1:IN@[!//
eTPU_B_ETPUB4_INOUT_PORT151;1:INOUT@[!//
eTPU_B_ETPUB20_PORT151;2:OUT@[!//
eTPU_B_ETPUB4_OUT_PORT151;1:OUT@[!//
eTPU_B_ETPUB4_IN_PORT151;1:IN@[!//
eTPU_B_ETPUB5_INOUT_PORT152;1:INOUT@[!//
eTPU_B_ETPUB21_PORT152;2:OUT@[!//
eTPU_B_ETPUB5_OUT_PORT152;1:OUT@[!//
eTPU_B_ETPUB5_IN_PORT152;1:IN@[!//
eTPU_B_ETPUB6_INOUT_PORT153;1:INOUT@[!//
eTPU_B_ETPUB22_PORT153;2:OUT@[!//
eTPU_B_ETPUB6_OUT_PORT153;1:OUT@[!//
eTPU_B_ETPUB6_IN_PORT153;1:IN@[!//
eTPU_B_ETPUB7_INOUT_PORT154;1:INOUT@[!//
eTPU_B_ETPUB23_PORT154;2:OUT@[!//
eTPU_B_ETPUB7_OUT_PORT154;1:OUT@[!//
eTPU_B_ETPUB7_IN_PORT154;1:IN@[!//
eTPU_B_ETPUB8_INOUT_PORT155;1:INOUT@[!//
eTPU_B_ETPUB24_PORT155;2:OUT@[!//
eTPU_B_ETPUB8_OUT_PORT155;1:OUT@[!//
eTPU_B_ETPUB8_IN_PORT155;1:IN@[!//
eTPU_B_ETPUB9_INOUT_PORT156;1:INOUT@[!//
eTPU_B_ETPUB25_PORT156;2:OUT@[!//
eTPU_B_ETPUB9_OUT_PORT156;1:OUT@[!//
eTPU_B_ETPUB9_IN_PORT156;1:IN@[!//
eTPU_B_ETPUB10_INOUT_PORT157;1:INOUT@[!//
eTPU_B_ETPUB26_PORT157;2:OUT@[!//
eTPU_B_ETPUB10_OUT_PORT157;1:OUT@[!//
eTPU_B_ETPUB10_IN_PORT157;1:IN@[!//
eTPU_B_ETPUB11_INOUT_PORT158;1:INOUT@[!//
eTPU_B_ETPUB27_PORT158;2:OUT@[!//
eTPU_B_ETPUB11_OUT_PORT158;1:OUT@[!//
eTPU_B_ETPUB11_IN_PORT158;1:IN@[!//
eTPU_B_ETPUB12_INOUT_PORT159;1:INOUT@[!//
eTPU_B_ETPUB28_PORT159;2:OUT@[!//
eTPU_B_ETPUB12_OUT_PORT159;1:OUT@[!//
eTPU_B_ETPUB12_IN_PORT159;1:IN@[!//
eTPU_B_ETPUB13_INOUT_PORT160;1:INOUT@[!//
eTPU_B_ETPUB29_PORT160;2:OUT@[!//
eTPU_B_ETPUB13_OUT_PORT160;1:OUT@[!//
eTPU_B_ETPUB13_IN_PORT160;1:IN@[!//
eTPU_B_ETPUB14_INOUT_PORT161;1:INOUT@[!//
eTPU_B_ETPUB30_PORT161;2:OUT@[!//
eTPU_B_ETPUB14_OUT_PORT161;1:OUT@[!//
eTPU_B_ETPUB14_IN_PORT161;1:IN@[!//
eTPU_B_ETPUB15_INOUT_PORT162;1:INOUT@[!//
eTPU_B_ETPUB31_PORT162;2:OUT@[!//
eTPU_B_ETPUB15_OUT_PORT162;1:OUT@[!//
eTPU_B_ETPUB15_IN_PORT162;1:IN@[!//
eTPU_B_ETPUB16_INOUT_PORT163;1:INOUT@[!//
DSPI_A_PCSA1_PORT163;2:OUT@[!//
eTPU_B_ETPUB16_OUT_PORT163;1:OUT@[!//
eTPU_B_ETPUB16_IN_PORT163;1:IN@[!//
eTPU_B_ETPUB17_INOUT_PORT164;1:INOUT@[!//
DSPI_A_PCSA2_PORT164;2:OUT@[!//
eTPU_B_ETPUB17_OUT_PORT164;1:OUT@[!//
eTPU_B_ETPUB17_IN_PORT164;1:IN@[!//
eTPU_B_ETPUB18_INOUT_PORT165;1:INOUT@[!//
DSPI_A_PCSA3_PORT165;2:OUT@[!//
eTPU_B_ETPUB18_OUT_PORT165;1:OUT@[!//
eTPU_B_ETPUB18_IN_PORT165;1:IN@[!//
eTPU_B_ETPUB19_INOUT_PORT166;1:INOUT@[!//
DSPI_A_PCSA4_PORT166;2:OUT@[!//
eTPU_B_ETPUB19_OUT_PORT166;1:OUT@[!//
eTPU_B_ETPUB19_IN_PORT166;1:IN@[!//
eTPU_B_ETPUB20_INOUT_PORT167;1:INOUT@[!//
eTPU_B_ETPUB20_OUT_PORT167;1:OUT@[!//
eTPU_B_ETPUB20_IN_PORT167;1:IN@[!//
eTPU_B_ETPUB21_INOUT_PORT168;1:INOUT@[!//
eTPU_B_ETPUB21_OUT_PORT168;1:OUT@[!//
eTPU_B_ETPUB21_IN_PORT168;1:IN@[!//
eTPU_B_ETPUB22_INOUT_PORT169;1:INOUT@[!//
REACM_RCH0_B_OUT_PORT169;2:OUT@[!//
eTPU_B_ETPUB22_OUT_PORT169;1:OUT@[!//
eTPU_B_ETPUB22_IN_PORT169;1:IN@[!//
eTPU_B_ETPUB23_INOUT_PORT170;1:INOUT@[!//
REACM_RCH1_B_OUT_PORT170;2:OUT@[!//
eTPU_B_ETPUB23_OUT_PORT170;1:OUT@[!//
eTPU_B_ETPUB23_IN_PORT170;1:IN@[!//
eTPU_B_ETPUB24_INOUT_PORT171;1:INOUT@[!//
REACM_RCH2_B_OUT_PORT171;2:OUT@[!//
eTPU_B_ETPUB24_OUT_PORT171;1:OUT@[!//
eTPU_B_ETPUB24_IN_PORT171;1:IN@[!//
eTPU_B_ETPUB25_INOUT_PORT172;1:INOUT@[!//
REACM_RCH3_B_OUT_PORT172;2:OUT@[!//
eTPU_B_ETPUB25_OUT_PORT172;1:OUT@[!//
eTPU_B_ETPUB25_IN_PORT172;1:IN@[!//
eTPU_B_ETPUB26_INOUT_PORT173;1:INOUT@[!//
REACM_RCH4_B_OUT_PORT173;2:OUT@[!//
eTPU_B_ETPUB26_OUT_PORT173;1:OUT@[!//
eTPU_B_ETPUB26_IN_PORT173;1:IN@[!//
eTPU_B_ETPUB27_INOUT_PORT174;1:INOUT@[!//
REACM_RCH5_B_OUT_PORT174;2:OUT@[!//
eTPU_B_ETPUB27_OUT_PORT174;1:OUT@[!//
eTPU_B_ETPUB27_IN_PORT174;1:IN@[!//
eTPU_B_ETPUB28_INOUT_PORT175;1:INOUT@[!//
REACM_RCH6_B_OUT_PORT175;2:OUT@[!//
eTPU_B_ETPUB28_OUT_PORT175;1:OUT@[!//
eTPU_B_ETPUB28_IN_PORT175;1:IN@[!//
eTPU_B_ETPUB29_INOUT_PORT176;1:INOUT@[!//
REACM_RCH7_B_OUT_PORT176;2:OUT@[!//
eTPU_B_ETPUB29_OUT_PORT176;1:OUT@[!//
eTPU_B_ETPUB29_IN_PORT176;1:IN@[!//
eTPU_B_ETPUB30_INOUT_PORT177;1:INOUT@[!//
REACM_RCH8_B_OUT_PORT177;2:OUT@[!//
eTPU_B_ETPUB30_OUT_PORT177;1:OUT@[!//
eTPU_B_ETPUB30_IN_PORT177;1:IN@[!//
eTPU_B_ETPUB31_INOUT_PORT178;1:INOUT@[!//
REACM_RCH9_B_OUT_PORT178;2:OUT@[!//
eTPU_B_ETPUB31_OUT_PORT178;1:OUT@[!//
eTPU_B_ETPUB31_IN_PORT178;1:IN@[!//
eMIOS_A_EMIOS0_INOUT_PORT179;1:INOUT@[!//
eTPU_A_ETPUA0_PORT179;2:OUT@[!//
REACM_RCH0_C_OUT_PORT179;3:OUT@[!//
eMIOS_A_EMIOS0_OUT_PORT179;1:OUT@[!//
eMIOS_A_EMIOS0_IN_PORT179;1:IN@[!//
eMIOS_A_EMIOS1_INOUT_PORT180;1:INOUT@[!//
eTPU_A_ETPUA1_PORT180;2:OUT@[!//
REACM_RCH1_C_OUT_PORT180;3:OUT@[!//
DSPI_E_PCSE2_PORT180;4:OUT@[!//
eMIOS_A_EMIOS1_OUT_PORT180;1:OUT@[!//
eMIOS_A_EMIOS1_IN_PORT180;1:IN@[!//
eMIOS_A_EMIOS2_INOUT_PORT181;1:INOUT@[!//
eTPU_A_ETPUA2_PORT181;2:OUT@[!//
REACM_RCH2_C_OUT_PORT181;3:OUT@[!//
DSPI_E_PCSE3_PORT181;4:OUT@[!//
eMIOS_A_EMIOS2_OUT_PORT181;1:OUT@[!//
eMIOS_A_EMIOS2_IN_PORT181;1:IN@[!//
eMIOS_A_EMIOS3_INOUT_PORT182;1:INOUT@[!//
eTPU_A_ETPUA3_PORT182;2:OUT@[!//
REACM_RCH3_C_OUT_PORT182;3:OUT@[!//
DSPI_E_PCSE4_PORT182;4:OUT@[!//
eMIOS_A_EMIOS3_OUT_PORT182;1:OUT@[!//
eMIOS_A_EMIOS3_IN_PORT182;1:IN@[!//
eMIOS_A_EMIOS4_PORT183;1:OUT@[!//
eTPU_A_ETPUA4_PORT183;2:OUT@[!//
REACM_RCH4_C_OUT_PORT183;3:OUT@[!//
DSPI_E_PCSE5_PORT183;4:OUT@[!//
eMIOS_A_EMIOS5_PORT184;1:OUT@[!//
eTPU_A_ETPUA5_PORT184;2:OUT@[!//
REACM_RCH5_C_OUT_PORT184;3:OUT@[!//
eMIOS_A_EMIOS6_INOUT_PORT185;1:INOUT@[!//
eTPU_A_ETPUA6_PORT185;2:OUT@[!//
REACM_RCH6_C_OUT_PORT185;3:OUT@[!//
eMIOS_A_EMIOS6_OUT_PORT185;1:OUT@[!//
eMIOS_A_EMIOS6_IN_PORT185;1:IN@[!//
eMIOS_A_EMIOS7_INOUT_PORT186;1:INOUT@[!//
eTPU_A_ETPUA7_PORT186;2:OUT@[!//
REACM_RCH7_C_OUT_PORT186;3:OUT@[!//
eMIOS_A_EMIOS7_OUT_PORT186;1:OUT@[!//
eMIOS_A_EMIOS7_IN_PORT186;1:IN@[!//
eMIOS_B_EMIOS0_INOUT_PORT187;1:INOUT@[!//
eTPU_A_ETPUA8_PORT187;2:OUT@[!//
REACM_RCH8_C_OUT_PORT187;3:OUT@[!//
eMIOS_B_EMIOS0_OUT_PORT187;1:OUT@[!//
eMIOS_B_EMIOS0_IN_PORT187;1:IN@[!//
eMIOS_B_EMIOS1_INOUT_PORT188;1:INOUT@[!//
eTPU_A_ETPUA9_PORT188;2:OUT@[!//
REACM_RCH9_C_OUT_PORT188;3:OUT@[!//
eMIOS_B_EMIOS1_OUT_PORT188;1:OUT@[!//
eMIOS_B_EMIOS1_IN_PORT188;1:IN@[!//
eMIOS_B_EMIOS2_INOUT_PORT189;1:INOUT@[!//
DSPI_D_SCKD_INOUT_PORT189;6:INOUT@[!//
eMIOS_B_EMIOS2_OUT_PORT189;1:OUT@[!//
DSPI_D_SCKD_OUT_PORT189;2:OUT@[!//
eMIOS_B_EMIOS2_IN_PORT189;1:IN@[!//
DSPI_D_SCKD_IN_PORT189;6:IN@[!//
eMIOS_B_EMIOS3_INOUT_PORT190;1:INOUT@[!//
DSPI_D_SIND_PORT190;6:IN@[!//
eMIOS_B_EMIOS3_OUT_PORT190;1:OUT@[!//
eMIOS_B_EMIOS3_IN_PORT190;1:IN@[!//
eMIOS_B_EMIOS4_INOUT_PORT191;1:INOUT@[!//
DSPI_C_SOUTC_PORT191;2:OUT@[!//
eMIOS_B_EMIOS4_OUT_PORT191;1:OUT@[!//
eMIOS_B_EMIOS4_IN_PORT191;1:IN@[!//
eMIOS_B_EMIOS5_INOUT_PORT192;1:INOUT@[!//
DSPI_D_SOUTD_PORT192;2:OUT@[!//
eMIOS_B_EMIOS5_OUT_PORT192;1:OUT@[!//
eMIOS_B_EMIOS5_IN_PORT192;1:IN@[!//
eMIOS_B_EMIOS6_PORT193;1:OUT@[!//
SIU_A_IRQ0_PORT193;6:IN@[!//
FlexCAN_D_CNTXD_PORT193;3:OUT@[!//
REACM_RCH0_C_OUT_PORT193;4:OUT@[!//
eMIOS_B_EMIOS7_PORT194;1:OUT@[!//
SIU_A_IRQ1_IN_PORT194;6:IN@[!//
FlexCAN_D_CNRXD_IN_PORT194;7:IN@[!//
REACM_RCH1_C_OUT_PORT194;4:OUT@[!//
eMIOS_A_EMIOS16_INOUT_PORT195;5:INOUT@[!//
eTPU_B_ETPUB0_PORT195;2:OUT@[!//
MCAN_1_TX_OUT_PORT195;3:OUT@[!//
REACM_RCH2_C_OUT_PORT195;4:OUT@[!//
eMIOS_A_EMIOS16_OUT_PORT195;1:OUT@[!//
eMIOS_A_EMIOS16_IN_PORT195;5:IN@[!//
eMIOS_A_EMIOS17_INOUT_PORT196;5:INOUT@[!//
eTPU_B_ETPUB1_PORT196;2:OUT@[!//
MCAN_1_RX_IN_PORT196;7:IN@[!//
REACM_RCH3_C_OUT_PORT196;4:OUT@[!//
eMIOS_A_EMIOS17_OUT_PORT196;1:OUT@[!//
eMIOS_A_EMIOS17_IN_PORT196;5:IN@[!//
eMIOS_A_EMIOS18_INOUT_PORT197;5:INOUT@[!//
eTPU_B_ETPUB2_PORT197;2:OUT@[!//
REACM_RCH4_C_OUT_PORT197;3:OUT@[!//
eMIOS_A_EMIOS18_OUT_PORT197;1:OUT@[!//
eMIOS_A_EMIOS18_IN_PORT197;5:IN@[!//
eMIOS_A_EMIOS19_INOUT_PORT198;5:INOUT@[!//
eTPU_B_ETPUB3_PORT198;2:OUT@[!//
REACM_RCH5_C_OUT_PORT198;3:OUT@[!//
eMIOS_A_EMIOS19_OUT_PORT198;1:OUT@[!//
eMIOS_A_EMIOS19_IN_PORT198;5:IN@[!//
eMIOS_A_EMIOS20_INOUT_PORT199;5:INOUT@[!//
eTPU_B_ETPUB4_PORT199;2:OUT@[!//
REACM_RCH6_C_OUT_PORT199;3:OUT@[!//
eMIOS_A_EMIOS20_OUT_PORT199;1:OUT@[!//
eMIOS_A_EMIOS20_IN_PORT199;5:IN@[!//
eMIOS_A_EMIOS21_INOUT_PORT200;5:INOUT@[!//
eTPU_B_ETPUB5_PORT200;2:OUT@[!//
REACM_RCH7_C_OUT_PORT200;3:OUT@[!//
eMIOS_A_EMIOS21_OUT_PORT200;1:OUT@[!//
eMIOS_A_EMIOS21_IN_PORT200;5:IN@[!//
eMIOS_A_EMIOS22_INOUT_PORT201;5:INOUT@[!//
eTPU_B_ETPUB6_PORT201;2:OUT@[!//
REACM_RCH8_C_OUT_PORT201;3:OUT@[!//
eMIOS_A_EMIOS22_OUT_PORT201;1:OUT@[!//
eMIOS_A_EMIOS22_IN_PORT201;5:IN@[!//
eMIOS_A_EMIOS23_INOUT_PORT202;5:INOUT@[!//
eTPU_B_ETPUB7_PORT202;2:OUT@[!//
REACM_RCH9_C_OUT_PORT202;3:OUT@[!//
eMIOS_A_EMIOS23_OUT_PORT202;1:OUT@[!//
eMIOS_A_EMIOS23_IN_PORT202;5:IN@[!//
eMIOS_B_EMIOS16_INOUT_PORT203;5:INOUT@[!//
DSPI_B_PCSB0_INOUT_PORT203;6:INOUT@[!//
eMIOS_B_EMIOS16_OUT_PORT203;1:OUT@[!//
DSPI_B_PCSB0_OUT_PORT203;2:OUT@[!//
eMIOS_B_EMIOS16_IN_PORT203;5:IN@[!//
DSPI_B_PCSB0_IN_PORT203;6:IN@[!//
eMIOS_B_EMIOS17_INOUT_PORT204;5:INOUT@[!//
DSPI_B_PCSB1_PORT204;2:OUT@[!//
eMIOS_B_EMIOS17_OUT_PORT204;1:OUT@[!//
eMIOS_B_EMIOS17_IN_PORT204;5:IN@[!//
SoC_PLLCFG0_IN_PORT208;1:IN@[!//
SIU_A_IRQ4_IN_PORT208;6:IN@[!//
eTPU_C_ETPUC9_INOUT_PORT208;7:INOUT@[!//
SIPI_TXN_PORT208;4:OUT@[!//
eTPU_C_ETPUC9_OUT_PORT208;3:OUT@[!//
eTPU_C_ETPUC9_IN_PORT208;7:IN@[!//
SoC_PLLCFG1_IN_PORT209;1:IN@[!//
SIU_A_IRQ5_IN_PORT209;6:IN@[!//
DSPI_D_SOUTD_PORT209;3:OUT@[!//
SIPI_TXP_PORT209;4:OUT@[!//
SoC_PLLCFG2_IN_PORT210;1:IN@[!//
eTPU_C_ETPUC3_INOUT_PORT210;6:INOUT@[!//
DSPI_E_PCSE1_PORT210;3:OUT@[!//
SIPI_REFCLK_INOUT_PORT210;4:INOUT@[!//
eTPU_C_ETPUC3_OUT_PORT210;2:OUT@[!//
SIPI_REFCLK_OUT_PORT210;4:OUT@[!//
eTPU_C_ETPUC3_IN_PORT210;6:IN@[!//
SIPI_REFCLK_IN_PORT210;4:IN@[!//
SoC_BOOTCFG0_IN_PORT211;1:IN@[!//
SIU_A_IRQ2_IN_PORT211;6:IN@[!//
SoC_BOOTCFG1_IN_PORT212;1:IN@[!//
SIU_A_IRQ3_IN_PORT212;6:IN@[!//
eTPU_C_ETPUC0_INOUT_PORT212;7:INOUT@[!//
SIPI_RXP_PORT212;4:IN@[!//
eTPU_C_ETPUC0_OUT_PORT212;3:OUT@[!//
eTPU_C_ETPUC0_IN_PORT212;7:IN@[!//
SoC_WKPCFG_IN_PORT213;1:IN@[!//
SIU_A_NMI_IN_PORT213;2:IN@[!//
eTPU_C_ETPUC1_INOUT_PORT213;7:INOUT@[!//
SIPI_RXN_PORT213;4:IN@[!//
eTPU_C_ETPUC1_OUT_PORT213;3:OUT@[!//
eTPU_C_ETPUC1_IN_PORT213;7:IN@[!//
ENGCLK_PORT214;1:OUT@[!//
MCKO_PORT219;1:OUT@[!//
eSCI_E_TXDE_PORT223;6:INOUT@[!//
MSEO0_PORT224;1:OUT@[!//
MSEO1_PORT225;1:OUT@[!//
RDY_PORT226;1:OUT@[!//
EVTO_PORT227;1:OUT@[!//
TDO_PORT228;1:OUT@[!//
D_CLKOUT_PORT229;1:OUT@[!//
RSTOUT_PORT230;1:OUT@[!//
DSPI_C_SCKC_INOUT_PORT235;5:INOUT@[!//
DSPI_C_SCK_C_LVDS_P_PORT235;2:OUT@[!//
DSPI_C_SCKC_OUT_PORT235;1:OUT@[!//
DSPI_C_SCKC_IN_PORT235;5:IN@[!//
DSPI_C_SINC_IN_PORT236;5:IN@[!//
DSPI_C_SCK_C_LVDS_N_OUT_PORT236;2:OUT@[!//
DSPI_C_SOUTC_PORT237;1:OUT@[!//
DSPI_C_SOUT_C_LVDS_P_PORT237;2:OUT@[!//
DSPI_C_PCSC0_INOUT_PORT238;5:INOUT@[!//
DSPI_C_SOUT_C_LVDS_N_OUT_PORT238;2:OUT@[!//
DSPI_C_PCSC0_OUT_PORT238;1:OUT@[!//
DSPI_C_PCSC0_IN_PORT238;5:IN@[!//
DSPI_C_PCSC1_PORT239;1:OUT@[!//
eSCI_D_TXDD_PORT239;2:INOUT@[!//
DSPI_C_PCSC2_PORT240;1:OUT@[!//
DSPI_D_SCK_D_LVDS_P_PORT240;2:OUT@[!//
DSPI_D_SCKD_INOUT_PORT240;7:INOUT@[!//
DSPI_D_SCKD_OUT_PORT240;3:OUT@[!//
DSPI_D_SCKD_IN_PORT240;7:IN@[!//
DSPI_C_PCSC3_PORT241;1:OUT@[!//
DSPI_D_SCK_D_LVDS_N_OUT_PORT241;2:OUT@[!//
DSPI_D_SIND_IN_PORT241;7:IN@[!//
DSPI_C_PCSC4_PORT242;1:OUT@[!//
MCAN_0_TX_OUT_PORT242;2:OUT@[!//
DSPI_D_SOUT_D_LVDS_P_PORT242;3:OUT@[!//
DSPI_D_SOUTD_PORT242;4:OUT@[!//
DSPI_C_PCSC5_PORT243;1:OUT@[!//
MCAN_0_RX_IN_PORT243;6:IN@[!//
DSPI_D_SOUT_D_LVDS_N_OUT_PORT243;3:OUT@[!//
DSPI_D_PCSD0_INOUT_PORT243;8:INOUT@[!//
DSPI_D_PCSD0_OUT_PORT243;4:OUT@[!//
DSPI_D_PCSD0_IN_PORT243;8:IN@[!//
eSCI_C_TXDC_PORT244;1:INOUT@[!//
eQADC_A_eQADC_B_ETRIG0_IN_PORT244;2:IN@[!//
eSCI_C_RXDC_IN_PORT245;1:IN@[!//
FlexCAN_D_CNTXD_PORT246;1:OUT@[!//
MCAN_1_TX_OUT_PORT246;3:OUT@[!//
FlexCAN_D_CNRXD_IN_PORT247;5:IN@[!//
MCAN_1_RX_IN_PORT247;7:IN@[!//
FEC_FEC_TXD0_OUT_PORT248;1:OUT@[!//
SENT_A_SENT0_A_IN_PORT248;6:IN@[!//
FEC_FEC_RX_DV_IN_PORT249;1:IN@[!//
SENT_A_SENT1_A_IN_PORT249;6:IN@[!//
FEC_FEC_RXD0_IN_PORT250;1:IN@[!//
SENT_A_SENT2_A_IN_PORT250;6:IN@[!//
FEC_FEC_TXD1_OUT_PORT251;1:OUT@[!//
SENT_A_SENT3_A_IN_PORT251;6:IN@[!//
FEC_FEC_TXEN_OUT_PORT252;1:OUT@[!//
SENT_A_SENT4_A_IN_PORT252;6:IN@[!//
FEC_FEC_RXD1_IN_PORT253;1:IN@[!//
SENT_A_SENT5_A_IN_PORT253;6:IN@[!//
EBI_D_CS0_PORT256;1:OUT@[!//
EBI_D_CS2_PORT257;1:OUT@[!//
EBI_D_ADD_DAT31_PORT257;2:INOUT@[!//
EBI_D_CS3_PORT258;1:OUT@[!//
EBI_D_TEA_PORT258;2:INOUT@[!//
EBI_D_ADD12_PORT259;1:OUT@[!//
EBI_D_ADD13_PORT260;1:OUT@[!//
EBI_D_ADD14_PORT261;1:OUT@[!//
EBI_D_ADD15_PORT262;1:OUT@[!//
EBI_D_ADD16_PORT263;1:OUT@[!//
EBI_D_ADD_DAT16_PORT263;2:INOUT@[!//
EBI_D_ADD17_PORT264;1:OUT@[!//
EBI_D_ADD_DAT17_PORT264;2:INOUT@[!//
EBI_D_ADD18_PORT265;1:OUT@[!//
EBI_D_ADD_DAT18_PORT265;2:INOUT@[!//
EBI_D_ADD19_PORT266;1:OUT@[!//
EBI_D_ADD_DAT19_PORT266;2:INOUT@[!//
EBI_D_ADD20_PORT267;1:OUT@[!//
EBI_D_ADD_DAT20_PORT267;2:INOUT@[!//
EBI_D_ADD21_PORT268;1:OUT@[!//
EBI_D_ADD_DAT21_PORT268;2:INOUT@[!//
EBI_D_ADD22_PORT269;1:OUT@[!//
EBI_D_ADD_DAT22_PORT269;2:INOUT@[!//
EBI_D_ADD23_PORT270;1:OUT@[!//
EBI_D_ADD_DAT23_PORT270;2:INOUT@[!//
EBI_D_ADD24_PORT271;1:OUT@[!//
EBI_D_ADD_DAT24_PORT271;2:INOUT@[!//
EBI_D_ADD25_PORT272;1:OUT@[!//
EBI_D_ADD_DAT25_PORT272;2:INOUT@[!//
EBI_D_ADD26_PORT273;1:OUT@[!//
EBI_D_ADD_DAT26_PORT273;2:INOUT@[!//
EBI_D_ADD27_PORT274;1:OUT@[!//
EBI_D_ADD_DAT27_PORT274;2:INOUT@[!//
EBI_D_ADD28_PORT275;1:OUT@[!//
EBI_D_ADD_DAT28_PORT275;2:INOUT@[!//
EBI_D_ADD29_PORT276;1:OUT@[!//
EBI_D_ADD_DAT29_PORT276;2:INOUT@[!//
EBI_D_ADD30_PORT277;1:OUT@[!//
EBI_D_ADD_DAT30_PORT277;2:INOUT@[!//
EBI_D_DAT0_PORT278;1:INOUT@[!//
EBI_D_DAT1_PORT279;1:INOUT@[!//
EBI_D_DAT2_PORT280;1:INOUT@[!//
EBI_D_DAT3_PORT281;1:INOUT@[!//
EBI_D_DAT4_PORT282;1:INOUT@[!//
EBI_D_DAT5_PORT283;1:INOUT@[!//
EBI_D_DAT6_PORT284;1:INOUT@[!//
EBI_D_DAT7_PORT285;1:INOUT@[!//
EBI_D_DAT8_PORT286;1:INOUT@[!//
EBI_D_DAT9_PORT287;1:INOUT@[!//
EBI_D_DAT10_PORT288;1:INOUT@[!//
EBI_D_DAT11_PORT289;1:INOUT@[!//
EBI_D_DAT12_PORT290;1:INOUT@[!//
EBI_D_DAT13_PORT291;1:INOUT@[!//
EBI_D_DAT14_PORT292;1:INOUT@[!//
EBI_D_DAT15_PORT293;1:INOUT@[!//
EBI_D_RD_WR_PORT294;1:OUT@[!//
EBI_D_WE0_PORT295;1:OUT@[!//
EBI_D_WE1_PORT296;1:OUT@[!//
EBI_D_OE_PORT297;1:OUT@[!//
EBI_D_TS_PORT298;1:OUT@[!//
EBI_D_ALE_PORT299;1:OUT@[!//
EBI_D_TA_PORT300;1:INOUT@[!//
EBI_D_CS1_PORT301;1:OUT@[!//
EBI_D_BDIP_PORT302;1:OUT@[!//
EBI_D_WE2_PORT303;1:OUT@[!//
EBI_D_WE3_PORT304;1:OUT@[!//
EBI_D_ADD9_PORT305;1:OUT@[!//
EBI_D_ADD10_PORT306;1:OUT@[!//
EBI_D_ADD11_PORT307;1:OUT@[!//
eMIOS_B_EMIOS18_INOUT_PORT432;5:INOUT@[!//
DSPI_B_PCSB2_PORT432;2:OUT@[!//
eMIOS_B_EMIOS18_OUT_PORT432;1:OUT@[!//
eMIOS_B_EMIOS18_IN_PORT432;5:IN@[!//
eMIOS_B_EMIOS19_INOUT_PORT433;5:INOUT@[!//
DSPI_B_PCSB3_PORT433;2:OUT@[!//
eMIOS_B_EMIOS19_OUT_PORT433;1:OUT@[!//
eMIOS_B_EMIOS19_IN_PORT433;5:IN@[!//
eMIOS_B_EMIOS20_INOUT_PORT434;5:INOUT@[!//
DSPI_C_PCSC0_INOUT_PORT434;6:INOUT@[!//
eMIOS_B_EMIOS20_OUT_PORT434;1:OUT@[!//
DSPI_C_PCSC0_OUT_PORT434;2:OUT@[!//
eMIOS_B_EMIOS20_IN_PORT434;5:IN@[!//
DSPI_C_PCSC0_IN_PORT434;6:IN@[!//
eMIOS_B_EMIOS21_INOUT_PORT435;5:INOUT@[!//
DSPI_C_PCSC1_PORT435;2:OUT@[!//
eMIOS_B_EMIOS21_OUT_PORT435;1:OUT@[!//
eMIOS_B_EMIOS21_IN_PORT435;5:IN@[!//
eMIOS_B_EMIOS22_INOUT_PORT436;5:INOUT@[!//
DSPI_C_PCSC2_PORT436;2:OUT@[!//
eMIOS_B_EMIOS22_OUT_PORT436;1:OUT@[!//
eMIOS_B_EMIOS22_IN_PORT436;5:IN@[!//
eMIOS_B_EMIOS23_INOUT_PORT437;5:INOUT@[!//
DSPI_C_PCSC5_PORT437;2:OUT@[!//
eMIOS_B_EMIOS23_OUT_PORT437;1:OUT@[!//
eMIOS_B_EMIOS23_IN_PORT437;5:IN@[!//
eTPU_C_TCRCLKC_IN_PORT440;5:IN@[!//
SIU_A_IRQ6_IN_PORT440;6:IN@[!//
eQADC_B_ANB40_IN_PORT440;9:IN@[!//
eTPU_C_ETPUC0_IN_PORT441;5:IN@[!//
SENT_A_SENT0_A_IN_PORT441;6:IN@[!//
eQADC_B_ANB41_IN_PORT441;9:IN@[!//
eTPU_C_ETPUC1_IN_PORT442;5:IN@[!//
SENT_A_SENT1_A_IN_PORT442;6:IN@[!//
eQADC_B_ANB42_IN_PORT442;9:IN@[!//
eTPU_C_ETPUC2_INOUT_PORT443;1:INOUT@[!//
SENT_A_SENT3_A_IN_PORT443;6:IN@[!//
eTPU_C_ETPUC2_OUT_PORT443;1:OUT@[!//
eTPU_C_ETPUC2_IN_PORT443;1:IN@[!//
eTPU_C_ETPUC3_IN_PORT444;5:IN@[!//
SENT_A_SENT4_A_IN_PORT444;6:IN@[!//
eQADC_B_ANB45_IN_PORT444;9:IN@[!//
eTPU_C_ETPUC4_INOUT_PORT445;1:INOUT@[!//
SENT_A_SENT5_A_IN_PORT445;6:IN@[!//
eTPU_C_TCRCLKC_IN_PORT445;7:IN@[!//
eTPU_C_ETPUC4_OUT_PORT445;1:OUT@[!//
eTPU_C_ETPUC4_IN_PORT445;1:IN@[!//
eTPU_C_ETPUC5_INOUT_PORT446;1:INOUT@[!//
DSPI_E_PCSE2_PORT446;2:OUT@[!//
SENT_B_SENT0_B_IN_PORT446;7:IN@[!//
eTPU_C_ETPUC5_OUT_PORT446;1:OUT@[!//
eTPU_C_ETPUC5_IN_PORT446;1:IN@[!//
eTPU_C_ETPUC6_INOUT_PORT447;1:INOUT@[!//
DSPI_E_PCSE3_PORT447;2:OUT@[!//
SENT_B_SENT1_B_IN_PORT447;7:IN@[!//
eTPU_C_ETPUC6_OUT_PORT447;1:OUT@[!//
eTPU_C_ETPUC6_IN_PORT447;1:IN@[!//
eTPU_C_ETPUC7_INOUT_PORT448;1:INOUT@[!//
DSPI_E_PCSE4_PORT448;2:OUT@[!//
SENT_B_SENT2_B_IN_PORT448;7:IN@[!//
eTPU_C_ETPUC7_OUT_PORT448;1:OUT@[!//
eTPU_C_ETPUC7_IN_PORT448;1:IN@[!//
eTPU_C_ETPUC8_INOUT_PORT449;5:INOUT@[!//
DSPI_E_PCSE5_PORT449;2:OUT@[!//
SENT_B_SENT3_B_IN_PORT449;7:IN@[!//
eTPU_C_ETPUC8_OUT_PORT449;1:OUT@[!//
eTPU_C_ETPUC8_IN_PORT449;5:IN@[!//
eTPU_C_ETPUC9_IN_PORT450;5:IN@[!//
SIU_A_IRQ0_IN_PORT450;6:IN@[!//
SENT_B_SENT4_B_IN_PORT450;7:IN@[!//
eQADC_B_ANB44_IN_PORT450;9:IN@[!//
eTPU_C_ETPUC10_INOUT_PORT451;5:INOUT@[!//
SIU_A_IRQ1_IN_PORT451;6:IN@[!//
SENT_B_SENT5_B_IN_PORT451;7:IN@[!//
eTPU_C_ETPUC10_OUT_PORT451;1:OUT@[!//
eTPU_C_ETPUC10_IN_PORT451;5:IN@[!//
eTPU_C_ETPUC11_INOUT_PORT452;5:INOUT@[!//
SIU_A_IRQ2_IN_PORT452;6:IN@[!//
eTPU_C_ETPUC11_OUT_PORT452;1:OUT@[!//
eTPU_C_ETPUC11_IN_PORT452;5:IN@[!//
eTPU_C_ETPUC12_INOUT_PORT453;5:INOUT@[!//
SIU_A_IRQ3_IN_PORT453;6:IN@[!//
MCAN_1_TX_OUT_PORT453;3:OUT@[!//
eTPU_C_ETPUC12_OUT_PORT453;1:OUT@[!//
eTPU_C_ETPUC12_IN_PORT453;5:IN@[!//
eTPU_C_ETPUC13_INOUT_PORT454;5:INOUT@[!//
SIU_A_IRQ4_IN_PORT454;6:IN@[!//
PSI5A_SDOUT0_PSI5A_OUT_PORT454;3:OUT@[!//
REACM_RCH0_C_OUT_PORT454;4:OUT@[!//
eTPU_C_ETPUC13_OUT_PORT454;1:OUT@[!//
eTPU_C_ETPUC13_IN_PORT454;5:IN@[!//
eTPU_C_ETPUC14_INOUT_PORT455;5:INOUT@[!//
SIU_A_IRQ5_IN_PORT455;6:IN@[!//
PSI5A_SDIN0_PSI5A_IN_PORT455;3:IN@[!//
REACM_RCH1_C_OUT_PORT455;4:OUT@[!//
eTPU_C_ETPUC14_OUT_PORT455;1:OUT@[!//
eTPU_C_ETPUC14_IN_PORT455;5:IN@[!//
eTPU_C_ETPUC15_INOUT_PORT456;5:INOUT@[!//
MCAN_1_RX_IN_PORT456;6:IN@[!//
REACM_RCH2_C_OUT_PORT456;3:OUT@[!//
eTPU_C_ETPUC15_OUT_PORT456;1:OUT@[!//
eTPU_C_ETPUC15_IN_PORT456;5:IN@[!//
eTPU_C_ETPUC16_INOUT_PORT457;1:INOUT@[!//
MCAN_1_TX_OUT_PORT457;2:OUT@[!//
REACM_RCH3_C_OUT_PORT457;3:OUT@[!//
eTPU_C_ETPUC16_OUT_PORT457;1:OUT@[!//
eTPU_C_ETPUC16_IN_PORT457;1:IN@[!//
eTPU_C_ETPUC17_INOUT_PORT458;1:INOUT@[!//
eSCI_F_TXDF_PORT458;2:INOUT@[!//
REACM_RCH4_C_OUT_PORT458;3:OUT@[!//
eTPU_C_ETPUC17_OUT_PORT458;1:OUT@[!//
eTPU_C_ETPUC17_IN_PORT458;1:IN@[!//
eTPU_C_ETPUC18_INOUT_PORT459;1:INOUT@[!//
eSCI_F_RXDF_IN_PORT459;2:IN@[!//
eTPU_C_ETPUC18_OUT_PORT459;1:OUT@[!//
eTPU_C_ETPUC18_IN_PORT459;1:IN@[!//
eTPU_C_ETPUC19_INOUT_PORT460;1:INOUT@[!//
eSCI_A_TXDA_PORT460;6:INOUT@[!//
PSI5A_SDOUT0_PSI5B_OUT_PORT460;3:OUT@[!//
eTPU_C_ETPUC19_OUT_PORT460;1:OUT@[!//
eTPU_C_ETPUC19_IN_PORT460;1:IN@[!//
eTPU_C_ETPUC20_INOUT_PORT461;1:INOUT@[!//
eSCI_A_RXDA_IN_PORT461;6:IN@[!//
PSI5A_SDIN0_PSI5B_IN_PORT461;3:IN@[!//
eTPU_C_ETPUC20_OUT_PORT461;1:OUT@[!//
eTPU_C_ETPUC20_IN_PORT461;1:IN@[!//
eTPU_C_ETPUC21_INOUT_PORT462;1:INOUT@[!//
eSCI_B_TXDB_PORT462;6:INOUT@[!//
eTPU_C_ETPUC21_OUT_PORT462;1:OUT@[!//
eTPU_C_ETPUC21_IN_PORT462;1:IN@[!//
eTPU_C_ETPUC22_INOUT_PORT463;1:INOUT@[!//
eSCI_B_RXDB_IN_PORT463;6:IN@[!//
eTPU_C_ETPUC22_OUT_PORT463;1:OUT@[!//
eTPU_C_ETPUC22_IN_PORT463;1:IN@[!//
eTPU_C_ETPUC23_INOUT_PORT464;1:INOUT@[!//
DSPI_D_PCSD5_PORT464;2:OUT@[!//
eQADC_A_MAA0_PORT464;3:OUT@[!//
eQADC_B_MAB0_PORT464;4:OUT@[!//
eTPU_C_ETPUC23_OUT_PORT464;1:OUT@[!//
eTPU_C_ETPUC23_IN_PORT464;1:IN@[!//
eTPU_C_ETPUC24_INOUT_PORT465;1:INOUT@[!//
DSPI_D_PCSD4_PORT465;2:OUT@[!//
eQADC_A_MAA1_PORT465;3:OUT@[!//
eQADC_B_MAB1_PORT465;4:OUT@[!//
eTPU_C_ETPUC24_OUT_PORT465;1:OUT@[!//
eTPU_C_ETPUC24_IN_PORT465;1:IN@[!//
eTPU_C_ETPUC25_INOUT_PORT466;1:INOUT@[!//
DSPI_D_PCSD3_PORT466;2:OUT@[!//
eQADC_A_MAA2_PORT466;3:OUT@[!//
eQADC_B_MAB2_PORT466;4:OUT@[!//
eTPU_C_ETPUC25_OUT_PORT466;1:OUT@[!//
eTPU_C_ETPUC25_IN_PORT466;1:IN@[!//
eTPU_C_ETPUC26_INOUT_PORT467;1:INOUT@[!//
DSPI_D_PCSD2_PORT467;2:OUT@[!//
eQADC_B_MAB0_PORT467;3:OUT@[!//
eTPU_C_ETPUC26_OUT_PORT467;1:OUT@[!//
eTPU_C_ETPUC26_IN_PORT467;1:IN@[!//
eTPU_C_ETPUC27_INOUT_PORT468;1:INOUT@[!//
DSPI_D_PCSD1_PORT468;2:OUT@[!//
REACM_RCH5_C_OUT_PORT468;3:OUT@[!//
eQADC_B_MAB1_PORT468;4:OUT@[!//
eTPU_C_ETPUC27_OUT_PORT468;1:OUT@[!//
eTPU_C_ETPUC27_IN_PORT468;1:IN@[!//
eTPU_C_ETPUC28_INOUT_PORT469;1:INOUT@[!//
DSPI_D_PCSD0_INOUT_PORT469;6:INOUT@[!//
REACM_RCH6_C_OUT_PORT469;3:OUT@[!//
eQADC_B_MAB2_PORT469;4:OUT@[!//
eTPU_C_ETPUC28_OUT_PORT469;1:OUT@[!//
DSPI_D_PCSD0_OUT_PORT469;2:OUT@[!//
eTPU_C_ETPUC28_IN_PORT469;1:IN@[!//
DSPI_D_PCSD0_IN_PORT469;6:IN@[!//
eTPU_C_ETPUC29_INOUT_PORT470;1:INOUT@[!//
DSPI_D_SCKD_INOUT_PORT470;6:INOUT@[!//
REACM_RCH7_C_OUT_PORT470;3:OUT@[!//
eTPU_C_ETPUC29_OUT_PORT470;1:OUT@[!//
DSPI_D_SCKD_OUT_PORT470;2:OUT@[!//
eTPU_C_ETPUC29_IN_PORT470;1:IN@[!//
DSPI_D_SCKD_IN_PORT470;6:IN@[!//
eTPU_C_ETPUC30_INOUT_PORT471;1:INOUT@[!//
DSPI_D_SOUTD_PORT471;2:OUT@[!//
REACM_RCH8_C_OUT_PORT471;3:OUT@[!//
eTPU_C_ETPUC30_OUT_PORT471;1:OUT@[!//
eTPU_C_ETPUC30_IN_PORT471;1:IN@[!//
eTPU_C_ETPUC31_INOUT_PORT472;1:INOUT@[!//
DSPI_D_SIND_IN_PORT472;6:IN@[!//
REACM_RCH9_C_OUT_PORT472;3:OUT@[!//
eTPU_C_ETPUC31_OUT_PORT472;1:OUT@[!//
eTPU_C_ETPUC31_IN_PORT472;1:IN@[!//
FEC_FEC_TXCLK_REFCLK_IN_PORT474;1:IN@[!//
SENT_B_SENT0_B_IN_PORT474;6:IN@[!//
SENT_A_SENT2_A_IN_PORT475;5:IN@[!//
eQADC_B_ANB43_IN_PORT475;9:IN@[!//
eQADC_B_ANB8_IN_PORT476;9:IN@[!//
eTPU_A_ETPUA31_IN_PORT476;6:IN@[!//
eMIOS_A_EMIOS16_IN_PORT476;7:IN@[!//
eQADC_B_ANB9_IN_PORT477;9:IN@[!//
eTPU_A_ETPUA30_IN_PORT477;6:IN@[!//
eMIOS_A_EMIOS17_IN_PORT477;7:IN@[!//
eQADC_B_ANB10_IN_PORT478;9:IN@[!//
eTPU_A_ETPUA29_IN_PORT478;6:IN@[!//
eMIOS_A_EMIOS18_IN_PORT478;7:IN@[!//
eQADC_B_ANB11_IN_PORT479;9:IN@[!//
eTPU_A_ETPUA28_IN_PORT479;6:IN@[!//
eMIOS_A_EMIOS19_IN_PORT479;7:IN@[!//
eQADC_B_ANB12_IN_PORT480;9:IN@[!//
eTPU_A_ETPUA27_IN_PORT480;6:IN@[!//
eMIOS_A_EMIOS20_IN_PORT480;7:IN@[!//
eQADC_B_ANB13_IN_PORT481;9:IN@[!//
eTPU_A_ETPUA26_IN_PORT481;6:IN@[!//
eMIOS_A_EMIOS21_IN_PORT481;7:IN@[!//
eQADC_B_ANB14_IN_PORT482;9:IN@[!//
eTPU_A_ETPUA25_IN_PORT482;6:IN@[!//
eMIOS_A_EMIOS22_IN_PORT482;7:IN@[!//
eQADC_B_ANB15_IN_PORT483;9:IN@[!//
eTPU_A_ETPUA24_IN_PORT483;6:IN@[!//
eMIOS_A_EMIOS23_IN_PORT483;7:IN@[!//
eQADC_B_ANB16_IN_PORT484;9:IN@[!//
eTPU_C_ETPUC15_IN_PORT484;6:IN@[!//
eMIOS_B_EMIOS16_IN_PORT484;7:IN@[!//
eQADC_B_ANB17_IN_PORT485;9:IN@[!//
eTPU_C_ETPUC14_IN_PORT485;6:IN@[!//
eMIOS_B_EMIOS17_IN_PORT485;7:IN@[!//
eQADC_B_ANB18_IN_PORT486;9:IN@[!//
eTPU_C_ETPUC13_IN_PORT486;6:IN@[!//
eMIOS_B_EMIOS18_IN_PORT486;7:IN@[!//
eQADC_B_ANB19_IN_PORT487;9:IN@[!//
eTPU_C_ETPUC12_IN_PORT487;6:IN@[!//
eMIOS_B_EMIOS19_IN_PORT487;7:IN@[!//
eQADC_B_ANB20_IN_PORT488;9:IN@[!//
eTPU_C_ETPUC11_IN_PORT488;6:IN@[!//
eMIOS_B_EMIOS20_IN_PORT488;7:IN@[!//
eQADC_B_ANB21_IN_PORT489;9:IN@[!//
eTPU_C_ETPUC10_IN_PORT489;6:IN@[!//
eMIOS_B_EMIOS21_IN_PORT489;7:IN@[!//
eQADC_B_ANB22_IN_PORT490;9:IN@[!//
eTPU_C_ETPUC9_IN_PORT490;6:IN@[!//
eMIOS_B_EMIOS22_IN_PORT490;7:IN@[!//
eQADC_B_ANB23_IN_PORT491;9:IN@[!//
eTPU_C_ETPUC8_IN_PORT491;6:IN@[!//
eMIOS_B_EMIOS23_IN_PORT491;7:IN@[!//
[!ENDVAR!]

[!VAR "PinAbstractionModes_1"!]

#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_FlexCAN_A_CNTXA        (PORT_ALT1_FUNC_MODE)
#define    PORT83_eSCI_A_TXDA        (PORT_INPUT2_MODE)
#define    PORT83_MCAN_0_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_FlexCAN_A_CNRXA        (PORT_ALT1_FUNC_MODE)
#define    PORT84_eSCI_A_RXDA        (PORT_INPUT2_MODE)
#define    PORT84_MCAN_0_RX_IN        (PORT_INPUT3_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_FlexCAN_B_CNTXB        (PORT_ALT1_FUNC_MODE)
#define    PORT85_DSPI_C_PCSC3        (PORT_ALT2_FUNC_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_FlexCAN_B_CNRXB        (PORT_ALT1_FUNC_MODE)
#define    PORT86_DSPI_C_PCSC4        (PORT_ALT2_FUNC_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_FlexCAN_C_CNTXC        (PORT_ALT1_FUNC_MODE)
#define    PORT87_DSPI_D_PCSD3        (PORT_ALT2_FUNC_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FlexCAN_C_CNRXC        (PORT_ALT1_FUNC_MODE)
#define    PORT88_DSPI_D_PCSD4        (PORT_ALT2_FUNC_MODE)
#define    PORT88_eSCI_E_RXDE        (PORT_ALT3_FUNC_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_eSCI_A_TXDA        (PORT_INPUT1_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_eSCI_A_RXDA_IN        (PORT_INPUT1_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_eSCI_B_TXDB        (PORT_INPUT1_MODE)
#define    PORT91_DSPI_D_PCSD1        (PORT_ALT2_FUNC_MODE)
#define    PORT91_MCAN_0_RX_IN        (PORT_INPUT3_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_eSCI_B_RXDB        (PORT_INPUT1_MODE)
#define    PORT92_DSPI_D_PCSD5        (PORT_ALT2_FUNC_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_DSPI_A_SCKA_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_DSPI_A_SCKA_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT93_DSPI_A_SCKA_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_DSPI_C_PCSC1        (PORT_ALT2_FUNC_MODE)
#define    PORT93_MCAN_0_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT93_SENT_B_SENT1_B_IN        (PORT_INPUT4_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_DSPI_A_SINA        (PORT_ALT1_FUNC_MODE)
#define    PORT94_DSPI_C_PCSC2        (PORT_ALT2_FUNC_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_DSPI_A_SOUTA        (PORT_ALT1_FUNC_MODE)
#define    PORT95_DSPI_C_PCSC5        (PORT_ALT2_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_DSPI_A_PCSA0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT96_DSPI_A_PCSA0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT96_DSPI_A_PCSA0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT96_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_DSPI_A_PCSA1        (PORT_ALT1_FUNC_MODE)
#define    PORT97_DSPI_E_PCSE0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT97_DSPI_E_PCSE0_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT97_DSPI_E_PCSE0_INOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_DSPI_A_PCSA2        (PORT_ALT1_FUNC_MODE)
#define    PORT98_DSPI_E_SOUTE        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FEC_FEC_TXD2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FEC_FEC_RXER_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_DSPI_A_PCSA3        (PORT_ALT1_FUNC_MODE)
#define    PORT99_DSPI_E_SINE        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FEC_FEC_MDIO        (PORT_ALT3_FUNC_MODE)
#define    PORT99_eSCI_D_TXDD        (PORT_ALT4_FUNC_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_DSPI_A_PCSA4        (PORT_ALT1_FUNC_MODE)
#define    PORT100_DSPI_E_SCKE_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_DSPI_E_SCKE_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT100_DSPI_E_SCKE_INOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_eSCI_E_TXDE        (PORT_INPUT3_MODE)
#define    PORT100_FEC_FEC_RXCLK_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_DSPI_A_PCSA5        (PORT_ALT1_FUNC_MODE)
#define    PORT101_eQADC_A_eQADC_B_ETRIG1        (PORT_ALT2_FUNC_MODE)
#define    PORT101_eSCI_D_RXDD        (PORT_ALT3_FUNC_MODE)
#define    PORT101_FEC_FEC_TXD3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_DSPI_B_SCKB_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_DSPI_B_SCKB_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_DSPI_B_SCKB_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_DSPI_B_SINB        (PORT_ALT1_FUNC_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_DSPI_B_SOUTB        (PORT_ALT1_FUNC_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_DSPI_B_PCSB0_INOUT        (PORT_INPUT1_MODE)
#define    PORT105_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT105_DSPI_B_PCSB0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT105_DSPI_B_PCSB0_IN        (PORT_INPUT1_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_DSPI_B_PCSB1        (PORT_ALT1_FUNC_MODE)
#define    PORT106_DSPI_D_PCSD0_INOUT        (PORT_INPUT2_MODE)
#define    PORT106_DSPI_D_PCSD0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT106_DSPI_D_PCSD0_IN        (PORT_INPUT2_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_DSPI_B_PCSB2        (PORT_ALT1_FUNC_MODE)
#define    PORT107_DSPI_C_SOUTC        (PORT_ALT2_FUNC_MODE)
#define    PORT107_SENT_B_SENT2_B_IN        (PORT_INPUT3_MODE)
#define    PORT107_FEC_FEC_RXD3_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_DSPI_B_PCSB3        (PORT_ALT1_FUNC_MODE)
#define    PORT108_DSPI_C_SINC        (PORT_INPUT2_MODE)
#define    PORT108_SENT_B_SENT3_B_IN        (PORT_INPUT3_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_DSPI_B_PCSB4        (PORT_ALT1_FUNC_MODE)
#define    PORT109_DSPI_C_SCKC_INOUT        (PORT_INPUT2_MODE)
#define    PORT109_SENT_B_SENT4_B_IN        (PORT_INPUT3_MODE)
#define    PORT109_FEC_FEC_MDC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT109_DSPI_C_SCKC_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT109_DSPI_C_SCKC_IN        (PORT_INPUT2_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_DSPI_B_PCSB5        (PORT_ALT1_FUNC_MODE)
#define    PORT110_DSPI_C_PCSC0_INOUT        (PORT_INPUT2_MODE)
#define    PORT110_SENT_B_SENT5_B_IN        (PORT_INPUT3_MODE)
#define    PORT110_FEC_FEC_RXD2_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT110_DSPI_C_PCSC0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT110_DSPI_C_PCSC0_IN        (PORT_INPUT2_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_eTPU_A_TCRCLKA        (PORT_ALT1_FUNC_MODE)
#define    PORT113_SIU_A_IRQ7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_eTPU_A_ETPUA0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_eTPU_A_ETPUA12        (PORT_ALT2_FUNC_MODE)
#define    PORT114_eTPU_A_ETPUA0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_eTPU_A_ETPUA0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_eTPU_A_ETPUA1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_eTPU_A_ETPUA13        (PORT_ALT2_FUNC_MODE)
#define    PORT115_eTPU_A_ETPUA1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_eTPU_A_ETPUA1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_eTPU_A_ETPUA2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_eTPU_A_ETPUA14        (PORT_ALT2_FUNC_MODE)
#define    PORT116_REACM_RCH0_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT116_eTPU_A_ETPUA2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_eTPU_A_ETPUA2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_eTPU_A_ETPUA3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_eTPU_A_ETPUA15        (PORT_ALT2_FUNC_MODE)
#define    PORT117_REACM_RCH1_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT117_FCCU_ERROR0        (PORT_ALT4_FUNC_MODE)
#define    PORT117_eTPU_A_ETPUA3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_eTPU_A_ETPUA3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_eTPU_A_ETPUA4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_eTPU_A_ETPUA16        (PORT_ALT2_FUNC_MODE)
#define    PORT118_REACM_RCH2_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT118_eTPU_A_ETPUA4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_eTPU_A_ETPUA4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_eTPU_A_ETPUA5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_eTPU_A_ETPUA17        (PORT_ALT2_FUNC_MODE)
#define    PORT119_REACM_RCH3_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT119_eTPU_A_ETPUA5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_eTPU_A_ETPUA5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_eTPU_A_ETPUA6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_eTPU_A_ETPUA18        (PORT_ALT2_FUNC_MODE)
#define    PORT120_REACM_RCH4_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT120_eTPU_A_ETPUA6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_eTPU_A_ETPUA6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_eTPU_A_ETPUA7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT121_eTPU_A_ETPUA19        (PORT_ALT2_FUNC_MODE)
#define    PORT121_REACM_RCH5_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT121_eTPU_A_ETPUA7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT121_eTPU_A_ETPUA7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_eTPU_A_ETPUA8_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_eTPU_A_ETPUA20        (PORT_ALT2_FUNC_MODE)
#define    PORT122_REACM_RCH6_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT122_eTPU_A_ETPUA8_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_eTPU_A_ETPUA8_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_eTPU_A_ETPUA9_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_eTPU_A_ETPUA21        (PORT_ALT2_FUNC_MODE)
#define    PORT123_REACM_RCH7_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT123_eTPU_A_ETPUA9_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_eTPU_A_ETPUA9_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_eTPU_A_ETPUA10_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_eTPU_A_ETPUA22        (PORT_ALT2_FUNC_MODE)
#define    PORT124_REACM_RCH8_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT124_FCCU_ERRORIN        (PORT_ALT4_FUNC_MODE)
#define    PORT124_eTPU_A_ETPUA10_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_eTPU_A_ETPUA10_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_eTPU_A_ETPUA11_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT125_eTPU_A_ETPUA23        (PORT_ALT2_FUNC_MODE)
#define    PORT125_REACM_RCH9_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT125_FCCU_ERROR1        (PORT_ALT4_FUNC_MODE)
#define    PORT125_eTPU_A_ETPUA11_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT125_eTPU_A_ETPUA11_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_eTPU_A_ETPUA12_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_DSPI_B_PCSB1        (PORT_ALT2_FUNC_MODE)
#define    PORT126_eTPU_A_ETPUA12_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_eTPU_A_ETPUA12_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_eTPU_A_ETPUA13_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT127_DSPI_B_PCSB3        (PORT_ALT2_FUNC_MODE)
#define    PORT127_eTPU_A_ETPUA13_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT127_eTPU_A_ETPUA13_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_eTPU_A_ETPUA14_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_DSPI_B_PCSB4        (PORT_ALT2_FUNC_MODE)
#define    PORT128_eTPU_A_ETPUA14_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_eTPU_A_ETPUA14_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_eTPU_A_ETPUA15_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_DSPI_B_PCSB5        (PORT_ALT2_FUNC_MODE)
#define    PORT129_MCAN_0_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT129_eTPU_A_ETPUA15_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_eTPU_A_ETPUA15_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_eTPU_A_ETPUA16_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_DSPI_D_PCSD1        (PORT_ALT2_FUNC_MODE)
#define    PORT130_eTPU_A_ETPUA16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_eTPU_A_ETPUA16_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_eTPU_A_ETPUA17_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT131_eTPU_A_ETPUA17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_eTPU_A_ETPUA17_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_eTPU_A_ETPUA18_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_DSPI_D_PCSD3        (PORT_ALT2_FUNC_MODE)
#define    PORT132_eTPU_A_ETPUA18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_eTPU_A_ETPUA18_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_eTPU_A_ETPUA19_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_DSPI_D_PCSD4        (PORT_ALT2_FUNC_MODE)
#define    PORT133_MCAN_0_RX_IN        (PORT_INPUT3_MODE)
#define    PORT133_eTPU_A_ETPUA19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_eTPU_A_ETPUA19_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_eTPU_A_ETPUA20_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_SIU_A_IRQ8        (PORT_ALT2_FUNC_MODE)
#define    PORT134_eTPU_A_ETPUA20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_eTPU_A_ETPUA20_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_eTPU_A_ETPUA21_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_SIU_A_IRQ9        (PORT_ALT2_FUNC_MODE)
#define    PORT135_eTPU_A_ETPUA21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_eTPU_A_ETPUA21_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_eTPU_A_ETPUA22_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT136_SIU_A_IRQ10        (PORT_ALT2_FUNC_MODE)
#define    PORT136_REACM_RCH0_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT136_eTPU_A_ETPUA22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT136_eTPU_A_ETPUA22_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_eTPU_A_ETPUA23_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT137_SIU_A_IRQ11        (PORT_ALT2_FUNC_MODE)
#define    PORT137_REACM_RCH1_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT137_eTPU_A_ETPUA23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT137_eTPU_A_ETPUA23_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_eTPU_A_ETPUA24_INOUT        (PORT_INPUT1_MODE)
#define    PORT138_SIU_A_IRQ12        (PORT_ALT2_FUNC_MODE)
#define    PORT138_REACM_RCH2_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT138_eTPU_A_ETPUA24_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT138_eTPU_A_ETPUA24_IN        (PORT_INPUT1_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_eTPU_A_ETPUA25_INOUT        (PORT_INPUT1_MODE)
#define    PORT139_SIU_A_IRQ13        (PORT_ALT2_FUNC_MODE)
#define    PORT139_REACM_RCH3_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT139_eTPU_A_ETPUA25_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT139_eTPU_A_ETPUA25_IN        (PORT_INPUT1_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_eTPU_A_ETPUA26_INOUT        (PORT_INPUT1_MODE)
#define    PORT140_SIU_A_IRQ14        (PORT_ALT2_FUNC_MODE)
#define    PORT140_REACM_RCH4_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT140_eTPU_A_ETPUA26_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT140_eTPU_A_ETPUA26_IN        (PORT_INPUT1_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_eTPU_A_ETPUA27_INOUT        (PORT_INPUT1_MODE)
#define    PORT141_SIU_A_IRQ15        (PORT_ALT2_FUNC_MODE)
#define    PORT141_REACM_RCH5_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT141_eTPU_A_ETPUA27_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT141_eTPU_A_ETPUA27_IN        (PORT_INPUT1_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_eTPU_A_ETPUA28_INOUT        (PORT_INPUT1_MODE)
#define    PORT142_DSPI_C_PCSC1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_REACM_RCH6_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT142_eTPU_A_ETPUA28_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT142_eTPU_A_ETPUA28_IN        (PORT_INPUT1_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_eTPU_A_ETPUA29_INOUT        (PORT_INPUT1_MODE)
#define    PORT143_DSPI_C_PCSC2        (PORT_ALT2_FUNC_MODE)
#define    PORT143_REACM_RCH7_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT143_eTPU_A_ETPUA29_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT143_eTPU_A_ETPUA29_IN        (PORT_INPUT1_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_eTPU_A_ETPUA30_INOUT        (PORT_INPUT1_MODE)
#define    PORT144_DSPI_C_PCSC3        (PORT_ALT2_FUNC_MODE)
#define    PORT144_REACM_RCH8_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT144_eTPU_A_ETPUA30_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT144_eTPU_A_ETPUA30_IN        (PORT_INPUT1_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_eTPU_A_ETPUA31_INOUT        (PORT_INPUT1_MODE)
#define    PORT145_DSPI_C_PCSC4        (PORT_ALT2_FUNC_MODE)
#define    PORT145_REACM_RCH9_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT145_eTPU_A_ETPUA31_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT145_eTPU_A_ETPUA31_IN        (PORT_INPUT1_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_eTPU_B_TCRCLKB        (PORT_ALT1_FUNC_MODE)
#define    PORT146_SIU_A_IRQ6        (PORT_INPUT2_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_eTPU_B_ETPUB0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT147_eTPU_B_ETPUB16        (PORT_ALT2_FUNC_MODE)
#define    PORT147_eTPU_B_ETPUB0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT147_eTPU_B_ETPUB0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_eTPU_B_ETPUB1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_eTPU_B_ETPUB17        (PORT_ALT2_FUNC_MODE)
#define    PORT148_eTPU_B_ETPUB1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_eTPU_B_ETPUB1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_eTPU_B_ETPUB2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT149_eTPU_B_ETPUB18        (PORT_ALT2_FUNC_MODE)
#define    PORT149_eTPU_B_ETPUB2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT149_eTPU_B_ETPUB2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_eTPU_B_ETPUB3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT150_eTPU_B_ETPUB19        (PORT_ALT2_FUNC_MODE)
#define    PORT150_eTPU_B_ETPUB3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT150_eTPU_B_ETPUB3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_eTPU_B_ETPUB4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT151_eTPU_B_ETPUB20        (PORT_ALT2_FUNC_MODE)
#define    PORT151_eTPU_B_ETPUB4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT151_eTPU_B_ETPUB4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_eTPU_B_ETPUB5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT152_eTPU_B_ETPUB21        (PORT_ALT2_FUNC_MODE)
#define    PORT152_eTPU_B_ETPUB5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT152_eTPU_B_ETPUB5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_eTPU_B_ETPUB6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT153_eTPU_B_ETPUB22        (PORT_ALT2_FUNC_MODE)
#define    PORT153_eTPU_B_ETPUB6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT153_eTPU_B_ETPUB6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_eTPU_B_ETPUB7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT154_eTPU_B_ETPUB23        (PORT_ALT2_FUNC_MODE)
#define    PORT154_eTPU_B_ETPUB7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT154_eTPU_B_ETPUB7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_eTPU_B_ETPUB8_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT155_eTPU_B_ETPUB24        (PORT_ALT2_FUNC_MODE)
#define    PORT155_eTPU_B_ETPUB8_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT155_eTPU_B_ETPUB8_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT156_GPIO        (PORT_GPIO_MODE)
#define    PORT156_eTPU_B_ETPUB9_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT156_eTPU_B_ETPUB25        (PORT_ALT2_FUNC_MODE)
#define    PORT156_eTPU_B_ETPUB9_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT156_eTPU_B_ETPUB9_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT157_GPIO        (PORT_GPIO_MODE)
#define    PORT157_eTPU_B_ETPUB10_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT157_eTPU_B_ETPUB26        (PORT_ALT2_FUNC_MODE)
#define    PORT157_eTPU_B_ETPUB10_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT157_eTPU_B_ETPUB10_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT158_GPIO        (PORT_GPIO_MODE)
#define    PORT158_eTPU_B_ETPUB11_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT158_eTPU_B_ETPUB27        (PORT_ALT2_FUNC_MODE)
#define    PORT158_eTPU_B_ETPUB11_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT158_eTPU_B_ETPUB11_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT159_GPIO        (PORT_GPIO_MODE)
#define    PORT159_eTPU_B_ETPUB12_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT159_eTPU_B_ETPUB28        (PORT_ALT2_FUNC_MODE)
#define    PORT159_eTPU_B_ETPUB12_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT159_eTPU_B_ETPUB12_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT160_GPIO        (PORT_GPIO_MODE)
#define    PORT160_eTPU_B_ETPUB13_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT160_eTPU_B_ETPUB29        (PORT_ALT2_FUNC_MODE)
#define    PORT160_eTPU_B_ETPUB13_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT160_eTPU_B_ETPUB13_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT161_GPIO        (PORT_GPIO_MODE)
#define    PORT161_eTPU_B_ETPUB14_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT161_eTPU_B_ETPUB30        (PORT_ALT2_FUNC_MODE)
#define    PORT161_eTPU_B_ETPUB14_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT161_eTPU_B_ETPUB14_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT162_GPIO        (PORT_GPIO_MODE)
#define    PORT162_eTPU_B_ETPUB15_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT162_eTPU_B_ETPUB31        (PORT_ALT2_FUNC_MODE)
#define    PORT162_eTPU_B_ETPUB15_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT162_eTPU_B_ETPUB15_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT163_GPIO        (PORT_GPIO_MODE)
#define    PORT163_eTPU_B_ETPUB16_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT163_DSPI_A_PCSA1        (PORT_ALT2_FUNC_MODE)
#define    PORT163_eTPU_B_ETPUB16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT163_eTPU_B_ETPUB16_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT164_GPIO        (PORT_GPIO_MODE)
#define    PORT164_eTPU_B_ETPUB17_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT164_DSPI_A_PCSA2        (PORT_ALT2_FUNC_MODE)
#define    PORT164_eTPU_B_ETPUB17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT164_eTPU_B_ETPUB17_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT165_GPIO        (PORT_GPIO_MODE)
#define    PORT165_eTPU_B_ETPUB18_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT165_DSPI_A_PCSA3        (PORT_ALT2_FUNC_MODE)
#define    PORT165_eTPU_B_ETPUB18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT165_eTPU_B_ETPUB18_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT166_GPIO        (PORT_GPIO_MODE)
#define    PORT166_eTPU_B_ETPUB19_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT166_DSPI_A_PCSA4        (PORT_ALT2_FUNC_MODE)
#define    PORT166_eTPU_B_ETPUB19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT166_eTPU_B_ETPUB19_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT167_GPIO        (PORT_GPIO_MODE)
#define    PORT167_eTPU_B_ETPUB20_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT167_eTPU_B_ETPUB20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT167_eTPU_B_ETPUB20_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT168_GPIO        (PORT_GPIO_MODE)
#define    PORT168_eTPU_B_ETPUB21_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT168_eTPU_B_ETPUB21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT168_eTPU_B_ETPUB21_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT169_GPIO        (PORT_GPIO_MODE)
#define    PORT169_eTPU_B_ETPUB22_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT169_REACM_RCH0_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT169_eTPU_B_ETPUB22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT169_eTPU_B_ETPUB22_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT170_GPIO        (PORT_GPIO_MODE)
#define    PORT170_eTPU_B_ETPUB23_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT170_REACM_RCH1_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT170_eTPU_B_ETPUB23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT170_eTPU_B_ETPUB23_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT171_GPIO        (PORT_GPIO_MODE)
#define    PORT171_eTPU_B_ETPUB24_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT171_REACM_RCH2_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT171_eTPU_B_ETPUB24_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT171_eTPU_B_ETPUB24_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT172_GPIO        (PORT_GPIO_MODE)
#define    PORT172_eTPU_B_ETPUB25_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT172_REACM_RCH3_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT172_eTPU_B_ETPUB25_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT172_eTPU_B_ETPUB25_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT173_GPIO        (PORT_GPIO_MODE)
#define    PORT173_eTPU_B_ETPUB26_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT173_REACM_RCH4_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT173_eTPU_B_ETPUB26_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT173_eTPU_B_ETPUB26_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT174_GPIO        (PORT_GPIO_MODE)
#define    PORT174_eTPU_B_ETPUB27_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT174_REACM_RCH5_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT174_eTPU_B_ETPUB27_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT174_eTPU_B_ETPUB27_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT175_GPIO        (PORT_GPIO_MODE)
#define    PORT175_eTPU_B_ETPUB28_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT175_REACM_RCH6_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT175_eTPU_B_ETPUB28_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT175_eTPU_B_ETPUB28_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT176_GPIO        (PORT_GPIO_MODE)
#define    PORT176_eTPU_B_ETPUB29_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT176_REACM_RCH7_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT176_eTPU_B_ETPUB29_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT176_eTPU_B_ETPUB29_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT177_GPIO        (PORT_GPIO_MODE)
#define    PORT177_eTPU_B_ETPUB30_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT177_REACM_RCH8_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT177_eTPU_B_ETPUB30_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT177_eTPU_B_ETPUB30_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT178_GPIO        (PORT_GPIO_MODE)
#define    PORT178_eTPU_B_ETPUB31_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT178_REACM_RCH9_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT178_eTPU_B_ETPUB31_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT178_eTPU_B_ETPUB31_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT179_GPIO        (PORT_GPIO_MODE)
#define    PORT179_eMIOS_A_EMIOS0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT179_eTPU_A_ETPUA0        (PORT_ALT2_FUNC_MODE)
#define    PORT179_REACM_RCH0_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT179_eMIOS_A_EMIOS0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT179_eMIOS_A_EMIOS0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT180_GPIO        (PORT_GPIO_MODE)
#define    PORT180_eMIOS_A_EMIOS1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT180_eTPU_A_ETPUA1        (PORT_ALT2_FUNC_MODE)
#define    PORT180_REACM_RCH1_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT180_DSPI_E_PCSE2        (PORT_ALT4_FUNC_MODE)
#define    PORT180_eMIOS_A_EMIOS1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT180_eMIOS_A_EMIOS1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT181_GPIO        (PORT_GPIO_MODE)
#define    PORT181_eMIOS_A_EMIOS2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT181_eTPU_A_ETPUA2        (PORT_ALT2_FUNC_MODE)
#define    PORT181_REACM_RCH2_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT181_DSPI_E_PCSE3        (PORT_ALT4_FUNC_MODE)
#define    PORT181_eMIOS_A_EMIOS2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT181_eMIOS_A_EMIOS2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT182_GPIO        (PORT_GPIO_MODE)
#define    PORT182_eMIOS_A_EMIOS3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT182_eTPU_A_ETPUA3        (PORT_ALT2_FUNC_MODE)
#define    PORT182_REACM_RCH3_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT182_DSPI_E_PCSE4        (PORT_ALT4_FUNC_MODE)
#define    PORT182_eMIOS_A_EMIOS3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT182_eMIOS_A_EMIOS3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT183_GPIO        (PORT_GPIO_MODE)
#define    PORT183_eMIOS_A_EMIOS4        (PORT_ALT1_FUNC_MODE)
#define    PORT183_eTPU_A_ETPUA4        (PORT_ALT2_FUNC_MODE)
#define    PORT183_REACM_RCH4_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT183_DSPI_E_PCSE5        (PORT_ALT4_FUNC_MODE)
#define    PORT184_GPIO        (PORT_GPIO_MODE)
#define    PORT184_eMIOS_A_EMIOS5        (PORT_ALT1_FUNC_MODE)
#define    PORT184_eTPU_A_ETPUA5        (PORT_ALT2_FUNC_MODE)
#define    PORT184_REACM_RCH5_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT185_GPIO        (PORT_GPIO_MODE)
#define    PORT185_eMIOS_A_EMIOS6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT185_eTPU_A_ETPUA6        (PORT_ALT2_FUNC_MODE)
#define    PORT185_REACM_RCH6_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT185_eMIOS_A_EMIOS6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT185_eMIOS_A_EMIOS6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT186_GPIO        (PORT_GPIO_MODE)
#define    PORT186_eMIOS_A_EMIOS7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT186_eTPU_A_ETPUA7        (PORT_ALT2_FUNC_MODE)
#define    PORT186_REACM_RCH7_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT186_eMIOS_A_EMIOS7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT186_eMIOS_A_EMIOS7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT187_GPIO        (PORT_GPIO_MODE)
#define    PORT187_eMIOS_B_EMIOS0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT187_eTPU_A_ETPUA8        (PORT_ALT2_FUNC_MODE)
#define    PORT187_REACM_RCH8_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT187_eMIOS_B_EMIOS0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT187_eMIOS_B_EMIOS0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT188_GPIO        (PORT_GPIO_MODE)
#define    PORT188_eMIOS_B_EMIOS1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT188_eTPU_A_ETPUA9        (PORT_ALT2_FUNC_MODE)
#define    PORT188_REACM_RCH9_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT188_eMIOS_B_EMIOS1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT188_eMIOS_B_EMIOS1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT189_GPIO        (PORT_GPIO_MODE)
#define    PORT189_eMIOS_B_EMIOS2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT189_DSPI_D_SCKD_INOUT        (PORT_INPUT2_MODE)
#define    PORT189_eMIOS_B_EMIOS2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT189_DSPI_D_SCKD_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT189_eMIOS_B_EMIOS2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT189_DSPI_D_SCKD_IN        (PORT_INPUT2_MODE)
#define    PORT190_GPIO        (PORT_GPIO_MODE)
#define    PORT190_eMIOS_B_EMIOS3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT190_DSPI_D_SIND        (PORT_INPUT2_MODE)
#define    PORT190_eMIOS_B_EMIOS3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT190_eMIOS_B_EMIOS3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT191_GPIO        (PORT_GPIO_MODE)
#define    PORT191_eMIOS_B_EMIOS4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT191_DSPI_C_SOUTC        (PORT_ALT2_FUNC_MODE)
#define    PORT191_eMIOS_B_EMIOS4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT191_eMIOS_B_EMIOS4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT192_GPIO        (PORT_GPIO_MODE)
#define    PORT192_eMIOS_B_EMIOS5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT192_DSPI_D_SOUTD        (PORT_ALT2_FUNC_MODE)
#define    PORT192_eMIOS_B_EMIOS5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT192_eMIOS_B_EMIOS5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT193_GPIO        (PORT_GPIO_MODE)
#define    PORT193_eMIOS_B_EMIOS6        (PORT_ALT1_FUNC_MODE)
#define    PORT193_SIU_A_IRQ0        (PORT_INPUT2_MODE)
#define    PORT193_FlexCAN_D_CNTXD        (PORT_ALT3_FUNC_MODE)
#define    PORT193_REACM_RCH0_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT194_GPIO        (PORT_GPIO_MODE)
#define    PORT194_eMIOS_B_EMIOS7        (PORT_ALT1_FUNC_MODE)
#define    PORT194_SIU_A_IRQ1_IN        (PORT_INPUT2_MODE)
#define    PORT194_FlexCAN_D_CNRXD_IN        (PORT_INPUT3_MODE)
#define    PORT194_REACM_RCH1_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT195_GPIO        (PORT_GPIO_MODE)
#define    PORT195_eMIOS_A_EMIOS16_INOUT        (PORT_INPUT1_MODE)
#define    PORT195_eTPU_B_ETPUB0        (PORT_ALT2_FUNC_MODE)
#define    PORT195_MCAN_1_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT195_REACM_RCH2_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT195_eMIOS_A_EMIOS16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT195_eMIOS_A_EMIOS16_IN        (PORT_INPUT1_MODE)
#define    PORT196_GPIO        (PORT_GPIO_MODE)
#define    PORT196_eMIOS_A_EMIOS17_INOUT        (PORT_INPUT1_MODE)
#define    PORT196_eTPU_B_ETPUB1        (PORT_ALT2_FUNC_MODE)
#define    PORT196_MCAN_1_RX_IN        (PORT_INPUT3_MODE)
#define    PORT196_REACM_RCH3_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT196_eMIOS_A_EMIOS17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT196_eMIOS_A_EMIOS17_IN        (PORT_INPUT1_MODE)
#define    PORT197_GPIO        (PORT_GPIO_MODE)
#define    PORT197_eMIOS_A_EMIOS18_INOUT        (PORT_INPUT1_MODE)
#define    PORT197_eTPU_B_ETPUB2        (PORT_ALT2_FUNC_MODE)
#define    PORT197_REACM_RCH4_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT197_eMIOS_A_EMIOS18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT197_eMIOS_A_EMIOS18_IN        (PORT_INPUT1_MODE)
#define    PORT198_GPIO        (PORT_GPIO_MODE)
#define    PORT198_eMIOS_A_EMIOS19_INOUT        (PORT_INPUT1_MODE)
#define    PORT198_eTPU_B_ETPUB3        (PORT_ALT2_FUNC_MODE)
#define    PORT198_REACM_RCH5_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT198_eMIOS_A_EMIOS19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT198_eMIOS_A_EMIOS19_IN        (PORT_INPUT1_MODE)
#define    PORT199_GPIO        (PORT_GPIO_MODE)
#define    PORT199_eMIOS_A_EMIOS20_INOUT        (PORT_INPUT1_MODE)
#define    PORT199_eTPU_B_ETPUB4        (PORT_ALT2_FUNC_MODE)
#define    PORT199_REACM_RCH6_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT199_eMIOS_A_EMIOS20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT199_eMIOS_A_EMIOS20_IN        (PORT_INPUT1_MODE)
#define    PORT200_GPIO        (PORT_GPIO_MODE)
#define    PORT200_eMIOS_A_EMIOS21_INOUT        (PORT_INPUT1_MODE)
#define    PORT200_eTPU_B_ETPUB5        (PORT_ALT2_FUNC_MODE)
#define    PORT200_REACM_RCH7_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT200_eMIOS_A_EMIOS21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT200_eMIOS_A_EMIOS21_IN        (PORT_INPUT1_MODE)
#define    PORT201_GPIO        (PORT_GPIO_MODE)
#define    PORT201_eMIOS_A_EMIOS22_INOUT        (PORT_INPUT1_MODE)
#define    PORT201_eTPU_B_ETPUB6        (PORT_ALT2_FUNC_MODE)
#define    PORT201_REACM_RCH8_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT201_eMIOS_A_EMIOS22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT201_eMIOS_A_EMIOS22_IN        (PORT_INPUT1_MODE)
#define    PORT202_GPIO        (PORT_GPIO_MODE)
#define    PORT202_eMIOS_A_EMIOS23_INOUT        (PORT_INPUT1_MODE)
#define    PORT202_eTPU_B_ETPUB7        (PORT_ALT2_FUNC_MODE)
#define    PORT202_REACM_RCH9_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT202_eMIOS_A_EMIOS23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT202_eMIOS_A_EMIOS23_IN        (PORT_INPUT1_MODE)
#define    PORT203_GPIO        (PORT_GPIO_MODE)
#define    PORT203_eMIOS_B_EMIOS16_INOUT        (PORT_INPUT1_MODE)
#define    PORT203_DSPI_B_PCSB0_INOUT        (PORT_INPUT2_MODE)
#define    PORT203_eMIOS_B_EMIOS16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT203_DSPI_B_PCSB0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT203_eMIOS_B_EMIOS16_IN        (PORT_INPUT1_MODE)
#define    PORT203_DSPI_B_PCSB0_IN        (PORT_INPUT2_MODE)
#define    PORT204_GPIO        (PORT_GPIO_MODE)
#define    PORT204_eMIOS_B_EMIOS17_INOUT        (PORT_INPUT1_MODE)
#define    PORT204_DSPI_B_PCSB1        (PORT_ALT2_FUNC_MODE)
#define    PORT204_eMIOS_B_EMIOS17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT204_eMIOS_B_EMIOS17_IN        (PORT_INPUT1_MODE)
#define    PORT208_GPIO        (PORT_GPIO_MODE)
#define    PORT208_SoC_PLLCFG0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT208_SIU_A_IRQ4_IN        (PORT_INPUT2_MODE)
#define    PORT208_eTPU_C_ETPUC9_INOUT        (PORT_INPUT3_MODE)
#define    PORT208_SIPI_TXN        (PORT_ALT4_FUNC_MODE)
#define    PORT208_eTPU_C_ETPUC9_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT208_eTPU_C_ETPUC9_IN        (PORT_INPUT3_MODE)
#define    PORT209_GPIO        (PORT_GPIO_MODE)
#define    PORT209_SoC_PLLCFG1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT209_SIU_A_IRQ5_IN        (PORT_INPUT2_MODE)
#define    PORT209_DSPI_D_SOUTD        (PORT_ALT3_FUNC_MODE)
#define    PORT209_SIPI_TXP        (PORT_ALT4_FUNC_MODE)
#define    PORT210_GPIO        (PORT_GPIO_MODE)
#define    PORT210_SoC_PLLCFG2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT210_eTPU_C_ETPUC3_INOUT        (PORT_INPUT2_MODE)
#define    PORT210_DSPI_E_PCSE1        (PORT_ALT3_FUNC_MODE)
#define    PORT210_SIPI_REFCLK_INOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT210_eTPU_C_ETPUC3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT210_SIPI_REFCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT210_eTPU_C_ETPUC3_IN        (PORT_INPUT2_MODE)
#define    PORT210_SIPI_REFCLK_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT212_GPIO        (PORT_GPIO_MODE)
#define    PORT212_SoC_BOOTCFG1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT212_SIU_A_IRQ3_IN        (PORT_INPUT2_MODE)
#define    PORT212_eTPU_C_ETPUC0_INOUT        (PORT_INPUT3_MODE)
#define    PORT212_SIPI_RXP        (PORT_ALT4_FUNC_MODE)
#define    PORT212_eTPU_C_ETPUC0_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT212_eTPU_C_ETPUC0_IN        (PORT_INPUT3_MODE)
#define    PORT213_GPIO        (PORT_GPIO_MODE)
#define    PORT213_SoC_WKPCFG_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT213_SIU_A_NMI_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT213_eTPU_C_ETPUC1_INOUT        (PORT_INPUT3_MODE)
#define    PORT213_SIPI_RXN        (PORT_ALT4_FUNC_MODE)
#define    PORT213_eTPU_C_ETPUC1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT213_eTPU_C_ETPUC1_IN        (PORT_INPUT3_MODE)
#define    PORT214_GPIO        (PORT_GPIO_MODE)
#define    PORT214_ENGCLK        (PORT_ALT1_FUNC_MODE)
#define    PORT219_GPIO        (PORT_GPIO_MODE)
#define    PORT219_MCKO        (PORT_ALT1_FUNC_MODE)
#define    PORT220_GPIO        (PORT_GPIO_MODE)
#define    PORT221_GPIO        (PORT_GPIO_MODE)
#define    PORT222_GPIO        (PORT_GPIO_MODE)
#define    PORT223_GPIO        (PORT_GPIO_MODE)
#define    PORT223_eSCI_E_TXDE        (PORT_INPUT2_MODE)
#define    PORT224_GPIO        (PORT_GPIO_MODE)
#define    PORT224_MSEO0        (PORT_ALT1_FUNC_MODE)
#define    PORT225_GPIO        (PORT_GPIO_MODE)
#define    PORT225_MSEO1        (PORT_ALT1_FUNC_MODE)
#define    PORT226_GPIO        (PORT_GPIO_MODE)
#define    PORT226_RDY        (PORT_ALT1_FUNC_MODE)
#define    PORT227_GPIO        (PORT_GPIO_MODE)
#define    PORT227_EVTO        (PORT_ALT1_FUNC_MODE)
#define    PORT228_GPIO        (PORT_GPIO_MODE)
#define    PORT228_TDO        (PORT_ALT1_FUNC_MODE)
#define    PORT229_GPIO        (PORT_GPIO_MODE)
#define    PORT229_D_CLKOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT230_GPIO        (PORT_GPIO_MODE)
#define    PORT230_RSTOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT231_GPIO        (PORT_GPIO_MODE)
#define    PORT232_GPIO        (PORT_GPIO_MODE)
#define    PORT233_GPIO        (PORT_GPIO_MODE)
#define    PORT234_GPIO        (PORT_GPIO_MODE)
#define    PORT235_GPIO        (PORT_GPIO_MODE)
#define    PORT235_DSPI_C_SCKC_INOUT        (PORT_INPUT1_MODE)
#define    PORT235_DSPI_C_SCK_C_LVDS_P        (PORT_ALT2_FUNC_MODE)
#define    PORT235_DSPI_C_SCKC_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT235_DSPI_C_SCKC_IN        (PORT_INPUT1_MODE)
#define    PORT236_GPIO        (PORT_GPIO_MODE)
#define    PORT236_DSPI_C_SINC_IN        (PORT_INPUT1_MODE)
#define    PORT236_DSPI_C_SCK_C_LVDS_N_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT237_GPIO        (PORT_GPIO_MODE)
#define    PORT237_DSPI_C_SOUTC        (PORT_ALT1_FUNC_MODE)
#define    PORT237_DSPI_C_SOUT_C_LVDS_P        (PORT_ALT2_FUNC_MODE)
#define    PORT238_GPIO        (PORT_GPIO_MODE)
#define    PORT238_DSPI_C_PCSC0_INOUT        (PORT_INPUT1_MODE)
#define    PORT238_DSPI_C_SOUT_C_LVDS_N_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT238_DSPI_C_PCSC0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT238_DSPI_C_PCSC0_IN        (PORT_INPUT1_MODE)
#define    PORT239_GPIO        (PORT_GPIO_MODE)
#define    PORT239_DSPI_C_PCSC1        (PORT_ALT1_FUNC_MODE)
#define    PORT239_eSCI_D_TXDD        (PORT_ALT2_FUNC_MODE)
#define    PORT240_GPIO        (PORT_GPIO_MODE)
#define    PORT240_DSPI_C_PCSC2        (PORT_ALT1_FUNC_MODE)
#define    PORT240_DSPI_D_SCK_D_LVDS_P        (PORT_ALT2_FUNC_MODE)
#define    PORT240_DSPI_D_SCKD_INOUT        (PORT_INPUT3_MODE)
#define    PORT240_DSPI_D_SCKD_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT240_DSPI_D_SCKD_IN        (PORT_INPUT3_MODE)
#define    PORT241_GPIO        (PORT_GPIO_MODE)
#define    PORT241_DSPI_C_PCSC3        (PORT_ALT1_FUNC_MODE)
#define    PORT241_DSPI_D_SCK_D_LVDS_N_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT241_DSPI_D_SIND_IN        (PORT_INPUT3_MODE)
#define    PORT242_GPIO        (PORT_GPIO_MODE)
#define    PORT242_DSPI_C_PCSC4        (PORT_ALT1_FUNC_MODE)
#define    PORT242_MCAN_0_TX_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT242_DSPI_D_SOUT_D_LVDS_P        (PORT_ALT3_FUNC_MODE)
#define    PORT242_DSPI_D_SOUTD        (PORT_ALT4_FUNC_MODE)
#define    PORT243_GPIO        (PORT_GPIO_MODE)
#define    PORT243_DSPI_C_PCSC5        (PORT_ALT1_FUNC_MODE)
#define    PORT243_MCAN_0_RX_IN        (PORT_INPUT2_MODE)
#define    PORT243_DSPI_D_SOUT_D_LVDS_N_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT243_DSPI_D_PCSD0_INOUT        (PORT_INPUT4_MODE)
#define    PORT243_DSPI_D_PCSD0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT243_DSPI_D_PCSD0_IN        (PORT_INPUT4_MODE)
#define    PORT244_GPIO        (PORT_GPIO_MODE)
#define    PORT244_eSCI_C_TXDC        (PORT_ALT1_FUNC_MODE)
#define    PORT244_eQADC_A_eQADC_B_ETRIG0_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT245_GPIO        (PORT_GPIO_MODE)
#define    PORT245_eSCI_C_RXDC_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT246_GPIO        (PORT_GPIO_MODE)
#define    PORT246_FlexCAN_D_CNTXD        (PORT_ALT1_FUNC_MODE)
#define    PORT246_MCAN_1_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT247_GPIO        (PORT_GPIO_MODE)
#define    PORT247_FlexCAN_D_CNRXD_IN        (PORT_INPUT1_MODE)
#define    PORT247_MCAN_1_RX_IN        (PORT_INPUT3_MODE)
#define    PORT248_GPIO        (PORT_GPIO_MODE)
#define    PORT248_FEC_FEC_TXD0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT248_SENT_A_SENT0_A_IN        (PORT_INPUT2_MODE)
#define    PORT249_GPIO        (PORT_GPIO_MODE)
#define    PORT249_FEC_FEC_RX_DV_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT249_SENT_A_SENT1_A_IN        (PORT_INPUT2_MODE)
#define    PORT250_GPIO        (PORT_GPIO_MODE)
#define    PORT250_FEC_FEC_RXD0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT250_SENT_A_SENT2_A_IN        (PORT_INPUT2_MODE)
#define    PORT251_GPIO        (PORT_GPIO_MODE)
#define    PORT251_FEC_FEC_TXD1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT251_SENT_A_SENT3_A_IN        (PORT_INPUT2_MODE)
#define    PORT252_GPIO        (PORT_GPIO_MODE)
#define    PORT252_FEC_FEC_TXEN_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT252_SENT_A_SENT4_A_IN        (PORT_INPUT2_MODE)
#define    PORT253_GPIO        (PORT_GPIO_MODE)
#define    PORT253_FEC_FEC_RXD1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT253_SENT_A_SENT5_A_IN        (PORT_INPUT2_MODE)
#define    PORT432_GPIO        (PORT_GPIO_MODE)
#define    PORT432_eMIOS_B_EMIOS18_INOUT        (PORT_INPUT1_MODE)
#define    PORT432_DSPI_B_PCSB2        (PORT_ALT2_FUNC_MODE)
#define    PORT432_eMIOS_B_EMIOS18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT432_eMIOS_B_EMIOS18_IN        (PORT_INPUT1_MODE)
#define    PORT433_GPIO        (PORT_GPIO_MODE)
#define    PORT433_eMIOS_B_EMIOS19_INOUT        (PORT_INPUT1_MODE)
#define    PORT433_DSPI_B_PCSB3        (PORT_ALT2_FUNC_MODE)
#define    PORT433_eMIOS_B_EMIOS19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT433_eMIOS_B_EMIOS19_IN        (PORT_INPUT1_MODE)
#define    PORT434_GPIO        (PORT_GPIO_MODE)
#define    PORT434_eMIOS_B_EMIOS20_INOUT        (PORT_INPUT1_MODE)
#define    PORT434_DSPI_C_PCSC0_INOUT        (PORT_INPUT2_MODE)
#define    PORT434_eMIOS_B_EMIOS20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT434_DSPI_C_PCSC0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT434_eMIOS_B_EMIOS20_IN        (PORT_INPUT1_MODE)
#define    PORT434_DSPI_C_PCSC0_IN        (PORT_INPUT2_MODE)
#define    PORT435_GPIO        (PORT_GPIO_MODE)
#define    PORT435_eMIOS_B_EMIOS21_INOUT        (PORT_INPUT1_MODE)
#define    PORT435_DSPI_C_PCSC1        (PORT_ALT2_FUNC_MODE)
#define    PORT435_eMIOS_B_EMIOS21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT435_eMIOS_B_EMIOS21_IN        (PORT_INPUT1_MODE)
#define    PORT436_GPIO        (PORT_GPIO_MODE)
#define    PORT436_eMIOS_B_EMIOS22_INOUT        (PORT_INPUT1_MODE)
#define    PORT436_DSPI_C_PCSC2        (PORT_ALT2_FUNC_MODE)
#define    PORT436_eMIOS_B_EMIOS22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT436_eMIOS_B_EMIOS22_IN        (PORT_INPUT1_MODE)
#define    PORT437_GPIO        (PORT_GPIO_MODE)
#define    PORT437_eMIOS_B_EMIOS23_INOUT        (PORT_INPUT1_MODE)
#define    PORT437_DSPI_C_PCSC5        (PORT_ALT2_FUNC_MODE)
#define    PORT437_eMIOS_B_EMIOS23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT437_eMIOS_B_EMIOS23_IN        (PORT_INPUT1_MODE)
#define    PORT440_GPI        (PORT_GPIO_MODE)
#define    PORT440_eTPU_C_TCRCLKC_IN        (PORT_INPUT1_MODE)
#define    PORT440_SIU_A_IRQ6_IN        (PORT_INPUT2_MODE)
#define    PORT440_eQADC_B_ANB40_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT441_GPI        (PORT_GPIO_MODE)
#define    PORT441_eTPU_C_ETPUC0_IN        (PORT_INPUT1_MODE)
#define    PORT441_SENT_A_SENT0_A_IN        (PORT_INPUT2_MODE)
#define    PORT441_eQADC_B_ANB41_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT442_GPI        (PORT_GPIO_MODE)
#define    PORT442_eTPU_C_ETPUC1_IN        (PORT_INPUT1_MODE)
#define    PORT442_SENT_A_SENT1_A_IN        (PORT_INPUT2_MODE)
#define    PORT442_eQADC_B_ANB42_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT443_GPIO        (PORT_GPIO_MODE)
#define    PORT443_eTPU_C_ETPUC2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT443_SENT_A_SENT3_A_IN        (PORT_INPUT2_MODE)
#define    PORT443_eTPU_C_ETPUC2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT443_eTPU_C_ETPUC2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT444_GPI        (PORT_GPIO_MODE)
#define    PORT444_eTPU_C_ETPUC3_IN        (PORT_INPUT1_MODE)
#define    PORT444_SENT_A_SENT4_A_IN        (PORT_INPUT2_MODE)
#define    PORT444_eQADC_B_ANB45_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT445_GPIO        (PORT_GPIO_MODE)
#define    PORT445_eTPU_C_ETPUC4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT445_SENT_A_SENT5_A_IN        (PORT_INPUT2_MODE)
#define    PORT445_eTPU_C_TCRCLKC_IN        (PORT_INPUT3_MODE)
#define    PORT445_eTPU_C_ETPUC4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT445_eTPU_C_ETPUC4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT446_GPIO        (PORT_GPIO_MODE)
#define    PORT446_eTPU_C_ETPUC5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT446_DSPI_E_PCSE2        (PORT_ALT2_FUNC_MODE)
#define    PORT446_SENT_B_SENT0_B_IN        (PORT_INPUT3_MODE)
#define    PORT446_eTPU_C_ETPUC5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT446_eTPU_C_ETPUC5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT447_GPIO        (PORT_GPIO_MODE)
#define    PORT447_eTPU_C_ETPUC6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT447_DSPI_E_PCSE3        (PORT_ALT2_FUNC_MODE)
#define    PORT447_SENT_B_SENT1_B_IN        (PORT_INPUT3_MODE)
#define    PORT447_eTPU_C_ETPUC6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT447_eTPU_C_ETPUC6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT448_GPIO        (PORT_GPIO_MODE)
#define    PORT448_eTPU_C_ETPUC7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT448_DSPI_E_PCSE4        (PORT_ALT2_FUNC_MODE)
#define    PORT448_SENT_B_SENT2_B_IN        (PORT_INPUT3_MODE)
#define    PORT448_eTPU_C_ETPUC7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT448_eTPU_C_ETPUC7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT449_GPIO        (PORT_GPIO_MODE)
#define    PORT449_eTPU_C_ETPUC8_INOUT        (PORT_INPUT1_MODE)
#define    PORT449_DSPI_E_PCSE5        (PORT_ALT2_FUNC_MODE)
#define    PORT449_SENT_B_SENT3_B_IN        (PORT_INPUT3_MODE)
#define    PORT449_eTPU_C_ETPUC8_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT449_eTPU_C_ETPUC8_IN        (PORT_INPUT1_MODE)
#define    PORT450_GPI        (PORT_GPIO_MODE)
#define    PORT450_eTPU_C_ETPUC9_IN        (PORT_INPUT1_MODE)
#define    PORT450_SIU_A_IRQ0_IN        (PORT_INPUT2_MODE)
#define    PORT450_SENT_B_SENT4_B_IN        (PORT_INPUT3_MODE)
#define    PORT450_eQADC_B_ANB44_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT451_GPIO        (PORT_GPIO_MODE)
#define    PORT451_eTPU_C_ETPUC10_INOUT        (PORT_INPUT1_MODE)
#define    PORT451_SIU_A_IRQ1_IN        (PORT_INPUT2_MODE)
#define    PORT451_SENT_B_SENT5_B_IN        (PORT_INPUT3_MODE)
#define    PORT451_eTPU_C_ETPUC10_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT451_eTPU_C_ETPUC10_IN        (PORT_INPUT1_MODE)
#define    PORT452_GPIO        (PORT_GPIO_MODE)
#define    PORT452_eTPU_C_ETPUC11_INOUT        (PORT_INPUT1_MODE)
#define    PORT452_SIU_A_IRQ2_IN        (PORT_INPUT2_MODE)
#define    PORT452_eTPU_C_ETPUC11_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT452_eTPU_C_ETPUC11_IN        (PORT_INPUT1_MODE)
#define    PORT453_GPIO        (PORT_GPIO_MODE)
#define    PORT453_eTPU_C_ETPUC12_INOUT        (PORT_INPUT1_MODE)
#define    PORT453_SIU_A_IRQ3_IN        (PORT_INPUT2_MODE)
#define    PORT453_MCAN_1_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT453_eTPU_C_ETPUC12_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT453_eTPU_C_ETPUC12_IN        (PORT_INPUT1_MODE)
#define    PORT454_GPIO        (PORT_GPIO_MODE)
#define    PORT454_eTPU_C_ETPUC13_INOUT        (PORT_INPUT1_MODE)
#define    PORT454_SIU_A_IRQ4_IN        (PORT_INPUT2_MODE)
#define    PORT454_PSI5A_SDOUT0_PSI5A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT454_REACM_RCH0_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT454_eTPU_C_ETPUC13_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT454_eTPU_C_ETPUC13_IN        (PORT_INPUT1_MODE)
#define    PORT455_GPIO        (PORT_GPIO_MODE)
#define    PORT455_eTPU_C_ETPUC14_INOUT        (PORT_INPUT1_MODE)
#define    PORT455_SIU_A_IRQ5_IN        (PORT_INPUT2_MODE)
#define    PORT455_PSI5A_SDIN0_PSI5A_IN        (PORT_ALT3_FUNC_MODE)
#define    PORT455_REACM_RCH1_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT455_eTPU_C_ETPUC14_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT455_eTPU_C_ETPUC14_IN        (PORT_INPUT1_MODE)
#define    PORT456_GPIO        (PORT_GPIO_MODE)
#define    PORT456_eTPU_C_ETPUC15_INOUT        (PORT_INPUT1_MODE)
#define    PORT456_MCAN_1_RX_IN        (PORT_INPUT2_MODE)
#define    PORT456_REACM_RCH2_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT456_eTPU_C_ETPUC15_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT456_eTPU_C_ETPUC15_IN        (PORT_INPUT1_MODE)
#define    PORT457_GPIO        (PORT_GPIO_MODE)
#define    PORT457_eTPU_C_ETPUC16_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT457_MCAN_1_TX_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT457_REACM_RCH3_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT457_eTPU_C_ETPUC16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT457_eTPU_C_ETPUC16_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT458_GPIO        (PORT_GPIO_MODE)
#define    PORT458_eTPU_C_ETPUC17_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT458_eSCI_F_TXDF        (PORT_ALT2_FUNC_MODE)
#define    PORT458_REACM_RCH4_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT458_eTPU_C_ETPUC17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT458_eTPU_C_ETPUC17_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT459_GPIO        (PORT_GPIO_MODE)
#define    PORT459_eTPU_C_ETPUC18_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT459_eSCI_F_RXDF_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT459_eTPU_C_ETPUC18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT459_eTPU_C_ETPUC18_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT460_GPIO        (PORT_GPIO_MODE)
#define    PORT460_eTPU_C_ETPUC19_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT460_eSCI_A_TXDA        (PORT_INPUT2_MODE)
#define    PORT460_PSI5A_SDOUT0_PSI5B_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT460_eTPU_C_ETPUC19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT460_eTPU_C_ETPUC19_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT461_GPIO        (PORT_GPIO_MODE)
#define    PORT461_eTPU_C_ETPUC20_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT461_eSCI_A_RXDA_IN        (PORT_INPUT2_MODE)
#define    PORT461_PSI5A_SDIN0_PSI5B_IN        (PORT_ALT3_FUNC_MODE)
#define    PORT461_eTPU_C_ETPUC20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT461_eTPU_C_ETPUC20_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT462_GPIO        (PORT_GPIO_MODE)
#define    PORT462_eTPU_C_ETPUC21_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT462_eSCI_B_TXDB        (PORT_INPUT2_MODE)
#define    PORT462_eTPU_C_ETPUC21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT462_eTPU_C_ETPUC21_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT463_GPIO        (PORT_GPIO_MODE)
#define    PORT463_eTPU_C_ETPUC22_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT463_eSCI_B_RXDB_IN        (PORT_INPUT2_MODE)
#define    PORT463_eTPU_C_ETPUC22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT463_eTPU_C_ETPUC22_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT464_GPIO        (PORT_GPIO_MODE)
#define    PORT464_eTPU_C_ETPUC23_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT464_DSPI_D_PCSD5        (PORT_ALT2_FUNC_MODE)
#define    PORT464_eQADC_A_MAA0        (PORT_ALT3_FUNC_MODE)
#define    PORT464_eQADC_B_MAB0        (PORT_ALT4_FUNC_MODE)
#define    PORT464_eTPU_C_ETPUC23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT464_eTPU_C_ETPUC23_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT465_GPIO        (PORT_GPIO_MODE)
#define    PORT465_eTPU_C_ETPUC24_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT465_DSPI_D_PCSD4        (PORT_ALT2_FUNC_MODE)
#define    PORT465_eQADC_A_MAA1        (PORT_ALT3_FUNC_MODE)
#define    PORT465_eQADC_B_MAB1        (PORT_ALT4_FUNC_MODE)
#define    PORT465_eTPU_C_ETPUC24_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT465_eTPU_C_ETPUC24_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT466_GPIO        (PORT_GPIO_MODE)
#define    PORT466_eTPU_C_ETPUC25_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT466_DSPI_D_PCSD3        (PORT_ALT2_FUNC_MODE)
#define    PORT466_eQADC_A_MAA2        (PORT_ALT3_FUNC_MODE)
#define    PORT466_eQADC_B_MAB2        (PORT_ALT4_FUNC_MODE)
#define    PORT466_eTPU_C_ETPUC25_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT466_eTPU_C_ETPUC25_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT467_GPIO        (PORT_GPIO_MODE)
#define    PORT467_eTPU_C_ETPUC26_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT467_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT467_eQADC_B_MAB0        (PORT_ALT3_FUNC_MODE)
#define    PORT467_eTPU_C_ETPUC26_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT467_eTPU_C_ETPUC26_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT468_GPIO        (PORT_GPIO_MODE)
#define    PORT468_eTPU_C_ETPUC27_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT468_DSPI_D_PCSD1        (PORT_ALT2_FUNC_MODE)
#define    PORT468_REACM_RCH5_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT468_eQADC_B_MAB1        (PORT_ALT4_FUNC_MODE)
#define    PORT468_eTPU_C_ETPUC27_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT468_eTPU_C_ETPUC27_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT469_GPIO        (PORT_GPIO_MODE)
#define    PORT469_eTPU_C_ETPUC28_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT469_DSPI_D_PCSD0_INOUT        (PORT_INPUT2_MODE)
#define    PORT469_REACM_RCH6_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT469_eQADC_B_MAB2        (PORT_ALT4_FUNC_MODE)
#define    PORT469_eTPU_C_ETPUC28_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT469_DSPI_D_PCSD0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT469_eTPU_C_ETPUC28_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT469_DSPI_D_PCSD0_IN        (PORT_INPUT2_MODE)
#define    PORT470_GPIO        (PORT_GPIO_MODE)
#define    PORT470_eTPU_C_ETPUC29_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT470_DSPI_D_SCKD_INOUT        (PORT_INPUT2_MODE)
#define    PORT470_REACM_RCH7_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT470_eTPU_C_ETPUC29_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT470_DSPI_D_SCKD_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT470_eTPU_C_ETPUC29_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT470_DSPI_D_SCKD_IN        (PORT_INPUT2_MODE)
#define    PORT471_GPIO        (PORT_GPIO_MODE)
#define    PORT471_eTPU_C_ETPUC30_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT471_DSPI_D_SOUTD        (PORT_ALT2_FUNC_MODE)
#define    PORT471_REACM_RCH8_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT471_eTPU_C_ETPUC30_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT471_eTPU_C_ETPUC30_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT472_GPIO        (PORT_GPIO_MODE)
#define    PORT472_eTPU_C_ETPUC31_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT472_DSPI_D_SIND_IN        (PORT_INPUT2_MODE)
#define    PORT472_REACM_RCH9_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT472_eTPU_C_ETPUC31_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT472_eTPU_C_ETPUC31_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT474_GPI        (PORT_GPIO_MODE)
#define    PORT474_FEC_FEC_TXCLK_REFCLK_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT474_SENT_B_SENT0_B_IN        (PORT_INPUT2_MODE)
#define    PORT475_GPI        (PORT_GPIO_MODE)
#define    PORT475_SENT_A_SENT2_A_IN        (PORT_INPUT1_MODE)
#define    PORT475_eQADC_B_ANB43_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT476_GPI        (PORT_GPIO_MODE)
#define    PORT476_eQADC_B_ANB8_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT476_eTPU_A_ETPUA31_IN        (PORT_INPUT2_MODE)
#define    PORT476_eMIOS_A_EMIOS16_IN        (PORT_INPUT3_MODE)
#define    PORT477_GPI        (PORT_GPIO_MODE)
#define    PORT477_eQADC_B_ANB9_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT477_eTPU_A_ETPUA30_IN        (PORT_INPUT2_MODE)
#define    PORT477_eMIOS_A_EMIOS17_IN        (PORT_INPUT3_MODE)
#define    PORT478_GPI        (PORT_GPIO_MODE)
#define    PORT478_eQADC_B_ANB10_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT478_eTPU_A_ETPUA29_IN        (PORT_INPUT2_MODE)
#define    PORT478_eMIOS_A_EMIOS18_IN        (PORT_INPUT3_MODE)
#define    PORT479_GPI        (PORT_GPIO_MODE)
#define    PORT479_eQADC_B_ANB11_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT479_eTPU_A_ETPUA28_IN        (PORT_INPUT2_MODE)
#define    PORT479_eMIOS_A_EMIOS19_IN        (PORT_INPUT3_MODE)
#define    PORT480_GPI        (PORT_GPIO_MODE)
#define    PORT480_eQADC_B_ANB12_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT480_eTPU_A_ETPUA27_IN        (PORT_INPUT2_MODE)
#define    PORT480_eMIOS_A_EMIOS20_IN        (PORT_INPUT3_MODE)
#define    PORT481_GPI        (PORT_GPIO_MODE)
#define    PORT481_eQADC_B_ANB13_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT481_eTPU_A_ETPUA26_IN        (PORT_INPUT2_MODE)
#define    PORT481_eMIOS_A_EMIOS21_IN        (PORT_INPUT3_MODE)
#define    PORT482_GPI        (PORT_GPIO_MODE)
#define    PORT482_eQADC_B_ANB14_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT482_eTPU_A_ETPUA25_IN        (PORT_INPUT2_MODE)
#define    PORT482_eMIOS_A_EMIOS22_IN        (PORT_INPUT3_MODE)
#define    PORT483_GPI        (PORT_GPIO_MODE)
#define    PORT483_eQADC_B_ANB15_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT483_eTPU_A_ETPUA24_IN        (PORT_INPUT2_MODE)
#define    PORT483_eMIOS_A_EMIOS23_IN        (PORT_INPUT3_MODE)
#define    PORT484_GPI        (PORT_GPIO_MODE)
#define    PORT484_eQADC_B_ANB16_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT484_eTPU_C_ETPUC15_IN        (PORT_INPUT2_MODE)
#define    PORT484_eMIOS_B_EMIOS16_IN        (PORT_INPUT3_MODE)
#define    PORT485_GPI        (PORT_GPIO_MODE)
#define    PORT485_eQADC_B_ANB17_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT485_eTPU_C_ETPUC14_IN        (PORT_INPUT2_MODE)
#define    PORT485_eMIOS_B_EMIOS17_IN        (PORT_INPUT3_MODE)
#define    PORT486_GPI        (PORT_GPIO_MODE)
#define    PORT486_eQADC_B_ANB18_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT486_eTPU_C_ETPUC13_IN        (PORT_INPUT2_MODE)
#define    PORT486_eMIOS_B_EMIOS18_IN        (PORT_INPUT3_MODE)
#define    PORT487_GPI        (PORT_GPIO_MODE)
#define    PORT487_eQADC_B_ANB19_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT487_eTPU_C_ETPUC12_IN        (PORT_INPUT2_MODE)
#define    PORT487_eMIOS_B_EMIOS19_IN        (PORT_INPUT3_MODE)
#define    PORT488_GPI        (PORT_GPIO_MODE)
#define    PORT488_eQADC_B_ANB20_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT488_eTPU_C_ETPUC11_IN        (PORT_INPUT2_MODE)
#define    PORT488_eMIOS_B_EMIOS20_IN        (PORT_INPUT3_MODE)
#define    PORT489_GPI        (PORT_GPIO_MODE)
#define    PORT489_eQADC_B_ANB21_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT489_eTPU_C_ETPUC10_IN        (PORT_INPUT2_MODE)
#define    PORT489_eMIOS_B_EMIOS21_IN        (PORT_INPUT3_MODE)
#define    PORT490_GPI        (PORT_GPIO_MODE)
#define    PORT490_eQADC_B_ANB22_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT490_eTPU_C_ETPUC9_IN        (PORT_INPUT2_MODE)
#define    PORT490_eMIOS_B_EMIOS22_IN        (PORT_INPUT3_MODE)
#define    PORT491_GPI        (PORT_GPIO_MODE)
#define    PORT491_eQADC_B_ANB23_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT491_eTPU_C_ETPUC8_IN        (PORT_INPUT2_MODE)
#define    PORT491_eMIOS_B_EMIOS23_IN        (PORT_INPUT3_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_2"!]

#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_FlexCAN_A_CNTXA        (PORT_ALT1_FUNC_MODE)
#define    PORT83_eSCI_A_TXDA        (PORT_INPUT2_MODE)
#define    PORT83_MCAN_0_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_FlexCAN_A_CNRXA        (PORT_ALT1_FUNC_MODE)
#define    PORT84_eSCI_A_RXDA        (PORT_INPUT2_MODE)
#define    PORT84_MCAN_0_RX_IN        (PORT_INPUT3_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_FlexCAN_B_CNTXB        (PORT_ALT1_FUNC_MODE)
#define    PORT85_DSPI_C_PCSC3        (PORT_ALT2_FUNC_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_FlexCAN_B_CNRXB        (PORT_ALT1_FUNC_MODE)
#define    PORT86_DSPI_C_PCSC4        (PORT_ALT2_FUNC_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_FlexCAN_C_CNTXC        (PORT_ALT1_FUNC_MODE)
#define    PORT87_DSPI_D_PCSD3        (PORT_ALT2_FUNC_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FlexCAN_C_CNRXC        (PORT_ALT1_FUNC_MODE)
#define    PORT88_DSPI_D_PCSD4        (PORT_ALT2_FUNC_MODE)
#define    PORT88_eSCI_E_RXDE        (PORT_ALT3_FUNC_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_eSCI_A_TXDA        (PORT_INPUT1_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_eSCI_A_RXDA_IN        (PORT_INPUT1_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_eSCI_B_TXDB        (PORT_INPUT1_MODE)
#define    PORT91_DSPI_D_PCSD1        (PORT_ALT2_FUNC_MODE)
#define    PORT91_MCAN_0_RX_IN        (PORT_INPUT3_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_eSCI_B_RXDB        (PORT_INPUT1_MODE)
#define    PORT92_DSPI_D_PCSD5        (PORT_ALT2_FUNC_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_DSPI_A_SCKA_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_DSPI_A_SCKA_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT93_DSPI_A_SCKA_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_DSPI_C_PCSC1        (PORT_ALT2_FUNC_MODE)
#define    PORT93_MCAN_0_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT93_SENT_B_SENT1_B_IN        (PORT_INPUT4_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_DSPI_A_SINA        (PORT_ALT1_FUNC_MODE)
#define    PORT94_DSPI_C_PCSC2        (PORT_ALT2_FUNC_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_DSPI_A_SOUTA        (PORT_ALT1_FUNC_MODE)
#define    PORT95_DSPI_C_PCSC5        (PORT_ALT2_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_DSPI_A_PCSA0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT96_DSPI_A_PCSA0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT96_DSPI_A_PCSA0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT96_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_DSPI_A_PCSA1        (PORT_ALT1_FUNC_MODE)
#define    PORT97_DSPI_E_PCSE0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT97_DSPI_E_PCSE0_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT97_DSPI_E_PCSE0_INOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_DSPI_A_PCSA2        (PORT_ALT1_FUNC_MODE)
#define    PORT98_DSPI_E_SOUTE        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FEC_FEC_TXD2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FEC_FEC_RXER_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_DSPI_A_PCSA3        (PORT_ALT1_FUNC_MODE)
#define    PORT99_DSPI_E_SINE        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FEC_FEC_MDIO        (PORT_ALT3_FUNC_MODE)
#define    PORT99_eSCI_D_TXDD        (PORT_ALT4_FUNC_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_DSPI_A_PCSA4        (PORT_ALT1_FUNC_MODE)
#define    PORT100_DSPI_E_SCKE_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_DSPI_E_SCKE_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT100_DSPI_E_SCKE_INOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_eSCI_E_TXDE        (PORT_INPUT3_MODE)
#define    PORT100_FEC_FEC_RXCLK_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_DSPI_A_PCSA5        (PORT_ALT1_FUNC_MODE)
#define    PORT101_eQADC_A_eQADC_B_ETRIG1        (PORT_ALT2_FUNC_MODE)
#define    PORT101_eSCI_D_RXDD        (PORT_ALT3_FUNC_MODE)
#define    PORT101_FEC_FEC_TXD3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_DSPI_B_SCKB_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_DSPI_B_SCKB_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_DSPI_B_SCKB_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_DSPI_B_SINB        (PORT_ALT1_FUNC_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_DSPI_B_SOUTB        (PORT_ALT1_FUNC_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_DSPI_B_PCSB0_INOUT        (PORT_INPUT1_MODE)
#define    PORT105_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT105_DSPI_B_PCSB0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT105_DSPI_B_PCSB0_IN        (PORT_INPUT1_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_DSPI_B_PCSB1        (PORT_ALT1_FUNC_MODE)
#define    PORT106_DSPI_D_PCSD0_INOUT        (PORT_INPUT2_MODE)
#define    PORT106_DSPI_D_PCSD0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT106_DSPI_D_PCSD0_IN        (PORT_INPUT2_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_DSPI_B_PCSB2        (PORT_ALT1_FUNC_MODE)
#define    PORT107_DSPI_C_SOUTC        (PORT_ALT2_FUNC_MODE)
#define    PORT107_SENT_B_SENT2_B_IN        (PORT_INPUT3_MODE)
#define    PORT107_FEC_FEC_RXD3_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_DSPI_B_PCSB3        (PORT_ALT1_FUNC_MODE)
#define    PORT108_DSPI_C_SINC        (PORT_INPUT2_MODE)
#define    PORT108_SENT_B_SENT3_B_IN        (PORT_INPUT3_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_DSPI_B_PCSB4        (PORT_ALT1_FUNC_MODE)
#define    PORT109_DSPI_C_SCKC_INOUT        (PORT_INPUT2_MODE)
#define    PORT109_SENT_B_SENT4_B_IN        (PORT_INPUT3_MODE)
#define    PORT109_FEC_FEC_MDC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT109_DSPI_C_SCKC_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT109_DSPI_C_SCKC_IN        (PORT_INPUT2_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_DSPI_B_PCSB5        (PORT_ALT1_FUNC_MODE)
#define    PORT110_DSPI_C_PCSC0_INOUT        (PORT_INPUT2_MODE)
#define    PORT110_SENT_B_SENT5_B_IN        (PORT_INPUT3_MODE)
#define    PORT110_FEC_FEC_RXD2_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT110_DSPI_C_PCSC0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT110_DSPI_C_PCSC0_IN        (PORT_INPUT2_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_eTPU_A_TCRCLKA        (PORT_ALT1_FUNC_MODE)
#define    PORT113_SIU_A_IRQ7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_eTPU_A_ETPUA0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_eTPU_A_ETPUA12        (PORT_ALT2_FUNC_MODE)
#define    PORT114_eTPU_A_ETPUA0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_eTPU_A_ETPUA0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_eTPU_A_ETPUA1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_eTPU_A_ETPUA13        (PORT_ALT2_FUNC_MODE)
#define    PORT115_eTPU_A_ETPUA1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_eTPU_A_ETPUA1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_eTPU_A_ETPUA2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_eTPU_A_ETPUA14        (PORT_ALT2_FUNC_MODE)
#define    PORT116_REACM_RCH0_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT116_eTPU_A_ETPUA2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_eTPU_A_ETPUA2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_eTPU_A_ETPUA3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_eTPU_A_ETPUA15        (PORT_ALT2_FUNC_MODE)
#define    PORT117_REACM_RCH1_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT117_FCCU_ERROR0        (PORT_ALT4_FUNC_MODE)
#define    PORT117_eTPU_A_ETPUA3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_eTPU_A_ETPUA3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_eTPU_A_ETPUA4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_eTPU_A_ETPUA16        (PORT_ALT2_FUNC_MODE)
#define    PORT118_REACM_RCH2_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT118_eTPU_A_ETPUA4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_eTPU_A_ETPUA4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_eTPU_A_ETPUA5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_eTPU_A_ETPUA17        (PORT_ALT2_FUNC_MODE)
#define    PORT119_REACM_RCH3_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT119_eTPU_A_ETPUA5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_eTPU_A_ETPUA5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_eTPU_A_ETPUA6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_eTPU_A_ETPUA18        (PORT_ALT2_FUNC_MODE)
#define    PORT120_REACM_RCH4_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT120_eTPU_A_ETPUA6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_eTPU_A_ETPUA6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_eTPU_A_ETPUA7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT121_eTPU_A_ETPUA19        (PORT_ALT2_FUNC_MODE)
#define    PORT121_REACM_RCH5_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT121_eTPU_A_ETPUA7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT121_eTPU_A_ETPUA7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_eTPU_A_ETPUA8_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_eTPU_A_ETPUA20        (PORT_ALT2_FUNC_MODE)
#define    PORT122_REACM_RCH6_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT122_eTPU_A_ETPUA8_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_eTPU_A_ETPUA8_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_eTPU_A_ETPUA9_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_eTPU_A_ETPUA21        (PORT_ALT2_FUNC_MODE)
#define    PORT123_REACM_RCH7_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT123_eTPU_A_ETPUA9_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_eTPU_A_ETPUA9_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_eTPU_A_ETPUA10_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_eTPU_A_ETPUA22        (PORT_ALT2_FUNC_MODE)
#define    PORT124_REACM_RCH8_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT124_FCCU_ERRORIN        (PORT_ALT4_FUNC_MODE)
#define    PORT124_eTPU_A_ETPUA10_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_eTPU_A_ETPUA10_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_eTPU_A_ETPUA11_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT125_eTPU_A_ETPUA23        (PORT_ALT2_FUNC_MODE)
#define    PORT125_REACM_RCH9_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT125_FCCU_ERROR1        (PORT_ALT4_FUNC_MODE)
#define    PORT125_eTPU_A_ETPUA11_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT125_eTPU_A_ETPUA11_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_eTPU_A_ETPUA12_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_DSPI_B_PCSB1        (PORT_ALT2_FUNC_MODE)
#define    PORT126_eTPU_A_ETPUA12_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_eTPU_A_ETPUA12_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_eTPU_A_ETPUA13_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT127_DSPI_B_PCSB3        (PORT_ALT2_FUNC_MODE)
#define    PORT127_eTPU_A_ETPUA13_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT127_eTPU_A_ETPUA13_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_eTPU_A_ETPUA14_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_DSPI_B_PCSB4        (PORT_ALT2_FUNC_MODE)
#define    PORT128_eTPU_A_ETPUA14_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_eTPU_A_ETPUA14_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_eTPU_A_ETPUA15_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_DSPI_B_PCSB5        (PORT_ALT2_FUNC_MODE)
#define    PORT129_MCAN_0_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT129_eTPU_A_ETPUA15_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_eTPU_A_ETPUA15_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_eTPU_A_ETPUA16_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_DSPI_D_PCSD1        (PORT_ALT2_FUNC_MODE)
#define    PORT130_eTPU_A_ETPUA16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_eTPU_A_ETPUA16_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_eTPU_A_ETPUA17_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT131_eTPU_A_ETPUA17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_eTPU_A_ETPUA17_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_eTPU_A_ETPUA18_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_DSPI_D_PCSD3        (PORT_ALT2_FUNC_MODE)
#define    PORT132_eTPU_A_ETPUA18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_eTPU_A_ETPUA18_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_eTPU_A_ETPUA19_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_DSPI_D_PCSD4        (PORT_ALT2_FUNC_MODE)
#define    PORT133_MCAN_0_RX_IN        (PORT_INPUT3_MODE)
#define    PORT133_eTPU_A_ETPUA19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_eTPU_A_ETPUA19_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_eTPU_A_ETPUA20_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_SIU_A_IRQ8        (PORT_ALT2_FUNC_MODE)
#define    PORT134_eTPU_A_ETPUA20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_eTPU_A_ETPUA20_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_eTPU_A_ETPUA21_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_SIU_A_IRQ9        (PORT_ALT2_FUNC_MODE)
#define    PORT135_eTPU_A_ETPUA21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_eTPU_A_ETPUA21_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_eTPU_A_ETPUA22_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT136_SIU_A_IRQ10        (PORT_ALT2_FUNC_MODE)
#define    PORT136_REACM_RCH0_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT136_eTPU_A_ETPUA22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT136_eTPU_A_ETPUA22_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_eTPU_A_ETPUA23_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT137_SIU_A_IRQ11        (PORT_ALT2_FUNC_MODE)
#define    PORT137_REACM_RCH1_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT137_eTPU_A_ETPUA23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT137_eTPU_A_ETPUA23_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_eTPU_A_ETPUA24_INOUT        (PORT_INPUT1_MODE)
#define    PORT138_SIU_A_IRQ12        (PORT_ALT2_FUNC_MODE)
#define    PORT138_REACM_RCH2_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT138_eTPU_A_ETPUA24_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT138_eTPU_A_ETPUA24_IN        (PORT_INPUT1_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_eTPU_A_ETPUA25_INOUT        (PORT_INPUT1_MODE)
#define    PORT139_SIU_A_IRQ13        (PORT_ALT2_FUNC_MODE)
#define    PORT139_REACM_RCH3_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT139_eTPU_A_ETPUA25_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT139_eTPU_A_ETPUA25_IN        (PORT_INPUT1_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_eTPU_A_ETPUA26_INOUT        (PORT_INPUT1_MODE)
#define    PORT140_SIU_A_IRQ14        (PORT_ALT2_FUNC_MODE)
#define    PORT140_REACM_RCH4_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT140_eTPU_A_ETPUA26_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT140_eTPU_A_ETPUA26_IN        (PORT_INPUT1_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_eTPU_A_ETPUA27_INOUT        (PORT_INPUT1_MODE)
#define    PORT141_SIU_A_IRQ15        (PORT_ALT2_FUNC_MODE)
#define    PORT141_REACM_RCH5_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT141_eTPU_A_ETPUA27_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT141_eTPU_A_ETPUA27_IN        (PORT_INPUT1_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_eTPU_A_ETPUA28_INOUT        (PORT_INPUT1_MODE)
#define    PORT142_DSPI_C_PCSC1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_REACM_RCH6_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT142_eTPU_A_ETPUA28_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT142_eTPU_A_ETPUA28_IN        (PORT_INPUT1_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_eTPU_A_ETPUA29_INOUT        (PORT_INPUT1_MODE)
#define    PORT143_DSPI_C_PCSC2        (PORT_ALT2_FUNC_MODE)
#define    PORT143_REACM_RCH7_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT143_eTPU_A_ETPUA29_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT143_eTPU_A_ETPUA29_IN        (PORT_INPUT1_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_eTPU_A_ETPUA30_INOUT        (PORT_INPUT1_MODE)
#define    PORT144_DSPI_C_PCSC3        (PORT_ALT2_FUNC_MODE)
#define    PORT144_REACM_RCH8_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT144_eTPU_A_ETPUA30_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT144_eTPU_A_ETPUA30_IN        (PORT_INPUT1_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_eTPU_A_ETPUA31_INOUT        (PORT_INPUT1_MODE)
#define    PORT145_DSPI_C_PCSC4        (PORT_ALT2_FUNC_MODE)
#define    PORT145_REACM_RCH9_A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT145_eTPU_A_ETPUA31_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT145_eTPU_A_ETPUA31_IN        (PORT_INPUT1_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_eTPU_B_TCRCLKB        (PORT_ALT1_FUNC_MODE)
#define    PORT146_SIU_A_IRQ6        (PORT_INPUT2_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_eTPU_B_ETPUB0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT147_eTPU_B_ETPUB16        (PORT_ALT2_FUNC_MODE)
#define    PORT147_eTPU_B_ETPUB0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT147_eTPU_B_ETPUB0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_eTPU_B_ETPUB1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_eTPU_B_ETPUB17        (PORT_ALT2_FUNC_MODE)
#define    PORT148_eTPU_B_ETPUB1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_eTPU_B_ETPUB1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_eTPU_B_ETPUB2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT149_eTPU_B_ETPUB18        (PORT_ALT2_FUNC_MODE)
#define    PORT149_eTPU_B_ETPUB2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT149_eTPU_B_ETPUB2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_eTPU_B_ETPUB3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT150_eTPU_B_ETPUB19        (PORT_ALT2_FUNC_MODE)
#define    PORT150_eTPU_B_ETPUB3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT150_eTPU_B_ETPUB3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_eTPU_B_ETPUB4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT151_eTPU_B_ETPUB20        (PORT_ALT2_FUNC_MODE)
#define    PORT151_eTPU_B_ETPUB4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT151_eTPU_B_ETPUB4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_eTPU_B_ETPUB5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT152_eTPU_B_ETPUB21        (PORT_ALT2_FUNC_MODE)
#define    PORT152_eTPU_B_ETPUB5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT152_eTPU_B_ETPUB5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_eTPU_B_ETPUB6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT153_eTPU_B_ETPUB22        (PORT_ALT2_FUNC_MODE)
#define    PORT153_eTPU_B_ETPUB6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT153_eTPU_B_ETPUB6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_eTPU_B_ETPUB7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT154_eTPU_B_ETPUB23        (PORT_ALT2_FUNC_MODE)
#define    PORT154_eTPU_B_ETPUB7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT154_eTPU_B_ETPUB7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_eTPU_B_ETPUB8_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT155_eTPU_B_ETPUB24        (PORT_ALT2_FUNC_MODE)
#define    PORT155_eTPU_B_ETPUB8_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT155_eTPU_B_ETPUB8_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT156_GPIO        (PORT_GPIO_MODE)
#define    PORT156_eTPU_B_ETPUB9_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT156_eTPU_B_ETPUB25        (PORT_ALT2_FUNC_MODE)
#define    PORT156_eTPU_B_ETPUB9_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT156_eTPU_B_ETPUB9_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT157_GPIO        (PORT_GPIO_MODE)
#define    PORT157_eTPU_B_ETPUB10_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT157_eTPU_B_ETPUB26        (PORT_ALT2_FUNC_MODE)
#define    PORT157_eTPU_B_ETPUB10_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT157_eTPU_B_ETPUB10_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT158_GPIO        (PORT_GPIO_MODE)
#define    PORT158_eTPU_B_ETPUB11_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT158_eTPU_B_ETPUB27        (PORT_ALT2_FUNC_MODE)
#define    PORT158_eTPU_B_ETPUB11_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT158_eTPU_B_ETPUB11_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT159_GPIO        (PORT_GPIO_MODE)
#define    PORT159_eTPU_B_ETPUB12_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT159_eTPU_B_ETPUB28        (PORT_ALT2_FUNC_MODE)
#define    PORT159_eTPU_B_ETPUB12_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT159_eTPU_B_ETPUB12_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT160_GPIO        (PORT_GPIO_MODE)
#define    PORT160_eTPU_B_ETPUB13_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT160_eTPU_B_ETPUB29        (PORT_ALT2_FUNC_MODE)
#define    PORT160_eTPU_B_ETPUB13_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT160_eTPU_B_ETPUB13_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT161_GPIO        (PORT_GPIO_MODE)
#define    PORT161_eTPU_B_ETPUB14_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT161_eTPU_B_ETPUB30        (PORT_ALT2_FUNC_MODE)
#define    PORT161_eTPU_B_ETPUB14_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT161_eTPU_B_ETPUB14_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT162_GPIO        (PORT_GPIO_MODE)
#define    PORT162_eTPU_B_ETPUB15_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT162_eTPU_B_ETPUB31        (PORT_ALT2_FUNC_MODE)
#define    PORT162_eTPU_B_ETPUB15_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT162_eTPU_B_ETPUB15_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT163_GPIO        (PORT_GPIO_MODE)
#define    PORT163_eTPU_B_ETPUB16_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT163_DSPI_A_PCSA1        (PORT_ALT2_FUNC_MODE)
#define    PORT163_eTPU_B_ETPUB16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT163_eTPU_B_ETPUB16_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT164_GPIO        (PORT_GPIO_MODE)
#define    PORT164_eTPU_B_ETPUB17_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT164_DSPI_A_PCSA2        (PORT_ALT2_FUNC_MODE)
#define    PORT164_eTPU_B_ETPUB17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT164_eTPU_B_ETPUB17_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT165_GPIO        (PORT_GPIO_MODE)
#define    PORT165_eTPU_B_ETPUB18_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT165_DSPI_A_PCSA3        (PORT_ALT2_FUNC_MODE)
#define    PORT165_eTPU_B_ETPUB18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT165_eTPU_B_ETPUB18_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT166_GPIO        (PORT_GPIO_MODE)
#define    PORT166_eTPU_B_ETPUB19_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT166_DSPI_A_PCSA4        (PORT_ALT2_FUNC_MODE)
#define    PORT166_eTPU_B_ETPUB19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT166_eTPU_B_ETPUB19_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT167_GPIO        (PORT_GPIO_MODE)
#define    PORT167_eTPU_B_ETPUB20_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT167_eTPU_B_ETPUB20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT167_eTPU_B_ETPUB20_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT168_GPIO        (PORT_GPIO_MODE)
#define    PORT168_eTPU_B_ETPUB21_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT168_eTPU_B_ETPUB21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT168_eTPU_B_ETPUB21_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT169_GPIO        (PORT_GPIO_MODE)
#define    PORT169_eTPU_B_ETPUB22_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT169_REACM_RCH0_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT169_eTPU_B_ETPUB22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT169_eTPU_B_ETPUB22_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT170_GPIO        (PORT_GPIO_MODE)
#define    PORT170_eTPU_B_ETPUB23_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT170_REACM_RCH1_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT170_eTPU_B_ETPUB23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT170_eTPU_B_ETPUB23_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT171_GPIO        (PORT_GPIO_MODE)
#define    PORT171_eTPU_B_ETPUB24_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT171_REACM_RCH2_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT171_eTPU_B_ETPUB24_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT171_eTPU_B_ETPUB24_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT172_GPIO        (PORT_GPIO_MODE)
#define    PORT172_eTPU_B_ETPUB25_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT172_REACM_RCH3_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT172_eTPU_B_ETPUB25_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT172_eTPU_B_ETPUB25_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT173_GPIO        (PORT_GPIO_MODE)
#define    PORT173_eTPU_B_ETPUB26_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT173_REACM_RCH4_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT173_eTPU_B_ETPUB26_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT173_eTPU_B_ETPUB26_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT174_GPIO        (PORT_GPIO_MODE)
#define    PORT174_eTPU_B_ETPUB27_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT174_REACM_RCH5_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT174_eTPU_B_ETPUB27_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT174_eTPU_B_ETPUB27_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT175_GPIO        (PORT_GPIO_MODE)
#define    PORT175_eTPU_B_ETPUB28_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT175_REACM_RCH6_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT175_eTPU_B_ETPUB28_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT175_eTPU_B_ETPUB28_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT176_GPIO        (PORT_GPIO_MODE)
#define    PORT176_eTPU_B_ETPUB29_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT176_REACM_RCH7_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT176_eTPU_B_ETPUB29_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT176_eTPU_B_ETPUB29_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT177_GPIO        (PORT_GPIO_MODE)
#define    PORT177_eTPU_B_ETPUB30_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT177_REACM_RCH8_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT177_eTPU_B_ETPUB30_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT177_eTPU_B_ETPUB30_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT178_GPIO        (PORT_GPIO_MODE)
#define    PORT178_eTPU_B_ETPUB31_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT178_REACM_RCH9_B_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT178_eTPU_B_ETPUB31_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT178_eTPU_B_ETPUB31_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT179_GPIO        (PORT_GPIO_MODE)
#define    PORT179_eMIOS_A_EMIOS0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT179_eTPU_A_ETPUA0        (PORT_ALT2_FUNC_MODE)
#define    PORT179_REACM_RCH0_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT179_eMIOS_A_EMIOS0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT179_eMIOS_A_EMIOS0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT180_GPIO        (PORT_GPIO_MODE)
#define    PORT180_eMIOS_A_EMIOS1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT180_eTPU_A_ETPUA1        (PORT_ALT2_FUNC_MODE)
#define    PORT180_REACM_RCH1_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT180_DSPI_E_PCSE2        (PORT_ALT4_FUNC_MODE)
#define    PORT180_eMIOS_A_EMIOS1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT180_eMIOS_A_EMIOS1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT181_GPIO        (PORT_GPIO_MODE)
#define    PORT181_eMIOS_A_EMIOS2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT181_eTPU_A_ETPUA2        (PORT_ALT2_FUNC_MODE)
#define    PORT181_REACM_RCH2_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT181_DSPI_E_PCSE3        (PORT_ALT4_FUNC_MODE)
#define    PORT181_eMIOS_A_EMIOS2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT181_eMIOS_A_EMIOS2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT182_GPIO        (PORT_GPIO_MODE)
#define    PORT182_eMIOS_A_EMIOS3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT182_eTPU_A_ETPUA3        (PORT_ALT2_FUNC_MODE)
#define    PORT182_REACM_RCH3_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT182_DSPI_E_PCSE4        (PORT_ALT4_FUNC_MODE)
#define    PORT182_eMIOS_A_EMIOS3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT182_eMIOS_A_EMIOS3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT183_GPIO        (PORT_GPIO_MODE)
#define    PORT183_eMIOS_A_EMIOS4        (PORT_ALT1_FUNC_MODE)
#define    PORT183_eTPU_A_ETPUA4        (PORT_ALT2_FUNC_MODE)
#define    PORT183_REACM_RCH4_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT183_DSPI_E_PCSE5        (PORT_ALT4_FUNC_MODE)
#define    PORT184_GPIO        (PORT_GPIO_MODE)
#define    PORT184_eMIOS_A_EMIOS5        (PORT_ALT1_FUNC_MODE)
#define    PORT184_eTPU_A_ETPUA5        (PORT_ALT2_FUNC_MODE)
#define    PORT184_REACM_RCH5_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT185_GPIO        (PORT_GPIO_MODE)
#define    PORT185_eMIOS_A_EMIOS6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT185_eTPU_A_ETPUA6        (PORT_ALT2_FUNC_MODE)
#define    PORT185_REACM_RCH6_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT185_eMIOS_A_EMIOS6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT185_eMIOS_A_EMIOS6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT186_GPIO        (PORT_GPIO_MODE)
#define    PORT186_eMIOS_A_EMIOS7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT186_eTPU_A_ETPUA7        (PORT_ALT2_FUNC_MODE)
#define    PORT186_REACM_RCH7_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT186_eMIOS_A_EMIOS7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT186_eMIOS_A_EMIOS7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT187_GPIO        (PORT_GPIO_MODE)
#define    PORT187_eMIOS_B_EMIOS0_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT187_eTPU_A_ETPUA8        (PORT_ALT2_FUNC_MODE)
#define    PORT187_REACM_RCH8_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT187_eMIOS_B_EMIOS0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT187_eMIOS_B_EMIOS0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT188_GPIO        (PORT_GPIO_MODE)
#define    PORT188_eMIOS_B_EMIOS1_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT188_eTPU_A_ETPUA9        (PORT_ALT2_FUNC_MODE)
#define    PORT188_REACM_RCH9_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT188_eMIOS_B_EMIOS1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT188_eMIOS_B_EMIOS1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT189_GPIO        (PORT_GPIO_MODE)
#define    PORT189_eMIOS_B_EMIOS2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT189_DSPI_D_SCKD_INOUT        (PORT_INPUT2_MODE)
#define    PORT189_eMIOS_B_EMIOS2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT189_DSPI_D_SCKD_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT189_eMIOS_B_EMIOS2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT189_DSPI_D_SCKD_IN        (PORT_INPUT2_MODE)
#define    PORT190_GPIO        (PORT_GPIO_MODE)
#define    PORT190_eMIOS_B_EMIOS3_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT190_DSPI_D_SIND        (PORT_INPUT2_MODE)
#define    PORT190_eMIOS_B_EMIOS3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT190_eMIOS_B_EMIOS3_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT191_GPIO        (PORT_GPIO_MODE)
#define    PORT191_eMIOS_B_EMIOS4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT191_DSPI_C_SOUTC        (PORT_ALT2_FUNC_MODE)
#define    PORT191_eMIOS_B_EMIOS4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT191_eMIOS_B_EMIOS4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT192_GPIO        (PORT_GPIO_MODE)
#define    PORT192_eMIOS_B_EMIOS5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT192_DSPI_D_SOUTD        (PORT_ALT2_FUNC_MODE)
#define    PORT192_eMIOS_B_EMIOS5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT192_eMIOS_B_EMIOS5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT193_GPIO        (PORT_GPIO_MODE)
#define    PORT193_eMIOS_B_EMIOS6        (PORT_ALT1_FUNC_MODE)
#define    PORT193_SIU_A_IRQ0        (PORT_INPUT2_MODE)
#define    PORT193_FlexCAN_D_CNTXD        (PORT_ALT3_FUNC_MODE)
#define    PORT193_REACM_RCH0_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT194_GPIO        (PORT_GPIO_MODE)
#define    PORT194_eMIOS_B_EMIOS7        (PORT_ALT1_FUNC_MODE)
#define    PORT194_SIU_A_IRQ1_IN        (PORT_INPUT2_MODE)
#define    PORT194_FlexCAN_D_CNRXD_IN        (PORT_INPUT3_MODE)
#define    PORT194_REACM_RCH1_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT195_GPIO        (PORT_GPIO_MODE)
#define    PORT195_eMIOS_A_EMIOS16_INOUT        (PORT_INPUT1_MODE)
#define    PORT195_eTPU_B_ETPUB0        (PORT_ALT2_FUNC_MODE)
#define    PORT195_MCAN_1_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT195_REACM_RCH2_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT195_eMIOS_A_EMIOS16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT195_eMIOS_A_EMIOS16_IN        (PORT_INPUT1_MODE)
#define    PORT196_GPIO        (PORT_GPIO_MODE)
#define    PORT196_eMIOS_A_EMIOS17_INOUT        (PORT_INPUT1_MODE)
#define    PORT196_eTPU_B_ETPUB1        (PORT_ALT2_FUNC_MODE)
#define    PORT196_MCAN_1_RX_IN        (PORT_INPUT3_MODE)
#define    PORT196_REACM_RCH3_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT196_eMIOS_A_EMIOS17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT196_eMIOS_A_EMIOS17_IN        (PORT_INPUT1_MODE)
#define    PORT197_GPIO        (PORT_GPIO_MODE)
#define    PORT197_eMIOS_A_EMIOS18_INOUT        (PORT_INPUT1_MODE)
#define    PORT197_eTPU_B_ETPUB2        (PORT_ALT2_FUNC_MODE)
#define    PORT197_REACM_RCH4_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT197_eMIOS_A_EMIOS18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT197_eMIOS_A_EMIOS18_IN        (PORT_INPUT1_MODE)
#define    PORT198_GPIO        (PORT_GPIO_MODE)
#define    PORT198_eMIOS_A_EMIOS19_INOUT        (PORT_INPUT1_MODE)
#define    PORT198_eTPU_B_ETPUB3        (PORT_ALT2_FUNC_MODE)
#define    PORT198_REACM_RCH5_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT198_eMIOS_A_EMIOS19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT198_eMIOS_A_EMIOS19_IN        (PORT_INPUT1_MODE)
#define    PORT199_GPIO        (PORT_GPIO_MODE)
#define    PORT199_eMIOS_A_EMIOS20_INOUT        (PORT_INPUT1_MODE)
#define    PORT199_eTPU_B_ETPUB4        (PORT_ALT2_FUNC_MODE)
#define    PORT199_REACM_RCH6_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT199_eMIOS_A_EMIOS20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT199_eMIOS_A_EMIOS20_IN        (PORT_INPUT1_MODE)
#define    PORT200_GPIO        (PORT_GPIO_MODE)
#define    PORT200_eMIOS_A_EMIOS21_INOUT        (PORT_INPUT1_MODE)
#define    PORT200_eTPU_B_ETPUB5        (PORT_ALT2_FUNC_MODE)
#define    PORT200_REACM_RCH7_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT200_eMIOS_A_EMIOS21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT200_eMIOS_A_EMIOS21_IN        (PORT_INPUT1_MODE)
#define    PORT201_GPIO        (PORT_GPIO_MODE)
#define    PORT201_eMIOS_A_EMIOS22_INOUT        (PORT_INPUT1_MODE)
#define    PORT201_eTPU_B_ETPUB6        (PORT_ALT2_FUNC_MODE)
#define    PORT201_REACM_RCH8_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT201_eMIOS_A_EMIOS22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT201_eMIOS_A_EMIOS22_IN        (PORT_INPUT1_MODE)
#define    PORT202_GPIO        (PORT_GPIO_MODE)
#define    PORT202_eMIOS_A_EMIOS23_INOUT        (PORT_INPUT1_MODE)
#define    PORT202_eTPU_B_ETPUB7        (PORT_ALT2_FUNC_MODE)
#define    PORT202_REACM_RCH9_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT202_eMIOS_A_EMIOS23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT202_eMIOS_A_EMIOS23_IN        (PORT_INPUT1_MODE)
#define    PORT203_GPIO        (PORT_GPIO_MODE)
#define    PORT203_eMIOS_B_EMIOS16_INOUT        (PORT_INPUT1_MODE)
#define    PORT203_DSPI_B_PCSB0_INOUT        (PORT_INPUT2_MODE)
#define    PORT203_eMIOS_B_EMIOS16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT203_DSPI_B_PCSB0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT203_eMIOS_B_EMIOS16_IN        (PORT_INPUT1_MODE)
#define    PORT203_DSPI_B_PCSB0_IN        (PORT_INPUT2_MODE)
#define    PORT204_GPIO        (PORT_GPIO_MODE)
#define    PORT204_eMIOS_B_EMIOS17_INOUT        (PORT_INPUT1_MODE)
#define    PORT204_DSPI_B_PCSB1        (PORT_ALT2_FUNC_MODE)
#define    PORT204_eMIOS_B_EMIOS17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT204_eMIOS_B_EMIOS17_IN        (PORT_INPUT1_MODE)
#define    PORT208_GPIO        (PORT_GPIO_MODE)
#define    PORT208_SoC_PLLCFG0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT208_SIU_A_IRQ4_IN        (PORT_INPUT2_MODE)
#define    PORT208_eTPU_C_ETPUC9_INOUT        (PORT_INPUT3_MODE)
#define    PORT208_SIPI_TXN        (PORT_ALT4_FUNC_MODE)
#define    PORT208_eTPU_C_ETPUC9_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT208_eTPU_C_ETPUC9_IN        (PORT_INPUT3_MODE)
#define    PORT209_GPIO        (PORT_GPIO_MODE)
#define    PORT209_SoC_PLLCFG1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT209_SIU_A_IRQ5_IN        (PORT_INPUT2_MODE)
#define    PORT209_DSPI_D_SOUTD        (PORT_ALT3_FUNC_MODE)
#define    PORT209_SIPI_TXP        (PORT_ALT4_FUNC_MODE)
#define    PORT210_GPIO        (PORT_GPIO_MODE)
#define    PORT210_SoC_PLLCFG2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT210_eTPU_C_ETPUC3_INOUT        (PORT_INPUT2_MODE)
#define    PORT210_DSPI_E_PCSE1        (PORT_ALT3_FUNC_MODE)
#define    PORT210_SIPI_REFCLK_INOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT210_eTPU_C_ETPUC3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT210_SIPI_REFCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT210_eTPU_C_ETPUC3_IN        (PORT_INPUT2_MODE)
#define    PORT210_SIPI_REFCLK_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT211_GPIO        (PORT_GPIO_MODE)
#define    PORT211_SoC_BOOTCFG0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT211_SIU_A_IRQ2_IN        (PORT_INPUT2_MODE)
#define    PORT212_GPIO        (PORT_GPIO_MODE)
#define    PORT212_SoC_BOOTCFG1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT212_SIU_A_IRQ3_IN        (PORT_INPUT2_MODE)
#define    PORT212_eTPU_C_ETPUC0_INOUT        (PORT_INPUT3_MODE)
#define    PORT212_SIPI_RXP        (PORT_ALT4_FUNC_MODE)
#define    PORT212_eTPU_C_ETPUC0_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT212_eTPU_C_ETPUC0_IN        (PORT_INPUT3_MODE)
#define    PORT213_GPIO        (PORT_GPIO_MODE)
#define    PORT213_SoC_WKPCFG_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT213_SIU_A_NMI_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT213_eTPU_C_ETPUC1_INOUT        (PORT_INPUT3_MODE)
#define    PORT213_SIPI_RXN        (PORT_ALT4_FUNC_MODE)
#define    PORT213_eTPU_C_ETPUC1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT213_eTPU_C_ETPUC1_IN        (PORT_INPUT3_MODE)
#define    PORT214_GPIO        (PORT_GPIO_MODE)
#define    PORT214_ENGCLK        (PORT_ALT1_FUNC_MODE)
#define    PORT219_GPIO        (PORT_GPIO_MODE)
#define    PORT219_MCKO        (PORT_ALT1_FUNC_MODE)
#define    PORT220_GPIO        (PORT_GPIO_MODE)
#define    PORT221_GPIO        (PORT_GPIO_MODE)
#define    PORT222_GPIO        (PORT_GPIO_MODE)
#define    PORT223_GPIO        (PORT_GPIO_MODE)
#define    PORT223_eSCI_E_TXDE        (PORT_INPUT2_MODE)
#define    PORT224_GPIO        (PORT_GPIO_MODE)
#define    PORT224_MSEO0        (PORT_ALT1_FUNC_MODE)
#define    PORT225_GPIO        (PORT_GPIO_MODE)
#define    PORT225_MSEO1        (PORT_ALT1_FUNC_MODE)
#define    PORT226_GPIO        (PORT_GPIO_MODE)
#define    PORT226_RDY        (PORT_ALT1_FUNC_MODE)
#define    PORT227_GPIO        (PORT_GPIO_MODE)
#define    PORT227_EVTO        (PORT_ALT1_FUNC_MODE)
#define    PORT228_GPIO        (PORT_GPIO_MODE)
#define    PORT228_TDO        (PORT_ALT1_FUNC_MODE)
#define    PORT229_GPIO        (PORT_GPIO_MODE)
#define    PORT229_D_CLKOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT230_GPIO        (PORT_GPIO_MODE)
#define    PORT230_RSTOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT231_GPIO        (PORT_GPIO_MODE)
#define    PORT232_GPIO        (PORT_GPIO_MODE)
#define    PORT233_GPIO        (PORT_GPIO_MODE)
#define    PORT234_GPIO        (PORT_GPIO_MODE)
#define    PORT235_GPIO        (PORT_GPIO_MODE)
#define    PORT235_DSPI_C_SCKC_INOUT        (PORT_INPUT1_MODE)
#define    PORT235_DSPI_C_SCK_C_LVDS_P        (PORT_ALT2_FUNC_MODE)
#define    PORT235_DSPI_C_SCKC_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT235_DSPI_C_SCKC_IN        (PORT_INPUT1_MODE)
#define    PORT236_GPIO        (PORT_GPIO_MODE)
#define    PORT236_DSPI_C_SINC_IN        (PORT_INPUT1_MODE)
#define    PORT236_DSPI_C_SCK_C_LVDS_N_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT237_GPIO        (PORT_GPIO_MODE)
#define    PORT237_DSPI_C_SOUTC        (PORT_ALT1_FUNC_MODE)
#define    PORT237_DSPI_C_SOUT_C_LVDS_P        (PORT_ALT2_FUNC_MODE)
#define    PORT238_GPIO        (PORT_GPIO_MODE)
#define    PORT238_DSPI_C_PCSC0_INOUT        (PORT_INPUT1_MODE)
#define    PORT238_DSPI_C_SOUT_C_LVDS_N_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT238_DSPI_C_PCSC0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT238_DSPI_C_PCSC0_IN        (PORT_INPUT1_MODE)
#define    PORT239_GPIO        (PORT_GPIO_MODE)
#define    PORT239_DSPI_C_PCSC1        (PORT_ALT1_FUNC_MODE)
#define    PORT239_eSCI_D_TXDD        (PORT_ALT2_FUNC_MODE)
#define    PORT240_GPIO        (PORT_GPIO_MODE)
#define    PORT240_DSPI_C_PCSC2        (PORT_ALT1_FUNC_MODE)
#define    PORT240_DSPI_D_SCK_D_LVDS_P        (PORT_ALT2_FUNC_MODE)
#define    PORT240_DSPI_D_SCKD_INOUT        (PORT_INPUT3_MODE)
#define    PORT240_DSPI_D_SCKD_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT240_DSPI_D_SCKD_IN        (PORT_INPUT3_MODE)
#define    PORT241_GPIO        (PORT_GPIO_MODE)
#define    PORT241_DSPI_C_PCSC3        (PORT_ALT1_FUNC_MODE)
#define    PORT241_DSPI_D_SCK_D_LVDS_N_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT241_DSPI_D_SIND_IN        (PORT_INPUT3_MODE)
#define    PORT242_GPIO        (PORT_GPIO_MODE)
#define    PORT242_DSPI_C_PCSC4        (PORT_ALT1_FUNC_MODE)
#define    PORT242_MCAN_0_TX_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT242_DSPI_D_SOUT_D_LVDS_P        (PORT_ALT3_FUNC_MODE)
#define    PORT242_DSPI_D_SOUTD        (PORT_ALT4_FUNC_MODE)
#define    PORT243_GPIO        (PORT_GPIO_MODE)
#define    PORT243_DSPI_C_PCSC5        (PORT_ALT1_FUNC_MODE)
#define    PORT243_MCAN_0_RX_IN        (PORT_INPUT2_MODE)
#define    PORT243_DSPI_D_SOUT_D_LVDS_N_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT243_DSPI_D_PCSD0_INOUT        (PORT_INPUT4_MODE)
#define    PORT243_DSPI_D_PCSD0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT243_DSPI_D_PCSD0_IN        (PORT_INPUT4_MODE)
#define    PORT244_GPIO        (PORT_GPIO_MODE)
#define    PORT244_eSCI_C_TXDC        (PORT_ALT1_FUNC_MODE)
#define    PORT244_eQADC_A_eQADC_B_ETRIG0_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT245_GPIO        (PORT_GPIO_MODE)
#define    PORT245_eSCI_C_RXDC_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT246_GPIO        (PORT_GPIO_MODE)
#define    PORT246_FlexCAN_D_CNTXD        (PORT_ALT1_FUNC_MODE)
#define    PORT246_MCAN_1_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT247_GPIO        (PORT_GPIO_MODE)
#define    PORT247_FlexCAN_D_CNRXD_IN        (PORT_INPUT1_MODE)
#define    PORT247_MCAN_1_RX_IN        (PORT_INPUT3_MODE)
#define    PORT248_GPIO        (PORT_GPIO_MODE)
#define    PORT248_FEC_FEC_TXD0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT248_SENT_A_SENT0_A_IN        (PORT_INPUT2_MODE)
#define    PORT249_GPIO        (PORT_GPIO_MODE)
#define    PORT249_FEC_FEC_RX_DV_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT249_SENT_A_SENT1_A_IN        (PORT_INPUT2_MODE)
#define    PORT250_GPIO        (PORT_GPIO_MODE)
#define    PORT250_FEC_FEC_RXD0_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT250_SENT_A_SENT2_A_IN        (PORT_INPUT2_MODE)
#define    PORT251_GPIO        (PORT_GPIO_MODE)
#define    PORT251_FEC_FEC_TXD1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT251_SENT_A_SENT3_A_IN        (PORT_INPUT2_MODE)
#define    PORT252_GPIO        (PORT_GPIO_MODE)
#define    PORT252_FEC_FEC_TXEN_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT252_SENT_A_SENT4_A_IN        (PORT_INPUT2_MODE)
#define    PORT253_GPIO        (PORT_GPIO_MODE)
#define    PORT253_FEC_FEC_RXD1_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT253_SENT_A_SENT5_A_IN        (PORT_INPUT2_MODE)
#define    PORT256_GPIO        (PORT_GPIO_MODE)
#define    PORT256_EBI_D_CS0        (PORT_ALT1_FUNC_MODE)
#define    PORT257_GPIO        (PORT_GPIO_MODE)
#define    PORT257_EBI_D_CS2        (PORT_ALT1_FUNC_MODE)
#define    PORT257_EBI_D_ADD_DAT31        (PORT_ALT2_FUNC_MODE)
#define    PORT258_GPIO        (PORT_GPIO_MODE)
#define    PORT258_EBI_D_CS3        (PORT_ALT1_FUNC_MODE)
#define    PORT258_EBI_D_TEA        (PORT_ALT2_FUNC_MODE)
#define    PORT259_GPIO        (PORT_GPIO_MODE)
#define    PORT259_EBI_D_ADD12        (PORT_ALT1_FUNC_MODE)
#define    PORT260_GPIO        (PORT_GPIO_MODE)
#define    PORT260_EBI_D_ADD13        (PORT_ALT1_FUNC_MODE)
#define    PORT261_GPIO        (PORT_GPIO_MODE)
#define    PORT261_EBI_D_ADD14        (PORT_ALT1_FUNC_MODE)
#define    PORT262_GPIO        (PORT_GPIO_MODE)
#define    PORT262_EBI_D_ADD15        (PORT_ALT1_FUNC_MODE)
#define    PORT263_GPIO        (PORT_GPIO_MODE)
#define    PORT263_EBI_D_ADD16        (PORT_ALT1_FUNC_MODE)
#define    PORT263_EBI_D_ADD_DAT16        (PORT_ALT2_FUNC_MODE)
#define    PORT264_GPIO        (PORT_GPIO_MODE)
#define    PORT264_EBI_D_ADD17        (PORT_ALT1_FUNC_MODE)
#define    PORT264_EBI_D_ADD_DAT17        (PORT_ALT2_FUNC_MODE)
#define    PORT265_GPIO        (PORT_GPIO_MODE)
#define    PORT265_EBI_D_ADD18        (PORT_ALT1_FUNC_MODE)
#define    PORT265_EBI_D_ADD_DAT18        (PORT_ALT2_FUNC_MODE)
#define    PORT266_GPIO        (PORT_GPIO_MODE)
#define    PORT266_EBI_D_ADD19        (PORT_ALT1_FUNC_MODE)
#define    PORT266_EBI_D_ADD_DAT19        (PORT_ALT2_FUNC_MODE)
#define    PORT267_GPIO        (PORT_GPIO_MODE)
#define    PORT267_EBI_D_ADD20        (PORT_ALT1_FUNC_MODE)
#define    PORT267_EBI_D_ADD_DAT20        (PORT_ALT2_FUNC_MODE)
#define    PORT268_GPIO        (PORT_GPIO_MODE)
#define    PORT268_EBI_D_ADD21        (PORT_ALT1_FUNC_MODE)
#define    PORT268_EBI_D_ADD_DAT21        (PORT_ALT2_FUNC_MODE)
#define    PORT269_GPIO        (PORT_GPIO_MODE)
#define    PORT269_EBI_D_ADD22        (PORT_ALT1_FUNC_MODE)
#define    PORT269_EBI_D_ADD_DAT22        (PORT_ALT2_FUNC_MODE)
#define    PORT270_GPIO        (PORT_GPIO_MODE)
#define    PORT270_EBI_D_ADD23        (PORT_ALT1_FUNC_MODE)
#define    PORT270_EBI_D_ADD_DAT23        (PORT_ALT2_FUNC_MODE)
#define    PORT271_GPIO        (PORT_GPIO_MODE)
#define    PORT271_EBI_D_ADD24        (PORT_ALT1_FUNC_MODE)
#define    PORT271_EBI_D_ADD_DAT24        (PORT_ALT2_FUNC_MODE)
#define    PORT272_GPIO        (PORT_GPIO_MODE)
#define    PORT272_EBI_D_ADD25        (PORT_ALT1_FUNC_MODE)
#define    PORT272_EBI_D_ADD_DAT25        (PORT_ALT2_FUNC_MODE)
#define    PORT273_GPIO        (PORT_GPIO_MODE)
#define    PORT273_EBI_D_ADD26        (PORT_ALT1_FUNC_MODE)
#define    PORT273_EBI_D_ADD_DAT26        (PORT_ALT2_FUNC_MODE)
#define    PORT274_GPIO        (PORT_GPIO_MODE)
#define    PORT274_EBI_D_ADD27        (PORT_ALT1_FUNC_MODE)
#define    PORT274_EBI_D_ADD_DAT27        (PORT_ALT2_FUNC_MODE)
#define    PORT275_GPIO        (PORT_GPIO_MODE)
#define    PORT275_EBI_D_ADD28        (PORT_ALT1_FUNC_MODE)
#define    PORT275_EBI_D_ADD_DAT28        (PORT_ALT2_FUNC_MODE)
#define    PORT276_GPIO        (PORT_GPIO_MODE)
#define    PORT276_EBI_D_ADD29        (PORT_ALT1_FUNC_MODE)
#define    PORT276_EBI_D_ADD_DAT29        (PORT_ALT2_FUNC_MODE)
#define    PORT277_GPIO        (PORT_GPIO_MODE)
#define    PORT277_EBI_D_ADD30        (PORT_ALT1_FUNC_MODE)
#define    PORT277_EBI_D_ADD_DAT30        (PORT_ALT2_FUNC_MODE)
#define    PORT278_GPIO        (PORT_GPIO_MODE)
#define    PORT278_EBI_D_DAT0        (PORT_ALT1_FUNC_MODE)
#define    PORT279_GPIO        (PORT_GPIO_MODE)
#define    PORT279_EBI_D_DAT1        (PORT_ALT1_FUNC_MODE)
#define    PORT280_GPIO        (PORT_GPIO_MODE)
#define    PORT280_EBI_D_DAT2        (PORT_ALT1_FUNC_MODE)
#define    PORT281_GPIO        (PORT_GPIO_MODE)
#define    PORT281_EBI_D_DAT3        (PORT_ALT1_FUNC_MODE)
#define    PORT282_GPIO        (PORT_GPIO_MODE)
#define    PORT282_EBI_D_DAT4        (PORT_ALT1_FUNC_MODE)
#define    PORT283_GPIO        (PORT_GPIO_MODE)
#define    PORT283_EBI_D_DAT5        (PORT_ALT1_FUNC_MODE)
#define    PORT284_GPIO        (PORT_GPIO_MODE)
#define    PORT284_EBI_D_DAT6        (PORT_ALT1_FUNC_MODE)
#define    PORT285_GPIO        (PORT_GPIO_MODE)
#define    PORT285_EBI_D_DAT7        (PORT_ALT1_FUNC_MODE)
#define    PORT286_GPIO        (PORT_GPIO_MODE)
#define    PORT286_EBI_D_DAT8        (PORT_ALT1_FUNC_MODE)
#define    PORT287_GPIO        (PORT_GPIO_MODE)
#define    PORT287_EBI_D_DAT9        (PORT_ALT1_FUNC_MODE)
#define    PORT288_GPIO        (PORT_GPIO_MODE)
#define    PORT288_EBI_D_DAT10        (PORT_ALT1_FUNC_MODE)
#define    PORT289_GPIO        (PORT_GPIO_MODE)
#define    PORT289_EBI_D_DAT11        (PORT_ALT1_FUNC_MODE)
#define    PORT290_GPIO        (PORT_GPIO_MODE)
#define    PORT290_EBI_D_DAT12        (PORT_ALT1_FUNC_MODE)
#define    PORT291_GPIO        (PORT_GPIO_MODE)
#define    PORT291_EBI_D_DAT13        (PORT_ALT1_FUNC_MODE)
#define    PORT292_GPIO        (PORT_GPIO_MODE)
#define    PORT292_EBI_D_DAT14        (PORT_ALT1_FUNC_MODE)
#define    PORT293_GPIO        (PORT_GPIO_MODE)
#define    PORT293_EBI_D_DAT15        (PORT_ALT1_FUNC_MODE)
#define    PORT294_GPIO        (PORT_GPIO_MODE)
#define    PORT294_EBI_D_RD_WR        (PORT_ALT1_FUNC_MODE)
#define    PORT295_GPIO        (PORT_GPIO_MODE)
#define    PORT295_EBI_D_WE0        (PORT_ALT1_FUNC_MODE)
#define    PORT296_GPIO        (PORT_GPIO_MODE)
#define    PORT296_EBI_D_WE1        (PORT_ALT1_FUNC_MODE)
#define    PORT297_GPIO        (PORT_GPIO_MODE)
#define    PORT297_EBI_D_OE        (PORT_ALT1_FUNC_MODE)
#define    PORT298_GPIO        (PORT_GPIO_MODE)
#define    PORT298_EBI_D_TS        (PORT_ALT1_FUNC_MODE)
#define    PORT299_GPIO        (PORT_GPIO_MODE)
#define    PORT299_EBI_D_ALE        (PORT_ALT1_FUNC_MODE)
#define    PORT300_GPIO        (PORT_GPIO_MODE)
#define    PORT300_EBI_D_TA        (PORT_ALT1_FUNC_MODE)
#define    PORT301_GPIO        (PORT_GPIO_MODE)
#define    PORT301_EBI_D_CS1        (PORT_ALT1_FUNC_MODE)
#define    PORT302_GPIO        (PORT_GPIO_MODE)
#define    PORT302_EBI_D_BDIP        (PORT_ALT1_FUNC_MODE)
#define    PORT303_GPIO        (PORT_GPIO_MODE)
#define    PORT303_EBI_D_WE2        (PORT_ALT1_FUNC_MODE)
#define    PORT304_GPIO        (PORT_GPIO_MODE)
#define    PORT304_EBI_D_WE3        (PORT_ALT1_FUNC_MODE)
#define    PORT305_GPIO        (PORT_GPIO_MODE)
#define    PORT305_EBI_D_ADD9        (PORT_ALT1_FUNC_MODE)
#define    PORT306_GPIO        (PORT_GPIO_MODE)
#define    PORT306_EBI_D_ADD10        (PORT_ALT1_FUNC_MODE)
#define    PORT307_GPIO        (PORT_GPIO_MODE)
#define    PORT307_EBI_D_ADD11        (PORT_ALT1_FUNC_MODE)
#define    PORT432_GPIO        (PORT_GPIO_MODE)
#define    PORT432_eMIOS_B_EMIOS18_INOUT        (PORT_INPUT1_MODE)
#define    PORT432_DSPI_B_PCSB2        (PORT_ALT2_FUNC_MODE)
#define    PORT432_eMIOS_B_EMIOS18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT432_eMIOS_B_EMIOS18_IN        (PORT_INPUT1_MODE)
#define    PORT433_GPIO        (PORT_GPIO_MODE)
#define    PORT433_eMIOS_B_EMIOS19_INOUT        (PORT_INPUT1_MODE)
#define    PORT433_DSPI_B_PCSB3        (PORT_ALT2_FUNC_MODE)
#define    PORT433_eMIOS_B_EMIOS19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT433_eMIOS_B_EMIOS19_IN        (PORT_INPUT1_MODE)
#define    PORT434_GPIO        (PORT_GPIO_MODE)
#define    PORT434_eMIOS_B_EMIOS20_INOUT        (PORT_INPUT1_MODE)
#define    PORT434_DSPI_C_PCSC0_INOUT        (PORT_INPUT2_MODE)
#define    PORT434_eMIOS_B_EMIOS20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT434_DSPI_C_PCSC0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT434_eMIOS_B_EMIOS20_IN        (PORT_INPUT1_MODE)
#define    PORT434_DSPI_C_PCSC0_IN        (PORT_INPUT2_MODE)
#define    PORT435_GPIO        (PORT_GPIO_MODE)
#define    PORT435_eMIOS_B_EMIOS21_INOUT        (PORT_INPUT1_MODE)
#define    PORT435_DSPI_C_PCSC1        (PORT_ALT2_FUNC_MODE)
#define    PORT435_eMIOS_B_EMIOS21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT435_eMIOS_B_EMIOS21_IN        (PORT_INPUT1_MODE)
#define    PORT436_GPIO        (PORT_GPIO_MODE)
#define    PORT436_eMIOS_B_EMIOS22_INOUT        (PORT_INPUT1_MODE)
#define    PORT436_DSPI_C_PCSC2        (PORT_ALT2_FUNC_MODE)
#define    PORT436_eMIOS_B_EMIOS22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT436_eMIOS_B_EMIOS22_IN        (PORT_INPUT1_MODE)
#define    PORT437_GPIO        (PORT_GPIO_MODE)
#define    PORT437_eMIOS_B_EMIOS23_INOUT        (PORT_INPUT1_MODE)
#define    PORT437_DSPI_C_PCSC5        (PORT_ALT2_FUNC_MODE)
#define    PORT437_eMIOS_B_EMIOS23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT437_eMIOS_B_EMIOS23_IN        (PORT_INPUT1_MODE)
#define    PORT440_GPI        (PORT_GPIO_MODE)
#define    PORT440_eTPU_C_TCRCLKC_IN        (PORT_INPUT1_MODE)
#define    PORT440_SIU_A_IRQ6_IN        (PORT_INPUT2_MODE)
#define    PORT440_eQADC_B_ANB40_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT441_GPI        (PORT_GPIO_MODE)
#define    PORT441_eTPU_C_ETPUC0_IN        (PORT_INPUT1_MODE)
#define    PORT441_SENT_A_SENT0_A_IN        (PORT_INPUT2_MODE)
#define    PORT441_eQADC_B_ANB41_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT442_GPI        (PORT_GPIO_MODE)
#define    PORT442_eTPU_C_ETPUC1_IN        (PORT_INPUT1_MODE)
#define    PORT442_SENT_A_SENT1_A_IN        (PORT_INPUT2_MODE)
#define    PORT442_eQADC_B_ANB42_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT443_GPIO        (PORT_GPIO_MODE)
#define    PORT443_eTPU_C_ETPUC2_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT443_SENT_A_SENT3_A_IN        (PORT_INPUT2_MODE)
#define    PORT443_eTPU_C_ETPUC2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT443_eTPU_C_ETPUC2_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT444_GPI        (PORT_GPIO_MODE)
#define    PORT444_eTPU_C_ETPUC3_IN        (PORT_INPUT1_MODE)
#define    PORT444_SENT_A_SENT4_A_IN        (PORT_INPUT2_MODE)
#define    PORT444_eQADC_B_ANB45_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT445_GPIO        (PORT_GPIO_MODE)
#define    PORT445_eTPU_C_ETPUC4_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT445_SENT_A_SENT5_A_IN        (PORT_INPUT2_MODE)
#define    PORT445_eTPU_C_TCRCLKC_IN        (PORT_INPUT3_MODE)
#define    PORT445_eTPU_C_ETPUC4_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT445_eTPU_C_ETPUC4_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT446_GPIO        (PORT_GPIO_MODE)
#define    PORT446_eTPU_C_ETPUC5_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT446_DSPI_E_PCSE2        (PORT_ALT2_FUNC_MODE)
#define    PORT446_SENT_B_SENT0_B_IN        (PORT_INPUT3_MODE)
#define    PORT446_eTPU_C_ETPUC5_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT446_eTPU_C_ETPUC5_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT447_GPIO        (PORT_GPIO_MODE)
#define    PORT447_eTPU_C_ETPUC6_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT447_DSPI_E_PCSE3        (PORT_ALT2_FUNC_MODE)
#define    PORT447_SENT_B_SENT1_B_IN        (PORT_INPUT3_MODE)
#define    PORT447_eTPU_C_ETPUC6_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT447_eTPU_C_ETPUC6_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT448_GPIO        (PORT_GPIO_MODE)
#define    PORT448_eTPU_C_ETPUC7_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT448_DSPI_E_PCSE4        (PORT_ALT2_FUNC_MODE)
#define    PORT448_SENT_B_SENT2_B_IN        (PORT_INPUT3_MODE)
#define    PORT448_eTPU_C_ETPUC7_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT448_eTPU_C_ETPUC7_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT449_GPIO        (PORT_GPIO_MODE)
#define    PORT449_eTPU_C_ETPUC8_INOUT        (PORT_INPUT1_MODE)
#define    PORT449_DSPI_E_PCSE5        (PORT_ALT2_FUNC_MODE)
#define    PORT449_SENT_B_SENT3_B_IN        (PORT_INPUT3_MODE)
#define    PORT449_eTPU_C_ETPUC8_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT449_eTPU_C_ETPUC8_IN        (PORT_INPUT1_MODE)
#define    PORT450_GPI        (PORT_GPIO_MODE)
#define    PORT450_eTPU_C_ETPUC9_IN        (PORT_INPUT1_MODE)
#define    PORT450_SIU_A_IRQ0_IN        (PORT_INPUT2_MODE)
#define    PORT450_SENT_B_SENT4_B_IN        (PORT_INPUT3_MODE)
#define    PORT450_eQADC_B_ANB44_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT451_GPIO        (PORT_GPIO_MODE)
#define    PORT451_eTPU_C_ETPUC10_INOUT        (PORT_INPUT1_MODE)
#define    PORT451_SIU_A_IRQ1_IN        (PORT_INPUT2_MODE)
#define    PORT451_SENT_B_SENT5_B_IN        (PORT_INPUT3_MODE)
#define    PORT451_eTPU_C_ETPUC10_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT451_eTPU_C_ETPUC10_IN        (PORT_INPUT1_MODE)
#define    PORT452_GPIO        (PORT_GPIO_MODE)
#define    PORT452_eTPU_C_ETPUC11_INOUT        (PORT_INPUT1_MODE)
#define    PORT452_SIU_A_IRQ2_IN        (PORT_INPUT2_MODE)
#define    PORT452_eTPU_C_ETPUC11_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT452_eTPU_C_ETPUC11_IN        (PORT_INPUT1_MODE)
#define    PORT453_GPIO        (PORT_GPIO_MODE)
#define    PORT453_eTPU_C_ETPUC12_INOUT        (PORT_INPUT1_MODE)
#define    PORT453_SIU_A_IRQ3_IN        (PORT_INPUT2_MODE)
#define    PORT453_MCAN_1_TX_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT453_eTPU_C_ETPUC12_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT453_eTPU_C_ETPUC12_IN        (PORT_INPUT1_MODE)
#define    PORT454_GPIO        (PORT_GPIO_MODE)
#define    PORT454_eTPU_C_ETPUC13_INOUT        (PORT_INPUT1_MODE)
#define    PORT454_SIU_A_IRQ4_IN        (PORT_INPUT2_MODE)
#define    PORT454_PSI5A_SDOUT0_PSI5A_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT454_REACM_RCH0_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT454_eTPU_C_ETPUC13_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT454_eTPU_C_ETPUC13_IN        (PORT_INPUT1_MODE)
#define    PORT455_GPIO        (PORT_GPIO_MODE)
#define    PORT455_eTPU_C_ETPUC14_INOUT        (PORT_INPUT1_MODE)
#define    PORT455_SIU_A_IRQ5_IN        (PORT_INPUT2_MODE)
#define    PORT455_PSI5A_SDIN0_PSI5A_IN        (PORT_ALT3_FUNC_MODE)
#define    PORT455_REACM_RCH1_C_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT455_eTPU_C_ETPUC14_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT455_eTPU_C_ETPUC14_IN        (PORT_INPUT1_MODE)
#define    PORT456_GPIO        (PORT_GPIO_MODE)
#define    PORT456_eTPU_C_ETPUC15_INOUT        (PORT_INPUT1_MODE)
#define    PORT456_MCAN_1_RX_IN        (PORT_INPUT2_MODE)
#define    PORT456_REACM_RCH2_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT456_eTPU_C_ETPUC15_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT456_eTPU_C_ETPUC15_IN        (PORT_INPUT1_MODE)
#define    PORT457_GPIO        (PORT_GPIO_MODE)
#define    PORT457_eTPU_C_ETPUC16_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT457_MCAN_1_TX_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT457_REACM_RCH3_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT457_eTPU_C_ETPUC16_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT457_eTPU_C_ETPUC16_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT458_GPIO        (PORT_GPIO_MODE)
#define    PORT458_eTPU_C_ETPUC17_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT458_eSCI_F_TXDF        (PORT_ALT2_FUNC_MODE)
#define    PORT458_REACM_RCH4_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT458_eTPU_C_ETPUC17_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT458_eTPU_C_ETPUC17_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT459_GPIO        (PORT_GPIO_MODE)
#define    PORT459_eTPU_C_ETPUC18_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT459_eSCI_F_RXDF_IN        (PORT_ALT2_FUNC_MODE)
#define    PORT459_eTPU_C_ETPUC18_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT459_eTPU_C_ETPUC18_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT460_GPIO        (PORT_GPIO_MODE)
#define    PORT460_eTPU_C_ETPUC19_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT460_eSCI_A_TXDA        (PORT_INPUT2_MODE)
#define    PORT460_PSI5A_SDOUT0_PSI5B_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT460_eTPU_C_ETPUC19_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT460_eTPU_C_ETPUC19_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT461_GPIO        (PORT_GPIO_MODE)
#define    PORT461_eTPU_C_ETPUC20_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT461_eSCI_A_RXDA_IN        (PORT_INPUT2_MODE)
#define    PORT461_PSI5A_SDIN0_PSI5B_IN        (PORT_ALT3_FUNC_MODE)
#define    PORT461_eTPU_C_ETPUC20_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT461_eTPU_C_ETPUC20_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT462_GPIO        (PORT_GPIO_MODE)
#define    PORT462_eTPU_C_ETPUC21_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT462_eSCI_B_TXDB        (PORT_INPUT2_MODE)
#define    PORT462_eTPU_C_ETPUC21_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT462_eTPU_C_ETPUC21_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT463_GPIO        (PORT_GPIO_MODE)
#define    PORT463_eTPU_C_ETPUC22_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT463_eSCI_B_RXDB_IN        (PORT_INPUT2_MODE)
#define    PORT463_eTPU_C_ETPUC22_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT463_eTPU_C_ETPUC22_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT464_GPIO        (PORT_GPIO_MODE)
#define    PORT464_eTPU_C_ETPUC23_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT464_DSPI_D_PCSD5        (PORT_ALT2_FUNC_MODE)
#define    PORT464_eQADC_A_MAA0        (PORT_ALT3_FUNC_MODE)
#define    PORT464_eQADC_B_MAB0        (PORT_ALT4_FUNC_MODE)
#define    PORT464_eTPU_C_ETPUC23_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT464_eTPU_C_ETPUC23_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT465_GPIO        (PORT_GPIO_MODE)
#define    PORT465_eTPU_C_ETPUC24_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT465_DSPI_D_PCSD4        (PORT_ALT2_FUNC_MODE)
#define    PORT465_eQADC_A_MAA1        (PORT_ALT3_FUNC_MODE)
#define    PORT465_eQADC_B_MAB1        (PORT_ALT4_FUNC_MODE)
#define    PORT465_eTPU_C_ETPUC24_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT465_eTPU_C_ETPUC24_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT466_GPIO        (PORT_GPIO_MODE)
#define    PORT466_eTPU_C_ETPUC25_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT466_DSPI_D_PCSD3        (PORT_ALT2_FUNC_MODE)
#define    PORT466_eQADC_A_MAA2        (PORT_ALT3_FUNC_MODE)
#define    PORT466_eQADC_B_MAB2        (PORT_ALT4_FUNC_MODE)
#define    PORT466_eTPU_C_ETPUC25_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT466_eTPU_C_ETPUC25_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT467_GPIO        (PORT_GPIO_MODE)
#define    PORT467_eTPU_C_ETPUC26_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT467_DSPI_D_PCSD2        (PORT_ALT2_FUNC_MODE)
#define    PORT467_eQADC_B_MAB0        (PORT_ALT3_FUNC_MODE)
#define    PORT467_eTPU_C_ETPUC26_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT467_eTPU_C_ETPUC26_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT468_GPIO        (PORT_GPIO_MODE)
#define    PORT468_eTPU_C_ETPUC27_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT468_DSPI_D_PCSD1        (PORT_ALT2_FUNC_MODE)
#define    PORT468_REACM_RCH5_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT468_eQADC_B_MAB1        (PORT_ALT4_FUNC_MODE)
#define    PORT468_eTPU_C_ETPUC27_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT468_eTPU_C_ETPUC27_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT469_GPIO        (PORT_GPIO_MODE)
#define    PORT469_eTPU_C_ETPUC28_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT469_DSPI_D_PCSD0_INOUT        (PORT_INPUT2_MODE)
#define    PORT469_REACM_RCH6_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT469_eQADC_B_MAB2        (PORT_ALT4_FUNC_MODE)
#define    PORT469_eTPU_C_ETPUC28_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT469_DSPI_D_PCSD0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT469_eTPU_C_ETPUC28_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT469_DSPI_D_PCSD0_IN        (PORT_INPUT2_MODE)
#define    PORT470_GPIO        (PORT_GPIO_MODE)
#define    PORT470_eTPU_C_ETPUC29_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT470_DSPI_D_SCKD_INOUT        (PORT_INPUT2_MODE)
#define    PORT470_REACM_RCH7_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT470_eTPU_C_ETPUC29_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT470_DSPI_D_SCKD_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT470_eTPU_C_ETPUC29_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT470_DSPI_D_SCKD_IN        (PORT_INPUT2_MODE)
#define    PORT471_GPIO        (PORT_GPIO_MODE)
#define    PORT471_eTPU_C_ETPUC30_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT471_DSPI_D_SOUTD        (PORT_ALT2_FUNC_MODE)
#define    PORT471_REACM_RCH8_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT471_eTPU_C_ETPUC30_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT471_eTPU_C_ETPUC30_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT472_GPIO        (PORT_GPIO_MODE)
#define    PORT472_eTPU_C_ETPUC31_INOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT472_DSPI_D_SIND_IN        (PORT_INPUT2_MODE)
#define    PORT472_REACM_RCH9_C_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT472_eTPU_C_ETPUC31_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT472_eTPU_C_ETPUC31_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT474_GPI        (PORT_GPIO_MODE)
#define    PORT474_FEC_FEC_TXCLK_REFCLK_IN        (PORT_ALT1_FUNC_MODE)
#define    PORT474_SENT_B_SENT0_B_IN        (PORT_INPUT2_MODE)
#define    PORT475_GPI        (PORT_GPIO_MODE)
#define    PORT475_SENT_A_SENT2_A_IN        (PORT_INPUT1_MODE)
#define    PORT475_eQADC_B_ANB43_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT476_GPI        (PORT_GPIO_MODE)
#define    PORT476_eQADC_B_ANB8_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT476_eTPU_A_ETPUA31_IN        (PORT_INPUT2_MODE)
#define    PORT476_eMIOS_A_EMIOS16_IN        (PORT_INPUT3_MODE)
#define    PORT477_GPI        (PORT_GPIO_MODE)
#define    PORT477_eQADC_B_ANB9_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT477_eTPU_A_ETPUA30_IN        (PORT_INPUT2_MODE)
#define    PORT477_eMIOS_A_EMIOS17_IN        (PORT_INPUT3_MODE)
#define    PORT478_GPI        (PORT_GPIO_MODE)
#define    PORT478_eQADC_B_ANB10_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT478_eTPU_A_ETPUA29_IN        (PORT_INPUT2_MODE)
#define    PORT478_eMIOS_A_EMIOS18_IN        (PORT_INPUT3_MODE)
#define    PORT479_GPI        (PORT_GPIO_MODE)
#define    PORT479_eQADC_B_ANB11_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT479_eTPU_A_ETPUA28_IN        (PORT_INPUT2_MODE)
#define    PORT479_eMIOS_A_EMIOS19_IN        (PORT_INPUT3_MODE)
#define    PORT480_GPI        (PORT_GPIO_MODE)
#define    PORT480_eQADC_B_ANB12_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT480_eTPU_A_ETPUA27_IN        (PORT_INPUT2_MODE)
#define    PORT480_eMIOS_A_EMIOS20_IN        (PORT_INPUT3_MODE)
#define    PORT481_GPI        (PORT_GPIO_MODE)
#define    PORT481_eQADC_B_ANB13_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT481_eTPU_A_ETPUA26_IN        (PORT_INPUT2_MODE)
#define    PORT481_eMIOS_A_EMIOS21_IN        (PORT_INPUT3_MODE)
#define    PORT482_GPI        (PORT_GPIO_MODE)
#define    PORT482_eQADC_B_ANB14_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT482_eTPU_A_ETPUA25_IN        (PORT_INPUT2_MODE)
#define    PORT482_eMIOS_A_EMIOS22_IN        (PORT_INPUT3_MODE)
#define    PORT483_GPI        (PORT_GPIO_MODE)
#define    PORT483_eQADC_B_ANB15_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT483_eTPU_A_ETPUA24_IN        (PORT_INPUT2_MODE)
#define    PORT483_eMIOS_A_EMIOS23_IN        (PORT_INPUT3_MODE)
#define    PORT484_GPI        (PORT_GPIO_MODE)
#define    PORT484_eQADC_B_ANB16_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT484_eTPU_C_ETPUC15_IN        (PORT_INPUT2_MODE)
#define    PORT484_eMIOS_B_EMIOS16_IN        (PORT_INPUT3_MODE)
#define    PORT485_GPI        (PORT_GPIO_MODE)
#define    PORT485_eQADC_B_ANB17_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT485_eTPU_C_ETPUC14_IN        (PORT_INPUT2_MODE)
#define    PORT485_eMIOS_B_EMIOS17_IN        (PORT_INPUT3_MODE)
#define    PORT486_GPI        (PORT_GPIO_MODE)
#define    PORT486_eQADC_B_ANB18_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT486_eTPU_C_ETPUC13_IN        (PORT_INPUT2_MODE)
#define    PORT486_eMIOS_B_EMIOS18_IN        (PORT_INPUT3_MODE)
#define    PORT487_GPI        (PORT_GPIO_MODE)
#define    PORT487_eQADC_B_ANB19_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT487_eTPU_C_ETPUC12_IN        (PORT_INPUT2_MODE)
#define    PORT487_eMIOS_B_EMIOS19_IN        (PORT_INPUT3_MODE)
#define    PORT488_GPI        (PORT_GPIO_MODE)
#define    PORT488_eQADC_B_ANB20_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT488_eTPU_C_ETPUC11_IN        (PORT_INPUT2_MODE)
#define    PORT488_eMIOS_B_EMIOS20_IN        (PORT_INPUT3_MODE)
#define    PORT489_GPI        (PORT_GPIO_MODE)
#define    PORT489_eQADC_B_ANB21_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT489_eTPU_C_ETPUC10_IN        (PORT_INPUT2_MODE)
#define    PORT489_eMIOS_B_EMIOS21_IN        (PORT_INPUT3_MODE)
#define    PORT490_GPI        (PORT_GPIO_MODE)
#define    PORT490_eQADC_B_ANB22_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT490_eTPU_C_ETPUC9_IN        (PORT_INPUT2_MODE)
#define    PORT490_eMIOS_B_EMIOS22_IN        (PORT_INPUT3_MODE)
#define    PORT491_GPI        (PORT_GPIO_MODE)
#define    PORT491_eQADC_B_ANB23_IN        (PORT_ANALOG_INPUT_MODE)
#define    PORT491_eTPU_C_ETPUC8_IN        (PORT_INPUT2_MODE)
#define    PORT491_eMIOS_B_EMIOS23_IN        (PORT_INPUT3_MODE)
[!ENDVAR!]




[!VAR "INMUX0"!]
SENT_A_SENT0_A_IN_PORT248;1:[!//
SENT_A_SENT0_A_IN_PORT441;0:[!//
[!ENDVAR!]

[!VAR "INMUX1"!]
SENT_A_SENT1_A_IN_PORT249;1:[!//
SENT_A_SENT1_A_IN_PORT442;0:[!//
[!ENDVAR!]

[!VAR "INMUX2"!]
SENT_A_SENT2_A_IN_PORT250;1:[!//
SENT_A_SENT2_A_IN_PORT475;0:[!//
[!ENDVAR!]

[!VAR "INMUX3"!]
SENT_A_SENT3_A_IN_PORT251;1:[!//
SENT_A_SENT3_A_IN_PORT443;0:[!//
[!ENDVAR!]

[!VAR "INMUX4"!]
SENT_A_SENT4_A_IN_PORT252;1:[!//
SENT_A_SENT4_A_IN_PORT444;0:[!//
[!ENDVAR!]

[!VAR "INMUX5"!]
SENT_A_SENT5_A_IN_PORT253;1:[!//
SENT_A_SENT5_A_IN_PORT445;0:[!//
[!ENDVAR!]

[!VAR "INMUX6"!]
SENT_B_SENT0_B_IN_PORT446;0:[!//
SENT_B_SENT0_B_IN_PORT474;1:[!//
[!ENDVAR!]

[!VAR "INMUX7"!]
SENT_B_SENT1_B_IN_PORT93;1:[!//
SENT_B_SENT1_B_IN_PORT447;0:[!//
[!ENDVAR!]

[!VAR "INMUX8"!]
SENT_B_SENT2_B_IN_PORT107;1:[!//
SENT_B_SENT2_B_IN_PORT448;0:[!//
[!ENDVAR!]

[!VAR "INMUX9"!]
SENT_B_SENT3_B_IN_PORT108;1:[!//
SENT_B_SENT3_B_IN_PORT449;0:[!//
[!ENDVAR!]

[!VAR "INMUX10"!]
SENT_B_SENT4_B_IN_PORT109;1:[!//
SENT_B_SENT4_B_IN_PORT450;0:[!//
[!ENDVAR!]

[!VAR "INMUX11"!]
SENT_B_SENT5_B_IN_PORT110;1:[!//
SENT_B_SENT5_B_IN_PORT451;0:[!//
[!ENDVAR!]

[!VAR "INMUX12"!]
[!ENDVAR!]

[!VAR "INMUX13"!]
[!ENDVAR!]

[!VAR "INMUX14"!]
[!ENDVAR!]

[!VAR "INMUX15"!]
[!ENDVAR!]

[!VAR "INMUX16"!]
MCAN_0_RX_IN_PORT84;1:[!//
MCAN_0_RX_IN_PORT91;2:[!//
MCAN_0_RX_IN_PORT133;0:[!//
MCAN_0_RX_IN_PORT243;3:[!//
[!ENDVAR!]

[!VAR "INMUX17"!]
MCAN_1_RX_IN_PORT196;2:[!//
MCAN_1_RX_IN_PORT247;1:[!//
MCAN_1_RX_IN_PORT456;0:[!//
[!ENDVAR!]

[!VAR "INMUX18"!]
[!ENDVAR!]

[!VAR "INMUX19"!]
[!ENDVAR!]

[!VAR "INMUX20"!]
[!ENDVAR!]

[!VAR "INMUX21"!]
FlexCAN_D_CNRXD_IN_PORT194;1:[!//
FlexCAN_D_CNRXD_IN_PORT247;0:[!//
[!ENDVAR!]

[!VAR "INMUX22"!]
[!ENDVAR!]

[!VAR "INMUX23"!]
[!ENDVAR!]

[!VAR "INMUX24"!]
[!ENDVAR!]

[!VAR "INMUX25"!]
[!ENDVAR!]

[!VAR "INMUX26"!]
[!ENDVAR!]

[!VAR "INMUX27"!]
[!ENDVAR!]

[!VAR "INMUX28"!]
[!ENDVAR!]

[!VAR "INMUX29"!]
[!ENDVAR!]

[!VAR "INMUX30"!]
[!ENDVAR!]

[!VAR "INMUX31"!]
[!ENDVAR!]

[!VAR "INMUX32"!]
[!ENDVAR!]

[!VAR "INMUX33"!]
[!ENDVAR!]

[!VAR "INMUX34"!]
[!ENDVAR!]

[!VAR "INMUX35"!]
[!ENDVAR!]

[!VAR "INMUX36"!]
[!ENDVAR!]

[!VAR "INMUX37"!]
DSPI_B_PCSB0_INOUT_PORT105;0:[!//
DSPI_B_PCSB0_IN_PORT105;0:[!//
DSPI_B_PCSB0_INOUT_PORT203;1:[!//
DSPI_B_PCSB0_IN_PORT203;1:[!//
[!ENDVAR!]

[!VAR "INMUX38"!]
DSPI_C_SCKC_INOUT_PORT109;1:[!//
DSPI_C_SCKC_IN_PORT109;1:[!//
DSPI_C_SCKC_INOUT_PORT235;0:[!//
DSPI_C_SCKC_IN_PORT235;0:[!//
[!ENDVAR!]

[!VAR "INMUX39"!]
DSPI_C_SINC_PORT108;1:[!//
DSPI_C_SINC_IN_PORT236;0:[!//
[!ENDVAR!]

[!VAR "INMUX40"!]
DSPI_C_PCSC0_INOUT_PORT110;1:[!//
DSPI_C_PCSC0_IN_PORT110;1:[!//
DSPI_C_PCSC0_INOUT_PORT238;0:[!//
DSPI_C_PCSC0_IN_PORT238;0:[!//
DSPI_C_PCSC0_INOUT_PORT434;2:[!//
DSPI_C_PCSC0_IN_PORT434;2:[!//
[!ENDVAR!]

[!VAR "INMUX41"!]
DSPI_D_SCKD_INOUT_PORT189;2:[!//
DSPI_D_SCKD_IN_PORT189;2:[!//
DSPI_D_SCKD_INOUT_PORT240;0:[!//
DSPI_D_SCKD_IN_PORT240;0:[!//
DSPI_D_SCKD_INOUT_PORT470;1:[!//
DSPI_D_SCKD_IN_PORT470;1:[!//
[!ENDVAR!]

[!VAR "INMUX42"!]
DSPI_D_SIND_PORT190;2:[!//
DSPI_D_SIND_IN_PORT241;0:[!//
DSPI_D_SIND_IN_PORT472;1:[!//
[!ENDVAR!]

[!VAR "INMUX43"!]
DSPI_D_PCSD0_INOUT_PORT106;0:[!//
DSPI_D_PCSD0_IN_PORT106;0:[!//
DSPI_D_PCSD0_INOUT_PORT243;2:[!//
DSPI_D_PCSD0_IN_PORT243;2:[!//
DSPI_D_PCSD0_INOUT_PORT469;1:[!//
DSPI_D_PCSD0_IN_PORT469;1:[!//
[!ENDVAR!]

[!VAR "INMUX44"!]
[!ENDVAR!]

[!VAR "INMUX45"!]
[!ENDVAR!]

[!VAR "INMUX46"!]
[!ENDVAR!]

[!VAR "INMUX47"!]
[!ENDVAR!]

[!VAR "INMUX48"!]
SIU_A_IRQ0_PORT193;0:[!//
SIU_A_IRQ0_IN_PORT450;1:[!//
[!ENDVAR!]

[!VAR "INMUX49"!]
SIU_A_IRQ1_IN_PORT194;0:[!//
SIU_A_IRQ1_IN_PORT451;1:[!//
[!ENDVAR!]

[!VAR "INMUX50"!]
SIU_A_IRQ2_IN_PORT211;0:[!//
SIU_A_IRQ2_IN_PORT452;1:[!//
[!ENDVAR!]

[!VAR "INMUX51"!]
SIU_A_IRQ3_IN_PORT212;0:[!//
SIU_A_IRQ3_IN_PORT453;1:[!//
[!ENDVAR!]

[!VAR "INMUX52"!]
SIU_A_IRQ4_IN_PORT208;0:[!//
SIU_A_IRQ4_IN_PORT454;1:[!//
[!ENDVAR!]

[!VAR "INMUX53"!]
SIU_A_IRQ5_IN_PORT209;0:[!//
SIU_A_IRQ5_IN_PORT455;1:[!//
[!ENDVAR!]

[!VAR "INMUX54"!]
SIU_A_IRQ6_PORT146;0:[!//
SIU_A_IRQ6_IN_PORT440;1:[!//
[!ENDVAR!]

[!VAR "INMUX55"!]
[!ENDVAR!]

[!VAR "INMUX56"!]
[!ENDVAR!]

[!VAR "INMUX57"!]
[!ENDVAR!]

[!VAR "INMUX58"!]
[!ENDVAR!]

[!VAR "INMUX59"!]
[!ENDVAR!]

[!VAR "INMUX60"!]
[!ENDVAR!]

[!VAR "INMUX61"!]
[!ENDVAR!]

[!VAR "INMUX62"!]
[!ENDVAR!]

[!VAR "INMUX63"!]
[!ENDVAR!]

[!VAR "INMUX64"!]
eSCI_A_TXDA_PORT83;1:[!//
eSCI_A_TXDA_PORT89;0:[!//
eSCI_A_TXDA_PORT460;2:[!//
[!ENDVAR!]

[!VAR "INMUX65"!]
eSCI_A_RXDA_PORT84;1:[!//
eSCI_A_RXDA_IN_PORT90;0:[!//
eSCI_A_RXDA_IN_PORT461;2:[!//
[!ENDVAR!]

[!VAR "INMUX66"!]
eSCI_B_RXDB_PORT92;0:[!//
eSCI_B_RXDB_IN_PORT463;1:[!//
[!ENDVAR!]

[!VAR "INMUX67"!]
eSCI_B_TXDB_PORT91;0:[!//
eSCI_B_TXDB_PORT462;1:[!//
[!ENDVAR!]

[!VAR "INMUX68"!]
[!ENDVAR!]

[!VAR "INMUX69"!]
[!ENDVAR!]

[!VAR "INMUX70"!]
[!ENDVAR!]

[!VAR "INMUX71"!]
[!ENDVAR!]

[!VAR "INMUX72"!]
eSCI_E_TXDE_PORT100;0:[!//
eSCI_E_TXDE_PORT223;1:[!//
[!ENDVAR!]

[!VAR "INMUX73"!]
[!ENDVAR!]

[!VAR "INMUX74"!]
[!ENDVAR!]

[!VAR "INMUX75"!]
[!ENDVAR!]

[!VAR "INMUX76"!]
[!ENDVAR!]

[!VAR "INMUX77"!]
[!ENDVAR!]

[!VAR "INMUX78"!]
[!ENDVAR!]

[!VAR "INMUX79"!]
[!ENDVAR!]

[!VAR "INMUX80"!]
eMIOS_A_EMIOS16_INOUT_PORT195;0:[!//
eMIOS_A_EMIOS16_IN_PORT195;0:[!//
eMIOS_A_EMIOS16_IN_PORT476;1:[!//
[!ENDVAR!]

[!VAR "INMUX81"!]
eMIOS_A_EMIOS17_INOUT_PORT196;0:[!//
eMIOS_A_EMIOS17_IN_PORT196;0:[!//
eMIOS_A_EMIOS17_IN_PORT477;1:[!//
[!ENDVAR!]

[!VAR "INMUX82"!]
eMIOS_A_EMIOS18_INOUT_PORT197;0:[!//
eMIOS_A_EMIOS18_IN_PORT197;0:[!//
eMIOS_A_EMIOS18_IN_PORT478;1:[!//
[!ENDVAR!]

[!VAR "INMUX83"!]
eMIOS_A_EMIOS19_INOUT_PORT198;0:[!//
eMIOS_A_EMIOS19_IN_PORT198;0:[!//
eMIOS_A_EMIOS19_IN_PORT479;1:[!//
[!ENDVAR!]

[!VAR "INMUX84"!]
eMIOS_A_EMIOS20_INOUT_PORT199;0:[!//
eMIOS_A_EMIOS20_IN_PORT199;0:[!//
eMIOS_A_EMIOS20_IN_PORT480;1:[!//
[!ENDVAR!]

[!VAR "INMUX85"!]
eMIOS_A_EMIOS21_INOUT_PORT200;0:[!//
eMIOS_A_EMIOS21_IN_PORT200;0:[!//
eMIOS_A_EMIOS21_IN_PORT481;1:[!//
[!ENDVAR!]

[!VAR "INMUX86"!]
eMIOS_A_EMIOS22_INOUT_PORT201;0:[!//
eMIOS_A_EMIOS22_IN_PORT201;0:[!//
eMIOS_A_EMIOS22_IN_PORT482;1:[!//
[!ENDVAR!]

[!VAR "INMUX87"!]
eMIOS_A_EMIOS23_INOUT_PORT202;0:[!//
eMIOS_A_EMIOS23_IN_PORT202;0:[!//
eMIOS_A_EMIOS23_IN_PORT483;1:[!//
[!ENDVAR!]

[!VAR "INMUX88"!]
eMIOS_B_EMIOS16_INOUT_PORT203;0:[!//
eMIOS_B_EMIOS16_IN_PORT203;0:[!//
eMIOS_B_EMIOS16_IN_PORT484;1:[!//
[!ENDVAR!]

[!VAR "INMUX89"!]
eMIOS_B_EMIOS17_INOUT_PORT204;0:[!//
eMIOS_B_EMIOS17_IN_PORT204;0:[!//
eMIOS_B_EMIOS17_IN_PORT485;1:[!//
[!ENDVAR!]

[!VAR "INMUX90"!]
eMIOS_B_EMIOS18_INOUT_PORT432;0:[!//
eMIOS_B_EMIOS18_IN_PORT432;0:[!//
eMIOS_B_EMIOS18_IN_PORT486;1:[!//
[!ENDVAR!]

[!VAR "INMUX91"!]
eMIOS_B_EMIOS19_INOUT_PORT433;0:[!//
eMIOS_B_EMIOS19_IN_PORT433;0:[!//
eMIOS_B_EMIOS19_IN_PORT487;1:[!//
[!ENDVAR!]

[!VAR "INMUX92"!]
eMIOS_B_EMIOS20_INOUT_PORT434;0:[!//
eMIOS_B_EMIOS20_IN_PORT434;0:[!//
eMIOS_B_EMIOS20_IN_PORT488;1:[!//
[!ENDVAR!]

[!VAR "INMUX93"!]
eMIOS_B_EMIOS21_INOUT_PORT435;0:[!//
eMIOS_B_EMIOS21_IN_PORT435;0:[!//
eMIOS_B_EMIOS21_IN_PORT489;1:[!//
[!ENDVAR!]

[!VAR "INMUX94"!]
eMIOS_B_EMIOS22_INOUT_PORT436;0:[!//
eMIOS_B_EMIOS22_IN_PORT436;0:[!//
eMIOS_B_EMIOS22_IN_PORT490;1:[!//
[!ENDVAR!]

[!VAR "INMUX95"!]
eMIOS_B_EMIOS23_INOUT_PORT437;0:[!//
eMIOS_B_EMIOS23_IN_PORT437;0:[!//
eMIOS_B_EMIOS23_IN_PORT491;1:[!//
[!ENDVAR!]

[!VAR "INMUX96"!]
[!ENDVAR!]

[!VAR "INMUX97"!]
[!ENDVAR!]

[!VAR "INMUX98"!]
[!ENDVAR!]

[!VAR "INMUX99"!]
[!ENDVAR!]

[!VAR "INMUX100"!]
[!ENDVAR!]

[!VAR "INMUX101"!]
[!ENDVAR!]

[!VAR "INMUX102"!]
[!ENDVAR!]

[!VAR "INMUX103"!]
[!ENDVAR!]

[!VAR "INMUX104"!]
[!ENDVAR!]

[!VAR "INMUX105"!]
[!ENDVAR!]

[!VAR "INMUX106"!]
[!ENDVAR!]

[!VAR "INMUX107"!]
[!ENDVAR!]

[!VAR "INMUX108"!]
[!ENDVAR!]

[!VAR "INMUX109"!]
[!ENDVAR!]

[!VAR "INMUX110"!]
[!ENDVAR!]

[!VAR "INMUX111"!]
[!ENDVAR!]

[!VAR "INMUX112"!]
[!ENDVAR!]

[!VAR "INMUX113"!]
[!ENDVAR!]

[!VAR "INMUX114"!]
[!ENDVAR!]

[!VAR "INMUX115"!]
[!ENDVAR!]

[!VAR "INMUX116"!]
[!ENDVAR!]

[!VAR "INMUX117"!]
[!ENDVAR!]

[!VAR "INMUX118"!]
[!ENDVAR!]

[!VAR "INMUX119"!]
[!ENDVAR!]

[!VAR "INMUX120"!]
eTPU_A_ETPUA24_INOUT_PORT138;0:[!//
eTPU_A_ETPUA24_IN_PORT138;0:[!//
eTPU_A_ETPUA24_IN_PORT483;1:[!//
[!ENDVAR!]

[!VAR "INMUX121"!]
eTPU_A_ETPUA25_INOUT_PORT139;0:[!//
eTPU_A_ETPUA25_IN_PORT139;0:[!//
eTPU_A_ETPUA25_IN_PORT482;1:[!//
[!ENDVAR!]

[!VAR "INMUX122"!]
eTPU_A_ETPUA26_INOUT_PORT140;0:[!//
eTPU_A_ETPUA26_IN_PORT140;0:[!//
eTPU_A_ETPUA26_IN_PORT481;1:[!//
[!ENDVAR!]

[!VAR "INMUX123"!]
eTPU_A_ETPUA27_INOUT_PORT141;0:[!//
eTPU_A_ETPUA27_IN_PORT141;0:[!//
eTPU_A_ETPUA27_IN_PORT480;1:[!//
[!ENDVAR!]

[!VAR "INMUX124"!]
eTPU_A_ETPUA28_INOUT_PORT142;0:[!//
eTPU_A_ETPUA28_IN_PORT142;0:[!//
eTPU_A_ETPUA28_IN_PORT479;1:[!//
[!ENDVAR!]

[!VAR "INMUX125"!]
eTPU_A_ETPUA29_INOUT_PORT143;0:[!//
eTPU_A_ETPUA29_IN_PORT143;0:[!//
eTPU_A_ETPUA29_IN_PORT478;1:[!//
[!ENDVAR!]

[!VAR "INMUX126"!]
eTPU_A_ETPUA30_INOUT_PORT144;0:[!//
eTPU_A_ETPUA30_IN_PORT144;0:[!//
eTPU_A_ETPUA30_IN_PORT477;1:[!//
[!ENDVAR!]

[!VAR "INMUX127"!]
eTPU_A_ETPUA31_INOUT_PORT145;0:[!//
eTPU_A_ETPUA31_IN_PORT145;0:[!//
eTPU_A_ETPUA31_IN_PORT476;1:[!//
[!ENDVAR!]

[!VAR "INMUX128"!]
[!ENDVAR!]

[!VAR "INMUX129"!]
[!ENDVAR!]

[!VAR "INMUX130"!]
[!ENDVAR!]

[!VAR "INMUX131"!]
[!ENDVAR!]

[!VAR "INMUX132"!]
[!ENDVAR!]

[!VAR "INMUX133"!]
[!ENDVAR!]

[!VAR "INMUX134"!]
[!ENDVAR!]

[!VAR "INMUX135"!]
[!ENDVAR!]

[!VAR "INMUX136"!]
[!ENDVAR!]

[!VAR "INMUX137"!]
[!ENDVAR!]

[!VAR "INMUX138"!]
[!ENDVAR!]

[!VAR "INMUX139"!]
[!ENDVAR!]

[!VAR "INMUX140"!]
[!ENDVAR!]

[!VAR "INMUX141"!]
[!ENDVAR!]

[!VAR "INMUX142"!]
[!ENDVAR!]

[!VAR "INMUX143"!]
[!ENDVAR!]

[!VAR "INMUX144"!]
[!ENDVAR!]

[!VAR "INMUX145"!]
[!ENDVAR!]

[!VAR "INMUX146"!]
[!ENDVAR!]

[!VAR "INMUX147"!]
[!ENDVAR!]

[!VAR "INMUX148"!]
[!ENDVAR!]

[!VAR "INMUX149"!]
[!ENDVAR!]

[!VAR "INMUX150"!]
[!ENDVAR!]

[!VAR "INMUX151"!]
[!ENDVAR!]

[!VAR "INMUX152"!]
[!ENDVAR!]

[!VAR "INMUX153"!]
[!ENDVAR!]

[!VAR "INMUX154"!]
[!ENDVAR!]

[!VAR "INMUX155"!]
[!ENDVAR!]

[!VAR "INMUX156"!]
[!ENDVAR!]

[!VAR "INMUX157"!]
[!ENDVAR!]

[!VAR "INMUX158"!]
[!ENDVAR!]

[!VAR "INMUX159"!]
[!ENDVAR!]

[!VAR "INMUX160"!]
eTPU_C_ETPUC0_INOUT_PORT212;1:[!//
eTPU_C_ETPUC0_IN_PORT212;1:[!//
eTPU_C_ETPUC0_IN_PORT441;0:[!//
[!ENDVAR!]

[!VAR "INMUX161"!]
eTPU_C_ETPUC1_INOUT_PORT213;1:[!//
eTPU_C_ETPUC1_IN_PORT213;1:[!//
eTPU_C_ETPUC1_IN_PORT442;0:[!//
[!ENDVAR!]

[!VAR "INMUX162"!]
[!ENDVAR!]

[!VAR "INMUX163"!]
eTPU_C_ETPUC3_INOUT_PORT210;1:[!//
eTPU_C_ETPUC3_IN_PORT210;1:[!//
eTPU_C_ETPUC3_IN_PORT444;0:[!//
[!ENDVAR!]

[!VAR "INMUX164"!]
[!ENDVAR!]

[!VAR "INMUX165"!]
[!ENDVAR!]

[!VAR "INMUX166"!]
[!ENDVAR!]

[!VAR "INMUX167"!]
[!ENDVAR!]

[!VAR "INMUX168"!]
eTPU_C_ETPUC8_INOUT_PORT449;0:[!//
eTPU_C_ETPUC8_IN_PORT449;0:[!//
eTPU_C_ETPUC8_IN_PORT491;1:[!//
[!ENDVAR!]

[!VAR "INMUX169"!]
eTPU_C_ETPUC9_INOUT_PORT208;2:[!//
eTPU_C_ETPUC9_IN_PORT208;2:[!//
eTPU_C_ETPUC9_IN_PORT450;0:[!//
eTPU_C_ETPUC9_IN_PORT490;1:[!//
[!ENDVAR!]

[!VAR "INMUX170"!]
eTPU_C_ETPUC10_INOUT_PORT451;0:[!//
eTPU_C_ETPUC10_IN_PORT451;0:[!//
eTPU_C_ETPUC10_IN_PORT489;1:[!//
[!ENDVAR!]

[!VAR "INMUX171"!]
eTPU_C_ETPUC11_INOUT_PORT452;0:[!//
eTPU_C_ETPUC11_IN_PORT452;0:[!//
eTPU_C_ETPUC11_IN_PORT488;1:[!//
[!ENDVAR!]

[!VAR "INMUX172"!]
eTPU_C_ETPUC12_INOUT_PORT453;0:[!//
eTPU_C_ETPUC12_IN_PORT453;0:[!//
eTPU_C_ETPUC12_IN_PORT487;1:[!//
[!ENDVAR!]

[!VAR "INMUX173"!]
eTPU_C_ETPUC13_INOUT_PORT454;0:[!//
eTPU_C_ETPUC13_IN_PORT454;0:[!//
eTPU_C_ETPUC13_IN_PORT486;1:[!//
[!ENDVAR!]

[!VAR "INMUX174"!]
eTPU_C_ETPUC14_INOUT_PORT455;0:[!//
eTPU_C_ETPUC14_IN_PORT455;0:[!//
eTPU_C_ETPUC14_IN_PORT485;1:[!//
[!ENDVAR!]

[!VAR "INMUX175"!]
eTPU_C_ETPUC15_INOUT_PORT456;0:[!//
eTPU_C_ETPUC15_IN_PORT456;0:[!//
eTPU_C_ETPUC15_IN_PORT484;1:[!//
[!ENDVAR!]

[!VAR "INMUX176"!]
[!ENDVAR!]

[!VAR "INMUX177"!]
[!ENDVAR!]

[!VAR "INMUX178"!]
[!ENDVAR!]

[!VAR "INMUX179"!]
[!ENDVAR!]

[!VAR "INMUX180"!]
[!ENDVAR!]

[!VAR "INMUX181"!]
[!ENDVAR!]

[!VAR "INMUX182"!]
[!ENDVAR!]

[!VAR "INMUX183"!]
[!ENDVAR!]

[!VAR "INMUX184"!]
[!ENDVAR!]

[!VAR "INMUX185"!]
[!ENDVAR!]

[!VAR "INMUX186"!]
[!ENDVAR!]

[!VAR "INMUX187"!]
[!ENDVAR!]

[!VAR "INMUX188"!]
[!ENDVAR!]

[!VAR "INMUX189"!]
[!ENDVAR!]

[!VAR "INMUX190"!]
[!ENDVAR!]

[!VAR "INMUX191"!]
[!ENDVAR!]

[!VAR "INMUX192"!]
[!ENDVAR!]

[!VAR "INMUX193"!]
[!ENDVAR!]

[!VAR "INMUX194"!]
eTPU_C_TCRCLKC_IN_PORT440;0:[!//
eTPU_C_TCRCLKC_IN_PORT445;1:[!//
[!ENDVAR!]


[!VAR "CHECK_1"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT75_GPIO | 
PORT76_GPIO | 
PORT77_GPIO | 
PORT78_GPIO | 
PORT79_GPIO */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  80 ...  95 : PORT80_GPIO | 
PORT81_GPIO | 
PORT82_GPIO | 
PORT83_GPIO | 
PORT84_GPIO | 
PORT85_GPIO | 
PORT86_GPIO | 
PORT87_GPIO | 
PORT88_GPIO | 
PORT89_GPIO | 
PORT90_GPIO | 
PORT91_GPIO | 
PORT92_GPIO | 
PORT93_GPIO | 
PORT94_GPIO | 
PORT95_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  96 ... 111 : PORT96_GPIO | 
PORT97_GPIO | 
PORT98_GPIO | 
PORT99_GPIO | 
PORT100_GPIO | 
PORT101_GPIO | 
PORT102_GPIO | 
PORT103_GPIO | 
PORT104_GPIO | 
PORT105_GPIO | 
PORT106_GPIO | 
PORT107_GPIO | 
PORT108_GPIO | 
PORT109_GPIO | 
PORT110_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT113_GPIO | 
PORT114_GPIO | 
PORT115_GPIO | 
PORT116_GPIO | 
PORT117_GPIO | 
PORT118_GPIO | 
PORT119_GPIO | 
PORT120_GPIO | 
PORT121_GPIO | 
PORT122_GPIO | 
PORT123_GPIO | 
PORT124_GPIO | 
PORT125_GPIO | 
PORT126_GPIO | 
PORT127_GPIO */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 128 ... 143 : PORT128_GPIO | 
PORT129_GPIO | 
PORT130_GPIO | 
PORT131_GPIO | 
PORT132_GPIO | 
PORT133_GPIO | 
PORT134_GPIO | 
PORT135_GPIO | 
PORT136_GPIO | 
PORT137_GPIO | 
PORT138_GPIO | 
PORT139_GPIO | 
PORT140_GPIO | 
PORT141_GPIO | 
PORT142_GPIO | 
PORT143_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_GPIO | 
PORT145_GPIO | 
PORT146_GPIO | 
PORT147_GPIO | 
PORT148_GPIO | 
PORT149_GPIO | 
PORT150_GPIO | 
PORT151_GPIO | 
PORT152_GPIO | 
PORT153_GPIO | 
PORT154_GPIO | 
PORT155_GPIO | 
PORT156_GPIO | 
PORT157_GPIO | 
PORT158_GPIO | 
PORT159_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 160 ... 175 : PORT160_GPIO | 
PORT161_GPIO | 
PORT162_GPIO | 
PORT163_GPIO | 
PORT164_GPIO | 
PORT165_GPIO | 
PORT166_GPIO | 
PORT167_GPIO | 
PORT168_GPIO | 
PORT169_GPIO | 
PORT170_GPIO | 
PORT171_GPIO | 
PORT172_GPIO | 
PORT173_GPIO | 
PORT174_GPIO | 
PORT175_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 176 ... 191 : PORT176_GPIO | 
PORT177_GPIO | 
PORT178_GPIO | 
PORT179_GPIO | 
PORT180_GPIO | 
PORT181_GPIO | 
PORT182_GPIO | 
PORT183_GPIO | 
PORT184_GPIO | 
PORT185_GPIO | 
PORT186_GPIO | 
PORT187_GPIO | 
PORT188_GPIO | 
PORT189_GPIO | 
PORT190_GPIO | 
PORT191_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 192 ... 207 : PORT192_GPIO | 
PORT193_GPIO | 
PORT194_GPIO | 
PORT195_GPIO | 
PORT196_GPIO | 
PORT197_GPIO | 
PORT198_GPIO | 
PORT199_GPIO | 
PORT200_GPIO | 
PORT201_GPIO | 
PORT202_GPIO | 
PORT203_GPIO | 
PORT204_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 : PORT208_GPIO | 
PORT209_GPIO | 
PORT210_GPIO | 
PORT212_GPIO | 
PORT213_GPIO | 
PORT214_GPIO | 
PORT219_GPIO | 
PORT220_GPIO | 
PORT221_GPIO | 
PORT222_GPIO | 
PORT223_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 224 ... 239 : PORT224_GPIO | 
PORT225_GPIO | 
PORT226_GPIO | 
PORT227_GPIO | 
PORT228_GPIO | 
PORT229_GPIO | 
PORT230_GPIO | 
PORT231_GPIO | 
PORT232_GPIO | 
PORT233_GPIO | 
PORT234_GPIO | 
PORT235_GPIO | 
PORT236_GPIO | 
PORT237_GPIO | 
PORT238_GPIO | 
PORT239_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 240 ... 255 : PORT240_GPIO | 
PORT241_GPIO | 
PORT242_GPIO | 
PORT243_GPIO | 
PORT244_GPIO | 
PORT245_GPIO | 
PORT246_GPIO | 
PORT247_GPIO | 
PORT248_GPIO | 
PORT249_GPIO | 
PORT250_GPIO | 
PORT251_GPIO | 
PORT252_GPIO | 
PORT253_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_GPIO | 
PORT433_GPIO | 
PORT434_GPIO | 
PORT435_GPIO | 
PORT436_GPIO | 
PORT437_GPIO | 
PORT440_GPI | 
PORT441_GPI | 
PORT442_GPI | 
PORT443_GPIO | 
PORT444_GPI | 
PORT445_GPIO | 
PORT446_GPIO | 
PORT447_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_GPIO | 
PORT449_GPIO | 
PORT450_GPI | 
PORT451_GPIO | 
PORT452_GPIO | 
PORT453_GPIO | 
PORT454_GPIO | 
PORT455_GPIO | 
PORT456_GPIO | 
PORT457_GPIO | 
PORT458_GPIO | 
PORT459_GPIO | 
PORT460_GPIO | 
PORT461_GPIO | 
PORT462_GPIO | 
PORT463_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 464 ... 479 : PORT464_GPIO | 
PORT465_GPIO | 
PORT466_GPIO | 
PORT467_GPIO | 
PORT468_GPIO | 
PORT469_GPIO | 
PORT470_GPIO | 
PORT471_GPIO | 
PORT472_GPIO | 
PORT474_GPI | 
PORT475_GPI | 
PORT476_GPI | 
PORT477_GPI | 
PORT478_GPI | 
PORT479_GPI */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_GPI | 
PORT481_GPI | 
PORT482_GPI | 
PORT483_GPI | 
PORT484_GPI | 
PORT485_GPI | 
PORT486_GPI | 
PORT487_GPI | 
PORT488_GPI | 
PORT489_GPI | 
PORT490_GPI | 
PORT491_GPI */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT83_FlexCAN_A_CNTXA | 
PORT84_FlexCAN_A_CNRXA | 
PORT85_FlexCAN_B_CNTXB | 
PORT86_FlexCAN_B_CNRXB | 
PORT87_FlexCAN_C_CNTXC | 
PORT88_FlexCAN_C_CNRXC | 
PORT93_DSPI_A_SCKA_OUT | 
PORT93_DSPI_A_SCKA_IN | 
PORT93_DSPI_A_SCKA_INOUT | 
PORT94_DSPI_A_SINA | 
PORT95_DSPI_A_SOUTA */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  96 ... 111 : PORT96_DSPI_A_PCSA0_OUT | 
PORT96_DSPI_A_PCSA0_IN | 
PORT96_DSPI_A_PCSA0_INOUT | 
PORT97_DSPI_A_PCSA1 | 
PORT98_DSPI_A_PCSA2 | 
PORT99_DSPI_A_PCSA3 | 
PORT100_DSPI_A_PCSA4 | 
PORT101_DSPI_A_PCSA5 | 
PORT102_DSPI_B_SCKB_INOUT | 
PORT102_DSPI_B_SCKB_OUT | 
PORT102_DSPI_B_SCKB_IN | 
PORT103_DSPI_B_SINB | 
PORT104_DSPI_B_SOUTB | 
PORT105_DSPI_B_PCSB0_OUT | 
PORT106_DSPI_B_PCSB1 | 
PORT107_DSPI_B_PCSB2 | 
PORT108_DSPI_B_PCSB3 | 
PORT109_DSPI_B_PCSB4 | 
PORT110_DSPI_B_PCSB5 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT113_eTPU_A_TCRCLKA | 
PORT114_eTPU_A_ETPUA0_INOUT | 
PORT114_eTPU_A_ETPUA0_OUT | 
PORT114_eTPU_A_ETPUA0_IN | 
PORT115_eTPU_A_ETPUA1_INOUT | 
PORT115_eTPU_A_ETPUA1_OUT | 
PORT115_eTPU_A_ETPUA1_IN | 
PORT116_eTPU_A_ETPUA2_INOUT | 
PORT116_eTPU_A_ETPUA2_OUT | 
PORT116_eTPU_A_ETPUA2_IN | 
PORT117_eTPU_A_ETPUA3_INOUT | 
PORT117_eTPU_A_ETPUA3_OUT | 
PORT117_eTPU_A_ETPUA3_IN | 
PORT118_eTPU_A_ETPUA4_INOUT | 
PORT118_eTPU_A_ETPUA4_OUT | 
PORT118_eTPU_A_ETPUA4_IN | 
PORT119_eTPU_A_ETPUA5_INOUT | 
PORT119_eTPU_A_ETPUA5_OUT | 
PORT119_eTPU_A_ETPUA5_IN | 
PORT120_eTPU_A_ETPUA6_INOUT | 
PORT120_eTPU_A_ETPUA6_OUT | 
PORT120_eTPU_A_ETPUA6_IN | 
PORT121_eTPU_A_ETPUA7_INOUT | 
PORT121_eTPU_A_ETPUA7_OUT | 
PORT121_eTPU_A_ETPUA7_IN | 
PORT122_eTPU_A_ETPUA8_INOUT | 
PORT122_eTPU_A_ETPUA8_OUT | 
PORT122_eTPU_A_ETPUA8_IN | 
PORT123_eTPU_A_ETPUA9_INOUT | 
PORT123_eTPU_A_ETPUA9_OUT | 
PORT123_eTPU_A_ETPUA9_IN | 
PORT124_eTPU_A_ETPUA10_INOUT | 
PORT124_eTPU_A_ETPUA10_OUT | 
PORT124_eTPU_A_ETPUA10_IN | 
PORT125_eTPU_A_ETPUA11_INOUT | 
PORT125_eTPU_A_ETPUA11_OUT | 
PORT125_eTPU_A_ETPUA11_IN | 
PORT126_eTPU_A_ETPUA12_INOUT | 
PORT126_eTPU_A_ETPUA12_OUT | 
PORT126_eTPU_A_ETPUA12_IN | 
PORT127_eTPU_A_ETPUA13_INOUT | 
PORT127_eTPU_A_ETPUA13_OUT | 
PORT127_eTPU_A_ETPUA13_IN */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 128 ... 143 : PORT128_eTPU_A_ETPUA14_INOUT | 
PORT128_eTPU_A_ETPUA14_OUT | 
PORT128_eTPU_A_ETPUA14_IN | 
PORT129_eTPU_A_ETPUA15_INOUT | 
PORT129_eTPU_A_ETPUA15_OUT | 
PORT129_eTPU_A_ETPUA15_IN | 
PORT130_eTPU_A_ETPUA16_INOUT | 
PORT130_eTPU_A_ETPUA16_OUT | 
PORT130_eTPU_A_ETPUA16_IN | 
PORT131_eTPU_A_ETPUA17_INOUT | 
PORT131_eTPU_A_ETPUA17_OUT | 
PORT131_eTPU_A_ETPUA17_IN | 
PORT132_eTPU_A_ETPUA18_INOUT | 
PORT132_eTPU_A_ETPUA18_OUT | 
PORT132_eTPU_A_ETPUA18_IN | 
PORT133_eTPU_A_ETPUA19_INOUT | 
PORT133_eTPU_A_ETPUA19_OUT | 
PORT133_eTPU_A_ETPUA19_IN | 
PORT134_eTPU_A_ETPUA20_INOUT | 
PORT134_eTPU_A_ETPUA20_OUT | 
PORT134_eTPU_A_ETPUA20_IN | 
PORT135_eTPU_A_ETPUA21_INOUT | 
PORT135_eTPU_A_ETPUA21_OUT | 
PORT135_eTPU_A_ETPUA21_IN | 
PORT136_eTPU_A_ETPUA22_INOUT | 
PORT136_eTPU_A_ETPUA22_OUT | 
PORT136_eTPU_A_ETPUA22_IN | 
PORT137_eTPU_A_ETPUA23_INOUT | 
PORT137_eTPU_A_ETPUA23_OUT | 
PORT137_eTPU_A_ETPUA23_IN | 
PORT138_eTPU_A_ETPUA24_OUT | 
PORT139_eTPU_A_ETPUA25_OUT | 
PORT140_eTPU_A_ETPUA26_OUT | 
PORT141_eTPU_A_ETPUA27_OUT | 
PORT142_eTPU_A_ETPUA28_OUT | 
PORT143_eTPU_A_ETPUA29_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_eTPU_A_ETPUA30_OUT | 
PORT145_eTPU_A_ETPUA31_OUT | 
PORT146_eTPU_B_TCRCLKB | 
PORT147_eTPU_B_ETPUB0_INOUT | 
PORT147_eTPU_B_ETPUB0_OUT | 
PORT147_eTPU_B_ETPUB0_IN | 
PORT148_eTPU_B_ETPUB1_INOUT | 
PORT148_eTPU_B_ETPUB1_OUT | 
PORT148_eTPU_B_ETPUB1_IN | 
PORT149_eTPU_B_ETPUB2_INOUT | 
PORT149_eTPU_B_ETPUB2_OUT | 
PORT149_eTPU_B_ETPUB2_IN | 
PORT150_eTPU_B_ETPUB3_INOUT | 
PORT150_eTPU_B_ETPUB3_OUT | 
PORT150_eTPU_B_ETPUB3_IN | 
PORT151_eTPU_B_ETPUB4_INOUT | 
PORT151_eTPU_B_ETPUB4_OUT | 
PORT151_eTPU_B_ETPUB4_IN | 
PORT152_eTPU_B_ETPUB5_INOUT | 
PORT152_eTPU_B_ETPUB5_OUT | 
PORT152_eTPU_B_ETPUB5_IN | 
PORT153_eTPU_B_ETPUB6_INOUT | 
PORT153_eTPU_B_ETPUB6_OUT | 
PORT153_eTPU_B_ETPUB6_IN | 
PORT154_eTPU_B_ETPUB7_INOUT | 
PORT154_eTPU_B_ETPUB7_OUT | 
PORT154_eTPU_B_ETPUB7_IN | 
PORT155_eTPU_B_ETPUB8_INOUT | 
PORT155_eTPU_B_ETPUB8_OUT | 
PORT155_eTPU_B_ETPUB8_IN | 
PORT156_eTPU_B_ETPUB9_INOUT | 
PORT156_eTPU_B_ETPUB9_OUT | 
PORT156_eTPU_B_ETPUB9_IN | 
PORT157_eTPU_B_ETPUB10_INOUT | 
PORT157_eTPU_B_ETPUB10_OUT | 
PORT157_eTPU_B_ETPUB10_IN | 
PORT158_eTPU_B_ETPUB11_INOUT | 
PORT158_eTPU_B_ETPUB11_OUT | 
PORT158_eTPU_B_ETPUB11_IN | 
PORT159_eTPU_B_ETPUB12_INOUT | 
PORT159_eTPU_B_ETPUB12_OUT | 
PORT159_eTPU_B_ETPUB12_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 160 ... 175 : PORT160_eTPU_B_ETPUB13_INOUT | 
PORT160_eTPU_B_ETPUB13_OUT | 
PORT160_eTPU_B_ETPUB13_IN | 
PORT161_eTPU_B_ETPUB14_INOUT | 
PORT161_eTPU_B_ETPUB14_OUT | 
PORT161_eTPU_B_ETPUB14_IN | 
PORT162_eTPU_B_ETPUB15_INOUT | 
PORT162_eTPU_B_ETPUB15_OUT | 
PORT162_eTPU_B_ETPUB15_IN | 
PORT163_eTPU_B_ETPUB16_INOUT | 
PORT163_eTPU_B_ETPUB16_OUT | 
PORT163_eTPU_B_ETPUB16_IN | 
PORT164_eTPU_B_ETPUB17_INOUT | 
PORT164_eTPU_B_ETPUB17_OUT | 
PORT164_eTPU_B_ETPUB17_IN | 
PORT165_eTPU_B_ETPUB18_INOUT | 
PORT165_eTPU_B_ETPUB18_OUT | 
PORT165_eTPU_B_ETPUB18_IN | 
PORT166_eTPU_B_ETPUB19_INOUT | 
PORT166_eTPU_B_ETPUB19_OUT | 
PORT166_eTPU_B_ETPUB19_IN | 
PORT167_eTPU_B_ETPUB20_INOUT | 
PORT167_eTPU_B_ETPUB20_OUT | 
PORT167_eTPU_B_ETPUB20_IN | 
PORT168_eTPU_B_ETPUB21_INOUT | 
PORT168_eTPU_B_ETPUB21_OUT | 
PORT168_eTPU_B_ETPUB21_IN | 
PORT169_eTPU_B_ETPUB22_INOUT | 
PORT169_eTPU_B_ETPUB22_OUT | 
PORT169_eTPU_B_ETPUB22_IN | 
PORT170_eTPU_B_ETPUB23_INOUT | 
PORT170_eTPU_B_ETPUB23_OUT | 
PORT170_eTPU_B_ETPUB23_IN | 
PORT171_eTPU_B_ETPUB24_INOUT | 
PORT171_eTPU_B_ETPUB24_OUT | 
PORT171_eTPU_B_ETPUB24_IN | 
PORT172_eTPU_B_ETPUB25_INOUT | 
PORT172_eTPU_B_ETPUB25_OUT | 
PORT172_eTPU_B_ETPUB25_IN | 
PORT173_eTPU_B_ETPUB26_INOUT | 
PORT173_eTPU_B_ETPUB26_OUT | 
PORT173_eTPU_B_ETPUB26_IN | 
PORT174_eTPU_B_ETPUB27_INOUT | 
PORT174_eTPU_B_ETPUB27_OUT | 
PORT174_eTPU_B_ETPUB27_IN | 
PORT175_eTPU_B_ETPUB28_INOUT | 
PORT175_eTPU_B_ETPUB28_OUT | 
PORT175_eTPU_B_ETPUB28_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 176 ... 191 : PORT176_eTPU_B_ETPUB29_INOUT | 
PORT176_eTPU_B_ETPUB29_OUT | 
PORT176_eTPU_B_ETPUB29_IN | 
PORT177_eTPU_B_ETPUB30_INOUT | 
PORT177_eTPU_B_ETPUB30_OUT | 
PORT177_eTPU_B_ETPUB30_IN | 
PORT178_eTPU_B_ETPUB31_INOUT | 
PORT178_eTPU_B_ETPUB31_OUT | 
PORT178_eTPU_B_ETPUB31_IN | 
PORT179_eMIOS_A_EMIOS0_INOUT | 
PORT179_eMIOS_A_EMIOS0_OUT | 
PORT179_eMIOS_A_EMIOS0_IN | 
PORT180_eMIOS_A_EMIOS1_INOUT | 
PORT180_eMIOS_A_EMIOS1_OUT | 
PORT180_eMIOS_A_EMIOS1_IN | 
PORT181_eMIOS_A_EMIOS2_INOUT | 
PORT181_eMIOS_A_EMIOS2_OUT | 
PORT181_eMIOS_A_EMIOS2_IN | 
PORT182_eMIOS_A_EMIOS3_INOUT | 
PORT182_eMIOS_A_EMIOS3_OUT | 
PORT182_eMIOS_A_EMIOS3_IN | 
PORT183_eMIOS_A_EMIOS4 | 
PORT184_eMIOS_A_EMIOS5 | 
PORT185_eMIOS_A_EMIOS6_INOUT | 
PORT185_eMIOS_A_EMIOS6_OUT | 
PORT185_eMIOS_A_EMIOS6_IN | 
PORT186_eMIOS_A_EMIOS7_INOUT | 
PORT186_eMIOS_A_EMIOS7_OUT | 
PORT186_eMIOS_A_EMIOS7_IN | 
PORT187_eMIOS_B_EMIOS0_INOUT | 
PORT187_eMIOS_B_EMIOS0_OUT | 
PORT187_eMIOS_B_EMIOS0_IN | 
PORT188_eMIOS_B_EMIOS1_INOUT | 
PORT188_eMIOS_B_EMIOS1_OUT | 
PORT188_eMIOS_B_EMIOS1_IN | 
PORT189_eMIOS_B_EMIOS2_INOUT | 
PORT189_eMIOS_B_EMIOS2_OUT | 
PORT189_eMIOS_B_EMIOS2_IN | 
PORT190_eMIOS_B_EMIOS3_INOUT | 
PORT190_eMIOS_B_EMIOS3_OUT | 
PORT190_eMIOS_B_EMIOS3_IN | 
PORT191_eMIOS_B_EMIOS4_INOUT | 
PORT191_eMIOS_B_EMIOS4_OUT | 
PORT191_eMIOS_B_EMIOS4_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 192 ... 207 : PORT192_eMIOS_B_EMIOS5_INOUT | 
PORT192_eMIOS_B_EMIOS5_OUT | 
PORT192_eMIOS_B_EMIOS5_IN | 
PORT193_eMIOS_B_EMIOS6 | 
PORT194_eMIOS_B_EMIOS7 | 
PORT195_eMIOS_A_EMIOS16_OUT | 
PORT196_eMIOS_A_EMIOS17_OUT | 
PORT197_eMIOS_A_EMIOS18_OUT | 
PORT198_eMIOS_A_EMIOS19_OUT | 
PORT199_eMIOS_A_EMIOS20_OUT | 
PORT200_eMIOS_A_EMIOS21_OUT | 
PORT201_eMIOS_A_EMIOS22_OUT | 
PORT202_eMIOS_A_EMIOS23_OUT | 
PORT203_eMIOS_B_EMIOS16_OUT | 
PORT204_eMIOS_B_EMIOS17_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 : PORT208_SoC_PLLCFG0_IN | 
PORT209_SoC_PLLCFG1_IN | 
PORT210_SoC_PLLCFG2_IN | 
PORT212_SoC_BOOTCFG1_IN | 
PORT213_SoC_WKPCFG_IN | 
PORT214_ENGCLK | 
PORT219_MCKO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(11U)
          ),
/* Pads 224 ... 239 : PORT224_MSEO0 | 
PORT225_MSEO1 | 
PORT226_RDY | 
PORT227_EVTO | 
PORT228_TDO | 
PORT229_D_CLKOUT | 
PORT230_RSTOUT | 
PORT235_DSPI_C_SCKC_OUT | 
PORT237_DSPI_C_SOUTC | 
PORT238_DSPI_C_PCSC0_OUT | 
PORT239_DSPI_C_PCSC1 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 240 ... 255 : PORT240_DSPI_C_PCSC2 | 
PORT241_DSPI_C_PCSC3 | 
PORT242_DSPI_C_PCSC4 | 
PORT243_DSPI_C_PCSC5 | 
PORT244_eSCI_C_TXDC | 
PORT245_eSCI_C_RXDC_IN | 
PORT246_FlexCAN_D_CNTXD | 
PORT248_FEC_FEC_TXD0_OUT | 
PORT249_FEC_FEC_RX_DV_IN | 
PORT250_FEC_FEC_RXD0_IN | 
PORT251_FEC_FEC_TXD1_OUT | 
PORT252_FEC_FEC_TXEN_OUT | 
PORT253_FEC_FEC_RXD1_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_eMIOS_B_EMIOS18_OUT | 
PORT433_eMIOS_B_EMIOS19_OUT | 
PORT434_eMIOS_B_EMIOS20_OUT | 
PORT435_eMIOS_B_EMIOS21_OUT | 
PORT436_eMIOS_B_EMIOS22_OUT | 
PORT437_eMIOS_B_EMIOS23_OUT | 
PORT443_eTPU_C_ETPUC2_INOUT | 
PORT443_eTPU_C_ETPUC2_OUT | 
PORT443_eTPU_C_ETPUC2_IN | 
PORT445_eTPU_C_ETPUC4_INOUT | 
PORT445_eTPU_C_ETPUC4_OUT | 
PORT445_eTPU_C_ETPUC4_IN | 
PORT446_eTPU_C_ETPUC5_INOUT | 
PORT446_eTPU_C_ETPUC5_OUT | 
PORT446_eTPU_C_ETPUC5_IN | 
PORT447_eTPU_C_ETPUC6_INOUT | 
PORT447_eTPU_C_ETPUC6_OUT | 
PORT447_eTPU_C_ETPUC6_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_eTPU_C_ETPUC7_INOUT | 
PORT448_eTPU_C_ETPUC7_OUT | 
PORT448_eTPU_C_ETPUC7_IN | 
PORT449_eTPU_C_ETPUC8_OUT | 
PORT451_eTPU_C_ETPUC10_OUT | 
PORT452_eTPU_C_ETPUC11_OUT | 
PORT453_eTPU_C_ETPUC12_OUT | 
PORT454_eTPU_C_ETPUC13_OUT | 
PORT455_eTPU_C_ETPUC14_OUT | 
PORT456_eTPU_C_ETPUC15_OUT | 
PORT457_eTPU_C_ETPUC16_INOUT | 
PORT457_eTPU_C_ETPUC16_OUT | 
PORT457_eTPU_C_ETPUC16_IN | 
PORT458_eTPU_C_ETPUC17_INOUT | 
PORT458_eTPU_C_ETPUC17_OUT | 
PORT458_eTPU_C_ETPUC17_IN | 
PORT459_eTPU_C_ETPUC18_INOUT | 
PORT459_eTPU_C_ETPUC18_OUT | 
PORT459_eTPU_C_ETPUC18_IN | 
PORT460_eTPU_C_ETPUC19_INOUT | 
PORT460_eTPU_C_ETPUC19_OUT | 
PORT460_eTPU_C_ETPUC19_IN | 
PORT461_eTPU_C_ETPUC20_INOUT | 
PORT461_eTPU_C_ETPUC20_OUT | 
PORT461_eTPU_C_ETPUC20_IN | 
PORT462_eTPU_C_ETPUC21_INOUT | 
PORT462_eTPU_C_ETPUC21_OUT | 
PORT462_eTPU_C_ETPUC21_IN | 
PORT463_eTPU_C_ETPUC22_INOUT | 
PORT463_eTPU_C_ETPUC22_OUT | 
PORT463_eTPU_C_ETPUC22_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 464 ... 479 : PORT464_eTPU_C_ETPUC23_INOUT | 
PORT464_eTPU_C_ETPUC23_OUT | 
PORT464_eTPU_C_ETPUC23_IN | 
PORT465_eTPU_C_ETPUC24_INOUT | 
PORT465_eTPU_C_ETPUC24_OUT | 
PORT465_eTPU_C_ETPUC24_IN | 
PORT466_eTPU_C_ETPUC25_INOUT | 
PORT466_eTPU_C_ETPUC25_OUT | 
PORT466_eTPU_C_ETPUC25_IN | 
PORT467_eTPU_C_ETPUC26_INOUT | 
PORT467_eTPU_C_ETPUC26_OUT | 
PORT467_eTPU_C_ETPUC26_IN | 
PORT468_eTPU_C_ETPUC27_INOUT | 
PORT468_eTPU_C_ETPUC27_OUT | 
PORT468_eTPU_C_ETPUC27_IN | 
PORT469_eTPU_C_ETPUC28_INOUT | 
PORT469_eTPU_C_ETPUC28_OUT | 
PORT469_eTPU_C_ETPUC28_IN | 
PORT470_eTPU_C_ETPUC29_INOUT | 
PORT470_eTPU_C_ETPUC29_OUT | 
PORT470_eTPU_C_ETPUC29_IN | 
PORT471_eTPU_C_ETPUC30_INOUT | 
PORT471_eTPU_C_ETPUC30_OUT | 
PORT471_eTPU_C_ETPUC30_IN | 
PORT472_eTPU_C_ETPUC31_INOUT | 
PORT472_eTPU_C_ETPUC31_OUT | 
PORT472_eTPU_C_ETPUC31_IN | 
PORT474_FEC_FEC_TXCLK_REFCLK_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(10U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT85_DSPI_C_PCSC3 | 
PORT86_DSPI_C_PCSC4 | 
PORT87_DSPI_D_PCSD3 | 
PORT88_DSPI_D_PCSD4 | 
PORT91_DSPI_D_PCSD1 | 
PORT92_DSPI_D_PCSD5 | 
PORT93_DSPI_C_PCSC1 | 
PORT94_DSPI_C_PCSC2 | 
PORT95_DSPI_C_PCSC5 */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  96 ... 111 : PORT96_DSPI_D_PCSD2 | 
PORT97_DSPI_E_PCSE0_OUT | 
PORT97_DSPI_E_PCSE0_IN | 
PORT97_DSPI_E_PCSE0_INOUT | 
PORT98_DSPI_E_SOUTE | 
PORT99_DSPI_E_SINE | 
PORT100_DSPI_E_SCKE_OUT | 
PORT100_DSPI_E_SCKE_IN | 
PORT100_DSPI_E_SCKE_INOUT | 
PORT101_eQADC_A_eQADC_B_ETRIG1 | 
PORT105_DSPI_D_PCSD2 | 
PORT106_DSPI_D_PCSD0_OUT | 
PORT107_DSPI_C_SOUTC | 
PORT109_DSPI_C_SCKC_OUT | 
PORT110_DSPI_C_PCSC0_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT113_SIU_A_IRQ7 | 
PORT114_eTPU_A_ETPUA12 | 
PORT115_eTPU_A_ETPUA13 | 
PORT116_eTPU_A_ETPUA14 | 
PORT117_eTPU_A_ETPUA15 | 
PORT118_eTPU_A_ETPUA16 | 
PORT119_eTPU_A_ETPUA17 | 
PORT120_eTPU_A_ETPUA18 | 
PORT121_eTPU_A_ETPUA19 | 
PORT122_eTPU_A_ETPUA20 | 
PORT123_eTPU_A_ETPUA21 | 
PORT124_eTPU_A_ETPUA22 | 
PORT125_eTPU_A_ETPUA23 | 
PORT126_DSPI_B_PCSB1 | 
PORT127_DSPI_B_PCSB3 */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 128 ... 143 : PORT128_DSPI_B_PCSB4 | 
PORT129_DSPI_B_PCSB5 | 
PORT130_DSPI_D_PCSD1 | 
PORT131_DSPI_D_PCSD2 | 
PORT132_DSPI_D_PCSD3 | 
PORT133_DSPI_D_PCSD4 | 
PORT134_SIU_A_IRQ8 | 
PORT135_SIU_A_IRQ9 | 
PORT136_SIU_A_IRQ10 | 
PORT137_SIU_A_IRQ11 | 
PORT138_SIU_A_IRQ12 | 
PORT139_SIU_A_IRQ13 | 
PORT140_SIU_A_IRQ14 | 
PORT141_SIU_A_IRQ15 | 
PORT142_DSPI_C_PCSC1 | 
PORT143_DSPI_C_PCSC2 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_DSPI_C_PCSC3 | 
PORT145_DSPI_C_PCSC4 | 
PORT147_eTPU_B_ETPUB16 | 
PORT148_eTPU_B_ETPUB17 | 
PORT149_eTPU_B_ETPUB18 | 
PORT150_eTPU_B_ETPUB19 | 
PORT151_eTPU_B_ETPUB20 | 
PORT152_eTPU_B_ETPUB21 | 
PORT153_eTPU_B_ETPUB22 | 
PORT154_eTPU_B_ETPUB23 | 
PORT155_eTPU_B_ETPUB24 | 
PORT156_eTPU_B_ETPUB25 | 
PORT157_eTPU_B_ETPUB26 | 
PORT158_eTPU_B_ETPUB27 | 
PORT159_eTPU_B_ETPUB28 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 160 ... 175 : PORT160_eTPU_B_ETPUB29 | 
PORT161_eTPU_B_ETPUB30 | 
PORT162_eTPU_B_ETPUB31 | 
PORT163_DSPI_A_PCSA1 | 
PORT164_DSPI_A_PCSA2 | 
PORT165_DSPI_A_PCSA3 | 
PORT166_DSPI_A_PCSA4 | 
PORT169_REACM_RCH0_B_OUT | 
PORT170_REACM_RCH1_B_OUT | 
PORT171_REACM_RCH2_B_OUT | 
PORT172_REACM_RCH3_B_OUT | 
PORT173_REACM_RCH4_B_OUT | 
PORT174_REACM_RCH5_B_OUT | 
PORT175_REACM_RCH6_B_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 176 ... 191 : PORT176_REACM_RCH7_B_OUT | 
PORT177_REACM_RCH8_B_OUT | 
PORT178_REACM_RCH9_B_OUT | 
PORT179_eTPU_A_ETPUA0 | 
PORT180_eTPU_A_ETPUA1 | 
PORT181_eTPU_A_ETPUA2 | 
PORT182_eTPU_A_ETPUA3 | 
PORT183_eTPU_A_ETPUA4 | 
PORT184_eTPU_A_ETPUA5 | 
PORT185_eTPU_A_ETPUA6 | 
PORT186_eTPU_A_ETPUA7 | 
PORT187_eTPU_A_ETPUA8 | 
PORT188_eTPU_A_ETPUA9 | 
PORT189_DSPI_D_SCKD_OUT | 
PORT191_DSPI_C_SOUTC */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 192 ... 207 : PORT192_DSPI_D_SOUTD | 
PORT195_eTPU_B_ETPUB0 | 
PORT196_eTPU_B_ETPUB1 | 
PORT197_eTPU_B_ETPUB2 | 
PORT198_eTPU_B_ETPUB3 | 
PORT199_eTPU_B_ETPUB4 | 
PORT200_eTPU_B_ETPUB5 | 
PORT201_eTPU_B_ETPUB6 | 
PORT202_eTPU_B_ETPUB7 | 
PORT203_DSPI_B_PCSB0_OUT | 
PORT204_DSPI_B_PCSB1 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 : PORT210_eTPU_C_ETPUC3_OUT | 
PORT213_SIU_A_NMI_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 : PORT235_DSPI_C_SCK_C_LVDS_P | 
PORT236_DSPI_C_SCK_C_LVDS_N_OUT | 
PORT237_DSPI_C_SOUT_C_LVDS_P | 
PORT238_DSPI_C_SOUT_C_LVDS_N_OUT | 
PORT239_eSCI_D_TXDD */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 240 ... 255 : PORT240_DSPI_D_SCK_D_LVDS_P | 
PORT241_DSPI_D_SCK_D_LVDS_N_OUT | 
PORT242_MCAN_0_TX_OUT | 
PORT244_eQADC_A_eQADC_B_ETRIG0_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_DSPI_B_PCSB2 | 
PORT433_DSPI_B_PCSB3 | 
PORT434_DSPI_C_PCSC0_OUT | 
PORT435_DSPI_C_PCSC1 | 
PORT436_DSPI_C_PCSC2 | 
PORT437_DSPI_C_PCSC5 | 
PORT446_DSPI_E_PCSE2 | 
PORT447_DSPI_E_PCSE3 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_DSPI_E_PCSE4 | 
PORT449_DSPI_E_PCSE5 | 
PORT457_MCAN_1_TX_OUT | 
PORT458_eSCI_F_TXDF | 
PORT459_eSCI_F_RXDF_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          ),
/* Pads 464 ... 479 : PORT464_DSPI_D_PCSD5 | 
PORT465_DSPI_D_PCSD4 | 
PORT466_DSPI_D_PCSD3 | 
PORT467_DSPI_D_PCSD2 | 
PORT468_DSPI_D_PCSD1 | 
PORT469_DSPI_D_PCSD0_OUT | 
PORT470_DSPI_D_SCKD_OUT | 
PORT471_DSPI_D_SOUTD */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT83_MCAN_0_TX_OUT | 
PORT88_eSCI_E_RXDE | 
PORT93_MCAN_0_TX_OUT */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(13U)
          ),
/* Pads  96 ... 111 : PORT98_FEC_FEC_TXD2_OUT | 
PORT99_FEC_FEC_MDIO | 
PORT101_eSCI_D_RXDD */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 112 ... 127 : PORT116_REACM_RCH0_A_OUT | 
PORT117_REACM_RCH1_A_OUT | 
PORT118_REACM_RCH2_A_OUT | 
PORT119_REACM_RCH3_A_OUT | 
PORT120_REACM_RCH4_A_OUT | 
PORT121_REACM_RCH5_A_OUT | 
PORT122_REACM_RCH6_A_OUT | 
PORT123_REACM_RCH7_A_OUT | 
PORT124_REACM_RCH8_A_OUT | 
PORT125_REACM_RCH9_A_OUT */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 128 ... 143 : PORT129_MCAN_0_TX_OUT | 
PORT136_REACM_RCH0_A_OUT | 
PORT137_REACM_RCH1_A_OUT | 
PORT138_REACM_RCH2_A_OUT | 
PORT139_REACM_RCH3_A_OUT | 
PORT140_REACM_RCH4_A_OUT | 
PORT141_REACM_RCH5_A_OUT | 
PORT142_REACM_RCH6_A_OUT | 
PORT143_REACM_RCH7_A_OUT */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_REACM_RCH8_A_OUT | 
PORT145_REACM_RCH9_A_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT179_REACM_RCH0_C_OUT | 
PORT180_REACM_RCH1_C_OUT | 
PORT181_REACM_RCH2_C_OUT | 
PORT182_REACM_RCH3_C_OUT | 
PORT183_REACM_RCH4_C_OUT | 
PORT184_REACM_RCH5_C_OUT | 
PORT185_REACM_RCH6_C_OUT | 
PORT186_REACM_RCH7_C_OUT | 
PORT187_REACM_RCH8_C_OUT | 
PORT188_REACM_RCH9_C_OUT */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 192 ... 207 : PORT193_FlexCAN_D_CNTXD | 
PORT195_MCAN_1_TX_OUT | 
PORT197_REACM_RCH4_C_OUT | 
PORT198_REACM_RCH5_C_OUT | 
PORT199_REACM_RCH6_C_OUT | 
PORT200_REACM_RCH7_C_OUT | 
PORT201_REACM_RCH8_C_OUT | 
PORT202_REACM_RCH9_C_OUT */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U)
          ),
/* Pads 208 ... 223 : PORT208_eTPU_C_ETPUC9_OUT | 
PORT209_DSPI_D_SOUTD | 
PORT210_DSPI_E_PCSE1 | 
PORT212_eTPU_C_ETPUC0_OUT | 
PORT213_eTPU_C_ETPUC1_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT240_DSPI_D_SCKD_OUT | 
PORT242_DSPI_D_SOUT_D_LVDS_P | 
PORT243_DSPI_D_SOUT_D_LVDS_N_OUT | 
PORT246_MCAN_1_TX_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(6U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 */
  (uint16)0x0000,
/* Pads 448 ... 463 : PORT453_MCAN_1_TX_OUT | 
PORT454_PSI5A_SDOUT0_PSI5A_OUT | 
PORT455_PSI5A_SDIN0_PSI5A_IN | 
PORT456_REACM_RCH2_C_OUT | 
PORT457_REACM_RCH3_C_OUT | 
PORT458_REACM_RCH4_C_OUT | 
PORT460_PSI5A_SDOUT0_PSI5B_OUT | 
PORT461_PSI5A_SDIN0_PSI5B_IN */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 464 ... 479 : PORT464_eQADC_A_MAA0 | 
PORT465_eQADC_A_MAA1 | 
PORT466_eQADC_A_MAA2 | 
PORT467_eQADC_B_MAB0 | 
PORT468_REACM_RCH5_C_OUT | 
PORT469_REACM_RCH6_C_OUT | 
PORT470_REACM_RCH7_C_OUT | 
PORT471_REACM_RCH8_C_OUT | 
PORT472_REACM_RCH9_C_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT98_FEC_FEC_RXER_IN | 
PORT99_eSCI_D_TXDD | 
PORT100_FEC_FEC_RXCLK_IN | 
PORT101_FEC_FEC_TXD3_OUT | 
PORT107_FEC_FEC_RXD3_IN | 
PORT109_FEC_FEC_MDC_OUT | 
PORT110_FEC_FEC_RXD2_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT117_FCCU_ERROR0 | 
PORT124_FCCU_ERRORIN | 
PORT125_FCCU_ERROR1 */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT180_DSPI_E_PCSE2 | 
PORT181_DSPI_E_PCSE3 | 
PORT182_DSPI_E_PCSE4 | 
PORT183_DSPI_E_PCSE5 */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 192 ... 207 : PORT193_REACM_RCH0_C_OUT | 
PORT194_REACM_RCH1_C_OUT | 
PORT195_REACM_RCH2_C_OUT | 
PORT196_REACM_RCH3_C_OUT */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U)
          ),
/* Pads 208 ... 223 : PORT208_SIPI_TXN | 
PORT209_SIPI_TXP | 
PORT210_SIPI_REFCLK_INOUT | 
PORT210_SIPI_REFCLK_OUT | 
PORT210_SIPI_REFCLK_IN | 
PORT212_SIPI_RXP | 
PORT213_SIPI_RXN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT242_DSPI_D_SOUTD | 
PORT243_DSPI_D_PCSD0_OUT */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 */
  (uint16)0x0000,
/* Pads 448 ... 463 : PORT454_REACM_RCH0_C_OUT | 
PORT455_REACM_RCH1_C_OUT */
  (uint16)( SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 464 ... 479 : PORT464_eQADC_B_MAB0 | 
PORT465_eQADC_B_MAB1 | 
PORT466_eQADC_B_MAB2 | 
PORT468_eQADC_B_MAB1 | 
PORT469_eQADC_B_MAB2 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT89_eSCI_A_TXDA | 
PORT90_eSCI_A_RXDA_IN | 
PORT91_eSCI_B_TXDB | 
PORT92_eSCI_B_RXDB */
  (uint16)( SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads  96 ... 111 : PORT105_DSPI_B_PCSB0_INOUT | 
PORT105_DSPI_B_PCSB0_IN */
  (uint16)( SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT138_eTPU_A_ETPUA24_INOUT | 
PORT138_eTPU_A_ETPUA24_IN | 
PORT139_eTPU_A_ETPUA25_INOUT | 
PORT139_eTPU_A_ETPUA25_IN | 
PORT140_eTPU_A_ETPUA26_INOUT | 
PORT140_eTPU_A_ETPUA26_IN | 
PORT141_eTPU_A_ETPUA27_INOUT | 
PORT141_eTPU_A_ETPUA27_IN | 
PORT142_eTPU_A_ETPUA28_INOUT | 
PORT142_eTPU_A_ETPUA28_IN | 
PORT143_eTPU_A_ETPUA29_INOUT | 
PORT143_eTPU_A_ETPUA29_IN */
  (uint16)( SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_eTPU_A_ETPUA30_INOUT | 
PORT144_eTPU_A_ETPUA30_IN | 
PORT145_eTPU_A_ETPUA31_INOUT | 
PORT145_eTPU_A_ETPUA31_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT195_eMIOS_A_EMIOS16_INOUT | 
PORT195_eMIOS_A_EMIOS16_IN | 
PORT196_eMIOS_A_EMIOS17_INOUT | 
PORT196_eMIOS_A_EMIOS17_IN | 
PORT197_eMIOS_A_EMIOS18_INOUT | 
PORT197_eMIOS_A_EMIOS18_IN | 
PORT198_eMIOS_A_EMIOS19_INOUT | 
PORT198_eMIOS_A_EMIOS19_IN | 
PORT199_eMIOS_A_EMIOS20_INOUT | 
PORT199_eMIOS_A_EMIOS20_IN | 
PORT200_eMIOS_A_EMIOS21_INOUT | 
PORT200_eMIOS_A_EMIOS21_IN | 
PORT201_eMIOS_A_EMIOS22_INOUT | 
PORT201_eMIOS_A_EMIOS22_IN | 
PORT202_eMIOS_A_EMIOS23_INOUT | 
PORT202_eMIOS_A_EMIOS23_IN | 
PORT203_eMIOS_B_EMIOS16_INOUT | 
PORT203_eMIOS_B_EMIOS16_IN | 
PORT204_eMIOS_B_EMIOS17_INOUT | 
PORT204_eMIOS_B_EMIOS17_IN */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT235_DSPI_C_SCKC_INOUT | 
PORT235_DSPI_C_SCKC_IN | 
PORT236_DSPI_C_SINC_IN | 
PORT238_DSPI_C_PCSC0_INOUT | 
PORT238_DSPI_C_PCSC0_IN */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 240 ... 255 : PORT247_FlexCAN_D_CNRXD_IN */
  (uint16)( SHL_PAD_U32(7U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_eMIOS_B_EMIOS18_INOUT | 
PORT432_eMIOS_B_EMIOS18_IN | 
PORT433_eMIOS_B_EMIOS19_INOUT | 
PORT433_eMIOS_B_EMIOS19_IN | 
PORT434_eMIOS_B_EMIOS20_INOUT | 
PORT434_eMIOS_B_EMIOS20_IN | 
PORT435_eMIOS_B_EMIOS21_INOUT | 
PORT435_eMIOS_B_EMIOS21_IN | 
PORT436_eMIOS_B_EMIOS22_INOUT | 
PORT436_eMIOS_B_EMIOS22_IN | 
PORT437_eMIOS_B_EMIOS23_INOUT | 
PORT437_eMIOS_B_EMIOS23_IN | 
PORT440_eTPU_C_TCRCLKC_IN | 
PORT441_eTPU_C_ETPUC0_IN | 
PORT442_eTPU_C_ETPUC1_IN | 
PORT444_eTPU_C_ETPUC3_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 448 ... 463 : PORT449_eTPU_C_ETPUC8_INOUT | 
PORT449_eTPU_C_ETPUC8_IN | 
PORT450_eTPU_C_ETPUC9_IN | 
PORT451_eTPU_C_ETPUC10_INOUT | 
PORT451_eTPU_C_ETPUC10_IN | 
PORT452_eTPU_C_ETPUC11_INOUT | 
PORT452_eTPU_C_ETPUC11_IN | 
PORT453_eTPU_C_ETPUC12_INOUT | 
PORT453_eTPU_C_ETPUC12_IN | 
PORT454_eTPU_C_ETPUC13_INOUT | 
PORT454_eTPU_C_ETPUC13_IN | 
PORT455_eTPU_C_ETPUC14_INOUT | 
PORT455_eTPU_C_ETPUC14_IN | 
PORT456_eTPU_C_ETPUC15_INOUT | 
PORT456_eTPU_C_ETPUC15_IN */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U)
          ),
/* Pads 464 ... 479 : PORT475_SENT_A_SENT2_A_IN */
  (uint16)( SHL_PAD_U32(11U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT83_eSCI_A_TXDA | 
PORT84_eSCI_A_RXDA */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U)
          ),
/* Pads  96 ... 111 : PORT106_DSPI_D_PCSD0_INOUT | 
PORT106_DSPI_D_PCSD0_IN | 
PORT108_DSPI_C_SINC | 
PORT109_DSPI_C_SCKC_INOUT | 
PORT109_DSPI_C_SCKC_IN | 
PORT110_DSPI_C_PCSC0_INOUT | 
PORT110_DSPI_C_PCSC0_IN */
  (uint16)( SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SIU_A_IRQ6 */
  (uint16)( SHL_PAD_U32(2U)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT189_DSPI_D_SCKD_INOUT | 
PORT189_DSPI_D_SCKD_IN | 
PORT190_DSPI_D_SIND */
  (uint16)( SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 192 ... 207 : PORT193_SIU_A_IRQ0 | 
PORT194_SIU_A_IRQ1_IN | 
PORT203_DSPI_B_PCSB0_INOUT | 
PORT203_DSPI_B_PCSB0_IN */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U)
          ),
/* Pads 208 ... 223 : PORT208_SIU_A_IRQ4_IN | 
PORT209_SIU_A_IRQ5_IN | 
PORT210_eTPU_C_ETPUC3_INOUT | 
PORT210_eTPU_C_ETPUC3_IN | 
PORT212_SIU_A_IRQ3_IN | 
PORT223_eSCI_E_TXDE */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT243_MCAN_0_RX_IN | 
PORT248_SENT_A_SENT0_A_IN | 
PORT249_SENT_A_SENT1_A_IN | 
PORT250_SENT_A_SENT2_A_IN | 
PORT251_SENT_A_SENT3_A_IN | 
PORT252_SENT_A_SENT4_A_IN | 
PORT253_SENT_A_SENT5_A_IN */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT434_DSPI_C_PCSC0_INOUT | 
PORT434_DSPI_C_PCSC0_IN | 
PORT440_SIU_A_IRQ6_IN | 
PORT441_SENT_A_SENT0_A_IN | 
PORT442_SENT_A_SENT1_A_IN | 
PORT443_SENT_A_SENT3_A_IN | 
PORT444_SENT_A_SENT4_A_IN | 
PORT445_SENT_A_SENT5_A_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 448 ... 463 : PORT450_SIU_A_IRQ0_IN | 
PORT451_SIU_A_IRQ1_IN | 
PORT452_SIU_A_IRQ2_IN | 
PORT453_SIU_A_IRQ3_IN | 
PORT454_SIU_A_IRQ4_IN | 
PORT455_SIU_A_IRQ5_IN | 
PORT456_MCAN_1_RX_IN | 
PORT460_eSCI_A_TXDA | 
PORT461_eSCI_A_RXDA_IN | 
PORT462_eSCI_B_TXDB | 
PORT463_eSCI_B_RXDB_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 464 ... 479 : PORT469_DSPI_D_PCSD0_INOUT | 
PORT469_DSPI_D_PCSD0_IN | 
PORT470_DSPI_D_SCKD_INOUT | 
PORT470_DSPI_D_SCKD_IN | 
PORT472_DSPI_D_SIND_IN | 
PORT474_SENT_B_SENT0_B_IN | 
PORT476_eTPU_A_ETPUA31_IN | 
PORT477_eTPU_A_ETPUA30_IN | 
PORT478_eTPU_A_ETPUA29_IN | 
PORT479_eTPU_A_ETPUA28_IN */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_eTPU_A_ETPUA27_IN | 
PORT481_eTPU_A_ETPUA26_IN | 
PORT482_eTPU_A_ETPUA25_IN | 
PORT483_eTPU_A_ETPUA24_IN | 
PORT484_eTPU_C_ETPUC15_IN | 
PORT485_eTPU_C_ETPUC14_IN | 
PORT486_eTPU_C_ETPUC13_IN | 
PORT487_eTPU_C_ETPUC12_IN | 
PORT488_eTPU_C_ETPUC11_IN | 
PORT489_eTPU_C_ETPUC10_IN | 
PORT490_eTPU_C_ETPUC9_IN | 
PORT491_eTPU_C_ETPUC8_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT84_MCAN_0_RX_IN | 
PORT91_MCAN_0_RX_IN */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(11U)
          ),
/* Pads  96 ... 111 : PORT100_eSCI_E_TXDE | 
PORT107_SENT_B_SENT2_B_IN | 
PORT108_SENT_B_SENT3_B_IN | 
PORT109_SENT_B_SENT4_B_IN | 
PORT110_SENT_B_SENT5_B_IN */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT133_MCAN_0_RX_IN */
  (uint16)( SHL_PAD_U32(5U)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT194_FlexCAN_D_CNRXD_IN | 
PORT196_MCAN_1_RX_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U)
          ),
/* Pads 208 ... 223 : PORT208_eTPU_C_ETPUC9_INOUT | 
PORT208_eTPU_C_ETPUC9_IN | 
PORT212_eTPU_C_ETPUC0_INOUT | 
PORT212_eTPU_C_ETPUC0_IN | 
PORT213_eTPU_C_ETPUC1_INOUT | 
PORT213_eTPU_C_ETPUC1_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT240_DSPI_D_SCKD_INOUT | 
PORT240_DSPI_D_SCKD_IN | 
PORT241_DSPI_D_SIND_IN | 
PORT247_MCAN_1_RX_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT445_eTPU_C_TCRCLKC_IN | 
PORT446_SENT_B_SENT0_B_IN | 
PORT447_SENT_B_SENT1_B_IN */
  (uint16)( SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_SENT_B_SENT2_B_IN | 
PORT449_SENT_B_SENT3_B_IN | 
PORT450_SENT_B_SENT4_B_IN | 
PORT451_SENT_B_SENT5_B_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 464 ... 479 : PORT476_eMIOS_A_EMIOS16_IN | 
PORT477_eMIOS_A_EMIOS17_IN | 
PORT478_eMIOS_A_EMIOS18_IN | 
PORT479_eMIOS_A_EMIOS19_IN */
  (uint16)( SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_eMIOS_A_EMIOS20_IN | 
PORT481_eMIOS_A_EMIOS21_IN | 
PORT482_eMIOS_A_EMIOS22_IN | 
PORT483_eMIOS_A_EMIOS23_IN | 
PORT484_eMIOS_B_EMIOS16_IN | 
PORT485_eMIOS_B_EMIOS17_IN | 
PORT486_eMIOS_B_EMIOS18_IN | 
PORT487_eMIOS_B_EMIOS19_IN | 
PORT488_eMIOS_B_EMIOS20_IN | 
PORT489_eMIOS_B_EMIOS21_IN | 
PORT490_eMIOS_B_EMIOS22_IN | 
PORT491_eMIOS_B_EMIOS23_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT93_SENT_B_SENT1_B_IN */
  (uint16)( SHL_PAD_U32(13U)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT243_DSPI_D_PCSD0_INOUT | 
PORT243_DSPI_D_PCSD0_IN */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 */
  (uint16)0x0000,
/* Pads 448 ... 463 */
  (uint16)0x0000,
/* Pads 464 ... 479 */
  (uint16)0x0000,
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT440_eQADC_B_ANB40_IN | 
PORT441_eQADC_B_ANB41_IN | 
PORT442_eQADC_B_ANB42_IN | 
PORT444_eQADC_B_ANB45_IN */
  (uint16)( SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 448 ... 463 : PORT450_eQADC_B_ANB44_IN */
  (uint16)( SHL_PAD_U32(2U)
          ),
/* Pads 464 ... 479 : PORT475_eQADC_B_ANB43_IN | 
PORT476_eQADC_B_ANB8_IN | 
PORT477_eQADC_B_ANB9_IN | 
PORT478_eQADC_B_ANB10_IN | 
PORT479_eQADC_B_ANB11_IN */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_eQADC_B_ANB12_IN | 
PORT481_eQADC_B_ANB13_IN | 
PORT482_eQADC_B_ANB14_IN | 
PORT483_eQADC_B_ANB15_IN | 
PORT484_eQADC_B_ANB16_IN | 
PORT485_eQADC_B_ANB17_IN | 
PORT486_eQADC_B_ANB18_IN | 
PORT487_eQADC_B_ANB19_IN | 
PORT488_eQADC_B_ANB20_IN | 
PORT489_eQADC_B_ANB21_IN | 
PORT490_eQADC_B_ANB22_IN | 
PORT491_eQADC_B_ANB23_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}

[!ENDVAR!]




[!VAR "CHECK_2"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT75_GPIO | 
PORT76_GPIO | 
PORT77_GPIO | 
PORT78_GPIO | 
PORT79_GPIO */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  80 ...  95 : PORT80_GPIO | 
PORT81_GPIO | 
PORT82_GPIO | 
PORT83_GPIO | 
PORT84_GPIO | 
PORT85_GPIO | 
PORT86_GPIO | 
PORT87_GPIO | 
PORT88_GPIO | 
PORT89_GPIO | 
PORT90_GPIO | 
PORT91_GPIO | 
PORT92_GPIO | 
PORT93_GPIO | 
PORT94_GPIO | 
PORT95_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  96 ... 111 : PORT96_GPIO | 
PORT97_GPIO | 
PORT98_GPIO | 
PORT99_GPIO | 
PORT100_GPIO | 
PORT101_GPIO | 
PORT102_GPIO | 
PORT103_GPIO | 
PORT104_GPIO | 
PORT105_GPIO | 
PORT106_GPIO | 
PORT107_GPIO | 
PORT108_GPIO | 
PORT109_GPIO | 
PORT110_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT113_GPIO | 
PORT114_GPIO | 
PORT115_GPIO | 
PORT116_GPIO | 
PORT117_GPIO | 
PORT118_GPIO | 
PORT119_GPIO | 
PORT120_GPIO | 
PORT121_GPIO | 
PORT122_GPIO | 
PORT123_GPIO | 
PORT124_GPIO | 
PORT125_GPIO | 
PORT126_GPIO | 
PORT127_GPIO */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 128 ... 143 : PORT128_GPIO | 
PORT129_GPIO | 
PORT130_GPIO | 
PORT131_GPIO | 
PORT132_GPIO | 
PORT133_GPIO | 
PORT134_GPIO | 
PORT135_GPIO | 
PORT136_GPIO | 
PORT137_GPIO | 
PORT138_GPIO | 
PORT139_GPIO | 
PORT140_GPIO | 
PORT141_GPIO | 
PORT142_GPIO | 
PORT143_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_GPIO | 
PORT145_GPIO | 
PORT146_GPIO | 
PORT147_GPIO | 
PORT148_GPIO | 
PORT149_GPIO | 
PORT150_GPIO | 
PORT151_GPIO | 
PORT152_GPIO | 
PORT153_GPIO | 
PORT154_GPIO | 
PORT155_GPIO | 
PORT156_GPIO | 
PORT157_GPIO | 
PORT158_GPIO | 
PORT159_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 160 ... 175 : PORT160_GPIO | 
PORT161_GPIO | 
PORT162_GPIO | 
PORT163_GPIO | 
PORT164_GPIO | 
PORT165_GPIO | 
PORT166_GPIO | 
PORT167_GPIO | 
PORT168_GPIO | 
PORT169_GPIO | 
PORT170_GPIO | 
PORT171_GPIO | 
PORT172_GPIO | 
PORT173_GPIO | 
PORT174_GPIO | 
PORT175_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 176 ... 191 : PORT176_GPIO | 
PORT177_GPIO | 
PORT178_GPIO | 
PORT179_GPIO | 
PORT180_GPIO | 
PORT181_GPIO | 
PORT182_GPIO | 
PORT183_GPIO | 
PORT184_GPIO | 
PORT185_GPIO | 
PORT186_GPIO | 
PORT187_GPIO | 
PORT188_GPIO | 
PORT189_GPIO | 
PORT190_GPIO | 
PORT191_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 192 ... 207 : PORT192_GPIO | 
PORT193_GPIO | 
PORT194_GPIO | 
PORT195_GPIO | 
PORT196_GPIO | 
PORT197_GPIO | 
PORT198_GPIO | 
PORT199_GPIO | 
PORT200_GPIO | 
PORT201_GPIO | 
PORT202_GPIO | 
PORT203_GPIO | 
PORT204_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 : PORT208_GPIO | 
PORT209_GPIO | 
PORT210_GPIO | 
PORT211_GPIO | 
PORT212_GPIO | 
PORT213_GPIO | 
PORT214_GPIO | 
PORT219_GPIO | 
PORT220_GPIO | 
PORT221_GPIO | 
PORT222_GPIO | 
PORT223_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 224 ... 239 : PORT224_GPIO | 
PORT225_GPIO | 
PORT226_GPIO | 
PORT227_GPIO | 
PORT228_GPIO | 
PORT229_GPIO | 
PORT230_GPIO | 
PORT231_GPIO | 
PORT232_GPIO | 
PORT233_GPIO | 
PORT234_GPIO | 
PORT235_GPIO | 
PORT236_GPIO | 
PORT237_GPIO | 
PORT238_GPIO | 
PORT239_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 240 ... 255 : PORT240_GPIO | 
PORT241_GPIO | 
PORT242_GPIO | 
PORT243_GPIO | 
PORT244_GPIO | 
PORT245_GPIO | 
PORT246_GPIO | 
PORT247_GPIO | 
PORT248_GPIO | 
PORT249_GPIO | 
PORT250_GPIO | 
PORT251_GPIO | 
PORT252_GPIO | 
PORT253_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 256 ... 271 : PORT256_GPIO | 
PORT257_GPIO | 
PORT258_GPIO | 
PORT259_GPIO | 
PORT260_GPIO | 
PORT261_GPIO | 
PORT262_GPIO | 
PORT263_GPIO | 
PORT264_GPIO | 
PORT265_GPIO | 
PORT266_GPIO | 
PORT267_GPIO | 
PORT268_GPIO | 
PORT269_GPIO | 
PORT270_GPIO | 
PORT271_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 272 ... 287 : PORT272_GPIO | 
PORT273_GPIO | 
PORT274_GPIO | 
PORT275_GPIO | 
PORT276_GPIO | 
PORT277_GPIO | 
PORT278_GPIO | 
PORT279_GPIO | 
PORT280_GPIO | 
PORT281_GPIO | 
PORT282_GPIO | 
PORT283_GPIO | 
PORT284_GPIO | 
PORT285_GPIO | 
PORT286_GPIO | 
PORT287_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 288 ... 303 : PORT288_GPIO | 
PORT289_GPIO | 
PORT290_GPIO | 
PORT291_GPIO | 
PORT292_GPIO | 
PORT293_GPIO | 
PORT294_GPIO | 
PORT295_GPIO | 
PORT296_GPIO | 
PORT297_GPIO | 
PORT298_GPIO | 
PORT299_GPIO | 
PORT300_GPIO | 
PORT301_GPIO | 
PORT302_GPIO | 
PORT303_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 304 ... 319 : PORT304_GPIO | 
PORT305_GPIO | 
PORT306_GPIO | 
PORT307_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_GPIO | 
PORT433_GPIO | 
PORT434_GPIO | 
PORT435_GPIO | 
PORT436_GPIO | 
PORT437_GPIO | 
PORT440_GPI | 
PORT441_GPI | 
PORT442_GPI | 
PORT443_GPIO | 
PORT444_GPI | 
PORT445_GPIO | 
PORT446_GPIO | 
PORT447_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_GPIO | 
PORT449_GPIO | 
PORT450_GPI | 
PORT451_GPIO | 
PORT452_GPIO | 
PORT453_GPIO | 
PORT454_GPIO | 
PORT455_GPIO | 
PORT456_GPIO | 
PORT457_GPIO | 
PORT458_GPIO | 
PORT459_GPIO | 
PORT460_GPIO | 
PORT461_GPIO | 
PORT462_GPIO | 
PORT463_GPIO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 464 ... 479 : PORT464_GPIO | 
PORT465_GPIO | 
PORT466_GPIO | 
PORT467_GPIO | 
PORT468_GPIO | 
PORT469_GPIO | 
PORT470_GPIO | 
PORT471_GPIO | 
PORT472_GPIO | 
PORT474_GPI | 
PORT475_GPI | 
PORT476_GPI | 
PORT477_GPI | 
PORT478_GPI | 
PORT479_GPI */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_GPI | 
PORT481_GPI | 
PORT482_GPI | 
PORT483_GPI | 
PORT484_GPI | 
PORT485_GPI | 
PORT486_GPI | 
PORT487_GPI | 
PORT488_GPI | 
PORT489_GPI | 
PORT490_GPI | 
PORT491_GPI */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT83_FlexCAN_A_CNTXA | 
PORT84_FlexCAN_A_CNRXA | 
PORT85_FlexCAN_B_CNTXB | 
PORT86_FlexCAN_B_CNRXB | 
PORT87_FlexCAN_C_CNTXC | 
PORT88_FlexCAN_C_CNRXC | 
PORT93_DSPI_A_SCKA_OUT | 
PORT93_DSPI_A_SCKA_IN | 
PORT93_DSPI_A_SCKA_INOUT | 
PORT94_DSPI_A_SINA | 
PORT95_DSPI_A_SOUTA */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  96 ... 111 : PORT96_DSPI_A_PCSA0_OUT | 
PORT96_DSPI_A_PCSA0_IN | 
PORT96_DSPI_A_PCSA0_INOUT | 
PORT97_DSPI_A_PCSA1 | 
PORT98_DSPI_A_PCSA2 | 
PORT99_DSPI_A_PCSA3 | 
PORT100_DSPI_A_PCSA4 | 
PORT101_DSPI_A_PCSA5 | 
PORT102_DSPI_B_SCKB_INOUT | 
PORT102_DSPI_B_SCKB_OUT | 
PORT102_DSPI_B_SCKB_IN | 
PORT103_DSPI_B_SINB | 
PORT104_DSPI_B_SOUTB | 
PORT105_DSPI_B_PCSB0_OUT | 
PORT106_DSPI_B_PCSB1 | 
PORT107_DSPI_B_PCSB2 | 
PORT108_DSPI_B_PCSB3 | 
PORT109_DSPI_B_PCSB4 | 
PORT110_DSPI_B_PCSB5 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT113_eTPU_A_TCRCLKA | 
PORT114_eTPU_A_ETPUA0_INOUT | 
PORT114_eTPU_A_ETPUA0_OUT | 
PORT114_eTPU_A_ETPUA0_IN | 
PORT115_eTPU_A_ETPUA1_INOUT | 
PORT115_eTPU_A_ETPUA1_OUT | 
PORT115_eTPU_A_ETPUA1_IN | 
PORT116_eTPU_A_ETPUA2_INOUT | 
PORT116_eTPU_A_ETPUA2_OUT | 
PORT116_eTPU_A_ETPUA2_IN | 
PORT117_eTPU_A_ETPUA3_INOUT | 
PORT117_eTPU_A_ETPUA3_OUT | 
PORT117_eTPU_A_ETPUA3_IN | 
PORT118_eTPU_A_ETPUA4_INOUT | 
PORT118_eTPU_A_ETPUA4_OUT | 
PORT118_eTPU_A_ETPUA4_IN | 
PORT119_eTPU_A_ETPUA5_INOUT | 
PORT119_eTPU_A_ETPUA5_OUT | 
PORT119_eTPU_A_ETPUA5_IN | 
PORT120_eTPU_A_ETPUA6_INOUT | 
PORT120_eTPU_A_ETPUA6_OUT | 
PORT120_eTPU_A_ETPUA6_IN | 
PORT121_eTPU_A_ETPUA7_INOUT | 
PORT121_eTPU_A_ETPUA7_OUT | 
PORT121_eTPU_A_ETPUA7_IN | 
PORT122_eTPU_A_ETPUA8_INOUT | 
PORT122_eTPU_A_ETPUA8_OUT | 
PORT122_eTPU_A_ETPUA8_IN | 
PORT123_eTPU_A_ETPUA9_INOUT | 
PORT123_eTPU_A_ETPUA9_OUT | 
PORT123_eTPU_A_ETPUA9_IN | 
PORT124_eTPU_A_ETPUA10_INOUT | 
PORT124_eTPU_A_ETPUA10_OUT | 
PORT124_eTPU_A_ETPUA10_IN | 
PORT125_eTPU_A_ETPUA11_INOUT | 
PORT125_eTPU_A_ETPUA11_OUT | 
PORT125_eTPU_A_ETPUA11_IN | 
PORT126_eTPU_A_ETPUA12_INOUT | 
PORT126_eTPU_A_ETPUA12_OUT | 
PORT126_eTPU_A_ETPUA12_IN | 
PORT127_eTPU_A_ETPUA13_INOUT | 
PORT127_eTPU_A_ETPUA13_OUT | 
PORT127_eTPU_A_ETPUA13_IN */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 128 ... 143 : PORT128_eTPU_A_ETPUA14_INOUT | 
PORT128_eTPU_A_ETPUA14_OUT | 
PORT128_eTPU_A_ETPUA14_IN | 
PORT129_eTPU_A_ETPUA15_INOUT | 
PORT129_eTPU_A_ETPUA15_OUT | 
PORT129_eTPU_A_ETPUA15_IN | 
PORT130_eTPU_A_ETPUA16_INOUT | 
PORT130_eTPU_A_ETPUA16_OUT | 
PORT130_eTPU_A_ETPUA16_IN | 
PORT131_eTPU_A_ETPUA17_INOUT | 
PORT131_eTPU_A_ETPUA17_OUT | 
PORT131_eTPU_A_ETPUA17_IN | 
PORT132_eTPU_A_ETPUA18_INOUT | 
PORT132_eTPU_A_ETPUA18_OUT | 
PORT132_eTPU_A_ETPUA18_IN | 
PORT133_eTPU_A_ETPUA19_INOUT | 
PORT133_eTPU_A_ETPUA19_OUT | 
PORT133_eTPU_A_ETPUA19_IN | 
PORT134_eTPU_A_ETPUA20_INOUT | 
PORT134_eTPU_A_ETPUA20_OUT | 
PORT134_eTPU_A_ETPUA20_IN | 
PORT135_eTPU_A_ETPUA21_INOUT | 
PORT135_eTPU_A_ETPUA21_OUT | 
PORT135_eTPU_A_ETPUA21_IN | 
PORT136_eTPU_A_ETPUA22_INOUT | 
PORT136_eTPU_A_ETPUA22_OUT | 
PORT136_eTPU_A_ETPUA22_IN | 
PORT137_eTPU_A_ETPUA23_INOUT | 
PORT137_eTPU_A_ETPUA23_OUT | 
PORT137_eTPU_A_ETPUA23_IN | 
PORT138_eTPU_A_ETPUA24_OUT | 
PORT139_eTPU_A_ETPUA25_OUT | 
PORT140_eTPU_A_ETPUA26_OUT | 
PORT141_eTPU_A_ETPUA27_OUT | 
PORT142_eTPU_A_ETPUA28_OUT | 
PORT143_eTPU_A_ETPUA29_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_eTPU_A_ETPUA30_OUT | 
PORT145_eTPU_A_ETPUA31_OUT | 
PORT146_eTPU_B_TCRCLKB | 
PORT147_eTPU_B_ETPUB0_INOUT | 
PORT147_eTPU_B_ETPUB0_OUT | 
PORT147_eTPU_B_ETPUB0_IN | 
PORT148_eTPU_B_ETPUB1_INOUT | 
PORT148_eTPU_B_ETPUB1_OUT | 
PORT148_eTPU_B_ETPUB1_IN | 
PORT149_eTPU_B_ETPUB2_INOUT | 
PORT149_eTPU_B_ETPUB2_OUT | 
PORT149_eTPU_B_ETPUB2_IN | 
PORT150_eTPU_B_ETPUB3_INOUT | 
PORT150_eTPU_B_ETPUB3_OUT | 
PORT150_eTPU_B_ETPUB3_IN | 
PORT151_eTPU_B_ETPUB4_INOUT | 
PORT151_eTPU_B_ETPUB4_OUT | 
PORT151_eTPU_B_ETPUB4_IN | 
PORT152_eTPU_B_ETPUB5_INOUT | 
PORT152_eTPU_B_ETPUB5_OUT | 
PORT152_eTPU_B_ETPUB5_IN | 
PORT153_eTPU_B_ETPUB6_INOUT | 
PORT153_eTPU_B_ETPUB6_OUT | 
PORT153_eTPU_B_ETPUB6_IN | 
PORT154_eTPU_B_ETPUB7_INOUT | 
PORT154_eTPU_B_ETPUB7_OUT | 
PORT154_eTPU_B_ETPUB7_IN | 
PORT155_eTPU_B_ETPUB8_INOUT | 
PORT155_eTPU_B_ETPUB8_OUT | 
PORT155_eTPU_B_ETPUB8_IN | 
PORT156_eTPU_B_ETPUB9_INOUT | 
PORT156_eTPU_B_ETPUB9_OUT | 
PORT156_eTPU_B_ETPUB9_IN | 
PORT157_eTPU_B_ETPUB10_INOUT | 
PORT157_eTPU_B_ETPUB10_OUT | 
PORT157_eTPU_B_ETPUB10_IN | 
PORT158_eTPU_B_ETPUB11_INOUT | 
PORT158_eTPU_B_ETPUB11_OUT | 
PORT158_eTPU_B_ETPUB11_IN | 
PORT159_eTPU_B_ETPUB12_INOUT | 
PORT159_eTPU_B_ETPUB12_OUT | 
PORT159_eTPU_B_ETPUB12_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 160 ... 175 : PORT160_eTPU_B_ETPUB13_INOUT | 
PORT160_eTPU_B_ETPUB13_OUT | 
PORT160_eTPU_B_ETPUB13_IN | 
PORT161_eTPU_B_ETPUB14_INOUT | 
PORT161_eTPU_B_ETPUB14_OUT | 
PORT161_eTPU_B_ETPUB14_IN | 
PORT162_eTPU_B_ETPUB15_INOUT | 
PORT162_eTPU_B_ETPUB15_OUT | 
PORT162_eTPU_B_ETPUB15_IN | 
PORT163_eTPU_B_ETPUB16_INOUT | 
PORT163_eTPU_B_ETPUB16_OUT | 
PORT163_eTPU_B_ETPUB16_IN | 
PORT164_eTPU_B_ETPUB17_INOUT | 
PORT164_eTPU_B_ETPUB17_OUT | 
PORT164_eTPU_B_ETPUB17_IN | 
PORT165_eTPU_B_ETPUB18_INOUT | 
PORT165_eTPU_B_ETPUB18_OUT | 
PORT165_eTPU_B_ETPUB18_IN | 
PORT166_eTPU_B_ETPUB19_INOUT | 
PORT166_eTPU_B_ETPUB19_OUT | 
PORT166_eTPU_B_ETPUB19_IN | 
PORT167_eTPU_B_ETPUB20_INOUT | 
PORT167_eTPU_B_ETPUB20_OUT | 
PORT167_eTPU_B_ETPUB20_IN | 
PORT168_eTPU_B_ETPUB21_INOUT | 
PORT168_eTPU_B_ETPUB21_OUT | 
PORT168_eTPU_B_ETPUB21_IN | 
PORT169_eTPU_B_ETPUB22_INOUT | 
PORT169_eTPU_B_ETPUB22_OUT | 
PORT169_eTPU_B_ETPUB22_IN | 
PORT170_eTPU_B_ETPUB23_INOUT | 
PORT170_eTPU_B_ETPUB23_OUT | 
PORT170_eTPU_B_ETPUB23_IN | 
PORT171_eTPU_B_ETPUB24_INOUT | 
PORT171_eTPU_B_ETPUB24_OUT | 
PORT171_eTPU_B_ETPUB24_IN | 
PORT172_eTPU_B_ETPUB25_INOUT | 
PORT172_eTPU_B_ETPUB25_OUT | 
PORT172_eTPU_B_ETPUB25_IN | 
PORT173_eTPU_B_ETPUB26_INOUT | 
PORT173_eTPU_B_ETPUB26_OUT | 
PORT173_eTPU_B_ETPUB26_IN | 
PORT174_eTPU_B_ETPUB27_INOUT | 
PORT174_eTPU_B_ETPUB27_OUT | 
PORT174_eTPU_B_ETPUB27_IN | 
PORT175_eTPU_B_ETPUB28_INOUT | 
PORT175_eTPU_B_ETPUB28_OUT | 
PORT175_eTPU_B_ETPUB28_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 176 ... 191 : PORT176_eTPU_B_ETPUB29_INOUT | 
PORT176_eTPU_B_ETPUB29_OUT | 
PORT176_eTPU_B_ETPUB29_IN | 
PORT177_eTPU_B_ETPUB30_INOUT | 
PORT177_eTPU_B_ETPUB30_OUT | 
PORT177_eTPU_B_ETPUB30_IN | 
PORT178_eTPU_B_ETPUB31_INOUT | 
PORT178_eTPU_B_ETPUB31_OUT | 
PORT178_eTPU_B_ETPUB31_IN | 
PORT179_eMIOS_A_EMIOS0_INOUT | 
PORT179_eMIOS_A_EMIOS0_OUT | 
PORT179_eMIOS_A_EMIOS0_IN | 
PORT180_eMIOS_A_EMIOS1_INOUT | 
PORT180_eMIOS_A_EMIOS1_OUT | 
PORT180_eMIOS_A_EMIOS1_IN | 
PORT181_eMIOS_A_EMIOS2_INOUT | 
PORT181_eMIOS_A_EMIOS2_OUT | 
PORT181_eMIOS_A_EMIOS2_IN | 
PORT182_eMIOS_A_EMIOS3_INOUT | 
PORT182_eMIOS_A_EMIOS3_OUT | 
PORT182_eMIOS_A_EMIOS3_IN | 
PORT183_eMIOS_A_EMIOS4 | 
PORT184_eMIOS_A_EMIOS5 | 
PORT185_eMIOS_A_EMIOS6_INOUT | 
PORT185_eMIOS_A_EMIOS6_OUT | 
PORT185_eMIOS_A_EMIOS6_IN | 
PORT186_eMIOS_A_EMIOS7_INOUT | 
PORT186_eMIOS_A_EMIOS7_OUT | 
PORT186_eMIOS_A_EMIOS7_IN | 
PORT187_eMIOS_B_EMIOS0_INOUT | 
PORT187_eMIOS_B_EMIOS0_OUT | 
PORT187_eMIOS_B_EMIOS0_IN | 
PORT188_eMIOS_B_EMIOS1_INOUT | 
PORT188_eMIOS_B_EMIOS1_OUT | 
PORT188_eMIOS_B_EMIOS1_IN | 
PORT189_eMIOS_B_EMIOS2_INOUT | 
PORT189_eMIOS_B_EMIOS2_OUT | 
PORT189_eMIOS_B_EMIOS2_IN | 
PORT190_eMIOS_B_EMIOS3_INOUT | 
PORT190_eMIOS_B_EMIOS3_OUT | 
PORT190_eMIOS_B_EMIOS3_IN | 
PORT191_eMIOS_B_EMIOS4_INOUT | 
PORT191_eMIOS_B_EMIOS4_OUT | 
PORT191_eMIOS_B_EMIOS4_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 192 ... 207 : PORT192_eMIOS_B_EMIOS5_INOUT | 
PORT192_eMIOS_B_EMIOS5_OUT | 
PORT192_eMIOS_B_EMIOS5_IN | 
PORT193_eMIOS_B_EMIOS6 | 
PORT194_eMIOS_B_EMIOS7 | 
PORT195_eMIOS_A_EMIOS16_OUT | 
PORT196_eMIOS_A_EMIOS17_OUT | 
PORT197_eMIOS_A_EMIOS18_OUT | 
PORT198_eMIOS_A_EMIOS19_OUT | 
PORT199_eMIOS_A_EMIOS20_OUT | 
PORT200_eMIOS_A_EMIOS21_OUT | 
PORT201_eMIOS_A_EMIOS22_OUT | 
PORT202_eMIOS_A_EMIOS23_OUT | 
PORT203_eMIOS_B_EMIOS16_OUT | 
PORT204_eMIOS_B_EMIOS17_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 : PORT208_SoC_PLLCFG0_IN | 
PORT209_SoC_PLLCFG1_IN | 
PORT210_SoC_PLLCFG2_IN | 
PORT211_SoC_BOOTCFG0_IN | 
PORT212_SoC_BOOTCFG1_IN | 
PORT213_SoC_WKPCFG_IN | 
PORT214_ENGCLK | 
PORT219_MCKO */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(11U)
          ),
/* Pads 224 ... 239 : PORT224_MSEO0 | 
PORT225_MSEO1 | 
PORT226_RDY | 
PORT227_EVTO | 
PORT228_TDO | 
PORT229_D_CLKOUT | 
PORT230_RSTOUT | 
PORT235_DSPI_C_SCKC_OUT | 
PORT237_DSPI_C_SOUTC | 
PORT238_DSPI_C_PCSC0_OUT | 
PORT239_DSPI_C_PCSC1 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 240 ... 255 : PORT240_DSPI_C_PCSC2 | 
PORT241_DSPI_C_PCSC3 | 
PORT242_DSPI_C_PCSC4 | 
PORT243_DSPI_C_PCSC5 | 
PORT244_eSCI_C_TXDC | 
PORT245_eSCI_C_RXDC_IN | 
PORT246_FlexCAN_D_CNTXD | 
PORT248_FEC_FEC_TXD0_OUT | 
PORT249_FEC_FEC_RX_DV_IN | 
PORT250_FEC_FEC_RXD0_IN | 
PORT251_FEC_FEC_TXD1_OUT | 
PORT252_FEC_FEC_TXEN_OUT | 
PORT253_FEC_FEC_RXD1_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 256 ... 271 : PORT256_EBI_D_CS0 | 
PORT257_EBI_D_CS2 | 
PORT258_EBI_D_CS3 | 
PORT259_EBI_D_ADD12 | 
PORT260_EBI_D_ADD13 | 
PORT261_EBI_D_ADD14 | 
PORT262_EBI_D_ADD15 | 
PORT263_EBI_D_ADD16 | 
PORT264_EBI_D_ADD17 | 
PORT265_EBI_D_ADD18 | 
PORT266_EBI_D_ADD19 | 
PORT267_EBI_D_ADD20 | 
PORT268_EBI_D_ADD21 | 
PORT269_EBI_D_ADD22 | 
PORT270_EBI_D_ADD23 | 
PORT271_EBI_D_ADD24 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 272 ... 287 : PORT272_EBI_D_ADD25 | 
PORT273_EBI_D_ADD26 | 
PORT274_EBI_D_ADD27 | 
PORT275_EBI_D_ADD28 | 
PORT276_EBI_D_ADD29 | 
PORT277_EBI_D_ADD30 | 
PORT278_EBI_D_DAT0 | 
PORT279_EBI_D_DAT1 | 
PORT280_EBI_D_DAT2 | 
PORT281_EBI_D_DAT3 | 
PORT282_EBI_D_DAT4 | 
PORT283_EBI_D_DAT5 | 
PORT284_EBI_D_DAT6 | 
PORT285_EBI_D_DAT7 | 
PORT286_EBI_D_DAT8 | 
PORT287_EBI_D_DAT9 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 288 ... 303 : PORT288_EBI_D_DAT10 | 
PORT289_EBI_D_DAT11 | 
PORT290_EBI_D_DAT12 | 
PORT291_EBI_D_DAT13 | 
PORT292_EBI_D_DAT14 | 
PORT293_EBI_D_DAT15 | 
PORT294_EBI_D_RD_WR | 
PORT295_EBI_D_WE0 | 
PORT296_EBI_D_WE1 | 
PORT297_EBI_D_OE | 
PORT298_EBI_D_TS | 
PORT299_EBI_D_ALE | 
PORT300_EBI_D_TA | 
PORT301_EBI_D_CS1 | 
PORT302_EBI_D_BDIP | 
PORT303_EBI_D_WE2 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 304 ... 319 : PORT304_EBI_D_WE3 | 
PORT305_EBI_D_ADD9 | 
PORT306_EBI_D_ADD10 | 
PORT307_EBI_D_ADD11 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_eMIOS_B_EMIOS18_OUT | 
PORT433_eMIOS_B_EMIOS19_OUT | 
PORT434_eMIOS_B_EMIOS20_OUT | 
PORT435_eMIOS_B_EMIOS21_OUT | 
PORT436_eMIOS_B_EMIOS22_OUT | 
PORT437_eMIOS_B_EMIOS23_OUT | 
PORT443_eTPU_C_ETPUC2_INOUT | 
PORT443_eTPU_C_ETPUC2_OUT | 
PORT443_eTPU_C_ETPUC2_IN | 
PORT445_eTPU_C_ETPUC4_INOUT | 
PORT445_eTPU_C_ETPUC4_OUT | 
PORT445_eTPU_C_ETPUC4_IN | 
PORT446_eTPU_C_ETPUC5_INOUT | 
PORT446_eTPU_C_ETPUC5_OUT | 
PORT446_eTPU_C_ETPUC5_IN | 
PORT447_eTPU_C_ETPUC6_INOUT | 
PORT447_eTPU_C_ETPUC6_OUT | 
PORT447_eTPU_C_ETPUC6_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_eTPU_C_ETPUC7_INOUT | 
PORT448_eTPU_C_ETPUC7_OUT | 
PORT448_eTPU_C_ETPUC7_IN | 
PORT449_eTPU_C_ETPUC8_OUT | 
PORT451_eTPU_C_ETPUC10_OUT | 
PORT452_eTPU_C_ETPUC11_OUT | 
PORT453_eTPU_C_ETPUC12_OUT | 
PORT454_eTPU_C_ETPUC13_OUT | 
PORT455_eTPU_C_ETPUC14_OUT | 
PORT456_eTPU_C_ETPUC15_OUT | 
PORT457_eTPU_C_ETPUC16_INOUT | 
PORT457_eTPU_C_ETPUC16_OUT | 
PORT457_eTPU_C_ETPUC16_IN | 
PORT458_eTPU_C_ETPUC17_INOUT | 
PORT458_eTPU_C_ETPUC17_OUT | 
PORT458_eTPU_C_ETPUC17_IN | 
PORT459_eTPU_C_ETPUC18_INOUT | 
PORT459_eTPU_C_ETPUC18_OUT | 
PORT459_eTPU_C_ETPUC18_IN | 
PORT460_eTPU_C_ETPUC19_INOUT | 
PORT460_eTPU_C_ETPUC19_OUT | 
PORT460_eTPU_C_ETPUC19_IN | 
PORT461_eTPU_C_ETPUC20_INOUT | 
PORT461_eTPU_C_ETPUC20_OUT | 
PORT461_eTPU_C_ETPUC20_IN | 
PORT462_eTPU_C_ETPUC21_INOUT | 
PORT462_eTPU_C_ETPUC21_OUT | 
PORT462_eTPU_C_ETPUC21_IN | 
PORT463_eTPU_C_ETPUC22_INOUT | 
PORT463_eTPU_C_ETPUC22_OUT | 
PORT463_eTPU_C_ETPUC22_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 464 ... 479 : PORT464_eTPU_C_ETPUC23_INOUT | 
PORT464_eTPU_C_ETPUC23_OUT | 
PORT464_eTPU_C_ETPUC23_IN | 
PORT465_eTPU_C_ETPUC24_INOUT | 
PORT465_eTPU_C_ETPUC24_OUT | 
PORT465_eTPU_C_ETPUC24_IN | 
PORT466_eTPU_C_ETPUC25_INOUT | 
PORT466_eTPU_C_ETPUC25_OUT | 
PORT466_eTPU_C_ETPUC25_IN | 
PORT467_eTPU_C_ETPUC26_INOUT | 
PORT467_eTPU_C_ETPUC26_OUT | 
PORT467_eTPU_C_ETPUC26_IN | 
PORT468_eTPU_C_ETPUC27_INOUT | 
PORT468_eTPU_C_ETPUC27_OUT | 
PORT468_eTPU_C_ETPUC27_IN | 
PORT469_eTPU_C_ETPUC28_INOUT | 
PORT469_eTPU_C_ETPUC28_OUT | 
PORT469_eTPU_C_ETPUC28_IN | 
PORT470_eTPU_C_ETPUC29_INOUT | 
PORT470_eTPU_C_ETPUC29_OUT | 
PORT470_eTPU_C_ETPUC29_IN | 
PORT471_eTPU_C_ETPUC30_INOUT | 
PORT471_eTPU_C_ETPUC30_OUT | 
PORT471_eTPU_C_ETPUC30_IN | 
PORT472_eTPU_C_ETPUC31_INOUT | 
PORT472_eTPU_C_ETPUC31_OUT | 
PORT472_eTPU_C_ETPUC31_IN | 
PORT474_FEC_FEC_TXCLK_REFCLK_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(10U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT85_DSPI_C_PCSC3 | 
PORT86_DSPI_C_PCSC4 | 
PORT87_DSPI_D_PCSD3 | 
PORT88_DSPI_D_PCSD4 | 
PORT91_DSPI_D_PCSD1 | 
PORT92_DSPI_D_PCSD5 | 
PORT93_DSPI_C_PCSC1 | 
PORT94_DSPI_C_PCSC2 | 
PORT95_DSPI_C_PCSC5 */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads  96 ... 111 : PORT96_DSPI_D_PCSD2 | 
PORT97_DSPI_E_PCSE0_OUT | 
PORT97_DSPI_E_PCSE0_IN | 
PORT97_DSPI_E_PCSE0_INOUT | 
PORT98_DSPI_E_SOUTE | 
PORT99_DSPI_E_SINE | 
PORT100_DSPI_E_SCKE_OUT | 
PORT100_DSPI_E_SCKE_IN | 
PORT100_DSPI_E_SCKE_INOUT | 
PORT101_eQADC_A_eQADC_B_ETRIG1 | 
PORT105_DSPI_D_PCSD2 | 
PORT106_DSPI_D_PCSD0_OUT | 
PORT107_DSPI_C_SOUTC | 
PORT109_DSPI_C_SCKC_OUT | 
PORT110_DSPI_C_PCSC0_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT113_SIU_A_IRQ7 | 
PORT114_eTPU_A_ETPUA12 | 
PORT115_eTPU_A_ETPUA13 | 
PORT116_eTPU_A_ETPUA14 | 
PORT117_eTPU_A_ETPUA15 | 
PORT118_eTPU_A_ETPUA16 | 
PORT119_eTPU_A_ETPUA17 | 
PORT120_eTPU_A_ETPUA18 | 
PORT121_eTPU_A_ETPUA19 | 
PORT122_eTPU_A_ETPUA20 | 
PORT123_eTPU_A_ETPUA21 | 
PORT124_eTPU_A_ETPUA22 | 
PORT125_eTPU_A_ETPUA23 | 
PORT126_DSPI_B_PCSB1 | 
PORT127_DSPI_B_PCSB3 */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 128 ... 143 : PORT128_DSPI_B_PCSB4 | 
PORT129_DSPI_B_PCSB5 | 
PORT130_DSPI_D_PCSD1 | 
PORT131_DSPI_D_PCSD2 | 
PORT132_DSPI_D_PCSD3 | 
PORT133_DSPI_D_PCSD4 | 
PORT134_SIU_A_IRQ8 | 
PORT135_SIU_A_IRQ9 | 
PORT136_SIU_A_IRQ10 | 
PORT137_SIU_A_IRQ11 | 
PORT138_SIU_A_IRQ12 | 
PORT139_SIU_A_IRQ13 | 
PORT140_SIU_A_IRQ14 | 
PORT141_SIU_A_IRQ15 | 
PORT142_DSPI_C_PCSC1 | 
PORT143_DSPI_C_PCSC2 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_DSPI_C_PCSC3 | 
PORT145_DSPI_C_PCSC4 | 
PORT147_eTPU_B_ETPUB16 | 
PORT148_eTPU_B_ETPUB17 | 
PORT149_eTPU_B_ETPUB18 | 
PORT150_eTPU_B_ETPUB19 | 
PORT151_eTPU_B_ETPUB20 | 
PORT152_eTPU_B_ETPUB21 | 
PORT153_eTPU_B_ETPUB22 | 
PORT154_eTPU_B_ETPUB23 | 
PORT155_eTPU_B_ETPUB24 | 
PORT156_eTPU_B_ETPUB25 | 
PORT157_eTPU_B_ETPUB26 | 
PORT158_eTPU_B_ETPUB27 | 
PORT159_eTPU_B_ETPUB28 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 160 ... 175 : PORT160_eTPU_B_ETPUB29 | 
PORT161_eTPU_B_ETPUB30 | 
PORT162_eTPU_B_ETPUB31 | 
PORT163_DSPI_A_PCSA1 | 
PORT164_DSPI_A_PCSA2 | 
PORT165_DSPI_A_PCSA3 | 
PORT166_DSPI_A_PCSA4 | 
PORT169_REACM_RCH0_B_OUT | 
PORT170_REACM_RCH1_B_OUT | 
PORT171_REACM_RCH2_B_OUT | 
PORT172_REACM_RCH3_B_OUT | 
PORT173_REACM_RCH4_B_OUT | 
PORT174_REACM_RCH5_B_OUT | 
PORT175_REACM_RCH6_B_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 176 ... 191 : PORT176_REACM_RCH7_B_OUT | 
PORT177_REACM_RCH8_B_OUT | 
PORT178_REACM_RCH9_B_OUT | 
PORT179_eTPU_A_ETPUA0 | 
PORT180_eTPU_A_ETPUA1 | 
PORT181_eTPU_A_ETPUA2 | 
PORT182_eTPU_A_ETPUA3 | 
PORT183_eTPU_A_ETPUA4 | 
PORT184_eTPU_A_ETPUA5 | 
PORT185_eTPU_A_ETPUA6 | 
PORT186_eTPU_A_ETPUA7 | 
PORT187_eTPU_A_ETPUA8 | 
PORT188_eTPU_A_ETPUA9 | 
PORT189_DSPI_D_SCKD_OUT | 
PORT191_DSPI_C_SOUTC */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 192 ... 207 : PORT192_DSPI_D_SOUTD | 
PORT195_eTPU_B_ETPUB0 | 
PORT196_eTPU_B_ETPUB1 | 
PORT197_eTPU_B_ETPUB2 | 
PORT198_eTPU_B_ETPUB3 | 
PORT199_eTPU_B_ETPUB4 | 
PORT200_eTPU_B_ETPUB5 | 
PORT201_eTPU_B_ETPUB6 | 
PORT202_eTPU_B_ETPUB7 | 
PORT203_DSPI_B_PCSB0_OUT | 
PORT204_DSPI_B_PCSB1 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 : PORT210_eTPU_C_ETPUC3_OUT | 
PORT213_SIU_A_NMI_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 : PORT235_DSPI_C_SCK_C_LVDS_P | 
PORT236_DSPI_C_SCK_C_LVDS_N_OUT | 
PORT237_DSPI_C_SOUT_C_LVDS_P | 
PORT238_DSPI_C_SOUT_C_LVDS_N_OUT | 
PORT239_eSCI_D_TXDD */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 240 ... 255 : PORT240_DSPI_D_SCK_D_LVDS_P | 
PORT241_DSPI_D_SCK_D_LVDS_N_OUT | 
PORT242_MCAN_0_TX_OUT | 
PORT244_eQADC_A_eQADC_B_ETRIG0_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U)
          ),
/* Pads 256 ... 271 : PORT257_EBI_D_ADD_DAT31 | 
PORT258_EBI_D_TEA | 
PORT263_EBI_D_ADD_DAT16 | 
PORT264_EBI_D_ADD_DAT17 | 
PORT265_EBI_D_ADD_DAT18 | 
PORT266_EBI_D_ADD_DAT19 | 
PORT267_EBI_D_ADD_DAT20 | 
PORT268_EBI_D_ADD_DAT21 | 
PORT269_EBI_D_ADD_DAT22 | 
PORT270_EBI_D_ADD_DAT23 | 
PORT271_EBI_D_ADD_DAT24 */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 272 ... 287 : PORT272_EBI_D_ADD_DAT25 | 
PORT273_EBI_D_ADD_DAT26 | 
PORT274_EBI_D_ADD_DAT27 | 
PORT275_EBI_D_ADD_DAT28 | 
PORT276_EBI_D_ADD_DAT29 | 
PORT277_EBI_D_ADD_DAT30 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_DSPI_B_PCSB2 | 
PORT433_DSPI_B_PCSB3 | 
PORT434_DSPI_C_PCSC0_OUT | 
PORT435_DSPI_C_PCSC1 | 
PORT436_DSPI_C_PCSC2 | 
PORT437_DSPI_C_PCSC5 | 
PORT446_DSPI_E_PCSE2 | 
PORT447_DSPI_E_PCSE3 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_DSPI_E_PCSE4 | 
PORT449_DSPI_E_PCSE5 | 
PORT457_MCAN_1_TX_OUT | 
PORT458_eSCI_F_TXDF | 
PORT459_eSCI_F_RXDF_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          ),
/* Pads 464 ... 479 : PORT464_DSPI_D_PCSD5 | 
PORT465_DSPI_D_PCSD4 | 
PORT466_DSPI_D_PCSD3 | 
PORT467_DSPI_D_PCSD2 | 
PORT468_DSPI_D_PCSD1 | 
PORT469_DSPI_D_PCSD0_OUT | 
PORT470_DSPI_D_SCKD_OUT | 
PORT471_DSPI_D_SOUTD */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT83_MCAN_0_TX_OUT | 
PORT88_eSCI_E_RXDE | 
PORT93_MCAN_0_TX_OUT */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(13U)
          ),
/* Pads  96 ... 111 : PORT98_FEC_FEC_TXD2_OUT | 
PORT99_FEC_FEC_MDIO | 
PORT101_eSCI_D_RXDD */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 112 ... 127 : PORT116_REACM_RCH0_A_OUT | 
PORT117_REACM_RCH1_A_OUT | 
PORT118_REACM_RCH2_A_OUT | 
PORT119_REACM_RCH3_A_OUT | 
PORT120_REACM_RCH4_A_OUT | 
PORT121_REACM_RCH5_A_OUT | 
PORT122_REACM_RCH6_A_OUT | 
PORT123_REACM_RCH7_A_OUT | 
PORT124_REACM_RCH8_A_OUT | 
PORT125_REACM_RCH9_A_OUT */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 128 ... 143 : PORT129_MCAN_0_TX_OUT | 
PORT136_REACM_RCH0_A_OUT | 
PORT137_REACM_RCH1_A_OUT | 
PORT138_REACM_RCH2_A_OUT | 
PORT139_REACM_RCH3_A_OUT | 
PORT140_REACM_RCH4_A_OUT | 
PORT141_REACM_RCH5_A_OUT | 
PORT142_REACM_RCH6_A_OUT | 
PORT143_REACM_RCH7_A_OUT */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_REACM_RCH8_A_OUT | 
PORT145_REACM_RCH9_A_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT179_REACM_RCH0_C_OUT | 
PORT180_REACM_RCH1_C_OUT | 
PORT181_REACM_RCH2_C_OUT | 
PORT182_REACM_RCH3_C_OUT | 
PORT183_REACM_RCH4_C_OUT | 
PORT184_REACM_RCH5_C_OUT | 
PORT185_REACM_RCH6_C_OUT | 
PORT186_REACM_RCH7_C_OUT | 
PORT187_REACM_RCH8_C_OUT | 
PORT188_REACM_RCH9_C_OUT */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 192 ... 207 : PORT193_FlexCAN_D_CNTXD | 
PORT195_MCAN_1_TX_OUT | 
PORT197_REACM_RCH4_C_OUT | 
PORT198_REACM_RCH5_C_OUT | 
PORT199_REACM_RCH6_C_OUT | 
PORT200_REACM_RCH7_C_OUT | 
PORT201_REACM_RCH8_C_OUT | 
PORT202_REACM_RCH9_C_OUT */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U)
          ),
/* Pads 208 ... 223 : PORT208_eTPU_C_ETPUC9_OUT | 
PORT209_DSPI_D_SOUTD | 
PORT210_DSPI_E_PCSE1 | 
PORT212_eTPU_C_ETPUC0_OUT | 
PORT213_eTPU_C_ETPUC1_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT240_DSPI_D_SCKD_OUT | 
PORT242_DSPI_D_SOUT_D_LVDS_P | 
PORT243_DSPI_D_SOUT_D_LVDS_N_OUT | 
PORT246_MCAN_1_TX_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(6U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 */
  (uint16)0x0000,
/* Pads 448 ... 463 : PORT453_MCAN_1_TX_OUT | 
PORT454_PSI5A_SDOUT0_PSI5A_OUT | 
PORT455_PSI5A_SDIN0_PSI5A_IN | 
PORT456_REACM_RCH2_C_OUT | 
PORT457_REACM_RCH3_C_OUT | 
PORT458_REACM_RCH4_C_OUT | 
PORT460_PSI5A_SDOUT0_PSI5B_OUT | 
PORT461_PSI5A_SDIN0_PSI5B_IN */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 464 ... 479 : PORT464_eQADC_A_MAA0 | 
PORT465_eQADC_A_MAA1 | 
PORT466_eQADC_A_MAA2 | 
PORT467_eQADC_B_MAB0 | 
PORT468_REACM_RCH5_C_OUT | 
PORT469_REACM_RCH6_C_OUT | 
PORT470_REACM_RCH7_C_OUT | 
PORT471_REACM_RCH8_C_OUT | 
PORT472_REACM_RCH9_C_OUT */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT98_FEC_FEC_RXER_IN | 
PORT99_eSCI_D_TXDD | 
PORT100_FEC_FEC_RXCLK_IN | 
PORT101_FEC_FEC_TXD3_OUT | 
PORT107_FEC_FEC_RXD3_IN | 
PORT109_FEC_FEC_MDC_OUT | 
PORT110_FEC_FEC_RXD2_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 : PORT117_FCCU_ERROR0 | 
PORT124_FCCU_ERRORIN | 
PORT125_FCCU_ERROR1 */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT180_DSPI_E_PCSE2 | 
PORT181_DSPI_E_PCSE3 | 
PORT182_DSPI_E_PCSE4 | 
PORT183_DSPI_E_PCSE5 */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 192 ... 207 : PORT193_REACM_RCH0_C_OUT | 
PORT194_REACM_RCH1_C_OUT | 
PORT195_REACM_RCH2_C_OUT | 
PORT196_REACM_RCH3_C_OUT */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U)
          ),
/* Pads 208 ... 223 : PORT208_SIPI_TXN | 
PORT209_SIPI_TXP | 
PORT210_SIPI_REFCLK_INOUT | 
PORT210_SIPI_REFCLK_OUT | 
PORT210_SIPI_REFCLK_IN | 
PORT212_SIPI_RXP | 
PORT213_SIPI_RXN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT242_DSPI_D_SOUTD | 
PORT243_DSPI_D_PCSD0_OUT */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 */
  (uint16)0x0000,
/* Pads 448 ... 463 : PORT454_REACM_RCH0_C_OUT | 
PORT455_REACM_RCH1_C_OUT */
  (uint16)( SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 464 ... 479 : PORT464_eQADC_B_MAB0 | 
PORT465_eQADC_B_MAB1 | 
PORT466_eQADC_B_MAB2 | 
PORT468_eQADC_B_MAB1 | 
PORT469_eQADC_B_MAB2 */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT89_eSCI_A_TXDA | 
PORT90_eSCI_A_RXDA_IN | 
PORT91_eSCI_B_TXDB | 
PORT92_eSCI_B_RXDB */
  (uint16)( SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U)
          ),
/* Pads  96 ... 111 : PORT105_DSPI_B_PCSB0_INOUT | 
PORT105_DSPI_B_PCSB0_IN */
  (uint16)( SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT138_eTPU_A_ETPUA24_INOUT | 
PORT138_eTPU_A_ETPUA24_IN | 
PORT139_eTPU_A_ETPUA25_INOUT | 
PORT139_eTPU_A_ETPUA25_IN | 
PORT140_eTPU_A_ETPUA26_INOUT | 
PORT140_eTPU_A_ETPUA26_IN | 
PORT141_eTPU_A_ETPUA27_INOUT | 
PORT141_eTPU_A_ETPUA27_IN | 
PORT142_eTPU_A_ETPUA28_INOUT | 
PORT142_eTPU_A_ETPUA28_IN | 
PORT143_eTPU_A_ETPUA29_INOUT | 
PORT143_eTPU_A_ETPUA29_IN */
  (uint16)( SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 144 ... 159 : PORT144_eTPU_A_ETPUA30_INOUT | 
PORT144_eTPU_A_ETPUA30_IN | 
PORT145_eTPU_A_ETPUA31_INOUT | 
PORT145_eTPU_A_ETPUA31_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT195_eMIOS_A_EMIOS16_INOUT | 
PORT195_eMIOS_A_EMIOS16_IN | 
PORT196_eMIOS_A_EMIOS17_INOUT | 
PORT196_eMIOS_A_EMIOS17_IN | 
PORT197_eMIOS_A_EMIOS18_INOUT | 
PORT197_eMIOS_A_EMIOS18_IN | 
PORT198_eMIOS_A_EMIOS19_INOUT | 
PORT198_eMIOS_A_EMIOS19_IN | 
PORT199_eMIOS_A_EMIOS20_INOUT | 
PORT199_eMIOS_A_EMIOS20_IN | 
PORT200_eMIOS_A_EMIOS21_INOUT | 
PORT200_eMIOS_A_EMIOS21_IN | 
PORT201_eMIOS_A_EMIOS22_INOUT | 
PORT201_eMIOS_A_EMIOS22_IN | 
PORT202_eMIOS_A_EMIOS23_INOUT | 
PORT202_eMIOS_A_EMIOS23_IN | 
PORT203_eMIOS_B_EMIOS16_INOUT | 
PORT203_eMIOS_B_EMIOS16_IN | 
PORT204_eMIOS_B_EMIOS17_INOUT | 
PORT204_eMIOS_B_EMIOS17_IN */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT235_DSPI_C_SCKC_INOUT | 
PORT235_DSPI_C_SCKC_IN | 
PORT236_DSPI_C_SINC_IN | 
PORT238_DSPI_C_PCSC0_INOUT | 
PORT238_DSPI_C_PCSC0_IN */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 240 ... 255 : PORT247_FlexCAN_D_CNRXD_IN */
  (uint16)( SHL_PAD_U32(7U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT432_eMIOS_B_EMIOS18_INOUT | 
PORT432_eMIOS_B_EMIOS18_IN | 
PORT433_eMIOS_B_EMIOS19_INOUT | 
PORT433_eMIOS_B_EMIOS19_IN | 
PORT434_eMIOS_B_EMIOS20_INOUT | 
PORT434_eMIOS_B_EMIOS20_IN | 
PORT435_eMIOS_B_EMIOS21_INOUT | 
PORT435_eMIOS_B_EMIOS21_IN | 
PORT436_eMIOS_B_EMIOS22_INOUT | 
PORT436_eMIOS_B_EMIOS22_IN | 
PORT437_eMIOS_B_EMIOS23_INOUT | 
PORT437_eMIOS_B_EMIOS23_IN | 
PORT440_eTPU_C_TCRCLKC_IN | 
PORT441_eTPU_C_ETPUC0_IN | 
PORT442_eTPU_C_ETPUC1_IN | 
PORT444_eTPU_C_ETPUC3_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 448 ... 463 : PORT449_eTPU_C_ETPUC8_INOUT | 
PORT449_eTPU_C_ETPUC8_IN | 
PORT450_eTPU_C_ETPUC9_IN | 
PORT451_eTPU_C_ETPUC10_INOUT | 
PORT451_eTPU_C_ETPUC10_IN | 
PORT452_eTPU_C_ETPUC11_INOUT | 
PORT452_eTPU_C_ETPUC11_IN | 
PORT453_eTPU_C_ETPUC12_INOUT | 
PORT453_eTPU_C_ETPUC12_IN | 
PORT454_eTPU_C_ETPUC13_INOUT | 
PORT454_eTPU_C_ETPUC13_IN | 
PORT455_eTPU_C_ETPUC14_INOUT | 
PORT455_eTPU_C_ETPUC14_IN | 
PORT456_eTPU_C_ETPUC15_INOUT | 
PORT456_eTPU_C_ETPUC15_IN */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(8U)
          ),
/* Pads 464 ... 479 : PORT475_SENT_A_SENT2_A_IN */
  (uint16)( SHL_PAD_U32(11U)
          ),
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT83_eSCI_A_TXDA | 
PORT84_eSCI_A_RXDA */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U)
          ),
/* Pads  96 ... 111 : PORT106_DSPI_D_PCSD0_INOUT | 
PORT106_DSPI_D_PCSD0_IN | 
PORT108_DSPI_C_SINC | 
PORT109_DSPI_C_SCKC_INOUT | 
PORT109_DSPI_C_SCKC_IN | 
PORT110_DSPI_C_PCSC0_INOUT | 
PORT110_DSPI_C_PCSC0_IN */
  (uint16)( SHL_PAD_U32(10U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SIU_A_IRQ6 */
  (uint16)( SHL_PAD_U32(2U)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT189_DSPI_D_SCKD_INOUT | 
PORT189_DSPI_D_SCKD_IN | 
PORT190_DSPI_D_SIND */
  (uint16)( SHL_PAD_U32(13U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 192 ... 207 : PORT193_SIU_A_IRQ0 | 
PORT194_SIU_A_IRQ1_IN | 
PORT203_DSPI_B_PCSB0_INOUT | 
PORT203_DSPI_B_PCSB0_IN */
  (uint16)( SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(11U)
          ),
/* Pads 208 ... 223 : PORT208_SIU_A_IRQ4_IN | 
PORT209_SIU_A_IRQ5_IN | 
PORT210_eTPU_C_ETPUC3_INOUT | 
PORT210_eTPU_C_ETPUC3_IN | 
PORT211_SIU_A_IRQ2_IN | 
PORT212_SIU_A_IRQ3_IN | 
PORT223_eSCI_E_TXDE */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT243_MCAN_0_RX_IN | 
PORT248_SENT_A_SENT0_A_IN | 
PORT249_SENT_A_SENT1_A_IN | 
PORT250_SENT_A_SENT2_A_IN | 
PORT251_SENT_A_SENT3_A_IN | 
PORT252_SENT_A_SENT4_A_IN | 
PORT253_SENT_A_SENT5_A_IN */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT434_DSPI_C_PCSC0_INOUT | 
PORT434_DSPI_C_PCSC0_IN | 
PORT440_SIU_A_IRQ6_IN | 
PORT441_SENT_A_SENT0_A_IN | 
PORT442_SENT_A_SENT1_A_IN | 
PORT443_SENT_A_SENT3_A_IN | 
PORT444_SENT_A_SENT4_A_IN | 
PORT445_SENT_A_SENT5_A_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U)
          ),
/* Pads 448 ... 463 : PORT450_SIU_A_IRQ0_IN | 
PORT451_SIU_A_IRQ1_IN | 
PORT452_SIU_A_IRQ2_IN | 
PORT453_SIU_A_IRQ3_IN | 
PORT454_SIU_A_IRQ4_IN | 
PORT455_SIU_A_IRQ5_IN | 
PORT456_MCAN_1_RX_IN | 
PORT460_eSCI_A_TXDA | 
PORT461_eSCI_A_RXDA_IN | 
PORT462_eSCI_B_TXDB | 
PORT463_eSCI_B_RXDB_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 464 ... 479 : PORT469_DSPI_D_PCSD0_INOUT | 
PORT469_DSPI_D_PCSD0_IN | 
PORT470_DSPI_D_SCKD_INOUT | 
PORT470_DSPI_D_SCKD_IN | 
PORT472_DSPI_D_SIND_IN | 
PORT474_SENT_B_SENT0_B_IN | 
PORT476_eTPU_A_ETPUA31_IN | 
PORT477_eTPU_A_ETPUA30_IN | 
PORT478_eTPU_A_ETPUA29_IN | 
PORT479_eTPU_A_ETPUA28_IN */
  (uint16)( SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_eTPU_A_ETPUA27_IN | 
PORT481_eTPU_A_ETPUA26_IN | 
PORT482_eTPU_A_ETPUA25_IN | 
PORT483_eTPU_A_ETPUA24_IN | 
PORT484_eTPU_C_ETPUC15_IN | 
PORT485_eTPU_C_ETPUC14_IN | 
PORT486_eTPU_C_ETPUC13_IN | 
PORT487_eTPU_C_ETPUC12_IN | 
PORT488_eTPU_C_ETPUC11_IN | 
PORT489_eTPU_C_ETPUC10_IN | 
PORT490_eTPU_C_ETPUC9_IN | 
PORT491_eTPU_C_ETPUC8_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT84_MCAN_0_RX_IN | 
PORT91_MCAN_0_RX_IN */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(11U)
          ),
/* Pads  96 ... 111 : PORT100_eSCI_E_TXDE | 
PORT107_SENT_B_SENT2_B_IN | 
PORT108_SENT_B_SENT3_B_IN | 
PORT109_SENT_B_SENT4_B_IN | 
PORT110_SENT_B_SENT5_B_IN */
  (uint16)( SHL_PAD_U32(4U) |
            SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT133_MCAN_0_RX_IN */
  (uint16)( SHL_PAD_U32(5U)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT194_FlexCAN_D_CNRXD_IN | 
PORT196_MCAN_1_RX_IN */
  (uint16)( SHL_PAD_U32(2U) |
            SHL_PAD_U32(4U)
          ),
/* Pads 208 ... 223 : PORT208_eTPU_C_ETPUC9_INOUT | 
PORT208_eTPU_C_ETPUC9_IN | 
PORT212_eTPU_C_ETPUC0_INOUT | 
PORT212_eTPU_C_ETPUC0_IN | 
PORT213_eTPU_C_ETPUC1_INOUT | 
PORT213_eTPU_C_ETPUC1_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(5U)
          ),
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT240_DSPI_D_SCKD_INOUT | 
PORT240_DSPI_D_SCKD_IN | 
PORT241_DSPI_D_SIND_IN | 
PORT247_MCAN_1_RX_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(7U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT445_eTPU_C_TCRCLKC_IN | 
PORT446_SENT_B_SENT0_B_IN | 
PORT447_SENT_B_SENT1_B_IN */
  (uint16)( SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 448 ... 463 : PORT448_SENT_B_SENT2_B_IN | 
PORT449_SENT_B_SENT3_B_IN | 
PORT450_SENT_B_SENT4_B_IN | 
PORT451_SENT_B_SENT5_B_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 464 ... 479 : PORT476_eMIOS_A_EMIOS16_IN | 
PORT477_eMIOS_A_EMIOS17_IN | 
PORT478_eMIOS_A_EMIOS18_IN | 
PORT479_eMIOS_A_EMIOS19_IN */
  (uint16)( SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_eMIOS_A_EMIOS20_IN | 
PORT481_eMIOS_A_EMIOS21_IN | 
PORT482_eMIOS_A_EMIOS22_IN | 
PORT483_eMIOS_A_EMIOS23_IN | 
PORT484_eMIOS_B_EMIOS16_IN | 
PORT485_eMIOS_B_EMIOS17_IN | 
PORT486_eMIOS_B_EMIOS18_IN | 
PORT487_eMIOS_B_EMIOS19_IN | 
PORT488_eMIOS_B_EMIOS20_IN | 
PORT489_eMIOS_B_EMIOS21_IN | 
PORT490_eMIOS_B_EMIOS22_IN | 
PORT491_eMIOS_B_EMIOS23_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT93_SENT_B_SENT1_B_IN */
  (uint16)( SHL_PAD_U32(13U)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT243_DSPI_D_PCSD0_INOUT | 
PORT243_DSPI_D_PCSD0_IN */
  (uint16)( SHL_PAD_U32(3U) |
            SHL_PAD_U32(3U)
          ),
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 */
  (uint16)0x0000,
/* Pads 448 ... 463 */
  (uint16)0x0000,
/* Pads 464 ... 479 */
  (uint16)0x0000,
/* Pads 480 ... 495 */
  (uint16)0x0000
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000,
/* Pads 272 ... 287 */
  (uint16)0x0000,
/* Pads 288 ... 303 */
  (uint16)0x0000,
/* Pads 304 ... 319 */
  (uint16)0x0000,
/* Pads 320 ... 335 */
  (uint16)0x0000,
/* Pads 336 ... 351 */
  (uint16)0x0000,
/* Pads 352 ... 367 */
  (uint16)0x0000,
/* Pads 368 ... 383 */
  (uint16)0x0000,
/* Pads 384 ... 399 */
  (uint16)0x0000,
/* Pads 400 ... 415 */
  (uint16)0x0000,
/* Pads 416 ... 431 */
  (uint16)0x0000,
/* Pads 432 ... 447 : PORT440_eQADC_B_ANB40_IN | 
PORT441_eQADC_B_ANB41_IN | 
PORT442_eQADC_B_ANB42_IN | 
PORT444_eQADC_B_ANB45_IN */
  (uint16)( SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(12U)
          ),
/* Pads 448 ... 463 : PORT450_eQADC_B_ANB44_IN */
  (uint16)( SHL_PAD_U32(2U)
          ),
/* Pads 464 ... 479 : PORT475_eQADC_B_ANB43_IN | 
PORT476_eQADC_B_ANB8_IN | 
PORT477_eQADC_B_ANB9_IN | 
PORT478_eQADC_B_ANB10_IN | 
PORT479_eQADC_B_ANB11_IN */
  (uint16)( SHL_PAD_U32(11U) |
            SHL_PAD_U32(12U) |
            SHL_PAD_U32(13U) |
            SHL_PAD_U32(14U) |
            SHL_PAD_U32(15U)
          ),
/* Pads 480 ... 495 : PORT480_eQADC_B_ANB12_IN | 
PORT481_eQADC_B_ANB13_IN | 
PORT482_eQADC_B_ANB14_IN | 
PORT483_eQADC_B_ANB15_IN | 
PORT484_eQADC_B_ANB16_IN | 
PORT485_eQADC_B_ANB17_IN | 
PORT486_eQADC_B_ANB18_IN | 
PORT487_eQADC_B_ANB19_IN | 
PORT488_eQADC_B_ANB20_IN | 
PORT489_eQADC_B_ANB21_IN | 
PORT490_eQADC_B_ANB22_IN | 
PORT491_eQADC_B_ANB23_IN */
  (uint16)( SHL_PAD_U32(0U) |
            SHL_PAD_U32(1U) |
            SHL_PAD_U32(2U) |
            SHL_PAD_U32(3U) |
            SHL_PAD_U32(4U) |
            SHL_PAD_U32(5U) |
            SHL_PAD_U32(6U) |
            SHL_PAD_U32(7U) |
            SHL_PAD_U32(8U) |
            SHL_PAD_U32(9U) |
            SHL_PAD_U32(10U) |
            SHL_PAD_U32(11U)
          )
}

[!ENDVAR!]




[!VAR "MUX_1"!]
  /* Mux settings for pad PORT83:       {Direction} */
  /* FlexCAN_A_CNTXA functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT84:       {Direction} */
  /* FlexCAN_A_CNRXA functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT85:       {Direction} */
  /* FlexCAN_B_CNTXB functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT86:       {Direction} */
  /* FlexCAN_B_CNRXB functionality */
  PORT_PIN_IN, 
  /* DSPI_C_PCSC4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT87:       {Direction} */
  /* FlexCAN_C_CNTXC functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT88:       {Direction} */
  /* FlexCAN_C_CNRXC functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD4 functionality */
  PORT_PIN_OUT, 
  /* eSCI_E_RXDE functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT91:       {Direction} */
  /* DSPI_D_PCSD1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT92:       {Direction} */
  /* DSPI_D_PCSD5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT93:       {Direction} */
  /* DSPI_A_SCKA_INOUT functionality */
  PORT_PIN_INOUT, 
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT94:       {Direction} */
  /* DSPI_A_SINA functionality */
  PORT_PIN_IN, 
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT95:       {Direction} */
  /* DSPI_A_SOUTA functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT96:       {Direction} */
  /* DSPI_A_PCSA0_INOUT functionality */
  PORT_PIN_INOUT, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT97:       {Direction} */
  /* DSPI_A_PCSA1 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE0_INOUT functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT98:       {Direction} */
  /* DSPI_A_PCSA2 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_SOUTE functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_TXD2_OUT functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_RXER_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT99:       {Direction} */
  /* DSPI_A_PCSA3 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_SINE functionality */
  PORT_PIN_IN, 
  /* FEC_FEC_MDIO functionality */
  PORT_PIN_INOUT, 
  /* eSCI_D_TXDD functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT100:      {Direction} */
  /* DSPI_A_PCSA4 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_SCKE_INOUT functionality */
  PORT_PIN_INOUT, 
  /* FEC_FEC_RXCLK_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT101:      {Direction} */
  /* DSPI_A_PCSA5 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_eQADC_B_ETRIG1 functionality */
  PORT_PIN_IN, 
  /* eSCI_D_RXDD functionality */
  PORT_PIN_IN, 
  /* FEC_FEC_TXD3_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT102:      {Direction} */
  /* DSPI_B_SCKB_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT103:      {Direction} */
  /* DSPI_B_SINB functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT104:      {Direction} */
  /* DSPI_B_SOUTB functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT105:      {Direction} */
  /* DSPI_B_PCSB0_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT106:      {Direction} */
  /* DSPI_B_PCSB1 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT107:      {Direction} */
  /* DSPI_B_PCSB2 functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SOUTC functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_RXD3_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT108:      {Direction} */
  /* DSPI_B_PCSB3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT109:      {Direction} */
  /* DSPI_B_PCSB4 functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SCKC_OUT functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_MDC_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT110:      {Direction} */
  /* DSPI_B_PCSB5 functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC0_OUT functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_RXD2_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT113:      {Direction} */
  /* eTPU_A_TCRCLKA functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ7 functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT114:      {Direction} */
  /* eTPU_A_ETPUA0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA12 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT115:      {Direction} */
  /* eTPU_A_ETPUA1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA13 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT116:      {Direction} */
  /* eTPU_A_ETPUA2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA14 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT117:      {Direction} */
  /* eTPU_A_ETPUA3_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA15 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH1_A_OUT functionality */
  PORT_PIN_OUT, 
  /* FCCU_ERROR0 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT118:      {Direction} */
  /* eTPU_A_ETPUA4_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA16 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT119:      {Direction} */
  /* eTPU_A_ETPUA5_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA17 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT120:      {Direction} */
  /* eTPU_A_ETPUA6_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA18 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH4_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT121:      {Direction} */
  /* eTPU_A_ETPUA7_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA19 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT122:      {Direction} */
  /* eTPU_A_ETPUA8_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA20 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT123:      {Direction} */
  /* eTPU_A_ETPUA9_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA21 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT124:      {Direction} */
  /* eTPU_A_ETPUA10_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA22 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_A_OUT functionality */
  PORT_PIN_OUT, 
  /* FCCU_ERRORIN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT125:      {Direction} */
  /* eTPU_A_ETPUA11_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA23 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_A_OUT functionality */
  PORT_PIN_OUT, 
  /* FCCU_ERROR1 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT126:      {Direction} */
  /* eTPU_A_ETPUA12_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT127:      {Direction} */
  /* eTPU_A_ETPUA13_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT128:      {Direction} */
  /* eTPU_A_ETPUA14_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT129:      {Direction} */
  /* eTPU_A_ETPUA15_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB5 functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT130:      {Direction} */
  /* eTPU_A_ETPUA16_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT131:      {Direction} */
  /* eTPU_A_ETPUA17_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT132:      {Direction} */
  /* eTPU_A_ETPUA18_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT133:      {Direction} */
  /* eTPU_A_ETPUA19_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT134:      {Direction} */
  /* eTPU_A_ETPUA20_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ8 functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT135:      {Direction} */
  /* eTPU_A_ETPUA21_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ9 functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT136:      {Direction} */
  /* eTPU_A_ETPUA22_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ10 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH0_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT137:      {Direction} */
  /* eTPU_A_ETPUA23_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ11 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH1_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT138:      {Direction} */
  /* eTPU_A_ETPUA24_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ12 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH2_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT139:      {Direction} */
  /* eTPU_A_ETPUA25_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ13 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH3_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT140:      {Direction} */
  /* eTPU_A_ETPUA26_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ14 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH4_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT141:      {Direction} */
  /* eTPU_A_ETPUA27_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ15 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH5_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT142:      {Direction} */
  /* eTPU_A_ETPUA28_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT143:      {Direction} */
  /* eTPU_A_ETPUA29_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT144:      {Direction} */
  /* eTPU_A_ETPUA30_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC3 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT145:      {Direction} */
  /* eTPU_A_ETPUA31_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC4 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT146:      {Direction} */
  /* eTPU_B_TCRCLKB functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT147:      {Direction} */
  /* eTPU_B_ETPUB0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB16 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT148:      {Direction} */
  /* eTPU_B_ETPUB1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB17 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT149:      {Direction} */
  /* eTPU_B_ETPUB2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB18 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT150:      {Direction} */
  /* eTPU_B_ETPUB3_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB19 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT151:      {Direction} */
  /* eTPU_B_ETPUB4_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB20 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT152:      {Direction} */
  /* eTPU_B_ETPUB5_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB21 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT153:      {Direction} */
  /* eTPU_B_ETPUB6_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB22 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT154:      {Direction} */
  /* eTPU_B_ETPUB7_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB23 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT155:      {Direction} */
  /* eTPU_B_ETPUB8_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB24 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT156:      {Direction} */
  /* eTPU_B_ETPUB9_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB25 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT157:      {Direction} */
  /* eTPU_B_ETPUB10_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB26 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT158:      {Direction} */
  /* eTPU_B_ETPUB11_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB27 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT159:      {Direction} */
  /* eTPU_B_ETPUB12_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB28 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT160:      {Direction} */
  /* eTPU_B_ETPUB13_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB29 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT161:      {Direction} */
  /* eTPU_B_ETPUB14_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB30 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT162:      {Direction} */
  /* eTPU_B_ETPUB15_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB31 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT163:      {Direction} */
  /* eTPU_B_ETPUB16_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT164:      {Direction} */
  /* eTPU_B_ETPUB17_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT165:      {Direction} */
  /* eTPU_B_ETPUB18_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT166:      {Direction} */
  /* eTPU_B_ETPUB19_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT167:      {Direction} */
  /* eTPU_B_ETPUB20_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT168:      {Direction} */
  /* eTPU_B_ETPUB21_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT169:      {Direction} */
  /* eTPU_B_ETPUB22_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH0_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT170:      {Direction} */
  /* eTPU_B_ETPUB23_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH1_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT171:      {Direction} */
  /* eTPU_B_ETPUB24_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH2_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT172:      {Direction} */
  /* eTPU_B_ETPUB25_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH3_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT173:      {Direction} */
  /* eTPU_B_ETPUB26_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH4_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT174:      {Direction} */
  /* eTPU_B_ETPUB27_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH5_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT175:      {Direction} */
  /* eTPU_B_ETPUB28_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH6_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT176:      {Direction} */
  /* eTPU_B_ETPUB29_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH7_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT177:      {Direction} */
  /* eTPU_B_ETPUB30_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH8_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT178:      {Direction} */
  /* eTPU_B_ETPUB31_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH9_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT179:      {Direction} */
  /* eMIOS_A_EMIOS0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA0 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT180:      {Direction} */
  /* eMIOS_A_EMIOS1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH1_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT181:      {Direction} */
  /* eMIOS_A_EMIOS2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA2 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT182:      {Direction} */
  /* eMIOS_A_EMIOS3_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA3 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT183:      {Direction} */
  /* eMIOS_A_EMIOS4 functionality */
  PORT_PIN_OUT, 
  /* eTPU_A_ETPUA4 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH4_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT184:      {Direction} */
  /* eMIOS_A_EMIOS5 functionality */
  PORT_PIN_OUT, 
  /* eTPU_A_ETPUA5 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT185:      {Direction} */
  /* eMIOS_A_EMIOS6_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA6 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT186:      {Direction} */
  /* eMIOS_A_EMIOS7_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA7 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT187:      {Direction} */
  /* eMIOS_B_EMIOS0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA8 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT188:      {Direction} */
  /* eMIOS_B_EMIOS1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA9 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT189:      {Direction} */
  /* eMIOS_B_EMIOS2_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SCKD_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT190:      {Direction} */
  /* eMIOS_B_EMIOS3_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT191:      {Direction} */
  /* eMIOS_B_EMIOS4_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_C_SOUTC functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT192:      {Direction} */
  /* eMIOS_B_EMIOS5_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT193:      {Direction} */
  /* eMIOS_B_EMIOS6 functionality */
  PORT_PIN_OUT, 
  /* FlexCAN_D_CNTXD functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT194:      {Direction} */
  /* eMIOS_B_EMIOS7 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH1_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT195:      {Direction} */
  /* eMIOS_A_EMIOS16_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB0 functionality */
  PORT_PIN_OUT, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT196:      {Direction} */
  /* eMIOS_A_EMIOS17_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT197:      {Direction} */
  /* eMIOS_A_EMIOS18_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB2 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH4_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT198:      {Direction} */
  /* eMIOS_A_EMIOS19_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB3 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT199:      {Direction} */
  /* eMIOS_A_EMIOS20_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB4 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT200:      {Direction} */
  /* eMIOS_A_EMIOS21_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB5 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT201:      {Direction} */
  /* eMIOS_A_EMIOS22_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB6 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT202:      {Direction} */
  /* eMIOS_A_EMIOS23_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB7 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT203:      {Direction} */
  /* eMIOS_B_EMIOS16_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT204:      {Direction} */
  /* eMIOS_B_EMIOS17_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT208:      {Direction} */
  /* SoC_PLLCFG0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC9_OUT functionality */
  PORT_PIN_OUT, 
  /* SIPI_TXN functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT209:      {Direction} */
  /* SoC_PLLCFG1_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* SIPI_TXP functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT210:      {Direction} */
  /* SoC_PLLCFG2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC3_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE1 functionality */
  PORT_PIN_OUT, 
  /* SIPI_REFCLK_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT212:      {Direction} */
  /* SoC_BOOTCFG1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC0_OUT functionality */
  PORT_PIN_OUT, 
  /* SIPI_RXP functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT213:      {Direction} */
  /* SoC_WKPCFG_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_NMI_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC1_OUT functionality */
  PORT_PIN_OUT, 
  /* SIPI_RXN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT214:      {Direction} */
  /* ENGCLK functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT219:      {Direction} */
  /* MCKO functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT224:      {Direction} */
  /* MSEO0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT225:      {Direction} */
  /* MSEO1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT226:      {Direction} */
  /* RDY functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT227:      {Direction} */
  /* EVTO functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT228:      {Direction} */
  /* TDO functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT229:      {Direction} */
  /* D_CLKOUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT230:      {Direction} */
  /* RSTOUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT235:      {Direction} */
  /* DSPI_C_SCKC_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SCK_C_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT236:      {Direction} */
  /* DSPI_C_SCK_C_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT237:      {Direction} */
  /* DSPI_C_SOUTC functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SOUT_C_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT238:      {Direction} */
  /* DSPI_C_PCSC0_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SOUT_C_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT239:      {Direction} */
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* eSCI_D_TXDD functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT240:      {Direction} */
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SCK_D_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SCKD_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT241:      {Direction} */
  /* DSPI_C_PCSC3 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SCK_D_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT242:      {Direction} */
  /* DSPI_C_PCSC4 functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SOUT_D_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT243:      {Direction} */
  /* DSPI_C_PCSC5 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SOUT_D_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT244:      {Direction} */
  /* eSCI_C_TXDC functionality */
  PORT_PIN_INOUT, 
  /* eQADC_A_eQADC_B_ETRIG0_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT245:      {Direction} */
  /* eSCI_C_RXDC_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT246:      {Direction} */
  /* FlexCAN_D_CNTXD functionality */
  PORT_PIN_OUT, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT248:      {Direction} */
  /* FEC_FEC_TXD0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT249:      {Direction} */
  /* FEC_FEC_RX_DV_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT250:      {Direction} */
  /* FEC_FEC_RXD0_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT251:      {Direction} */
  /* FEC_FEC_TXD1_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT252:      {Direction} */
  /* FEC_FEC_TXEN_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT253:      {Direction} */
  /* FEC_FEC_RXD1_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT432:      {Direction} */
  /* eMIOS_B_EMIOS18_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT433:      {Direction} */
  /* eMIOS_B_EMIOS19_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT434:      {Direction} */
  /* eMIOS_B_EMIOS20_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT435:      {Direction} */
  /* eMIOS_B_EMIOS21_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT436:      {Direction} */
  /* eMIOS_B_EMIOS22_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT437:      {Direction} */
  /* eMIOS_B_EMIOS23_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT443:      {Direction} */
  /* eTPU_C_ETPUC2_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT445:      {Direction} */
  /* eTPU_C_ETPUC4_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT446:      {Direction} */
  /* eTPU_C_ETPUC5_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_E_PCSE2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT447:      {Direction} */
  /* eTPU_C_ETPUC6_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_E_PCSE3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT448:      {Direction} */
  /* eTPU_C_ETPUC7_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_E_PCSE4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT449:      {Direction} */
  /* eTPU_C_ETPUC8_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT451:      {Direction} */
  /* eTPU_C_ETPUC10_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT452:      {Direction} */
  /* eTPU_C_ETPUC11_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT453:      {Direction} */
  /* eTPU_C_ETPUC12_OUT functionality */
  PORT_PIN_OUT, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT454:      {Direction} */
  /* eTPU_C_ETPUC13_OUT functionality */
  PORT_PIN_OUT, 
  /* PSI5A_SDOUT0_PSI5A_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT455:      {Direction} */
  /* eTPU_C_ETPUC14_OUT functionality */
  PORT_PIN_OUT, 
  /* PSI5A_SDIN0_PSI5A_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH1_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT456:      {Direction} */
  /* eTPU_C_ETPUC15_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT457:      {Direction} */
  /* eTPU_C_ETPUC16_IN functionality */
  PORT_PIN_IN, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT458:      {Direction} */
  /* eTPU_C_ETPUC17_IN functionality */
  PORT_PIN_IN, 
  /* eSCI_F_TXDF functionality */
  PORT_PIN_INOUT, 
  /* REACM_RCH4_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT459:      {Direction} */
  /* eTPU_C_ETPUC18_IN functionality */
  PORT_PIN_IN, 
  /* eSCI_F_RXDF_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT460:      {Direction} */
  /* eTPU_C_ETPUC19_IN functionality */
  PORT_PIN_IN, 
  /* PSI5A_SDOUT0_PSI5B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT461:      {Direction} */
  /* eTPU_C_ETPUC20_IN functionality */
  PORT_PIN_IN, 
  /* PSI5A_SDIN0_PSI5B_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT462:      {Direction} */
  /* eTPU_C_ETPUC21_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT463:      {Direction} */
  /* eTPU_C_ETPUC22_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT464:      {Direction} */
  /* eTPU_C_ETPUC23_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD5 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_MAA0 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT465:      {Direction} */
  /* eTPU_C_ETPUC24_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD4 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_MAA1 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT466:      {Direction} */
  /* eTPU_C_ETPUC25_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD3 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_MAA2 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT467:      {Direction} */
  /* eTPU_C_ETPUC26_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT468:      {Direction} */
  /* eTPU_C_ETPUC27_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_C_OUT functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT469:      {Direction} */
  /* eTPU_C_ETPUC28_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD0_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_C_OUT functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT470:      {Direction} */
  /* eTPU_C_ETPUC29_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SCKD_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT471:      {Direction} */
  /* eTPU_C_ETPUC30_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT472:      {Direction} */
  /* eTPU_C_ETPUC31_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH9_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT474:      {Direction} */
  /* FEC_FEC_TXCLK_REFCLK_IN functionality */
  PORT_PIN_IN
[!ENDVAR!]


[!VAR "MUX_2"!]
  /* Mux settings for pad PORT83:       {Direction} */
  /* FlexCAN_A_CNTXA functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT84:       {Direction} */
  /* FlexCAN_A_CNRXA functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT85:       {Direction} */
  /* FlexCAN_B_CNTXB functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT86:       {Direction} */
  /* FlexCAN_B_CNRXB functionality */
  PORT_PIN_IN, 
  /* DSPI_C_PCSC4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT87:       {Direction} */
  /* FlexCAN_C_CNTXC functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT88:       {Direction} */
  /* FlexCAN_C_CNRXC functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD4 functionality */
  PORT_PIN_OUT, 
  /* eSCI_E_RXDE functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT91:       {Direction} */
  /* DSPI_D_PCSD1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT92:       {Direction} */
  /* DSPI_D_PCSD5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT93:       {Direction} */
  /* DSPI_A_SCKA_INOUT functionality */
  PORT_PIN_INOUT, 
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT94:       {Direction} */
  /* DSPI_A_SINA functionality */
  PORT_PIN_IN, 
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT95:       {Direction} */
  /* DSPI_A_SOUTA functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT96:       {Direction} */
  /* DSPI_A_PCSA0_INOUT functionality */
  PORT_PIN_INOUT, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT97:       {Direction} */
  /* DSPI_A_PCSA1 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE0_INOUT functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT98:       {Direction} */
  /* DSPI_A_PCSA2 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_SOUTE functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_TXD2_OUT functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_RXER_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT99:       {Direction} */
  /* DSPI_A_PCSA3 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_SINE functionality */
  PORT_PIN_IN, 
  /* FEC_FEC_MDIO functionality */
  PORT_PIN_INOUT, 
  /* eSCI_D_TXDD functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT100:      {Direction} */
  /* DSPI_A_PCSA4 functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_SCKE_INOUT functionality */
  PORT_PIN_INOUT, 
  /* FEC_FEC_RXCLK_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT101:      {Direction} */
  /* DSPI_A_PCSA5 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_eQADC_B_ETRIG1 functionality */
  PORT_PIN_IN, 
  /* eSCI_D_RXDD functionality */
  PORT_PIN_IN, 
  /* FEC_FEC_TXD3_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT102:      {Direction} */
  /* DSPI_B_SCKB_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT103:      {Direction} */
  /* DSPI_B_SINB functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT104:      {Direction} */
  /* DSPI_B_SOUTB functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT105:      {Direction} */
  /* DSPI_B_PCSB0_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT106:      {Direction} */
  /* DSPI_B_PCSB1 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT107:      {Direction} */
  /* DSPI_B_PCSB2 functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SOUTC functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_RXD3_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT108:      {Direction} */
  /* DSPI_B_PCSB3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT109:      {Direction} */
  /* DSPI_B_PCSB4 functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SCKC_OUT functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_MDC_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT110:      {Direction} */
  /* DSPI_B_PCSB5 functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC0_OUT functionality */
  PORT_PIN_OUT, 
  /* FEC_FEC_RXD2_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT113:      {Direction} */
  /* eTPU_A_TCRCLKA functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ7 functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT114:      {Direction} */
  /* eTPU_A_ETPUA0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA12 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT115:      {Direction} */
  /* eTPU_A_ETPUA1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA13 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT116:      {Direction} */
  /* eTPU_A_ETPUA2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA14 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT117:      {Direction} */
  /* eTPU_A_ETPUA3_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA15 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH1_A_OUT functionality */
  PORT_PIN_OUT, 
  /* FCCU_ERROR0 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT118:      {Direction} */
  /* eTPU_A_ETPUA4_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA16 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT119:      {Direction} */
  /* eTPU_A_ETPUA5_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA17 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT120:      {Direction} */
  /* eTPU_A_ETPUA6_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA18 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH4_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT121:      {Direction} */
  /* eTPU_A_ETPUA7_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA19 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT122:      {Direction} */
  /* eTPU_A_ETPUA8_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA20 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT123:      {Direction} */
  /* eTPU_A_ETPUA9_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA21 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT124:      {Direction} */
  /* eTPU_A_ETPUA10_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA22 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_A_OUT functionality */
  PORT_PIN_OUT, 
  /* FCCU_ERRORIN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT125:      {Direction} */
  /* eTPU_A_ETPUA11_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA23 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_A_OUT functionality */
  PORT_PIN_OUT, 
  /* FCCU_ERROR1 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT126:      {Direction} */
  /* eTPU_A_ETPUA12_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT127:      {Direction} */
  /* eTPU_A_ETPUA13_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT128:      {Direction} */
  /* eTPU_A_ETPUA14_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT129:      {Direction} */
  /* eTPU_A_ETPUA15_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_B_PCSB5 functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT130:      {Direction} */
  /* eTPU_A_ETPUA16_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT131:      {Direction} */
  /* eTPU_A_ETPUA17_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT132:      {Direction} */
  /* eTPU_A_ETPUA18_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT133:      {Direction} */
  /* eTPU_A_ETPUA19_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT134:      {Direction} */
  /* eTPU_A_ETPUA20_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ8 functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT135:      {Direction} */
  /* eTPU_A_ETPUA21_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ9 functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT136:      {Direction} */
  /* eTPU_A_ETPUA22_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ10 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH0_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT137:      {Direction} */
  /* eTPU_A_ETPUA23_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_IRQ11 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH1_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT138:      {Direction} */
  /* eTPU_A_ETPUA24_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ12 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH2_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT139:      {Direction} */
  /* eTPU_A_ETPUA25_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ13 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH3_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT140:      {Direction} */
  /* eTPU_A_ETPUA26_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ14 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH4_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT141:      {Direction} */
  /* eTPU_A_ETPUA27_OUT functionality */
  PORT_PIN_OUT, 
  /* SIU_A_IRQ15 functionality */
  PORT_PIN_IN, 
  /* REACM_RCH5_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT142:      {Direction} */
  /* eTPU_A_ETPUA28_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT143:      {Direction} */
  /* eTPU_A_ETPUA29_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT144:      {Direction} */
  /* eTPU_A_ETPUA30_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC3 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT145:      {Direction} */
  /* eTPU_A_ETPUA31_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC4 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_A_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT146:      {Direction} */
  /* eTPU_B_TCRCLKB functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT147:      {Direction} */
  /* eTPU_B_ETPUB0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB16 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT148:      {Direction} */
  /* eTPU_B_ETPUB1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB17 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT149:      {Direction} */
  /* eTPU_B_ETPUB2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB18 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT150:      {Direction} */
  /* eTPU_B_ETPUB3_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB19 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT151:      {Direction} */
  /* eTPU_B_ETPUB4_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB20 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT152:      {Direction} */
  /* eTPU_B_ETPUB5_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB21 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT153:      {Direction} */
  /* eTPU_B_ETPUB6_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB22 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT154:      {Direction} */
  /* eTPU_B_ETPUB7_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB23 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT155:      {Direction} */
  /* eTPU_B_ETPUB8_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB24 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT156:      {Direction} */
  /* eTPU_B_ETPUB9_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB25 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT157:      {Direction} */
  /* eTPU_B_ETPUB10_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB26 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT158:      {Direction} */
  /* eTPU_B_ETPUB11_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB27 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT159:      {Direction} */
  /* eTPU_B_ETPUB12_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB28 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT160:      {Direction} */
  /* eTPU_B_ETPUB13_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB29 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT161:      {Direction} */
  /* eTPU_B_ETPUB14_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB30 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT162:      {Direction} */
  /* eTPU_B_ETPUB15_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_B_ETPUB31 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT163:      {Direction} */
  /* eTPU_B_ETPUB16_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT164:      {Direction} */
  /* eTPU_B_ETPUB17_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT165:      {Direction} */
  /* eTPU_B_ETPUB18_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT166:      {Direction} */
  /* eTPU_B_ETPUB19_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_A_PCSA4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT167:      {Direction} */
  /* eTPU_B_ETPUB20_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT168:      {Direction} */
  /* eTPU_B_ETPUB21_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT169:      {Direction} */
  /* eTPU_B_ETPUB22_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH0_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT170:      {Direction} */
  /* eTPU_B_ETPUB23_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH1_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT171:      {Direction} */
  /* eTPU_B_ETPUB24_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH2_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT172:      {Direction} */
  /* eTPU_B_ETPUB25_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH3_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT173:      {Direction} */
  /* eTPU_B_ETPUB26_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH4_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT174:      {Direction} */
  /* eTPU_B_ETPUB27_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH5_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT175:      {Direction} */
  /* eTPU_B_ETPUB28_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH6_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT176:      {Direction} */
  /* eTPU_B_ETPUB29_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH7_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT177:      {Direction} */
  /* eTPU_B_ETPUB30_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH8_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT178:      {Direction} */
  /* eTPU_B_ETPUB31_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH9_B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT179:      {Direction} */
  /* eMIOS_A_EMIOS0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA0 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT180:      {Direction} */
  /* eMIOS_A_EMIOS1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH1_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT181:      {Direction} */
  /* eMIOS_A_EMIOS2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA2 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT182:      {Direction} */
  /* eMIOS_A_EMIOS3_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA3 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT183:      {Direction} */
  /* eMIOS_A_EMIOS4 functionality */
  PORT_PIN_OUT, 
  /* eTPU_A_ETPUA4 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH4_C_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT184:      {Direction} */
  /* eMIOS_A_EMIOS5 functionality */
  PORT_PIN_OUT, 
  /* eTPU_A_ETPUA5 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT185:      {Direction} */
  /* eMIOS_A_EMIOS6_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA6 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT186:      {Direction} */
  /* eMIOS_A_EMIOS7_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA7 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT187:      {Direction} */
  /* eMIOS_B_EMIOS0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA8 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT188:      {Direction} */
  /* eMIOS_B_EMIOS1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_A_ETPUA9 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT189:      {Direction} */
  /* eMIOS_B_EMIOS2_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SCKD_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT190:      {Direction} */
  /* eMIOS_B_EMIOS3_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT191:      {Direction} */
  /* eMIOS_B_EMIOS4_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_C_SOUTC functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT192:      {Direction} */
  /* eMIOS_B_EMIOS5_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT193:      {Direction} */
  /* eMIOS_B_EMIOS6 functionality */
  PORT_PIN_OUT, 
  /* FlexCAN_D_CNTXD functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT194:      {Direction} */
  /* eMIOS_B_EMIOS7 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH1_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT195:      {Direction} */
  /* eMIOS_A_EMIOS16_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB0 functionality */
  PORT_PIN_OUT, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT196:      {Direction} */
  /* eMIOS_A_EMIOS17_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT197:      {Direction} */
  /* eMIOS_A_EMIOS18_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB2 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH4_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT198:      {Direction} */
  /* eMIOS_A_EMIOS19_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB3 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT199:      {Direction} */
  /* eMIOS_A_EMIOS20_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB4 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT200:      {Direction} */
  /* eMIOS_A_EMIOS21_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB5 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT201:      {Direction} */
  /* eMIOS_A_EMIOS22_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB6 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT202:      {Direction} */
  /* eMIOS_A_EMIOS23_OUT functionality */
  PORT_PIN_OUT, 
  /* eTPU_B_ETPUB7 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH9_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT203:      {Direction} */
  /* eMIOS_B_EMIOS16_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT204:      {Direction} */
  /* eMIOS_B_EMIOS17_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT208:      {Direction} */
  /* SoC_PLLCFG0_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC9_OUT functionality */
  PORT_PIN_OUT, 
  /* SIPI_TXN functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT209:      {Direction} */
  /* SoC_PLLCFG1_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* SIPI_TXP functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT210:      {Direction} */
  /* SoC_PLLCFG2_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC3_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE1 functionality */
  PORT_PIN_OUT, 
  /* SIPI_REFCLK_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT211:      {Direction} */
  /* SoC_BOOTCFG0_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT212:      {Direction} */
  /* SoC_BOOTCFG1_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC0_OUT functionality */
  PORT_PIN_OUT, 
  /* SIPI_RXP functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT213:      {Direction} */
  /* SoC_WKPCFG_IN functionality */
  PORT_PIN_IN, 
  /* SIU_A_NMI_IN functionality */
  PORT_PIN_IN, 
  /* eTPU_C_ETPUC1_OUT functionality */
  PORT_PIN_OUT, 
  /* SIPI_RXN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT214:      {Direction} */
  /* ENGCLK functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT219:      {Direction} */
  /* MCKO functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT224:      {Direction} */
  /* MSEO0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT225:      {Direction} */
  /* MSEO1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT226:      {Direction} */
  /* RDY functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT227:      {Direction} */
  /* EVTO functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT228:      {Direction} */
  /* TDO functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT229:      {Direction} */
  /* D_CLKOUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT230:      {Direction} */
  /* RSTOUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT235:      {Direction} */
  /* DSPI_C_SCKC_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SCK_C_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT236:      {Direction} */
  /* DSPI_C_SCK_C_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT237:      {Direction} */
  /* DSPI_C_SOUTC functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SOUT_C_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT238:      {Direction} */
  /* DSPI_C_PCSC0_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_SOUT_C_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT239:      {Direction} */
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* eSCI_D_TXDD functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT240:      {Direction} */
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SCK_D_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SCKD_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT241:      {Direction} */
  /* DSPI_C_PCSC3 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SCK_D_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT242:      {Direction} */
  /* DSPI_C_PCSC4 functionality */
  PORT_PIN_OUT, 
  /* MCAN_0_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SOUT_D_LVDS_P functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT243:      {Direction} */
  /* DSPI_C_PCSC5 functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_SOUT_D_LVDS_N_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_D_PCSD0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT244:      {Direction} */
  /* eSCI_C_TXDC functionality */
  PORT_PIN_INOUT, 
  /* eQADC_A_eQADC_B_ETRIG0_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT245:      {Direction} */
  /* eSCI_C_RXDC_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT246:      {Direction} */
  /* FlexCAN_D_CNTXD functionality */
  PORT_PIN_OUT, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT248:      {Direction} */
  /* FEC_FEC_TXD0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT249:      {Direction} */
  /* FEC_FEC_RX_DV_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT250:      {Direction} */
  /* FEC_FEC_RXD0_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT251:      {Direction} */
  /* FEC_FEC_TXD1_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT252:      {Direction} */
  /* FEC_FEC_TXEN_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT253:      {Direction} */
  /* FEC_FEC_RXD1_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT256:      {Direction} */
  /* EBI_D_CS0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT257:      {Direction} */
  /* EBI_D_CS2 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT31 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT258:      {Direction} */
  /* EBI_D_CS3 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_TEA functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT259:      {Direction} */
  /* EBI_D_ADD12 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT260:      {Direction} */
  /* EBI_D_ADD13 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT261:      {Direction} */
  /* EBI_D_ADD14 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT262:      {Direction} */
  /* EBI_D_ADD15 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT263:      {Direction} */
  /* EBI_D_ADD16 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT16 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT264:      {Direction} */
  /* EBI_D_ADD17 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT17 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT265:      {Direction} */
  /* EBI_D_ADD18 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT18 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT266:      {Direction} */
  /* EBI_D_ADD19 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT19 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT267:      {Direction} */
  /* EBI_D_ADD20 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT20 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT268:      {Direction} */
  /* EBI_D_ADD21 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT21 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT269:      {Direction} */
  /* EBI_D_ADD22 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT22 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT270:      {Direction} */
  /* EBI_D_ADD23 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT23 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT271:      {Direction} */
  /* EBI_D_ADD24 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT24 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT272:      {Direction} */
  /* EBI_D_ADD25 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT25 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT273:      {Direction} */
  /* EBI_D_ADD26 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT26 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT274:      {Direction} */
  /* EBI_D_ADD27 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT27 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT275:      {Direction} */
  /* EBI_D_ADD28 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT28 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT276:      {Direction} */
  /* EBI_D_ADD29 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT29 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT277:      {Direction} */
  /* EBI_D_ADD30 functionality */
  PORT_PIN_OUT, 
  /* EBI_D_ADD_DAT30 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT278:      {Direction} */
  /* EBI_D_DAT0 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT279:      {Direction} */
  /* EBI_D_DAT1 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT280:      {Direction} */
  /* EBI_D_DAT2 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT281:      {Direction} */
  /* EBI_D_DAT3 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT282:      {Direction} */
  /* EBI_D_DAT4 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT283:      {Direction} */
  /* EBI_D_DAT5 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT284:      {Direction} */
  /* EBI_D_DAT6 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT285:      {Direction} */
  /* EBI_D_DAT7 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT286:      {Direction} */
  /* EBI_D_DAT8 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT287:      {Direction} */
  /* EBI_D_DAT9 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT288:      {Direction} */
  /* EBI_D_DAT10 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT289:      {Direction} */
  /* EBI_D_DAT11 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT290:      {Direction} */
  /* EBI_D_DAT12 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT291:      {Direction} */
  /* EBI_D_DAT13 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT292:      {Direction} */
  /* EBI_D_DAT14 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT293:      {Direction} */
  /* EBI_D_DAT15 functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT294:      {Direction} */
  /* EBI_D_RD_WR functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT295:      {Direction} */
  /* EBI_D_WE0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT296:      {Direction} */
  /* EBI_D_WE1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT297:      {Direction} */
  /* EBI_D_OE functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT298:      {Direction} */
  /* EBI_D_TS functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT299:      {Direction} */
  /* EBI_D_ALE functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT300:      {Direction} */
  /* EBI_D_TA functionality */
  PORT_PIN_INOUT, 
  /* Mux settings for pad PORT301:      {Direction} */
  /* EBI_D_CS1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT302:      {Direction} */
  /* EBI_D_BDIP functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT303:      {Direction} */
  /* EBI_D_WE2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT304:      {Direction} */
  /* EBI_D_WE3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT305:      {Direction} */
  /* EBI_D_ADD9 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT306:      {Direction} */
  /* EBI_D_ADD10 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT307:      {Direction} */
  /* EBI_D_ADD11 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT432:      {Direction} */
  /* eMIOS_B_EMIOS18_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT433:      {Direction} */
  /* eMIOS_B_EMIOS19_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_B_PCSB3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT434:      {Direction} */
  /* eMIOS_B_EMIOS20_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC0_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT435:      {Direction} */
  /* eMIOS_B_EMIOS21_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT436:      {Direction} */
  /* eMIOS_B_EMIOS22_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT437:      {Direction} */
  /* eMIOS_B_EMIOS23_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_C_PCSC5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT443:      {Direction} */
  /* eTPU_C_ETPUC2_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT445:      {Direction} */
  /* eTPU_C_ETPUC4_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT446:      {Direction} */
  /* eTPU_C_ETPUC5_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_E_PCSE2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT447:      {Direction} */
  /* eTPU_C_ETPUC6_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_E_PCSE3 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT448:      {Direction} */
  /* eTPU_C_ETPUC7_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_E_PCSE4 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT449:      {Direction} */
  /* eTPU_C_ETPUC8_OUT functionality */
  PORT_PIN_OUT, 
  /* DSPI_E_PCSE5 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT451:      {Direction} */
  /* eTPU_C_ETPUC10_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT452:      {Direction} */
  /* eTPU_C_ETPUC11_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT453:      {Direction} */
  /* eTPU_C_ETPUC12_OUT functionality */
  PORT_PIN_OUT, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT454:      {Direction} */
  /* eTPU_C_ETPUC13_OUT functionality */
  PORT_PIN_OUT, 
  /* PSI5A_SDOUT0_PSI5A_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH0_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT455:      {Direction} */
  /* eTPU_C_ETPUC14_OUT functionality */
  PORT_PIN_OUT, 
  /* PSI5A_SDIN0_PSI5A_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH1_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT456:      {Direction} */
  /* eTPU_C_ETPUC15_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH2_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT457:      {Direction} */
  /* eTPU_C_ETPUC16_IN functionality */
  PORT_PIN_IN, 
  /* MCAN_1_TX_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH3_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT458:      {Direction} */
  /* eTPU_C_ETPUC17_IN functionality */
  PORT_PIN_IN, 
  /* eSCI_F_TXDF functionality */
  PORT_PIN_INOUT, 
  /* REACM_RCH4_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT459:      {Direction} */
  /* eTPU_C_ETPUC18_IN functionality */
  PORT_PIN_IN, 
  /* eSCI_F_RXDF_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT460:      {Direction} */
  /* eTPU_C_ETPUC19_IN functionality */
  PORT_PIN_IN, 
  /* PSI5A_SDOUT0_PSI5B_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT461:      {Direction} */
  /* eTPU_C_ETPUC20_IN functionality */
  PORT_PIN_IN, 
  /* PSI5A_SDIN0_PSI5B_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT462:      {Direction} */
  /* eTPU_C_ETPUC21_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT463:      {Direction} */
  /* eTPU_C_ETPUC22_IN functionality */
  PORT_PIN_IN, 
  /* Mux settings for pad PORT464:      {Direction} */
  /* eTPU_C_ETPUC23_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD5 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_MAA0 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT465:      {Direction} */
  /* eTPU_C_ETPUC24_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD4 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_MAA1 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT466:      {Direction} */
  /* eTPU_C_ETPUC25_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD3 functionality */
  PORT_PIN_OUT, 
  /* eQADC_A_MAA2 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT467:      {Direction} */
  /* eTPU_C_ETPUC26_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD2 functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB0 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT468:      {Direction} */
  /* eTPU_C_ETPUC27_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD1 functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH5_C_OUT functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB1 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT469:      {Direction} */
  /* eTPU_C_ETPUC28_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_PCSD0_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH6_C_OUT functionality */
  PORT_PIN_OUT, 
  /* eQADC_B_MAB2 functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT470:      {Direction} */
  /* eTPU_C_ETPUC29_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SCKD_OUT functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH7_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT471:      {Direction} */
  /* eTPU_C_ETPUC30_IN functionality */
  PORT_PIN_IN, 
  /* DSPI_D_SOUTD functionality */
  PORT_PIN_OUT, 
  /* REACM_RCH8_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT472:      {Direction} */
  /* eTPU_C_ETPUC31_IN functionality */
  PORT_PIN_IN, 
  /* REACM_RCH9_C_OUT functionality */
  PORT_PIN_OUT, 
  /* Mux settings for pad PORT474:      {Direction} */
  /* FEC_FEC_TXCLK_REFCLK_IN functionality */
  PORT_PIN_IN
[!ENDVAR!]


[!VAR "INMUX_1"!]
  /* Inmux settings for pad PORT83:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_TXDA input func */
  {(uint16)64, (uint8)1, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT84:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_RXDA input func */
  {(uint16)65, (uint8)1, PORT_PIN_IN}, 
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT89:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_TXDA input func */
  {(uint16)64, (uint8)0, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT90:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_RXDA_IN input func */
  {(uint16)65, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT91:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_TXDB input func */
  {(uint16)67, (uint8)0, PORT_PIN_INOUT}, 
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT92:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_RXDB input func */
  {(uint16)66, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT93:     {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT1_B_IN input func */
  {(uint16)7, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT100:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_E_TXDE input func */
  {(uint16)72, (uint8)0, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT105:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_B_PCSB0_IN input func */
  {(uint16)37, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT106:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_PCSD0_IN input func */
  {(uint16)43, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT107:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT2_B_IN input func */
  {(uint16)8, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT108:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SINC input func */
  {(uint16)39, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT3_B_IN input func */
  {(uint16)9, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT109:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SCKC_IN input func */
  {(uint16)38, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT4_B_IN input func */
  {(uint16)10, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT110:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_PCSC0_IN input func */
  {(uint16)40, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT5_B_IN input func */
  {(uint16)11, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT133:    {Inmux reg, Inmux value, Direction} */
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT138:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA24_IN input func */
  {(uint16)120, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT139:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA25_IN input func */
  {(uint16)121, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT140:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA26_IN input func */
  {(uint16)122, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT141:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA27_IN input func */
  {(uint16)123, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT142:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA28_IN input func */
  {(uint16)124, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT143:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA29_IN input func */
  {(uint16)125, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT144:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA30_IN input func */
  {(uint16)126, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT145:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA31_IN input func */
  {(uint16)127, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT146:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ6 input func */
  {(uint16)54, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT189:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SCKD_IN input func */
  {(uint16)41, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT190:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SIND input func */
  {(uint16)42, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT193:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ0 input func */
  {(uint16)48, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT194:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ1_IN input func */
  {(uint16)49, (uint8)0, PORT_PIN_IN}, 
  /* FlexCAN_D_CNRXD_IN input func */
  {(uint16)21, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT195:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS16_IN input func */
  {(uint16)80, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT196:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS17_IN input func */
  {(uint16)81, (uint8)0, PORT_PIN_IN}, 
  /* MCAN_1_RX_IN input func */
  {(uint16)17, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT197:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS18_IN input func */
  {(uint16)82, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT198:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS19_IN input func */
  {(uint16)83, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT199:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS20_IN input func */
  {(uint16)84, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT200:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS21_IN input func */
  {(uint16)85, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT201:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS22_IN input func */
  {(uint16)86, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT202:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS23_IN input func */
  {(uint16)87, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT203:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS16_IN input func */
  {(uint16)88, (uint8)0, PORT_PIN_IN}, 
  /* DSPI_B_PCSB0_IN input func */
  {(uint16)37, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT204:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS17_IN input func */
  {(uint16)89, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT208:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ4_IN input func */
  {(uint16)52, (uint8)0, PORT_PIN_IN}, 
  /* eTPU_C_ETPUC9_IN input func */
  {(uint16)169, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT209:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ5_IN input func */
  {(uint16)53, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT210:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC3_IN input func */
  {(uint16)163, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT212:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ3_IN input func */
  {(uint16)51, (uint8)0, PORT_PIN_IN}, 
  /* eTPU_C_ETPUC0_IN input func */
  {(uint16)160, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT213:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC1_IN input func */
  {(uint16)161, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT223:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_E_TXDE input func */
  {(uint16)72, (uint8)1, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT235:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SCKC_IN input func */
  {(uint16)38, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT236:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SINC_IN input func */
  {(uint16)39, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT238:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_PCSC0_IN input func */
  {(uint16)40, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT240:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SCKD_IN input func */
  {(uint16)41, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT241:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SIND_IN input func */
  {(uint16)42, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT243:    {Inmux reg, Inmux value, Direction} */
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)3, PORT_PIN_IN}, 
  /* DSPI_D_PCSD0_IN input func */
  {(uint16)43, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT247:    {Inmux reg, Inmux value, Direction} */
  /* FlexCAN_D_CNRXD_IN input func */
  {(uint16)21, (uint8)0, PORT_PIN_IN}, 
  /* MCAN_1_RX_IN input func */
  {(uint16)17, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT248:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT0_A_IN input func */
  {(uint16)0, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT249:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT1_A_IN input func */
  {(uint16)1, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT250:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT2_A_IN input func */
  {(uint16)2, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT251:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT3_A_IN input func */
  {(uint16)3, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT252:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT4_A_IN input func */
  {(uint16)4, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT253:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT5_A_IN input func */
  {(uint16)5, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT432:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS18_IN input func */
  {(uint16)90, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT433:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS19_IN input func */
  {(uint16)91, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT434:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS20_IN input func */
  {(uint16)92, (uint8)0, PORT_PIN_IN}, 
  /* DSPI_C_PCSC0_IN input func */
  {(uint16)40, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT435:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS21_IN input func */
  {(uint16)93, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT436:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS22_IN input func */
  {(uint16)94, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT437:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS23_IN input func */
  {(uint16)95, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT440:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_TCRCLKC_IN input func */
  {(uint16)194, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ6_IN input func */
  {(uint16)54, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT441:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC0_IN input func */
  {(uint16)160, (uint8)0, PORT_PIN_IN}, 
  /* SENT_A_SENT0_A_IN input func */
  {(uint16)0, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT442:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC1_IN input func */
  {(uint16)161, (uint8)0, PORT_PIN_IN}, 
  /* SENT_A_SENT1_A_IN input func */
  {(uint16)1, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT443:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT3_A_IN input func */
  {(uint16)3, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT444:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC3_IN input func */
  {(uint16)163, (uint8)0, PORT_PIN_IN}, 
  /* SENT_A_SENT4_A_IN input func */
  {(uint16)4, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT445:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT5_A_IN input func */
  {(uint16)5, (uint8)0, PORT_PIN_IN}, 
  /* eTPU_C_TCRCLKC_IN input func */
  {(uint16)194, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT446:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT0_B_IN input func */
  {(uint16)6, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT447:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT1_B_IN input func */
  {(uint16)7, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT448:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT2_B_IN input func */
  {(uint16)8, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT449:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC8_IN input func */
  {(uint16)168, (uint8)0, PORT_PIN_IN}, 
  /* SENT_B_SENT3_B_IN input func */
  {(uint16)9, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT450:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC9_IN input func */
  {(uint16)169, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ0_IN input func */
  {(uint16)48, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT4_B_IN input func */
  {(uint16)10, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT451:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC10_IN input func */
  {(uint16)170, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ1_IN input func */
  {(uint16)49, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT5_B_IN input func */
  {(uint16)11, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT452:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC11_IN input func */
  {(uint16)171, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ2_IN input func */
  {(uint16)50, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT453:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC12_IN input func */
  {(uint16)172, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ3_IN input func */
  {(uint16)51, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT454:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC13_IN input func */
  {(uint16)173, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ4_IN input func */
  {(uint16)52, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT455:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC14_IN input func */
  {(uint16)174, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ5_IN input func */
  {(uint16)53, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT456:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC15_IN input func */
  {(uint16)175, (uint8)0, PORT_PIN_IN}, 
  /* MCAN_1_RX_IN input func */
  {(uint16)17, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT460:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_TXDA input func */
  {(uint16)64, (uint8)2, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT461:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_RXDA_IN input func */
  {(uint16)65, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT462:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_TXDB input func */
  {(uint16)67, (uint8)1, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT463:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_RXDB_IN input func */
  {(uint16)66, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT469:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_PCSD0_IN input func */
  {(uint16)43, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT470:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SCKD_IN input func */
  {(uint16)41, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT472:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SIND_IN input func */
  {(uint16)42, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT474:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT0_B_IN input func */
  {(uint16)6, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT475:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT2_A_IN input func */
  {(uint16)2, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT476:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA31_IN input func */
  {(uint16)127, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS16_IN input func */
  {(uint16)80, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT477:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA30_IN input func */
  {(uint16)126, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS17_IN input func */
  {(uint16)81, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT478:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA29_IN input func */
  {(uint16)125, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS18_IN input func */
  {(uint16)82, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT479:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA28_IN input func */
  {(uint16)124, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS19_IN input func */
  {(uint16)83, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT480:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA27_IN input func */
  {(uint16)123, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS20_IN input func */
  {(uint16)84, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT481:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA26_IN input func */
  {(uint16)122, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS21_IN input func */
  {(uint16)85, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT482:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA25_IN input func */
  {(uint16)121, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS22_IN input func */
  {(uint16)86, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT483:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA24_IN input func */
  {(uint16)120, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS23_IN input func */
  {(uint16)87, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT484:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC15_IN input func */
  {(uint16)175, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS16_IN input func */
  {(uint16)88, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT485:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC14_IN input func */
  {(uint16)174, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS17_IN input func */
  {(uint16)89, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT486:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC13_IN input func */
  {(uint16)173, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS18_IN input func */
  {(uint16)90, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT487:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC12_IN input func */
  {(uint16)172, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS19_IN input func */
  {(uint16)91, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT488:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC11_IN input func */
  {(uint16)171, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS20_IN input func */
  {(uint16)92, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT489:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC10_IN input func */
  {(uint16)170, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS21_IN input func */
  {(uint16)93, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT490:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC9_IN input func */
  {(uint16)169, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS22_IN input func */
  {(uint16)94, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT491:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC8_IN input func */
  {(uint16)168, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS23_IN input func */
  {(uint16)95, (uint8)1, PORT_PIN_IN}
[!ENDVAR!]


[!VAR "INMUX_2"!]
  /* Inmux settings for pad PORT83:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_TXDA input func */
  {(uint16)64, (uint8)1, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT84:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_RXDA input func */
  {(uint16)65, (uint8)1, PORT_PIN_IN}, 
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT89:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_TXDA input func */
  {(uint16)64, (uint8)0, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT90:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_RXDA_IN input func */
  {(uint16)65, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT91:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_TXDB input func */
  {(uint16)67, (uint8)0, PORT_PIN_INOUT}, 
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT92:     {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_RXDB input func */
  {(uint16)66, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT93:     {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT1_B_IN input func */
  {(uint16)7, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT100:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_E_TXDE input func */
  {(uint16)72, (uint8)0, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT105:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_B_PCSB0_IN input func */
  {(uint16)37, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT106:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_PCSD0_IN input func */
  {(uint16)43, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT107:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT2_B_IN input func */
  {(uint16)8, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT108:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SINC input func */
  {(uint16)39, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT3_B_IN input func */
  {(uint16)9, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT109:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SCKC_IN input func */
  {(uint16)38, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT4_B_IN input func */
  {(uint16)10, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT110:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_PCSC0_IN input func */
  {(uint16)40, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT5_B_IN input func */
  {(uint16)11, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT133:    {Inmux reg, Inmux value, Direction} */
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT138:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA24_IN input func */
  {(uint16)120, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT139:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA25_IN input func */
  {(uint16)121, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT140:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA26_IN input func */
  {(uint16)122, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT141:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA27_IN input func */
  {(uint16)123, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT142:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA28_IN input func */
  {(uint16)124, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT143:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA29_IN input func */
  {(uint16)125, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT144:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA30_IN input func */
  {(uint16)126, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT145:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA31_IN input func */
  {(uint16)127, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT146:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ6 input func */
  {(uint16)54, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT189:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SCKD_IN input func */
  {(uint16)41, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT190:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SIND input func */
  {(uint16)42, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT193:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ0 input func */
  {(uint16)48, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT194:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ1_IN input func */
  {(uint16)49, (uint8)0, PORT_PIN_IN}, 
  /* FlexCAN_D_CNRXD_IN input func */
  {(uint16)21, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT195:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS16_IN input func */
  {(uint16)80, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT196:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS17_IN input func */
  {(uint16)81, (uint8)0, PORT_PIN_IN}, 
  /* MCAN_1_RX_IN input func */
  {(uint16)17, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT197:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS18_IN input func */
  {(uint16)82, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT198:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS19_IN input func */
  {(uint16)83, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT199:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS20_IN input func */
  {(uint16)84, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT200:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS21_IN input func */
  {(uint16)85, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT201:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS22_IN input func */
  {(uint16)86, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT202:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_A_EMIOS23_IN input func */
  {(uint16)87, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT203:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS16_IN input func */
  {(uint16)88, (uint8)0, PORT_PIN_IN}, 
  /* DSPI_B_PCSB0_IN input func */
  {(uint16)37, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT204:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS17_IN input func */
  {(uint16)89, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT208:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ4_IN input func */
  {(uint16)52, (uint8)0, PORT_PIN_IN}, 
  /* eTPU_C_ETPUC9_IN input func */
  {(uint16)169, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT209:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ5_IN input func */
  {(uint16)53, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT210:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC3_IN input func */
  {(uint16)163, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT211:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ2_IN input func */
  {(uint16)50, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT212:    {Inmux reg, Inmux value, Direction} */
  /* SIU_A_IRQ3_IN input func */
  {(uint16)51, (uint8)0, PORT_PIN_IN}, 
  /* eTPU_C_ETPUC0_IN input func */
  {(uint16)160, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT213:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC1_IN input func */
  {(uint16)161, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT223:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_E_TXDE input func */
  {(uint16)72, (uint8)1, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT235:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SCKC_IN input func */
  {(uint16)38, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT236:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_SINC_IN input func */
  {(uint16)39, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT238:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_C_PCSC0_IN input func */
  {(uint16)40, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT240:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SCKD_IN input func */
  {(uint16)41, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT241:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SIND_IN input func */
  {(uint16)42, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT243:    {Inmux reg, Inmux value, Direction} */
  /* MCAN_0_RX_IN input func */
  {(uint16)16, (uint8)3, PORT_PIN_IN}, 
  /* DSPI_D_PCSD0_IN input func */
  {(uint16)43, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT247:    {Inmux reg, Inmux value, Direction} */
  /* FlexCAN_D_CNRXD_IN input func */
  {(uint16)21, (uint8)0, PORT_PIN_IN}, 
  /* MCAN_1_RX_IN input func */
  {(uint16)17, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT248:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT0_A_IN input func */
  {(uint16)0, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT249:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT1_A_IN input func */
  {(uint16)1, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT250:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT2_A_IN input func */
  {(uint16)2, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT251:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT3_A_IN input func */
  {(uint16)3, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT252:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT4_A_IN input func */
  {(uint16)4, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT253:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT5_A_IN input func */
  {(uint16)5, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT432:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS18_IN input func */
  {(uint16)90, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT433:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS19_IN input func */
  {(uint16)91, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT434:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS20_IN input func */
  {(uint16)92, (uint8)0, PORT_PIN_IN}, 
  /* DSPI_C_PCSC0_IN input func */
  {(uint16)40, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT435:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS21_IN input func */
  {(uint16)93, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT436:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS22_IN input func */
  {(uint16)94, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT437:    {Inmux reg, Inmux value, Direction} */
  /* eMIOS_B_EMIOS23_IN input func */
  {(uint16)95, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT440:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_TCRCLKC_IN input func */
  {(uint16)194, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ6_IN input func */
  {(uint16)54, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT441:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC0_IN input func */
  {(uint16)160, (uint8)0, PORT_PIN_IN}, 
  /* SENT_A_SENT0_A_IN input func */
  {(uint16)0, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT442:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC1_IN input func */
  {(uint16)161, (uint8)0, PORT_PIN_IN}, 
  /* SENT_A_SENT1_A_IN input func */
  {(uint16)1, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT443:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT3_A_IN input func */
  {(uint16)3, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT444:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC3_IN input func */
  {(uint16)163, (uint8)0, PORT_PIN_IN}, 
  /* SENT_A_SENT4_A_IN input func */
  {(uint16)4, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT445:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT5_A_IN input func */
  {(uint16)5, (uint8)0, PORT_PIN_IN}, 
  /* eTPU_C_TCRCLKC_IN input func */
  {(uint16)194, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT446:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT0_B_IN input func */
  {(uint16)6, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT447:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT1_B_IN input func */
  {(uint16)7, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT448:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT2_B_IN input func */
  {(uint16)8, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT449:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC8_IN input func */
  {(uint16)168, (uint8)0, PORT_PIN_IN}, 
  /* SENT_B_SENT3_B_IN input func */
  {(uint16)9, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT450:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC9_IN input func */
  {(uint16)169, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ0_IN input func */
  {(uint16)48, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT4_B_IN input func */
  {(uint16)10, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT451:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC10_IN input func */
  {(uint16)170, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ1_IN input func */
  {(uint16)49, (uint8)1, PORT_PIN_IN}, 
  /* SENT_B_SENT5_B_IN input func */
  {(uint16)11, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT452:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC11_IN input func */
  {(uint16)171, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ2_IN input func */
  {(uint16)50, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT453:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC12_IN input func */
  {(uint16)172, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ3_IN input func */
  {(uint16)51, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT454:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC13_IN input func */
  {(uint16)173, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ4_IN input func */
  {(uint16)52, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT455:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC14_IN input func */
  {(uint16)174, (uint8)0, PORT_PIN_IN}, 
  /* SIU_A_IRQ5_IN input func */
  {(uint16)53, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT456:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC15_IN input func */
  {(uint16)175, (uint8)0, PORT_PIN_IN}, 
  /* MCAN_1_RX_IN input func */
  {(uint16)17, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT460:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_TXDA input func */
  {(uint16)64, (uint8)2, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT461:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_A_RXDA_IN input func */
  {(uint16)65, (uint8)2, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT462:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_TXDB input func */
  {(uint16)67, (uint8)1, PORT_PIN_INOUT}, 
  /* Inmux settings for pad PORT463:    {Inmux reg, Inmux value, Direction} */
  /* eSCI_B_RXDB_IN input func */
  {(uint16)66, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT469:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_PCSD0_IN input func */
  {(uint16)43, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT470:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SCKD_IN input func */
  {(uint16)41, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT472:    {Inmux reg, Inmux value, Direction} */
  /* DSPI_D_SIND_IN input func */
  {(uint16)42, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT474:    {Inmux reg, Inmux value, Direction} */
  /* SENT_B_SENT0_B_IN input func */
  {(uint16)6, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT475:    {Inmux reg, Inmux value, Direction} */
  /* SENT_A_SENT2_A_IN input func */
  {(uint16)2, (uint8)0, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT476:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA31_IN input func */
  {(uint16)127, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS16_IN input func */
  {(uint16)80, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT477:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA30_IN input func */
  {(uint16)126, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS17_IN input func */
  {(uint16)81, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT478:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA29_IN input func */
  {(uint16)125, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS18_IN input func */
  {(uint16)82, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT479:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA28_IN input func */
  {(uint16)124, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS19_IN input func */
  {(uint16)83, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT480:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA27_IN input func */
  {(uint16)123, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS20_IN input func */
  {(uint16)84, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT481:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA26_IN input func */
  {(uint16)122, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS21_IN input func */
  {(uint16)85, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT482:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA25_IN input func */
  {(uint16)121, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS22_IN input func */
  {(uint16)86, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT483:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_A_ETPUA24_IN input func */
  {(uint16)120, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_A_EMIOS23_IN input func */
  {(uint16)87, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT484:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC15_IN input func */
  {(uint16)175, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS16_IN input func */
  {(uint16)88, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT485:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC14_IN input func */
  {(uint16)174, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS17_IN input func */
  {(uint16)89, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT486:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC13_IN input func */
  {(uint16)173, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS18_IN input func */
  {(uint16)90, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT487:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC12_IN input func */
  {(uint16)172, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS19_IN input func */
  {(uint16)91, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT488:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC11_IN input func */
  {(uint16)171, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS20_IN input func */
  {(uint16)92, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT489:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC10_IN input func */
  {(uint16)170, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS21_IN input func */
  {(uint16)93, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT490:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC9_IN input func */
  {(uint16)169, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS22_IN input func */
  {(uint16)94, (uint8)1, PORT_PIN_IN}, 
  /* Inmux settings for pad PORT491:    {Inmux reg, Inmux value, Direction} */
  /* eTPU_C_ETPUC8_IN input func */
  {(uint16)168, (uint8)1, PORT_PIN_IN}, 
  /* eMIOS_B_EMIOS23_IN input func */
  {(uint16)95, (uint8)1, PORT_PIN_IN}
[!ENDVAR!]


[!VAR "INDEX_1"!]
  /* Settings information for pad 0 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 1 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 2 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 3 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 4 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 5 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 6 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 7 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 8 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 9 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 10 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 11 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 12 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 13 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 14 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 15 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 16 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 17 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 18 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 19 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 20 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 21 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 22 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 23 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 24 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 25 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 26 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 27 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 28 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 29 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 30 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 31 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 32 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 33 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 34 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 35 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 36 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 37 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 38 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 39 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 40 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 41 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 42 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 43 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 44 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 45 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 46 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 47 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 48 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 49 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 50 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 51 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 52 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 53 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 54 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 55 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 56 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 57 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 58 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 59 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 60 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 61 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 62 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 63 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 64 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 65 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 66 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 67 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 68 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 69 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 70 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 71 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 72 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 73 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 74 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 75 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 76 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 77 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 78 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 79 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 80 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 81 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 82 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 83 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_A_CNTXA functionality */
  {(uint16)83, (uint8)1, (uint16)0}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)83, (uint8)3, (uint16)1}
  /* eSCI_A_TXDA functionality */,
  {(uint16)83, (uint8)6, (uint16)0}
  /* Settings information for pad 84 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_A_CNRXA functionality */,
  {(uint16)84, (uint8)1, (uint16)2}
  /* eSCI_A_RXDA functionality */,
  {(uint16)84, (uint8)6, (uint16)1}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)84, (uint8)7, (uint16)2}
  /* Settings information for pad 85 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_B_CNTXB functionality */,
  {(uint16)85, (uint8)1, (uint16)3}
  /* DSPI_C_PCSC3 functionality */,
  {(uint16)85, (uint8)2, (uint16)4}
  /* Settings information for pad 86 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_B_CNRXB functionality */,
  {(uint16)86, (uint8)1, (uint16)5}
  /* DSPI_C_PCSC4 functionality */,
  {(uint16)86, (uint8)2, (uint16)6}
  /* Settings information for pad 87 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_C_CNTXC functionality */,
  {(uint16)87, (uint8)1, (uint16)7}
  /* DSPI_D_PCSD3 functionality */,
  {(uint16)87, (uint8)2, (uint16)8}
  /* Settings information for pad 88 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_C_CNRXC functionality */,
  {(uint16)88, (uint8)1, (uint16)9}
  /* DSPI_D_PCSD4 functionality */,
  {(uint16)88, (uint8)2, (uint16)10}
  /* eSCI_E_RXDE functionality */,
  {(uint16)88, (uint8)3, (uint16)11}
  /* Settings information for pad 89 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_A_TXDA functionality */,
  {(uint16)89, (uint8)5, (uint16)3}
  /* Settings information for pad 90 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_A_RXDA_IN functionality */,
  {(uint16)90, (uint8)5, (uint16)4}
  /* Settings information for pad 91 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_D_PCSD1 functionality */,
  {(uint16)91, (uint8)2, (uint16)12}
  /* eSCI_B_TXDB functionality */,
  {(uint16)91, (uint8)5, (uint16)5}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)91, (uint8)7, (uint16)6}
  /* Settings information for pad 92 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_D_PCSD5 functionality */,
  {(uint16)92, (uint8)2, (uint16)13}
  /* eSCI_B_RXDB functionality */,
  {(uint16)92, (uint8)5, (uint16)7}
  /* Settings information for pad 93 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_SCKA_INOUT functionality */,
  {(uint16)93, (uint8)1, (uint16)14}
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)93, (uint8)2, (uint16)15}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)93, (uint8)3, (uint16)16}
  /* SENT_B_SENT1_B_IN functionality */,
  {(uint16)93, (uint8)8, (uint16)8}
  /* Settings information for pad 94 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_SINA functionality */,
  {(uint16)94, (uint8)1, (uint16)17}
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)94, (uint8)2, (uint16)18}
  /* Settings information for pad 95 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_SOUTA functionality */,
  {(uint16)95, (uint8)1, (uint16)19}
  /* DSPI_C_PCSC5 functionality */,
  {(uint16)95, (uint8)2, (uint16)20}
  /* Settings information for pad 96 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA0_INOUT functionality */,
  {(uint16)96, (uint8)1, (uint16)21}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)96, (uint8)2, (uint16)22}
  /* Settings information for pad 97 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA1 functionality */,
  {(uint16)97, (uint8)1, (uint16)23}
  /* DSPI_E_PCSE0_INOUT functionality */,
  {(uint16)97, (uint8)2, (uint16)24}
  /* Settings information for pad 98 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA2 functionality */,
  {(uint16)98, (uint8)1, (uint16)25}
  /* DSPI_E_SOUTE functionality */,
  {(uint16)98, (uint8)2, (uint16)26}
  /* FEC_FEC_TXD2_OUT functionality */,
  {(uint16)98, (uint8)3, (uint16)27}
  /* FEC_FEC_RXER_IN functionality */,
  {(uint16)98, (uint8)4, (uint16)28}
  /* Settings information for pad 99 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA3 functionality */,
  {(uint16)99, (uint8)1, (uint16)29}
  /* DSPI_E_SINE functionality */,
  {(uint16)99, (uint8)2, (uint16)30}
  /* FEC_FEC_MDIO functionality */,
  {(uint16)99, (uint8)3, (uint16)31}
  /* eSCI_D_TXDD functionality */,
  {(uint16)99, (uint8)4, (uint16)32}
  /* Settings information for pad 100 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA4 functionality */,
  {(uint16)100, (uint8)1, (uint16)33}
  /* DSPI_E_SCKE_INOUT functionality */,
  {(uint16)100, (uint8)2, (uint16)34}
  /* FEC_FEC_RXCLK_IN functionality */,
  {(uint16)100, (uint8)4, (uint16)35}
  /* eSCI_E_TXDE functionality */,
  {(uint16)100, (uint8)7, (uint16)9}
  /* Settings information for pad 101 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA5 functionality */,
  {(uint16)101, (uint8)1, (uint16)36}
  /* eQADC_A_eQADC_B_ETRIG1 functionality */,
  {(uint16)101, (uint8)2, (uint16)37}
  /* eSCI_D_RXDD functionality */,
  {(uint16)101, (uint8)3, (uint16)38}
  /* FEC_FEC_TXD3_OUT functionality */,
  {(uint16)101, (uint8)4, (uint16)39}
  /* Settings information for pad 102 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_SCKB_IN functionality */,
  {(uint16)102, (uint8)1, (uint16)40}
  /* Settings information for pad 103 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_SINB functionality */,
  {(uint16)103, (uint8)1, (uint16)41}
  /* Settings information for pad 104 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_SOUTB functionality */,
  {(uint16)104, (uint8)1, (uint16)42}
  /* Settings information for pad 105 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB0_OUT functionality */,
  {(uint16)105, (uint8)1, (uint16)43}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)105, (uint8)2, (uint16)44}
  /* DSPI_B_PCSB0_IN functionality */,
  {(uint16)105, (uint8)5, (uint16)10}
  /* Settings information for pad 106 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB1 functionality */,
  {(uint16)106, (uint8)1, (uint16)45}
  /* DSPI_D_PCSD0_OUT functionality */,
  {(uint16)106, (uint8)2, (uint16)46}
  /* DSPI_D_PCSD0_IN functionality */,
  {(uint16)106, (uint8)6, (uint16)11}
  /* Settings information for pad 107 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB2 functionality */,
  {(uint16)107, (uint8)1, (uint16)47}
  /* DSPI_C_SOUTC functionality */,
  {(uint16)107, (uint8)2, (uint16)48}
  /* FEC_FEC_RXD3_IN functionality */,
  {(uint16)107, (uint8)4, (uint16)49}
  /* SENT_B_SENT2_B_IN functionality */,
  {(uint16)107, (uint8)7, (uint16)12}
  /* Settings information for pad 108 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB3 functionality */,
  {(uint16)108, (uint8)1, (uint16)50}
  /* DSPI_C_SINC functionality */,
  {(uint16)108, (uint8)6, (uint16)13}
  /* SENT_B_SENT3_B_IN functionality */,
  {(uint16)108, (uint8)7, (uint16)14}
  /* Settings information for pad 109 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB4 functionality */,
  {(uint16)109, (uint8)1, (uint16)51}
  /* DSPI_C_SCKC_OUT functionality */,
  {(uint16)109, (uint8)2, (uint16)52}
  /* FEC_FEC_MDC_OUT functionality */,
  {(uint16)109, (uint8)4, (uint16)53}
  /* DSPI_C_SCKC_IN functionality */,
  {(uint16)109, (uint8)6, (uint16)15}
  /* SENT_B_SENT4_B_IN functionality */,
  {(uint16)109, (uint8)7, (uint16)16}
  /* Settings information for pad 110 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB5 functionality */,
  {(uint16)110, (uint8)1, (uint16)54}
  /* DSPI_C_PCSC0_OUT functionality */,
  {(uint16)110, (uint8)2, (uint16)55}
  /* FEC_FEC_RXD2_IN functionality */,
  {(uint16)110, (uint8)4, (uint16)56}
  /* DSPI_C_PCSC0_IN functionality */,
  {(uint16)110, (uint8)6, (uint16)17}
  /* SENT_B_SENT5_B_IN functionality */,
  {(uint16)110, (uint8)7, (uint16)18}
  /* Settings information for pad 111 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 112 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 113 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_TCRCLKA functionality */,
  {(uint16)113, (uint8)1, (uint16)57}
  /* SIU_A_IRQ7 functionality */,
  {(uint16)113, (uint8)2, (uint16)58}
  /* Settings information for pad 114 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA0_IN functionality */,
  {(uint16)114, (uint8)1, (uint16)59}
  /* eTPU_A_ETPUA12 functionality */,
  {(uint16)114, (uint8)2, (uint16)60}
  /* Settings information for pad 115 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA1_IN functionality */,
  {(uint16)115, (uint8)1, (uint16)61}
  /* eTPU_A_ETPUA13 functionality */,
  {(uint16)115, (uint8)2, (uint16)62}
  /* Settings information for pad 116 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA2_IN functionality */,
  {(uint16)116, (uint8)1, (uint16)63}
  /* eTPU_A_ETPUA14 functionality */,
  {(uint16)116, (uint8)2, (uint16)64}
  /* REACM_RCH0_A_OUT functionality */,
  {(uint16)116, (uint8)3, (uint16)65}
  /* Settings information for pad 117 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA3_IN functionality */,
  {(uint16)117, (uint8)1, (uint16)66}
  /* eTPU_A_ETPUA15 functionality */,
  {(uint16)117, (uint8)2, (uint16)67}
  /* REACM_RCH1_A_OUT functionality */,
  {(uint16)117, (uint8)3, (uint16)68}
  /* FCCU_ERROR0 functionality */,
  {(uint16)117, (uint8)4, (uint16)69}
  /* Settings information for pad 118 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA4_IN functionality */,
  {(uint16)118, (uint8)1, (uint16)70}
  /* eTPU_A_ETPUA16 functionality */,
  {(uint16)118, (uint8)2, (uint16)71}
  /* REACM_RCH2_A_OUT functionality */,
  {(uint16)118, (uint8)3, (uint16)72}
  /* Settings information for pad 119 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA5_IN functionality */,
  {(uint16)119, (uint8)1, (uint16)73}
  /* eTPU_A_ETPUA17 functionality */,
  {(uint16)119, (uint8)2, (uint16)74}
  /* REACM_RCH3_A_OUT functionality */,
  {(uint16)119, (uint8)3, (uint16)75}
  /* Settings information for pad 120 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA6_IN functionality */,
  {(uint16)120, (uint8)1, (uint16)76}
  /* eTPU_A_ETPUA18 functionality */,
  {(uint16)120, (uint8)2, (uint16)77}
  /* REACM_RCH4_A_OUT functionality */,
  {(uint16)120, (uint8)3, (uint16)78}
  /* Settings information for pad 121 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA7_IN functionality */,
  {(uint16)121, (uint8)1, (uint16)79}
  /* eTPU_A_ETPUA19 functionality */,
  {(uint16)121, (uint8)2, (uint16)80}
  /* REACM_RCH5_A_OUT functionality */,
  {(uint16)121, (uint8)3, (uint16)81}
  /* Settings information for pad 122 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA8_IN functionality */,
  {(uint16)122, (uint8)1, (uint16)82}
  /* eTPU_A_ETPUA20 functionality */,
  {(uint16)122, (uint8)2, (uint16)83}
  /* REACM_RCH6_A_OUT functionality */,
  {(uint16)122, (uint8)3, (uint16)84}
  /* Settings information for pad 123 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA9_IN functionality */,
  {(uint16)123, (uint8)1, (uint16)85}
  /* eTPU_A_ETPUA21 functionality */,
  {(uint16)123, (uint8)2, (uint16)86}
  /* REACM_RCH7_A_OUT functionality */,
  {(uint16)123, (uint8)3, (uint16)87}
  /* Settings information for pad 124 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA10_IN functionality */,
  {(uint16)124, (uint8)1, (uint16)88}
  /* eTPU_A_ETPUA22 functionality */,
  {(uint16)124, (uint8)2, (uint16)89}
  /* REACM_RCH8_A_OUT functionality */,
  {(uint16)124, (uint8)3, (uint16)90}
  /* FCCU_ERRORIN functionality */,
  {(uint16)124, (uint8)4, (uint16)91}
  /* Settings information for pad 125 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA11_IN functionality */,
  {(uint16)125, (uint8)1, (uint16)92}
  /* eTPU_A_ETPUA23 functionality */,
  {(uint16)125, (uint8)2, (uint16)93}
  /* REACM_RCH9_A_OUT functionality */,
  {(uint16)125, (uint8)3, (uint16)94}
  /* FCCU_ERROR1 functionality */,
  {(uint16)125, (uint8)4, (uint16)95}
  /* Settings information for pad 126 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA12_IN functionality */,
  {(uint16)126, (uint8)1, (uint16)96}
  /* DSPI_B_PCSB1 functionality */,
  {(uint16)126, (uint8)2, (uint16)97}
  /* Settings information for pad 127 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA13_IN functionality */,
  {(uint16)127, (uint8)1, (uint16)98}
  /* DSPI_B_PCSB3 functionality */,
  {(uint16)127, (uint8)2, (uint16)99}
  /* Settings information for pad 128 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA14_IN functionality */,
  {(uint16)128, (uint8)1, (uint16)100}
  /* DSPI_B_PCSB4 functionality */,
  {(uint16)128, (uint8)2, (uint16)101}
  /* Settings information for pad 129 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA15_IN functionality */,
  {(uint16)129, (uint8)1, (uint16)102}
  /* DSPI_B_PCSB5 functionality */,
  {(uint16)129, (uint8)2, (uint16)103}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)129, (uint8)3, (uint16)104}
  /* Settings information for pad 130 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA16_IN functionality */,
  {(uint16)130, (uint8)1, (uint16)105}
  /* DSPI_D_PCSD1 functionality */,
  {(uint16)130, (uint8)2, (uint16)106}
  /* Settings information for pad 131 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA17_IN functionality */,
  {(uint16)131, (uint8)1, (uint16)107}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)131, (uint8)2, (uint16)108}
  /* Settings information for pad 132 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA18_IN functionality */,
  {(uint16)132, (uint8)1, (uint16)109}
  /* DSPI_D_PCSD3 functionality */,
  {(uint16)132, (uint8)2, (uint16)110}
  /* Settings information for pad 133 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA19_IN functionality */,
  {(uint16)133, (uint8)1, (uint16)111}
  /* DSPI_D_PCSD4 functionality */,
  {(uint16)133, (uint8)2, (uint16)112}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)133, (uint8)7, (uint16)19}
  /* Settings information for pad 134 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA20_IN functionality */,
  {(uint16)134, (uint8)1, (uint16)113}
  /* SIU_A_IRQ8 functionality */,
  {(uint16)134, (uint8)2, (uint16)114}
  /* Settings information for pad 135 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA21_IN functionality */,
  {(uint16)135, (uint8)1, (uint16)115}
  /* SIU_A_IRQ9 functionality */,
  {(uint16)135, (uint8)2, (uint16)116}
  /* Settings information for pad 136 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA22_IN functionality */,
  {(uint16)136, (uint8)1, (uint16)117}
  /* SIU_A_IRQ10 functionality */,
  {(uint16)136, (uint8)2, (uint16)118}
  /* REACM_RCH0_A_OUT functionality */,
  {(uint16)136, (uint8)3, (uint16)119}
  /* Settings information for pad 137 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA23_IN functionality */,
  {(uint16)137, (uint8)1, (uint16)120}
  /* SIU_A_IRQ11 functionality */,
  {(uint16)137, (uint8)2, (uint16)121}
  /* REACM_RCH1_A_OUT functionality */,
  {(uint16)137, (uint8)3, (uint16)122}
  /* Settings information for pad 138 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA24_OUT functionality */,
  {(uint16)138, (uint8)1, (uint16)123}
  /* SIU_A_IRQ12 functionality */,
  {(uint16)138, (uint8)2, (uint16)124}
  /* REACM_RCH2_A_OUT functionality */,
  {(uint16)138, (uint8)3, (uint16)125}
  /* eTPU_A_ETPUA24_IN functionality */,
  {(uint16)138, (uint8)5, (uint16)20}
  /* Settings information for pad 139 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA25_OUT functionality */,
  {(uint16)139, (uint8)1, (uint16)126}
  /* SIU_A_IRQ13 functionality */,
  {(uint16)139, (uint8)2, (uint16)127}
  /* REACM_RCH3_A_OUT functionality */,
  {(uint16)139, (uint8)3, (uint16)128}
  /* eTPU_A_ETPUA25_IN functionality */,
  {(uint16)139, (uint8)5, (uint16)21}
  /* Settings information for pad 140 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA26_OUT functionality */,
  {(uint16)140, (uint8)1, (uint16)129}
  /* SIU_A_IRQ14 functionality */,
  {(uint16)140, (uint8)2, (uint16)130}
  /* REACM_RCH4_A_OUT functionality */,
  {(uint16)140, (uint8)3, (uint16)131}
  /* eTPU_A_ETPUA26_IN functionality */,
  {(uint16)140, (uint8)5, (uint16)22}
  /* Settings information for pad 141 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA27_OUT functionality */,
  {(uint16)141, (uint8)1, (uint16)132}
  /* SIU_A_IRQ15 functionality */,
  {(uint16)141, (uint8)2, (uint16)133}
  /* REACM_RCH5_A_OUT functionality */,
  {(uint16)141, (uint8)3, (uint16)134}
  /* eTPU_A_ETPUA27_IN functionality */,
  {(uint16)141, (uint8)5, (uint16)23}
  /* Settings information for pad 142 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA28_OUT functionality */,
  {(uint16)142, (uint8)1, (uint16)135}
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)142, (uint8)2, (uint16)136}
  /* REACM_RCH6_A_OUT functionality */,
  {(uint16)142, (uint8)3, (uint16)137}
  /* eTPU_A_ETPUA28_IN functionality */,
  {(uint16)142, (uint8)5, (uint16)24}
  /* Settings information for pad 143 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA29_OUT functionality */,
  {(uint16)143, (uint8)1, (uint16)138}
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)143, (uint8)2, (uint16)139}
  /* REACM_RCH7_A_OUT functionality */,
  {(uint16)143, (uint8)3, (uint16)140}
  /* eTPU_A_ETPUA29_IN functionality */,
  {(uint16)143, (uint8)5, (uint16)25}
  /* Settings information for pad 144 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA30_OUT functionality */,
  {(uint16)144, (uint8)1, (uint16)141}
  /* DSPI_C_PCSC3 functionality */,
  {(uint16)144, (uint8)2, (uint16)142}
  /* REACM_RCH8_A_OUT functionality */,
  {(uint16)144, (uint8)3, (uint16)143}
  /* eTPU_A_ETPUA30_IN functionality */,
  {(uint16)144, (uint8)5, (uint16)26}
  /* Settings information for pad 145 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA31_OUT functionality */,
  {(uint16)145, (uint8)1, (uint16)144}
  /* DSPI_C_PCSC4 functionality */,
  {(uint16)145, (uint8)2, (uint16)145}
  /* REACM_RCH9_A_OUT functionality */,
  {(uint16)145, (uint8)3, (uint16)146}
  /* eTPU_A_ETPUA31_IN functionality */,
  {(uint16)145, (uint8)5, (uint16)27}
  /* Settings information for pad 146 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_TCRCLKB functionality */,
  {(uint16)146, (uint8)1, (uint16)147}
  /* SIU_A_IRQ6 functionality */,
  {(uint16)146, (uint8)6, (uint16)28}
  /* Settings information for pad 147 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB0_IN functionality */,
  {(uint16)147, (uint8)1, (uint16)148}
  /* eTPU_B_ETPUB16 functionality */,
  {(uint16)147, (uint8)2, (uint16)149}
  /* Settings information for pad 148 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB1_IN functionality */,
  {(uint16)148, (uint8)1, (uint16)150}
  /* eTPU_B_ETPUB17 functionality */,
  {(uint16)148, (uint8)2, (uint16)151}
  /* Settings information for pad 149 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB2_IN functionality */,
  {(uint16)149, (uint8)1, (uint16)152}
  /* eTPU_B_ETPUB18 functionality */,
  {(uint16)149, (uint8)2, (uint16)153}
  /* Settings information for pad 150 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB3_IN functionality */,
  {(uint16)150, (uint8)1, (uint16)154}
  /* eTPU_B_ETPUB19 functionality */,
  {(uint16)150, (uint8)2, (uint16)155}
  /* Settings information for pad 151 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB4_IN functionality */,
  {(uint16)151, (uint8)1, (uint16)156}
  /* eTPU_B_ETPUB20 functionality */,
  {(uint16)151, (uint8)2, (uint16)157}
  /* Settings information for pad 152 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB5_IN functionality */,
  {(uint16)152, (uint8)1, (uint16)158}
  /* eTPU_B_ETPUB21 functionality */,
  {(uint16)152, (uint8)2, (uint16)159}
  /* Settings information for pad 153 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB6_IN functionality */,
  {(uint16)153, (uint8)1, (uint16)160}
  /* eTPU_B_ETPUB22 functionality */,
  {(uint16)153, (uint8)2, (uint16)161}
  /* Settings information for pad 154 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB7_IN functionality */,
  {(uint16)154, (uint8)1, (uint16)162}
  /* eTPU_B_ETPUB23 functionality */,
  {(uint16)154, (uint8)2, (uint16)163}
  /* Settings information for pad 155 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB8_IN functionality */,
  {(uint16)155, (uint8)1, (uint16)164}
  /* eTPU_B_ETPUB24 functionality */,
  {(uint16)155, (uint8)2, (uint16)165}
  /* Settings information for pad 156 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB9_IN functionality */,
  {(uint16)156, (uint8)1, (uint16)166}
  /* eTPU_B_ETPUB25 functionality */,
  {(uint16)156, (uint8)2, (uint16)167}
  /* Settings information for pad 157 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB10_IN functionality */,
  {(uint16)157, (uint8)1, (uint16)168}
  /* eTPU_B_ETPUB26 functionality */,
  {(uint16)157, (uint8)2, (uint16)169}
  /* Settings information for pad 158 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB11_IN functionality */,
  {(uint16)158, (uint8)1, (uint16)170}
  /* eTPU_B_ETPUB27 functionality */,
  {(uint16)158, (uint8)2, (uint16)171}
  /* Settings information for pad 159 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB12_IN functionality */,
  {(uint16)159, (uint8)1, (uint16)172}
  /* eTPU_B_ETPUB28 functionality */,
  {(uint16)159, (uint8)2, (uint16)173}
  /* Settings information for pad 160 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB13_IN functionality */,
  {(uint16)160, (uint8)1, (uint16)174}
  /* eTPU_B_ETPUB29 functionality */,
  {(uint16)160, (uint8)2, (uint16)175}
  /* Settings information for pad 161 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB14_IN functionality */,
  {(uint16)161, (uint8)1, (uint16)176}
  /* eTPU_B_ETPUB30 functionality */,
  {(uint16)161, (uint8)2, (uint16)177}
  /* Settings information for pad 162 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB15_IN functionality */,
  {(uint16)162, (uint8)1, (uint16)178}
  /* eTPU_B_ETPUB31 functionality */,
  {(uint16)162, (uint8)2, (uint16)179}
  /* Settings information for pad 163 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB16_IN functionality */,
  {(uint16)163, (uint8)1, (uint16)180}
  /* DSPI_A_PCSA1 functionality */,
  {(uint16)163, (uint8)2, (uint16)181}
  /* Settings information for pad 164 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB17_IN functionality */,
  {(uint16)164, (uint8)1, (uint16)182}
  /* DSPI_A_PCSA2 functionality */,
  {(uint16)164, (uint8)2, (uint16)183}
  /* Settings information for pad 165 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB18_IN functionality */,
  {(uint16)165, (uint8)1, (uint16)184}
  /* DSPI_A_PCSA3 functionality */,
  {(uint16)165, (uint8)2, (uint16)185}
  /* Settings information for pad 166 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB19_IN functionality */,
  {(uint16)166, (uint8)1, (uint16)186}
  /* DSPI_A_PCSA4 functionality */,
  {(uint16)166, (uint8)2, (uint16)187}
  /* Settings information for pad 167 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB20_IN functionality */,
  {(uint16)167, (uint8)1, (uint16)188}
  /* Settings information for pad 168 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB21_IN functionality */,
  {(uint16)168, (uint8)1, (uint16)189}
  /* Settings information for pad 169 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB22_IN functionality */,
  {(uint16)169, (uint8)1, (uint16)190}
  /* REACM_RCH0_B_OUT functionality */,
  {(uint16)169, (uint8)2, (uint16)191}
  /* Settings information for pad 170 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB23_IN functionality */,
  {(uint16)170, (uint8)1, (uint16)192}
  /* REACM_RCH1_B_OUT functionality */,
  {(uint16)170, (uint8)2, (uint16)193}
  /* Settings information for pad 171 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB24_IN functionality */,
  {(uint16)171, (uint8)1, (uint16)194}
  /* REACM_RCH2_B_OUT functionality */,
  {(uint16)171, (uint8)2, (uint16)195}
  /* Settings information for pad 172 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB25_IN functionality */,
  {(uint16)172, (uint8)1, (uint16)196}
  /* REACM_RCH3_B_OUT functionality */,
  {(uint16)172, (uint8)2, (uint16)197}
  /* Settings information for pad 173 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB26_IN functionality */,
  {(uint16)173, (uint8)1, (uint16)198}
  /* REACM_RCH4_B_OUT functionality */,
  {(uint16)173, (uint8)2, (uint16)199}
  /* Settings information for pad 174 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB27_IN functionality */,
  {(uint16)174, (uint8)1, (uint16)200}
  /* REACM_RCH5_B_OUT functionality */,
  {(uint16)174, (uint8)2, (uint16)201}
  /* Settings information for pad 175 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB28_IN functionality */,
  {(uint16)175, (uint8)1, (uint16)202}
  /* REACM_RCH6_B_OUT functionality */,
  {(uint16)175, (uint8)2, (uint16)203}
  /* Settings information for pad 176 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB29_IN functionality */,
  {(uint16)176, (uint8)1, (uint16)204}
  /* REACM_RCH7_B_OUT functionality */,
  {(uint16)176, (uint8)2, (uint16)205}
  /* Settings information for pad 177 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB30_IN functionality */,
  {(uint16)177, (uint8)1, (uint16)206}
  /* REACM_RCH8_B_OUT functionality */,
  {(uint16)177, (uint8)2, (uint16)207}
  /* Settings information for pad 178 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB31_IN functionality */,
  {(uint16)178, (uint8)1, (uint16)208}
  /* REACM_RCH9_B_OUT functionality */,
  {(uint16)178, (uint8)2, (uint16)209}
  /* Settings information for pad 179 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS0_IN functionality */,
  {(uint16)179, (uint8)1, (uint16)210}
  /* eTPU_A_ETPUA0 functionality */,
  {(uint16)179, (uint8)2, (uint16)211}
  /* REACM_RCH0_C_OUT functionality */,
  {(uint16)179, (uint8)3, (uint16)212}
  /* Settings information for pad 180 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS1_IN functionality */,
  {(uint16)180, (uint8)1, (uint16)213}
  /* eTPU_A_ETPUA1 functionality */,
  {(uint16)180, (uint8)2, (uint16)214}
  /* REACM_RCH1_C_OUT functionality */,
  {(uint16)180, (uint8)3, (uint16)215}
  /* DSPI_E_PCSE2 functionality */,
  {(uint16)180, (uint8)4, (uint16)216}
  /* Settings information for pad 181 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS2_IN functionality */,
  {(uint16)181, (uint8)1, (uint16)217}
  /* eTPU_A_ETPUA2 functionality */,
  {(uint16)181, (uint8)2, (uint16)218}
  /* REACM_RCH2_C_OUT functionality */,
  {(uint16)181, (uint8)3, (uint16)219}
  /* DSPI_E_PCSE3 functionality */,
  {(uint16)181, (uint8)4, (uint16)220}
  /* Settings information for pad 182 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS3_IN functionality */,
  {(uint16)182, (uint8)1, (uint16)221}
  /* eTPU_A_ETPUA3 functionality */,
  {(uint16)182, (uint8)2, (uint16)222}
  /* REACM_RCH3_C_OUT functionality */,
  {(uint16)182, (uint8)3, (uint16)223}
  /* DSPI_E_PCSE4 functionality */,
  {(uint16)182, (uint8)4, (uint16)224}
  /* Settings information for pad 183 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS4 functionality */,
  {(uint16)183, (uint8)1, (uint16)225}
  /* eTPU_A_ETPUA4 functionality */,
  {(uint16)183, (uint8)2, (uint16)226}
  /* REACM_RCH4_C_OUT functionality */,
  {(uint16)183, (uint8)3, (uint16)227}
  /* DSPI_E_PCSE5 functionality */,
  {(uint16)183, (uint8)4, (uint16)228}
  /* Settings information for pad 184 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS5 functionality */,
  {(uint16)184, (uint8)1, (uint16)229}
  /* eTPU_A_ETPUA5 functionality */,
  {(uint16)184, (uint8)2, (uint16)230}
  /* REACM_RCH5_C_OUT functionality */,
  {(uint16)184, (uint8)3, (uint16)231}
  /* Settings information for pad 185 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS6_IN functionality */,
  {(uint16)185, (uint8)1, (uint16)232}
  /* eTPU_A_ETPUA6 functionality */,
  {(uint16)185, (uint8)2, (uint16)233}
  /* REACM_RCH6_C_OUT functionality */,
  {(uint16)185, (uint8)3, (uint16)234}
  /* Settings information for pad 186 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS7_IN functionality */,
  {(uint16)186, (uint8)1, (uint16)235}
  /* eTPU_A_ETPUA7 functionality */,
  {(uint16)186, (uint8)2, (uint16)236}
  /* REACM_RCH7_C_OUT functionality */,
  {(uint16)186, (uint8)3, (uint16)237}
  /* Settings information for pad 187 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS0_IN functionality */,
  {(uint16)187, (uint8)1, (uint16)238}
  /* eTPU_A_ETPUA8 functionality */,
  {(uint16)187, (uint8)2, (uint16)239}
  /* REACM_RCH8_C_OUT functionality */,
  {(uint16)187, (uint8)3, (uint16)240}
  /* Settings information for pad 188 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS1_IN functionality */,
  {(uint16)188, (uint8)1, (uint16)241}
  /* eTPU_A_ETPUA9 functionality */,
  {(uint16)188, (uint8)2, (uint16)242}
  /* REACM_RCH9_C_OUT functionality */,
  {(uint16)188, (uint8)3, (uint16)243}
  /* Settings information for pad 189 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS2_IN functionality */,
  {(uint16)189, (uint8)1, (uint16)244}
  /* DSPI_D_SCKD_OUT functionality */,
  {(uint16)189, (uint8)2, (uint16)245}
  /* DSPI_D_SCKD_IN functionality */,
  {(uint16)189, (uint8)6, (uint16)29}
  /* Settings information for pad 190 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS3_IN functionality */,
  {(uint16)190, (uint8)1, (uint16)246}
  /* DSPI_D_SIND functionality */,
  {(uint16)190, (uint8)6, (uint16)30}
  /* Settings information for pad 191 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS4_IN functionality */,
  {(uint16)191, (uint8)1, (uint16)247}
  /* DSPI_C_SOUTC functionality */,
  {(uint16)191, (uint8)2, (uint16)248}
  /* Settings information for pad 192 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS5_IN functionality */,
  {(uint16)192, (uint8)1, (uint16)249}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)192, (uint8)2, (uint16)250}
  /* Settings information for pad 193 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS6 functionality */,
  {(uint16)193, (uint8)1, (uint16)251}
  /* FlexCAN_D_CNTXD functionality */,
  {(uint16)193, (uint8)3, (uint16)252}
  /* REACM_RCH0_C_OUT functionality */,
  {(uint16)193, (uint8)4, (uint16)253}
  /* SIU_A_IRQ0 functionality */,
  {(uint16)193, (uint8)6, (uint16)31}
  /* Settings information for pad 194 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS7 functionality */,
  {(uint16)194, (uint8)1, (uint16)254}
  /* REACM_RCH1_C_OUT functionality */,
  {(uint16)194, (uint8)4, (uint16)255}
  /* SIU_A_IRQ1_IN functionality */,
  {(uint16)194, (uint8)6, (uint16)32}
  /* FlexCAN_D_CNRXD_IN functionality */,
  {(uint16)194, (uint8)7, (uint16)33}
  /* Settings information for pad 195 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS16_OUT functionality */,
  {(uint16)195, (uint8)1, (uint16)256}
  /* eTPU_B_ETPUB0 functionality */,
  {(uint16)195, (uint8)2, (uint16)257}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)195, (uint8)3, (uint16)258}
  /* REACM_RCH2_C_OUT functionality */,
  {(uint16)195, (uint8)4, (uint16)259}
  /* eMIOS_A_EMIOS16_IN functionality */,
  {(uint16)195, (uint8)5, (uint16)34}
  /* Settings information for pad 196 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS17_OUT functionality */,
  {(uint16)196, (uint8)1, (uint16)260}
  /* eTPU_B_ETPUB1 functionality */,
  {(uint16)196, (uint8)2, (uint16)261}
  /* REACM_RCH3_C_OUT functionality */,
  {(uint16)196, (uint8)4, (uint16)262}
  /* eMIOS_A_EMIOS17_IN functionality */,
  {(uint16)196, (uint8)5, (uint16)35}
  /* MCAN_1_RX_IN functionality */,
  {(uint16)196, (uint8)7, (uint16)36}
  /* Settings information for pad 197 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS18_OUT functionality */,
  {(uint16)197, (uint8)1, (uint16)263}
  /* eTPU_B_ETPUB2 functionality */,
  {(uint16)197, (uint8)2, (uint16)264}
  /* REACM_RCH4_C_OUT functionality */,
  {(uint16)197, (uint8)3, (uint16)265}
  /* eMIOS_A_EMIOS18_IN functionality */,
  {(uint16)197, (uint8)5, (uint16)37}
  /* Settings information for pad 198 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS19_OUT functionality */,
  {(uint16)198, (uint8)1, (uint16)266}
  /* eTPU_B_ETPUB3 functionality */,
  {(uint16)198, (uint8)2, (uint16)267}
  /* REACM_RCH5_C_OUT functionality */,
  {(uint16)198, (uint8)3, (uint16)268}
  /* eMIOS_A_EMIOS19_IN functionality */,
  {(uint16)198, (uint8)5, (uint16)38}
  /* Settings information for pad 199 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS20_OUT functionality */,
  {(uint16)199, (uint8)1, (uint16)269}
  /* eTPU_B_ETPUB4 functionality */,
  {(uint16)199, (uint8)2, (uint16)270}
  /* REACM_RCH6_C_OUT functionality */,
  {(uint16)199, (uint8)3, (uint16)271}
  /* eMIOS_A_EMIOS20_IN functionality */,
  {(uint16)199, (uint8)5, (uint16)39}
  /* Settings information for pad 200 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS21_OUT functionality */,
  {(uint16)200, (uint8)1, (uint16)272}
  /* eTPU_B_ETPUB5 functionality */,
  {(uint16)200, (uint8)2, (uint16)273}
  /* REACM_RCH7_C_OUT functionality */,
  {(uint16)200, (uint8)3, (uint16)274}
  /* eMIOS_A_EMIOS21_IN functionality */,
  {(uint16)200, (uint8)5, (uint16)40}
  /* Settings information for pad 201 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS22_OUT functionality */,
  {(uint16)201, (uint8)1, (uint16)275}
  /* eTPU_B_ETPUB6 functionality */,
  {(uint16)201, (uint8)2, (uint16)276}
  /* REACM_RCH8_C_OUT functionality */,
  {(uint16)201, (uint8)3, (uint16)277}
  /* eMIOS_A_EMIOS22_IN functionality */,
  {(uint16)201, (uint8)5, (uint16)41}
  /* Settings information for pad 202 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS23_OUT functionality */,
  {(uint16)202, (uint8)1, (uint16)278}
  /* eTPU_B_ETPUB7 functionality */,
  {(uint16)202, (uint8)2, (uint16)279}
  /* REACM_RCH9_C_OUT functionality */,
  {(uint16)202, (uint8)3, (uint16)280}
  /* eMIOS_A_EMIOS23_IN functionality */,
  {(uint16)202, (uint8)5, (uint16)42}
  /* Settings information for pad 203 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS16_OUT functionality */,
  {(uint16)203, (uint8)1, (uint16)281}
  /* DSPI_B_PCSB0_OUT functionality */,
  {(uint16)203, (uint8)2, (uint16)282}
  /* eMIOS_B_EMIOS16_IN functionality */,
  {(uint16)203, (uint8)5, (uint16)43}
  /* DSPI_B_PCSB0_IN functionality */,
  {(uint16)203, (uint8)6, (uint16)44}
  /* Settings information for pad 204 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS17_OUT functionality */,
  {(uint16)204, (uint8)1, (uint16)283}
  /* DSPI_B_PCSB1 functionality */,
  {(uint16)204, (uint8)2, (uint16)284}
  /* eMIOS_B_EMIOS17_IN functionality */,
  {(uint16)204, (uint8)5, (uint16)45}
  /* Settings information for pad 205 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 206 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 207 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 208 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_PLLCFG0_IN functionality */,
  {(uint16)208, (uint8)1, (uint16)285}
  /* eTPU_C_ETPUC9_OUT functionality */,
  {(uint16)208, (uint8)3, (uint16)286}
  /* SIPI_TXN functionality */,
  {(uint16)208, (uint8)4, (uint16)287}
  /* SIU_A_IRQ4_IN functionality */,
  {(uint16)208, (uint8)6, (uint16)46}
  /* eTPU_C_ETPUC9_IN functionality */,
  {(uint16)208, (uint8)7, (uint16)47}
  /* Settings information for pad 209 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_PLLCFG1_IN functionality */,
  {(uint16)209, (uint8)1, (uint16)288}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)209, (uint8)3, (uint16)289}
  /* SIPI_TXP functionality */,
  {(uint16)209, (uint8)4, (uint16)290}
  /* SIU_A_IRQ5_IN functionality */,
  {(uint16)209, (uint8)6, (uint16)48}
  /* Settings information for pad 210 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_PLLCFG2_IN functionality */,
  {(uint16)210, (uint8)1, (uint16)291}
  /* eTPU_C_ETPUC3_OUT functionality */,
  {(uint16)210, (uint8)2, (uint16)292}
  /* DSPI_E_PCSE1 functionality */,
  {(uint16)210, (uint8)3, (uint16)293}
  /* SIPI_REFCLK_IN functionality */,
  {(uint16)210, (uint8)4, (uint16)294}
  /* eTPU_C_ETPUC3_IN functionality */,
  {(uint16)210, (uint8)6, (uint16)49}
  /* Settings information for pad 211 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 212 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_BOOTCFG1_IN functionality */,
  {(uint16)212, (uint8)1, (uint16)295}
  /* eTPU_C_ETPUC0_OUT functionality */,
  {(uint16)212, (uint8)3, (uint16)296}
  /* SIPI_RXP functionality */,
  {(uint16)212, (uint8)4, (uint16)297}
  /* SIU_A_IRQ3_IN functionality */,
  {(uint16)212, (uint8)6, (uint16)50}
  /* eTPU_C_ETPUC0_IN functionality */,
  {(uint16)212, (uint8)7, (uint16)51}
  /* Settings information for pad 213 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_WKPCFG_IN functionality */,
  {(uint16)213, (uint8)1, (uint16)298}
  /* SIU_A_NMI_IN functionality */,
  {(uint16)213, (uint8)2, (uint16)299}
  /* eTPU_C_ETPUC1_OUT functionality */,
  {(uint16)213, (uint8)3, (uint16)300}
  /* SIPI_RXN functionality */,
  {(uint16)213, (uint8)4, (uint16)301}
  /* eTPU_C_ETPUC1_IN functionality */,
  {(uint16)213, (uint8)7, (uint16)52}
  /* Settings information for pad 214 {PCR, Mode, Index to Mux or Inmux table} */
  /* ENGCLK functionality */,
  {(uint16)214, (uint8)1, (uint16)302}
  /* Settings information for pad 215 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 216 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 217 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 218 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 219 {PCR, Mode, Index to Mux or Inmux table} */
  /* MCKO functionality */,
  {(uint16)219, (uint8)1, (uint16)303}
  /* Settings information for pad 220 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 221 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 222 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 223 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_E_TXDE functionality */,
  {(uint16)223, (uint8)6, (uint16)53}
  /* Settings information for pad 224 {PCR, Mode, Index to Mux or Inmux table} */
  /* MSEO0 functionality */,
  {(uint16)224, (uint8)1, (uint16)304}
  /* Settings information for pad 225 {PCR, Mode, Index to Mux or Inmux table} */
  /* MSEO1 functionality */,
  {(uint16)225, (uint8)1, (uint16)305}
  /* Settings information for pad 226 {PCR, Mode, Index to Mux or Inmux table} */
  /* RDY functionality */,
  {(uint16)226, (uint8)1, (uint16)306}
  /* Settings information for pad 227 {PCR, Mode, Index to Mux or Inmux table} */
  /* EVTO functionality */,
  {(uint16)227, (uint8)1, (uint16)307}
  /* Settings information for pad 228 {PCR, Mode, Index to Mux or Inmux table} */
  /* TDO functionality */,
  {(uint16)228, (uint8)1, (uint16)308}
  /* Settings information for pad 229 {PCR, Mode, Index to Mux or Inmux table} */
  /* D_CLKOUT functionality */,
  {(uint16)229, (uint8)1, (uint16)309}
  /* Settings information for pad 230 {PCR, Mode, Index to Mux or Inmux table} */
  /* RSTOUT functionality */,
  {(uint16)230, (uint8)1, (uint16)310}
  /* Settings information for pad 231 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 232 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 233 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 234 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 235 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_SCKC_OUT functionality */,
  {(uint16)235, (uint8)1, (uint16)311}
  /* DSPI_C_SCK_C_LVDS_P functionality */,
  {(uint16)235, (uint8)2, (uint16)312}
  /* DSPI_C_SCKC_IN functionality */,
  {(uint16)235, (uint8)5, (uint16)54}
  /* Settings information for pad 236 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_SCK_C_LVDS_N_OUT functionality */,
  {(uint16)236, (uint8)2, (uint16)313}
  /* DSPI_C_SINC_IN functionality */,
  {(uint16)236, (uint8)5, (uint16)55}
  /* Settings information for pad 237 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_SOUTC functionality */,
  {(uint16)237, (uint8)1, (uint16)314}
  /* DSPI_C_SOUT_C_LVDS_P functionality */,
  {(uint16)237, (uint8)2, (uint16)315}
  /* Settings information for pad 238 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC0_OUT functionality */,
  {(uint16)238, (uint8)1, (uint16)316}
  /* DSPI_C_SOUT_C_LVDS_N_OUT functionality */,
  {(uint16)238, (uint8)2, (uint16)317}
  /* DSPI_C_PCSC0_IN functionality */,
  {(uint16)238, (uint8)5, (uint16)56}
  /* Settings information for pad 239 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)239, (uint8)1, (uint16)318}
  /* eSCI_D_TXDD functionality */,
  {(uint16)239, (uint8)2, (uint16)319}
  /* Settings information for pad 240 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)240, (uint8)1, (uint16)320}
  /* DSPI_D_SCK_D_LVDS_P functionality */,
  {(uint16)240, (uint8)2, (uint16)321}
  /* DSPI_D_SCKD_OUT functionality */,
  {(uint16)240, (uint8)3, (uint16)322}
  /* DSPI_D_SCKD_IN functionality */,
  {(uint16)240, (uint8)7, (uint16)57}
  /* Settings information for pad 241 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC3 functionality */,
  {(uint16)241, (uint8)1, (uint16)323}
  /* DSPI_D_SCK_D_LVDS_N_OUT functionality */,
  {(uint16)241, (uint8)2, (uint16)324}
  /* DSPI_D_SIND_IN functionality */,
  {(uint16)241, (uint8)7, (uint16)58}
  /* Settings information for pad 242 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC4 functionality */,
  {(uint16)242, (uint8)1, (uint16)325}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)242, (uint8)2, (uint16)326}
  /* DSPI_D_SOUT_D_LVDS_P functionality */,
  {(uint16)242, (uint8)3, (uint16)327}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)242, (uint8)4, (uint16)328}
  /* Settings information for pad 243 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC5 functionality */,
  {(uint16)243, (uint8)1, (uint16)329}
  /* DSPI_D_SOUT_D_LVDS_N_OUT functionality */,
  {(uint16)243, (uint8)3, (uint16)330}
  /* DSPI_D_PCSD0_OUT functionality */,
  {(uint16)243, (uint8)4, (uint16)331}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)243, (uint8)6, (uint16)59}
  /* DSPI_D_PCSD0_IN functionality */,
  {(uint16)243, (uint8)8, (uint16)60}
  /* Settings information for pad 244 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_C_TXDC functionality */,
  {(uint16)244, (uint8)1, (uint16)332}
  /* eQADC_A_eQADC_B_ETRIG0_IN functionality */,
  {(uint16)244, (uint8)2, (uint16)333}
  /* Settings information for pad 245 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_C_RXDC_IN functionality */,
  {(uint16)245, (uint8)1, (uint16)334}
  /* Settings information for pad 246 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_D_CNTXD functionality */,
  {(uint16)246, (uint8)1, (uint16)335}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)246, (uint8)3, (uint16)336}
  /* Settings information for pad 247 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_D_CNRXD_IN functionality */,
  {(uint16)247, (uint8)5, (uint16)61}
  /* MCAN_1_RX_IN functionality */,
  {(uint16)247, (uint8)7, (uint16)62}
  /* Settings information for pad 248 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXD0_OUT functionality */,
  {(uint16)248, (uint8)1, (uint16)337}
  /* SENT_A_SENT0_A_IN functionality */,
  {(uint16)248, (uint8)6, (uint16)63}
  /* Settings information for pad 249 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_RX_DV_IN functionality */,
  {(uint16)249, (uint8)1, (uint16)338}
  /* SENT_A_SENT1_A_IN functionality */,
  {(uint16)249, (uint8)6, (uint16)64}
  /* Settings information for pad 250 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_RXD0_IN functionality */,
  {(uint16)250, (uint8)1, (uint16)339}
  /* SENT_A_SENT2_A_IN functionality */,
  {(uint16)250, (uint8)6, (uint16)65}
  /* Settings information for pad 251 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXD1_OUT functionality */,
  {(uint16)251, (uint8)1, (uint16)340}
  /* SENT_A_SENT3_A_IN functionality */,
  {(uint16)251, (uint8)6, (uint16)66}
  /* Settings information for pad 252 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXEN_OUT functionality */,
  {(uint16)252, (uint8)1, (uint16)341}
  /* SENT_A_SENT4_A_IN functionality */,
  {(uint16)252, (uint8)6, (uint16)67}
  /* Settings information for pad 253 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_RXD1_IN functionality */,
  {(uint16)253, (uint8)1, (uint16)342}
  /* SENT_A_SENT5_A_IN functionality */,
  {(uint16)253, (uint8)6, (uint16)68}
  /* Settings information for pad 254 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 255 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 256 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 257 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 258 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 259 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 260 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 261 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 262 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 263 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 264 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 265 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 266 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 267 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 268 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 269 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 270 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 271 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 272 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 273 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 274 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 275 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 276 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 277 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 278 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 279 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 280 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 281 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 282 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 283 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 284 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 285 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 286 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 287 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 288 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 289 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 290 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 291 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 292 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 293 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 294 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 295 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 296 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 297 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 298 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 299 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 300 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 301 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 302 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 303 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 304 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 305 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 306 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 307 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 308 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 309 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 310 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 311 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 312 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 313 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 314 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 315 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 316 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 317 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 318 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 319 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 320 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 321 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 322 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 323 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 324 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 325 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 326 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 327 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 328 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 329 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 330 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 331 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 332 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 333 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 334 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 335 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 336 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 337 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 338 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 339 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 340 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 341 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 342 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 343 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 344 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 345 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 346 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 347 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 348 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 349 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 350 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 351 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 352 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 353 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 354 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 355 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 356 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 357 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 358 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 359 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 360 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 361 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 362 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 363 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 364 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 365 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 366 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 367 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 368 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 369 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 370 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 371 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 372 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 373 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 374 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 375 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 376 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 377 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 378 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 379 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 380 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 381 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 382 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 383 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 384 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 385 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 386 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 387 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 388 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 389 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 390 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 391 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 392 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 393 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 394 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 395 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 396 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 397 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 398 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 399 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 400 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 401 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 402 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 403 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 404 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 405 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 406 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 407 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 408 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 409 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 410 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 411 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 412 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 413 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 414 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 415 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 416 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 417 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 418 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 419 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 420 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 421 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 422 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 423 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 424 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 425 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 426 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 427 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 428 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 429 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 430 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 431 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 432 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS18_OUT functionality */,
  {(uint16)432, (uint8)1, (uint16)343}
  /* DSPI_B_PCSB2 functionality */,
  {(uint16)432, (uint8)2, (uint16)344}
  /* eMIOS_B_EMIOS18_IN functionality */,
  {(uint16)432, (uint8)5, (uint16)69}
  /* Settings information for pad 433 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS19_OUT functionality */,
  {(uint16)433, (uint8)1, (uint16)345}
  /* DSPI_B_PCSB3 functionality */,
  {(uint16)433, (uint8)2, (uint16)346}
  /* eMIOS_B_EMIOS19_IN functionality */,
  {(uint16)433, (uint8)5, (uint16)70}
  /* Settings information for pad 434 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS20_OUT functionality */,
  {(uint16)434, (uint8)1, (uint16)347}
  /* DSPI_C_PCSC0_OUT functionality */,
  {(uint16)434, (uint8)2, (uint16)348}
  /* eMIOS_B_EMIOS20_IN functionality */,
  {(uint16)434, (uint8)5, (uint16)71}
  /* DSPI_C_PCSC0_IN functionality */,
  {(uint16)434, (uint8)6, (uint16)72}
  /* Settings information for pad 435 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS21_OUT functionality */,
  {(uint16)435, (uint8)1, (uint16)349}
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)435, (uint8)2, (uint16)350}
  /* eMIOS_B_EMIOS21_IN functionality */,
  {(uint16)435, (uint8)5, (uint16)73}
  /* Settings information for pad 436 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS22_OUT functionality */,
  {(uint16)436, (uint8)1, (uint16)351}
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)436, (uint8)2, (uint16)352}
  /* eMIOS_B_EMIOS22_IN functionality */,
  {(uint16)436, (uint8)5, (uint16)74}
  /* Settings information for pad 437 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS23_OUT functionality */,
  {(uint16)437, (uint8)1, (uint16)353}
  /* DSPI_C_PCSC5 functionality */,
  {(uint16)437, (uint8)2, (uint16)354}
  /* eMIOS_B_EMIOS23_IN functionality */,
  {(uint16)437, (uint8)5, (uint16)75}
  /* Settings information for pad 438 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 439 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 440 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_TCRCLKC_IN functionality */,
  {(uint16)440, (uint8)5, (uint16)76}
  /* SIU_A_IRQ6_IN functionality */,
  {(uint16)440, (uint8)6, (uint16)77}
  /* Settings information for pad 441 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC0_IN functionality */,
  {(uint16)441, (uint8)5, (uint16)78}
  /* SENT_A_SENT0_A_IN functionality */,
  {(uint16)441, (uint8)6, (uint16)79}
  /* Settings information for pad 442 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC1_IN functionality */,
  {(uint16)442, (uint8)5, (uint16)80}
  /* SENT_A_SENT1_A_IN functionality */,
  {(uint16)442, (uint8)6, (uint16)81}
  /* Settings information for pad 443 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC2_IN functionality */,
  {(uint16)443, (uint8)1, (uint16)355}
  /* SENT_A_SENT3_A_IN functionality */,
  {(uint16)443, (uint8)6, (uint16)82}
  /* Settings information for pad 444 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC3_IN functionality */,
  {(uint16)444, (uint8)5, (uint16)83}
  /* SENT_A_SENT4_A_IN functionality */,
  {(uint16)444, (uint8)6, (uint16)84}
  /* Settings information for pad 445 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC4_IN functionality */,
  {(uint16)445, (uint8)1, (uint16)356}
  /* SENT_A_SENT5_A_IN functionality */,
  {(uint16)445, (uint8)6, (uint16)85}
  /* eTPU_C_TCRCLKC_IN functionality */,
  {(uint16)445, (uint8)7, (uint16)86}
  /* Settings information for pad 446 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC5_IN functionality */,
  {(uint16)446, (uint8)1, (uint16)357}
  /* DSPI_E_PCSE2 functionality */,
  {(uint16)446, (uint8)2, (uint16)358}
  /* SENT_B_SENT0_B_IN functionality */,
  {(uint16)446, (uint8)7, (uint16)87}
  /* Settings information for pad 447 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC6_IN functionality */,
  {(uint16)447, (uint8)1, (uint16)359}
  /* DSPI_E_PCSE3 functionality */,
  {(uint16)447, (uint8)2, (uint16)360}
  /* SENT_B_SENT1_B_IN functionality */,
  {(uint16)447, (uint8)7, (uint16)88}
  /* Settings information for pad 448 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC7_IN functionality */,
  {(uint16)448, (uint8)1, (uint16)361}
  /* DSPI_E_PCSE4 functionality */,
  {(uint16)448, (uint8)2, (uint16)362}
  /* SENT_B_SENT2_B_IN functionality */,
  {(uint16)448, (uint8)7, (uint16)89}
  /* Settings information for pad 449 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC8_OUT functionality */,
  {(uint16)449, (uint8)1, (uint16)363}
  /* DSPI_E_PCSE5 functionality */,
  {(uint16)449, (uint8)2, (uint16)364}
  /* eTPU_C_ETPUC8_IN functionality */,
  {(uint16)449, (uint8)5, (uint16)90}
  /* SENT_B_SENT3_B_IN functionality */,
  {(uint16)449, (uint8)7, (uint16)91}
  /* Settings information for pad 450 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC9_IN functionality */,
  {(uint16)450, (uint8)5, (uint16)92}
  /* SIU_A_IRQ0_IN functionality */,
  {(uint16)450, (uint8)6, (uint16)93}
  /* SENT_B_SENT4_B_IN functionality */,
  {(uint16)450, (uint8)7, (uint16)94}
  /* Settings information for pad 451 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC10_OUT functionality */,
  {(uint16)451, (uint8)1, (uint16)365}
  /* eTPU_C_ETPUC10_IN functionality */,
  {(uint16)451, (uint8)5, (uint16)95}
  /* SIU_A_IRQ1_IN functionality */,
  {(uint16)451, (uint8)6, (uint16)96}
  /* SENT_B_SENT5_B_IN functionality */,
  {(uint16)451, (uint8)7, (uint16)97}
  /* Settings information for pad 452 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC11_OUT functionality */,
  {(uint16)452, (uint8)1, (uint16)366}
  /* eTPU_C_ETPUC11_IN functionality */,
  {(uint16)452, (uint8)5, (uint16)98}
  /* SIU_A_IRQ2_IN functionality */,
  {(uint16)452, (uint8)6, (uint16)99}
  /* Settings information for pad 453 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC12_OUT functionality */,
  {(uint16)453, (uint8)1, (uint16)367}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)453, (uint8)3, (uint16)368}
  /* eTPU_C_ETPUC12_IN functionality */,
  {(uint16)453, (uint8)5, (uint16)100}
  /* SIU_A_IRQ3_IN functionality */,
  {(uint16)453, (uint8)6, (uint16)101}
  /* Settings information for pad 454 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC13_OUT functionality */,
  {(uint16)454, (uint8)1, (uint16)369}
  /* PSI5A_SDOUT0_PSI5A_OUT functionality */,
  {(uint16)454, (uint8)3, (uint16)370}
  /* REACM_RCH0_C_OUT functionality */,
  {(uint16)454, (uint8)4, (uint16)371}
  /* eTPU_C_ETPUC13_IN functionality */,
  {(uint16)454, (uint8)5, (uint16)102}
  /* SIU_A_IRQ4_IN functionality */,
  {(uint16)454, (uint8)6, (uint16)103}
  /* Settings information for pad 455 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC14_OUT functionality */,
  {(uint16)455, (uint8)1, (uint16)372}
  /* PSI5A_SDIN0_PSI5A_IN functionality */,
  {(uint16)455, (uint8)3, (uint16)373}
  /* REACM_RCH1_C_OUT functionality */,
  {(uint16)455, (uint8)4, (uint16)374}
  /* eTPU_C_ETPUC14_IN functionality */,
  {(uint16)455, (uint8)5, (uint16)104}
  /* SIU_A_IRQ5_IN functionality */,
  {(uint16)455, (uint8)6, (uint16)105}
  /* Settings information for pad 456 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC15_OUT functionality */,
  {(uint16)456, (uint8)1, (uint16)375}
  /* REACM_RCH2_C_OUT functionality */,
  {(uint16)456, (uint8)3, (uint16)376}
  /* eTPU_C_ETPUC15_IN functionality */,
  {(uint16)456, (uint8)5, (uint16)106}
  /* MCAN_1_RX_IN functionality */,
  {(uint16)456, (uint8)6, (uint16)107}
  /* Settings information for pad 457 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC16_IN functionality */,
  {(uint16)457, (uint8)1, (uint16)377}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)457, (uint8)2, (uint16)378}
  /* REACM_RCH3_C_OUT functionality */,
  {(uint16)457, (uint8)3, (uint16)379}
  /* Settings information for pad 458 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC17_IN functionality */,
  {(uint16)458, (uint8)1, (uint16)380}
  /* eSCI_F_TXDF functionality */,
  {(uint16)458, (uint8)2, (uint16)381}
  /* REACM_RCH4_C_OUT functionality */,
  {(uint16)458, (uint8)3, (uint16)382}
  /* Settings information for pad 459 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC18_IN functionality */,
  {(uint16)459, (uint8)1, (uint16)383}
  /* eSCI_F_RXDF_IN functionality */,
  {(uint16)459, (uint8)2, (uint16)384}
  /* Settings information for pad 460 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC19_IN functionality */,
  {(uint16)460, (uint8)1, (uint16)385}
  /* PSI5A_SDOUT0_PSI5B_OUT functionality */,
  {(uint16)460, (uint8)3, (uint16)386}
  /* eSCI_A_TXDA functionality */,
  {(uint16)460, (uint8)6, (uint16)108}
  /* Settings information for pad 461 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC20_IN functionality */,
  {(uint16)461, (uint8)1, (uint16)387}
  /* PSI5A_SDIN0_PSI5B_IN functionality */,
  {(uint16)461, (uint8)3, (uint16)388}
  /* eSCI_A_RXDA_IN functionality */,
  {(uint16)461, (uint8)6, (uint16)109}
  /* Settings information for pad 462 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC21_IN functionality */,
  {(uint16)462, (uint8)1, (uint16)389}
  /* eSCI_B_TXDB functionality */,
  {(uint16)462, (uint8)6, (uint16)110}
  /* Settings information for pad 463 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC22_IN functionality */,
  {(uint16)463, (uint8)1, (uint16)390}
  /* eSCI_B_RXDB_IN functionality */,
  {(uint16)463, (uint8)6, (uint16)111}
  /* Settings information for pad 464 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC23_IN functionality */,
  {(uint16)464, (uint8)1, (uint16)391}
  /* DSPI_D_PCSD5 functionality */,
  {(uint16)464, (uint8)2, (uint16)392}
  /* eQADC_A_MAA0 functionality */,
  {(uint16)464, (uint8)3, (uint16)393}
  /* eQADC_B_MAB0 functionality */,
  {(uint16)464, (uint8)4, (uint16)394}
  /* Settings information for pad 465 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC24_IN functionality */,
  {(uint16)465, (uint8)1, (uint16)395}
  /* DSPI_D_PCSD4 functionality */,
  {(uint16)465, (uint8)2, (uint16)396}
  /* eQADC_A_MAA1 functionality */,
  {(uint16)465, (uint8)3, (uint16)397}
  /* eQADC_B_MAB1 functionality */,
  {(uint16)465, (uint8)4, (uint16)398}
  /* Settings information for pad 466 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC25_IN functionality */,
  {(uint16)466, (uint8)1, (uint16)399}
  /* DSPI_D_PCSD3 functionality */,
  {(uint16)466, (uint8)2, (uint16)400}
  /* eQADC_A_MAA2 functionality */,
  {(uint16)466, (uint8)3, (uint16)401}
  /* eQADC_B_MAB2 functionality */,
  {(uint16)466, (uint8)4, (uint16)402}
  /* Settings information for pad 467 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC26_IN functionality */,
  {(uint16)467, (uint8)1, (uint16)403}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)467, (uint8)2, (uint16)404}
  /* eQADC_B_MAB0 functionality */,
  {(uint16)467, (uint8)3, (uint16)405}
  /* Settings information for pad 468 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC27_IN functionality */,
  {(uint16)468, (uint8)1, (uint16)406}
  /* DSPI_D_PCSD1 functionality */,
  {(uint16)468, (uint8)2, (uint16)407}
  /* REACM_RCH5_C_OUT functionality */,
  {(uint16)468, (uint8)3, (uint16)408}
  /* eQADC_B_MAB1 functionality */,
  {(uint16)468, (uint8)4, (uint16)409}
  /* Settings information for pad 469 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC28_IN functionality */,
  {(uint16)469, (uint8)1, (uint16)410}
  /* DSPI_D_PCSD0_OUT functionality */,
  {(uint16)469, (uint8)2, (uint16)411}
  /* REACM_RCH6_C_OUT functionality */,
  {(uint16)469, (uint8)3, (uint16)412}
  /* eQADC_B_MAB2 functionality */,
  {(uint16)469, (uint8)4, (uint16)413}
  /* DSPI_D_PCSD0_IN functionality */,
  {(uint16)469, (uint8)6, (uint16)112}
  /* Settings information for pad 470 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC29_IN functionality */,
  {(uint16)470, (uint8)1, (uint16)414}
  /* DSPI_D_SCKD_OUT functionality */,
  {(uint16)470, (uint8)2, (uint16)415}
  /* REACM_RCH7_C_OUT functionality */,
  {(uint16)470, (uint8)3, (uint16)416}
  /* DSPI_D_SCKD_IN functionality */,
  {(uint16)470, (uint8)6, (uint16)113}
  /* Settings information for pad 471 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC30_IN functionality */,
  {(uint16)471, (uint8)1, (uint16)417}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)471, (uint8)2, (uint16)418}
  /* REACM_RCH8_C_OUT functionality */,
  {(uint16)471, (uint8)3, (uint16)419}
  /* Settings information for pad 472 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC31_IN functionality */,
  {(uint16)472, (uint8)1, (uint16)420}
  /* REACM_RCH9_C_OUT functionality */,
  {(uint16)472, (uint8)3, (uint16)421}
  /* DSPI_D_SIND_IN functionality */,
  {(uint16)472, (uint8)6, (uint16)114}
  /* Settings information for pad 473 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 474 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXCLK_REFCLK_IN functionality */,
  {(uint16)474, (uint8)1, (uint16)422}
  /* SENT_B_SENT0_B_IN functionality */,
  {(uint16)474, (uint8)6, (uint16)115}
  /* Settings information for pad 475 {PCR, Mode, Index to Mux or Inmux table} */
  /* SENT_A_SENT2_A_IN functionality */,
  {(uint16)475, (uint8)5, (uint16)116}
  /* Settings information for pad 476 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA31_IN functionality */,
  {(uint16)476, (uint8)6, (uint16)117}
  /* eMIOS_A_EMIOS16_IN functionality */,
  {(uint16)476, (uint8)7, (uint16)118}
  /* Settings information for pad 477 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA30_IN functionality */,
  {(uint16)477, (uint8)6, (uint16)119}
  /* eMIOS_A_EMIOS17_IN functionality */,
  {(uint16)477, (uint8)7, (uint16)120}
  /* Settings information for pad 478 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA29_IN functionality */,
  {(uint16)478, (uint8)6, (uint16)121}
  /* eMIOS_A_EMIOS18_IN functionality */,
  {(uint16)478, (uint8)7, (uint16)122}
  /* Settings information for pad 479 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA28_IN functionality */,
  {(uint16)479, (uint8)6, (uint16)123}
  /* eMIOS_A_EMIOS19_IN functionality */,
  {(uint16)479, (uint8)7, (uint16)124}
  /* Settings information for pad 480 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA27_IN functionality */,
  {(uint16)480, (uint8)6, (uint16)125}
  /* eMIOS_A_EMIOS20_IN functionality */,
  {(uint16)480, (uint8)7, (uint16)126}
  /* Settings information for pad 481 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA26_IN functionality */,
  {(uint16)481, (uint8)6, (uint16)127}
  /* eMIOS_A_EMIOS21_IN functionality */,
  {(uint16)481, (uint8)7, (uint16)128}
  /* Settings information for pad 482 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA25_IN functionality */,
  {(uint16)482, (uint8)6, (uint16)129}
  /* eMIOS_A_EMIOS22_IN functionality */,
  {(uint16)482, (uint8)7, (uint16)130}
  /* Settings information for pad 483 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA24_IN functionality */,
  {(uint16)483, (uint8)6, (uint16)131}
  /* eMIOS_A_EMIOS23_IN functionality */,
  {(uint16)483, (uint8)7, (uint16)132}
  /* Settings information for pad 484 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC15_IN functionality */,
  {(uint16)484, (uint8)6, (uint16)133}
  /* eMIOS_B_EMIOS16_IN functionality */,
  {(uint16)484, (uint8)7, (uint16)134}
  /* Settings information for pad 485 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC14_IN functionality */,
  {(uint16)485, (uint8)6, (uint16)135}
  /* eMIOS_B_EMIOS17_IN functionality */,
  {(uint16)485, (uint8)7, (uint16)136}
  /* Settings information for pad 486 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC13_IN functionality */,
  {(uint16)486, (uint8)6, (uint16)137}
  /* eMIOS_B_EMIOS18_IN functionality */,
  {(uint16)486, (uint8)7, (uint16)138}
  /* Settings information for pad 487 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC12_IN functionality */,
  {(uint16)487, (uint8)6, (uint16)139}
  /* eMIOS_B_EMIOS19_IN functionality */,
  {(uint16)487, (uint8)7, (uint16)140}
  /* Settings information for pad 488 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC11_IN functionality */,
  {(uint16)488, (uint8)6, (uint16)141}
  /* eMIOS_B_EMIOS20_IN functionality */,
  {(uint16)488, (uint8)7, (uint16)142}
  /* Settings information for pad 489 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC10_IN functionality */,
  {(uint16)489, (uint8)6, (uint16)143}
  /* eMIOS_B_EMIOS21_IN functionality */,
  {(uint16)489, (uint8)7, (uint16)144}
  /* Settings information for pad 490 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC9_IN functionality */,
  {(uint16)490, (uint8)6, (uint16)145}
  /* eMIOS_B_EMIOS22_IN functionality */,
  {(uint16)490, (uint8)7, (uint16)146}
  /* Settings information for pad 491 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC8_IN functionality */,
  {(uint16)491, (uint8)6, (uint16)147}
  /* eMIOS_B_EMIOS23_IN functionality */,
  {(uint16)491, (uint8)7, (uint16)148}
[!ENDVAR!]


[!VAR "SIZE_OF_MUX_TABLE_1"!][!//
423[!//
[!ENDVAR!]


[!VAR "SIZE_OF_INMUX_TABLE_1"!][!//
149[!//
[!ENDVAR!]


[!VAR "SIZE_OF_INDEX_TABLE_1"!][!//
((uint16)(572))[!//
[!ENDVAR!]


[!VAR "INDEX_2"!]
  /* Settings information for pad 0 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 1 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 2 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 3 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 4 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 5 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 6 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 7 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 8 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 9 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 10 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 11 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 12 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 13 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 14 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 15 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 16 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 17 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 18 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 19 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 20 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 21 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 22 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 23 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 24 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 25 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 26 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 27 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 28 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 29 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 30 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 31 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 32 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 33 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 34 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 35 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 36 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 37 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 38 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 39 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 40 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 41 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 42 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 43 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 44 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 45 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 46 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 47 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 48 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 49 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 50 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 51 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 52 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 53 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 54 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 55 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 56 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 57 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 58 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 59 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 60 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 61 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 62 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 63 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 64 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 65 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 66 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 67 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 68 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 69 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 70 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 71 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 72 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 73 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 74 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 75 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 76 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 77 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 78 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 79 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 80 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 81 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 82 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 83 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_A_CNTXA functionality */
  {(uint16)83, (uint8)1, (uint16)0}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)83, (uint8)3, (uint16)1}
  /* eSCI_A_TXDA functionality */,
  {(uint16)83, (uint8)6, (uint16)0}
  /* Settings information for pad 84 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_A_CNRXA functionality */,
  {(uint16)84, (uint8)1, (uint16)2}
  /* eSCI_A_RXDA functionality */,
  {(uint16)84, (uint8)6, (uint16)1}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)84, (uint8)7, (uint16)2}
  /* Settings information for pad 85 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_B_CNTXB functionality */,
  {(uint16)85, (uint8)1, (uint16)3}
  /* DSPI_C_PCSC3 functionality */,
  {(uint16)85, (uint8)2, (uint16)4}
  /* Settings information for pad 86 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_B_CNRXB functionality */,
  {(uint16)86, (uint8)1, (uint16)5}
  /* DSPI_C_PCSC4 functionality */,
  {(uint16)86, (uint8)2, (uint16)6}
  /* Settings information for pad 87 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_C_CNTXC functionality */,
  {(uint16)87, (uint8)1, (uint16)7}
  /* DSPI_D_PCSD3 functionality */,
  {(uint16)87, (uint8)2, (uint16)8}
  /* Settings information for pad 88 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_C_CNRXC functionality */,
  {(uint16)88, (uint8)1, (uint16)9}
  /* DSPI_D_PCSD4 functionality */,
  {(uint16)88, (uint8)2, (uint16)10}
  /* eSCI_E_RXDE functionality */,
  {(uint16)88, (uint8)3, (uint16)11}
  /* Settings information for pad 89 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_A_TXDA functionality */,
  {(uint16)89, (uint8)5, (uint16)3}
  /* Settings information for pad 90 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_A_RXDA_IN functionality */,
  {(uint16)90, (uint8)5, (uint16)4}
  /* Settings information for pad 91 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_D_PCSD1 functionality */,
  {(uint16)91, (uint8)2, (uint16)12}
  /* eSCI_B_TXDB functionality */,
  {(uint16)91, (uint8)5, (uint16)5}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)91, (uint8)7, (uint16)6}
  /* Settings information for pad 92 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_D_PCSD5 functionality */,
  {(uint16)92, (uint8)2, (uint16)13}
  /* eSCI_B_RXDB functionality */,
  {(uint16)92, (uint8)5, (uint16)7}
  /* Settings information for pad 93 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_SCKA_INOUT functionality */,
  {(uint16)93, (uint8)1, (uint16)14}
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)93, (uint8)2, (uint16)15}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)93, (uint8)3, (uint16)16}
  /* SENT_B_SENT1_B_IN functionality */,
  {(uint16)93, (uint8)8, (uint16)8}
  /* Settings information for pad 94 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_SINA functionality */,
  {(uint16)94, (uint8)1, (uint16)17}
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)94, (uint8)2, (uint16)18}
  /* Settings information for pad 95 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_SOUTA functionality */,
  {(uint16)95, (uint8)1, (uint16)19}
  /* DSPI_C_PCSC5 functionality */,
  {(uint16)95, (uint8)2, (uint16)20}
  /* Settings information for pad 96 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA0_INOUT functionality */,
  {(uint16)96, (uint8)1, (uint16)21}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)96, (uint8)2, (uint16)22}
  /* Settings information for pad 97 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA1 functionality */,
  {(uint16)97, (uint8)1, (uint16)23}
  /* DSPI_E_PCSE0_INOUT functionality */,
  {(uint16)97, (uint8)2, (uint16)24}
  /* Settings information for pad 98 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA2 functionality */,
  {(uint16)98, (uint8)1, (uint16)25}
  /* DSPI_E_SOUTE functionality */,
  {(uint16)98, (uint8)2, (uint16)26}
  /* FEC_FEC_TXD2_OUT functionality */,
  {(uint16)98, (uint8)3, (uint16)27}
  /* FEC_FEC_RXER_IN functionality */,
  {(uint16)98, (uint8)4, (uint16)28}
  /* Settings information for pad 99 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA3 functionality */,
  {(uint16)99, (uint8)1, (uint16)29}
  /* DSPI_E_SINE functionality */,
  {(uint16)99, (uint8)2, (uint16)30}
  /* FEC_FEC_MDIO functionality */,
  {(uint16)99, (uint8)3, (uint16)31}
  /* eSCI_D_TXDD functionality */,
  {(uint16)99, (uint8)4, (uint16)32}
  /* Settings information for pad 100 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA4 functionality */,
  {(uint16)100, (uint8)1, (uint16)33}
  /* DSPI_E_SCKE_INOUT functionality */,
  {(uint16)100, (uint8)2, (uint16)34}
  /* FEC_FEC_RXCLK_IN functionality */,
  {(uint16)100, (uint8)4, (uint16)35}
  /* eSCI_E_TXDE functionality */,
  {(uint16)100, (uint8)7, (uint16)9}
  /* Settings information for pad 101 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_A_PCSA5 functionality */,
  {(uint16)101, (uint8)1, (uint16)36}
  /* eQADC_A_eQADC_B_ETRIG1 functionality */,
  {(uint16)101, (uint8)2, (uint16)37}
  /* eSCI_D_RXDD functionality */,
  {(uint16)101, (uint8)3, (uint16)38}
  /* FEC_FEC_TXD3_OUT functionality */,
  {(uint16)101, (uint8)4, (uint16)39}
  /* Settings information for pad 102 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_SCKB_IN functionality */,
  {(uint16)102, (uint8)1, (uint16)40}
  /* Settings information for pad 103 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_SINB functionality */,
  {(uint16)103, (uint8)1, (uint16)41}
  /* Settings information for pad 104 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_SOUTB functionality */,
  {(uint16)104, (uint8)1, (uint16)42}
  /* Settings information for pad 105 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB0_OUT functionality */,
  {(uint16)105, (uint8)1, (uint16)43}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)105, (uint8)2, (uint16)44}
  /* DSPI_B_PCSB0_IN functionality */,
  {(uint16)105, (uint8)5, (uint16)10}
  /* Settings information for pad 106 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB1 functionality */,
  {(uint16)106, (uint8)1, (uint16)45}
  /* DSPI_D_PCSD0_OUT functionality */,
  {(uint16)106, (uint8)2, (uint16)46}
  /* DSPI_D_PCSD0_IN functionality */,
  {(uint16)106, (uint8)6, (uint16)11}
  /* Settings information for pad 107 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB2 functionality */,
  {(uint16)107, (uint8)1, (uint16)47}
  /* DSPI_C_SOUTC functionality */,
  {(uint16)107, (uint8)2, (uint16)48}
  /* FEC_FEC_RXD3_IN functionality */,
  {(uint16)107, (uint8)4, (uint16)49}
  /* SENT_B_SENT2_B_IN functionality */,
  {(uint16)107, (uint8)7, (uint16)12}
  /* Settings information for pad 108 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB3 functionality */,
  {(uint16)108, (uint8)1, (uint16)50}
  /* DSPI_C_SINC functionality */,
  {(uint16)108, (uint8)6, (uint16)13}
  /* SENT_B_SENT3_B_IN functionality */,
  {(uint16)108, (uint8)7, (uint16)14}
  /* Settings information for pad 109 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB4 functionality */,
  {(uint16)109, (uint8)1, (uint16)51}
  /* DSPI_C_SCKC_OUT functionality */,
  {(uint16)109, (uint8)2, (uint16)52}
  /* FEC_FEC_MDC_OUT functionality */,
  {(uint16)109, (uint8)4, (uint16)53}
  /* DSPI_C_SCKC_IN functionality */,
  {(uint16)109, (uint8)6, (uint16)15}
  /* SENT_B_SENT4_B_IN functionality */,
  {(uint16)109, (uint8)7, (uint16)16}
  /* Settings information for pad 110 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_B_PCSB5 functionality */,
  {(uint16)110, (uint8)1, (uint16)54}
  /* DSPI_C_PCSC0_OUT functionality */,
  {(uint16)110, (uint8)2, (uint16)55}
  /* FEC_FEC_RXD2_IN functionality */,
  {(uint16)110, (uint8)4, (uint16)56}
  /* DSPI_C_PCSC0_IN functionality */,
  {(uint16)110, (uint8)6, (uint16)17}
  /* SENT_B_SENT5_B_IN functionality */,
  {(uint16)110, (uint8)7, (uint16)18}
  /* Settings information for pad 111 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 112 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 113 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_TCRCLKA functionality */,
  {(uint16)113, (uint8)1, (uint16)57}
  /* SIU_A_IRQ7 functionality */,
  {(uint16)113, (uint8)2, (uint16)58}
  /* Settings information for pad 114 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA0_IN functionality */,
  {(uint16)114, (uint8)1, (uint16)59}
  /* eTPU_A_ETPUA12 functionality */,
  {(uint16)114, (uint8)2, (uint16)60}
  /* Settings information for pad 115 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA1_IN functionality */,
  {(uint16)115, (uint8)1, (uint16)61}
  /* eTPU_A_ETPUA13 functionality */,
  {(uint16)115, (uint8)2, (uint16)62}
  /* Settings information for pad 116 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA2_IN functionality */,
  {(uint16)116, (uint8)1, (uint16)63}
  /* eTPU_A_ETPUA14 functionality */,
  {(uint16)116, (uint8)2, (uint16)64}
  /* REACM_RCH0_A_OUT functionality */,
  {(uint16)116, (uint8)3, (uint16)65}
  /* Settings information for pad 117 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA3_IN functionality */,
  {(uint16)117, (uint8)1, (uint16)66}
  /* eTPU_A_ETPUA15 functionality */,
  {(uint16)117, (uint8)2, (uint16)67}
  /* REACM_RCH1_A_OUT functionality */,
  {(uint16)117, (uint8)3, (uint16)68}
  /* FCCU_ERROR0 functionality */,
  {(uint16)117, (uint8)4, (uint16)69}
  /* Settings information for pad 118 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA4_IN functionality */,
  {(uint16)118, (uint8)1, (uint16)70}
  /* eTPU_A_ETPUA16 functionality */,
  {(uint16)118, (uint8)2, (uint16)71}
  /* REACM_RCH2_A_OUT functionality */,
  {(uint16)118, (uint8)3, (uint16)72}
  /* Settings information for pad 119 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA5_IN functionality */,
  {(uint16)119, (uint8)1, (uint16)73}
  /* eTPU_A_ETPUA17 functionality */,
  {(uint16)119, (uint8)2, (uint16)74}
  /* REACM_RCH3_A_OUT functionality */,
  {(uint16)119, (uint8)3, (uint16)75}
  /* Settings information for pad 120 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA6_IN functionality */,
  {(uint16)120, (uint8)1, (uint16)76}
  /* eTPU_A_ETPUA18 functionality */,
  {(uint16)120, (uint8)2, (uint16)77}
  /* REACM_RCH4_A_OUT functionality */,
  {(uint16)120, (uint8)3, (uint16)78}
  /* Settings information for pad 121 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA7_IN functionality */,
  {(uint16)121, (uint8)1, (uint16)79}
  /* eTPU_A_ETPUA19 functionality */,
  {(uint16)121, (uint8)2, (uint16)80}
  /* REACM_RCH5_A_OUT functionality */,
  {(uint16)121, (uint8)3, (uint16)81}
  /* Settings information for pad 122 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA8_IN functionality */,
  {(uint16)122, (uint8)1, (uint16)82}
  /* eTPU_A_ETPUA20 functionality */,
  {(uint16)122, (uint8)2, (uint16)83}
  /* REACM_RCH6_A_OUT functionality */,
  {(uint16)122, (uint8)3, (uint16)84}
  /* Settings information for pad 123 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA9_IN functionality */,
  {(uint16)123, (uint8)1, (uint16)85}
  /* eTPU_A_ETPUA21 functionality */,
  {(uint16)123, (uint8)2, (uint16)86}
  /* REACM_RCH7_A_OUT functionality */,
  {(uint16)123, (uint8)3, (uint16)87}
  /* Settings information for pad 124 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA10_IN functionality */,
  {(uint16)124, (uint8)1, (uint16)88}
  /* eTPU_A_ETPUA22 functionality */,
  {(uint16)124, (uint8)2, (uint16)89}
  /* REACM_RCH8_A_OUT functionality */,
  {(uint16)124, (uint8)3, (uint16)90}
  /* FCCU_ERRORIN functionality */,
  {(uint16)124, (uint8)4, (uint16)91}
  /* Settings information for pad 125 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA11_IN functionality */,
  {(uint16)125, (uint8)1, (uint16)92}
  /* eTPU_A_ETPUA23 functionality */,
  {(uint16)125, (uint8)2, (uint16)93}
  /* REACM_RCH9_A_OUT functionality */,
  {(uint16)125, (uint8)3, (uint16)94}
  /* FCCU_ERROR1 functionality */,
  {(uint16)125, (uint8)4, (uint16)95}
  /* Settings information for pad 126 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA12_IN functionality */,
  {(uint16)126, (uint8)1, (uint16)96}
  /* DSPI_B_PCSB1 functionality */,
  {(uint16)126, (uint8)2, (uint16)97}
  /* Settings information for pad 127 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA13_IN functionality */,
  {(uint16)127, (uint8)1, (uint16)98}
  /* DSPI_B_PCSB3 functionality */,
  {(uint16)127, (uint8)2, (uint16)99}
  /* Settings information for pad 128 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA14_IN functionality */,
  {(uint16)128, (uint8)1, (uint16)100}
  /* DSPI_B_PCSB4 functionality */,
  {(uint16)128, (uint8)2, (uint16)101}
  /* Settings information for pad 129 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA15_IN functionality */,
  {(uint16)129, (uint8)1, (uint16)102}
  /* DSPI_B_PCSB5 functionality */,
  {(uint16)129, (uint8)2, (uint16)103}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)129, (uint8)3, (uint16)104}
  /* Settings information for pad 130 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA16_IN functionality */,
  {(uint16)130, (uint8)1, (uint16)105}
  /* DSPI_D_PCSD1 functionality */,
  {(uint16)130, (uint8)2, (uint16)106}
  /* Settings information for pad 131 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA17_IN functionality */,
  {(uint16)131, (uint8)1, (uint16)107}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)131, (uint8)2, (uint16)108}
  /* Settings information for pad 132 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA18_IN functionality */,
  {(uint16)132, (uint8)1, (uint16)109}
  /* DSPI_D_PCSD3 functionality */,
  {(uint16)132, (uint8)2, (uint16)110}
  /* Settings information for pad 133 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA19_IN functionality */,
  {(uint16)133, (uint8)1, (uint16)111}
  /* DSPI_D_PCSD4 functionality */,
  {(uint16)133, (uint8)2, (uint16)112}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)133, (uint8)7, (uint16)19}
  /* Settings information for pad 134 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA20_IN functionality */,
  {(uint16)134, (uint8)1, (uint16)113}
  /* SIU_A_IRQ8 functionality */,
  {(uint16)134, (uint8)2, (uint16)114}
  /* Settings information for pad 135 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA21_IN functionality */,
  {(uint16)135, (uint8)1, (uint16)115}
  /* SIU_A_IRQ9 functionality */,
  {(uint16)135, (uint8)2, (uint16)116}
  /* Settings information for pad 136 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA22_IN functionality */,
  {(uint16)136, (uint8)1, (uint16)117}
  /* SIU_A_IRQ10 functionality */,
  {(uint16)136, (uint8)2, (uint16)118}
  /* REACM_RCH0_A_OUT functionality */,
  {(uint16)136, (uint8)3, (uint16)119}
  /* Settings information for pad 137 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA23_IN functionality */,
  {(uint16)137, (uint8)1, (uint16)120}
  /* SIU_A_IRQ11 functionality */,
  {(uint16)137, (uint8)2, (uint16)121}
  /* REACM_RCH1_A_OUT functionality */,
  {(uint16)137, (uint8)3, (uint16)122}
  /* Settings information for pad 138 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA24_OUT functionality */,
  {(uint16)138, (uint8)1, (uint16)123}
  /* SIU_A_IRQ12 functionality */,
  {(uint16)138, (uint8)2, (uint16)124}
  /* REACM_RCH2_A_OUT functionality */,
  {(uint16)138, (uint8)3, (uint16)125}
  /* eTPU_A_ETPUA24_IN functionality */,
  {(uint16)138, (uint8)5, (uint16)20}
  /* Settings information for pad 139 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA25_OUT functionality */,
  {(uint16)139, (uint8)1, (uint16)126}
  /* SIU_A_IRQ13 functionality */,
  {(uint16)139, (uint8)2, (uint16)127}
  /* REACM_RCH3_A_OUT functionality */,
  {(uint16)139, (uint8)3, (uint16)128}
  /* eTPU_A_ETPUA25_IN functionality */,
  {(uint16)139, (uint8)5, (uint16)21}
  /* Settings information for pad 140 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA26_OUT functionality */,
  {(uint16)140, (uint8)1, (uint16)129}
  /* SIU_A_IRQ14 functionality */,
  {(uint16)140, (uint8)2, (uint16)130}
  /* REACM_RCH4_A_OUT functionality */,
  {(uint16)140, (uint8)3, (uint16)131}
  /* eTPU_A_ETPUA26_IN functionality */,
  {(uint16)140, (uint8)5, (uint16)22}
  /* Settings information for pad 141 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA27_OUT functionality */,
  {(uint16)141, (uint8)1, (uint16)132}
  /* SIU_A_IRQ15 functionality */,
  {(uint16)141, (uint8)2, (uint16)133}
  /* REACM_RCH5_A_OUT functionality */,
  {(uint16)141, (uint8)3, (uint16)134}
  /* eTPU_A_ETPUA27_IN functionality */,
  {(uint16)141, (uint8)5, (uint16)23}
  /* Settings information for pad 142 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA28_OUT functionality */,
  {(uint16)142, (uint8)1, (uint16)135}
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)142, (uint8)2, (uint16)136}
  /* REACM_RCH6_A_OUT functionality */,
  {(uint16)142, (uint8)3, (uint16)137}
  /* eTPU_A_ETPUA28_IN functionality */,
  {(uint16)142, (uint8)5, (uint16)24}
  /* Settings information for pad 143 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA29_OUT functionality */,
  {(uint16)143, (uint8)1, (uint16)138}
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)143, (uint8)2, (uint16)139}
  /* REACM_RCH7_A_OUT functionality */,
  {(uint16)143, (uint8)3, (uint16)140}
  /* eTPU_A_ETPUA29_IN functionality */,
  {(uint16)143, (uint8)5, (uint16)25}
  /* Settings information for pad 144 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA30_OUT functionality */,
  {(uint16)144, (uint8)1, (uint16)141}
  /* DSPI_C_PCSC3 functionality */,
  {(uint16)144, (uint8)2, (uint16)142}
  /* REACM_RCH8_A_OUT functionality */,
  {(uint16)144, (uint8)3, (uint16)143}
  /* eTPU_A_ETPUA30_IN functionality */,
  {(uint16)144, (uint8)5, (uint16)26}
  /* Settings information for pad 145 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA31_OUT functionality */,
  {(uint16)145, (uint8)1, (uint16)144}
  /* DSPI_C_PCSC4 functionality */,
  {(uint16)145, (uint8)2, (uint16)145}
  /* REACM_RCH9_A_OUT functionality */,
  {(uint16)145, (uint8)3, (uint16)146}
  /* eTPU_A_ETPUA31_IN functionality */,
  {(uint16)145, (uint8)5, (uint16)27}
  /* Settings information for pad 146 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_TCRCLKB functionality */,
  {(uint16)146, (uint8)1, (uint16)147}
  /* SIU_A_IRQ6 functionality */,
  {(uint16)146, (uint8)6, (uint16)28}
  /* Settings information for pad 147 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB0_IN functionality */,
  {(uint16)147, (uint8)1, (uint16)148}
  /* eTPU_B_ETPUB16 functionality */,
  {(uint16)147, (uint8)2, (uint16)149}
  /* Settings information for pad 148 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB1_IN functionality */,
  {(uint16)148, (uint8)1, (uint16)150}
  /* eTPU_B_ETPUB17 functionality */,
  {(uint16)148, (uint8)2, (uint16)151}
  /* Settings information for pad 149 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB2_IN functionality */,
  {(uint16)149, (uint8)1, (uint16)152}
  /* eTPU_B_ETPUB18 functionality */,
  {(uint16)149, (uint8)2, (uint16)153}
  /* Settings information for pad 150 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB3_IN functionality */,
  {(uint16)150, (uint8)1, (uint16)154}
  /* eTPU_B_ETPUB19 functionality */,
  {(uint16)150, (uint8)2, (uint16)155}
  /* Settings information for pad 151 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB4_IN functionality */,
  {(uint16)151, (uint8)1, (uint16)156}
  /* eTPU_B_ETPUB20 functionality */,
  {(uint16)151, (uint8)2, (uint16)157}
  /* Settings information for pad 152 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB5_IN functionality */,
  {(uint16)152, (uint8)1, (uint16)158}
  /* eTPU_B_ETPUB21 functionality */,
  {(uint16)152, (uint8)2, (uint16)159}
  /* Settings information for pad 153 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB6_IN functionality */,
  {(uint16)153, (uint8)1, (uint16)160}
  /* eTPU_B_ETPUB22 functionality */,
  {(uint16)153, (uint8)2, (uint16)161}
  /* Settings information for pad 154 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB7_IN functionality */,
  {(uint16)154, (uint8)1, (uint16)162}
  /* eTPU_B_ETPUB23 functionality */,
  {(uint16)154, (uint8)2, (uint16)163}
  /* Settings information for pad 155 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB8_IN functionality */,
  {(uint16)155, (uint8)1, (uint16)164}
  /* eTPU_B_ETPUB24 functionality */,
  {(uint16)155, (uint8)2, (uint16)165}
  /* Settings information for pad 156 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB9_IN functionality */,
  {(uint16)156, (uint8)1, (uint16)166}
  /* eTPU_B_ETPUB25 functionality */,
  {(uint16)156, (uint8)2, (uint16)167}
  /* Settings information for pad 157 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB10_IN functionality */,
  {(uint16)157, (uint8)1, (uint16)168}
  /* eTPU_B_ETPUB26 functionality */,
  {(uint16)157, (uint8)2, (uint16)169}
  /* Settings information for pad 158 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB11_IN functionality */,
  {(uint16)158, (uint8)1, (uint16)170}
  /* eTPU_B_ETPUB27 functionality */,
  {(uint16)158, (uint8)2, (uint16)171}
  /* Settings information for pad 159 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB12_IN functionality */,
  {(uint16)159, (uint8)1, (uint16)172}
  /* eTPU_B_ETPUB28 functionality */,
  {(uint16)159, (uint8)2, (uint16)173}
  /* Settings information for pad 160 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB13_IN functionality */,
  {(uint16)160, (uint8)1, (uint16)174}
  /* eTPU_B_ETPUB29 functionality */,
  {(uint16)160, (uint8)2, (uint16)175}
  /* Settings information for pad 161 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB14_IN functionality */,
  {(uint16)161, (uint8)1, (uint16)176}
  /* eTPU_B_ETPUB30 functionality */,
  {(uint16)161, (uint8)2, (uint16)177}
  /* Settings information for pad 162 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB15_IN functionality */,
  {(uint16)162, (uint8)1, (uint16)178}
  /* eTPU_B_ETPUB31 functionality */,
  {(uint16)162, (uint8)2, (uint16)179}
  /* Settings information for pad 163 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB16_IN functionality */,
  {(uint16)163, (uint8)1, (uint16)180}
  /* DSPI_A_PCSA1 functionality */,
  {(uint16)163, (uint8)2, (uint16)181}
  /* Settings information for pad 164 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB17_IN functionality */,
  {(uint16)164, (uint8)1, (uint16)182}
  /* DSPI_A_PCSA2 functionality */,
  {(uint16)164, (uint8)2, (uint16)183}
  /* Settings information for pad 165 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB18_IN functionality */,
  {(uint16)165, (uint8)1, (uint16)184}
  /* DSPI_A_PCSA3 functionality */,
  {(uint16)165, (uint8)2, (uint16)185}
  /* Settings information for pad 166 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB19_IN functionality */,
  {(uint16)166, (uint8)1, (uint16)186}
  /* DSPI_A_PCSA4 functionality */,
  {(uint16)166, (uint8)2, (uint16)187}
  /* Settings information for pad 167 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB20_IN functionality */,
  {(uint16)167, (uint8)1, (uint16)188}
  /* Settings information for pad 168 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB21_IN functionality */,
  {(uint16)168, (uint8)1, (uint16)189}
  /* Settings information for pad 169 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB22_IN functionality */,
  {(uint16)169, (uint8)1, (uint16)190}
  /* REACM_RCH0_B_OUT functionality */,
  {(uint16)169, (uint8)2, (uint16)191}
  /* Settings information for pad 170 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB23_IN functionality */,
  {(uint16)170, (uint8)1, (uint16)192}
  /* REACM_RCH1_B_OUT functionality */,
  {(uint16)170, (uint8)2, (uint16)193}
  /* Settings information for pad 171 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB24_IN functionality */,
  {(uint16)171, (uint8)1, (uint16)194}
  /* REACM_RCH2_B_OUT functionality */,
  {(uint16)171, (uint8)2, (uint16)195}
  /* Settings information for pad 172 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB25_IN functionality */,
  {(uint16)172, (uint8)1, (uint16)196}
  /* REACM_RCH3_B_OUT functionality */,
  {(uint16)172, (uint8)2, (uint16)197}
  /* Settings information for pad 173 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB26_IN functionality */,
  {(uint16)173, (uint8)1, (uint16)198}
  /* REACM_RCH4_B_OUT functionality */,
  {(uint16)173, (uint8)2, (uint16)199}
  /* Settings information for pad 174 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB27_IN functionality */,
  {(uint16)174, (uint8)1, (uint16)200}
  /* REACM_RCH5_B_OUT functionality */,
  {(uint16)174, (uint8)2, (uint16)201}
  /* Settings information for pad 175 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB28_IN functionality */,
  {(uint16)175, (uint8)1, (uint16)202}
  /* REACM_RCH6_B_OUT functionality */,
  {(uint16)175, (uint8)2, (uint16)203}
  /* Settings information for pad 176 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB29_IN functionality */,
  {(uint16)176, (uint8)1, (uint16)204}
  /* REACM_RCH7_B_OUT functionality */,
  {(uint16)176, (uint8)2, (uint16)205}
  /* Settings information for pad 177 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB30_IN functionality */,
  {(uint16)177, (uint8)1, (uint16)206}
  /* REACM_RCH8_B_OUT functionality */,
  {(uint16)177, (uint8)2, (uint16)207}
  /* Settings information for pad 178 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_B_ETPUB31_IN functionality */,
  {(uint16)178, (uint8)1, (uint16)208}
  /* REACM_RCH9_B_OUT functionality */,
  {(uint16)178, (uint8)2, (uint16)209}
  /* Settings information for pad 179 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS0_IN functionality */,
  {(uint16)179, (uint8)1, (uint16)210}
  /* eTPU_A_ETPUA0 functionality */,
  {(uint16)179, (uint8)2, (uint16)211}
  /* REACM_RCH0_C_OUT functionality */,
  {(uint16)179, (uint8)3, (uint16)212}
  /* Settings information for pad 180 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS1_IN functionality */,
  {(uint16)180, (uint8)1, (uint16)213}
  /* eTPU_A_ETPUA1 functionality */,
  {(uint16)180, (uint8)2, (uint16)214}
  /* REACM_RCH1_C_OUT functionality */,
  {(uint16)180, (uint8)3, (uint16)215}
  /* DSPI_E_PCSE2 functionality */,
  {(uint16)180, (uint8)4, (uint16)216}
  /* Settings information for pad 181 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS2_IN functionality */,
  {(uint16)181, (uint8)1, (uint16)217}
  /* eTPU_A_ETPUA2 functionality */,
  {(uint16)181, (uint8)2, (uint16)218}
  /* REACM_RCH2_C_OUT functionality */,
  {(uint16)181, (uint8)3, (uint16)219}
  /* DSPI_E_PCSE3 functionality */,
  {(uint16)181, (uint8)4, (uint16)220}
  /* Settings information for pad 182 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS3_IN functionality */,
  {(uint16)182, (uint8)1, (uint16)221}
  /* eTPU_A_ETPUA3 functionality */,
  {(uint16)182, (uint8)2, (uint16)222}
  /* REACM_RCH3_C_OUT functionality */,
  {(uint16)182, (uint8)3, (uint16)223}
  /* DSPI_E_PCSE4 functionality */,
  {(uint16)182, (uint8)4, (uint16)224}
  /* Settings information for pad 183 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS4 functionality */,
  {(uint16)183, (uint8)1, (uint16)225}
  /* eTPU_A_ETPUA4 functionality */,
  {(uint16)183, (uint8)2, (uint16)226}
  /* REACM_RCH4_C_OUT functionality */,
  {(uint16)183, (uint8)3, (uint16)227}
  /* DSPI_E_PCSE5 functionality */,
  {(uint16)183, (uint8)4, (uint16)228}
  /* Settings information for pad 184 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS5 functionality */,
  {(uint16)184, (uint8)1, (uint16)229}
  /* eTPU_A_ETPUA5 functionality */,
  {(uint16)184, (uint8)2, (uint16)230}
  /* REACM_RCH5_C_OUT functionality */,
  {(uint16)184, (uint8)3, (uint16)231}
  /* Settings information for pad 185 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS6_IN functionality */,
  {(uint16)185, (uint8)1, (uint16)232}
  /* eTPU_A_ETPUA6 functionality */,
  {(uint16)185, (uint8)2, (uint16)233}
  /* REACM_RCH6_C_OUT functionality */,
  {(uint16)185, (uint8)3, (uint16)234}
  /* Settings information for pad 186 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS7_IN functionality */,
  {(uint16)186, (uint8)1, (uint16)235}
  /* eTPU_A_ETPUA7 functionality */,
  {(uint16)186, (uint8)2, (uint16)236}
  /* REACM_RCH7_C_OUT functionality */,
  {(uint16)186, (uint8)3, (uint16)237}
  /* Settings information for pad 187 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS0_IN functionality */,
  {(uint16)187, (uint8)1, (uint16)238}
  /* eTPU_A_ETPUA8 functionality */,
  {(uint16)187, (uint8)2, (uint16)239}
  /* REACM_RCH8_C_OUT functionality */,
  {(uint16)187, (uint8)3, (uint16)240}
  /* Settings information for pad 188 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS1_IN functionality */,
  {(uint16)188, (uint8)1, (uint16)241}
  /* eTPU_A_ETPUA9 functionality */,
  {(uint16)188, (uint8)2, (uint16)242}
  /* REACM_RCH9_C_OUT functionality */,
  {(uint16)188, (uint8)3, (uint16)243}
  /* Settings information for pad 189 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS2_IN functionality */,
  {(uint16)189, (uint8)1, (uint16)244}
  /* DSPI_D_SCKD_OUT functionality */,
  {(uint16)189, (uint8)2, (uint16)245}
  /* DSPI_D_SCKD_IN functionality */,
  {(uint16)189, (uint8)6, (uint16)29}
  /* Settings information for pad 190 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS3_IN functionality */,
  {(uint16)190, (uint8)1, (uint16)246}
  /* DSPI_D_SIND functionality */,
  {(uint16)190, (uint8)6, (uint16)30}
  /* Settings information for pad 191 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS4_IN functionality */,
  {(uint16)191, (uint8)1, (uint16)247}
  /* DSPI_C_SOUTC functionality */,
  {(uint16)191, (uint8)2, (uint16)248}
  /* Settings information for pad 192 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS5_IN functionality */,
  {(uint16)192, (uint8)1, (uint16)249}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)192, (uint8)2, (uint16)250}
  /* Settings information for pad 193 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS6 functionality */,
  {(uint16)193, (uint8)1, (uint16)251}
  /* FlexCAN_D_CNTXD functionality */,
  {(uint16)193, (uint8)3, (uint16)252}
  /* REACM_RCH0_C_OUT functionality */,
  {(uint16)193, (uint8)4, (uint16)253}
  /* SIU_A_IRQ0 functionality */,
  {(uint16)193, (uint8)6, (uint16)31}
  /* Settings information for pad 194 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS7 functionality */,
  {(uint16)194, (uint8)1, (uint16)254}
  /* REACM_RCH1_C_OUT functionality */,
  {(uint16)194, (uint8)4, (uint16)255}
  /* SIU_A_IRQ1_IN functionality */,
  {(uint16)194, (uint8)6, (uint16)32}
  /* FlexCAN_D_CNRXD_IN functionality */,
  {(uint16)194, (uint8)7, (uint16)33}
  /* Settings information for pad 195 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS16_OUT functionality */,
  {(uint16)195, (uint8)1, (uint16)256}
  /* eTPU_B_ETPUB0 functionality */,
  {(uint16)195, (uint8)2, (uint16)257}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)195, (uint8)3, (uint16)258}
  /* REACM_RCH2_C_OUT functionality */,
  {(uint16)195, (uint8)4, (uint16)259}
  /* eMIOS_A_EMIOS16_IN functionality */,
  {(uint16)195, (uint8)5, (uint16)34}
  /* Settings information for pad 196 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS17_OUT functionality */,
  {(uint16)196, (uint8)1, (uint16)260}
  /* eTPU_B_ETPUB1 functionality */,
  {(uint16)196, (uint8)2, (uint16)261}
  /* REACM_RCH3_C_OUT functionality */,
  {(uint16)196, (uint8)4, (uint16)262}
  /* eMIOS_A_EMIOS17_IN functionality */,
  {(uint16)196, (uint8)5, (uint16)35}
  /* MCAN_1_RX_IN functionality */,
  {(uint16)196, (uint8)7, (uint16)36}
  /* Settings information for pad 197 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS18_OUT functionality */,
  {(uint16)197, (uint8)1, (uint16)263}
  /* eTPU_B_ETPUB2 functionality */,
  {(uint16)197, (uint8)2, (uint16)264}
  /* REACM_RCH4_C_OUT functionality */,
  {(uint16)197, (uint8)3, (uint16)265}
  /* eMIOS_A_EMIOS18_IN functionality */,
  {(uint16)197, (uint8)5, (uint16)37}
  /* Settings information for pad 198 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS19_OUT functionality */,
  {(uint16)198, (uint8)1, (uint16)266}
  /* eTPU_B_ETPUB3 functionality */,
  {(uint16)198, (uint8)2, (uint16)267}
  /* REACM_RCH5_C_OUT functionality */,
  {(uint16)198, (uint8)3, (uint16)268}
  /* eMIOS_A_EMIOS19_IN functionality */,
  {(uint16)198, (uint8)5, (uint16)38}
  /* Settings information for pad 199 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS20_OUT functionality */,
  {(uint16)199, (uint8)1, (uint16)269}
  /* eTPU_B_ETPUB4 functionality */,
  {(uint16)199, (uint8)2, (uint16)270}
  /* REACM_RCH6_C_OUT functionality */,
  {(uint16)199, (uint8)3, (uint16)271}
  /* eMIOS_A_EMIOS20_IN functionality */,
  {(uint16)199, (uint8)5, (uint16)39}
  /* Settings information for pad 200 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS21_OUT functionality */,
  {(uint16)200, (uint8)1, (uint16)272}
  /* eTPU_B_ETPUB5 functionality */,
  {(uint16)200, (uint8)2, (uint16)273}
  /* REACM_RCH7_C_OUT functionality */,
  {(uint16)200, (uint8)3, (uint16)274}
  /* eMIOS_A_EMIOS21_IN functionality */,
  {(uint16)200, (uint8)5, (uint16)40}
  /* Settings information for pad 201 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS22_OUT functionality */,
  {(uint16)201, (uint8)1, (uint16)275}
  /* eTPU_B_ETPUB6 functionality */,
  {(uint16)201, (uint8)2, (uint16)276}
  /* REACM_RCH8_C_OUT functionality */,
  {(uint16)201, (uint8)3, (uint16)277}
  /* eMIOS_A_EMIOS22_IN functionality */,
  {(uint16)201, (uint8)5, (uint16)41}
  /* Settings information for pad 202 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_A_EMIOS23_OUT functionality */,
  {(uint16)202, (uint8)1, (uint16)278}
  /* eTPU_B_ETPUB7 functionality */,
  {(uint16)202, (uint8)2, (uint16)279}
  /* REACM_RCH9_C_OUT functionality */,
  {(uint16)202, (uint8)3, (uint16)280}
  /* eMIOS_A_EMIOS23_IN functionality */,
  {(uint16)202, (uint8)5, (uint16)42}
  /* Settings information for pad 203 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS16_OUT functionality */,
  {(uint16)203, (uint8)1, (uint16)281}
  /* DSPI_B_PCSB0_OUT functionality */,
  {(uint16)203, (uint8)2, (uint16)282}
  /* eMIOS_B_EMIOS16_IN functionality */,
  {(uint16)203, (uint8)5, (uint16)43}
  /* DSPI_B_PCSB0_IN functionality */,
  {(uint16)203, (uint8)6, (uint16)44}
  /* Settings information for pad 204 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS17_OUT functionality */,
  {(uint16)204, (uint8)1, (uint16)283}
  /* DSPI_B_PCSB1 functionality */,
  {(uint16)204, (uint8)2, (uint16)284}
  /* eMIOS_B_EMIOS17_IN functionality */,
  {(uint16)204, (uint8)5, (uint16)45}
  /* Settings information for pad 205 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 206 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 207 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 208 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_PLLCFG0_IN functionality */,
  {(uint16)208, (uint8)1, (uint16)285}
  /* eTPU_C_ETPUC9_OUT functionality */,
  {(uint16)208, (uint8)3, (uint16)286}
  /* SIPI_TXN functionality */,
  {(uint16)208, (uint8)4, (uint16)287}
  /* SIU_A_IRQ4_IN functionality */,
  {(uint16)208, (uint8)6, (uint16)46}
  /* eTPU_C_ETPUC9_IN functionality */,
  {(uint16)208, (uint8)7, (uint16)47}
  /* Settings information for pad 209 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_PLLCFG1_IN functionality */,
  {(uint16)209, (uint8)1, (uint16)288}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)209, (uint8)3, (uint16)289}
  /* SIPI_TXP functionality */,
  {(uint16)209, (uint8)4, (uint16)290}
  /* SIU_A_IRQ5_IN functionality */,
  {(uint16)209, (uint8)6, (uint16)48}
  /* Settings information for pad 210 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_PLLCFG2_IN functionality */,
  {(uint16)210, (uint8)1, (uint16)291}
  /* eTPU_C_ETPUC3_OUT functionality */,
  {(uint16)210, (uint8)2, (uint16)292}
  /* DSPI_E_PCSE1 functionality */,
  {(uint16)210, (uint8)3, (uint16)293}
  /* SIPI_REFCLK_IN functionality */,
  {(uint16)210, (uint8)4, (uint16)294}
  /* eTPU_C_ETPUC3_IN functionality */,
  {(uint16)210, (uint8)6, (uint16)49}
  /* Settings information for pad 211 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_BOOTCFG0_IN functionality */,
  {(uint16)211, (uint8)1, (uint16)295}
  /* SIU_A_IRQ2_IN functionality */,
  {(uint16)211, (uint8)6, (uint16)50}
  /* Settings information for pad 212 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_BOOTCFG1_IN functionality */,
  {(uint16)212, (uint8)1, (uint16)296}
  /* eTPU_C_ETPUC0_OUT functionality */,
  {(uint16)212, (uint8)3, (uint16)297}
  /* SIPI_RXP functionality */,
  {(uint16)212, (uint8)4, (uint16)298}
  /* SIU_A_IRQ3_IN functionality */,
  {(uint16)212, (uint8)6, (uint16)51}
  /* eTPU_C_ETPUC0_IN functionality */,
  {(uint16)212, (uint8)7, (uint16)52}
  /* Settings information for pad 213 {PCR, Mode, Index to Mux or Inmux table} */
  /* SoC_WKPCFG_IN functionality */,
  {(uint16)213, (uint8)1, (uint16)299}
  /* SIU_A_NMI_IN functionality */,
  {(uint16)213, (uint8)2, (uint16)300}
  /* eTPU_C_ETPUC1_OUT functionality */,
  {(uint16)213, (uint8)3, (uint16)301}
  /* SIPI_RXN functionality */,
  {(uint16)213, (uint8)4, (uint16)302}
  /* eTPU_C_ETPUC1_IN functionality */,
  {(uint16)213, (uint8)7, (uint16)53}
  /* Settings information for pad 214 {PCR, Mode, Index to Mux or Inmux table} */
  /* ENGCLK functionality */,
  {(uint16)214, (uint8)1, (uint16)303}
  /* Settings information for pad 215 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 216 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 217 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 218 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 219 {PCR, Mode, Index to Mux or Inmux table} */
  /* MCKO functionality */,
  {(uint16)219, (uint8)1, (uint16)304}
  /* Settings information for pad 220 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 221 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 222 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 223 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_E_TXDE functionality */,
  {(uint16)223, (uint8)6, (uint16)54}
  /* Settings information for pad 224 {PCR, Mode, Index to Mux or Inmux table} */
  /* MSEO0 functionality */,
  {(uint16)224, (uint8)1, (uint16)305}
  /* Settings information for pad 225 {PCR, Mode, Index to Mux or Inmux table} */
  /* MSEO1 functionality */,
  {(uint16)225, (uint8)1, (uint16)306}
  /* Settings information for pad 226 {PCR, Mode, Index to Mux or Inmux table} */
  /* RDY functionality */,
  {(uint16)226, (uint8)1, (uint16)307}
  /* Settings information for pad 227 {PCR, Mode, Index to Mux or Inmux table} */
  /* EVTO functionality */,
  {(uint16)227, (uint8)1, (uint16)308}
  /* Settings information for pad 228 {PCR, Mode, Index to Mux or Inmux table} */
  /* TDO functionality */,
  {(uint16)228, (uint8)1, (uint16)309}
  /* Settings information for pad 229 {PCR, Mode, Index to Mux or Inmux table} */
  /* D_CLKOUT functionality */,
  {(uint16)229, (uint8)1, (uint16)310}
  /* Settings information for pad 230 {PCR, Mode, Index to Mux or Inmux table} */
  /* RSTOUT functionality */,
  {(uint16)230, (uint8)1, (uint16)311}
  /* Settings information for pad 231 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 232 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 233 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 234 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 235 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_SCKC_OUT functionality */,
  {(uint16)235, (uint8)1, (uint16)312}
  /* DSPI_C_SCK_C_LVDS_P functionality */,
  {(uint16)235, (uint8)2, (uint16)313}
  /* DSPI_C_SCKC_IN functionality */,
  {(uint16)235, (uint8)5, (uint16)55}
  /* Settings information for pad 236 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_SCK_C_LVDS_N_OUT functionality */,
  {(uint16)236, (uint8)2, (uint16)314}
  /* DSPI_C_SINC_IN functionality */,
  {(uint16)236, (uint8)5, (uint16)56}
  /* Settings information for pad 237 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_SOUTC functionality */,
  {(uint16)237, (uint8)1, (uint16)315}
  /* DSPI_C_SOUT_C_LVDS_P functionality */,
  {(uint16)237, (uint8)2, (uint16)316}
  /* Settings information for pad 238 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC0_OUT functionality */,
  {(uint16)238, (uint8)1, (uint16)317}
  /* DSPI_C_SOUT_C_LVDS_N_OUT functionality */,
  {(uint16)238, (uint8)2, (uint16)318}
  /* DSPI_C_PCSC0_IN functionality */,
  {(uint16)238, (uint8)5, (uint16)57}
  /* Settings information for pad 239 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)239, (uint8)1, (uint16)319}
  /* eSCI_D_TXDD functionality */,
  {(uint16)239, (uint8)2, (uint16)320}
  /* Settings information for pad 240 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)240, (uint8)1, (uint16)321}
  /* DSPI_D_SCK_D_LVDS_P functionality */,
  {(uint16)240, (uint8)2, (uint16)322}
  /* DSPI_D_SCKD_OUT functionality */,
  {(uint16)240, (uint8)3, (uint16)323}
  /* DSPI_D_SCKD_IN functionality */,
  {(uint16)240, (uint8)7, (uint16)58}
  /* Settings information for pad 241 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC3 functionality */,
  {(uint16)241, (uint8)1, (uint16)324}
  /* DSPI_D_SCK_D_LVDS_N_OUT functionality */,
  {(uint16)241, (uint8)2, (uint16)325}
  /* DSPI_D_SIND_IN functionality */,
  {(uint16)241, (uint8)7, (uint16)59}
  /* Settings information for pad 242 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC4 functionality */,
  {(uint16)242, (uint8)1, (uint16)326}
  /* MCAN_0_TX_OUT functionality */,
  {(uint16)242, (uint8)2, (uint16)327}
  /* DSPI_D_SOUT_D_LVDS_P functionality */,
  {(uint16)242, (uint8)3, (uint16)328}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)242, (uint8)4, (uint16)329}
  /* Settings information for pad 243 {PCR, Mode, Index to Mux or Inmux table} */
  /* DSPI_C_PCSC5 functionality */,
  {(uint16)243, (uint8)1, (uint16)330}
  /* DSPI_D_SOUT_D_LVDS_N_OUT functionality */,
  {(uint16)243, (uint8)3, (uint16)331}
  /* DSPI_D_PCSD0_OUT functionality */,
  {(uint16)243, (uint8)4, (uint16)332}
  /* MCAN_0_RX_IN functionality */,
  {(uint16)243, (uint8)6, (uint16)60}
  /* DSPI_D_PCSD0_IN functionality */,
  {(uint16)243, (uint8)8, (uint16)61}
  /* Settings information for pad 244 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_C_TXDC functionality */,
  {(uint16)244, (uint8)1, (uint16)333}
  /* eQADC_A_eQADC_B_ETRIG0_IN functionality */,
  {(uint16)244, (uint8)2, (uint16)334}
  /* Settings information for pad 245 {PCR, Mode, Index to Mux or Inmux table} */
  /* eSCI_C_RXDC_IN functionality */,
  {(uint16)245, (uint8)1, (uint16)335}
  /* Settings information for pad 246 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_D_CNTXD functionality */,
  {(uint16)246, (uint8)1, (uint16)336}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)246, (uint8)3, (uint16)337}
  /* Settings information for pad 247 {PCR, Mode, Index to Mux or Inmux table} */
  /* FlexCAN_D_CNRXD_IN functionality */,
  {(uint16)247, (uint8)5, (uint16)62}
  /* MCAN_1_RX_IN functionality */,
  {(uint16)247, (uint8)7, (uint16)63}
  /* Settings information for pad 248 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXD0_OUT functionality */,
  {(uint16)248, (uint8)1, (uint16)338}
  /* SENT_A_SENT0_A_IN functionality */,
  {(uint16)248, (uint8)6, (uint16)64}
  /* Settings information for pad 249 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_RX_DV_IN functionality */,
  {(uint16)249, (uint8)1, (uint16)339}
  /* SENT_A_SENT1_A_IN functionality */,
  {(uint16)249, (uint8)6, (uint16)65}
  /* Settings information for pad 250 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_RXD0_IN functionality */,
  {(uint16)250, (uint8)1, (uint16)340}
  /* SENT_A_SENT2_A_IN functionality */,
  {(uint16)250, (uint8)6, (uint16)66}
  /* Settings information for pad 251 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXD1_OUT functionality */,
  {(uint16)251, (uint8)1, (uint16)341}
  /* SENT_A_SENT3_A_IN functionality */,
  {(uint16)251, (uint8)6, (uint16)67}
  /* Settings information for pad 252 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXEN_OUT functionality */,
  {(uint16)252, (uint8)1, (uint16)342}
  /* SENT_A_SENT4_A_IN functionality */,
  {(uint16)252, (uint8)6, (uint16)68}
  /* Settings information for pad 253 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_RXD1_IN functionality */,
  {(uint16)253, (uint8)1, (uint16)343}
  /* SENT_A_SENT5_A_IN functionality */,
  {(uint16)253, (uint8)6, (uint16)69}
  /* Settings information for pad 254 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 255 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 256 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_CS0 functionality */,
  {(uint16)256, (uint8)1, (uint16)344}
  /* Settings information for pad 257 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_CS2 functionality */,
  {(uint16)257, (uint8)1, (uint16)345}
  /* EBI_D_ADD_DAT31 functionality */,
  {(uint16)257, (uint8)2, (uint16)346}
  /* Settings information for pad 258 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_CS3 functionality */,
  {(uint16)258, (uint8)1, (uint16)347}
  /* EBI_D_TEA functionality */,
  {(uint16)258, (uint8)2, (uint16)348}
  /* Settings information for pad 259 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD12 functionality */,
  {(uint16)259, (uint8)1, (uint16)349}
  /* Settings information for pad 260 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD13 functionality */,
  {(uint16)260, (uint8)1, (uint16)350}
  /* Settings information for pad 261 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD14 functionality */,
  {(uint16)261, (uint8)1, (uint16)351}
  /* Settings information for pad 262 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD15 functionality */,
  {(uint16)262, (uint8)1, (uint16)352}
  /* Settings information for pad 263 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD16 functionality */,
  {(uint16)263, (uint8)1, (uint16)353}
  /* EBI_D_ADD_DAT16 functionality */,
  {(uint16)263, (uint8)2, (uint16)354}
  /* Settings information for pad 264 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD17 functionality */,
  {(uint16)264, (uint8)1, (uint16)355}
  /* EBI_D_ADD_DAT17 functionality */,
  {(uint16)264, (uint8)2, (uint16)356}
  /* Settings information for pad 265 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD18 functionality */,
  {(uint16)265, (uint8)1, (uint16)357}
  /* EBI_D_ADD_DAT18 functionality */,
  {(uint16)265, (uint8)2, (uint16)358}
  /* Settings information for pad 266 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD19 functionality */,
  {(uint16)266, (uint8)1, (uint16)359}
  /* EBI_D_ADD_DAT19 functionality */,
  {(uint16)266, (uint8)2, (uint16)360}
  /* Settings information for pad 267 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD20 functionality */,
  {(uint16)267, (uint8)1, (uint16)361}
  /* EBI_D_ADD_DAT20 functionality */,
  {(uint16)267, (uint8)2, (uint16)362}
  /* Settings information for pad 268 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD21 functionality */,
  {(uint16)268, (uint8)1, (uint16)363}
  /* EBI_D_ADD_DAT21 functionality */,
  {(uint16)268, (uint8)2, (uint16)364}
  /* Settings information for pad 269 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD22 functionality */,
  {(uint16)269, (uint8)1, (uint16)365}
  /* EBI_D_ADD_DAT22 functionality */,
  {(uint16)269, (uint8)2, (uint16)366}
  /* Settings information for pad 270 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD23 functionality */,
  {(uint16)270, (uint8)1, (uint16)367}
  /* EBI_D_ADD_DAT23 functionality */,
  {(uint16)270, (uint8)2, (uint16)368}
  /* Settings information for pad 271 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD24 functionality */,
  {(uint16)271, (uint8)1, (uint16)369}
  /* EBI_D_ADD_DAT24 functionality */,
  {(uint16)271, (uint8)2, (uint16)370}
  /* Settings information for pad 272 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD25 functionality */,
  {(uint16)272, (uint8)1, (uint16)371}
  /* EBI_D_ADD_DAT25 functionality */,
  {(uint16)272, (uint8)2, (uint16)372}
  /* Settings information for pad 273 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD26 functionality */,
  {(uint16)273, (uint8)1, (uint16)373}
  /* EBI_D_ADD_DAT26 functionality */,
  {(uint16)273, (uint8)2, (uint16)374}
  /* Settings information for pad 274 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD27 functionality */,
  {(uint16)274, (uint8)1, (uint16)375}
  /* EBI_D_ADD_DAT27 functionality */,
  {(uint16)274, (uint8)2, (uint16)376}
  /* Settings information for pad 275 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD28 functionality */,
  {(uint16)275, (uint8)1, (uint16)377}
  /* EBI_D_ADD_DAT28 functionality */,
  {(uint16)275, (uint8)2, (uint16)378}
  /* Settings information for pad 276 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD29 functionality */,
  {(uint16)276, (uint8)1, (uint16)379}
  /* EBI_D_ADD_DAT29 functionality */,
  {(uint16)276, (uint8)2, (uint16)380}
  /* Settings information for pad 277 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD30 functionality */,
  {(uint16)277, (uint8)1, (uint16)381}
  /* EBI_D_ADD_DAT30 functionality */,
  {(uint16)277, (uint8)2, (uint16)382}
  /* Settings information for pad 278 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT0 functionality */,
  {(uint16)278, (uint8)1, (uint16)383}
  /* Settings information for pad 279 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT1 functionality */,
  {(uint16)279, (uint8)1, (uint16)384}
  /* Settings information for pad 280 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT2 functionality */,
  {(uint16)280, (uint8)1, (uint16)385}
  /* Settings information for pad 281 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT3 functionality */,
  {(uint16)281, (uint8)1, (uint16)386}
  /* Settings information for pad 282 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT4 functionality */,
  {(uint16)282, (uint8)1, (uint16)387}
  /* Settings information for pad 283 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT5 functionality */,
  {(uint16)283, (uint8)1, (uint16)388}
  /* Settings information for pad 284 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT6 functionality */,
  {(uint16)284, (uint8)1, (uint16)389}
  /* Settings information for pad 285 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT7 functionality */,
  {(uint16)285, (uint8)1, (uint16)390}
  /* Settings information for pad 286 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT8 functionality */,
  {(uint16)286, (uint8)1, (uint16)391}
  /* Settings information for pad 287 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT9 functionality */,
  {(uint16)287, (uint8)1, (uint16)392}
  /* Settings information for pad 288 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT10 functionality */,
  {(uint16)288, (uint8)1, (uint16)393}
  /* Settings information for pad 289 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT11 functionality */,
  {(uint16)289, (uint8)1, (uint16)394}
  /* Settings information for pad 290 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT12 functionality */,
  {(uint16)290, (uint8)1, (uint16)395}
  /* Settings information for pad 291 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT13 functionality */,
  {(uint16)291, (uint8)1, (uint16)396}
  /* Settings information for pad 292 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT14 functionality */,
  {(uint16)292, (uint8)1, (uint16)397}
  /* Settings information for pad 293 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_DAT15 functionality */,
  {(uint16)293, (uint8)1, (uint16)398}
  /* Settings information for pad 294 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_RD_WR functionality */,
  {(uint16)294, (uint8)1, (uint16)399}
  /* Settings information for pad 295 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_WE0 functionality */,
  {(uint16)295, (uint8)1, (uint16)400}
  /* Settings information for pad 296 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_WE1 functionality */,
  {(uint16)296, (uint8)1, (uint16)401}
  /* Settings information for pad 297 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_OE functionality */,
  {(uint16)297, (uint8)1, (uint16)402}
  /* Settings information for pad 298 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_TS functionality */,
  {(uint16)298, (uint8)1, (uint16)403}
  /* Settings information for pad 299 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ALE functionality */,
  {(uint16)299, (uint8)1, (uint16)404}
  /* Settings information for pad 300 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_TA functionality */,
  {(uint16)300, (uint8)1, (uint16)405}
  /* Settings information for pad 301 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_CS1 functionality */,
  {(uint16)301, (uint8)1, (uint16)406}
  /* Settings information for pad 302 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_BDIP functionality */,
  {(uint16)302, (uint8)1, (uint16)407}
  /* Settings information for pad 303 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_WE2 functionality */,
  {(uint16)303, (uint8)1, (uint16)408}
  /* Settings information for pad 304 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_WE3 functionality */,
  {(uint16)304, (uint8)1, (uint16)409}
  /* Settings information for pad 305 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD9 functionality */,
  {(uint16)305, (uint8)1, (uint16)410}
  /* Settings information for pad 306 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD10 functionality */,
  {(uint16)306, (uint8)1, (uint16)411}
  /* Settings information for pad 307 {PCR, Mode, Index to Mux or Inmux table} */
  /* EBI_D_ADD11 functionality */,
  {(uint16)307, (uint8)1, (uint16)412}
  /* Settings information for pad 308 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 309 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 310 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 311 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 312 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 313 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 314 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 315 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 316 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 317 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 318 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 319 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 320 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 321 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 322 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 323 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 324 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 325 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 326 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 327 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 328 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 329 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 330 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 331 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 332 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 333 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 334 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 335 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 336 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 337 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 338 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 339 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 340 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 341 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 342 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 343 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 344 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 345 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 346 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 347 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 348 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 349 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 350 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 351 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 352 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 353 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 354 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 355 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 356 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 357 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 358 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 359 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 360 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 361 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 362 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 363 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 364 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 365 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 366 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 367 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 368 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 369 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 370 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 371 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 372 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 373 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 374 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 375 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 376 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 377 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 378 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 379 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 380 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 381 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 382 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 383 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 384 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 385 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 386 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 387 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 388 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 389 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 390 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 391 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 392 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 393 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 394 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 395 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 396 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 397 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 398 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 399 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 400 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 401 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 402 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 403 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 404 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 405 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 406 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 407 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 408 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 409 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 410 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 411 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 412 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 413 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 414 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 415 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 416 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 417 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 418 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 419 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 420 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 421 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 422 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 423 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 424 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 425 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 426 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 427 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 428 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 429 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 430 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 431 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 432 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS18_OUT functionality */,
  {(uint16)432, (uint8)1, (uint16)413}
  /* DSPI_B_PCSB2 functionality */,
  {(uint16)432, (uint8)2, (uint16)414}
  /* eMIOS_B_EMIOS18_IN functionality */,
  {(uint16)432, (uint8)5, (uint16)70}
  /* Settings information for pad 433 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS19_OUT functionality */,
  {(uint16)433, (uint8)1, (uint16)415}
  /* DSPI_B_PCSB3 functionality */,
  {(uint16)433, (uint8)2, (uint16)416}
  /* eMIOS_B_EMIOS19_IN functionality */,
  {(uint16)433, (uint8)5, (uint16)71}
  /* Settings information for pad 434 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS20_OUT functionality */,
  {(uint16)434, (uint8)1, (uint16)417}
  /* DSPI_C_PCSC0_OUT functionality */,
  {(uint16)434, (uint8)2, (uint16)418}
  /* eMIOS_B_EMIOS20_IN functionality */,
  {(uint16)434, (uint8)5, (uint16)72}
  /* DSPI_C_PCSC0_IN functionality */,
  {(uint16)434, (uint8)6, (uint16)73}
  /* Settings information for pad 435 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS21_OUT functionality */,
  {(uint16)435, (uint8)1, (uint16)419}
  /* DSPI_C_PCSC1 functionality */,
  {(uint16)435, (uint8)2, (uint16)420}
  /* eMIOS_B_EMIOS21_IN functionality */,
  {(uint16)435, (uint8)5, (uint16)74}
  /* Settings information for pad 436 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS22_OUT functionality */,
  {(uint16)436, (uint8)1, (uint16)421}
  /* DSPI_C_PCSC2 functionality */,
  {(uint16)436, (uint8)2, (uint16)422}
  /* eMIOS_B_EMIOS22_IN functionality */,
  {(uint16)436, (uint8)5, (uint16)75}
  /* Settings information for pad 437 {PCR, Mode, Index to Mux or Inmux table} */
  /* eMIOS_B_EMIOS23_OUT functionality */,
  {(uint16)437, (uint8)1, (uint16)423}
  /* DSPI_C_PCSC5 functionality */,
  {(uint16)437, (uint8)2, (uint16)424}
  /* eMIOS_B_EMIOS23_IN functionality */,
  {(uint16)437, (uint8)5, (uint16)76}
  /* Settings information for pad 438 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 439 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 440 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_TCRCLKC_IN functionality */,
  {(uint16)440, (uint8)5, (uint16)77}
  /* SIU_A_IRQ6_IN functionality */,
  {(uint16)440, (uint8)6, (uint16)78}
  /* Settings information for pad 441 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC0_IN functionality */,
  {(uint16)441, (uint8)5, (uint16)79}
  /* SENT_A_SENT0_A_IN functionality */,
  {(uint16)441, (uint8)6, (uint16)80}
  /* Settings information for pad 442 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC1_IN functionality */,
  {(uint16)442, (uint8)5, (uint16)81}
  /* SENT_A_SENT1_A_IN functionality */,
  {(uint16)442, (uint8)6, (uint16)82}
  /* Settings information for pad 443 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC2_IN functionality */,
  {(uint16)443, (uint8)1, (uint16)425}
  /* SENT_A_SENT3_A_IN functionality */,
  {(uint16)443, (uint8)6, (uint16)83}
  /* Settings information for pad 444 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC3_IN functionality */,
  {(uint16)444, (uint8)5, (uint16)84}
  /* SENT_A_SENT4_A_IN functionality */,
  {(uint16)444, (uint8)6, (uint16)85}
  /* Settings information for pad 445 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC4_IN functionality */,
  {(uint16)445, (uint8)1, (uint16)426}
  /* SENT_A_SENT5_A_IN functionality */,
  {(uint16)445, (uint8)6, (uint16)86}
  /* eTPU_C_TCRCLKC_IN functionality */,
  {(uint16)445, (uint8)7, (uint16)87}
  /* Settings information for pad 446 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC5_IN functionality */,
  {(uint16)446, (uint8)1, (uint16)427}
  /* DSPI_E_PCSE2 functionality */,
  {(uint16)446, (uint8)2, (uint16)428}
  /* SENT_B_SENT0_B_IN functionality */,
  {(uint16)446, (uint8)7, (uint16)88}
  /* Settings information for pad 447 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC6_IN functionality */,
  {(uint16)447, (uint8)1, (uint16)429}
  /* DSPI_E_PCSE3 functionality */,
  {(uint16)447, (uint8)2, (uint16)430}
  /* SENT_B_SENT1_B_IN functionality */,
  {(uint16)447, (uint8)7, (uint16)89}
  /* Settings information for pad 448 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC7_IN functionality */,
  {(uint16)448, (uint8)1, (uint16)431}
  /* DSPI_E_PCSE4 functionality */,
  {(uint16)448, (uint8)2, (uint16)432}
  /* SENT_B_SENT2_B_IN functionality */,
  {(uint16)448, (uint8)7, (uint16)90}
  /* Settings information for pad 449 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC8_OUT functionality */,
  {(uint16)449, (uint8)1, (uint16)433}
  /* DSPI_E_PCSE5 functionality */,
  {(uint16)449, (uint8)2, (uint16)434}
  /* eTPU_C_ETPUC8_IN functionality */,
  {(uint16)449, (uint8)5, (uint16)91}
  /* SENT_B_SENT3_B_IN functionality */,
  {(uint16)449, (uint8)7, (uint16)92}
  /* Settings information for pad 450 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC9_IN functionality */,
  {(uint16)450, (uint8)5, (uint16)93}
  /* SIU_A_IRQ0_IN functionality */,
  {(uint16)450, (uint8)6, (uint16)94}
  /* SENT_B_SENT4_B_IN functionality */,
  {(uint16)450, (uint8)7, (uint16)95}
  /* Settings information for pad 451 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC10_OUT functionality */,
  {(uint16)451, (uint8)1, (uint16)435}
  /* eTPU_C_ETPUC10_IN functionality */,
  {(uint16)451, (uint8)5, (uint16)96}
  /* SIU_A_IRQ1_IN functionality */,
  {(uint16)451, (uint8)6, (uint16)97}
  /* SENT_B_SENT5_B_IN functionality */,
  {(uint16)451, (uint8)7, (uint16)98}
  /* Settings information for pad 452 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC11_OUT functionality */,
  {(uint16)452, (uint8)1, (uint16)436}
  /* eTPU_C_ETPUC11_IN functionality */,
  {(uint16)452, (uint8)5, (uint16)99}
  /* SIU_A_IRQ2_IN functionality */,
  {(uint16)452, (uint8)6, (uint16)100}
  /* Settings information for pad 453 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC12_OUT functionality */,
  {(uint16)453, (uint8)1, (uint16)437}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)453, (uint8)3, (uint16)438}
  /* eTPU_C_ETPUC12_IN functionality */,
  {(uint16)453, (uint8)5, (uint16)101}
  /* SIU_A_IRQ3_IN functionality */,
  {(uint16)453, (uint8)6, (uint16)102}
  /* Settings information for pad 454 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC13_OUT functionality */,
  {(uint16)454, (uint8)1, (uint16)439}
  /* PSI5A_SDOUT0_PSI5A_OUT functionality */,
  {(uint16)454, (uint8)3, (uint16)440}
  /* REACM_RCH0_C_OUT functionality */,
  {(uint16)454, (uint8)4, (uint16)441}
  /* eTPU_C_ETPUC13_IN functionality */,
  {(uint16)454, (uint8)5, (uint16)103}
  /* SIU_A_IRQ4_IN functionality */,
  {(uint16)454, (uint8)6, (uint16)104}
  /* Settings information for pad 455 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC14_OUT functionality */,
  {(uint16)455, (uint8)1, (uint16)442}
  /* PSI5A_SDIN0_PSI5A_IN functionality */,
  {(uint16)455, (uint8)3, (uint16)443}
  /* REACM_RCH1_C_OUT functionality */,
  {(uint16)455, (uint8)4, (uint16)444}
  /* eTPU_C_ETPUC14_IN functionality */,
  {(uint16)455, (uint8)5, (uint16)105}
  /* SIU_A_IRQ5_IN functionality */,
  {(uint16)455, (uint8)6, (uint16)106}
  /* Settings information for pad 456 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC15_OUT functionality */,
  {(uint16)456, (uint8)1, (uint16)445}
  /* REACM_RCH2_C_OUT functionality */,
  {(uint16)456, (uint8)3, (uint16)446}
  /* eTPU_C_ETPUC15_IN functionality */,
  {(uint16)456, (uint8)5, (uint16)107}
  /* MCAN_1_RX_IN functionality */,
  {(uint16)456, (uint8)6, (uint16)108}
  /* Settings information for pad 457 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC16_IN functionality */,
  {(uint16)457, (uint8)1, (uint16)447}
  /* MCAN_1_TX_OUT functionality */,
  {(uint16)457, (uint8)2, (uint16)448}
  /* REACM_RCH3_C_OUT functionality */,
  {(uint16)457, (uint8)3, (uint16)449}
  /* Settings information for pad 458 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC17_IN functionality */,
  {(uint16)458, (uint8)1, (uint16)450}
  /* eSCI_F_TXDF functionality */,
  {(uint16)458, (uint8)2, (uint16)451}
  /* REACM_RCH4_C_OUT functionality */,
  {(uint16)458, (uint8)3, (uint16)452}
  /* Settings information for pad 459 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC18_IN functionality */,
  {(uint16)459, (uint8)1, (uint16)453}
  /* eSCI_F_RXDF_IN functionality */,
  {(uint16)459, (uint8)2, (uint16)454}
  /* Settings information for pad 460 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC19_IN functionality */,
  {(uint16)460, (uint8)1, (uint16)455}
  /* PSI5A_SDOUT0_PSI5B_OUT functionality */,
  {(uint16)460, (uint8)3, (uint16)456}
  /* eSCI_A_TXDA functionality */,
  {(uint16)460, (uint8)6, (uint16)109}
  /* Settings information for pad 461 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC20_IN functionality */,
  {(uint16)461, (uint8)1, (uint16)457}
  /* PSI5A_SDIN0_PSI5B_IN functionality */,
  {(uint16)461, (uint8)3, (uint16)458}
  /* eSCI_A_RXDA_IN functionality */,
  {(uint16)461, (uint8)6, (uint16)110}
  /* Settings information for pad 462 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC21_IN functionality */,
  {(uint16)462, (uint8)1, (uint16)459}
  /* eSCI_B_TXDB functionality */,
  {(uint16)462, (uint8)6, (uint16)111}
  /* Settings information for pad 463 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC22_IN functionality */,
  {(uint16)463, (uint8)1, (uint16)460}
  /* eSCI_B_RXDB_IN functionality */,
  {(uint16)463, (uint8)6, (uint16)112}
  /* Settings information for pad 464 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC23_IN functionality */,
  {(uint16)464, (uint8)1, (uint16)461}
  /* DSPI_D_PCSD5 functionality */,
  {(uint16)464, (uint8)2, (uint16)462}
  /* eQADC_A_MAA0 functionality */,
  {(uint16)464, (uint8)3, (uint16)463}
  /* eQADC_B_MAB0 functionality */,
  {(uint16)464, (uint8)4, (uint16)464}
  /* Settings information for pad 465 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC24_IN functionality */,
  {(uint16)465, (uint8)1, (uint16)465}
  /* DSPI_D_PCSD4 functionality */,
  {(uint16)465, (uint8)2, (uint16)466}
  /* eQADC_A_MAA1 functionality */,
  {(uint16)465, (uint8)3, (uint16)467}
  /* eQADC_B_MAB1 functionality */,
  {(uint16)465, (uint8)4, (uint16)468}
  /* Settings information for pad 466 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC25_IN functionality */,
  {(uint16)466, (uint8)1, (uint16)469}
  /* DSPI_D_PCSD3 functionality */,
  {(uint16)466, (uint8)2, (uint16)470}
  /* eQADC_A_MAA2 functionality */,
  {(uint16)466, (uint8)3, (uint16)471}
  /* eQADC_B_MAB2 functionality */,
  {(uint16)466, (uint8)4, (uint16)472}
  /* Settings information for pad 467 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC26_IN functionality */,
  {(uint16)467, (uint8)1, (uint16)473}
  /* DSPI_D_PCSD2 functionality */,
  {(uint16)467, (uint8)2, (uint16)474}
  /* eQADC_B_MAB0 functionality */,
  {(uint16)467, (uint8)3, (uint16)475}
  /* Settings information for pad 468 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC27_IN functionality */,
  {(uint16)468, (uint8)1, (uint16)476}
  /* DSPI_D_PCSD1 functionality */,
  {(uint16)468, (uint8)2, (uint16)477}
  /* REACM_RCH5_C_OUT functionality */,
  {(uint16)468, (uint8)3, (uint16)478}
  /* eQADC_B_MAB1 functionality */,
  {(uint16)468, (uint8)4, (uint16)479}
  /* Settings information for pad 469 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC28_IN functionality */,
  {(uint16)469, (uint8)1, (uint16)480}
  /* DSPI_D_PCSD0_OUT functionality */,
  {(uint16)469, (uint8)2, (uint16)481}
  /* REACM_RCH6_C_OUT functionality */,
  {(uint16)469, (uint8)3, (uint16)482}
  /* eQADC_B_MAB2 functionality */,
  {(uint16)469, (uint8)4, (uint16)483}
  /* DSPI_D_PCSD0_IN functionality */,
  {(uint16)469, (uint8)6, (uint16)113}
  /* Settings information for pad 470 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC29_IN functionality */,
  {(uint16)470, (uint8)1, (uint16)484}
  /* DSPI_D_SCKD_OUT functionality */,
  {(uint16)470, (uint8)2, (uint16)485}
  /* REACM_RCH7_C_OUT functionality */,
  {(uint16)470, (uint8)3, (uint16)486}
  /* DSPI_D_SCKD_IN functionality */,
  {(uint16)470, (uint8)6, (uint16)114}
  /* Settings information for pad 471 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC30_IN functionality */,
  {(uint16)471, (uint8)1, (uint16)487}
  /* DSPI_D_SOUTD functionality */,
  {(uint16)471, (uint8)2, (uint16)488}
  /* REACM_RCH8_C_OUT functionality */,
  {(uint16)471, (uint8)3, (uint16)489}
  /* Settings information for pad 472 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC31_IN functionality */,
  {(uint16)472, (uint8)1, (uint16)490}
  /* REACM_RCH9_C_OUT functionality */,
  {(uint16)472, (uint8)3, (uint16)491}
  /* DSPI_D_SIND_IN functionality */,
  {(uint16)472, (uint8)6, (uint16)115}
  /* Settings information for pad 473 {PCR, Mode, Index to Mux or Inmux table} */
  /* Settings information for pad 474 {PCR, Mode, Index to Mux or Inmux table} */
  /* FEC_FEC_TXCLK_REFCLK_IN functionality */,
  {(uint16)474, (uint8)1, (uint16)492}
  /* SENT_B_SENT0_B_IN functionality */,
  {(uint16)474, (uint8)6, (uint16)116}
  /* Settings information for pad 475 {PCR, Mode, Index to Mux or Inmux table} */
  /* SENT_A_SENT2_A_IN functionality */,
  {(uint16)475, (uint8)5, (uint16)117}
  /* Settings information for pad 476 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA31_IN functionality */,
  {(uint16)476, (uint8)6, (uint16)118}
  /* eMIOS_A_EMIOS16_IN functionality */,
  {(uint16)476, (uint8)7, (uint16)119}
  /* Settings information for pad 477 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA30_IN functionality */,
  {(uint16)477, (uint8)6, (uint16)120}
  /* eMIOS_A_EMIOS17_IN functionality */,
  {(uint16)477, (uint8)7, (uint16)121}
  /* Settings information for pad 478 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA29_IN functionality */,
  {(uint16)478, (uint8)6, (uint16)122}
  /* eMIOS_A_EMIOS18_IN functionality */,
  {(uint16)478, (uint8)7, (uint16)123}
  /* Settings information for pad 479 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA28_IN functionality */,
  {(uint16)479, (uint8)6, (uint16)124}
  /* eMIOS_A_EMIOS19_IN functionality */,
  {(uint16)479, (uint8)7, (uint16)125}
  /* Settings information for pad 480 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA27_IN functionality */,
  {(uint16)480, (uint8)6, (uint16)126}
  /* eMIOS_A_EMIOS20_IN functionality */,
  {(uint16)480, (uint8)7, (uint16)127}
  /* Settings information for pad 481 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA26_IN functionality */,
  {(uint16)481, (uint8)6, (uint16)128}
  /* eMIOS_A_EMIOS21_IN functionality */,
  {(uint16)481, (uint8)7, (uint16)129}
  /* Settings information for pad 482 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA25_IN functionality */,
  {(uint16)482, (uint8)6, (uint16)130}
  /* eMIOS_A_EMIOS22_IN functionality */,
  {(uint16)482, (uint8)7, (uint16)131}
  /* Settings information for pad 483 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_A_ETPUA24_IN functionality */,
  {(uint16)483, (uint8)6, (uint16)132}
  /* eMIOS_A_EMIOS23_IN functionality */,
  {(uint16)483, (uint8)7, (uint16)133}
  /* Settings information for pad 484 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC15_IN functionality */,
  {(uint16)484, (uint8)6, (uint16)134}
  /* eMIOS_B_EMIOS16_IN functionality */,
  {(uint16)484, (uint8)7, (uint16)135}
  /* Settings information for pad 485 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC14_IN functionality */,
  {(uint16)485, (uint8)6, (uint16)136}
  /* eMIOS_B_EMIOS17_IN functionality */,
  {(uint16)485, (uint8)7, (uint16)137}
  /* Settings information for pad 486 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC13_IN functionality */,
  {(uint16)486, (uint8)6, (uint16)138}
  /* eMIOS_B_EMIOS18_IN functionality */,
  {(uint16)486, (uint8)7, (uint16)139}
  /* Settings information for pad 487 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC12_IN functionality */,
  {(uint16)487, (uint8)6, (uint16)140}
  /* eMIOS_B_EMIOS19_IN functionality */,
  {(uint16)487, (uint8)7, (uint16)141}
  /* Settings information for pad 488 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC11_IN functionality */,
  {(uint16)488, (uint8)6, (uint16)142}
  /* eMIOS_B_EMIOS20_IN functionality */,
  {(uint16)488, (uint8)7, (uint16)143}
  /* Settings information for pad 489 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC10_IN functionality */,
  {(uint16)489, (uint8)6, (uint16)144}
  /* eMIOS_B_EMIOS21_IN functionality */,
  {(uint16)489, (uint8)7, (uint16)145}
  /* Settings information for pad 490 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC9_IN functionality */,
  {(uint16)490, (uint8)6, (uint16)146}
  /* eMIOS_B_EMIOS22_IN functionality */,
  {(uint16)490, (uint8)7, (uint16)147}
  /* Settings information for pad 491 {PCR, Mode, Index to Mux or Inmux table} */
  /* eTPU_C_ETPUC8_IN functionality */,
  {(uint16)491, (uint8)6, (uint16)148}
  /* eMIOS_B_EMIOS23_IN functionality */,
  {(uint16)491, (uint8)7, (uint16)149}
[!ENDVAR!]


[!VAR "SIZE_OF_MUX_TABLE_2"!][!//
493[!//
[!ENDVAR!]


[!VAR "SIZE_OF_INMUX_TABLE_2"!][!//
150[!//
[!ENDVAR!]


[!VAR "SIZE_OF_INDEX_TABLE_2"!][!//
((uint16)(643))[!//
[!ENDVAR!]

[!ENDIF!][!//avoid multiple inclusion
