/**
*   @file    Eth_Fec_Reg_Sys.h
*   @version 1.0.1
*
*   @brief   AUTOSAR FEC Registers and Macros Definitions.
*   @details Header file for FEC Registers and Macros Definitions.
*
*   @addtogroup FR_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : FEC
*   Dependencies         : 
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP 
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/


#ifndef ETH_FEC_REG_SYS_H
#define ETH_FEC_REG_SYS_H

#ifdef __cplusplus
extern "C" {
#endif

/**
* @page misra_violations MISRA-C:2012 violations
* 
* @section Eth_Fec_Reg_Sys_h_REF_1
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
*
* @section Eth_Fec_Reg_Sys_h_REF_2
* Violates MISRA 2012 Advisory Rule 4.9, A function should be used in preference to a function-like macro where they are interchangeable.
*
* @section Eth_Fec_Reg_Sys_h_REF_3
* Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
*
* @section Eth_Fec_Reg_Sys_h_REF_4
* Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space shall be distinct.
*
* @section Eth_Fec_Reg_Sys_h_REF_5
* Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
*
* @section Eth_Fec_Reg_Sys_h_REF_6
* Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
*/

/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
/** 
* @file        Eth_Fec_Reg_Sys.h
* @brief Include IP module versions
*/
#include "Platform_Types.h"
#include "Soc_Ips.h"
/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define ETH_VENDOR_ID_REG_SYS_H                    43
#define ETH_MODULE_ID_REG_SYS_H                    88
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_3 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_4 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_5 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_6 */
#define ETH_AR_RELEASE_MAJOR_VERSION_REG_SYS_H     4
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_3 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_4 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_5 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_6 */
#define ETH_AR_RELEASE_MINOR_VERSION_REG_SYS_H     3
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_3 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_4 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_5 */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_6 */
#define ETH_AR_RELEASE_REVISION_VERSION_REG_SYS_H  1
#define ETH_SW_MAJOR_VERSION_REG_SYS_H             1
#define ETH_SW_MINOR_VERSION_REG_SYS_H             0
#define ETH_SW_PATCH_VERSION_REG_SYS_H             0
/*==================================================================================================
*                                      FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if source file and Platform_Types.h header file are of the same Autosar version */
    #if ((ETH_AR_RELEASE_MAJOR_VERSION_REG_SYS_H != PLATFORM_AR_RELEASE_MAJOR_VERSION) || \
         (ETH_AR_RELEASE_MINOR_VERSION_REG_SYS_H != PLATFORM_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Eth_Fec_Reg_Sys.h and Platform_Types.h are different"
    #endif
    /* Check if source file and Soc_Ips.h header file are of the same Autosar version */
    #if ((ETH_AR_RELEASE_MAJOR_VERSION_REG_SYS_H != SOC_IPS_AR_RELEASE_MAJOR_VERSION) || \
         (ETH_AR_RELEASE_MINOR_VERSION_REG_SYS_H != SOC_IPS_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Eth_Fec_Reg_Sys.h and Soc_Ips.h are different"
    #endif
#endif
/*==================================================================================================
*                                          CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      DEFINES AND MACROS
==================================================================================================*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_ADDR16   0x0004U /**< Interrupt Event Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_ADDR16  0x0008U /**< Interrupt Mask Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_RDAR_ADDR16  0x0010U /**< Receive Descriptor Active Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_TDAR_ADDR16  0x0014U /**< Transmit Descriptor Active Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_ECR_ADDR16   0x0024U /**< Ethernet Control Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_ADDR16  0x0040U /**< MII Management Frame Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MSCR_ADDR16  0x0044U /**< MII Speed Control Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MIBC_ADDR16  0x0064U /**< MIB Control/Status Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_RCR_ADDR16   0x0084U /**< Receive Control Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_TCR_ADDR16   0x00C4U /**< Transmit Control Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_PALR_ADDR16  0x00E4U /**< MAC Address Low Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_PAUR_ADDR16  0x00E8U /**< MAC Address Upper Register + Type Field */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_OPD_ADDR16   0x00ECU /**< Opcode + Pause Duration Fields */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_IAUR_ADDR16  0x0118U /**< Upper 32 bits of Individual Hash Table */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_IALR_ADDR16  0x011CU /**< Lower 32 Bits of Individual Hash Table */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_GAUR_ADDR16  0x0120U /**< Upper 32 bits of Group Hash Table */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_GALR_ADDR16  0x0124U /**< Lower 32 bits of Group Hash Table */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_TFWR_ADDR16  0x0144U /**< Transmit FIFO Watermark */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_FRBR_ADDR16  0x014CU /**< FIFO Receive Bound Register */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_FRSR_ADDR16  0x0150U /**< FIFO Receive FIFO Start Registers */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_ERDSR_ADDR16 0x0180U /**< Pointer to Receive Descriptor Ring */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_ETDSR_ADDR16 0x0184U /**< Transmit Buffer Descriptor Ring Start Reg. */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EMRBR_ADDR16 0x0188U /**< Receive Buffer Size Register */
/***************************************************************************
* Register Bits Macros 
***************************************************************************/
/* EIR register bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_HBERR_U32 0x80000000U /* Heartbeat error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_BABR_U32  0x40000000U /* Babbling receive error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_BABT_U32  0x20000000U /* Babbling transmit error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_GRA_U32   0x10000000U /* Graceful stop complete */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_TXF_U32   0x08000000U /* Transmit frame interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_TXB_U32   0x04000000U /* Transmit buffer interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_RXF_U32   0x02000000U /* Receive frame interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_RXB_U32   0x01000000U /* Receive buffer interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_MII_U32   0x00800000U /* MII interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_EBERR_U32 0x00400000U /* Ethernet bus error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_LC_U32    0x00200000U /* Late collision */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_RL_U32    0x00100000U /* Collision retry limit */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_UN_U32    0x00080000U /* Transmit FIFO underrun */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_ALL_U32   0xFFF80000U /* All bits */

/* EIR register bits for write-1-to-clear operations */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_EIR_HBERR_W1C 0x80000000U /* Heartbeat error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_BABR_W1C  0x40000000U /* Babbling receive error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_BABT_W1C  0x20000000U /* Babbling transmit error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_GRA_W1C   0x10000000U /* Graceful stop complete */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_TXF_W1C   0x08000000U /* Transmit frame interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_TXB_W1C   0x04000000U /* Transmit buffer interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_RXF_W1C   0x02000000U /* Receive frame interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_RXB_W1C   0x01000000U /* Receive buffer interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_MII_W1C   0x00800000U /* MII interrupt */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_EBERR_W1C 0x00400000U /* Ethernet bus error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_LC_W1C    0x00200000U /* Late collision */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_RL_W1C    0x00100000U /* Collision retry limit */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_UN_W1C    0x00080000U /* Transmit FIFO underrun */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIR_ALL_W1C   0xFFF80000U /* All bits */

/* EIMR register bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_HBERR_U32 0x80000000U /* Heartbeat error interrupt enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_BABR_U32  0x40000000U /* Babbling receive error int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_BABT_U32  0x20000000U /* Babbling transmit error int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_GRA_U32   0x10000000U /* Graceful stop complete int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_TXF_U32   0x08000000U /* Transmit frame int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_TXB_U32   0x04000000U /* Transmit buffer int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_RXF_U32   0x02000000U /* Receive frame int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_RXB_U32   0x01000000U /* Receive buffer int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_MII_U32   0x00800000U /* MII interrupt enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_EBERR_U32 0x00400000U /* Ethernet bus error interrupt enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_LC_U32    0x00200000U /* Late collision interrupt enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_RL_U32    0x00100000U /* Collision retry limit int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_UN_U32    0x00080000U /* Transmit FIFO underrun int. enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_EIMR_ALL_U32   0xFFF80000U /* All bits */
/* RDAR register bit*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_RDAR_R_DES_ACTIVE_U32 0x01000000U /* Empty Rx buffer exists */
/* TDAR register bit*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_TDAR_X_DES_ACTIVE_U32 0x01000000U /* Empty Tx buffer exists */
/* ECR register bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_ECR_ETHER_EN_U32 0x00000002U /* Enable the controller */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_ECR_RESET_U32    0x00000001U /* Reset the controller */
/* MMFR register bitfield masks and default values */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_ST_U32      0xC0000000U /* Start of frame delimiter */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_OP_U32      0x30000000U /* Operation */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_PA_U32      0x0F800000U /* PHY address */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_RA_U32      0x007C0000U /* Register address */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_TA_U32      0x00030000U /* Turn around */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_DATA_U32    0x0000FFFFU /* Data */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_ST_VAL_U32  0x40000000U /* 802.3 compliant value for ST field (22.2.4.5.3 in 2008 version) */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_OP_READ_U32 0x20000000U /* Operation "read" according to 802.3(22.2.4.5.4 in 2008 version) */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_OP_WRITE_U32 0x10000000U /* Operation "write" according to 802.3 (22.2.4.5.4 in 2008 version) */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MMFR_TA_VAL_U32  0x00020000U /* 802.3 compliant value for TA field (22.2.4.5.7 in 2008 version)  */
/* MSCR register bit mask and bitfield mask */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MSCR_DIS_PREAMBLE_U32 0x00000080U /* Disable preamble */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MCSR_MII_SPEED_U32    0x0000007EU /* Speed bitfield mask */ 
/* MIB register bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_MIBC_MIB_DISABLE_U32  0x80000000U /* Disable/enable trigger*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_MIBC_MIB_IDLE_U32     0x40000000U /* Disable/enable indicator */
/* RCR register bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_RCR_MAX_FL_U32   0x07FF0000U /* */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_FCE_U32      0x00000020U /* */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_BC_REJ_U32   0x00000010U /* Reject broadcast */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_PROM_U32     0x00000008U /* Promiscuous mode */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_MII_MODE_U32 0x00000004U /* */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_DRT_U32      0x00000002U /* */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_LOOP_U32     0x00000001U /* Loopback enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RCR_INIT_VAL_U32 0x05EE0001U /* Initial register value */
/* TCR register bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TCR_RFC_PAUSE_U32 0x00000010U /* Receive pause frame */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TCR_TFC_PAUSE_U32 0x00000008U /* Transmit pause frame trigger */ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TCR_FDEN_U32      0x00000004U /* Full duplex enable */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TCR_HBC_U32       0x00000002U /* Heartbeat control */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TCR_GTS_U32       0x00000001U /* Graceful transmit stop */
/* PAUR register bitfields */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_PAUR_PADDR2_U32   0xFFFF0000U
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_PAUR_TYPE_U32     0x0000FFFFU
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_PAUR_TYPE_INIT_VAL_U32 0x00008808U
/* OPD register bitfields */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_OPD_OPCODE_U32    0xFFFF0000U
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_OPD_PAUSE_DUR_U32 0x0000FFFFU
/* TFWR register bitfield */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_TFWR_X_WMRK_U32   0x00000003U
/* FRBR register bitfield */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_FRBR_R_BOUND_U32  0x000003FCU
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_FRBR_RESERVED_U32 0x00000400U /* Reserved bit with value 1 */
/* FRSR register bitfield */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_FRSR_R_FSTART_U32 0x000003FCU
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_FRSR_RESERVED_U32 0x00000400U /* Reserved bit with value 1 */
/* ERDSR register bitfield */
#define FEC_ERDSR_R_DES_START_U32 0xFFFFFFFCU
/* ETDSR register bitfield */
#define FEC_ETDSR_X_DES_START_U32 0xFFFFFFFCU
/* EMRBR register bitfield */
#define FEC_EMRBR_R_BUF_SIZE_U32  0x000007F0U
/***************************************************************************
* Buffer Descriptors Bits
***************************************************************************/
/* RX BDs */
#define FEC_RXBD_E_U32      0x80000000U /* Receive buffer empty */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RXBD_R01_U32    0x40000000U /* User bit 1*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_RXBD_W_U32      0x20000000U /* Last descriptor in the ring */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RXBD_RO2_U32    0x10000000U /* User bit 2 */
#define FEC_RXBD_L_U32      0x08000000U /* Last buffer in the received frame */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RXBD_M_U32      0x01000000U /* Frame received in promiscuous mode (would not be received if not promiscuous)*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_BC_U32     0x00800000U /* Frame received as broadcast */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_RXBD_MC_U32     0x00400000U /* Frame received as multicast but not broadcast */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_LG_U32     0x00200000U /* Frame length violation */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_NO_U32     0x00100000U /* Non octet aligned frame */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_CR_U32     0x00040000U /* CRC error */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_OV_U32     0x00020000U /* FIFO overrun during reception */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_TR_U32     0x00010000U /* Frame was longer than 2047B and therefore was truncated */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RXBD_LENGTH_U32 0x0000FFFFU /* Buffer length bitfield mask */
/* TX BDs */
#define FEC_TXBD_R_U32      0x80000000U /* Transmit buffer is ready for
                                        transmission (filled with data) */
#define FEC_TXBD_TO1_U32    0x40000000U /* User bit 1 */
#define FEC_TXBD_W_U32      0x20000000U /* Last descriptor in the ring */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TXBD_TO2_U32    0x10000000U /* User bit 2 */
#define FEC_TXBD_L_U32      0x08000000U /* Last buffer in the transmitted frame */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TXBD_TC_U32     0x04000000U /* Compute and append CRC to the frame */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TXBD_ABC_U32    0x02000000U /* Append the bad CRC to the frame */ 
#define FEC_TXBD_LENGTH_U32 0x0000FFFFU /* Buffer length bitfield mask */

/**
* @brief Define the RX status
*/
/* RX Frame status bits - frame reception mode */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define ETH_FEC_RXF_PROMISCUOUS     0x01000000U /* Frame received in promiscuous mode (would not be received if not promiscuous) */
#define ETH_FEC_RXF_ERRORS_MASK     0x86370000U /* Mask for previous bits */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define ETH_FEC_RXF_MULTICAST       0x00400000U /* Frame received as multicast but not broadcast */
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define ETH_FEC_RXF_BROADCAST       0x00800000U /* Frame received as broadcast */

#define ETH_FEC_BD_SIZE             8U

/*******************************************************************************
* MIB Counters Offset Macros
*******************************************************************************/
/**
*   @def FEC_RMON_T_DROP_ADDR16
*   @brief Count of frames not counted correctly
*   @details RFC 1757 counter counting number of events where the 
*            transmitted frame was dropped from counting due to lack 
*            of resources.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_DROP_ADDR16        0x0200U 
/**
*   @def FEC_RMON_T_PACKETS_ADDR16
*   @brief Transmitted Packets count
*   @details RFC 1757 counter counting number of all transmitted frames 
*            (including broadcast and multicast frames).
*                 
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_PACKETS_ADDR16     0x0204U
/**
*   @def FEC_RMON_T_BC_PKT_ADDR16 
*   @brief Transmitted Broadcast Packets count
*   @details RFC 1757 counter counting number of transmitted broadcast 
*            frames (multicast frames are excluded).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_BC_PKT_ADDR16      0x0208U
/**
*   @def FEC_RMON_T_MC_PKT_ADDR16
*   @brief Transmitted Multicast Packets count
*   @details RFC 1757 counter counting number of transmitted multicast 
*            frames (broadcast frames excluded).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_MC_PKT_ADDR16      0x020CU 
/**
*   @def FEC_RMON_T_CRC_ALIGN_ADDR16
*   @brief Transmitted Packets with CRC or Align error count
*   @details RFC 1757 counter counting number of transmitted frames of 
*            length between 64 and 1518 bytes inclusive that were sent
*            with bad CRC (or not integral number of octets - this can occur
*            only when the controller is reset).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_CRC_ALIGN_ADDR16   0x0210U
/**
*   @def FEC_RMON_T_UNDERSIZE_ADDR16
*   @brief Transmitted Packets < 64 bytes, good CRC
*   @details RFC 1757 counter counting number of frames transmitted with 
*            good CRC and less then 64 bytes. This can occur only when the
*            controller is stopped.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_UNDERSIZE_ADDR16   0x0214U 
/**
*   @def FEC_RMON_T_OVERSIZE_ADDR16
*   @brief Transmitted Packets > MAX_FL bytes, good CRC
*   @details RFC 1757 counter counting number of frames transmitted with 
*            good CRC but with length greater than length of one receive
*            buffer (transmit buffer length shall be less than or equal
*            to the receive buffer length).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_OVERSIZE_ADDR16    0x0218U
/**
*   @def FEC_RMON_T_FRAG_ADDR16
*   @brief Transmitted Packets < 64 bytes, bad CRC
*   @details RFC 1757 counter counting number of transmitted frame 
*            fragments - they have bad CRC and are shorter than 64 bytes
*            (they have been cut - can occur when the controller is reset).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_FRAG_ADDR16        0x021CU 
/**
*   @def FEC_RMON_T_JAB_ADDR16
*   @brief Transmitted Packets > MAX_FL bytes, bad CRC
*   @details RFC 1757 counter counting number of transmitted frames with 
*            length greater than configured receive buffer length and bad 
*            CRC.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_JAB_ADDR16         0x0220U 
/**
*   @def FEC_RMON_T_COL_ADDR16
*   @brief Transmission collisions count
*   @details RFC 1757 counter counting number of collisions during
*            transmission.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_COL_ADDR16         0x0224U 
/**
*   @def FEC_RMON_T_P64_ADDR16
*   @brief Transmitted packets with length equal to 64 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length equal to 64 bytes (including bad ones).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_P64_ADDR16         0x0228U
/**
*   @def FEC_RMON_T_P65TO127_ADDR16
*   @brief Transmitted packets with length 65 to 127 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length between 65 and 127 inclusive 
*            (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_P65TO127_ADDR16    0x022CU 
/**
*   @def FEC_RMON_T_P128TO255_ADDR16
*   @brief Transmitted packets with length 128 to 255 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length between 128 and 255 inclusive 
*            (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */    
#define FEC_RMON_T_P128TO255_ADDR16   0x0230U
/**
*   @def FEC_RMON_T_P256TO511_ADDR16
*   @brief Transmitted packets with length 256 to 511 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length between 256 and 511 inclusive 
*            (including bad frames).
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */               
#define FEC_RMON_T_P256TO511_ADDR16   0x0234U 
/**
*   @def FEC_RMON_T_P512TO1023_ADDR16
*   @brief Transmitted packets with length 512 to 1023 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length between 512 and 1023 inclusive 
*            (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_P512TO1023_ADDR16  0x0238U 
/**
*   @def FEC_RMON_T_P1024TO2047_ADDR16
*   @brief Transmitted packets with length 1024 to 2047 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length between 1024 and 2047 inclusive 
*            (including bad frames).
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */           
#define FEC_RMON_T_P1024TO2047_ADDR16 0x023CU 
/**
*   @def FEC_RMON_T_P_GTE2048_ADDR16
*   @brief Transmitted packets with length greater than 2047 byte count 
*   @details RFC 1757 counter counting number of transmitted frames
*            with length greater or equal to 2048 
*            (including bad frames).
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */           
#define FEC_RMON_T_P_GTE2048_ADDR16   0x0240U 
/**
*   @def FEC_RMON_T_OCTETS_ADDR16
*   @brief Transmitted octets count
*   @details RFC 1757 counter counting total number of transmitted bytes -
*   header (14 B), frame payload, frame pad and crc (4 B) bytes are counted.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_T_OCTETS_ADDR16      0x0244U 
/**
*   @def FEC_IEEE_T_DROP_ADDR16
*   @brief Count of frames not counted correctly 
*   @details IEEE 802.3 counter counting transmitted frames which could
*            not be successfully counted due to a lack of needed resources.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_T_DROP_ADDR16        0x0248U
/**
*   @def FEC_IEEE_T_FRAME_OK_ADDR16
*   @brief  Frames Transmitted OK 
*   @details IEEE 802.3 counter counting successfully transmitted frames 
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_T_FRAME_OK_ADDR16    0x024CU
/**
*   @def FEC_IEEE_T_1COL_ADDR16
*   @brief Frames Transmitted with Single Collision
*   @details IEEE 802.3 counter counting successfully transmitted frames 
*           involved in one collision (collision and then successful 
*           transmission).         
*/    
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_IEEE_T_1COL_ADDR16        0x0250U
/**
*   @def FEC_IEEE_T_MCOL_ADDR16
*   @brief  Frames Transmitted with Multiple Collisions
*   @details IEEE 802.3 counter counting successfully transmitted frames 
*            involved in more collisions (n collisions and then successful 
*            transmission).   
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_IEEE_T_MCOL_ADDR16        0x0254U
/**
*   @def FEC_IEEE_T_DEF_ADDR16
*   @brief  Frames Transmitted after Deferral Delay
*   @details IEEE 802.3 counter counting frames with delayed transmission 
*            because of bussy medium.
*/   
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_IEEE_T_DEF_ADDR16         0x0258U
/**
*   @def FEC_IEEE_T_LCOL_ADDR16
*   @brief Frames Transmitted with Late Collision
*   @details IEEE 802.3 counter counting transmitted frames with a 
*           collision after the 512th bit. Other collision counters
*           may be also implemented if their conditions are met.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_IEEE_T_LCOL_ADDR16        0x025CU
/**
*   @def FEC_IEEE_T_EXCOL_ADDR16
*   @brief Frames Transmitted with Excessive Collisions
*   @details IEEE 802.3 counter counting frames which transmission was 
*            aborted due to excessive collisions. Frames have not been sent.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_T_EXCOL_ADDR16       0x0260U
/**
*   @def FEC_IEEE_T_MACERR_ADDR16 
*   @brief Frames Transmitted with Tx FIFO Underrun
*   @details IEEE 802.3 counter counting number of transmit FIFO underruns.
*            Transmit FIFO underrun results in discarding the frame being 
*            currently transmitted.      
*/  
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_IEEE_T_MACERR_ADDR16      0x0264U 
/**
*   @def FEC_IEEE_T_CSERR_ADDR16
*   @brief Carrier Sense Errors count 
*   @details IEEE 802.3 counter counting carrier sense deasertions while 
*            transmitting a frame not involved in a collision.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_T_CSERR_ADDR16       0x0268U 
/**
*   @def FEC_IEEE_T_SQE_ADDR16
*   @brief SQE_TEST_ERROR receptions count
*/  
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */  
#define FEC_IEEE_T_SQE_ADDR16         0x026CU 
/**
*   @def FEC_IEEE_T_FDXFC_ADDR16
*   @brief Flow Control Pause frames transmitted count
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_T_FDXFC_ADDR16       0x0270U
/**
*   @def FEC_IEEE_T_OCTETS_OK_ADDR16
*   @brief Octet count for Frames Transmitted w/o Error
*   @details IEEE 802.3 counter ciounting number of correctly transmitted 
*            bytes.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */    
#define FEC_IEEE_T_OCTETS_OK_ADDR16   0x0274U
/**
*   @def FEC_RMON_R_DROP_ADDR16
*   @brief Count of received frames not counted correctly
*   @details RFC 1757 counter counting number of received frames not counted correctly.
*                 
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_DROP_ADDR16             0x0280U
/**
*   @def FEC_RMON_R_PACKETS_ADDR16
*   @brief received Packets count
*   @details RFC 1757 counter counting number of all received frames 
*            (including broadcast and multicast frames).
*                 
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_PACKETS_ADDR16     0x0284U 
/**
*   @def FEC_RMON_R_BC_PKT_ADDR16 
*   @brief Received Broadcast Packets count
*   @details RFC 1757 counter counting number of received broadcast 
*            frames (multicast frames are excluded).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_BC_PKT_ADDR16      0x0288U
/**
*   @def FEC_RMON_R_MC_PKT_ADDR16
*   @brief Received Multicast Packets count
*   @details RFC 1757 counter counting number of received multicast 
*            frames (broadcast frames excluded).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_MC_PKT_ADDR16      0x028CU
/**
*   @def FEC_RMON_R_CRC_ALIGN_ADDR16
*   @brief Received Packets with CRC or Align error count
*   @details RFC 1757 counter counting number of transmitted frames of 
*            length between 64 and 1518 bytes inclusive that were received
*            with bad CRC or not integral number of octets.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_CRC_ALIGN_ADDR16   0x0290U 
/**
*   @def FEC_RMON_R_UNDERSIZE_ADDR16
*   @brief Received Packets < 64 bytes, good CRC
*   @details RFC 1757 counter counting number of frames received with 
*            good CRC and less then 64 bytes.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_UNDERSIZE_ADDR16   0x0294U 
/**
*   @def FEC_RMON_R_OVERSIZE_ADDR16
*   @brief Received Packets > MAX_FL bytes, good CRC
*   @details RFC 1757 counter counting number of frames received with 
*            good CRC but with length greater than length of one receive
*            buffer (frame is stored into more buffers).
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_RMON_R_OVERSIZE_ADDR16    0x0298U 
/**
*   @def FEC_RMON_R_FRAG_ADDR16
*   @brief Received Packets < 64 bytes, bad CRC
*   @details RFC 1757 counter counting number of received frame 
*            fragments - they have bad CRC and are shorter than 64 bytes.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_FRAG_ADDR16        0x029CU 
/**
*   @def FEC_RMON_R_JAB_ADDR16
*   @brief Received Packets > MAX_FL bytes, bad CRC
*   @details RFC 1757 counter counting number of received frames with 
*            length greater than configured receive buffer length and bad 
*            CRC.        
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_JAB_ADDR16         0x02A0U 
/**
*   @def FEC_RMON_R_P64_ADDR16
*   @brief Received packets with length equal to 64 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length equal to 64 bytes (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_P64_ADDR16         0x02A8U
/**
*   @def FEC_RMON_R_P65TO127_ADDR16
*   @brief Received packets with length 65 to 127 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length between 65 and 127 inclusive 
*            (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_P65TO127_ADDR16    0x02ACU
/**
*   @def FEC_RMON_R_P128TO255_ADDR16
*   @brief Received packets with length 128 to 255 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length between 128 and 255 inclusive 
*            (including bad frames).*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_P128TO255_ADDR16   0x02B0U
/**
*   @def FEC_RMON_R_P256TO511_ADDR16
*   @brief Received packets with length 256 to 511 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length between 256 and 511 inclusive
*            (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_P256TO511_ADDR16   0x02B4U
/**
*   @def FEC_RMON_R_P512TO1023_ADDR16
*   @brief Received packets with length 512 to 1023 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length between 512 and 1023 inclusive
*            (including bad frames).
*/    
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_P512TO1023_ADDR16  0x02B8U
/**
*   @def FEC_RMON_R_P1024TO2047_ADDR16
*   @brief Received packets with length 1024 to 2047 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length between 1024 and 2047 inclusive
*            (including bad frames).
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_RMON_R_P1024TO2047_ADDR16 0x02BCU
/**
*   @def FEC_RMON_R_P_GTE2048_ADDR16
*   @brief Received packets with length greater than 2047 byte count 
*   @details RFC 1757 counter counting number of received frames
*            with length greater or equal to 2048
*            (including bad frames).
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_P_GTE2048_ADDR16   0x02C0U
/**
*   @def FEC_RMON_R_OCTETS_ADDR16
*   @brief Received octets count
*   @details RFC 1757 counter counting total number of received bytes
*            (preamble and SFD are excluded) i.e. header (14 B), 
*            frame payload, frame pad and crc (4 B) bytes are counted.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_RMON_R_OCTETS_ADDR16      0x02C4U
/**
*   @def FEC_IEEE_R_DROP_ADDR16
*   @brief Count of frames not counted correctly 
*   @details IEEE 802.3 counter counting received frames which could
*            not be successfully counted due to a lack of needed resources.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_R_DROP_ADDR16        0x02C8U
/**
*   @def FEC_IEEE_R_FRAME_OK_ADDR16
*   @brief Frames Received OK
*   @details IEEE 802.3 counter counting received frames without CRC error, 
*           alignment error which are not too long (64-1518 bytes).
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_R_FRAME_OK_ADDR16    0x02CCU
/**
*   @def FEC_IEEE_R_CRC_ADDR16
*   @brief Frames Received with CRC Error
*   @details IEEE 802.3 counter counting received frames with bad CRC but
*            with integral number of octets.
*/  
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_IEEE_R_CRC_ADDR16         0x02D0U
/**
*   @def FEC_IEEE_R_ALIGN_ADDR16
*   @brief Frames Received with Alignment Error
*   @details IEEE 802.3 counter counting received frames with bad CRC and
*            with not integral number of octets.
*/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */ 
#define FEC_IEEE_R_ALIGN_ADDR16       0x02D4U
/**
*   @def FEC_IEEE_R_MACERR_ADDR16
*   @brief Receive Fifo Overflow count
*   @details IEEE 802.3 counter counting received frames which are damaged 
*            due to internal receive FIFO overflow error.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_R_MACERR_ADDR16      0x02D8U
/**
*   @def FEC_IEEE_R_FDXFC_ADDR16
*   @brief Flow Control Pause frames received
*   @details IEEE 802.3 counter counting  number of received flow control 
*            pause frames.
*/ 
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */   
#define FEC_IEEE_R_FDXFC_ADDR16       0x02DCU
/**
*   @def FEC_IEEE_R_OCTETS_OK_ADDR16
*   @brief Octet count for Frames received without an error 
*   @details  IEEE 802.3 counter counting received bytes of data and pad
*             in correctly received frames (no error).
*/ 
#define FEC_IEEE_R_OCTETS_OK_ADDR16   0x02E0U

/***************************************************************************
* TX Buffer Status Bits
***************************************************************************/
/** @brief    Status bit for TX buffer flags, TRUE -> buffer is locked */
#define FEC_TXB_LOCK_U8 (8U)
/** @brief    Status bit for TX buffer flags, TRUE -> TxConfirmation pending */
#define FEC_TXB_CONF_U8  (4U)
/** @brief    Status bit for TX buffer flags, TRUE -> buffer linked with BD */
#define FEC_TXB_LINK_U8  (2U)
/** @brief    Status bit for TX buffer flags, TRUE -> first buffer of frame */
#define FEC_TXB_FIRST_U8 (1U)

/***************************************************************************
* Invalid value 
***************************************************************************/
/* @violates @ref Eth_Fec_Reg_Sys_h_REF_1 */
#define FEC_TXFIFO_INVALID (16U)
/*==================================================================================================
                CONTROLLER OPTIONS
==================================================================================================*/
#define ETH_FEC_CONTROLLERS_NO 1U

#ifdef __cplusplus
}
#endif

#endif /*TEMPLATE_H*/
