/**
*   @file    Reg_eSys_DmaV3.h
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcl - eDMAV3 Registers and Macros Definitions.
*   @details eDMAV3 Registers and Macros Definitions.
*
*   @addtogroup DMA_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

/**
@file        Reg_eSys_DmaV3.h
*/

#ifndef REG_ESYS_DMAV3_H
#define REG_ESYS_DMAV3_H


#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, A function should be used in preference to a function-like macro where they are interchangeable.
* Function like macro are used to reduce code complexity.
*
* @section Reg_eSys_DmaV3_h_REF_1
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Macros are used only in some configurations or for future releases.
*/
/*==================================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/

#include "Reg_eSys.h"


/*==================================================================================================
*                               SOURCE FILE VERSION INFORMATION
==================================================================================================*/
/**
* @file           Reg_eSys_Dma.h
* @requirements
*/

/*==================================================================================================
*                                 GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/


/*==================================================================================================
*                                             ENUMS
==================================================================================================*/


/*==================================================================================================
*                                           CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                       DEFINES AND MACROS
==================================================================================================*/
/**
* @brief Macro to get the DMA V3 Module address by module index.
*/
#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)

#ifndef DMA_0_BASEADDR
#define DMA_0_BASEADDR (0x01UL)
#endif
#ifndef DMA_1_BASEADDR
#define DMA_1_BASEADDR (0x01UL)
#endif

/**
* @brief Macro to select Instance of DMA engine
*/
#define DMAV3_MOD_BASE_ADDR32(mIdx) \
    ((uint32)(((mIdx)>0UL) ? \
    (DMA_1_BASEADDR) : (DMA_0_BASEADDR)))
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_DEFAULT_VAL_U32               ((uint32) (0x00000000UL))
/**
* @brief Mask used to select the configurable bits of DMA v3 CSR register
*/
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CSR_MASK_U32                  (0x000003F7UL)
/**
* @brief Value used for deinitializing the eDMA3 modules
*/
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CSR_DEINIT_VAL_U32            (0x00300000UL)
/**
* @brief ERCA CSR mask
*/
#define DMAV3_CSR_ERCA_U32                  ((uint32)0x00000004UL)

#define DMAV3_CSR_ADDR32(mIdx)              ((uint32)(DMAV3_MOD_BASE_ADDR32((mIdx))))
#define DMAV3_ES_ADDR32(mIdx)               ((uint32)(DMAV3_MOD_BASE_ADDR32(mIdx)+0x00000004UL))
/** TCD address offset for the eDMA3 IP version */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_TCD_OFFSET_U32                ((uint32)(0x4020UL))
/** CH_CSR offset for the eDMA3 IP version */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_OFFSET_U32             ((uint32)(0x4000UL))
/** CH_ES offset for the eDMA3 IP version */
#define DMAV3_CH_ES_OFFSET_U32              ((uint32)(0x4004UL))
/** CH_INT offset for the eDMA3 IP version */
#define DMAV3_CH_INT_OFFSET_U32             ((uint32)(0x4008UL))
/** CH_SBR offset for the eDMA3 IP version */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_SBR_OFFSET_U32             ((uint32)(0x400CUL))
/** CH_PRI offset for the eDMA3 IP version */
#define DMAV3_CH_PRI_OFFSET_U32             ((uint32)(0x4010UL))

/** distance between CH_GRPRI registers for the eDMA3 IP version */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_GRPRI_GAP_U32              ((uint32)(0x4))

/**
* @brief Channel priority block address offset
*/
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_GRPRI_OFFSET_U32              ((uint32)(0x100UL))

/** masks used to set the CHn_CSR fields of eDMA3 instances. */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_ERQ_U32                ((uint32)0x00000001UL)
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_EARQ_U32               ((uint32)0x00000002UL)
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_EEI_U32                ((uint32)0x00000004UL)
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_DONE_U32               ((uint32)0x40000000UL)
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_ACTIVE_U32             ((uint32)0x80000000UL)

/* Gap between channels */
/*(channel)>>4U <=> channel/16 that mean: if channel > 16, the GAP will be added more 
* MCL_EDMA_TCD_GAP_GROUP_CHANNELS = (distance between channel 15 and channel 16) - MCL_EDMA_TCD_GAP_CHANNELS*/
#define DMAV3_TCD_GAP_U32(channel) \
        (uint32)((uint32)((channel & DMA_CTRL_MAX_CHANNELS_MASK_U32) * ((uint32)MCL_EDMA_TCD_GAP_CHANNELS)) + \
        (uint32)(((uint32)((channel)>>4U)) * MCL_EDMA_TCD_GAP_GROUP_CHANNELS))
/* address of eDMA3 CHnCHPRI registers */
#define DMAV3_CH_PRI(channel) \
        ((uint32)(DMAV3_MOD_BASE_CH_ADDR32((channel)) + DMAV3_CH_PRI_OFFSET_U32 + \
        (DMAV3_TCD_GAP_U32(channel))))

/* address of eDMA3 CHnCHGRPRI registers */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_GRPRI(channel) \
        ((uint32)(DMAV3_MOD_BASE_CH_ADDR32((channel)) + DMAV3_GRPRI_OFFSET_U32 + \
        (((channel) & DMA_CTRL_MAX_CHANNELS_MASK_U32) * DMAV3_CH_GRPRI_GAP_U32)))

/* address of eDMA3 CHnSBR registers */
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_SBR(channel) \
        ((uint32)(DMAV3_MOD_BASE_CH_ADDR32((channel)) + DMAV3_CH_SBR_OFFSET_U32 + \
        (DMAV3_TCD_GAP_U32(channel))))

/** masks used to unset the CHn_INT field of eDMA3 instances. */
#define DMAV3_CH_INT_U32    ((uint32)0x00000001UL)

#define DMAV3_MOD_BASE_CH_ADDR32(channel) \
    DMAV3_MOD_BASE_ADDR32(DMAV3_MOD_IDX_U32(channel))

#define DMAV3_MOD_IDX_U32(channel) \
    ((uint32)((channel)/MCL_DMA_INSTANCE_CHANNELS_NO))

 /** address of CHn_CSR registers for eDMA3 instances */
 /* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_CH_CSR_ADDR(channel) \
    ((uint32)(DMAV3_MOD_BASE_CH_ADDR32((channel)) + DMAV3_CH_CSR_OFFSET_U32 + \
    (DMAV3_TCD_GAP_U32(channel))))

 /** address of CHn_INT registers for eDMA3 instances */
#define DMAV3_CH_INT_ADDR(channel) \
    ((uint32)(DMAV3_MOD_BASE_CH_ADDR32((channel)) + DMAV3_CH_INT_OFFSET_U32 + \
    (DMAV3_TCD_GAP_U32(channel))))

  /** address of CHn_ES registers for eDMA3 instances */
#define DMAV3_CH_ES_ADDR32(channel) \
    ((uint32)(DMA_MOD_BASE_CH_ADDR32((channel)) + DMAV3_CH_ES_OFFSET_U32 + \
    (DMAV3_TCD_GAP_U32(channel))))
/**
* @{
* @brief DMA_CH_ES ERR register bit masks.
*/
#define DMAV3_CH_ES_ERR_U32           ((uint32)0x80000000UL)
/**
* @{
* @brief DMA_ES MP register bit masks.
*/
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_ES_UCE_U32              ((uint32)0x00000200UL)
/* @violates @ref Reg_eSys_DmaV3_h_REF_1 MISRA 2012 Advisory 2.5*/
#define DMAV3_ES_ECX_U32              ((uint32)0x00000100UL)

#if ((MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON) || (MCL_DMA_GET_CH_ERR_STATUS_API == STD_ON) || (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON))

#define DMAV3_ES_ERRCHN_U32           ((uint32)0x1F000000UL)
/**
* @{
* @brief DMA_ES register shift value.
*/
#define DMAV3_ES_ERRCHN_SHIFT_RIGTH_U8          ((uint8)24U)

#endif /*MCL_DMA_GET_GLOBAL_ERR_STATUS_API  */

#endif
#endif  /*MCL_ENABLE_DMA*/

#ifdef __cplusplus
}
#endif

#endif /* REG_ESYS_DMAV3_H */

/** @} */
