/**
*   @file    Mcu_PBcfg.c
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcu - Data structures for the Mcu driver.
*   @details Postbuild structure configurations for the driver initalization.
*
*   @addtogroup MCU
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : MC
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/


#ifdef __cplusplus
extern "C"
{
#endif


/**
* @page misra_violations MISRA-C:2012 violations
*
* @section Mcu_PBcfg_c_REF_1
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor
* directives or comments. AUTOSAR imposes the specification of the sections in which certain parts
* of the driver must be placed.
*
* @section Mcu_PBcfg_c_REF_2
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents
* of a header file being included more than once. This comes from the order of includes in the .c file
* and from include dependencies. As a safe approach, any file must include all its dependencies.
* Header files are already protected against double inclusions. The inclusion of Mcu_MemMap.h is as
* per AUTOSAR requirement [SWS_MemMap_00003].
*
* @section Mcu_PBcfg_c_REF_3
* Violates MISRA 2012 Advisory Rule 8.7, Functions and objects should not be defined with external
* linkage if they are referenced in only one translation unit. This violation is due to exporting
* the externally configured initialization structure required to be passed to the "Mcu_Init" function.
*
* @section Mcu_PBcfg_c_REF_4
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block scope if its identifier
* only appears in a single function. This violation is due to exporting the externally configured
* initialization structure used by the "Mcu_Init" function when (MCU_PRECOMPILE_SUPPORT == STD_ON).
*
* @section Mcu_PBcfg_c_REF_5
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void and an
* arithmetic type.
* This is a false positive error. PC-Lint is checking against a more restrictive condition
* ("pointer/non-pointer to non-pointer/pointer" vs "pointer-to-void to arithmetic type").
*
* @section Mcu_PBcfg_c_REF_6
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer to object
* and an integer type.
* The cast is used to access RAM in order to perform RAM initialization.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
* The compilers used are supporting more than 31 characters for macro identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
* The compilers used are supporting more than 31 characters for external identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space shall be distinct.
* This rule does not apply, because this case is covered by Rule 5.1 and Rule 5.4.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
* The identifier clash is between macro identifiers or external identifiers. Therefore, this rule is incorrectly
* reported by the tool.
*/

/*==================================================================================================
                                         INCLUDE FILES
 1) system and project includes
 2) needed interfaces from external units
 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Mcu.h"

#if (MCU_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
#include "Dem.h"
#endif /* (MCU_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF) */

/*==================================================================================================
                                SOURCE FILE VERSION INFORMATION
==================================================================================================*/

#define MCU_PBCFG_VENDOR_ID_C                     43
#define MCU_PBCFG_AR_RELEASE_MAJOR_VERSION_C      4
#define MCU_PBCFG_AR_RELEASE_MINOR_VERSION_C      3
#define MCU_PBCFG_AR_RELEASE_REVISION_VERSION_C   1
#define MCU_PBCFG_SW_MAJOR_VERSION_C              1
#define MCU_PBCFG_SW_MINOR_VERSION_C              0
#define MCU_PBCFG_SW_PATCH_VERSION_C              0

/*==================================================================================================
                                      FILE VERSION CHECKS
==================================================================================================*/
/* Check if current file and MCU header file are of the same vendor */
#if (MCU_PBCFG_VENDOR_ID_C != MCU_VENDOR_ID)
    #error "Mcu_PBcfg.c and Mcu.h have different vendor ids"
#endif
/* Check if current file and MCU header file are of the same Autosar version */
#if ((MCU_PBCFG_AR_RELEASE_MAJOR_VERSION_C != MCU_AR_RELEASE_MAJOR_VERSION) || \
     (MCU_PBCFG_AR_RELEASE_MINOR_VERSION_C != MCU_AR_RELEASE_MINOR_VERSION) || \
     (MCU_PBCFG_AR_RELEASE_REVISION_VERSION_C != MCU_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Mcu_PBcfg.c and Mcu.h are different"
#endif
/* Check if current file and MCU header file are of the same Software version */
#if ((MCU_PBCFG_SW_MAJOR_VERSION_C != MCU_SW_MAJOR_VERSION) || \
     (MCU_PBCFG_SW_MINOR_VERSION_C != MCU_SW_MINOR_VERSION) || \
     (MCU_PBCFG_SW_PATCH_VERSION_C != MCU_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Mcu_PBcfg.c and Mcu.h are different"
#endif

/* Check if current file and DEM header file are of the same version */
#if (MCU_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
  #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
/* Check if current file and DEM header file are of the same version */
    #if ((MCU_PBCFG_AR_RELEASE_MAJOR_VERSION_C != DEM_AR_RELEASE_MAJOR_VERSION) || \
         (MCU_PBCFG_AR_RELEASE_MINOR_VERSION_C != DEM_AR_RELEASE_MINOR_VERSION) \
        )
        #error "AutoSar Version Numbers of Mcu_PBcfg.c and Dem.h are different"
    #endif
#endif
#endif


/*==================================================================================================
                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/


/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/


/*==================================================================================================
                                       LOCAL CONSTANTS
==================================================================================================*/


/*==================================================================================================
                                       LOCAL VARIABLES
==================================================================================================*/


/*==================================================================================================
                                       GLOBAL CONSTANTS
==================================================================================================*/
#define MCU_START_SEC_CONFIG_DATA_UNSPECIFIED
/**
* @violates @ref Mcu_PBcfg_c_REF_2 Precautions shall be taken in order to prevent the contents
* of a header file being included more than once.
*/
#include "Mcu_MemMap.h"


/*==================================================================================================
                                       GLOBAL VARIABLES
==================================================================================================*/









#ifndef MCU_MAX_NORAMCONFIGS
/**
* @brief        Definition of RAM sections within the configuration structure.
* @details      Blocks of memory are initialized with a default data.
*               Configuration set by calling Mcu_InitRamSection() API.
*
*/
static CONST(Mcu_RamConfigType, MCU_CONST) Mcu_aRamConfigPB[1] =
{

    {
        /* The ID for Ram Sector configuration. */
        (Mcu_RamSectionType)0U,

        /* RAM section base address: Start of Mcu_aRamConfig[0]. */
        /** @violates @ref Mcu_PBcfg_c_REF_5 False positive error */
        /** @violates @ref Mcu_PBcfg_c_REF_6 The cast is used to access RAM in order to perform RAM initialization. */
        (uint8 (*)[1U])0x40000000U,

        /* RAM section size: Section base address (must be aligned to 4 bytes). */
        (Mcu_RamSizeType)0x00000400U,

        /* RAM default value. */
        (uint64) ( ((uint64)0xbaU << 0U) | ((uint64)0xbaU << 8U) | ((uint64)0xbaU << 16U) | ((uint64)0xbaU << 24U) | ((uint64)0xbaU << 32U) | ((uint64)0xbaU << 40U) | ((uint64)0xbaU << 48U) | ((uint64)0xbaU << 56U) ),

        /* RAM section write size (maximum allowed: 8). */
        (Mcu_RamWriteSizeType)8U

    } /* End of Mcu_aRamConfigPB[0]. */

};
#endif /* ifndef MCU_MAX_NORAMCONFIGS */




/**
* @brief        Definition of MCU mode sections in the configuration structure.
* @details      Specifies the system behaviour during the selected target mode.
*               Configuration set by calling Mcu_SetMode() API.
*/
static CONST(Mcu_ModeConfigType, MCU_CONST) Mcu_aModeConfigPB[1U] =
{

    /* Start of Mcu_aModeConfig[0]*/
    {
        /* The ID for Power Mode configuration. */
        (Mcu_ModeType)0U,
        
        /* The Power Mode name (code). */
        (MCU_RUN_MODE),
        
        /* Core 0 Reset Vector Register Configuration */
        (
            SIU_RSTVEC_RSTVEC_U32(0xfffffffcU) |
            SIU_RSTVEC_RST_DISABLE_U32 |
            SIU_RSTVEC_VLE_BOOK_E_U32
        ),
        
        /* Core 1 Reset Vector Register Configuration */
        (
            SIU_RSTVEC_RSTVEC_U32(0xfffffffcU) |
            SIU_RSTVEC_RST_DISABLE_U32 |
            SIU_RSTVEC_VLE_BOOK_E_U32
        ),    
        
        
        /* SIU_HLT1 register value */
        (
                            
            SIU_HLT1_CORE0_HALT_DIS_U32                                             | 
            SIU_HLT1_CORE1_HALT_DIS_U32                                             | 
            SIU_HLT1_CSE_HALT_DIS_U32                                             | 
            SIU_HLT1_DECFIL_HALT_DIS_U32                                             | 
            SIU_HLT1_DSPIA_HALT_DIS_U32                                             | 
            SIU_HLT1_DSPIB_HALT_DIS_U32                                             | 
            SIU_HLT1_DSPIC_HALT_DIS_U32                                             | 
            SIU_HLT1_DSPID_HALT_DIS_U32                                             | 
            SIU_HLT1_DSPIE_HALT_DIS_U32                                             | 
            SIU_HLT1_EBI_HALT_DIS_U32                                             | 
            SIU_HLT1_EMIOS0_HALT_DIS_U32                                             | 
            SIU_HLT1_EMIOS1_HALT_DIS_U32                                             | 
            SIU_HLT1_EQADCA_HALT_DIS_U32                                             | 
            SIU_HLT1_EQADCB_HALT_DIS_U32                                             | 
            SIU_HLT1_ESCIA_HALT_DIS_U32                                             | 
            SIU_HLT1_ESCIB_HALT_DIS_U32                                             | 
            SIU_HLT1_ESCIC_HALT_DIS_U32                                             | 
            SIU_HLT1_ESCID_HALT_DIS_U32                                             | 
            SIU_HLT1_ESCIE_HALT_DIS_U32                                             | 
            SIU_HLT1_ESCIF_HALT_DIS_U32                                             | 
            SIU_HLT1_ETPUA_HALT_DIS_U32                                             | 
            SIU_HLT1_ETPUC_HALT_DIS_U32                                             | 
            SIU_HLT1_FLEXCANA_HALT_DIS_U32                                             | 
            SIU_HLT1_FLEXCANB_HALT_DIS_U32                                             | 
            SIU_HLT1_FLEXCANC_HALT_DIS_U32                                             | 
            SIU_HLT1_FLEXCAND_HALT_DIS_U32                                             | 
            SIU_HLT1_NPC_HALT_DIS_U32                                             | 
            SIU_HLT1_PIT_HALT_DIS_U32                                    ),
        
        
        /* SIU_HLT2 register value */
        (
                            
            SIU_HLT2_CRC_HALT_DIS_U32
                                             | 
            SIU_HLT2_FEC_HALT_DIS_U32
                                             | 
            SIU_HLT2_MCANA_HALT_DIS_U32
                                             | 
            SIU_HLT2_MCANB_HALT_DIS_U32
                                             | 
            SIU_HLT2_PSI5A_HALT_DIS_U32
                                             | 
            SIU_HLT2_PSI5B_HALT_DIS_U32
                                             | 
            SIU_HLT2_SDA_HALT_DIS_U32
                                             | 
            SIU_HLT2_SDB_HALT_DIS_U32
                                             | 
            SIU_HLT2_SDC_HALT_DIS_U32
                                             | 
            SIU_HLT2_SDD_HALT_DIS_U32
                                             | 
            SIU_HLT2_SIPI_HALT_DIS_U32
                                             | 
            SIU_HLT2_SRX0_HALT_DIS_U32
                                             | 
            SIU_HLT2_SRX1_HALT_DIS_U32
                                             | 
            SIU_HLT2_STCU_HALT_DIS_U32
                                    )
    }/* end of Mcu_aModeConfigPB[0]. */

};




#if (MCU_INIT_CLOCK == STD_ON)
#if (MCU_DISABLE_FLASH_CONFIG == STD_OFF)
/**
* @brief        Timing configuration for FLASH hw IP.
* @details      Set the Pipeline/Write/Read wait states for FLASH controller.
*               Configuration set by calling Mcu_InitClock API.
*/
static CONST( Mcu_FLASH_ClockConfigType, MCU_CONST) FLASH_Clock_ConfigPB_0 =
{
    /* Flash Controller timing settings.
       PFCR1 configuration register: Address Pipelining Control & Read Wait State Control. */
    (
        MCU_FLASH_ADDR_PIPELINE_WS_U32(1U) |
        MCU_FLASH_READ_WS_U32(3U)
    )
};
#endif /* (MCU_DISABLE_FLASH_CONFIG == STD_OFF) */
#endif /* (MCU_INIT_CLOCK == STD_ON) */
            



#if (MCU_INIT_CLOCK == STD_ON)
static CONST( Mcu_SIU_RegisterConfigType, MCU_CONST) aPcsClock_ConfigPB_0[MCU_NUMBER_OF_PCS_REGS] =
{

    /* PCS Divider Change Register 1. */
    {
        PCS_DIVC1_ADDR32,
        PCS_DIVC_U32
        (
            PCS_DIVC_INIT_U32((uint32)0x000003e7U) |
            PCS_DIVC_RATE_U32((uint32)0x00000000U)
        )
    },
    /* PCS Divider Start Register 1. */
    {
        PCS_DIVS1_ADDR32,
        PCS_DIVS_U32((uint32)0x000003e7U)
    },
    /* PCS Divider End Register 1. */
    {
        PCS_DIVE1_ADDR32,
        PCS_DIVE_U32((uint32)0x000003e7U)
    },

    /* PCS Divider Change Register 2. */
    {
        PCS_DIVC2_ADDR32,
        PCS_DIVC_U32
        (
            PCS_DIVC_INIT_U32((uint32)0x000003e7U) |
            PCS_DIVC_RATE_U32((uint32)0x00000000U)
        )
    },
    /* PCS Divider Start Register 2. */
    {
        PCS_DIVS2_ADDR32,
        PCS_DIVS_U32((uint32)0x000003e7U)
    },
    /* PCS Divider End Register 2. */
    {
        PCS_DIVE2_ADDR32,
        PCS_DIVE_U32((uint32)0x000003e7U)
    },

    /* PCS Divider Change Register 3. */
    {
        PCS_DIVC3_ADDR32,
        PCS_DIVC_U32
        (
            PCS_DIVC_INIT_U32((uint32)0x000003e7U) |
            PCS_DIVC_RATE_U32((uint32)0x00000000U)
        )
    },
    /* PCS Divider Start Register 3. */
    {
        PCS_DIVS3_ADDR32,
        PCS_DIVS_U32((uint32)0x000003e7U)
    },
    /* PCS Divider End Register 3. */
    {
        PCS_DIVE3_ADDR32,
        PCS_DIVE_U32((uint32)0x000003e7U)
    }

};
#endif /* (MCU_INIT_CLOCK == STD_ON) */




#if (MCU_INIT_CLOCK == STD_ON)
static CONST( Mcu_SIU_RegisterConfigType, MCU_CONST) SIU_aAuxClock_ConfigPB_0[4] =
{

        /* External Clock Register Configuration. */
    {
        SIU_ECCR_ADDR32,
        (
            SIU_ECCR_ENGDIV_U32((uint32)(66U)) |
            SIU_ECCR_ECCS_SOURCE_PLAT_CLK_U32 |
            SIU_ECCR_EBTS_ZERO_HOLD_TIMES_U32 |
            SIU_ECCR_EBDF_U32((uint32)(3U))
        )
    }

    ,    /* Sigma Delta Clock Config Register. */
    {
        SIU_SDCLKCFG_ADDR32,
        SIU_SDCLKCFG_SDDIV_U32((uint32)(1U))
    }

    ,    /* LFAST Clock Config Register. */
    {
        SIU_LFCLKCFG_ADDR32,
        (
                                                SIU_LFCLKSEL_SOURCE_PER_CLK_UNDIV_U32 |
        SIU_LFCLKCFG_LFDDIV_U32((uint32)(1U))
        )
    }

    ,    /* PSI5 Clock Config Register. */
    {
        SIU_PSCLKCFG_ADDR32,
        (
            SIU_PSCLKCFG_PSDIV_U32((uint32)(1U)) |
            SIU_PSCLKCFG_PSDIV1M_U32((uint32)(1U))
        )
    }

};
#endif /* (MCU_INIT_CLOCK == STD_ON) */




#if (MCU_INIT_CLOCK == STD_ON)
/**
* @brief            SIU clock configuration.
* @details          This structure contains information for XOSC, PLL, Output Clocks, CMUs
*
*/
static CONST( Mcu_SIU_ClockConfigType, MCU_CONST) SIU_Clock_ConfigPB_0 =
{
    /* system clock configuration */
        (
                                                    SIU_SYSDIV_SYSCLKSEL_SOURCE_PLL1_PHI_U32 |
        SIU_SYSDIV_SYSCLKDIV_U32((uint32)(4U)) |
        SIU_SYSDIV_PLL0SEL_SOURCE_XOSC_U32 |
        SIU_SYSDIV_PLL1SEL_SOURCE_PLL0_PHI1_U32 |
        SIU_SYSDIV_FMPERDIV_U32((uint32)(0U)) |
        SIU_SYSDIV_PERCLKSEL_SOURCE_PLL0_PHI_U32 |
        SIU_SYSDIV_PERDIV_U32((uint32)(0U)) |
        SIU_SYSDIV_ETPUDIV_DIVIDE_BY_2_U32 |
        SIU_SYSDIV_MCANSEL_SOURCE_XOSC_U32 |
        SIU_PCSEN_PCS_ENABLED_U32
    )
    ,
    
    /* Progressive Clock Switching (CGM_PCS_SDUR[SDUR]) */
    PCS_SDUR_U32((uint32)0x00U),

    /* number of pcs registers unde mcu control */
    MCU_NUMBER_OF_PCS_REGS,

    /* pcs registers */
    &aPcsClock_ConfigPB_0,

    /* number of configurable aux clock regs */
    ((uint8)4U),

    /* auxiliary clock dividers */
     &SIU_aAuxClock_ConfigPB_0
    

};
#endif /* (MCU_INIT_CLOCK == STD_ON) */
            



#if (MCU_INIT_CLOCK == STD_ON)
/**
* @brief            PLLDIG Registers configuration.
* @details          This structure contains configuration for PLLDIG Registers.
*
*/
static CONST( Mcu_PLLDIG_RegisterConfigType, MCU_CONST) Mcu_aPLLDIG_Registers_Config_PB_0[8] =
{
    
    /* turn off PLL0 */
    {
        PLLDIG_PLL0CR_ADDR32,
        MCU_PLLDIG_PLL0CR_U32
        (
            PLLDIG_PLL0CR_CLKCFG_BO_U32
        )
    },
    /* PLL0 dividers */
    {
        PLLDIG_PLL0DV_ADDR32,
        MCU_PLLDIG_PLL0DV_U32
        (
            MCU_PLLDIG_PLL0DV_RFDPHI1_U32( (uint32)12U ) |
            MCU_PLLDIG_PLL0DV_RFDPHI_U32( (uint32)4U ) |
            MCU_PLLDIG_PLL0DV_PREDIV_U32( (uint32)5U ) |
            MCU_PLLDIG_PLL0DV_MFD_U32( (uint32)72U )
        )
    },
    /* PLL0 configuration */
    {
        PLLDIG_PLL0CR_ADDR32,
        MCU_PLLDIG_PLL0CR_U32
        (
            PLLDIG_PLL0CR_CLKCFG_NR_U32 |
            MCU_PLLDIG_PLL0CR_LOLIE_DIS_U32
        )
    },
    /* turn off PLL1 */
    {
        PLLDIG_PLL1CR_ADDR32,
        MCU_PLLDIG_PLL1CR_U32
        (
            PLLDIG_PLL1CR_CLKCFG_BO_U32
        )
    },
    /* PLL1 dividers */
    {
        PLLDIG_PLL1DV_ADDR32,
        MCU_PLLDIG_PLL1DV_U32
        (
            MCU_PLLDIG_PLL1DV_RFDPHI_U32( (uint32)2U ) |
            MCU_PLLDIG_PLL1DV_MFD_U32( (uint32)22U )
        )
    },
    /* PLL1 frequency modulation */
    {
        PLLDIG_PLL1FM_ADDR32,
        MCU_PLLDIG_PLL1FM_U32( MCU_PLLDIG_PLL1FM_MODEN_DIS_U32 )
    },
    /* PLL1 fractional divider */
    {
        PLLDIG_PLL1FD_ADDR32,
        MCU_PLLDIG_PLL1FD_U32( MCU_PLLDIG_PLL1FD_FDEN_DIS_U32 )
    },
    /* PLL1 configuration */
    {
        PLLDIG_PLL1CR_ADDR32,
        MCU_PLLDIG_PLL1CR_U32
        (
            PLLDIG_PLL1CR_CLKCFG_NR_U32 |
            MCU_PLLDIG_PLL1CR_LOLIE_DIS_U32
        )
    }
};
#endif /* (MCU_INIT_CLOCK == STD_ON) */
            



#if (MCU_INIT_CLOCK == STD_ON)
/**
* @brief            PLLDIG clock configuration.
* @details          This structure contains information for PLLDIG PLL0 and FMPLL1.
*
*/
static CONST( Mcu_PLLDIG_ConfigType, MCU_CONST) MC_PLLDIG_ClockConfigPB_0 =
{
    /* number of pll regs under mcu control */
    0x08U,
    /* configuration for PLLDIG registers */
    &Mcu_aPLLDIG_Registers_Config_PB_0
};
#endif /* (MCU_INIT_CLOCK == STD_ON) */
            




#if (MCU_INIT_CLOCK == STD_ON)
#if (MCU_EMIOS_SUPPORT == STD_ON)
/**
* @brief            eMios Module Configuration.
* @details          This structure contains information for eMios0 and eMios1.
*
*/
static CONST(Mcu_eMios_ConfigType, MCU_CONST) EMIOS_Module_ConfigPB_0 = 
{
    {
        /* eMios0 configuration */
        EMIOS_MCR_U32
        (
            EMIOS_MCR_MDIS_DIS_U32 |
            EMIOS_MCR_FRZ_ENA_U32 |
            EMIOS_MCR_GTBE_ENA_U32 |
            EMIOS_MCR_ETB_DIS_U32 |
            EMIOS_MCR_GPREN_ENA_U32 |
            EMIOS_MCR_SRV_U32((uint32)0U)|
            EMIOS_MCR_GPRE_U32((uint32)71U)
        ),
        /* eMios1 configuration */
        EMIOS_MCR_U32
        (
            EMIOS_MCR_MDIS_DIS_U32 |
            EMIOS_MCR_FRZ_ENA_U32 |
            EMIOS_MCR_GTBE_ENA_U32 |
            EMIOS_MCR_ETB_DIS_U32 |
            EMIOS_MCR_GPREN_ENA_U32 |
            EMIOS_MCR_SRV_U32((uint32)0U)|
            EMIOS_MCR_GPRE_U32((uint32)8U)
        )
    }
};
#endif /* (MCU_EMIOS_SUPPORT == STD_ON) */
#endif /* (MCU_INIT_CLOCK == STD_ON) */




#if (MCU_INIT_CLOCK == STD_ON)
/**
* @brief            CMU configuration.
* @details          This structure contains information for CMU[n].
*                   The number of CMU's is defined in the resource files,
*
*/
static CONST( Mcu_CMU_ConfigType, MCU_CONST) CMU_ConfigPB_0 =
{
#if (defined(MCU_CMU_RCDIV_INDEPEND) && (MCU_CMU_RCDIV_INDEPEND == STD_ON))
    {

        
        /* CMU_x_CSR[RCDIV] exist on CMU_0_XOSC_AND_PLL_PHI0_CLK */
        (boolean)TRUE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_1_CORE_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_2_PLAT_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_3_FM_PER_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_4_ETPU_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_5_PER_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_6_SD_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_7_PSI5_RX_CLK */
        (boolean)FALSE

        ,
        /* CMU_x_CSR[RCDIV] exist on CMU_8_PSI5_1US_CLK */
        (boolean)FALSE

    },
#endif
    {

        
        /* CSR for CMU_0_XOSC_AND_PLL_PHI0_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            | CMU_CSR_RCDIV_8_U32
        )

        ,
        /* CSR for CMU_1_CORE_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_2_PLAT_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_3_FM_PER_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_4_ETPU_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_5_PER_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_6_SD_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_7_PSI5_RX_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

        ,
        /* CSR for CMU_8_PSI5_1US_CLK */
        CMU_CSR_U32
        (
            CMU_CSR_CMU_DIS_U32
            
        )

    },
    {

        
        /* HFREFR for CMU_0_XOSC_AND_PLL_PHI0_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_1_CORE_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_2_PLAT_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_3_FM_PER_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_4_ETPU_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_5_PER_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_6_SD_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_7_PSI5_RX_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

        ,
        /* HFREFR for CMU_8_PSI5_1US_CLK */
        CMU_HFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_HFREFR_RESET_VALUE_U32
        )

    },
    {

        
        /* LFREFR for CMU_0_XOSC_AND_PLL_PHI0_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_1_CORE_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_2_PLAT_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_3_FM_PER_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_4_ETPU_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_5_PER_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_6_SD_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_7_PSI5_RX_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

        ,
        /* LFREFR for CMU_8_PSI5_1US_CLK */
        CMU_LFREFR_VALUE_U32
        (
            (uint32)MCU_CMU_LREF_RESET_VALUE_U32
        )

    }
};
#endif /* (MCU_INIT_CLOCK == STD_ON) */




#if (MCU_INIT_CLOCK == STD_ON)
#if (MCU_DISABLE_RAM_WS_CONFIG == STD_OFF)
/**
* @brief        Timing configuration for SRAMC hw IP.
* @details      Set the Read wait states for RAM.
*               Configuration set by calling Mcu_InitClock API.
*/
static CONST( Mcu_PRAM_ClockConfigType, MCU_CONST) SRAMC_ClockConfigPB_0 =
{
    /* PRAMC_0 Controller timing settings. PRCR1 configuration register. */
    PRAMC_PRCR1_VALUE_U32
    (
        PRAMC_PRCR1_P0_BO_ENA_U32 |
        PRAMC_PRCR1_FT_ENA_U32
    ),
    /* PRAMC_1 Controller timing settings. PRCR1 configuration register. */
    PRAMC_PRCR1_VALUE_U32
    (
        PRAMC_PRCR1_P0_BO_ENA_U32 |
        PRAMC_PRCR1_FT_ENA_U32
    )
};
#endif /* (MCU_DISABLE_RAM_WS_CONFIG == STD_OFF) */
#endif /* (MCU_INIT_CLOCK == STD_ON) */
            



#if (MCU_INIT_CLOCK == STD_ON)
/**
* @brief          Initialization clock data.
* @details        Static configuration realized by calling Mcu_InitClock() API.
*
*/
static CONST( Mcu_ClockConfigType, MCU_CONST) Mcu_aClockConfigPB[1] =
{
    
    /* Start of Mcu_ClockConfig[0]. */
    {
            
        /* ID Clock Configuration. */
        (uint8)0U,

        /* Globally enable/disable SCM, loss of clock and loss of lock notification. */
        (MCU_CLK_NOTIF_DIS),
        
        /* SIU IP Clock settings. */
        &SIU_Clock_ConfigPB_0,

        /* PLLDIG IP Clock settings. */
        &MC_PLLDIG_ClockConfigPB_0,
        
#if (MCU_EMIOS_SUPPORT == STD_ON)
        /* eMios Module settings. */
        &EMIOS_Module_ConfigPB_0,
#endif
        /* CMU IP Clock settings. */
        &CMU_ConfigPB_0,

#if (MCU_DISABLE_RAM_WS_CONFIG == STD_OFF)
        /* SRAMC IP Clock settings. */
        &SRAMC_ClockConfigPB_0,
#endif /* (MCU_DISABLE_RAM_WS_CONFIG == STD_OFF) */

#if (MCU_DISABLE_FLASH_CONFIG == STD_OFF)
        /* FLASH IP Clock settings. */
        &FLASH_Clock_ConfigPB_0,
#endif /* (MCU_DISABLE_FLASH_CONFIG == STD_OFF) */

    } /* end of Mcu_ClockConfig[0] */
            
};
#endif /* (MCU_INIT_CLOCK == STD_ON) */
        



/**
* @brief          Initialization data for MC_RGM hw IP.
* @details        Static configuration realized at statup by calling Mcu_Init() API.
*
*/
static CONST(Mcu_SIU_ResetConfigType, MCU_CONST) SIU_ResetConfigPB =
{
#if (MCU_PERFORM_RESET_API == STD_ON)
    /* Reset type: software system vs software external. */
    (MCU_SOFT_SYSTEM_RESET),
#endif /* (MCU_PERFORM_RESET_API == STD_ON) */

    /* Reset escalation threshold */
    SIU_RCR_RET_U32((uint32)(8U))
};




#if (MCU_DISABLE_FLASH_CONFIG == STD_OFF)
/**
* @brief            Platform FLASH hw IP configuration.
* @details          Configure prefetch mechanism, buffers, access protection.
*                   Configuration set by calling Mcu_Init API.
*/
static CONST( Mcu_FLASH_ConfigType, MCU_CONST) FLASH_ConfigPB =
{
    /* Platform Flash Configuration Register 1 (PFCR1). */
    MCU_FLASH_PFCR1_U32
    (
        MCU_FLASH_P0_MASTER15_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER14_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER13_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER12_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER11_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER10_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER9_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER8_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER7_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER6_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER5_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER4_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER3_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER2_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER1_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_MASTER0_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_DATA_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_INSTR_PREFETCH_DIS_U32 |
        MCU_FLASH_P0_PFLIM_U32( (uint32)0U ) |
        MCU_FLASH_P0_BUFFER_EN_U32
    ),

    /* Platform Flash Configuration Register 2 (PFCR2). */
    MCU_FLASH_PFCR2_U32
    (
        MCU_FLASH_P1_MASTER15_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER14_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER13_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER12_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER11_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER10_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER9_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER8_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER7_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER6_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER5_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER4_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER3_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER2_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER1_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_MASTER0_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_DATA_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_INSTR_PREFETCH_DIS_U32 |
        MCU_FLASH_P1_PFLIM_U32( (uint32)0U ) |
        MCU_FLASH_P1_BUFFER_EN_U32
    ),

    /* Platform Flash Configuration Register 3 (PFCR3). */
    MCU_FLASH_PFCR3_U32
    (
        MCU_FLASH_BFEN_LOCK_U32 |
        MCU_FLASH_P0_WCFG_U32( (uint32)0U ) |
        MCU_FLASH_P1_WCFG_U32( (uint32)0U ) |
        MCU_FLASH_ARBM_WCFG_U32( (uint32)0U ) |
        MCU_FLASH_DERR_SUP_DIS_U32
    ),

    /* Platform Flash Access Protection Register (PFAPR). */
    MCU_FLASH_PFAPR_U32
    (
        MCU_FLASH_M0AP_U32( (uint32)3U ) |
        MCU_FLASH_M1AP_U32( (uint32)3U ) |
        MCU_FLASH_M2AP_U32( (uint32)3U ) |
        MCU_FLASH_M3AP_U32( (uint32)3U ) |
        MCU_FLASH_M4AP_U32( (uint32)3U ) |
        MCU_FLASH_M5AP_U32( (uint32)3U ) |
        MCU_FLASH_M6AP_U32( (uint32)3U ) |
        MCU_FLASH_M7AP_U32( (uint32)3U ) |
        MCU_FLASH_M8AP_U32( (uint32)3U ) |
        MCU_FLASH_M9AP_U32( (uint32)3U ) |
        MCU_FLASH_M10AP_U32( (uint32)3U ) |
        MCU_FLASH_M11AP_U32( (uint32)3U ) |
        MCU_FLASH_M12AP_U32( (uint32)3U ) |
        MCU_FLASH_M13AP_U32( (uint32)3U ) |
        MCU_FLASH_M14AP_U32( (uint32)3U ) |
        MCU_FLASH_M15AP_U32( (uint32)3U )
    )
};
#endif /* (MCU_DISABLE_FLASH_CONFIG == STD_OFF) */
        



/**
* @brief          Initialization data for PMC hw IP.
* @details        Static configuration realized at statup by calling Mcu_Init() API.
*
*/
static CONST( Mcu_PMC_ConfigType, MCU_CONST) PMC_Config =
{
    /* Reset event interrupt enable register. PMC_TS_IER register. */
    PMC_TS_IER_CONFIG_U32
    (
        PMC_TS_IER_TS1_2IE_DIS_U32 |
        PMC_TS_IER_TS1_0IE_DIS_U32 |
        PMC_TS_IER_TS0_2IE_DIS_U32 |
        PMC_TS_IER_TS0_0IE_DIS_U32
    ),

    /* Temperature reset event enable register. PMC_REE_TD register. */
    PMC_REE_TD_CONFIG_U32
    (
        PMC_REE_TD_TEMP1_2_ENA_U32 |
        PMC_REE_TD_TEMP1_0_ENA_U32 |
        PMC_REE_TD_TEMP0_2_ENA_U32 |
        PMC_REE_TD_TEMP0_0_ENA_U32
    ),

    /* Temperature reset event selection register. PMC_RES_TD register. */
    PMC_RES_TD_CONFIG_U32
    (
        PMC_RES_TD_TEMP1_2_POR_GENERATED_U32 |
        PMC_RES_TD_TEMP1_0_POR_GENERATED_U32 |
        PMC_RES_TD_TEMP0_2_POR_GENERATED_U32 |
        PMC_RES_TD_TEMP0_0_POR_GENERATED_U32
    ),

    /* Temperature detector configuration register. PMC_CTL_TD register. */
    PMC_CTL_TD_CONFIG_U32
    (
        PMC_CTL_TD_TS1_ENA_U32 |
        PMC_CTL_TD_TS0_ENA_U32
    ),

     /* LVD/HVD Interrupt Enable Control Register. PMC_LVD_HVD_INTR_ENB register. */
     PMC_LVD_HVD_INTR_ENB_U32
     (
        PMC_HVD_FLASH_INT_DISABLED_U32 |
        PMC_HVD_HV_INT_DISABLED_U32 |
        PMC_HVD_CORE_INT_DISABLED_U32 |
        PMC_LVD_CORE_COLD_INT_DISABLED_U32
    ),
    
     /* ADC Channel Select Register. PMC_ADC_CS register. */
     PMC_ADC_CS_ADC_CHANNEL_OFF_U32,
     
     /* Reset Event Enable Register. PMC_REE register. */
     PMC_REE_U32
     (
        PMC_HVD_FLASH_RESET_DISABLED_U32 |
        PMC_HVD_HV_RESET_DISABLED_U32 |
        PMC_HVD_CORE_RESET_DISABLED_U32 |
        PMC_LVD_CORE_COLD_RESET_DISABLED_U32
     )
};
        



/**
* @brief          Initialization data for SSCM hw IP.
* @details        Static configuration realized at statup by calling Mcu_Init() API.
*
*/
static CONST( Mcu_SSCM_ConfigType, MCU_CONST) SSCM_ConfigPB =
{
    /* SSCM configuration */
    SSCM_ERROR_U16(
        SSCM_ERROR_PAE_ENABLE_U16
    )

};




/**
* @brief          Initialization data for different hw IPs.
* @details        Static configuration realized at statup by calling Mcu_Init() API.
*
*/
static CONST( Mcu_HwIPsConfigType, MCU_CONST) Mcu_HwIPs_ConfigPB =
{
    /* Configuration for SIU Reset. */
    &SIU_ResetConfigPB,

    /* Configuration for PMC (Power Management Control) hardware IP. */
    &PMC_Config,

#if (MCU_DISABLE_FLASH_CONFIG == STD_OFF)
    /* Configuration for FLASH (Flash Memory) hardware IP. */
    &FLASH_ConfigPB,
#endif

    /* Configuration for SSCM hardware IP. */
    &SSCM_ConfigPB
};




/**
* @brief          Initialization data for the MCU driver.
* @details        A pointer to such a structure is provided to the MCU initialization routines for configuration.
*
*/

/**
* @violates @ref Mcu_PBcfg_c_REF_3 Functions and objects should not be defined with external
* linkage if they are referenced in only one translation unit.
*/
CONST(Mcu_ConfigType, MCU_CONST) McuModuleConfiguration =
{
#if (MCU_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
    /* Pointer to DEM error reporting configurations. */
    &Mcu_Dem_Config,
#endif

    /* Number of RAM Sections configurations. */
    (Mcu_RamSectionType)1U,

    /* Number of Power Modes configurations. */
    (Mcu_ModeType)1U,

#if (MCU_INIT_CLOCK == STD_ON)
    /* Number of Clock Setting configurations. */
    (Mcu_ClockType)1U,
#endif /* (MCU_INIT_CLOCK == STD_ON) */

    /* Pointer to RAM Section configurations. */
    &Mcu_aRamConfigPB,

    /* Pointer to Power Mode configurations. */
    &Mcu_aModeConfigPB,

#if (MCU_INIT_CLOCK == STD_ON)
    /* Pointer to Clock configurations. */
    &Mcu_aClockConfigPB,

#endif /* (MCU_INIT_CLOCK == STD_ON) */

    /* Pointer to Low Level Mcu driver configuration. */
    &Mcu_HwIPs_ConfigPB
};





#define MCU_STOP_SEC_CONFIG_DATA_UNSPECIFIED
/**
* @violates @ref Mcu_PBcfg_c_REF_1 #include directives should only be preceded by preprocessor
* directives or comments.
*
* @violates @ref Mcu_PBcfg_c_REF_2 Precautions shall be taken in order to prevent the contents
* of a header file being included more than once.
*/
#include "Mcu_MemMap.h"


/*==================================================================================================
                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/


/*==================================================================================================
                                       LOCAL FUNCTIONS
==================================================================================================*/


/*==================================================================================================
                                       GLOBAL FUNCTIONS
==================================================================================================*/

#ifdef __cplusplus
}
#endif

/** @} */

