/**
*   @file    Can_FlexCan.c
*   @version 1.0.0
*
*   @brief   AUTOSAR Can_43_FLEXCAN - LLD module implementation.
*   @details Low Level Driver implementation.
*
*   @addtogroup CAN_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : FLEXCAN
*   Dependencies         : 
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/


#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
* 
* @section [global]
*          Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
*          The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space shall be distinct.
*          The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
*          The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*          Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
*          The used compilers use more than 31 chars for identifiers.
* 
* @section Can_Flexcan_c_REF_1
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents 
* of a header file being included more than once
* This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement [SWS_MemMap_00003].)
*
* @section Can_Flexcan_c_REF_2
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor 
* directives or comments.
* <MA>_MemMap.h is included after each section define in order to set the current memory section as defined by AUTOSAR
*
* @section Can_Flexcan_c_REF_3
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer to object
* and an integer type.
* The cast is used to access memory mapped registers.
*
* @section Can_Flexcan_c_REF_4
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void and an arithmetic type.
* This macro computes the address of any register by using the hardware offset of the controller. The address calculated
* as an unsigned int is passed to a macro for initializing the pointer with that address  
*
* @section Can_Flexcan_c_REF_5
* Violates MISRA 2012 Required Rule 10.8, The value of a composite expression shall not be cast to a different essential 
* type category or a wider essential type.
* This violation is due to the complex expression (macro) is given as parameter is not evaluated at preprocessing step.
*
* @section Can_Flexcan_c_REF_6
* Violates MISRA 2012 Advisory Rule 8.7, Function and objects should not be defined with external linkage if they 
* are referenced in only one translation unit.
* These objects are used depending on user configuration.
* 
* @section Can_Flexcan_c_REF_7
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block scope if its identifier only appears
* in a single function.
*
* @section Can_Flexcan_c_REF_8
* Violates MISRA 2012 Required Rule 18.1, A pointer resulting from arithmetic on a pointer operand shall address
* an element of the same array as that pointer operand.
*
* @section Can_Flexcan_c_REF_9
* Violates MISRA 2012 Required Rule 14.3, Controlling expressions shall not be invariant.
*
* @section Can_Flexcan_c_REF_10
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Macro are required by ASR even they are not use in MCAL layer
*
* @section Can_Flexcan_c_REF_11
* Violates MISRA 2012 Required Rule 18.1, A pointer resulting from arithmetic on a pointer operand shall address
* an element of the same array as that pointer operand
* This violation is not fixed since it was prevented by checking condition.
*/

/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Can_43_FLEXCAN.h"
#include "CanIf_Cbk.h"
#include "Can_FlexCan.h"

#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
  #include "Det.h"
#endif
#ifdef CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT
#if CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT == STD_ON
  #ifndef USER_MODE_REG_PROT_ENABLED
     #define USER_MODE_REG_PROT_ENABLED   (STD_ON)
  #endif
  #include "RegLockMacros.h"
#endif
#endif

#include "SchM_Can_43_FLEXCAN.h"
#include "Mcal.h"
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    #include "Os.h"
#endif

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/

/**
* @file           Can_FlexCan.c
*/
#define CAN_FLEXCAN_VENDOR_ID_C                    43
/* @violates @ref Can_Flexcan_c_REF_10 MISRA 2012 Advisory Rule 2.5 */
#define CAN_FLEXCAN_MODULE_ID_C                    80
#define CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C     4
#define CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C     3
#define CAN_FLEXCAN_AR_RELEASE_REVISION_VERSION_C  1
#define CAN_FLEXCAN_SW_MAJOR_VERSION_C             1
#define CAN_FLEXCAN_SW_MINOR_VERSION_C             0
#define CAN_FLEXCAN_SW_PATCH_VERSION_C             0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/

/* Check if current file and CAN header file are of the same vendor */
#if (CAN_FLEXCAN_VENDOR_ID_C != CAN_FLEXCAN_VENDOR_ID_H)
    #error "Can_FlexCan.c and Can_FlexCan.h have different vendor ids"
#endif

/* Check if current file and CAN header file are of the same Autosar version */
#if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C    != CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_H) || \
     (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C    != CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_H) || \
     (CAN_FLEXCAN_AR_RELEASE_REVISION_VERSION_C != CAN_FLEXCAN_AR_RELEASE_REVISION_VERSION_H))
    #error "AutoSar Version Numbers of Can_FlexCan.c and Can_FlexCan.h are different"
#endif
/* Check if current file and CAN header file are of the same Software version */
#if ((CAN_FLEXCAN_SW_MAJOR_VERSION_C != CAN_FLEXCAN_SW_MAJOR_VERSION_H) || \
     (CAN_FLEXCAN_SW_MINOR_VERSION_C != CAN_FLEXCAN_SW_MINOR_VERSION_H) || \
     (CAN_FLEXCAN_SW_PATCH_VERSION_C != CAN_FLEXCAN_SW_PATCH_VERSION_H))
    #error "Software Version Numbers of Can_FlexCan.c and Can_FlexCan.h are different"
#endif


/* Check if current file and Can_43_FLEXCAN header file are of the same vendor */
#if (CAN_FLEXCAN_VENDOR_ID_C != CAN_43_FLEXCAN_VENDOR_ID)
    #error "Can_FlexCan.c and Can_43_FLEXCAN.h have different vendor ids"
#endif
/* Check if current file and Can_43_FLEXCAN header file are of the same Autosar version */
#if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C    != CAN_43_FLEXCAN_AR_RELEASE_MAJOR_VERSION) || \
     (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C    != CAN_43_FLEXCAN_AR_RELEASE_MINOR_VERSION) || \
     (CAN_FLEXCAN_AR_RELEASE_REVISION_VERSION_C != CAN_43_FLEXCAN_AR_RELEASE_REVISION_VERSION))
    #error "AutoSar Version Numbers of Can_FlexCan.c and Can_43_FLEXCAN.h are different"
#endif
/* Check if current file and Can_43_FLEXCAN header file are of the same Software version */
#if ((CAN_FLEXCAN_SW_MAJOR_VERSION_C != CAN_43_FLEXCAN_SW_MAJOR_VERSION) || \
     (CAN_FLEXCAN_SW_MINOR_VERSION_C != CAN_43_FLEXCAN_SW_MINOR_VERSION) || \
     (CAN_FLEXCAN_SW_PATCH_VERSION_C != CAN_43_FLEXCAN_SW_PATCH_VERSION))
    #error "Software Version Numbers of Can_FlexCan.c and Can_43_FLEXCAN.h are different"
#endif

#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if current file and CANIF_CBK header file are of the same version */
    #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
        #if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C != CANIF_CBK_AR_RELEASE_MAJOR_VERSION) || \
             (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C != CANIF_CBK_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Can_FlexCan.c and CanIf_Cbk.h are different"
        #endif
    #endif
    
    /* Check if current file and DET header file are of the same version */
    #if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
        #if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C != DET_AR_RELEASE_MAJOR_VERSION) || \
             (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C != DET_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Can_FlexCan.c and Det.h are different"
        #endif
    #endif
    
    /* Check if current file and Mcal.h file are of the same Software version */
    #if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
        (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Can_FlexCan.c and Mcal.h are different"
    #endif
    
    #ifdef CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT
        #if (STD_ON == CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT)
            /* Check if current file and StdRegMacros.h file are of the same Software version */
            #if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
                (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
                #error "AutoSar Version Numbers of Can_FlexCan.c and StdRegMacros.h are different"
            #endif
        #endif
    #endif
    
    /* Check if current file and Os.h file are of the same Software version */
    #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        #if ((CAN_FLEXCAN_AR_RELEASE_MAJOR_VERSION_C != OS_AR_RELEASE_MAJOR_VERSION) || \
            (CAN_FLEXCAN_AR_RELEASE_MINOR_VERSION_C != OS_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Can_FlexCan.c and Os.h are different"
        #endif
    #endif
#endif
/*==================================================================================================
*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/

/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/

/*==================================================================================================
*                                      LOCAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      LOCAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                      GLOBAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      GLOBAL VARIABLES
==================================================================================================*/

#define CAN_43_FLEXCAN_START_SEC_VAR_NO_INIT_UNSPECIFIED
/* @violates @ref Can_Flexcan_c_REF_1 MISRA 2012 Required Directive 4.10 */
#include "Can_43_FLEXCAN_MemMap.h"
/**
* @brief          Array holding current status/run-time configuration of individual FlexCAN controllers
* @details        Array holding current status/run-time configuration of individual FlexCAN controllers
*                 - information like Guard bits, Pre-calculated MB INT masks, Storage space for id, INT nesting level,
*                 Index of MB buffer being cancelled, Index of the first MB used for Tx , Controller Options.
*
*
*/
VAR(Can_43_FLEXCAN_ControllerStatusType, CAN_VAR) Can_43_FLEXCAN_ControllerStatuses[CAN_43_FLEXCAN_MAXCTRL_CONFIGURED];

/**
* @brief          Variable to hold the number of tick correspond to TimeOutDuration
* @details        Variable to hold the number of tick correspond to TimeOutDuration
*
*/
static VAR(uint32, CAN_VAR) Can_u32TicksDelayDuration;


#define CAN_43_FLEXCAN_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
/* @violates @ref Can_Flexcan_c_REF_1 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Flexcan_c_REF_2 MISRA 2012 Advisory Rule 20.1 */
#include "Can_43_FLEXCAN_MemMap.h"

#define CAN_43_FLEXCAN_START_SEC_CONST_UNSPECIFIED
/* @violates @ref Can_Flexcan_c_REF_1 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Flexcan_c_REF_2 MISRA 2012 Advisory Rule 20.1 */
#include "Can_43_FLEXCAN_MemMap.h"


 /**
* @brief          define number of bytes of MBs
* @details        define number of bytes of MBs
*
*/
#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    /*maximum threshold values for DLC*/
    static CONST(uint8, CAN_CONST)         Can_Flexcan_aDataLengthMax[CAN_FLEXCAN_NUM_VAL_DLC_U8] = {CAN_FLEXCAN_MAX_PAYLOAD8_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD12_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD16_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD20_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD24_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD32_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD48_U8,
                                                                                              CAN_FLEXCAN_MAX_PAYLOAD64_U8
                                                                                             };
    /*minimum threshold values for DLC*/
    /* @violates @ref Can_Flexcan_c_REF_7 MISRA 2012 Advisory Rule 8.9 */
    static CONST(uint8, CAN_CONST)         Can_Flexcan_aDataLengthMin[CAN_FLEXCAN_NUM_VAL_DLC_U8] = {CAN_FLEXCAN_MIN_PAYLOAD0_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD9_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD13_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD17_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD21_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD25_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD33_U8,
                                                                                              CAN_FLEXCAN_MIN_PAYLOAD49_U8
                                                                                             };
#endif

/**
* @brief          define number of filter's payload
* @details        define number of filter's payload
*/
#if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
    #if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
    /* @violates @ref Can_Flexcan_c_REF_7 MISRA 2012 Advisory Rule 8.9 */
    static CONST(uint8, CAN_CONST)         Can_Flexcan_aNumFilter[CAN_FLEXCAN_NUM_FILT_PAYLOAD_U8] = {CAN_FLEXCAN_FILTER_PAYLOAD7_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD9_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD11_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD13_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD15_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD17_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD19_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD21_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD23_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD25_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD27_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD29_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD31_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD33_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD35_U8,
                                                                                               CAN_FLEXCAN_FILTER_PAYLOAD37_U8
                                                                                              };
    #endif
 #endif

/**
* @brief          CAN base address array
* @details        CAN base address array
*/
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
CONST(uint32, CAN_CONST) Can_u32BaseAddress[] = {
#ifdef  FLEXCAN_0_BASEADDR
        FLEXCAN_0_BASEADDR,
#endif /* FLEXCAN_0_BASEADDR */
#ifdef  FLEXCAN_1_BASEADDR
        FLEXCAN_1_BASEADDR,
#endif /* FLEXCAN_1_BASEADDR */
#ifdef  FLEXCAN_2_BASEADDR
        FLEXCAN_2_BASEADDR,
#endif /* FLEXCAN_2_BASEADDR */
#ifdef  FLEXCAN_3_BASEADDR
        FLEXCAN_3_BASEADDR,
#endif /* FLEXCAN_3_BASEADDR */
#ifdef  FLEXCAN_4_BASEADDR
        FLEXCAN_4_BASEADDR,
#endif /* FLEXCAN_4_BASEADDR */
#ifdef  FLEXCAN_5_BASEADDR
        FLEXCAN_5_BASEADDR,
#endif /* FLEXCAN_5_BASEADDR */
#ifdef  FLEXCAN_6_BASEADDR
        FLEXCAN_6_BASEADDR,
#endif /* FLEXCAN_6_BASEADDR */
#ifdef  FLEXCAN_7_BASEADDR
        FLEXCAN_7_BASEADDR
#endif /* FLEXCAN_7_BASEADDR */
};


/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
CONST(Can_FlexcanMaskFlagType, CAN_CONST) Can_IflagImask[(uint8)((uint8)CAN_43_FLEXCAN_MAXMB_SUPPORTED >> FLEXCAN_MB_SHIFT5BIT_U8)][FLEXCAN_CONTROLLERS_NO] =
        {

                {
                   #ifdef  FLEXCAN_0_BASEADDR
                    {
                        (FLEXCAN_0_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_0_BASEADDR + 0x28U ) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_1_BASEADDR
                   ,{
                        (FLEXCAN_1_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_1_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_2_BASEADDR
                   ,{
                        (FLEXCAN_2_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_2_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_3_BASEADDR
                   ,{
                        (FLEXCAN_3_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_3_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_4_BASEADDR
                   ,{
                        (FLEXCAN_4_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_4_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_5_BASEADDR
                   ,{
                        (FLEXCAN_5_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_5_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_6_BASEADDR
                   ,{
                        (FLEXCAN_6_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_6_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_7_BASEADDR
                   ,{
                        (FLEXCAN_7_BASEADDR + 0x30U) /*Base Address + IFLAG 1 offset*/
                        ,
                        (FLEXCAN_7_BASEADDR + 0x28U) /*Base Address + IMASK 1 offset*/
                    }
                   #endif
                }
            #if ((CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_64_U8) || (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_96_U8 ) || (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_128_U8 ))
                ,{
                   #ifdef  FLEXCAN_0_BASEADDR
                    {
                        (FLEXCAN_0_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_0_BASEADDR + 0x24U ) /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_1_BASEADDR
                   ,{
                        (FLEXCAN_1_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_1_BASEADDR + 0x24U ) /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_2_BASEADDR
                   ,{
                        (FLEXCAN_2_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_2_BASEADDR + 0x24U )  /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_3_BASEADDR
                   ,{
                        (FLEXCAN_3_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_3_BASEADDR + 0x24U ) /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_4_BASEADDR
                   ,{
                        (FLEXCAN_4_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_4_BASEADDR + 0x24U )  /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_5_BASEADDR
                   ,{
                        (FLEXCAN_5_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_5_BASEADDR + 0x24U )  /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_6_BASEADDR
                   ,{
                        (FLEXCAN_6_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_6_BASEADDR + 0x24U ) /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                   #ifdef  FLEXCAN_7_BASEADDR
                   ,{
                        (FLEXCAN_7_BASEADDR + 0x2CU ) /*Base Address + IFLAG 2 offset*/
                        ,
                        (FLEXCAN_7_BASEADDR + 0x24U )  /*Base Address + IMASK 2 offset*/
                    }
                   #endif
                }
            #endif
            #if  ((CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_96_U8 ) || (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_128_U8 ))
                ,{
                    #ifdef  FLEXCAN_0_BASEADDR
                        {
                            (FLEXCAN_0_BASEADDR + 0x74U )  /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_0_BASEADDR + 0x6CU )  /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_1_BASEADDR
                       ,{
                            (FLEXCAN_1_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_1_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_2_BASEADDR
                       ,{
                            (FLEXCAN_2_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_2_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_3_BASEADDR
                       ,{
                            (FLEXCAN_3_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_3_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_4_BASEADDR
                       ,{
                            (FLEXCAN_4_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_4_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_5_BASEADDR
                       ,{
                            (FLEXCAN_5_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_5_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_6_BASEADDR
                       ,{
                            (FLEXCAN_6_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_6_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_7_BASEADDR
                       ,{

                            (FLEXCAN_7_BASEADDR + 0x74U ) /*Base Address + IFLAG 3 offset*/
                            ,
                            (FLEXCAN_7_BASEADDR + 0x6CU ) /*Base Address + IMASK 3 offset*/
                        }
                    #endif
                }
            #endif
            #if  (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_128_U8 )
                ,{
                    #ifdef  FLEXCAN_0_BASEADDR
                        {
                            (FLEXCAN_0_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_0_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_1_BASEADDR
                       ,{
                            (FLEXCAN_1_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_1_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_2_BASEADDR
                       ,{
                            (FLEXCAN_2_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_2_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_3_BASEADDR
                       ,{
                            (FLEXCAN_3_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_3_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_4_BASEADDR
                       ,{
                            (FLEXCAN_4_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_4_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_5_BASEADDR
                       ,{
                            (FLEXCAN_5_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_5_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_6_BASEADDR
                       ,{
                            (FLEXCAN_6_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_6_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                    #ifdef  FLEXCAN_7_BASEADDR
                       ,{

                            (FLEXCAN_7_BASEADDR + 0x70U ) /*Base Addrs + IFLAG 4 offset*/
                            ,
                            (FLEXCAN_7_BASEADDR + 0x68U ) /*Base Addrs + IMASK 4 offset*/
                        }
                    #endif
                }
            #endif
    };
#define CAN_43_FLEXCAN_STOP_SEC_CONST_UNSPECIFIED
/* @violates @ref Can_Flexcan_c_REF_1 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Flexcan_c_REF_2 MISRA 2012 Advisory Rule 20.1 */
#include "Can_43_FLEXCAN_MemMap.h"

#define CAN_43_FLEXCAN_START_SEC_CODE
/* @violates @ref Can_Flexcan_c_REF_1 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Flexcan_c_REF_2 MISRA 2012 Advisory Rule 20.1 */
#include "Can_43_FLEXCAN_MemMap.h"

/*=================================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
=================================================================================================*/
extern FUNC(boolean, COM_APPL_CODE) CAN_43_FLEXCAN_LPduReceiveCalloutFunction(uint8 Hrh,Can_IdType CanId,uint8 CanDlc,const uint8 *CanSduPtr);

LOCAL_INLINE FUNC(void, CAN_CODE) Can_FlexCan_DisableInterrupts (VAR(uint8, AUTOMATIC) u8Controller);

LOCAL_INLINE FUNC(void, CAN_CODE) Can_FlexCan_EnableInterrupts ( \
                                        VAR(uint8, AUTOMATIC) u8Controller, \
                                        P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor \
                                                               );

#if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
    static FUNC (void, CAN_CODE) Can_FlexCan_InitRxFiFo( VAR(uint8, AUTOMATIC) Controller, VAR(uint8, AUTOMATIC) u8HwOffset);
#endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) */

static FUNC (void, CAN_CODE) Can_FlexCan_InitTransmitMBs( VAR(uint8, AUTOMATIC) Controller, VAR(uint8, AUTOMATIC) u8HwOffset);

static FUNC (void, CAN_CODE) Can_FlexCan_InitReceiveMBs( VAR(uint8, AUTOMATIC) Controller, VAR(uint8, AUTOMATIC) u8HwOffset );

#if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
    static FUNC (void, CAN_CODE) Can_FlexCan_InitRxGlobalMask( VAR(uint16, AUTOMATIC) u16MBGlobalIndex, VAR(uint8, AUTOMATIC) u8HwOffset, P2VAR(boolean, AUTOMATIC, CAN_APPL_DATA) pRxglobalMskFlag);
#endif
static FUNC (void, CAN_CODE) Can_FlexCan_InitRxInvidualMask( VAR(uint16, AUTOMATIC) u16MBGlobalIndex, VAR(uint8, AUTOMATIC) u8HwOffset);

static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerToStopMode(  VAR(uint8, AUTOMATIC) Controller,
                                                                            P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor,
                                                                            VAR(boolean, AUTOMATIC) canif_notification_required
                                                                          );
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerToStartMode(  VAR(uint8, AUTOMATIC) Controller,
                                                                            P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor
                                                                          );
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerToSleepMode(  VAR(uint8, AUTOMATIC) Controller );

static FUNC (void, CAN_CODE) Can_FlexCan_ProcessTxPoll( CONST(uint8, AUTOMATIC) controller, CONST(uint16, AUTOMATIC) u16MBGlobalIndex );

#if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
static FUNC (void, CAN_CODE) Can_FlexCan_ProcessRxFifo( CONST(uint8, AUTOMATIC) controller);
#endif

static FUNC (void, CAN_CODE) Can_FlexCan_ProcessRxNormal( CONST(uint8, AUTOMATIC) controller, CONST(uint16, AUTOMATIC) u16MBGlobalIndex );

static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_UpdateMB( VAR(uint8, AUTOMATIC) u8CtrlId, VAR(uint16, AUTOMATIC) u16MBGlobalIndex ,
                                                                P2CONST(Can_PduType, AUTOMATIC, CAN_APPL_CONST) PduInfo, VAR(boolean, AUTOMATIC) bEnabledFD
                                                            );
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_ValidHth (  Can_HwHandleType Hth,
                                                               P2CONST(Can_PduType, AUTOMATIC, CAN_APPL_CONST) PduInfo,
                                                               VAR(uint16, AUTOMATIC) u16MBGlobalIndex,
                                                               VAR(boolean, AUTOMATIC) bEnabledFD
                                                            );
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */

#ifdef CAN_43_FLEXCAN_FLEXCAN_CLKSRC_AVAIABLE
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SellectClockSource( VAR(uint8, AUTOMATIC) u8Controller, VAR(uint8, AUTOMATIC) u8HwOffset, VAR(uint8, AUTOMATIC) u8BaudrateIndex );
#endif /* CAN_43_FLEXCAN_FLEXCAN_CLKSRC_AVAIABLE */
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_GotoFreezeMode( VAR(uint8, AUTOMATIC) u8HwOffset);

static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_ResetController( VAR(uint8, AUTOMATIC) u8HwOffset);

#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    #ifdef ERR_IPV_FLEXCAN_0016
        #if (ERR_IPV_FLEXCAN_0016 == STD_ON)
            static FUNC (void, CAN_CODE) Can_FlexCan_SetFDENBitErrata( VAR(uint8, AUTOMATIC) u8HwOffset );
        #else
            #error : the define ERR_IPV_FLEXCAN_0016 must not be STD_OFF
        #endif /* (ERR_IPV_FLEXCAN_0016 == STD_ON) */
    #endif /* (ERR_IPV_FLEXCAN_0016) */
#endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */

/*================================================================================================
*                                       LOCAL FUNCTIONS
=================================================================================================*/
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
LOCAL_INLINE FUNC(void, CAN_CODE) Can_FlexCan_DisableInterrupts (VAR(uint8, AUTOMATIC) u8Controller)
{
    VAR(uint8, AUTOMATIC) u8RegCount=0U;
    VAR(uint8, AUTOMATIC) u8HwOffset=0U;

    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8ControllerOffset;
    do
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_WRITE32( Can_IflagImask[u8RegCount][u8HwOffset].u32CanImask, (uint32)(0U));
        u8RegCount++;
    }
    while(u8RegCount < (CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8NumberOfMB >> FLEXCAN_MB_SHIFT5BIT_U8));
    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_07();
    /* Disable BusOff, Error, TxW, RxW interrupts. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    REG_BIT_CLEAR32( FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_BOFFMSK_U32);
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    REG_BIT_CLEAR32( FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_ERRMSK_U32);

#if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
    if ( CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_IE_U32 == (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_IE_U32 & Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u8Controller].u32Options))
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_CLEAR32( FLEXCAN_ERFIER(u8HwOffset), FLEXCAN_ERFSR_ERFDA_U32);
        
        if ( CAN_CONTROLLERCONFIG_OVER_EN_U32 == (CAN_CONTROLLERCONFIG_OVER_EN_U32 & Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u8Controller].u32Options))
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_BIT_CLEAR32( FLEXCAN_ERFIER(u8HwOffset), FLEXCAN_ERFSR_ERFOVF_U32);
        }
    }
#endif

    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_07();
}

/*================================================================================================*/
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
LOCAL_INLINE FUNC(void, CAN_CODE) Can_FlexCan_EnableInterrupts ( \
                                        VAR(uint8, AUTOMATIC) u8Controller, \
                                        P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor \
                                                               )
{
    VAR(uint8, AUTOMATIC) u8RegCount=0U;
    VAR(uint8, AUTOMATIC) u8HwOffset=0U;

    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8ControllerOffset;
    /* Enable INTs from MBs. */
    do
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_WRITE32(Can_IflagImask[u8RegCount][u8HwOffset].u32CanImask, Can_43_FLEXCAN_ControllerStatuses[u8Controller].u32MBInterruptMask[u8RegCount]);
        u8RegCount++;
    }while(u8RegCount < (CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8NumberOfMB >> FLEXCAN_MB_SHIFT5BIT_U8));
    /* Mark flag that tells if at least one INT is enabled. */

    /*
      (CAN204) The Can module shall track all individual enabling and disabling of interrupts in other functions (i.e. Can_SetControllerMode), so that the correct interrupt enable state can be restored.
    */
    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_08();
    if ( CAN_CONTROLLERCONFIG_BOPOL_EN_U32 != (CAN_CONTROLLERCONFIG_BOPOL_EN_U32 & CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u32Options))
    {
        /* BusOff - enable the interrupt. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_BOFFMSK_U32);

        /* Mark flag that tells if at least one INT is enabled. */
    }
    if ( CAN_CONTROLLERCONFIG_ERR_EN_U32 == (CAN_CONTROLLERCONFIG_ERR_EN_U32 & pCanControlerDescriptor->u32Options))
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_ERRMSK_U32);
    }

#if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
    if ( CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_IE_U32 == (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_IE_U32 & pCanControlerDescriptor->u32Options))
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_ERFIER(u8HwOffset), FLEXCAN_ERFSR_ERFDA_U32);
        
        if ( CAN_CONTROLLERCONFIG_OVER_EN_U32 == (CAN_CONTROLLERCONFIG_OVER_EN_U32 & pCanControlerDescriptor->u32Options))
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_BIT_SET32( FLEXCAN_ERFIER(u8HwOffset), FLEXCAN_ERFSR_ERFOVF_U32);
        }
    }
#endif
    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_08();
}

/*================================================================================================*/
/**
* @brief          This function performs to set the FDEN bit in the CAN_MCR register for Can FD.
* @details        This function performs to set the FDEN for Can FD (Errata e10368).
*                 This routine is called by:
*                  - Can_ChangeBaudrate() from Can.c file.
*
* @param[in]      Controller hardware offset
*
* @pre            FlexCAN is already in freeze mode.
*
*
*/
#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    #ifdef ERR_IPV_FLEXCAN_0016
        #if (ERR_IPV_FLEXCAN_0016 == STD_ON)
static FUNC (void, CAN_CODE) Can_FlexCan_SetFDENBitErrata( VAR(uint8, AUTOMATIC) u8HwOffset )
{
#if STD_OFF == CAN_43_FLEXCAN_E10368_INCONSISTENT
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
  #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
  #endif
#endif

#if STD_ON == CAN_43_FLEXCAN_E10368_INCONSISTENT
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), (uint32)(FLEXCAN_MCR_FDEN_U32));
#else

    #ifdef ERR_IPV_FLEXCAN_0016_ACTIVE
        if (ERR_IPV_FLEXCAN_0016_ACTIVE == (boolean)TRUE)
    #endif /*ERR_IPV_FLEXCAN_0016_ACTIVE*/
        {
            /* Step 3: Set the LPB (Loop Back Mode) bit of the CAN_CTRL1 register. */
            REG_BIT_SET32( FLEXCAN_CTRL(u8HwOffset), (uint32)(FLEXCAN_CTRL_LPB_U32));

            /* Step 4: Configure only one message buffer to be transmitted.*/
            REG_WRITE32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(0U)), (uint32)(0x682U) << (uint32)FLEXCAN_STANDARD_ID_SHIFT_U32);
            REG_WRITE32( FLEXCAN_MB((u8HwOffset), (uint32)(0U)), (uint32)(FLEXCAN_MBCS_CODETX_U32 | FLEXCAN_MBCS_CODETXEN_U32 | FLEXCAN_MBCS_SRR_U32| FLEXCAN_MBCS_RTR_U32 | ((uint32)0x5U << (uint32)16U)) );

            /*Extra steps, configure standard baudrate and fd baudrate */
            REG_WRITE32( FLEXCAN_CTRL(u8HwOffset), (uint32)((uint32)0x00490001U | FLEXCAN_CTRL_LPB_U32));
            REG_WRITE32(FLEXCAN_FDCBT(u8HwOffset), (uint32)(0x00000421U));

            /* Step 5: Set the FDEN bit of the CAN_MCR register. */
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FDEN_U32);

            /* Step 6: Clear the HALT bit of the MCR register to leave freeze mode. */
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);

            /* Step 7: Wait the FRZACK bit of the CAN_MCR register to be cleared by the hardware. */
            u32TotalElapsedTime = 0U;
        #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
        #endif
            while ( (FLEXCAN_MCR_FRZACK_U32 == ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
                    (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
                  )
            {
            #ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
                u32TotalElapsedTime++;
            #else
                (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
                u32TotalElapsedTime += u32ElapsedTime;
            #endif
            }

            /* Step 8: Wait the respective bit of the CAN_IFLAG register to be set (successfully transmission in loop back mode). */
            u32TotalElapsedTime = 0U;
        #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
        #endif
            while ( ( (uint32)0U == ((uint32)REG_READ32(FLEXCAN_IFLAG1(u8HwOffset))) ) && \
                    (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
                  )
            {
            #ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
                u32TotalElapsedTime++;
            #else
                (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
                u32TotalElapsedTime += u32ElapsedTime;
            #endif
            }

            /* Step 9: Clear the respective bit of the CAN_IFLAG register by writing 1. */
            REG_WRITE32(  FLEXCAN_IFLAG1(u8HwOffset), (uint32)0xFFFFFFFFU);

            /* Step 10: Set the HALT and FRZ bits of the CAN_MCR register. */
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);

            /* Step 11: Wait the FRZACK bit of the CAN_MCR register to be set by the hardware. */
            u32TotalElapsedTime = 0U;
        #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
        #endif
            while ( (FLEXCAN_MCR_FRZACK_U32 != ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
                    (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
                  )
            {
            #ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
                u32TotalElapsedTime++;
            #else
.                (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
                u32TotalElapsedTime += u32ElapsedTime;
            #endif
            }

            /*Extra steps, configure standard baudrate and fd baudrate */
            REG_WRITE32( FLEXCAN_CTRL(u8HwOffset), (uint32)0U );
            REG_WRITE32(FLEXCAN_FDCBT(u8HwOffset), (uint32)0U);
            /* Step 12: Clear the LPB (Loop Back Mode) bit of the CAN_CTRL1 register. */
            REG_BIT_CLEAR32( FLEXCAN_CTRL(u8HwOffset), (uint32)(FLEXCAN_CTRL_LPB_U32));
        }
    #ifdef ERR_IPV_FLEXCAN_0016_ACTIVE
       else
       {
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), (uint32)(FLEXCAN_MCR_FDEN_U32));
       }
    #endif /*ERR_IPV_FLEXCAN_0016_ACTIVE*/
#endif /* Errata inconsistency */
}
        #endif /* (ERR_IPV_FLEXCAN_0016 == STD_ON) */
    #endif /* (ERR_IPV_FLEXCAN_0016) */
#endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */
/*================================================================================================*/
/**
* @brief          Service for Rx FIFO initialization in the Can_FlexCan_InitController function
* @details        Service for Rx FIFO initialization in the Can_FlexCan_InitController function
*
*                 This routine is called by:
*                  - Can_FlexCan_InitController()
*
* @param[in]      + Controller: CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*                 + u8HwOffset: The hardware offset for this controller.
*
*/
#if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
static FUNC (void, CAN_CODE) Can_FlexCan_InitRxFiFo( VAR(uint8, AUTOMATIC) Controller, VAR(uint8, AUTOMATIC) u8HwOffset)
{
    /* Local copy of pointer to the controller descriptor. */
    VAR(Can_PtrControlerDescriptorType, AUTOMATIC) pCanControlerDescriptor = NULL_PTR;
    /* Used to save the the index pointing to the table id connfiguration. */
    VAR(uint16, AUTOMATIC)             u16RxFifoTableIdIndex = 0U;
    /* Used to index the Table ID for RxFifo. */
    VAR(uint8, AUTOMATIC)             u8RxFifoTableId = 0U;
    /* Used to access configured table id and filtermask. */
    VAR(uint16, AUTOMATIC)             u16TempIndex = 0U;
#if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
    /* Used to filter FIFO number */
    VAR(uint8, AUTOMATIC)             u8FilterIndex = 0U;
    /* Index of MB */
    VAR(uint16, AUTOMATIC)             u16MbGlobalIndex = 0U;
#endif
#if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
    VAR(uint32, AUTOMATIC)             u32EnhancedFifoCfg = 0U;
#endif
#ifdef CAN_43_FLEXCAN_DMA_USED
    static VAR(Mcl_DmaTcdAttributesType, MCL_VAR)  Can_DmaTcdAttributes;
#endif

    /* Fill the local pointer copy with address of the Controller Descriptor.  */
    pCanControlerDescriptor = &(Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller]);
    /*Initialize the index used to acces the fifo Rx fifo filter list for all controllers*/
    /* Calculate the index pointing to table id configuration. */
    for(u16TempIndex = 0U; u16TempIndex < Controller; u16TempIndex++)
    {
    #if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
        if ( CAN_CONTROLLERCONFIG_RXFIFO_U32 == (Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u16TempIndex].u32Options & CAN_CONTROLLERCONFIG_RXFIFO_U32) )
        {
            u16RxFifoTableIdIndex += (4U*((uint16)Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u16TempIndex].u8RxFiFoUsedMb - (uint16)6U));
        }
    #endif
    #if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
        if (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32 == (Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u16TempIndex].u32Options & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32))
        {
            u16RxFifoTableIdIndex += (((Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u16TempIndex].u16EnhancedRxFifoNFE) * 2U) - Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u16TempIndex].u16EnhancedRxFifoNEXIF);
        }
    #endif
    }

#if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
    /* If RX FIFO is used, then configure the Controller's registers for Rx Fifo. */
    if ( CAN_CONTROLLERCONFIG_RXFIFO_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_RXFIFO_U32) )
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FEN_U32) ;
#ifndef CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_RMW32( FLEXCAN_CTRL2(u8HwOffset),(FLEXCAN_CTRL2_RFFN_U32) ,(uint32)((((uint32)Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller].u8RxFiFoUsedMb-(uint32)8U)/(uint32)2U)<<24U));
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_RXFGMASK(u8HwOffset), (((uint32)(Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller].u32RxFifoGlobalMask)) & FLEXCAN_RXFGMASK_CONFIG_MASK_U32));
#endif /* defined CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK */
        /* Processing MB must start after the last MB used by the Rx Fifo filters */
        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_11();
        switch (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_IDAM_MASK_U32)
        {
            case CAN_CONTROLLERCONFIG_IDAM_A_U32:
                /* One full ID per filter element - clear IDAM bits. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                REG_RMW32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_IDAM_U32, ((uint32)(FLEXCAN_MCR_IDAM32_U32))) ;
                break;

            case CAN_CONTROLLERCONFIG_IDAM_B_U32:
                /* Two full standard IDs or two partial 14-bit extended IDs per filter element. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                REG_RMW32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_IDAM_U32, ((uint32)(FLEXCAN_MCR_IDAM16_U32))) ;
                break;

            case CAN_CONTROLLERCONFIG_IDAM_C_U32:
                /* Four partial 8-bit IDs (standard or extended) per filter element. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                REG_RMW32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_IDAM_U32, ((uint32)(FLEXCAN_MCR_IDAM08_U32))) ;
                break;

            case CAN_CONTROLLERCONFIG_IDAM_D_U32:
                /* RX Fifo is enabled, but all frames will be rejected. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                REG_RMW32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_IDAM_U32, ((uint32)(FLEXCAN_MCR_IDAM_U32))) ;
                break;
            default:
            {
                break;
            }
        } /* end switch. */
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_11();

        u8FilterIndex = ((Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller].u8RxFiFoUsedMb - 8U) / 2U);
        /* Init the IDTable and RXIMR registers of RxFifo. */
        for ( u16TempIndex = u16RxFifoTableIdIndex; u16TempIndex < (u16RxFifoTableIdIndex + (4U * ((uint16)Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller].u8RxFiFoUsedMb - (uint16)6U))); u16TempIndex++)
        {
            /* Calculate the physical address for each table to write the Table ID and FilterMask. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_RXFIFO_ID((u8HwOffset), (uint32)(u8RxFifoTableId)),(uint32)((Can_43_FLEXCAN_pCurrentConfig->pRxFiFoTableIdConfig[u16TempIndex]).u32TableId));

        #if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
            /* Check if BCC support is enabled in configuration */
            if ( CAN_CONTROLLERCONFIG_BCC_EN_U32 != (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_BCC_EN_U32) )
            {
        #endif
                if (u8RxFifoTableId <= Can_Flexcan_aNumFilter[u8FilterIndex])
                {
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32(FLEXCAN_RXIMR((u8HwOffset), (uint32)(u8RxFifoTableId)),(uint32)((Can_43_FLEXCAN_pCurrentConfig->pRxFiFoTableIdConfig[u16TempIndex]).u32TableFilterMask));
                }
        #if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
            }
        #endif
            /* Increment the Table Id index for RxFifo configuration. */
            u8RxFifoTableId++;
        }
        /* Get the index of first MB configured for Rx FiFo */
        /* @violates @ref Can_Flexcan_c_REF_8 MISRA 2012 Required Rule 18.1 */
        u16MbGlobalIndex = Can_43_FLEXCAN_ControllerStatuses[Controller].u16MBMapping[0U];
        /* Configure Interrupt Mask Bits in case handling of RX is implemented by interrupts (not by polling). */
        if ((boolean)TRUE != Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].CanHwObjectUsesPolling)
        {
            /* Check if Overflow RxFifo interrupt is enabled and set the IMASK bit if yes. */
            if ( CAN_CONTROLLERCONFIG_OVER_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_OVER_EN_U32) )
            {
                /* @violates @ref Can_Flexcan_c_REF_8 MISRA 2012 Required Rule 18.1 */
                Can_43_FLEXCAN_ControllerStatuses[Controller].u32MBInterruptMask[FLEXCAN_IMASK1_INDEX_U8] |= FLEXCAN_FIFO_OVERFLOW_INT_MASK_U32;
            }
            /* Check if Warning RxFifo interrupt is enabled and set the IMASK bit if yes. */
            if ( CAN_CONTROLLERCONFIG_WARN_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_WARN_EN_U32) )
            {
                /* @violates @ref Can_Flexcan_c_REF_8 MISRA 2012 Required Rule 18.1 */
                Can_43_FLEXCAN_ControllerStatuses[Controller].u32MBInterruptMask[FLEXCAN_IMASK1_INDEX_U8] |= FLEXCAN_FIFO_WARNING_INT_MASK_U32;
            }
            /* If RxFifo is enabled, then frames are implicitly enabled. IDAM bits can filter the messages or can block at all. */
            /* @violates @ref Can_Flexcan_c_REF_8 MISRA 2012 Required Rule 18.1 */
            Can_43_FLEXCAN_ControllerStatuses[Controller].u32MBInterruptMask[FLEXCAN_IMASK1_INDEX_U8] |= FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32;
        }
    }
#endif
#if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
    if (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32))
    {
        /* Enable Enhanced Rx FIFO */
        u32EnhancedFifoCfg = FLEXCAN_ERFCR_ERFEN_U32;
        /* configure the total number of enhanced Rx FIFO filter elements to be used in Enhanced Rx FIFO reception. */
        u32EnhancedFifoCfg |= (((uint32)pCanControlerDescriptor->u16EnhancedRxFifoNFE - (uint32)1U) << FLEXCAN_ERFCR_NFE_SHIFT_U8);
        /* configure the number of extended ID and standard ID filter elements to be used in Enhanced Rx FIFO reception. */
        u32EnhancedFifoCfg |= ((uint32)(pCanControlerDescriptor->u16EnhancedRxFifoNEXIF) << FLEXCAN_ERFCR_NEXIF_SHIFT_U8);
    #ifdef CAN_43_FLEXCAN_DMA_USED
        if (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_DMA_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_DMA_EN_U32))
        {
            /* number of words to be transfer for each Enhanced Rx FIFO data element. */
            u32EnhancedFifoCfg |= ((uint32)19U << FLEXCAN_ERFCR_DMALW_SHIFT_U8);
        }
    #endif
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_ERFCR(u8HwOffset), u32EnhancedFifoCfg);
        
        /*Clear EFRSR[ERFUFW], EFRSR[ERFOVF], EFRSR[ERFWMI], and EFRSR[ERFDA], if they are set and reset Enhanced Rx FIFO engine. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_ERFSR(u8HwOffset), (FLEXCAN_ERFSR_ERFUFW_U32 | FLEXCAN_ERFSR_ERFOVF_U32 | FLEXCAN_ERFSR_ERFWMI_U32 | FLEXCAN_ERFSR_ERFDA_U32 | FLEXCAN_ERFSR_ERFCLR_U32));
        
        for ( u16TempIndex = u16RxFifoTableIdIndex; u16TempIndex < (u16RxFifoTableIdIndex + (((pCanControlerDescriptor->u16EnhancedRxFifoNFE) * 2U) - pCanControlerDescriptor->u16EnhancedRxFifoNEXIF)); u16TempIndex++)
        {
            /* Configure the Extended filter elements fu32TableIdirst. */
            if (u16TempIndex < (u16RxFifoTableIdIndex + pCanControlerDescriptor->u16EnhancedRxFifoNEXIF))
            {
                /* Each extended-ID filter element is stored in two ERFFELn registers */
                /* First ERFFELn register */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(FLEXCAN_ERFFEL(u8HwOffset, u8RxFifoTableId), (uint32)((Can_43_FLEXCAN_pCurrentConfig->pRxFiFoTableIdConfig[u16TempIndex]).u32TableId));
                u8RxFifoTableId++;
                /* Second ERFFELn register */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(FLEXCAN_ERFFEL(u8HwOffset, u8RxFifoTableId), (uint32)((Can_43_FLEXCAN_pCurrentConfig->pRxFiFoTableIdConfig[u16TempIndex]).u32TableFilterMask));
            }
            else
            {
                /* each standard-ID filter element is stored in one ERFFELn register */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(FLEXCAN_ERFFEL(u8HwOffset, u8RxFifoTableId), ((Can_43_FLEXCAN_pCurrentConfig->pRxFiFoTableIdConfig[u16TempIndex]).u32TableId) | ((Can_43_FLEXCAN_pCurrentConfig->pRxFiFoTableIdConfig[u16TempIndex]).u32TableFilterMask));
            }
            u8RxFifoTableId++;
        }
    #ifdef CAN_43_FLEXCAN_DMA_USED
        if (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_DMA_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_DMA_EN_U32))
        {
            /* Enable DMA */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_BIT_SET32(FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_DMA_U32);
            /* DMA source address */
            Can_DmaTcdAttributes.u32saddr = FLEXCAN_ENHANCED(u8HwOffset);
            /* DMA destination address */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            Can_DmaTcdAttributes.u32daddr = (uint32)pCanControlerDescriptor->pDestBuffer; 
            /* Source Size */
            Can_DmaTcdAttributes.u32ssize = (uint32)DMA_SIZE_4BYTES;
            /* Destination Size */
            Can_DmaTcdAttributes.u32dsize = (uint32)DMA_SIZE_4BYTES;
            /* Source address offset */
            Can_DmaTcdAttributes.u32soff =  (uint32)DMA_OFFSET_32_BITS;
            /* Destination address offset */
            Can_DmaTcdAttributes.u32doff =  (uint32)DMA_OFFSET_32_BITS;
            /* Source Modulo, feature disabled */
            Can_DmaTcdAttributes.u32smod = 0U;
            /* Destination Modulo, feature disabled */
            Can_DmaTcdAttributes.u32dmod = 0U;
            /* Total bytes transfer = max size of a FD Message */
            Can_DmaTcdAttributes.u32num_bytes = (uint32)80U;
            /*
                Number of Major loop.
                Each time enhanced RxFiFo receive a Message buffer,a DMA request is generated, that MB is transfered by DMA (a minor loop).
                When the number MB transfered by DMA is equal Major loop, a DMA interrupt is generated, notification function is called.
            */
            Can_DmaTcdAttributes.u32iter = (uint32)pCanControlerDescriptor->u8NumberMBTransfer; 
            /* Configure DMA */
            Mcl_DmaConfigChannel(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel, &Can_DmaTcdAttributes);
            /* After each minor loop: set source address to its original address. */
            Mcl_DmaTcdSetMinorLoop(Mcl_DmaGetChannelTcdAddress(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel), (boolean)TRUE, (boolean)FALSE, ((sint32)Can_DmaTcdAttributes.u32num_bytes * (-1)), Can_DmaTcdAttributes.u32num_bytes);
            /* After each major loop: set source address to its original address */
            Mcl_DmaTcdSetSlast(Mcl_DmaGetChannelTcdAddress(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel), ((sint32)Can_DmaTcdAttributes.u32num_bytes * (-1)));
            /* After each major loop: set destination address to its original address */
            Mcl_DmaTcdSetDlast(Mcl_DmaGetChannelTcdAddress(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel), ((sint32)Can_DmaTcdAttributes.u32num_bytes * (-1)) * ((sint32)pCanControlerDescriptor->u8NumberMBTransfer));
            /* Disable Hardware request after each major loop complete */
            Mcl_DmaTcdSetFlags(Mcl_DmaGetChannelTcdAddress(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel),DMA_TCD_DISABLE_REQ_U8);
            /* Enable the callback notification at the end of the transfer */
            Mcl_DmaEnableNotification(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel, MCL_DMA_TRANSFER_COMPLETE);
            /*Enable Hardware request */
            Mcl_DmaEnableHwRequest(pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel);
        }
    #endif
    }
#endif
}
#endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) */

#if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
/*================================================================================================*/
/**
* @brief          Initialize Filter Global Mask for Receive Message buffer
* @details        Initialize Filter Global Mask for Receive Message buffer
*
*                 This routine is called by:
*                  - Can_FlexCan_InitReceiveMBs()
*
* @param[in]      + u16MBGlobalIndex: Index of MB in the MBs' information structure to process.
*                 + u8HwOffset: The hardware offset for this controller.
*
*/

static FUNC (void, CAN_CODE) Can_FlexCan_InitRxGlobalMask( VAR(uint16, AUTOMATIC) u16MBGlobalIndex, VAR(uint8, AUTOMATIC) u8HwOffset, P2VAR(boolean, AUTOMATIC, CAN_APPL_DATA) pRxglobalMskFlag)
{
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    /* Variable for indexing the MBs inside a single controller. */
    VAR(uint8, AUTOMATIC)             u8MbCtrlIndex = 0U;
    /* Mask of Message Buffer */
    VAR(uint32, AUTOMATIC)             u32IdMask = 0U;
    /* Pointer to the MB container structure. */
    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);
    /* Get the index of Hardware Message Buffer */
    u8MbCtrlIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;

    if(CAN_43_FLEXCAN_MAXMASKCOUNT == ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdMaskIndex))
    {
        u32IdMask = (uint32)(FLEXCAN_NO_MASK_U32);
    }
    else
    {
    #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
        if ( CAN_43_FLEXCAN_STANDARD == ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdType))
        {
    #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
            u32IdMask = ((uint32)((uint32)(Can_43_FLEXCAN_pCurrentConfig->pFilterMasks[(pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdMaskIndex]) << 18U));
    #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
        }
        else
        {
            u32IdMask = ((uint32)(Can_43_FLEXCAN_pCurrentConfig->pFilterMasks[(pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdMaskIndex]));
        }
    #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
    }

    if((u8MbCtrlIndex != FLEXCAN_MB_14_U8) && (u8MbCtrlIndex != FLEXCAN_MB_15_U8) && ((boolean)FALSE == (*pRxglobalMskFlag)))
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_RXGMASK(u8HwOffset), u32IdMask);
        *pRxglobalMskFlag = (boolean)TRUE;
    }
    else if(FLEXCAN_MB_14_U8 == u8MbCtrlIndex)
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_RX14MASK(u8HwOffset), (u32IdMask & FLEXCAN_RX14MASK_CONFIG_MASK_U32));
    }
    else if(FLEXCAN_MB_15_U8 == u8MbCtrlIndex)
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_RX15MASK(u8HwOffset), (u32IdMask & FLEXCAN_RX15MASK_CONFIG_MASK_U32));
    }
    else
    {
        /* Already the  RX Global MASK register is updated, its used as acceptance mask for all Rx MBs except for 14 and 15 MB's*/
    }
}
#endif /* CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON */

/*================================================================================================*/
/**
* @brief          Initialize Filter Individual Mask for Receive Message buffer
* @details        Initialize Filter Individual Mask for Receive Message buffer
*
*                 This routine is called by:
*                  - Can_FlexCan_InitReceiveMBs()
*
* @param[in]      + u16MBGlobalIndex: Index of MB in the MBs' information structure to process.
*                 + u8HwOffset: The hardware offset for this controller.
*
*/
static FUNC (void, CAN_CODE) Can_FlexCan_InitRxInvidualMask( VAR(uint16, AUTOMATIC) u16MBGlobalIndex, VAR(uint8, AUTOMATIC) u8HwOffset)
{
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    /* Variable for indexing the MBs inside a single controller. */
    VAR(uint8, AUTOMATIC)             u8MbCtrlIndex = 0U;

    /* Pointer to the MB container structure. */
    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);
    /* Get the index of Hardware Message Buffer */
    u8MbCtrlIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;

    if(CAN_43_FLEXCAN_MAXMASKCOUNT ==((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdMaskIndex))
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_RXIMR((u8HwOffset), (uint32)(u8MbCtrlIndex)), (uint32)(FLEXCAN_NO_MASK_U32));
    }
    else
    {
    #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
        if ( CAN_43_FLEXCAN_STANDARD == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdType)
        {
    #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32(FLEXCAN_RXIMR((u8HwOffset), (uint32)(u8MbCtrlIndex)), (uint32)((uint32)(Can_43_FLEXCAN_pCurrentConfig->pFilterMasks)[(pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdMaskIndex] << 18U));
    #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
        }
        else
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32(FLEXCAN_RXIMR((u8HwOffset), (uint32)(u8MbCtrlIndex)), (uint32)(Can_43_FLEXCAN_pCurrentConfig->pFilterMasks)[(pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdMaskIndex]);
        }
    #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
    }
}

/*================================================================================================*/
/**
* @brief          Service for Receive Message buffer initialization in the Can_FlexCan_InitController function
* @details        Service for Receive Message buffer initialization in the Can_FlexCan_InitController function
*
*                 This routine is called by:
*                  - Can_FlexCan_InitController()
*
* @param[in]      + Controller: CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*                 + u8HwOffset: The hardware offset for this controller.
*
*/
static FUNC (void, CAN_CODE) Can_FlexCan_InitReceiveMBs( VAR(uint8, AUTOMATIC) Controller, VAR(uint8, AUTOMATIC) u8HwOffset )
{
#if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) || (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON))
    /* Local copy of pointer to the controller descriptor. */
    VAR(Can_PtrControlerDescriptorType, AUTOMATIC) pCanControlerDescriptor = NULL_PTR;
#endif/* ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) || (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)) */
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    /* Variable for indexing all the MBs fron hardware unit chain (all controllers). */
    VAR(uint16, AUTOMATIC)            u16MBGlobalIndex = 0U;
    /* ID of current MB. */
    VAR(uint32, AUTOMATIC)            u32MbMessageId = 0U;
    /* Temporary register value. */
    VAR(uint32, AUTOMATIC)            u32MbConfig = 0U;
    /* Variable for indexing the MBs inside a single controller. */
    VAR(uint8, AUTOMATIC)             u8MbCtrlIndex = 0U;
#if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
    /* The Flag prevent to set value to Global Mask many time */
    static VAR(boolean, AUTOMATIC) bRxglobalMskFlag = (boolean)FALSE;
#endif

#if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) || (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON))
    /* Fill the local pointer copy with address of the Controller Descriptor.  */
    pCanControlerDescriptor = &(Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller]);
#endif /* ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) || (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)) */

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Parse all MBs that are of type RECEIVE from the chain list, but process only the MBs for controller transmitted as parameter in this function. */
    for (u16MBGlobalIndex = 0U; u16MBGlobalIndex < (uint16)Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex; u16MBGlobalIndex++)
    {
        /* u16MBGlobalIndex variable is incrementing based of existing HOH for MBs. */
        if ( Controller == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId)
        {
            u8MbCtrlIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;

        #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
            /* Skip the MB configuration if FIFO is enabled and this is the FIRST RX MB configured . */
            if ( ((CAN_CONTROLLERCONFIG_RXFIFO_U32 != (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_RXFIFO_U32)) ||
                 (u8MbCtrlIndex != (uint8)0U)) &&
                 (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].u16MBOffsetAddr != FLEXCAN_ENHANCED_RXFIFO_OFFSET_U16)
               )
            {
        #endif /* CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON */
            #if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
                /* Check if BCC support is enabled in configuration */
                if ( CAN_CONTROLLERCONFIG_BCC_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_BCC_EN_U32) )
                {
                    Can_FlexCan_InitRxGlobalMask( u16MBGlobalIndex, u8HwOffset, &bRxglobalMskFlag);
                }
                else
                {
            #endif /* CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON */

                    Can_FlexCan_InitRxInvidualMask( u16MBGlobalIndex, u8HwOffset);

            #if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
                }
            #endif /* CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON */

                /* Get the ID of the current MB. */
                u32MbMessageId = (uint32)((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uMessageId);

                /* Clear variable for every MB. */
                u32MbConfig = (uint32)0U;

            #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
                if (CAN_43_FLEXCAN_STANDARD == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).uIdType)
                {
            #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
                    /* Copy the Message ID (serves as acceptance filter for Rx MBs). For Standard type, ID is placed on bits 28:18 on ID Reg of the MB structure. */
                    u32MbMessageId <<= FLEXCAN_STANDARD_ID_SHIFT_U32;
            #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
                }
                else
                {
                    /* Set the IDE bit if the ID type is EXTENDED or MIXED. */
                    u32MbConfig = FLEXCAN_MBCS_IDE_U32 ;
                   /* For EXTENDED MB type the ID is placed starting from bits 0 ( unlike STANDARD type when is placed starting to bit 18). */
                }
            #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */

                /* Enable the MB as a Rx object. MB is used for Rx & Mark the buffer as empty. */
                u32MbConfig |= (FLEXCAN_MBCS_CODERXEMPTY_U32);
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)(u32MbConfig));
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)((u32MbMessageId) | ((REG_READ32(FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)))) & 0xE0000000U)));

                if ((boolean)TRUE != pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].CanHwObjectUsesPolling)
                {
                    Can_43_FLEXCAN_ControllerStatuses[Controller].u32MBInterruptMask[(uint8)((uint8)u8MbCtrlIndex >> FLEXCAN_MB_SHIFT5BIT_U8)] |= ((uint32)1U << (uint8)(u8MbCtrlIndex & FLEXCAN_MASK_32BITS_U32));
                }
                
        #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
            }
        #endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) */
        }
    }
}

/*================================================================================================*/
/**
* @brief          Service for Transmit Message buffer initialization in the Can_FlexCan_InitController function
* @details        Service for Transmit Message buffer initialization in the Can_FlexCan_InitController function
*
*                 This routine is called by:
*                  - Can_FlexCan_InitController()
*
* @param[in]      + Controller: CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*                 + u8HwOffset: The hardware offset for this controller.
*
*/
static FUNC (void, CAN_CODE) Can_FlexCan_InitTransmitMBs( VAR(uint8, AUTOMATIC) Controller, VAR(uint8, AUTOMATIC) u8HwOffset )
{
    /* Local copy of pointer to the controller descriptor. */
    VAR(Can_PtrControlerDescriptorType, AUTOMATIC) pCanControlerDescriptor = NULL_PTR;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    /* Variable for indexing all the MBs fron hardware unit chain (all controllers). */
    VAR(uint16, AUTOMATIC)            u16MBGlobalIndex = 0U;
    /* ID of current MB. */
    VAR(uint32, AUTOMATIC)            u32MbMessageId = 0U;
    /* Variable for indexing the MBs inside a single controller. */
    VAR(uint8, AUTOMATIC)             u8MbCtrlIndex = 0U;

    /* Fill the local pointer copy with address of the Controller Descriptor.  */
    pCanControlerDescriptor = &(Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller]);
    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Parse all MBs that are of type TRANSMIT from the chain list, but process only the MBs for controller transmitted as parameter in this function. */
    for (u16MBGlobalIndex = (uint16)Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex; u16MBGlobalIndex < (uint16)pCanMbConfigContainer->uMessageBufferConfigCount; u16MBGlobalIndex++)
    {
        /* u16MBGlobalIndex variable is incrementing based of existing HOH for MBs. */
        if ( Controller == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId)
        {
            /* Enable the MB as an TX object. MB is used for Tx & SRR must be set for Tx buffers. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)(FLEXCAN_MBCS_CODETX_U32 | FLEXCAN_MBCS_SRR_U32));

            /* Configure only PRIO field of MBCS register of every Tx MB. */
            if ( CAN_CONTROLLERCONFIG_LPRIO_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_LPRIO_EN_U32) )
            {
                u32MbMessageId = (uint32)((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8LocalPriority) << FLEXCAN_MB_ID_PRIO_SHIFT_U32 ;
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)(u32MbMessageId | ((REG_READ32(FLEXCAN_MB_ID(u8HwOffset, (uint32)(u16MBGlobalIndex)))) & 0xE0000000U)));

            }
            if ((boolean)TRUE != pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].CanHwObjectUsesPolling)
            {
                u8MbCtrlIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;
                Can_43_FLEXCAN_ControllerStatuses[Controller].u32MBInterruptMask[(u8MbCtrlIndex >> FLEXCAN_MB_SHIFT5BIT_U8)] |= ((uint32)1U << (uint8)(u8MbCtrlIndex & FLEXCAN_MASK_32BITS_U32));
            }
        }
    }
}

/*================================================================================================*/
/**
* @brief          Service to Perform software triggered state transitions of the CAN controller State machine.
* @details        Transition controller to Stop state/mode.
*
*                 This routine is called by:
*                  - Can_FlexCan_SetControllerMode()
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
* @param[in]      Transition Possible transitions
*
* @return         Std_ReturnType
* @retval         E_OK transition initiated
* @retval         E_NOT_OK development or production error
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerToStopMode(  VAR(uint8, AUTOMATIC) Controller,
                                                                            P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor,
                                                                            VAR(boolean, AUTOMATIC) canif_notification_required
                                                                          )
{
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = E_NOT_OK;
    VAR(uint16, AUTOMATIC)          u16MBGlobalIndex = 0U;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    /* Temporary variable for MB config register. */
    VAR(uint32, AUTOMATIC)          u32MbConfig = 0U;
#if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
    /*Temporary variable verify Rx FIFO is enabled or no*/
    VAR(boolean, AUTOMATIC) bFifoMB = (boolean)FALSE;
#endif

    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8ControllerOffset;

    /*
       (PR-MCAL-3057) The Can driver shall not create a development error if the CanIf requests a transision to a state that was already reached.
    */
    if ( CAN_CS_STOPPED == Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState)
    {
        /* If the controller is already in STOP state, return E_OK. */
        eReturnValue = E_OK;
    }
    else
    {
        /* Transit Controller state STARTED to STOPPED*/
        if ( CAN_CS_STARTED == Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState)
        {
            /*
              (SWS_Can_00263) The function Can_SetControllerMode(CAN_CS_STOPPED) shall set the bits inside the CAN hardware such that the CAN controller
                       stops participating on the network.
            */

            if ((Std_ReturnType)E_OK == Can_FlexCan_GotoFreezeMode(u8HwOffset))
            {
                /* Check if Software BusOff Recovery is enabled. */
                if ( CAN_CONTROLLERCONFIG_BUSOFFSWREC_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_BUSOFFSWREC_U32) )
                {
                    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_06();
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_BIT_CLEAR32( FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_BOFFREC_U32);
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_BIT_SET32( FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_BOFFREC_U32);
                    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_06();
                }
            /*if Rx FIFO is enabled.*/
            #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
                #if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
                if(CAN_CONTROLLERCONFIG_RXFIFO_U32 == ((Can_43_FLEXCAN_pControlerDescriptors[Controller].u32Options) & CAN_CONTROLLERCONFIG_RXFIFO_U32))
                {
                    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_06();
                    /*Clear flags for FIFO before delete content of FIFO*/
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_BIT_SET32( FLEXCAN_IFLAG1(u8HwOffset), (FLEXCAN_FIFO_OVERFLOW_INT_MASK_U32|FLEXCAN_FIFO_WARNING_INT_MASK_U32|FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32));
                    /*When this bit was trigged, the FIFO content was cleared*/
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_BIT_SET32( FLEXCAN_IFLAG1(u8HwOffset), FLEXCAN_IFLAG1_BUF0I_U32);
                    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_06();
                    bFifoMB = (boolean)TRUE;
                }
                #endif
                #if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
                if (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32 == ((Can_43_FLEXCAN_pControlerDescriptors[Controller].u32Options) & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32))
                {
                    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_06();
                     /*Clear EFRSR[ERFUFW], EFRSR[ERFOVF], EFRSR[ERFWMI], and EFRSR[ERFDA], if they are set and reset Enhanced Rx FIFO engine. */
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32(FLEXCAN_ERFSR(u8HwOffset), (FLEXCAN_ERFSR_ERFUFW_U32 | FLEXCAN_ERFSR_ERFOVF_U32 | FLEXCAN_ERFSR_ERFWMI_U32 | FLEXCAN_ERFSR_ERFDA_U32 | FLEXCAN_ERFSR_ERFCLR_U32));
                    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_06();
                    bFifoMB = (boolean)TRUE;
                }
                #endif
            #endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) */
                /* Loop through all MBs. -> Cancel pending messages. */
                for ( u16MBGlobalIndex = 0U; u16MBGlobalIndex < Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; u16MBGlobalIndex++)
                {
                    if  ( Controller == (Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId)
                    {
                      #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
                        if ((boolean)FALSE == bFifoMB)
                        {
                      #endif
                            /*
                            (SWS_Can_00282) The function Can_SetControllerMode(CAN_CS_STOPPED) shall cancel pending messages.
                            (SWS_Can_00273)After bus-off detection, the Can module shall cancel still pending messages without raising a cancellation notification.
                            */
                            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                            u32MbConfig = ( ((uint32)REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex))) & ~FLEXCAN_MBCS_CODE_U32) | FLEXCAN_MBCS_CODETX_U32 );
                            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                            REG_WRITE32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)(u32MbConfig));
                      #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
                        }
                        else
                        {
                            bFifoMB = (boolean)FALSE;
                        }
                      #endif
                    }
                }
                /*
                The Can module shall track all individual enabling and disabling of  interrupts
                    in other functions (i.e. Can_SetControllerMode), so that the correct interrupt enable state can be restored.
                When Freeze mode (or Autosar equiv Stop mode) need to not participate on network ->
                    no interrupt is required to be enabled.
                */
                /* Check if Ints are enabled by Can_EnableControllerInterrupts. */
                if ( CAN_FLEXCAN_INTERRUPT_ENABLED == Can_43_FLEXCAN_ControllerStatuses[Controller].eInterruptMode )
                {
                    Can_FlexCan_DisableInterrupts(Controller);
                }

                eReturnValue = E_OK;
            }
        }
        else
        {
           /* Transit Controller state SLEEP to STOPPED*/
            if (CAN_CS_SLEEP == Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState)
            {
                /* When Wakeup is not supported the driver should do nothing and return E_OK. */
                eReturnValue = E_OK;
            }
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
            else
            {
                (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_43_FLEXCAN_E_TRANSITION);
            }
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */

        }
    }

    if ((Std_ReturnType)E_OK == eReturnValue)
    {
#if (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
    /* [SWS_CAN_00499] The CAN driver shall deactivate Pretended Networking before the CAN Controller is stopped by SetControllerMode(CAN_CS_STOPPED). */
        REG_WRITE32(FLEXCAN_MCR(u8HwOffset), ((~FLEXCAN_PNET_ENABLE_U32) & REG_READ32 (FLEXCAN_MCR(u8HwOffset))));
        Can_43_FLEXCAN_ControllerStatuses[Controller].eCanIcomState = CAN_FLEXCAN_ICOM_DEACTIVATED;
#endif
        /* Set the Stop state to the controller. */
        Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState = CAN_CS_STOPPED;
        /*Do not notify CanIf for bus off events*/
        if((boolean)TRUE == canif_notification_required)
        {
            CanIf_ControllerModeIndication(Controller, CANIF_CS_STOPPED);
        }
    }

    return eReturnValue;
}

/*================================================================================================*/
/**
* @brief          Service to Perform software triggered state transitions of the CAN controller State machine.
* @details        Transition controller to Start state/mode.
*
*                 This routine is called by:
*                  - Can_FlexCan_SetControllerMode()
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
*
* @return         Std_ReturnType
* @retval         E_OK transition initiated
* @retval         E_NOT_OK development or production error
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerToStartMode(  VAR(uint8, AUTOMATIC) Controller,
                                                                            P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor
                                                                          )
{
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = E_NOT_OK;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    /* Timeout counter. */
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif
    VAR(uint32, AUTOMATIC)          u32TempVar = 0U;

    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8ControllerOffset;

#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
    /* Valid transitions to Start mode are only from Stop state. */
    if ( CAN_CS_STOPPED != Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState)
    {

        (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_43_FLEXCAN_E_TRANSITION);
    }
    else
    {
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */

        /* (SWS_Can_00384) Each time the CAN controller state machine is triggered with the state transition value CAN_CS_STARTED, the function
        Can_SetControllerMode shall re-initialize the CAN controller with the same controller configuration set previously used by functions
        Can_ChangeBaudrate or Can_Init.*/
        if ((Std_ReturnType)E_OK == Can_FlexCan_InitController( Controller))
        {

#if (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
        /* [SWS_CAN_00498] The CAN driver shall deactivate Pretended Networking before the CAN Controller is started by SetControllerMode(CAN_CS_STARTED) */
        u32TempVar = REG_READ32 (FLEXCAN_MCR(u8HwOffset));
        if(FLEXCAN_PNET_ENABLE_U32 != (FLEXCAN_PNET_ENABLE_U32 & u32TempVar))
        {
            REG_WRITE32(FLEXCAN_MCR(u8HwOffset), ((~FLEXCAN_PNET_ENABLE_U32) & u32TempVar));
            Can_43_FLEXCAN_ControllerStatuses[Controller].eCanIcomState = CAN_FLEXCAN_ICOM_DEACTIVATED;
        }
#endif
            /*
            (SWS_Can_00261) The function Can_SetControllerMode(CAN_CS_STARTED) shall set the hardware registers in a way that makes the CAN controller participating on the network.
            */
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_13();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);
            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_13();

            /*
            (SWS_Can_00196) The function Can_SetControllerMode shall enable interrupts that are needed in the new state.
            (SWS_Can_00425)   Enabling of CAN interrupts shall not be executed, when CAN interrupts have been disabled by function CAN_DisableControllerInterrupts.
             */

            if ( CAN_FLEXCAN_INTERRUPT_ENABLED == Can_43_FLEXCAN_ControllerStatuses[Controller].eInterruptMode )
            {
                Can_FlexCan_EnableInterrupts(Controller, pCanControlerDescriptor);
            }

            /* (SWS_Can_00262) The function Can_SetControllerMode(CAN_CS_STARTED) shall wait for limited time until the CAN controller is fully operational. Compare to SWS_Can_00398. */
            u32TotalElapsedTime = 0U;
        #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
        #endif
            u32TempVar = (uint32)0U;
            do
            {
            #ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
                u32TotalElapsedTime++;
            #else
                (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
                u32TotalElapsedTime += u32ElapsedTime;
            #endif
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                u32TempVar = ( (uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & (FLEXCAN_MCR_FRZ_U32 | FLEXCAN_MCR_HALT_U32 | FLEXCAN_MCR_NOTRDY_U32));
            } while ((u32TotalElapsedTime < Can_u32TicksDelayDuration) && ( 0x0U != u32TempVar));

            if ((uint32)0x0U == u32TempVar)
            {
                /* Set the Start State. */
                Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState = CAN_CS_STARTED;
                eReturnValue = E_OK;
            }
            else
            /* software timeout */
            {
                eReturnValue = E_NOT_OK;
            }
        }
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
    }
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */
    if ((Std_ReturnType)E_OK == eReturnValue)
    {
        CanIf_ControllerModeIndication(Controller, CANIF_CS_STARTED);
    }

    return eReturnValue;
}

/*================================================================================================*/
/**
* @brief          Service to Perform software triggered state transitions of the CAN controller State machine.
* @details        Transition controller to Sleep state/mode.
*
*                 This routine is called by:
*                  - Can_FlexCan_SetControllerMode()
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @return         Std_ReturnType
* @retval         E_OK transition initiated
* @retval         E_NOT_OK development or production error
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerToSleepMode(  VAR(uint8, AUTOMATIC) Controller )
{
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = E_NOT_OK;

    /*
       (PR-MCAL-3057) The Can driver shall not create a development error if the CanIf requests a transision to a state that was already reached.
    */
    if ( CAN_CS_SLEEP == Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState )
    {
        /* If the controller is already in SLEEP state, return E_OK. */
        eReturnValue = E_OK;
    }
    else
    {

#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
        /* Valid transitions to Sleep state are only from Stop state. */
        if ( CAN_CS_STOPPED != Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState)
        {

            (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_43_FLEXCAN_E_TRANSITION);
        }
        else
        {
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */
            /*[SWS_Can_00290]If the CAN HW does not support a sleep mode, the function Can_SetControllerMode(CAN_CS_SLEEP) shall set the CAN controller to the logical sleep mode*/
            /*[SWS_Can_00405] This logical sleep mode shall left only, if function Can_SetControllerMode(CAN_CS_WAKEUP) is called.*/
            eReturnValue = E_OK;
            Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState = CAN_CS_SLEEP;
            CanIf_ControllerModeIndication(Controller, CANIF_CS_SLEEP);
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
        }
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */
    }
    return eReturnValue;
}

/*================================================================================================*/
/**
* @brief          Service to write data into the Message buffer for transition
* @details        This routine is used in case enabled FD feature.
*
*                 This routine is called by:
*                  - Can_FlexCan_Write()
*
* @param[in]     u8CtrlId - The ID of Can controller
*                u16MBGlobalIndex - The index of HOH in the structure array which stores the information of configured HOHs
*                PduInfo - Pointer to SDU user memory, DLC and Identifier
*                bEnabledFD - Be TRUE if CAN FD is enabled, otherwise it is FALSE
*
* @return         Std_ReturnType
* @retval         E_OK transition initiated
* @retval         E_NOT_OK development or production error
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_UpdateMB( VAR(uint8, AUTOMATIC) u8CtrlId, VAR(uint16, AUTOMATIC) u16MBGlobalIndex ,
                                                                P2CONST(Can_PduType, AUTOMATIC, CAN_APPL_CONST) PduInfo, VAR(boolean, AUTOMATIC) bEnabledFD
                                                            )
{
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Variable for determining the IFLAG register for every MB: IFLAGx */
    VAR(uint8, AUTOMATIC)          u8IflagRegIndex = 0U;
    /* Variable for determining the mash bit in the IFLAGx register for current MB. */
    VAR(uint32, AUTOMATIC)         u32TempFlag = 0U;
    /* Variable for storing the value of IFLAG register. */
    VAR(uint32, AUTOMATIC)         u32IflagReg = 0U;
    /* Variable for byte index of the MB data. */
    VAR(uint8, AUTOMATIC)          u8MbDataByte = 0U;
    /* Variable for storing the ID of the MB from MB structure. */
    VAR(uint32, AUTOMATIC)         u32MbMessageId = 0U;
#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    /*Can_Flexcan_aDataLengthMax, Can_Flexcan_aDataLengthMin, Can_Flexcan_aDataLengthMax index counter*/
    VAR(uint8, AUTOMATIC)          u8DataLengthCount = 0U;
    /* The length of data which will be filled in MB */
    VAR(uint8, AUTOMATIC)          u8RealDataLength = (uint8)8U;
#endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */
    /* Variable for storing the ConfigReg of the MB. */
    VAR(uint32, AUTOMATIC)         u32MbConfig = 0U;
    /* DLC offset value is 16*/
    CONST(uint8, AUTOMATIC)        u8DataLengthOffset =16U;
    VAR(uint8, AUTOMATIC)          u8MbIndex;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    #if (CAN_43_FLEXCAN_TRIGGER_TRANSMIT_EN == STD_ON)
    static VAR(PduInfoType, AUTOMATIC) PduInfoPtr;
    VAR(PduIdType, CAN_VAR) TxPduId;
    #endif

    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)          u8HwOffset = 0U;

    /* Get the hardware offset for this controller. Note that hardware offset may not be the same with the controller index from the 'Can_43_FLEXCAN_ControlerDescriptorType' structure. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u8ControllerOffset;

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);
    u8MbIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;
    /* Calculate the index of the IFLAG register and u32TxGuard (index=0 for MB32...MB63, index=1 for MB0...MB31, index=2 for MBO64 ... 96). */
    u8IflagRegIndex = u8MbIndex >> FLEXCAN_MB_SHIFT5BIT_U8;
    /* Get the content of IFLAG register for which corresponds this MB. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    u32IflagReg = REG_READ32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag);

    /* Calculate the bit in the IFLAG register. */
    u32TempFlag = ((uint32)0x01U) << ((uint32)u8MbIndex & FLEXCAN_MASK_32BITS_U32);

    /* This MB is not signaled as used by another message. */
    if ( (uint32)0x0U == (u32IflagReg & u32TempFlag) )
    {
        /* Is the MB still empty? */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        if ( FLEXCAN_MBCS_CODETX_U32 == (uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32)))
        {
            u32MbMessageId = (uint32)PduInfo->id;
            u32MbConfig = (FLEXCAN_MBCS_CODETX_U32 | FLEXCAN_MBCS_CODETXEN_U32 | FLEXCAN_MBCS_SRR_U32 );

        #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
            if   (((uint8)PduInfo->length)<=(uint8)Can_Flexcan_aDataLengthMax[0])
            {
        #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */
                u32MbConfig |= ((uint32)PduInfo->length<<(uint32)u8DataLengthOffset);
        #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                u8RealDataLength = (uint8)PduInfo->length;
            }
            else
            {
                /* @violates @ref Can_Flexcan_c_REF_9 MISRA 2012 Required Rule 14.3 */
                if ((((uint32)PduInfo->id) & (uint32)CAN_FD_ID_DESCRIPTOR) == CAN_FD_ID_DESCRIPTOR )
                {
                    for (u8DataLengthCount=1U; u8DataLengthCount<CAN_FLEXCAN_NUM_VAL_DLC_U8; u8DataLengthCount++)
                    {
                        if ((((uint8)PduInfo->length)<=(uint8)Can_Flexcan_aDataLengthMax[u8DataLengthCount])&&(((uint8)PduInfo->length)>=(uint8)Can_Flexcan_aDataLengthMin[u8DataLengthCount]))
                        {
                            u32MbConfig |= ((uint32)((uint32)CAN_FLEXCAN_MAX_PAYLOAD8_U8+(uint32)u8DataLengthCount)<<((uint32)u8DataLengthOffset));
                            u8RealDataLength = (uint8)Can_Flexcan_aDataLengthMax[u8DataLengthCount];
                        }
                    }

                }
                /* else{ Development error detection from upper layer} */
            }

            if ((boolean)TRUE == bEnabledFD)
            {
                /*check to see if CanIf bit send from the user enables FD*/
                /* @violates @ref Can_Flexcan_c_REF_9 MISRA 2012 Required Rule 14.3 */
                if ((((uint32)PduInfo->id) & (uint32)CAN_FD_ID_DESCRIPTOR) == CAN_FD_ID_DESCRIPTOR )
                {

                    u32MbConfig |= FLEXCAN_MB_EDL_BRS_U32;

                }
            }
        #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */


            /* Set-up the MB content for Tx. Remember the PduId for reporting when the frame is transmitted. */
            Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].u32TxPduId[u8MbIndex] = PduInfo->swPduHandle;

        #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
            if ( (u32MbMessageId & FLEXCAN_MBC_ID_IDE_U32) != (uint32)0U)
            {
                /* Set the IDE bit in the MBCS register of the MB */
                u32MbConfig |= FLEXCAN_MBCS_IDE_U32;
                /* Clear the MSB bit of the id - this is used for sending embedded information by CanIf to Can to say if it is an extended or standard message type. */
                u32MbMessageId &= (~FLEXCAN_MBC_ID_IDE_U32);
            }
            else
            {
        #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
                /* Standard ID - need to shift left 18 bits. */
            u32MbMessageId <<= FLEXCAN_STANDARD_ID_SHIFT_U32;
        #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
            }
        #endif /* (CAN_43_FLEXCAN_EXTENDEDID == STD_ON) */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)((u32MbMessageId) | ((REG_READ32(FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)))) & 0xE0000000U) ));

        #if (CAN_43_FLEXCAN_TRIGGER_TRANSMIT_EN == STD_ON)
            if ( (NULL_PTR == PduInfo->sdu) )
            {
                if((boolean)TRUE == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].CanTriggerTransmitEnable)
                {
                    /* this MB enable the trigger transmit feature */
                    /* [SWS_CAN_00503] Can_Write() shall accept a null pointer as SDU
                            (Can_PduType.Can_SduPtrType = NULL) if the trigger transmit API is enabled
                            for this hardware object (CanTriggerTransmitEnable = TRUE). */
                    /* [SWS_CAN_00504] If the trigger transmit API is enabled for the hardware object, Can_Write() shall interpret a null pointer as SDU
                                (Can_PduType.Can_SduPtrType = NULL) as request for using the trigger transmit interface.
                                   If so and the hardware object is free, Can_Write() shall call CanIf_TriggerTransmit() to acquire the PDU’s data. */
                    TxPduId = PduInfo->swPduHandle;
                    PduInfoPtr.SduLength = (Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength;
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    PduInfoPtr.SduDataPtr = (uint8 *)((pointerSizeType)(CAN_GET_BASE_ADDRESS(u8HwOffset)) + (uint32)(FLEXCAN_MB_OFFSET(u16MBGlobalIndex)) + 0x08U);
                    if((Std_ReturnType)E_OK == CanIf_TriggerTransmit(TxPduId, &PduInfoPtr))
                    {
                        /* return value is OK */
                        if((Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength >= (uint32)PduInfoPtr.SduLength)
                        {
                            u32MbConfig = u32MbConfig & FLEXCAN_REMOVE_DLC_U8;
                        #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                            if(((uint8)PduInfoPtr.SduLength)<=(uint8)Can_Flexcan_aDataLengthMax[0])
                            {
                        #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */
                                u32MbConfig |= ((uint32)PduInfoPtr.SduLength<<(uint32)u8DataLengthOffset);
                        #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                                u8RealDataLength = (uint8)PduInfoPtr.SduLength;
                            }
                            else
                            {
                                for (u8DataLengthCount=1U; u8DataLengthCount<CAN_FLEXCAN_NUM_VAL_DLC_U8; u8DataLengthCount++)
                                {
                                    if ((((uint8)PduInfoPtr.SduLength)<=(uint8)Can_Flexcan_aDataLengthMax[u8DataLengthCount])&&(((uint8)PduInfoPtr.SduLength)>=(uint8)Can_Flexcan_aDataLengthMin[u8DataLengthCount]))
                                    {
                                        u32MbConfig |= ((uint32)((uint32)CAN_FLEXCAN_MAX_PAYLOAD8_U8+(uint32)u8DataLengthCount)<<((uint32)u8DataLengthOffset));
                                        u8RealDataLength = (uint8)Can_Flexcan_aDataLengthMax[u8DataLengthCount];
                                    }
                                }
                            }

                            if ((boolean)TRUE == bEnabledFD)
                            {
                                for ( u8MbDataByte = (uint8)PduInfoPtr.SduLength; u8MbDataByte < u8RealDataLength; u8MbDataByte++)
                                {
                                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                                    REG_WRITE8(FLEXCAN_MB_DATA((u8HwOffset), (uint32)(u16MBGlobalIndex), (uint32)(u8MbDataByte)), (uint8)(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u8MbIndex].u8FdPaddingValue));
                                }
                            }
                        #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */

                            eReturnValue = E_OK;
                        }
                        else
                        {
                            eReturnValue = E_NOT_OK;
                        }
                    }
                    else /* return value is NOT_OK */
                    {
                        /* [SWS_CAN_00506] If development error detection for CanDrv is enabled:
                            Can_Write() shall return E_NOT_OK if the trigger transmit API CanIf_TriggerTransmit()) returns E_NOT_OK. */
                        eReturnValue = E_NOT_OK;
                    }
                }
                else /* this MB do not enable the trigger transmit feature */
                {
                    /* [SWS_CAN_00505] If development error detection for CanDrv is enabled:
                        Can_Write() shall raise CAN_43_FLEXCAN_E_PARAM_POINTER and shall return E_NOT_OK if
                        the trigger transmit API is disabled for this hardware object
                        (CanTriggerTransmitEnable = FALSE) and the SDU pointer inside PduInfo is a null
                        pointer. */
                        #if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
                            (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_WRITE, CAN_43_FLEXCAN_E_PARAM_POINTER);
                        #endif
                        eReturnValue = E_NOT_OK;
                }
            }
            else /* sdu pointer is not null */
            {
        #endif
                /* Copy the data into the MB memory. The driver will not read from a null pointer SDU. */
                for ( u8MbDataByte = (uint8)0U; u8MbDataByte < PduInfo->length; u8MbDataByte++)
                {
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE8(FLEXCAN_MB_DATA((uint32)(u8HwOffset), (uint32)(u16MBGlobalIndex), (uint32)(u8MbDataByte)), (uint8)((PduInfo->sdu)[u8MbDataByte]));
                }

            #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                if ((boolean)TRUE == bEnabledFD)
                {
                    for ( u8MbDataByte = PduInfo->length; u8MbDataByte < u8RealDataLength ; u8MbDataByte++)
                    {
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        REG_WRITE8(FLEXCAN_MB_DATA((u8HwOffset), (uint32)(u16MBGlobalIndex), (uint32)(u8MbDataByte)), (uint8)(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u8FdPaddingValue));
                    }
                }
            #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */

        #if (CAN_43_FLEXCAN_TRIGGER_TRANSMIT_EN == STD_ON)
            }
            if ((Std_ReturnType)E_NOT_OK != eReturnValue)
            {
        #endif

                /* Transmit the Data - now the data should be on Can Bus. Configure the DLC. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)(u32MbConfig));
                eReturnValue = E_OK;
        #if (CAN_43_FLEXCAN_TRIGGER_TRANSMIT_EN == STD_ON)
            }
        #endif
        }
        else
        /* MB not empty anymore, preempting code has grabbed it before we managed to set the guard bit. Clear the guard bit. */
        {
            /*
               (CAN213) The function Can_Write shall perform no actions if the hardware transmit object is busy with another transmit request for an L-PDU that has higher priority than that for the current request:
                  - The transmission of the L-PDU with higher priority shall not be cancelled and the function Can_Write is left without any actions.
                  - The function Can_Write shall return CAN_BUSY.
            */
            /* MB not TX empty anymore, preempting code has grabbed it before we managed to set the guard bit. Clear the guard, end of critical section. */
            eReturnValue = (Std_ReturnType)CAN_BUSY;
        }
    }
    else /* else of "if((uint32)0x0U==(u32IflagReg&u32TempFlag))" */
    /* MB is locked because it has the IFLAG bit set. */
    {
        /*
        The fact that the return value of the function is the same irrespective of whether the MB is locked out or busy with a lower prio message is a deficiency in the AutoSAR spec.
        CanIf has no way of telling whether the message was cancelled or not in the special case and a priority inversion can occur.
        */
        /*
           (CAN214) The function Can_Write shall return CAN_BUSY if a preemptive call of Can_Write has been issued, that could not be
                    handled reentrant (i.e. a call with the same HTH).
        */
        eReturnValue = (Std_ReturnType)CAN_BUSY;
    }

    (void)bEnabledFD;   /* Prevent compiler warning when CAN_FD is disabled */
    return eReturnValue;
}


/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer during Can_MainFunction_Write if polling is selected.
* @details        Processes Tx interrupt flags.
*
*               This routine is called by:
*                   - Can_FlexCan_ProcessTx()
*                   - Can_FlexCan_MainFunctionWrite()
*
* @param[in]      controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      u16MBGlobalIndex MB in the MBs' information structure to process.
*
* @pre            MB is configured for Tx.
* @post           CanIf is informed with cancellation or transmit success.
*
*/
static FUNC (void, CAN_CODE) Can_FlexCan_ProcessTxPoll( CONST(uint8, AUTOMATIC) controller, CONST(uint16, AUTOMATIC) u16MBGlobalIndex )
{
    /* Pointer to the MBs structure configuration. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC) pCanMbConfigContainer = NULL_PTR;
    /* Variable for indexing the MBs. */
    VAR(uint8, AUTOMATIC)            u8MbIndex = 0U;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)            u8HwOffset = 0U;
    /* Variable for determining the IFLAG register for every MB: IFLAGx */
    VAR(uint8, AUTOMATIC)            u8IflagRegIndex = 0U;
    /* Variable for determining the mash bit in the IFLAGx register for current MB. */
    VAR(uint32, AUTOMATIC)           u32TempFlag = 0U;
    /* Variable for storing the value of IFLAG register. */
    VAR(uint32, AUTOMATIC)           u32IflagReg = 0U;
#if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
    VAR(uint32, AUTOMATIC) u32TimestanpValue;
    VAR(Can_HwHandleType, AUTOMATIC) Hoh;
#endif
#if (CAN_43_FLEXCAN_TXINT_SUPPORTED == STD_ON)
    /* Variable for storing the value of IMASKx register. */
    VAR(uint32, AUTOMATIC)           u32ImaskReg = 0U;
#endif
    /* Get the address of the MBConfigContainer in local pointer */
    pCanMbConfigContainer = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);
    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;

    u8MbIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;

    /* Calculate the index of the IFLAG/IMASK register. */
    u8IflagRegIndex = (uint8)((uint8)u8MbIndex >> FLEXCAN_MB_SHIFT5BIT_U8) ;

    /* Get the content of IFLAG register for which corresponds this MB. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    u32IflagReg = REG_READ32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag);

    /* Calculate the bit in the IFLAG/IMASK register allocated to a MB */
    u32TempFlag = ((uint32)0x01U) << ((uint32)u8MbIndex & FLEXCAN_MASK_32BITS_U32);
#ifndef ERR_IPV_FLEXCAN_0015
    /* Check the interrupt flag of the current MB. */
    if ( (uint32)0x0U != (u32IflagReg & u32TempFlag) )
    {
#endif
    #if (CAN_43_FLEXCAN_TXINT_SUPPORTED == STD_ON)
        /*Get the content of IMASK register for which corresponds this MB. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u32ImaskReg = REG_READ32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanImask);
        /* Check for spurious interrupt for a INTERRUPT Hardware object only. */
        if ((u32TempFlag == (u32ImaskReg & u32TempFlag)) || ((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanHwObjectUsesPolling))
        {
    #endif
        /* The interrupt flag is set, message was either transmitted or cancelled.
            This code does not check whether the u32TxGuard is set.
            It does not have to do the check as it only operates on MBs with the interrupt flag set and CanWrite does not
            operate on MBs which have the interrupt flag set.
            Set the u32TxGuard. */
        /*
            (SWS_Can_00031) The function Can_MainFunction_Write shall perform the polling of TX confirmation and TX cancellation confirmation when CanTxProcessing is set to POLLING.
        */

#ifdef ERR_IPV_FLEXCAN_0015
    #if(ERR_IPV_FLEXCAN_0015==STD_ON)
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        if  ( (((uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32))) == FLEXCAN_MBCS_CODETX_U32) && \
               ( 0U != ((((uint32)0x01U) << (uint32)u8MbIndex) &  Can_43_FLEXCAN_ControllerStatuses[controller].u32TxCancelFlag[u8IflagRegIndex] )) \
            )
        {
        #if (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_64_U8)
            Can_43_FLEXCAN_ControllerStatuses[controller].u32TxCancelFlag[u8IflagRegIndex] &= (PduIdType)(~(((uint32)0x01U) << ((uint32)u8MbIndex)));
        #else
            Can_43_FLEXCAN_ControllerStatuses[controller].u32TxCancelFlag[u8IflagRegIndex] &= ~(((uint32)0x01U) << ((uint32)u8MbIndex));
        #endif
    #else
         #error : the define ERR_IPV_FLEXCAN_0015 must not be STD_OFF
    #endif
#else
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            switch ( (uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32)) )
            {
#endif

    #ifdef ERR_IPV_FLEXCAN_0015
        #if(ERR_IPV_FLEXCAN_0015==STD_ON)
            }
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            else if((((uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32))) == FLEXCAN_MBCS_CODETX_U32) && ((uint32)0x0U != (u32IflagReg & u32TempFlag)))
        #else
            #error : the define ERR_IPV_FLEXCAN_0015 must not be STD_OFF
        #endif
    #else
                    /* Frame was transmitted */
                case ( FLEXCAN_MBCS_CODETX_U32 ):
    #endif
            {
                /* Clear the interrupt flag - w1c. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                REG_WRITE32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag, u32TempFlag);

                /*
                    (SWS_Can_00058) The Can module interacts among other modules (eg. Diagnostic Event Manager (DEM), Development Error Tracer (DET)) with the CanIf module in a direct way.
                            The driver only sees the CanIf module as origin and destination.
                */
                CanIf_TxConfirmation( Can_43_FLEXCAN_ControllerStatuses[controller].u32TxPduId[u8MbIndex]);
                
                #if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
                    if((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanTimestampEnable)
                    {
                        Hoh = (Can_HwHandleType)((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID);
                    #ifdef CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u32TimestanpValue = (REG_READ32( FLEXCAN_MB((u8HwOffset), (u16MBGlobalIndex)))) & CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_MASK_U32;
                    #endif
                    
                    #ifdef CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u32TimestanpValue = REG_READ32(FLEXCAN_HR_TIME_STAMP(u8HwOffset, u8MbIndex));
                    #endif
                        Can_43_FLEXCAN_pCurrentConfig->CanTxTimestampNotification(Hoh, Can_43_FLEXCAN_ControllerStatuses[controller].u32TxPduId[u8MbIndex], u32TimestanpValue);
                    }
                #endif
            }
    #ifdef ERR_IPV_FLEXCAN_0015
        #if(ERR_IPV_FLEXCAN_0015==STD_ON)
            else /* error condition, this should never occur */
            {
                /*This is left blank in oreder to respect MISRA */
            }
        #else
            #error : the define ERR_IPV_FLEXCAN_0015  not be STD_OFF
        #endif
    #else
                    break;
                default:
                {
                    break;
                }
            } /* end switch */
    #endif
    #if (CAN_43_FLEXCAN_TXINT_SUPPORTED == STD_ON)
        }
        else
        {
            /*Clear interrupt status flag when spurious interrupt is detected*/
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag, u32TempFlag);
        }
    #endif
#ifndef ERR_IPV_FLEXCAN_0015
    } /*if ( (uint32)0x0U != (u32IflagReg & u32TempFlag) )*/
#endif
}/*Can_FlexCan_ProcessTxPoll*/

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper during Can_MainFunction_Read if polling is selected and Rxfifo is disabled or doesn't supported.
* @details        Processes Rx interrupt flags.
                  This routine is called by:
                    - Can_FlexCan_ProcessRx() from Can_Flexcan.c file
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      u16MBGlobalIndex: index of MB to process in the struct which stores information of MBs
*
* @pre            MB is configured for Rx.
* @post           Inform CanIf in case a data frame was received.
*
*
*/
static FUNC (void, CAN_CODE) Can_FlexCan_ProcessRxNormal( CONST(uint8, AUTOMATIC) controller, CONST(uint16, AUTOMATIC) u16MBGlobalIndex )
{

    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif
    /* Variable for indexing the MBs. */
    VAR(Can_HwHandleType, AUTOMATIC)      u8MbIndex = 0U;
    /* Number of data bytes. */
    VAR(uint8, AUTOMATIC)      u8MbDataLength = 0U;
    /* Physical data bytes. */
#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    static VAR(uint8, AUTOMATIC)      u8CanMbData[64U];
#else
    static VAR(uint8, AUTOMATIC)      u8CanMbData[8U];
#endif
    /* Index for data byte of MB. */
    VAR(uint8, AUTOMATIC)      u8DatabyteIndex = 0U;
    /* Variable for storing the Hrh. */
    VAR(Can_HwHandleType, AUTOMATIC)      u32MbHrh = 0U;
    /* Variables for storing the CanID. */
    VAR(Can_IdType, AUTOMATIC) u32MbMessageId = 0U;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)      u8HwOffset = 0U;
    /* Variable for determining the IFLAG register for every MB: IFLAGx. */
    VAR(uint8, AUTOMATIC)      u8IflagRegIndex = 0U;
    /* Variable for determining the mash bit in the IFLAGx register for current MB. */
    VAR(uint32, AUTOMATIC)     u32TempFlag = 0U;
    /* Variable for storing the value of IFLAG register. */
    VAR(uint32, AUTOMATIC)     u32IflagReg = 0U;
    /* Variable for storing the ConfigReg of the MB. */
    VAR(uint32, AUTOMATIC)     u32MbConfig = 0U;

    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;

    /* Identifies the HRH and its corresponding CAN Con-troller. */
    static VAR(Can_HwType, AUTOMATIC) Mailbox;
    /* Pointer to the received L-PDU. */
    static VAR(PduInfoType, AUTOMATIC) PduInfoPtr;
#if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
    VAR(uint32, AUTOMATIC) u32TimestanpValue;
#endif
#if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
    /* Variable for storing the value of IMASKx register. */
    VAR(uint32, AUTOMATIC)           u32ImaskReg = 0U;
#endif

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    u8CanMbData[0U]=(uint8)0U;
    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;
    u8MbIndex = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;
    /* Calculate the Index of the IFLAG register. */
    u8IflagRegIndex = (uint8)((uint8)u8MbIndex >> FLEXCAN_MB_SHIFT5BIT_U8);

    /* Get the content of IFLAG register for which corresponds this MB. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    u32IflagReg = REG_READ32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag);

    /* Calculate the Flag value. */
    u32TempFlag = ((uint32)0x1U) << ((uint32)u8MbIndex & FLEXCAN_MASK_32BITS_U32);

    /* Check the interrupt flag. */
    if ( (uint32)0x0U != (u32IflagReg & u32TempFlag) )
    {
#if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
    /*Get the content of IMASK register for which corresponds this MB. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    u32ImaskReg = REG_READ32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanImask);
    /* Check for spurious interrupt for a INTERRUPT Hardware object only. */
    if ((u32TempFlag == (u32ImaskReg & u32TempFlag)) || ((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanHwObjectUsesPolling))
    {
#endif
        u32TotalElapsedTime = 0U;
    #ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
    #endif
        /*Check and wait if the BUSY code is set during the move-in process*/
        do
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32MbConfig = (uint32)REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)));
    #ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            u32TotalElapsedTime++;
    #else
            (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
            u32TotalElapsedTime += u32ElapsedTime;
    #endif
        }
        while ((FLEXCAN_MBCS_CODERXBUSY_U32 == (u32MbConfig & FLEXCAN_MBCS_CODERXBUSY_U32)) && (u32TotalElapsedTime < Can_u32TicksDelayDuration));

    #if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
        /* SWS_Can_00395: If the development error detection for the Can module is enabled, the Can module shall raise the error CAN_43_FLEXCAN_E_DATALOST in
                case of OVERWRITE or OVERRUN event detection.*/
        /* Check if a MBs used to receive data was overwrite */

        if(FLEXCAN_MBCS_CODERXOVRR_U32 == (u32MbConfig & FLEXCAN_MBCS_CODE_U32))
        {
            (void)Det_ReportRuntimeError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_MAIN_FUNCTION_READ , (uint8)CAN_43_FLEXCAN_E_DATALOST);
        }

    #endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */
        /* Create a local copy of the MB to ensure that it is locked out for minimum amount of time.
            Read the DLC; this read access also locks the MB. */
        u8MbDataLength = (uint8)( (u32MbConfig & FLEXCAN_MBCS_LENGTH_U32) >> FLEXCAN_MBCS_LENGTH_SHIFT_U32);

    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
        if   ((((uint8)u8MbDataLength)>=(uint8)FLEXCAN_DATA_LENGTH_MIN_U8) && (((uint8)u8MbDataLength)<=(uint8)FLEXCAN_DATA_LENGTH_MAX_U8))
        {
           u8MbDataLength = Can_Flexcan_aDataLengthMax[(uint8)u8MbDataLength - FLEXCAN_DATA_LENGTH_OFFSET_U8];
        }
    #endif

        /* Prevents that a buffer overflow to be generated by a CAN bus error affecting length field */
        if( u8MbDataLength > (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength )
        {
            u8MbDataLength = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength;
        }

        /* Get the ID of the message. For extended IDs the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
        if ((uint32)0x0U == (u32MbConfig & (uint32)FLEXCAN_MBCS_IDE_U32))
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32MbMessageId = (Can_IdType)((uint32)((REG_READ32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBID_ID_STANDARD_U32)) >> (uint32)(18U)));
        }
        else
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32MbMessageId = (Can_IdType)((uint32)(REG_READ32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBID_ID_EXTENDED_U32)) | FLEXCAN_MBC_ID_IDE_U32);
        }

        /* Get the ID of the message. For FD the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
        if ((uint32)0x0U != ((uint32)(u32MbConfig & (uint32)(FLEXCAN_FD_MB_MESSAGE_U32))))
        {
            u32MbMessageId |= (Can_IdType)CAN_FD_ID_DESCRIPTOR;
        }
    #endif

        /*
           (SWS_Can_00060) Data mapping by CAN to memory is defined in a way that the CAN data byte which is sent out first is array element 0,
                   the CAN data byte which is sent out last is array element 7.
           (SWS_Can_00299) The Can module shall copy the L-SDU in a shadow buffer after reception, if the RX buffer cannot be protected (locked)
                   by CAN Hardware against overwriting by a newly received message.
           (SWS_Can_00300) The Can module shall copy the L-SDU in a shadow buffer, if the CAN Hardware is not globally accessible.
        */

        for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
        {
            /* Copy the data  */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u8CanMbData[u8DatabyteIndex] = REG_READ8(FLEXCAN_MB_DATA((uint32)(u8HwOffset), (uint32)(u16MBGlobalIndex),(u8DatabyteIndex))) ;
        }

        /* Determine Hrh of the message. */
        u32MbHrh = (Can_HwHandleType)(pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID;

        /* Clear the interrupt flag - w1c. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_WRITE32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag, u32TempFlag);

        /* Release the internal lock. Reading the Free Running Timer is not mandatory. If not executed the MB remains locked,
            unless the CPU reads the C/S word of another MB.*/
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        (void)REG_READ32( FLEXCAN_TIMER(u8HwOffset));

    #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
         /*[SWS_Can_00444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */
        if ((boolean)TRUE == CAN_43_FLEXCAN_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
        {
    #endif

            /* Standard/Extended CAN ID of CAN L-PDU */
            Mailbox.CanId = u32MbMessageId;
            /* ID of the corresponding Hardware Object Range */
            Mailbox.Hoh = u32MbHrh;
            /* ControllerId provided by CanIf clearly identify the corresponding controller */
            Mailbox.ControllerId = controller;
            /* length of the SDU in bytes */
            PduInfoPtr.SduLength = u8MbDataLength;
            /* pointer to the SDU (i.e. payload data) of the PDU */
            PduInfoPtr.SduDataPtr = u8CanMbData;
            CanIf_RxIndication(&Mailbox, &PduInfoPtr );
    #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
        }
    #endif
#if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
    if((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanTimestampEnable)
    {
    #ifdef CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED
        u32TimestanpValue = u32MbConfig & CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_MASK_U32;
    #endif
    
    #ifdef CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u32TimestanpValue = REG_READ32(FLEXCAN_HR_TIME_STAMP(u8HwOffset, u8MbIndex));
    #endif
        Can_43_FLEXCAN_pCurrentConfig->CanRxTimestampNotification(u32MbHrh, u32TimestanpValue);
    }
#endif
#if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
    }
    else
    {
        /*Clear interrupt status flag when spurious interrupt is detected*/
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(Can_IflagImask[u8IflagRegIndex][u8HwOffset].u32CanIflag, u32TempFlag);
    }
#endif
    }/*if ( (uint32)0x0U != (u32IflagReg & u32TempFlag) )*/
}

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper during Can_MainFunction_Read if polling is selected and Rxfifo is supported and enabled.
* @details        Processes Rx interrupt flags.
                  This routine is called by:
                    - Can_FlexCan_ProcessRx() from Can_Flexcan.c file
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      u16MBGlobalIndex: index of MB to process in the struct which stores information of MBs
*
* @pre            MB is configured for Rx.
* @post           Inform CanIf in case a data frame was received.
*
*
*/
#if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
static FUNC (void, CAN_CODE) Can_FlexCan_ProcessRxFifo( CONST(uint8, AUTOMATIC) controller)
{
    /* Number of data bytes. */
    VAR(uint8, AUTOMATIC)      u8MbDataLength = 0U;
    /* Physical data bytes. */
#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    static VAR(uint8, AUTOMATIC)      u8CanMbData[64U];
#else
    static VAR(uint8, AUTOMATIC)      u8CanMbData[8U];
#endif
    /* Index for data byte of MB. */
    VAR(uint8, AUTOMATIC)      u8DatabyteIndex = 0U;
    /* Variable for storing the Hrh. */
    VAR(Can_HwHandleType, AUTOMATIC)      u32MbHrh = 0U;
    /* Variables for storing the CanID. */
    VAR(Can_IdType, AUTOMATIC) u32MbMessageId = 0U;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)      u8HwOffset = 0U;
    /* Variable for storing the value of IFLAG register. */
    VAR(uint32, AUTOMATIC)     u32IflagReg = 0U;
    /* Variable for storing the ConfigReg of the MB. */
    VAR(uint32, AUTOMATIC)     u32MbConfig = 0U;
    VAR(boolean, AUTOMATIC) bFifoNotEmpty = (VAR(boolean, AUTOMATIC))FALSE;

    /* Variable for indexing all the MBs fron hardware unit chain (all controllers). */
    VAR(uint16, AUTOMATIC)            u16MBGlobalIndex = 0U;
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    /* Identifies the HRH and its corresponding CAN Con-troller. */
    static VAR(Can_HwType, AUTOMATIC) Mailbox;
    /* Pointer to the received L-PDU. */
    static VAR(PduInfoType, AUTOMATIC) PduInfoPtr;

    /* Index for browsing the available Rx MBs in FIFO's memory. */
    VAR(uint8, AUTOMATIC)      u8BrwMbIndex = 0U;
#if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
    /* Variable for storing the value of IMASKx register. */
    VAR(uint32, AUTOMATIC)           u32ImaskReg = 0U;
#endif
#if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
#ifdef CAN_ENHANCED_RELEASE_OUTPUT_ISSUE
    VAR(uint8, AUTOMATIC)      u8TimeStampOffset = 0U;
#endif
#endif
#if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
    VAR(uint32, AUTOMATIC) u32TimestanpValue;
#endif

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Find the index of first HOH of this controller */
    while ( (u16MBGlobalIndex < (uint16)Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex) && \
            ((controller != ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId)) || \
            ((uint8)0U != ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex))) \
          )
    {
        u16MBGlobalIndex++;
    }

    u8CanMbData[0U]=(uint8)0U;
    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;

#if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
    if ( CAN_CONTROLLERCONFIG_RXFIFO_U32 == (Can_43_FLEXCAN_pControlerDescriptors[controller].u32Options & CAN_CONTROLLERCONFIG_RXFIFO_U32) )
    {
        do
        {
            bFifoNotEmpty = (VAR(boolean, AUTOMATIC))FALSE;
            /* Get the content of IFLAG register for which corresponds this MB. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            u32IflagReg = (REG_READ32(Can_IflagImask[0U][u8HwOffset].u32CanIflag)) & (FLEXCAN_FIFO_OVERFLOW_INT_MASK_U32 | FLEXCAN_FIFO_WARNING_INT_MASK_U32 | FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32);
            /* Check the interrupt flag. */
            if ((uint32)0x0U != u32IflagReg)
            {
    #if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
            /*Get the content of IMASK register for which corresponds this MB. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32ImaskReg = REG_READ32(Can_IflagImask[0U][u8HwOffset].u32CanImask);
            /* Check for spurious interrupt for a INTERRUPT Hardware object only. */
            if ((u32IflagReg == (u32ImaskReg & u32IflagReg)) || ((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanHwObjectUsesPolling))
            {
    #endif
                MCAL_FAULT_INJECTION_POINT(CAN_FIP_3_CHANGE_LENGTH_FIELD);
                /* ********************* Phase1 ********************* */
                /* Check if "mbindex" corresponds to flags for Int Fifo status: Overflow or Warning.
                            If Fifo is disabled, then current flags are normal MB interrupt bits. */
                if (FLEXCAN_FIFO_OVERFLOW_INT_MASK_U32 == (u32IflagReg & FLEXCAN_FIFO_OVERFLOW_INT_MASK_U32))
                {
                    /* Call the handling routine for Overflow fifo event. */
                    if ( NULL_PTR != Can_43_FLEXCAN_pControlerDescriptors[controller].Can_RxFifoOverflowNotification )
                    {
                        Can_43_FLEXCAN_pControlerDescriptors[controller].Can_RxFifoOverflowNotification();
                    }

                #if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
                    (void)Det_ReportRuntimeError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_MAIN_FUNCTION_READ , (uint8)CAN_43_FLEXCAN_E_DATALOST);
                #endif
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32(Can_IflagImask[0U][u8HwOffset].u32CanIflag, FLEXCAN_FIFO_OVERFLOW_INT_MASK_U32);
                }

                if (FLEXCAN_FIFO_WARNING_INT_MASK_U32 == (u32IflagReg & FLEXCAN_FIFO_WARNING_INT_MASK_U32))
                {
                    /* Call Rx FIFO warning Notification. */
                    if ( NULL_PTR != Can_43_FLEXCAN_pControlerDescriptors[controller].Can_RxFifoWarningNotification )
                    {
                        Can_43_FLEXCAN_pControlerDescriptors[controller].Can_RxFifoWarningNotification();
                    }

                    /*Clear the interrupt status flag for FIFO warning */
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32(Can_IflagImask[0U][u8HwOffset].u32CanIflag, FLEXCAN_FIFO_WARNING_INT_MASK_U32);
                }

                if (FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32 == (u32IflagReg & FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32))
                {
                    /* Access data available in MB0 when there is Buffer MB5 Interrupt - Frames Available in FIFO. */
                    bFifoNotEmpty = (VAR(boolean, AUTOMATIC))TRUE;

                    /* ********************* Phase2 ********************* */
                    /* Create a local copy of the MB to ensure that it is locked out for minimum amount of time.
                        Read the DLC; this read access also locks the MB. */
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    u32MbConfig = (uint32)REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)));
                    u8MbDataLength = (uint8)( (u32MbConfig & FLEXCAN_MBCS_LENGTH_U32) >> FLEXCAN_MBCS_LENGTH_SHIFT_U32);

                    /* Prevents that a buffer overflow to be generated by a CAN bus error affecting length field */
                    if( u8MbDataLength > (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength )
                    {
                        u8MbDataLength = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength;
                    }

                    /* Get the ID of the message.
                      For extended IDs the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
                    /* condition to test */
                    if ((uint32)0x0U == (u32MbConfig & (uint32)FLEXCAN_MBCS_IDE_U32))
                    {
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u32MbMessageId = (Can_IdType)((uint32)((REG_READ32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)) ) & (uint32)(FLEXCAN_MBID_ID_STANDARD_U32)) >> (uint32)(18U)));
                    }
                    else
                    {
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u32MbMessageId = (Can_IdType)((uint32)(REG_READ32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u16MBGlobalIndex)) ) & (uint32)(FLEXCAN_MBID_ID_EXTENDED_U32)) | FLEXCAN_MBC_ID_IDE_U32);
                    }

                    /* Get the ID of the message.
                      For FD the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
                    /*
                       (SWS_Can_00060) Data mapping by CAN to memory is defined in a way that the CAN data byte which is sent out first is array element 0,
                               the CAN data byte which is sent out last is array element 7.
                       (SWS_Can_00299) The Can module shall copy the L-SDU in a shadow buffer after reception, if the RX buffer cannot be protected (locked)
                               by CAN Hardware against overwriting by a newly received message.
                       (SWS_Can_00300) The Can module shall copy the L-SDU in a shadow buffer, if the CAN Hardware is not globally accessible.
                    */

                    for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
                    {
                        /* Copy the data  */
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u8CanMbData[u8DatabyteIndex] = REG_READ8(FLEXCAN_MB_DATA((uint32)(u8HwOffset), (uint32)(u16MBGlobalIndex), (u8DatabyteIndex))) ;
                    }

                    /* Determine Hrh of the message. */
                    u32MbHrh = (Can_HwHandleType)((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID);

                    /* Clear the interrupt flag - w1c. */
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    REG_WRITE32( Can_IflagImask[0U][u8HwOffset].u32CanIflag, FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32);

                    /* Release the internal lock. Reading the Free Running Timer is not mandatory. If not executed the MB remains locked,
                        unless the CPU reads the C/S word of another MB.*/
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    (void)REG_READ32( FLEXCAN_TIMER(u8HwOffset));

                #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                     /*[CAN444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */

                    if ((boolean)TRUE == CAN_43_FLEXCAN_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
                    {
                #endif
                    /* Standard/Extended CAN ID of CAN L-PDU */
                    Mailbox.CanId = u32MbMessageId;
                    /* ID of the corresponding Hardware Object Range */
                    Mailbox.Hoh = u32MbHrh;
                    /* ControllerId provided by CanIf clearly identify the corresponding controller */
                    Mailbox.ControllerId = controller;
                    /* length of the SDU in bytes */
                    PduInfoPtr.SduLength = u8MbDataLength;
                    /* pointer to the SDU (i.e. payload data) of the PDU */
                    PduInfoPtr.SduDataPtr = u8CanMbData;
                    CanIf_RxIndication(&Mailbox, &PduInfoPtr );
                #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                    }
                #endif
                
                #if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
                    if((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanTimestampEnable)
                    {
                    #ifdef CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED
                        u32TimestanpValue = u32MbConfig & CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_MASK_U32;
                    #endif
                    
                    #ifdef CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u32TimestanpValue = REG_READ32(FLEXCAN_HR_TIME_STAMP(u8HwOffset, 0U));
                    #endif
                        Can_43_FLEXCAN_pCurrentConfig->CanRxTimestampNotification(u32MbHrh, u32TimestanpValue);
                    }
                #endif
                }
    #if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
            }
            else
            {
                /*Clear interrupt status flag when spurious interrupt is detected*/
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_WRITE32(Can_IflagImask[0U][u8HwOffset].u32CanIflag, u32IflagReg);
            }
    #endif
            }/*if ((uint32)0x0U != (u32IflagReg))*/

            u8BrwMbIndex++;

         /* Processing all available received MBs in FIFO until FIFO is empty or the number of while loop reaches to the FLEXCAN_FIFO_DEPTH_UNIT_U8 times of the FIFO's depth */
        } while( (bFifoNotEmpty == (VAR(boolean, AUTOMATIC))TRUE) &&
                 ((uint8)(FLEXCAN_FIFO_DEPTH_UNIT_U8 * FLEXCAN_FIFO_DEPTH_U8) > u8BrwMbIndex )
               );
    }
#endif

#if (CAN_43_FLEXCAN_ENHANCED_RXFIFO_ENABLE == STD_ON)
    if (CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32 == (Can_43_FLEXCAN_pControlerDescriptors[controller].u32Options & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_U32))
    {
        do
        {
            bFifoNotEmpty = (VAR(boolean, AUTOMATIC))FALSE;
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32IflagReg = (REG_READ32(FLEXCAN_ERFSR(u8HwOffset))) & (FLEXCAN_ERFSR_ERFOVF_U32 | FLEXCAN_ERFSR_ERFDA_U32);
            
            if ((uint32)0U != u32IflagReg)
            {
        #if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
                /*Get the content of IMASK register for which corresponds this MB. */
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                u32ImaskReg = REG_READ32(FLEXCAN_ERFIER(u8HwOffset));
                /* Check for spurious interrupt for a INTERRUPT Hardware object only. */
                if ((u32IflagReg == (u32ImaskReg & u32IflagReg)) || ((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanHwObjectUsesPolling))
                {
        #endif
                    if (FLEXCAN_ERFSR_ERFOVF_U32 == (u32IflagReg & FLEXCAN_ERFSR_ERFOVF_U32))
                    {
                        /* Call the handling routine for Overflow fifo event. */
                        if ( NULL_PTR != Can_43_FLEXCAN_pControlerDescriptors[controller].Can_RxFifoOverflowNotification )
                        {
                            Can_43_FLEXCAN_pControlerDescriptors[controller].Can_RxFifoOverflowNotification();
                        }

                    #if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
                        (void)Det_ReportRuntimeError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_MAIN_FUNCTION_READ , (uint8)CAN_43_FLEXCAN_E_DATALOST);
                    #endif
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        REG_WRITE32(FLEXCAN_ERFSR(u8HwOffset), FLEXCAN_ERFSR_ERFOVF_U32);
                    }
                    
                    /* CAN_ERFSR[ERFDA] is set by the hardware when there is at least one frame available to be read from the Enhanced Rx FIFO */
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    if (FLEXCAN_ERFSR_ERFDA_U32 == (u32IflagReg & FLEXCAN_ERFSR_ERFDA_U32))
                    {
                        bFifoNotEmpty = (VAR(boolean, AUTOMATIC))TRUE;
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        u32MbConfig = (uint32)REG_READ32(FLEXCAN_ENHANCED(u8HwOffset));
                        u8MbDataLength = (uint8)( (u32MbConfig & FLEXCAN_MBCS_LENGTH_U32) >> FLEXCAN_MBCS_LENGTH_SHIFT_U32);
                        
                    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                        if ((((uint8)u8MbDataLength)>=(uint8)FLEXCAN_DATA_LENGTH_MIN_U8) && (((uint8)u8MbDataLength)<=(uint8)FLEXCAN_DATA_LENGTH_MAX_U8))
                        {
                           u8MbDataLength = Can_Flexcan_aDataLengthMax[(uint8)u8MbDataLength - FLEXCAN_DATA_LENGTH_OFFSET_U8];
                        }
                    #endif
                        /* Prevents that a buffer overflow to be generated by a CAN bus error affecting length field */
                        if( u8MbDataLength > (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength )
                        {
                            u8MbDataLength = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength;
                        }
                        /* Get the ID of the message.
                          For extended IDs the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
                        /* condition to test */
                        if ((uint32)0x0U == (u32MbConfig & (uint32)FLEXCAN_MBCS_IDE_U32))
                        {
                            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                            u32MbMessageId = (Can_IdType)((uint32)((REG_READ32(FLEXCAN_ENHANCED(u8HwOffset) + (uint32)4U) & (uint32)(FLEXCAN_MBID_ID_STANDARD_U32)) >> (uint32)(18U)));
                        }
                        else
                        {
                            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                            u32MbMessageId = (Can_IdType)((uint32)(REG_READ32(FLEXCAN_ENHANCED(u8HwOffset) + (uint32)4U) & (uint32)(FLEXCAN_MBID_ID_EXTENDED_U32)) | FLEXCAN_MBC_ID_IDE_U32);
                        }
                        
                        /* Get the ID of the message. For FD the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
                    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                        if ((uint32)0x0U != ((uint32)(u32MbConfig & (uint32)(FLEXCAN_FD_MB_MESSAGE_U32))))
                        {
                            u32MbMessageId |= (Can_IdType)CAN_FD_ID_DESCRIPTOR;
                        }
                    #endif
                        
                        for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
                        {
                            /* Copy the data  */
                            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                            u8CanMbData[u8DatabyteIndex] = REG_READ8(FLEXCAN_ENHANCED_DATA(u8HwOffset, u8DatabyteIndex));
                        }
                        
                        /* Determine Hrh of the message. */
                        u32MbHrh = (Can_HwHandleType)((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID);
                        
                        /* Clear EFRSR[ERFDA] flag */
                        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                        REG_WRITE32(FLEXCAN_ERFSR(u8HwOffset), FLEXCAN_ERFSR_ERFDA_U32);
                        
                        #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                         /*[CAN444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */
                        if ((boolean)TRUE == CAN_43_FLEXCAN_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
                        {
                        #endif
                            /* Standard/Extended CAN ID of CAN L-PDU */
                            Mailbox.CanId = u32MbMessageId;
                            /* ID of the corresponding Hardware Object Range */
                            Mailbox.Hoh = u32MbHrh;
                            /* ControllerId provided by CanIf clearly identify the corresponding controller */
                            Mailbox.ControllerId = controller;
                            /* length of the SDU in bytes */
                            PduInfoPtr.SduLength = u8MbDataLength;
                            /* pointer to the SDU (i.e. payload data) of the PDU */
                            PduInfoPtr.SduDataPtr = u8CanMbData;
                            CanIf_RxIndication(&Mailbox, &PduInfoPtr );
                        #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
                        }
                        #endif
                        
                        #ifdef CAN_ENHANCED_RELEASE_OUTPUT_ISSUE
                            /* Read HR time stamp to release output of enhanced RxFifo */
                            if ((u8MbDataLength >= (uint8)1U) && (u8MbDataLength <= (uint8)4U))
                            {
                                u8TimeStampOffset = (uint8)0x10U;
                            }
                            else if ((u8MbDataLength >= (uint8)5U) && (u8MbDataLength <= (uint8)8U))
                            {
                                u8TimeStampOffset = (uint8)0x14U;
                            }
                            else
                            {
                                /* u8TimeStampOffset = Arbitration length + u8MbDataLength + ID HIT length */
                                u8TimeStampOffset = (uint8)8U + u8MbDataLength + (uint8)4U;
                            }
                            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                            (void)(REG_READ32(FLEXCAN_ENHANCED(u8HwOffset) + (uint32)u8TimeStampOffset));
                        #endif
                        #if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
                            if((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanTimestampEnable)
                            {
                            #ifdef CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED
                                u32TimestanpValue = u32MbConfig & CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_MASK_U32;
                            #endif
                            
                            #ifdef CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED
                                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                                u32TimestanpValue = (REG_READ32(FLEXCAN_ENHANCED(u8HwOffset) + (uint32)u8TimeStampOffset));
                            #endif
                                Can_43_FLEXCAN_pCurrentConfig->CanRxTimestampNotification(u32MbHrh, u32TimestanpValue);
                            }
                        #endif
                    }
        #if (CAN_43_FLEXCAN_RXINT_SUPPORTED == STD_ON)
                }
                else
                {
                    /*Clear interrupt status flag when spurious interrupt is detected*/
                    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                    REG_WRITE32(FLEXCAN_ERFSR(u8HwOffset), u32IflagReg);
                }
        #endif
            }
            
            u8BrwMbIndex++;
        /* Processing all available received MBs in FIFO until FIFO is empty or the number of while loop reaches to the FLEXCAN_FIFO_DEPTH_UNIT_U8 times of the FIFO's depth */
        } while( (bFifoNotEmpty == (VAR(boolean, AUTOMATIC))TRUE) &&
                 (FLEXCAN_FIFO_ENHANCED_DEPTH_U8 > u8BrwMbIndex )
               );
    }
#endif
}
#endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON && CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON) */

/*================================================================================================*/

/**
* @brief          Can_FlexCan_ValidHth servers Can_FlexCan_Write to check the conditions on the Hth used.
* @details        The function is available if the development error detection for the Can module is enabled .
*                 and it shall report the errors if the conditions on Hth is not satisfied.
*
* @param[in]      Hth information which HW-transmit handle shall be used for transmit.
*                 Implicitly this is also the information about the controller to use
*                 because the Hth numbers are unique inside one hardware unit.
* @param[in]      PduInfo Pointer to SDU user memory, DLC and Identifier
* @param[in]      u16MBGlobalIndex - the index of the Hth in the array recording the HOH's information .
* @param[in]      bEnabledFD indicates if the FD feature is supported and enabled.
*                   + bEnabledFD = TRUE: indicates the FD feature is supported and enabled
*                   + bEnabledFD = FALSE: indicates the FD feature is not supported or enabled
*
* @return         A Std_ReturnType value
* @retval         E_OK if all conditions are satisfied
* @retval         E_NOT_OK if development error is occurred
*
*/
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_ValidHth (  Can_HwHandleType Hth,
                                                               P2CONST(Can_PduType, AUTOMATIC, CAN_APPL_CONST) PduInfo,
                                                               VAR(uint16, AUTOMATIC) u16MBGlobalIndex,
                                                               VAR(boolean, AUTOMATIC) bEnabledFD
                                                            )
{
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = E_OK;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Hth must be below uMessageBufferConfigCount and should be a Tx MB type. */
    if ( (Hth >= CanStatic_43_FLEXCAN_pCurrentConfig->u32CanMaxObjectId) || \
         (CAN_43_FLEXCAN_TRANSMIT != (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).eMBType) \
       )

    {
        /*
           (SWS_Can_00217) If development error detection for the Can module is enabled: The function Can_Write shall raise the error CAN_43_FLEXCAN_E_PARAM_HANDLE
                   if the parameter Hth is not a configured Hardware Transmit Handle.
        */

        (void)Det_ReportError((uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_WRITE, (uint8)CAN_43_FLEXCAN_E_PARAM_HANDLE);
        eReturnValue = E_NOT_OK;
    }
    else
    {
    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
        /* Report error if length > 8 bytes. */
        /* @violates @ref Can_Flexcan_c_REF_9 MISRA 2012 Required Rule 14.3 */
        if ( \
                ((PduInfo->length) > ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength)) || \
                ( ((boolean) FALSE == bEnabledFD) && ((PduInfo->length) > (uint8)8U) ) || \
                (( (((uint32)PduInfo->id) & (uint32)CAN_FD_ID_DESCRIPTOR) != CAN_FD_ID_DESCRIPTOR) && ( (PduInfo->length) > (uint8)8U )) \
           )
        {
            /*
               (SWS_Can_00218) If development error detection for the Can module is enabled: The function Can_Write shall raise the
                       error CAN_43_FLEXCAN_E_PARAM_DATA_LENGTH if the length is more than 8 byte.
            */

            (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_WRITE, (uint8)CAN_43_FLEXCAN_E_PARAM_DATA_LENGTH);
            eReturnValue = E_NOT_OK;
        }
    #else /* if(CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_OFF) */
        if ( (PduInfo->length) > 8U )
        {
            /*
               (SWS_Can_00218) If development error detection for the Can module is enabled: The function Can_Write shall raise the
                       error CAN_43_FLEXCAN_E_PARAM_DATA_LENGTH if the length is more than 8 byte.
            */

            (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_WRITE, (uint8)CAN_43_FLEXCAN_E_PARAM_DATA_LENGTH);
            eReturnValue = E_NOT_OK;
        }
    #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */
    }

    (void)bEnabledFD;   /* Prevent compiler warning when CAN_FD is disabled */
    return eReturnValue;
}
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */

/*================================================================================================*/
/**
* @brief          Service for putting the controller into Freeze Mode
* @details        Service for putting the controller into Freeze Mode
*
* @param[in]      Controller: The Can controller configured
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_GotoFreezeMode( VAR(uint8, AUTOMATIC) u8HwOffset)
{

    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Timeout counter. */
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif

    /* Go to Freeze mode through setting both CAN_MCR[FRZ] and CAN_MCR[HALT] to 1 */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);

    /* Check whether the controller is in Low power mode (CAN_MCR[MDIS] = 1 - Module Disable). If it is, clear it to 0 to enable the module*/
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    if ( FLEXCAN_MCR_MDIS_U32 == ((uint32)(REG_READ32( FLEXCAN_MCR(u8HwOffset))) & FLEXCAN_MCR_MDIS_U32) )
    {
        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_03();
        /* Clear CAN_MCR[MDIS] to enable Can module. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_MDIS_U32);

        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_03();
    }

    /* Poll the MCR register until CAN_MCR[FRZACK] (Freeze Mode Acknowledge) is set to 1 or timeout is reached */
    u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    while ( (FLEXCAN_MCR_FRZACK_U32 != ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
            (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
          )
    {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        u32TotalElapsedTime++;
#else
        (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
        u32TotalElapsedTime += u32ElapsedTime;
#endif
    }

    /* If the timeout is reached, then request a Soft Reset */
    if (u32TotalElapsedTime >= Can_u32TicksDelayDuration)
    {
        /* Set CAN_MCR[SOFTRST] to 1 for a Soft Reset request */
        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_03();
        /* Execute Controller Reset. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SOFTRST_U32);
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_03();

        u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        while ( (FLEXCAN_MCR_SOFTRST_U32 != ((uint32)(REG_READ32( FLEXCAN_MCR(u8HwOffset))) & FLEXCAN_MCR_SOFTRST_U32)) && \
                (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
              )
        {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            u32TotalElapsedTime++;
#else
            (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
            u32TotalElapsedTime += u32ElapsedTime;
#endif
        }

        if (u32TotalElapsedTime < Can_u32TicksDelayDuration)
        {
            /* Re-configure MCR_SUPV bit because this bis is reset by Soft reset */
#ifdef CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT
    #if (STD_ON == CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT)
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SUPV_U32);
            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
    #endif
#endif
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_BIT_SET32( FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_WRMFRZ_U32);
            eReturnValue = (Std_ReturnType)E_OK;
        }
        /* Else if the timeout is reached -> return E_NOT_OK */
        /* else {eReturnValue = (Std_ReturnType)E_NOT_OK;} */
    }
    else
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_WRMFRZ_U32);
        eReturnValue = (Std_ReturnType)E_OK;
    }

    return (eReturnValue);
}

/*================================================================================================*/
/**
* @brief          Service for the clock source selection
* @details        This function services for selecting the clock source to the CAN Protocol Engine (PE) to be either the peripheral clock or the oscillator clock
*
* @param[in]      Controller: The Can controller configured
*
*/
#ifdef CAN_43_FLEXCAN_FLEXCAN_CLKSRC_AVAIABLE
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SellectClockSource( VAR(uint8, AUTOMATIC) u8Controller, VAR(uint8, AUTOMATIC) u8HwOffset, VAR(uint8, AUTOMATIC) u8BaudrateIndex )
{
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = (Std_ReturnType)E_NOT_OK;
    VAR(uint32, AUTOMATIC)          u32ValueControlRegister = 0U;
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif

    /* Disable module to configure clock source (if it is supported)*/
    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_09();
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_MDIS_U32);

    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_09();
    /* Load local time-out variable with configured time-out value*/
    u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
    /* After controller disable, wait until low power mode acknowledgement bit to set*/
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    while ( (FLEXCAN_MCR_LPMACK_U32 != ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_LPMACK_U32)) && \
            (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
          )
    {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        u32TotalElapsedTime++;
#else
        (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
        u32TotalElapsedTime += u32ElapsedTime;
#endif
    }

    if (u32TotalElapsedTime < Can_u32TicksDelayDuration)
    {

#if (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON)
        if (Can_43_FLEXCAN_ControllerStatuses[u8Controller].CanClockMode == CAN_43_FLEXCAN_ALTERNATE)
        {
            u32ValueControlRegister = (uint32)(CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].pStaticControllerBaudrateConfigsPtr[u8BaudrateIndex].u32ControlRegisterAlternate);
        }
        else
        {
#endif /* (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON) */
            u32ValueControlRegister = (uint32)(CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].pStaticControllerBaudrateConfigsPtr[u8BaudrateIndex].u32ControlRegister);
#if (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON)
        }
#endif /* (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON) */

        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_09();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_CTRL(u8HwOffset), (uint32)(u32ValueControlRegister & CAN_43_FLEXCAN_CLKSRC_CONFIG_MASK_U32));
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_MDIS_U32);
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_09();

        eReturnValue = (Std_ReturnType)E_OK;
    }

    return (eReturnValue);
}
#endif /* CAN_43_FLEXCAN_FLEXCAN_CLKSRC_AVAIABLE */

/*================================================================================================*/
/**
* @brief          Service for reset the controller.
* @details        Re-initialization must start with a reset (soft).
*                 This routine is called by:
*                  - Can_FlexCan_InitController() from Can_FlexCan.c file.
*
* @param[in]      u8HwOffset: The hardware offset for the used controller.
*
* @post           Controller is enabled and reset.
*
*/
static FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_ResetController( VAR(uint8, AUTOMATIC) u8HwOffset)
{

    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Timeout counter. */
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif

    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_04();
    /* Execute Controller Reset. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SOFTRST_U32);
    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_04();

    /* Wait the Reset end off. */
    u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    while ( (FLEXCAN_MCR_SOFTRST_U32 == ((uint32)(REG_READ32( FLEXCAN_MCR(u8HwOffset))) & FLEXCAN_MCR_SOFTRST_U32)) && \
            (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
          )
    {
        /* MCR[SOFT_RST] still set -> reset in progress. */
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        u32TotalElapsedTime++;
#else
        (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
        u32TotalElapsedTime += u32ElapsedTime;
#endif
    }

    if (u32TotalElapsedTime < Can_u32TicksDelayDuration)
    {
        /* Re-configure MCR_SUPV bit because this bis is reset by Soft reset */
#ifdef CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT
#if (STD_ON == CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT)
        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SUPV_U32);
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
#endif
#endif
        eReturnValue = (Std_ReturnType)E_OK;
    }

    return (eReturnValue);
}



/*=================================================================================================
*                                       GLOBAL FUNCTIONS
==================================================================================================*/
#ifdef CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT
#if (STD_ON == CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT)
    #ifdef CAN_43_FLEXCAN_FLEXCAN_REG_PROT_AVAILABLE
        FUNC(void, CAN_CODE) Can_FlexCan_SetUserAccessAllowed(void)
        {
        #ifdef FLEXCAN_A_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_0_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_0_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_B_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_1_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_1_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_C_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_2_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_2_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_D_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_3_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_3_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_E_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_4_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_4_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_F_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_5_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_5_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_G_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_6_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_6_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        #ifdef FLEXCAN_H_REG_PROT_AVAILABLE
            #ifdef  FLEXCAN_7_BASEADDR
                SET_USER_ACCESS_ALLOWED(FLEXCAN_7_BASEADDR, CAN_FLEXCAN_PROT_MEM_U32);
            #endif
        #endif
        }
    #endif /* CAN_43_FLEXCAN_FLEXCAN_REG_PROT_AVAILABLE */
#endif /* (STD_ON == CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT) */
#endif


/*================================================================================================*/

/**
* @brief          Initialisation of indicator, statuses, etc.
* @details        Initialisation of indicator, statuses, etc.
*                 This routine is called by:
*                 - Can_Init() from Can.c file.
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           Set variables into a definite state.
*
*
*/
FUNC (void, CAN_CODE) Can_FlexCan_InitVariables( void )
{

    /* Index CAN controllers from configuration. */
    VAR(uint8, AUTOMATIC) u8CtrlIndex = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    VAR(float32, AUTOMATIC) f32TempFloat;
#endif
    VAR(uint8, AUTOMATIC) u8MbIndex = 0U;
    VAR(uint16, AUTOMATIC) u16MBGlobalIndex = 0U;

    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    
    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    Can_u32TicksDelayDuration = (uint32)CAN_43_FLEXCAN_TIMEOUT_DURATION;
#else
    f32TempFloat = (float32)(CAN_43_FLEXCAN_TIMEOUT_DURATION / (float32)CAN_43_FLEXCAN_TIMEOUT_COUNTER_TICK2NS());
    if ( (f32TempFloat - (float32)((uint32)f32TempFloat) ) > (float32)0)
    {
        Can_u32TicksDelayDuration = (uint32)((uint32)f32TempFloat + (uint32)1);
    }
    else
    {
        Can_u32TicksDelayDuration = (uint32)((uint32)f32TempFloat);
    }
#endif
    /* Init all global varibales/statuses for all controllers. */
    for ( u8CtrlIndex = 0U; u8CtrlIndex < (uint8)CanStatic_43_FLEXCAN_pCurrentConfig->u8ControllersConfigured; u8CtrlIndex++)
    {
        /* Init INT Disable nesting indicator. It is incremented after every call of Can_DisableControllerInterrupts().
           The function Can_EnableControllerInterrupts() shall perform no action when Can_DisableControllerInterrupts() has not been called before. */
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].s8IntDisableLevel = (sint8)0;
        /* Set to null the first Tx MB index for every controller. */
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].u8FirstTxMBIndex = (uint8)0U;

        /* Set  interrupt mode status to interrupt enabled mode.
           This is needed in order to support the implementation of requirements CAN425 and CAN426 into Can_SetControllerMode API. */
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].eInterruptMode= CAN_FLEXCAN_INTERRUPT_ENABLED;

        /* Set the controller state to STOP after power-up */
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].ControllerState = CAN_CS_STOPPED;

        /* Set the controller current baudrate index as default */
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].u8CurrentBaudRateIndex = (uint8)(Can_43_FLEXCAN_pControlerDescriptors[u8CtrlIndex].u8DefaultBaudRateIndex);

#if (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON)
        /* Set the controller clock mode to normal clock */
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].CanClockMode = CAN_43_FLEXCAN_NORMAL;
#endif /* (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON) */


#if (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
        Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].eCanIcomState = CAN_FLEXCAN_ICOM_DEACTIVATED;
#endif /* (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON) */
    }
    /* Map tu16MBGlobalIndex (the index of HOH in the HOW array) into the u16MBMapping array*/
    for ( u16MBGlobalIndex = 0U; u16MBGlobalIndex < pCanMbConfigContainer->uMessageBufferConfigCount; u16MBGlobalIndex++)
    {
    #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
        if (FLEXCAN_ENHANCED_RXFIFO_OFFSET_U16 != pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].u16MBOffsetAddr)
        {
    #endif
            u8MbIndex = pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].u8HWMBIndex;
            u8CtrlIndex = pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].u8ControllerId;
            Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].u16MBMapping[u8MbIndex] = u16MBGlobalIndex;
    #if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
        }
    #endif
    }
}

/*================================================================================================*/
/**
* @brief          Service for (re)initializing only CAN controller specific settings.
* @details        CAN controller (re-)initialization.
*                 This routine is called by:
*                  - Can_Init() from Can.c file.
*                  - Can_ChangeBaudrate() from Can.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           Set the MBs and interrupts into predefinite state for Can bus communication.
*
*
*/
FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_InitController( VAR(uint8, AUTOMATIC) Controller)
{
    /* Local copy of pointer to the controller descriptor. */
    VAR(Can_PtrControlerDescriptorType, AUTOMATIC) pCanControlerDescriptor = NULL_PTR;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eResetReturn = (Std_ReturnType)E_OK;
    /* Variable to hold the index of the current baudrate */
    VAR(uint8, AUTOMATIC)           u8BaudrateIndex = 0U;
    VAR(uint8, AUTOMATIC)           u8RegCount = 0U;
    VAR(uint32, AUTOMATIC)          u32ValueControlRegister = 0U;
    VAR(uint32, AUTOMATIC)          u32ValueBitTime = 0U;
    /* Max number of mb */
    VAR(uint8, AUTOMATIC)           u8MbMax = 0U;
    VAR(uint32, AUTOMATIC)          u32TempAddr;
    VAR(uint32, AUTOMATIC)          u32TempAddrMax;

    /* Fill the local pointer copy with address of the Controller Descriptor.  */
    pCanControlerDescriptor = &(Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[Controller]);
    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8ControllerOffset;

    /* Get the index of the current baudrate */
    u8BaudrateIndex = Can_43_FLEXCAN_ControllerStatuses[Controller].u8CurrentBaudRateIndex;

    /* Go to Freeze mode to be able to enter Module Disable mode */
    eResetReturn = Can_FlexCan_GotoFreezeMode(u8HwOffset);

#ifdef CAN_43_FLEXCAN_FLEXCAN_CLKSRC_AVAIABLE
    if ((Std_ReturnType)E_OK == eResetReturn)
    {
        /* Selects the clock source to the CAN Protocol Engine (PE) to be either the peripheral clock or the oscillator clock */
        eResetReturn = Can_FlexCan_SellectClockSource(Controller, u8HwOffset, u8BaudrateIndex);
    }
#endif /* CAN_43_FLEXCAN_FLEXCAN_CLKSRC_AVAIABLE */

    if ((Std_ReturnType)E_OK == eResetReturn)
    {
        /* Reset Controller*/
        eResetReturn = Can_FlexCan_ResetController( u8HwOffset);
    }

    if ((Std_ReturnType)E_OK == eResetReturn)
    {
        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SRXDIS_U32);
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();

        Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState = CAN_CS_STOPPED;
    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)

        if ((uint32)(FLEXCAN_MCR_FDEN_U32) == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanFdEnable))
        {
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();

#ifdef ERR_IPV_FLEXCAN_0016
    #if (ERR_IPV_FLEXCAN_0016 == STD_ON)
            Can_FlexCan_SetFDENBitErrata(u8HwOffset);
    #endif
#else
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), (uint32)(FLEXCAN_MCR_FDEN_U32));
#endif

            /* The configuration for Message Buffer Data Size (MBDS)*/
            if ((uint32)(FLEXCAN_MCR_FDEN_U32) == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanFdEnable))
            {
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_RMW32( FLEXCAN_FDCTRL(u8HwOffset), FLEXCAN_FDCTRL_MBDSR_MASK_U32, pCanControlerDescriptor->u32MBBlockSize);
            }

            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32(FLEXCAN_FDCBT(u8HwOffset), (uint32)(((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanFdCbtRegister)) ));

            if (FLEXCAN_FDCTRL_FDRATE_U32 == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanControllerTxBitRateSwitch))
            {
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32( FLEXCAN_FDCTRL(u8HwOffset), (uint32)(FLEXCAN_FDCTRL_FDRATE_U32) );
            }
            else
            {
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_BIT_CLEAR32( FLEXCAN_FDCTRL(u8HwOffset), (uint32)(FLEXCAN_FDCTRL_FDRATE_U32));
            }

            if ((uint32)0U != pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanControllerTrcvDelayCompensation)
            {
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32(FLEXCAN_FDCTRL(u8HwOffset), (uint32)(FLEXCAN_FDCTRL_TDCEN_U32));
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_RMW32(FLEXCAN_FDCTRL(u8HwOffset), FLEXCAN_FDCTRL_TDCOFF_U32,(uint32)((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanControllerTrcvDelayCompensation)<<FLEXCAN_FDCTRL_TDCOFF_OFFSET_U8));
            }
            else
            {
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_BIT_CLEAR32(FLEXCAN_FDCTRL(u8HwOffset), (uint32)(FLEXCAN_FDCTRL_TDCEN_U32));
            }

      #ifndef CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK
          #if ( (CAN_43_FLEXCAN_CONTROLLER_FD_ISO_CANFD == STD_ON) || (CAN_43_FLEXCAN_CONTROLLER_FD_PREXCEN == STD_ON) || (CAN_43_FLEXCAN_CONTROLLER_FD_EDFLTDIS == STD_ON))
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(FLEXCAN_CTRL2(u8HwOffset), (FLEXCAN_FD_CTRL2_STFCNTEN_U32) | (FLEXCAN_FD_CTRL2_EDFLTDIS_U32) | (FLEXCAN_FD_CTRL2_PREXCEN_U32), ((uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanFdCTRL2Register)));
          #endif
      #endif /* defined CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK */
        }
    #endif

#ifndef CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK
        /* Update the value of the CTRL2[TASD]] bit field */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_RMW32(FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_TASD_U32, (uint32)(((uint32)pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].u8TxArbitrationStartDelay)) << FLEXCAN_CTRL2_TASD_SHIFT_U32);
#endif /* defined CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK */
/*
* @ errata ERR_IPV_FLEXCAN_0008 software errata FlexCAN: Non-Correctable Errors In FlexCAN Access
*   Put Device In Freeze Mode bit not working properly
*   CAN_43_FLEXCAN_MEMORY_ECC_SUPPORT = STD_ON it does not represent an implementation of the feature, it represents just avaialability in HW and it is used in order to make sure that
*   this feature is completeley disabled before starting using the HW.
*/
#ifndef CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK
    #if (CAN_43_FLEXCAN_MEMORY_ECC_SUPPORT == STD_ON)
        /* Enable that the MECR register is updated */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_ECRWRE_U32);
        /* Enables writes on MECR register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_CLEAR32( FLEXCAN_MECR(u8HwOffset), FLEXCAN_MECR_ECRWRDIS_U32);
        /*Disable Error Correction  */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_MECR(u8HwOffset), FLEXCAN_MECR_ECCDIS_U32);
        /* Disables writes on MECR register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_SET32( FLEXCAN_MECR(u8HwOffset), FLEXCAN_MECR_ECRWRDIS_U32);
        /* Disable update on MECR register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_CLEAR32( FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_ECRWRE_U32);
    #endif
#endif /* defined CAN_43_FLEXCAN_NOT_SUPPORT_CTRL2_RXFGMASK */

#ifdef ERR_IPV_FLEXCAN_0015
    #if(ERR_IPV_FLEXCAN_0015==STD_ON)
        /* If RFIFO is enabled then the first MBs will be used by the FIFO, initialize the
        u32CancelMBIndex to the value of Max. MB supported to avoid the false TX-MB cancellation */
        if ( CAN_CONTROLLERCONFIG_RXFIFO_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_RXFIFO_U32))
        {
            Can_43_FLEXCAN_ControllerStatuses[Controller].u32CancelMBIndex = CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8NumberOfMB;
        }
        else /* RxFIFO is disabled */
        {
            /* Init the Cancelled MB index with a precalculated value - out of range for every controller. */
            Can_43_FLEXCAN_ControllerStatuses[Controller].u32CancelMBIndex = pCanMbConfigContainer->uMessageBufferConfigCount;
        }
    #else
        #error : the define ERR_IPV_FLEXCAN_0015 must not be STD_OFF
    #endif
#else
        /* Init the Cancelled MB index with a precalculated value - out of range for every controller. */
        Can_43_FLEXCAN_ControllerStatuses[Controller].u32CancelMBIndex = pCanMbConfigContainer->uMessageBufferConfigCount;
#endif
        /* Clear Tx guard flags. */
        do
        {
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();

            Can_43_FLEXCAN_ControllerStatuses[Controller].u32TxGuard[u8RegCount] = (uint32)0x0UL;

            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();

#ifdef ERR_IPV_FLEXCAN_0015
    #if(ERR_IPV_FLEXCAN_0015==STD_ON)
        #if (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_64_U8)
            Can_43_FLEXCAN_ControllerStatuses[Controller].u32TxCancelFlag[u8RegCount] = (PduIdType)0x0UL;
        #else
            Can_43_FLEXCAN_ControllerStatuses[Controller].u32TxCancelFlag[u8RegCount] = (uint32)0x0UL;
        #endif
    #else
        #error : the define ERR_IPV_FLEXCAN_0015 must not be STD_OFF
    #endif
#endif
            u8RegCount++;
        }
        while(u8RegCount < (uint8)((uint8)CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8NumberOfMB >> FLEXCAN_MB_SHIFT5BIT_U8));

#if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
        /* Check if BCC support is enabled in configuration */
        if ( CAN_CONTROLLERCONFIG_BCC_EN_U32 != (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_BCC_EN_U32) )
        {
#endif /* (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON) */
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* Enable individual MB filter masking. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_BCC_U32);
            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
#if (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON)
        }
#endif /* (CAN_43_FLEXCAN_BCC_SUPPORT_ENABLE == STD_ON) */

        /* FlexCan uses local priority feature - extend the ID during the arbitration process with PRIO field from MB reg. */
        if ( CAN_CONTROLLERCONFIG_LPRIO_EN_U32 == (pCanControlerDescriptor->u32Options & CAN_CONTROLLERCONFIG_LPRIO_EN_U32) )
        {
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_LPRIOEN_U32);

            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
        }

#if (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON)
        if (Can_43_FLEXCAN_ControllerStatuses[Controller].CanClockMode == CAN_43_FLEXCAN_ALTERNATE)
        {
            u32ValueBitTime = (uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].u32ControlRegisterAlternate);
            u32ValueControlRegister = (uint32)(CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].pStaticControllerBaudrateConfigsPtr[u8BaudrateIndex].u32ControlRegisterAlternate);
        }
        else
        {
#endif /* (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON) */
            u32ValueBitTime = (uint32)(pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].u32ControlRegister);
            u32ValueControlRegister = (uint32)(CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].pStaticControllerBaudrateConfigsPtr[u8BaudrateIndex].u32ControlRegister);
#if (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON)
        }
#endif /* (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON) */

        
    #if (CAN_43_FLEXCAN_CBT_ENABLE == STD_ON)
        if ((pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].bControllerCbtEnable) == (boolean)(TRUE))
        {
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_CTRL(u8HwOffset), u32ValueControlRegister);
            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_CBT(u8HwOffset), (u32ValueBitTime | FLEXCAN_CBT_BTF_U32));
        }
        else
        {
    #endif
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_WRITE32( FLEXCAN_CTRL(u8HwOffset), (uint32)((u32ValueControlRegister | u32ValueBitTime ) & FLEXCAN_CTRL_CONFIG_MASK_U32));
            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
    #if (CAN_43_FLEXCAN_CBT_ENABLE == STD_ON)
        }
    #endif
    
        /* Loop Back Mode configuration. Clear also the MCR[SRCXDIS] to allow receiving frames transmitted by itself. */
        if ( FLEXCAN_CTRL_LPB_U32 == (u32ValueControlRegister & FLEXCAN_CTRL_LPB_U32) )
        {
            SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SRXDIS_U32);

            SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
        }
        u32TempAddr = CAN_GET_BASE_ADDRESS(u8HwOffset) + FLEXCAN_MB_OFFSET_U32;

        u32TempAddrMax = u32TempAddr + (uint32)((uint32)(CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8NumberOfMB) * (uint32)16U);

        while(u32TempAddr < u32TempAddrMax)
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_WRITE32( u32TempAddr, (uint32)0U);
            u32TempAddr = u32TempAddr + 4U;
        }
        /* Stage1: init RxFifo ******************************************************************** */

#if (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON)
        Can_FlexCan_InitRxFiFo(Controller, u8HwOffset);
#endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) */

        /* Stage2: Init Rx and Tx MBs ******************************************************************** */
        Can_FlexCan_InitReceiveMBs ( Controller, u8HwOffset);

        Can_FlexCan_InitTransmitMBs(Controller, u8HwOffset);

        if(Can_43_FLEXCAN_pControlerDescriptors[Controller].u8MaxMBCount > 0U)
        {
            u8MbMax = Can_43_FLEXCAN_pControlerDescriptors[Controller].u8MaxMBCount - 1U;
        }
        else
        {
            u8MbMax = 0U;
        }
        /* Set the number of MBs configured for this controller (Rx + Tx MBs). */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        REG_RMW32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_MAXMB_U32, ((uint32)u8MbMax)) ;
#ifdef CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT
    #if (STD_ON == CAN_43_FLEXCAN_ENABLE_USER_MODE_SUPPORT)
        SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_SUPV_U32);
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_05();
    #endif
#endif

#ifdef ERR_IPV_FLEXCAN_0015
    #if(ERR_IPV_FLEXCAN_0015==STD_ON)
    /* Do not set the Abort Enable bit of the MCR */
    #else
        #error : the define ERR_IPV_FLEXCAN_0015 must not be STD_OFF
    #endif
#else
    #if (CAN_43_FLEXCAN_API_ENABLE_ABORT_MB == STD_ON)
            /* Abort Enable: Tx Cancelation supported and used for this Controller. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_AEN_U32);
    #endif /* (ERR_IPV_0015==STD_ON) */
#endif

        /* Pre-calculated MB INT masks (used in Can_EnableControllerInterrupts) - If events are set for polling mode these bits are not set.
            Clear all INTs flags  .. for MBs (w1c bits). */
        u8RegCount=0U;
        do
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            REG_WRITE32( Can_IflagImask[u8RegCount][u8HwOffset].u32CanIflag, (uint32)(FLEXCAN_32BITMASK_U32) );
            u8RegCount++;
        }
        while(u8RegCount < (uint8)(CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8NumberOfMB >> FLEXCAN_MB_SHIFT5BIT_U8));

        /* Clear bits for Tx/Rx/BusOff/Err/(w1c bits). */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( FLEXCAN_ESR(u8HwOffset), (uint32)(((uint32)(FLEXCAN_ESR_BOFFINT_U32 | FLEXCAN_ESR_ERRINT_U32 | FLEXCAN_ESR_WAK_INT_U32)) & FLEXCAN_ESR_CONFIG_MASK_U32));

        /* Clear the Error Counters Register. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( FLEXCAN_ECR(u8HwOffset), (uint32)(((uint32)0UL) & FLEXCAN_ECR_CONFIG_MASK_U32));

    #if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
        #ifdef CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED
            /* Selects the time tick source used for incrementing the Free Running Timer counter */
            if ((boolean)TRUE == Can_43_FLEXCAN_pCurrentConfig->bExternalClockEnable)
            {
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
                REG_BIT_SET32(FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_TIMER_SRC_U32);
            }
            /*selects which time base is used for capturing the 16-bit TIME_STAMP field of the Message Buffer register. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_MBTSBASE_MASK_U32, ((uint32)Can_43_FLEXCAN_pCurrentConfig->eMBTimestampBase << FLEXCAN_CTRL2_MBTSBASE_SHIFT_U8));
        #endif
            /* configures the point in time when a 32-bit time base is captured during a CAN frame and stored in the high resolution time stamp register */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            REG_RMW32(FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_TSTAMPCAP_MASK_U32, ((uint32)Can_43_FLEXCAN_pCurrentConfig->eHRTimestampCapturePoint << FLEXCAN_CTRL2_TSTAMPCAP_SHIFT_U8));
    #endif
        /* Release the internal lock. Reading the Free Running Timer is not mandatory. If not executed the MB remains locked,
            unless the CPU reads the C/S word of another MB.*/
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        (void)REG_READ32( FLEXCAN_TIMER(u8HwOffset));

    } /* (eResetReturn == E_OK) */

    return eResetReturn;
}

/*================================================================================================*/
/**
* @brief          Service for de-initializing only CAN controller specific settings.
* @details        CAN controller de-initialization.
*                 This routine is called by:
*                  - Can_43_FLEXCAN_DeInit() from Can.c file.
*
* @param[in]      Controller: CAN controller for which the initialization shall be done. Based on configuration order list (CanControllerId).
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           De-initialization controller's configuration.
*
*
*/
FUNC (void, CAN_CODE) Can_FlexCan_DeInitController( VAR(uint8, AUTOMATIC) Controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = (Std_ReturnType)E_NOT_OK;

    /* Get the hardware offset of controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8ControllerOffset;

    /* Reset Controller*/
    eReturnValue = Can_FlexCan_ResetController( u8HwOffset);
    if((Std_ReturnType)E_OK == eReturnValue)
    {
        /* Clear Control 1 register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_CTRL(u8HwOffset), FLEXCAN_CTRL_DEFAULT_VALUE_U32);
        /* Clear Control 2 register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_CTRL2(u8HwOffset), FLEXCAN_CTRL2_DEFAULT_VALUE_U32);
    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
        /* Clear Bit Timing register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_CBT(u8HwOffset), FLEXCAN_CBT_DEFAULT_VALUE_U32);
        /* Clear FD Control register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32(FLEXCAN_FDCTRL(u8HwOffset), FLEXCAN_FDCTRL_DEFAULT_VALUE_U32);
        /* Clear FD Bit Timing register */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        /* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
        REG_WRITE32(FLEXCAN_FDCBT(u8HwOffset), FLEXCAN_FDCBT_DEFAULT_VALUE_U32);
    #endif
        /* Set Controller state UNINIT */
        Can_43_FLEXCAN_ControllerStatuses[Controller].ControllerState = CAN_CS_UNINIT;
    }
}

/*================================================================================================*/
/**
* @brief          Service obtains the error state of the CAN controller.
* @details        Service obtains the error state of the CAN controller.
*                 This routine is called by:
*                  - Can_43_FLEXCAN_GetControllerErrorState() from Can.c file.
*
* @param[in]      Controller: CAN controller for which the initialization shall be done. Based on configuration order list (CanControllerId).
*
* @pre            At least one controller must be configured in the Driver structure.
* @post           Return the error state of Controller
*
*
*/
FUNC (Can_ErrorStateType, CAN_CODE) Can_FlexCan_GetControllerErrorState( VAR(uint8, AUTOMATIC) Controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)   u8HwOffset = 0U;
    /* The value Error State of Controller */
    VAR(uint32, AUTOMATIC)  u32ErrorState = 0;
    /* Update Error State of Controller */
    VAR(Can_ErrorStateType, AUTOMATIC)  eCtrlErrState = CAN_ERRORSTATE_BUSOFF;

    /* Get the hardware offset of controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[Controller].u8ControllerOffset;

    /* Get the value from FLTCONF field */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    u32ErrorState = REG_READ32(FLEXCAN_ESR(u8HwOffset)) & FLEXCAN_ESR_FLTCONF_U32;

    switch(u32ErrorState)
    {
        case (FLEXCAN_ESR_FLTCONF_ERROR_ACTIVE_U8):
        {
            eCtrlErrState = CAN_ERRORSTATE_ACTIVE;
            break;
        }
        case (FLEXCAN_ESR_FLTCONF_ERROR_PASSIVE_U8):
        {
            eCtrlErrState = CAN_ERRORSTATE_PASSIVE;
            break;
        }
        default:
        {
            break;
        }
    }
    return eCtrlErrState;
}
/*================================================================================================*/
/**
* @brief          Service to Perform software triggered state transitions of the CAN controller State machine.
* @details        Transition controller to another state/mode.
*                 This routine is called by:
*                  - Can_SetControllerMode() from Can.c file.
*                  - Can_43_FLEXCAN_IPW_ProcessBusOff() from Can_IPW.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
* @param[in]      Transition Possible transitions
*
* @return         Std_ReturnType
* @retval         E_OK transition initiated
* @retval         E_NOT_OK development or production error
*
* @pre            Controller is configured and must be into a state that permit the valid transition to another different state.
* @post           Shall enable interrupts that are needed in the new state. Shall disable interrupts that are not allowed in the new state.
*
*
*/
FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_SetControllerMode( VAR(uint8, AUTOMATIC) Controller,
                                                           P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor,
                                                           VAR(Can_ControllerStateType, AUTOMATIC) Transition,
                                                           VAR(boolean, AUTOMATIC) canif_notification_required)
{

    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC)  eReturnValue = E_NOT_OK;

    /*
      (SWS_Can_00017) The function Can_SetControllerMode shall perform software triggered state transitions of the CAN controller State machine.
    */
    switch (Transition)
    {
        /* CANIF_CS_STARTED -> CANIF_CS_STOPPED. */
        case (CAN_CS_STOPPED):
            eReturnValue = Can_FlexCan_SetControllerToStopMode(Controller, pCanControlerDescriptor, canif_notification_required);
            break;

        /* CANIF_CS_STOPPED -> CANIF_CS_STARTED. */
        case (CAN_CS_STARTED):
            eReturnValue = Can_FlexCan_SetControllerToStartMode(Controller, pCanControlerDescriptor);
            break;

        /* CANIF_CS_STOPPED -> CANIF_CS_SLEEP. */
        case (CAN_CS_SLEEP):
            eReturnValue = Can_FlexCan_SetControllerToSleepMode(Controller);
            break;

            /* Unknown transition requested. */
            default:
                /*
                   (SWS_Can_00200) If development error detection for the Can module is enabled: if an invalid transition has been requested, the function Can_SetControllerMode shall raise the error CAN_43_FLEXCAN_E_TRANSITION and return E_NOT_OK.
                */
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)

                (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_SET_CONTROLLER_MODE, (uint8)CAN_43_FLEXCAN_E_TRANSITION);
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */
                break;

        } /* end switch */

    return (eReturnValue);
}


/*================================================================================================*/
/**
* @brief          Service disables all interrupts for the given CAN controller.
* @details        This routine is called by:
*                 - Can_DisableControllerInterrupts() from Can.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
*
* @pre            Disable interrupts must be called prior to enable interrupts.
* @post           Clear all flags/bits that are needed for disabling the interrupts.
*
*
*/
FUNC (void, CAN_CODE) Can_FlexCan_DisableControllerInterrupts( VAR(uint8, AUTOMATIC) Controller)
{

    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_00();
    /*
       (SWS_Can_00202) When Can_DisableControllerInterrupts has been called several times, Can_EnableControllerInterrupts must be called
                as many times before the interrupts are re-enabled.
    */
    Can_43_FLEXCAN_ControllerStatuses[Controller].s8IntDisableLevel++;

    /* If nesting level is zero or below zero; <0 needed for reentrancy. */
    /*
       (SWS_Can_00049) The function Can_DisableControllerInterrupts shall access the
        CAN controller registers to disable all interrupts for that CAN controller only, if interrupts for that CAN Controller are enabled.
    */
    if ( (sint8)1 == Can_43_FLEXCAN_ControllerStatuses[Controller].s8IntDisableLevel )
    {
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_00();
        /* Switch to disabled mode. */
        Can_43_FLEXCAN_ControllerStatuses[Controller].eInterruptMode = CAN_FLEXCAN_INTERRUPT_DISABLED;
        Can_FlexCan_DisableInterrupts(Controller);
    }
    else
    {
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_00();
    }
}


/*================================================================================================*/
/**
* @brief          Service enables all interrupts that shall be enabled according the current software status.
* @details        This routine is called by:
*                  - Can_EnableControllerInterrupts() from Can.c file.
*
* @param[in]      Controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      pCanControlerDescriptor Pointer to controller descriptor configuration
*
* @pre            Can be executed only if disable interrupts was called before.
* @post           Enable all interrupts that must be enabled according the current sw status.
*
*
*/
FUNC (void, CAN_CODE) Can_FlexCan_EnableControllerInterrupts( VAR(uint8, AUTOMATIC) Controller,
                                                          P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor )
{
    /* Variable that tells if disable ints was called at least once before. */
    VAR(uint8, AUTOMATIC)   u8DisCalledBefore = 0U;


    /*
       (SWS_Can_00202) When Can_DisableControllerInterrupts has been called several times, Can_EnableControllerInterrupts must be called as many
               times before the interrupts are re-enabled.
    */
    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_01();

    if ( Can_43_FLEXCAN_ControllerStatuses[Controller].s8IntDisableLevel > (sint8)0 )
    {
        /* When s8IntDisableLevel is greater than 0  means Can_DisableControllerInterrupts was called at least once before this call of current function. */

        /* Decrement the nesting level. */
        Can_43_FLEXCAN_ControllerStatuses[Controller].s8IntDisableLevel--;

        u8DisCalledBefore = (uint8)0x1U;
    }

    /* Can_DisableControllerInterrupts and Can_EnableControllerInterrupts do not modify the software flags. */

    /*
       (SWS_Can_00208) The function Can_EnableControllerInterrupts shall perform no action when Can_DisableControllerInterrupts has not been called before.
    */
    if ( ((sint8)0 == Can_43_FLEXCAN_ControllerStatuses[Controller].s8IntDisableLevel) && ((uint8)0x1U == u8DisCalledBefore) )
    {
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_01();
        /* Switch to enabled mode. */
        Can_43_FLEXCAN_ControllerStatuses[Controller].eInterruptMode = CAN_FLEXCAN_INTERRUPT_ENABLED;
        Can_FlexCan_EnableInterrupts(Controller, pCanControlerDescriptor);
    }
    else
    {
        SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_01();
    }
}


/*================================================================================================*/
/**
* @brief          Local function for canceling low priority msg during Can Write operation.
* @details        This routine is called by:
*                  - Can_FlexCan_Write() from Can_FlexCan.c file.
*                  - Can_AbortMb() from Can.c file.
*
* @param[in]      controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      mbindex index of the message buffer to be canceled
*
* @pre            A Tx message with a higher priority was requested for a MB.
* @post           Inform CanIf about cancellation in case of success.
*
*/

#if (CAN_43_FLEXCAN_API_ENABLE_ABORT_MB == STD_ON)
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_FlexCan_Cancel( VAR(uint8, AUTOMATIC) controller,
                                          VAR(uint16, AUTOMATIC) u16MBGlobalIndex )
{
    VAR(uint8, AUTOMATIC)  u8MbIndex = 0U;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)  u8HwOffset = 0U;
    /* Some temporary variables for registers read/write.  */
    /* Configuration register for current MB. */
    VAR(uint32, AUTOMATIC) u32MbConfig = 0U;

    u8MbIndex = (Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex;
    /* Tell the interrupt routine that cancellation of this MB is in progress. */
    Can_43_FLEXCAN_ControllerStatuses[controller].u32CancelMBIndex = (Can_HwHandleType)u8MbIndex;
    /* Get the hardware offset for this controller. Note that hardware offset may not be the same with the controller index from the 'Can_43_FLEXCAN_ControlerDescriptorType' structure. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;

    /* Check if the MB is still full. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    if ( (uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32)) == (uint32)(FLEXCAN_MBCS_CODETX_U32 | FLEXCAN_MBCS_CODETXEN_U32) )
    {

#ifdef ERR_IPV_FLEXCAN_0015
    #if(ERR_IPV_FLEXCAN_0015==STD_ON)
        /* MB still full -> deactivate it. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u32MbConfig = ( REG_READ32( FLEXCAN_MB((u8HwOffset), (u16MBGlobalIndex))) & (uint32)(~FLEXCAN_MBCS_CODE_U32)) | FLEXCAN_MBCS_CODETX_U32;
        #if (CAN_43_FLEXCAN_MAXMB_SUPPORTED == FLEXCAN_MB_64_U8)
            Can_43_FLEXCAN_ControllerStatuses[controller].u32TxCancelFlag[(u8MbIndex >> FLEXCAN_MB_SHIFT5BIT_U8)] |= (PduIdType)(((uint32)0x01U) << ((uint32)u8MbIndex));
        #else
            Can_43_FLEXCAN_ControllerStatuses[controller].u32TxCancelFlag[(u8MbIndex >> FLEXCAN_MB_SHIFT5BIT_U8)] |= ((uint32)0x01U) << ((uint32)u8MbIndex);
        #endif
    #else
        #error : the define ERR_IPV_FLEXCAN_0015 must not be STD_OFF
    #endif
#else
        /* MB still full -> cancel it. */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u32MbConfig = ( REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(~FLEXCAN_MBCS_CODE_U32)) | FLEXCAN_MBCS_CODETX_U32 | FLEXCAN_MBCS_CODETXABORT_U32;
#endif
        /* Send command to abort the message */
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        REG_WRITE32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex)), (uint32)(u32MbConfig));
    }
}
#endif /* (CAN_43_FLEXCAN_API_ENABLE_ABORT_MB == STD_ON) */

/*================================================================================================*/
/**
* @brief          Process a message buffer abort
* @details        This function write a abort code (b'1001) to MBCS[CODE] field of the MB.
*                This routine is called by:
*                - CanIf or an upper layer according to Autosar requirements.
*
* @param[in]      Hth - HW-transmit handler
*
* @pre            Driver must be initialized and the current MB transmission should be ready for transmit.
*
*
*/

#if ((CAN_43_FLEXCAN_API_ENABLE_ABORT_MB == STD_ON))

FUNC(void, CAN_CODE) Can_FlexCan_AbortMb( VAR(Can_HwHandleType, AUTOMATIC) Hth )
{
    VAR(uint8, AUTOMATIC) u8Controller;
    /* Variable for indexing all the MBs fron hardware unit chain (all controllers). */
    VAR(uint16, AUTOMATIC)            u16MBGlobalIndex = 0U;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    while ( (u16MBGlobalIndex < pCanMbConfigContainer->uMessageBufferConfigCount) && \
            ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID != Hth) \
          )
    {
        u16MBGlobalIndex++;
    }
    u8Controller = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId;

#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
    if ( (Hth >= CanStatic_43_FLEXCAN_pCurrentConfig->u32CanMaxObjectId) || \
         (CAN_43_FLEXCAN_TRANSMIT != (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).eMBType) \
       )
    {
        /*
        (SWS_Can_00217) If development error detection for the Can module is enabled: The function Can_Write shall raise the error CAN_43_FLEXCAN_E_PARAM_HANDLE
                if the parameter Hth is not a configured Hardware Transmit Handle.
        */

        (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_ABORT_MB, (uint8)CAN_43_FLEXCAN_E_PARAM_HANDLE);
    }
    else
    {

        /* Test if controller is in valid range. */
        if ( (u8Controller >= (uint8)CanStatic_43_FLEXCAN_pCurrentConfig->u8ControllersConfigured) ||
             (FLEXCAN_NULL_OFFSET_U8 == (CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8ControllerOffset)) )
        {

            (void)Det_ReportError( (uint16)CAN_43_FLEXCAN_MODULE_ID, (uint8)CAN_43_FLEXCAN_INSTANCE, (uint8)CAN_43_FLEXCAN_SID_ABORT_MB, (uint8)CAN_43_FLEXCAN_E_PARAM_CONTROLLER);
        }
        else
        {
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */

#if ((CAN_43_FLEXCAN_ABORT_ONLY_ONE_MB==STD_OFF) && (CAN_43_FLEXCAN_MULTIPLEXED_TRANSMISSION==STD_ON))

            while ( u16MBGlobalIndex < pCanMbConfigContainer->uMessageBufferConfigCount )
            {
                if (Hth == ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID))
                {
                    Can_FlexCan_Cancel( u8Controller, u16MBGlobalIndex);
                }
                u16MBGlobalIndex++;
            }
#else /* CAN_43_FLEXCAN_ABORT_ONLY_ONE_MB==STD_OFF */
            if ( (u16MBGlobalIndex < pCanMbConfigContainer->uMessageBufferConfigCount))
            {
                Can_FlexCan_Cancel( u8Controller, u16MBGlobalIndex);
            }
#endif   /* CAN_43_FLEXCAN_ABORT_ONLY_ONE_MB==STD_ON */

#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
        }
    }
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */
}
#endif /* (CAN_43_FLEXCAN_API_ENABLE_ABORT_MB == STD_ON) */

/*================================================================================================*/
/**
* @brief          Can_FlexCan_Write checks if hardware transmit object that is identified by the HTH is free.
* @details        Can_FlexCan_Write checks if hardware transmit object that is identified by the HTH is free.
*                     Can_Write checks if another Can_Write is ongoing for the same HTH.
*                     a) hardware transmit object is free:
*                         The mutex for that HTH is set to 'signaled' the ID, DLC and SDU are put in a format appropriate for
*                           the hardware (if necessary) and copied in the appropriate hardware registers/buffers.
*                         All necessary control operations to initiate the transmit are done.
*                         The mutex for that HTH is released. The function returns with E_OK.
*                     b) hardware transmit object is busy with another transmit request.
*                         The function returns with CAN_BUSY.
*                     c) A preemptive call of Can_Write has been issued, that could not be handled reentrant (i.e. a call with the same HTH).
*                         The function returns with CAN_BUSY the function is non blocking
*                     d) The hardware transmit object is busy with another transmit request for an L-PDU that has lower priority than that for the current request
*                         The transmission of the previous L-PDU is cancelled (asynchronously).
*                         The function returns with CAN_BUSY.
*                         This routine is called by:
*                         - Can_Write() from Can.c file.
*                     Algorithm Description:
*                     Case1: TxMUX supported = ON
*                           Can_Write receive the Hth handle and the PduInfo for transmission. It starts to check from the first MBs of the
*                           current controller to search for a free MB. On the first free MB it stops and place the PduInfo and activate the transmission.
*                           In this case function set E_OK for return value and all other functionality is skipped.
*                           If no MB is finded as free then the lowest priority MB is selected for comparing with the priority of the current PduInfo.
*                           If the current PduInfo has a higher priority than the current lower priority (from all MBs) then this lower priority MB is canceled.
*                    Case2: TxMUX supported = OFF
*                          CanWrite() receive the Hth handle and the PduInfo for transmission. It checks if MB with the same index as Hth is free and if yes prepare
*                          and sends the current PduInfo data. If that MB is bussy with another data then it checks the priority between these 2 structures.
*                          Depending by the last evaluation it decides what MB data to cancel.
*
* @param[in]      Hth information which HW-transmit handle shall be used for transmit.
*                 Implicitly this is also the information about the controller to use
*                 because the Hth numbers are unique inside one hardware unit.
* @param[in]      PduInfo Pointer to SDU user memory, DLC and Identifier
*
* @return          Std_ReturnType
* @retval          E_OK write command has been accepted
* @retval          E_NOT_OK development error occured
* @retval          CAN_BUSY no TX hardware buffer available or preemtive call of Can_Write() that can't be implemented reentrant
*
* @pre            The MB must be configured for Tx.
* @post           Transmit the data or ignore it in case of MB is full with another task.
*
*/
FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_Write( Can_HwHandleType Hth,
                                                   P2CONST(Can_PduType, AUTOMATIC, CAN_APPL_CONST) PduInfo )
{

    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)CAN_BUSY;
    /* Variable for keeping the controller Id. */
    VAR(uint8, AUTOMATIC)          u8CtrlId = 0U;
    /* Variable for indexing the MBs. */
    VAR(uint8, AUTOMATIC)          u8MbIndex = 0U;
    /* General purpose variable */
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)          u8HwOffset = 0U;
    /* Variable for determining the IFLAG register for every MB: IFLAGx */
    VAR(uint8, AUTOMATIC)          u8IflagRegIndex = 0U;
    /* Variable for determining the mash bit in the IFLAGx register for current MB. */
    VAR(uint32, AUTOMATIC)         u32TempFlag = 0U;
    VAR(uint16, AUTOMATIC)         u16MBGlobalIndex = 0U;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;

#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    /*variable for current baudrate index*/
    VAR(uint8, AUTOMATIC) u8BaudrateIndex = 0U;
    P2CONST(Can_43_FLEXCAN_ControlerDescriptorType, AUTOMATIC, CAN_APPL_CONST) pCanControlerDescriptor;
    VAR(boolean, AUTOMATIC) bEnabledFD;
#endif

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Calculate the MB index. When transmit multiplex is enabled search any MB to be free, MBs that have the same ObjectID
    When Multiplex is disabled ,you can have more than one controller, everyone having MBs configured. In this case the index of the MB is different from the
            one in the plugin */
    while ( (u16MBGlobalIndex < pCanMbConfigContainer->uMessageBufferConfigCount) && \
            ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID != Hth) \
          )
    {
        u16MBGlobalIndex++;
    }
    u8CtrlId = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId;

#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    pCanControlerDescriptor = &Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[u8CtrlId];
    /* Get the index of the current baudrate */
    u8BaudrateIndex = Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].u8CurrentBaudRateIndex;
    if (((uint32)FLEXCAN_MCR_FDEN_U32) == (pCanControlerDescriptor->pControllerBaudrateConfigsPtr[u8BaudrateIndex].ControllerFD.u32CanFdEnable))
    {
        bEnabledFD = (boolean)TRUE;
    }
    else
    {
        bEnabledFD = (boolean)FALSE;
    }
#endif
    /* Get the hardware offset for this controller. Note that hardware offset may not be the same with the controller index from the 'Can_43_FLEXCAN_ControlerDescriptorType' structure. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u8ControllerOffset;

#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)

#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    eReturnValue = Can_FlexCan_ValidHth(Hth, PduInfo, u16MBGlobalIndex, bEnabledFD);
#else
    eReturnValue = Can_FlexCan_ValidHth(Hth, PduInfo, u16MBGlobalIndex, (boolean)FALSE);
#endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)   */

    if ((Std_ReturnType)E_OK == eReturnValue)
    {

#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */



    #if (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
        /* [SWS_CAN_00470] If Pretended  Networking  is  activated  CanDrv  shall  reject Can_Write() requests with return value CAN_BUSY. */
        if( CAN_FLXCAN_ICOM_ACTIVATED == Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].eCanIcomState)
        {
            eReturnValue = E_NOT_OK;
        }
        if (E_NOT_OK != eReturnValue)
        {
    #endif

    #if (CAN_43_FLEXCAN_MULTIPLEXED_TRANSMISSION == STD_ON)
        /* Need to find a free MB for transmission. This do-while block is executed only when multiplex transmission is ON because the data can be stored in any MB
                that has the same ObjectID. */
        do
        {
    #endif /* (CAN_43_FLEXCAN_MULTIPLEXED_TRANSMISSION == STD_ON) */
            u8MbIndex = pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].u8HWMBIndex;

            /* Is the MB empty?
                 This test is a bit early; the u32TxGuard is not set yet and someone else can grab this MB before we reserve it
                 but it saves setting the guard on full or cancelled MBs only to discover they are not empty and clearing the guard again. */
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            if ( FLEXCAN_MBCS_CODETX_U32 == (uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u16MBGlobalIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32)) )
            {
                /*
                   (SWS_Can_00212) The function Can_Write shall perform following actions if the hardware transmit object is free: The mutex for that HTH is set to 'signaled';
                         the ID, DLC and SDU are put in a format appropriate for the hardware; All necessary control operations to initiate the transmit are done;
                         The mutex for that HTH is released; The function returns with E_OK.
                */

                /* Calculate the index of the IFLAG register and u32TxGuard (index=0 for MB32...MB63, index=1 for MB0...MB31, index=2 for MBO64 ... 96). */
                u8IflagRegIndex = (u8MbIndex >> FLEXCAN_MB_SHIFT5BIT_U8);

                /* Calculate the bit in the IFLAG register. */
                u32TempFlag = ((uint32)0x01U) << ((uint32)u8MbIndex & FLEXCAN_MASK_32BITS_U32);

                SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_02();
                /* Test the GUARD MASK and the INTERRUPT FLAG.
                     Cannot operate on locked out MBs (re-entry).. also cannot operate on MBs for which the Tx confirmation has not been sent yet.
                     Below is read-modify-write cycle for u32TxGuard flag which may be interrupted -> must use SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_XX() for preventing broken u32TxGuard value. */

                if ( (uint32)0x0U == (Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].u32TxGuard[u8IflagRegIndex] & u32TempFlag) )
                {
                    /* Interrupt flag is not set for this MB this meaning MB is not in progress. */
                    /* The mutex for that HTH is set to 'signaled': The guard is 0, the MB is not locked out at the moment -> lock it out. */
                    Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].u32TxGuard[u8IflagRegIndex] |= u32TempFlag;

                    /* u32TxGuard was set without any risk of broken data - now can free the Critical section. */
                    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_02();

                    /* Write data into the Message buffer for transition*/
                #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
                    eReturnValue = Can_FlexCan_UpdateMB(u8CtrlId, u16MBGlobalIndex, PduInfo, bEnabledFD);
                #else
                    eReturnValue = Can_FlexCan_UpdateMB(u8CtrlId, u16MBGlobalIndex, PduInfo, (boolean) FALSE);
                #endif /* (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON) */

                    SchM_Enter_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_02();
                    Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].u32TxGuard[u8IflagRegIndex] &= (uint32)(~u32TempFlag);
                    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_02();
                }
                else /* else of "if((uint32)0x0U==(Can_43_FLEXCAN_ControllerStatuses[u8CtrlId].u32TxGuard[0]&u32TempFlag))" */
                {

                    SchM_Exit_Can_43_FLEXCAN_CAN_EXCLUSIVE_AREA_02();
                    /* MB is locked out because software flag (Guart bit) is set. */
                    eReturnValue = (Std_ReturnType)CAN_BUSY;
                }
            }
            else /* else of "if(FLEXCAN_MBCS_CODETX_U32==(uint32)(REG_READ32( FLEXCAN_MB((u8HwOffset), (u8MbIndex))) & (uint32)(FLEXCAN_MBCS_CODE_U32)))" */
            /* MB is not empty */
            {
                    /* MB is not empty. */
                    eReturnValue = (Std_ReturnType)CAN_BUSY;
            }

    #if (CAN_43_FLEXCAN_MULTIPLEXED_TRANSMISSION == STD_ON)
            u16MBGlobalIndex++;
        } while ( (u16MBGlobalIndex < pCanMbConfigContainer->uMessageBufferConfigCount) &&
                  (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex].u32HWObjID == Hth) &&
                  ((Std_ReturnType)CAN_BUSY == eReturnValue)
                );
    #endif /* (CAN_43_FLEXCAN_MULTIPLEXED_TRANSMISSION == STD_ON) */

    #if (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
        }
        else
        {
            eReturnValue = (Std_ReturnType)CAN_BUSY;
        }
    #endif
#if (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON)
    }
    else
    {
        eReturnValue = E_NOT_OK;
    }
#endif /* (CAN_43_FLEXCAN_DEV_ERROR_DETECT == STD_ON) */

    return (eReturnValue);
}

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer from ISR when Interrupt mode selected.
* @details        Processes Tx interrupt flags.
*               This routine is called by:
*                - Can_IsrFC##FC##_UNI() / Can_IsrFC##FC##_##Name() from Can_Irq.c file.
*
* @param[in]      controller CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      mbindex_start: index of start MB which will be resolved
*                 mbindex_end:   index of end MB which will be resolved
*
* @pre            MB is configured for Tx.
* @post           CanIf is informed with cancellation or transmit success.
*
*/
#if (CAN_43_FLEXCAN_TX_RX_INTR_SUPPORTED == STD_ON)
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_FlexCan_ProcessTx( CONST(uint8, AUTOMATIC) controller,
                                          CONST(uint8, AUTOMATIC) mbindex_start,
                                          CONST(uint8, AUTOMATIC) mbindex_end )
{
    VAR(uint8, AUTOMATIC)   u8MbIndex = 0U;
    VAR(uint16, AUTOMATIC)   u16MbGlobalIndex = 0U;

    for (u8MbIndex = mbindex_start; u8MbIndex <= mbindex_end; u8MbIndex++)
    {
        /* @violates @ref Can_Flexcan_c_REF_11 MISRA 2012 Required Rule 18.1 */
        u16MbGlobalIndex = Can_43_FLEXCAN_ControllerStatuses[controller].u16MBMapping[u8MbIndex];
        if ( ((CAN_43_FLEXCAN_TRANSMIT == (Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].eMBType)) && \
            (controller == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].u8ControllerId)) && \
            ((boolean)TRUE != Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].CanHwObjectUsesPolling) \
            )
        {
            Can_FlexCan_ProcessTxPoll(controller, u16MbGlobalIndex);
        }
    }
}
#endif /* (CAN_43_FLEXCAN_TX_RX_INTR_SUPPORTED == STD_ON) */

/*================================================================================================*/
/**
* @brief          Service to perform the polling of TX confirmation and TX cancellation confirmation
* @details        This routine is called by:
*               - Can_MainFunction_Write() from Can.c file.
*
* @pre            The controller must be configured for transmit in polling mode and at least one MB is configured for Tx.
* @post           Process the transmission data in case of availability.
*
*
*/
#if (CAN_43_FLEXCAN_TXPOLL_SUPPORTED == STD_ON)

FUNC (void, CAN_CODE) Can_FlexCan_MainFunctionWrite(void)
{

    /* Variable for indexing the controllers. */
    VAR(uint8, AUTOMATIC)   u8CtrlId = 0U;

    VAR(uint16, AUTOMATIC)   u16CtrlGlobalIndex;

    /* Loop through all configured controller descriptors. */
    for ( u16CtrlGlobalIndex = Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex; u16CtrlGlobalIndex < Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; u16CtrlGlobalIndex++)
    {
        u8CtrlId = Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16CtrlGlobalIndex].u8ControllerId;

        /* Check whether the controller is enabled and whether Tx polling is used for this controller. */
        if ( (FLEXCAN_NULL_OFFSET_U8 != CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
             ((boolean)TRUE == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16CtrlGlobalIndex].CanHwObjectUsesPolling) \
           )
        {
            /* Enabled & TxPoll used. Process Tx interrupt flags. */
            Can_FlexCan_ProcessTxPoll(u8CtrlId, u16CtrlGlobalIndex);
        }
    }

}

/*================================================================================================*/
/**
* @brief          Function called at fixed cyclic time, with polling of all the MessageBuffer referenced to writepoll
* @details        Service for performs the polling of TX confirmation and TX cancellation confirmation when CAN_TX_PROCESSING is set to POLLING.
*                 This routine is called by:
*                 - CanIf or an upper layer according to Autosar requirements.
*
* @api
*
* @pre            Driver must be initialized.
* @post           Send the data from that MB that is configured for Tx. 
*/
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_FlexCan_MainFunctionMultipleWritePoll( VAR(uint8, AUTOMATIC) writepoll)
{
    /* Variable for indexing the controllers. */
    VAR(uint8, AUTOMATIC)  u8CtrlId = 0U;
    /* First MB to process. */
    VAR(uint16, AUTOMATIC)  u16CtrlGlobalIndex = 0U;

    if ( NULL_PTR != Can_43_FLEXCAN_pCurrentConfig )
    {
        /* Parse through all TX configured message buffer */
        for ( u16CtrlGlobalIndex = Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex; u16CtrlGlobalIndex < Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.uMessageBufferConfigCount; u16CtrlGlobalIndex++)
        {
            u8CtrlId = Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16CtrlGlobalIndex].u8ControllerId;

            /*  Poll only the Tx MB which is referenced by Can_FlexCan_MainFunctionMultipleWritePoll */
            if ((writepoll == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16CtrlGlobalIndex].u32CanMainFuncRWPeriodRef) && \
                 (FLEXCAN_NULL_OFFSET_U8 != CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
                 ((boolean)TRUE == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16CtrlGlobalIndex].CanHwObjectUsesPolling) \
                )
            {
                /* Enabled & TxPoll used. Process Tx interrupt flags. */
                Can_FlexCan_ProcessTxPoll(u8CtrlId, u16CtrlGlobalIndex);
            }
        }
    }
}
#endif /* (CAN_43_FLEXCAN_TXPOLL_SUPPORTED == STD_ON) */

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer from ISR when Interrupt mode selected.
* @details        Processes Rx interrupt flags.
                  This routine is called by:
                    - Can_IsrFC##FC##_UNI() / Can_IsrFC##FC##_##Name() from Can_Irq.c file
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      mbindex_start first MB to process
* @param[in]      mbindex_end last MB to process
*
* @pre            MB is configured for Rx.
* @post           Inform CanIf in case a data frame was received.
*
*
*/
#if (CAN_43_FLEXCAN_TX_RX_INTR_SUPPORTED == STD_ON)
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_FlexCan_ProcessRx( CONST(uint8, AUTOMATIC) controller,
                                             CONST(uint8, AUTOMATIC) mbindex_start,
                                             CONST(uint8, AUTOMATIC) mbindex_end )
{
    VAR(uint8, AUTOMATIC)   u8MbIndex = 0U;
    VAR(uint16, AUTOMATIC)   u16MbGlobalIndex;
    
    u8MbIndex = mbindex_start;
    
    #if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
    if (((CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_IE_U32 == ((Can_43_FLEXCAN_pControlerDescriptors[controller].u32Options) & CAN_CONTROLLERCONFIG_RXFIFO_ENHANCED_IE_U32)) ||
        (CAN_CONTROLLERCONFIG_RXFIFO_U32 == ((Can_43_FLEXCAN_pControlerDescriptors[controller].u32Options) & CAN_CONTROLLERCONFIG_RXFIFO_U32))) &&
        ((uint8)0U == mbindex_start)
       )
    {
        Can_FlexCan_ProcessRxFifo(controller);
    #if (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON)
        u8MbIndex = Can_43_FLEXCAN_pCurrentConfig->ControlerDescriptors[controller].u8RxFiFoUsedMb;
    #endif
    }
    #endif
    
    while (u8MbIndex <= mbindex_end)
    {
        /* @violates @ref Can_Flexcan_c_REF_11 MISRA 2012 Required Rule 18.1 */
        u16MbGlobalIndex = Can_43_FLEXCAN_ControllerStatuses[controller].u16MBMapping[u8MbIndex];
        if (((CAN_43_FLEXCAN_RECEIVE == (Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].eMBType)) && \
            (controller == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].u8ControllerId))  && \
            ((boolean)TRUE != Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MbGlobalIndex].CanHwObjectUsesPolling)
            )
        {
            Can_FlexCan_ProcessRxNormal(controller, u16MbGlobalIndex);
        }

        u8MbIndex++;
    }
}

#endif /* (CAN_43_FLEXCAN_TX_RX_INTR_SUPPORTED == STD_ON) */


/*================================================================================================*/
/**
* @brief          Service to perform the polling of RX indications.
* @details        Processes Rx interrupt flags.
*                 This routine is called by:
*                    - Can_MainFunction_Read() from Can.c file.
*
* @pre            The controller must be configured for receive in polling mode and at least one MB is configured for Rx.
* @post           Process the reception data in case of availability.
*
*
*/
#if (CAN_43_FLEXCAN_RXPOLL_SUPPORTED == STD_ON)

FUNC (void, CAN_CODE) Can_FlexCan_MainFunctionRead( void)
{
    /* Variable for indexing the controllers. */
    VAR(uint8, AUTOMATIC)  u8CtrlId = 0U;
#if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
    /* First MB to process. */
    VAR(uint8, AUTOMATIC)  u8MbIndex = 0U;
#endif
    VAR(uint16, AUTOMATIC)  u16MBGlobalIndex = 0U;

    /* Loop through all configured controller descriptors. */
    for ( u16MBGlobalIndex = 0U; u16MBGlobalIndex < (uint16)Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex; u16MBGlobalIndex++)
    {
        u8CtrlId = Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u8ControllerId;
        /*
           (SWS_Can_00108) The function Can_MainFunction_Read shall perform the
            polling of RX indications when CanRxProcessing is set to POLLING or MIXED. In
            case of MIXED processing only the hardware objects for which
            CanHardwareObjectUsesPolling is set to TRUE shall be polled.
        */
        if ( (FLEXCAN_NULL_OFFSET_U8 != CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
             ((boolean)TRUE == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].CanHwObjectUsesPolling) \
           )
        {
        #if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
            u8MbIndex = Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u8HWMBIndex;
            if ( ((CAN_CONTROLLERCONFIG_RXFIFO_U32 == ((Can_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u32Options) & CAN_CONTROLLERCONFIG_RXFIFO_U32)) && (u8MbIndex == (uint8)0U)) ||
                 (FLEXCAN_ENHANCED_RXFIFO_OFFSET_U16 == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u16MBOffsetAddr)
               )
            {
                Can_FlexCan_ProcessRxFifo(u8CtrlId);
            }
            else
            {
        #endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON && CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON) */

                Can_FlexCan_ProcessRxNormal(u8CtrlId, u16MBGlobalIndex);

        #if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
            }
        #endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON && CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON) */
        }
    }
}

/*================================================================================================*/
/**
* @brief          Function called at fixed cyclic time, with polling of all the MessageBuffer referenced to .readpoll
* @details        Service for performs the polling of RX indications when CAN_RX_PROCESSING is set to POLLING.
*                 This routine is called by:
*                 - CanIf or an upper layer according to Autosar requirements.
*
* @api
* @pre            Driver must be initialized.
* @post           Receive the data from that MB that is configured for Rx. 
*/
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC (void, CAN_CODE) Can_FlexCan_MainFunctionMultipleReadPoll( VAR(uint8, AUTOMATIC) readpoll)
{
    /* Variable for indexing the controllers. */
    VAR(uint8, AUTOMATIC)  u8CtrlId = 0U;
#if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
    /* First MB to process. */
    VAR(uint8, AUTOMATIC)  u8MbIndex = 0U;
#endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) */
    VAR(uint16, AUTOMATIC)  u16MBGlobalIndex = 0U;

    if ( NULL_PTR != Can_43_FLEXCAN_pCurrentConfig )
    {
        /* Loop through all configured controller descriptors. */
        for ( u16MBGlobalIndex = 0U; u16MBGlobalIndex < Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex; u16MBGlobalIndex++)
        {
            u8CtrlId = Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u8ControllerId;

            /*
               (SWS_Can_00108) The function Can_MainFunction_Read shall perform the
                polling of RX indications when CanRxProcessing is set to POLLING or MIXED. In
                case of MIXED processing only the hardware objects for which
                CanHardwareObjectUsesPolling is set to TRUE shall be  polled.
            */
            if ( (readpoll == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u32CanMainFuncRWPeriodRef) && \
                (FLEXCAN_NULL_OFFSET_U8 != CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u8ControllerOffset) && \
                 ((boolean)TRUE == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].CanHwObjectUsesPolling) \
               )
            {
            #if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
                u8MbIndex = Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u8HWMBIndex;
                if ( ((CAN_CONTROLLERCONFIG_RXFIFO_U32 == ((Can_43_FLEXCAN_pControlerDescriptors[u8CtrlId].u32Options) & CAN_CONTROLLERCONFIG_RXFIFO_U32)) && (u8MbIndex == (uint8)0U)) ||
                     (FLEXCAN_ENHANCED_RXFIFO_OFFSET_U16 == Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer.pMessageBufferConfigsPtr[u16MBGlobalIndex].u16MBOffsetAddr)
                   )
                {
                    Can_FlexCan_ProcessRxFifo(u8CtrlId);
                }
                else
                {
            #endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON && CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON) */

                    Can_FlexCan_ProcessRxNormal(u8CtrlId, u16MBGlobalIndex);

            #if ((CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON))
                }
            #endif /* (CAN_43_FLEXCAN_RXFIFO_ENABLE == STD_ON && CAN_43_FLEXCAN_PROCESS_RXFIFO_USED == STD_ON) */
            }
        }
    }
}
#endif /* (CAN_43_FLEXCAN_RXPOLL_SUPPORTED == STD_ON) */


/*================================================================================================*/
/**
* @brief          Service to perform the polling of CAN status register flags to detect transition of CAN Controller state
* @details        The function Can_MainFunction_Mode shall implement the polling of CAN status register flags to detect transition of CAN Controller state
*
* @pre
* @post
*
*/

FUNC (void, CAN_CODE) Can_FlexCan_MainFunctionMode( void)
{
    /* Variable for indexing the controllers. */
    VAR(uint8, AUTOMATIC)  u8CtrlIndex = 0U;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)  u8HwOffset = 0U;
    /* Old and new MCR status Register*/

    VAR(uint32, AUTOMATIC)  u32NewMcr = 0U;

    /* Loop through all configured controller descriptors. */
    for ( u8CtrlIndex = (uint8)0U; u8CtrlIndex < (uint8)CanStatic_43_FLEXCAN_pCurrentConfig->u8ControllersConfigured; u8CtrlIndex++)
    {
        if ( (FLEXCAN_NULL_OFFSET_U8 != CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlIndex].u8ControllerOffset) )
        {

            if(CAN_CS_SLEEP != Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].ControllerState)
            {
                /* Get the hardware offset for this controller. */

                u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8CtrlIndex].u8ControllerOffset;
                /*
                    (SWS_Can_00373) The function Can_Mainfunction_Mode shall call the function CanIf_ControllerModeIndication to notify the upper layer about a successful
                             state transition of the CAN controller, in case the state transition was triggered by function Can_SetControllerMode.
                */

                /* We have to look for all the possible transitions*/
                /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
                /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
                 u32NewMcr = (uint32)(REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_NOTRDY_U32);


                /*Check if logical state is synchronized with hardware state*/
                if((FLEXCAN_MCR_NOTRDY_U32 == u32NewMcr) && (CAN_CS_STARTED == Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].ControllerState))
                {
            #if (CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
                    REG_WRITE32(FLEXCAN_MCR(u8HwOffset), ((~FLEXCAN_PNET_ENABLE_U32) & u32NewMcr));
                    Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].eCanIcomState = CAN_FLEXCAN_ICOM_DEACTIVATED;
            #endif
                    Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].ControllerState = CAN_CS_STOPPED;
                    CanIf_ControllerModeIndication(u8CtrlIndex, CANIF_CS_STOPPED);
                }
                else if ((FLEXCAN_MCR_NOTRDY_U32 != u32NewMcr) && (CAN_CS_STOPPED == Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].ControllerState))
                {
                    Can_43_FLEXCAN_ControllerStatuses[u8CtrlIndex].ControllerState = CAN_CS_STARTED;
                    CanIf_ControllerModeIndication(u8CtrlIndex, CANIF_CS_STARTED);
                }
                else
                {
                /* deliberately left blank to avoid MISRA violation  */
                }
            }
        }
    }
}

/*================================================================================================*/
/**
* @brief          Local function for calling notification function to notify upper layer during Can_MainFunction_BusOff if polling is selected or from ISR when Interrupt mode selected.
* @details        Local function for calling notification function to notify upper layer during
*                 Can_MainFunction_BusOff if polling is selected or from ISR when Interrupt mode selected.
*                 This routine is called by:
*                  - Can_43_FLEXCAN_IPW_ProcessBusOff() from Can.c file.
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @pre            A busoff condition must to be fulfilled.
* @post           Status flag is cleared.
*
*/
FUNC (void, CAN_CODE) Can_FlexCan_ProcessBusOff( CONST(uint8, AUTOMATIC) controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC) u8HwOffset = 0U;


    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;

    /* Clear the ESR[BOFF_INT] bus off interrupt flag (w1c). */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32( FLEXCAN_ESR(u8HwOffset), (FLEXCAN_ESR_BOFFINT_U32 & FLEXCAN_ESR_CONFIG_MASK_U32));
}

/*================================================================================================*/
/**
* @brief          This function checks if a BusOff has occurred for the given controller.
* @details        This routine is called by:
*                  - Can_MainFunction_BusOff() from Can.c file.
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @return        Std_ReturnType
* @retval        E_OK BusOff detected
* @retval        E_NOT_OK BusOff not detected
*
* @pre            A request for busoff checking is required.
* @post           Report the occurence or not for an busoff event.
*/
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC (Std_ReturnType, CAN_CODE) Can_FlexCan_CheckBusOff( VAR(uint8, AUTOMATIC) controller)
{

    /* Return value. */
    VAR(uint8, AUTOMATIC) eReturnValue = (uint8)E_NOT_OK;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC) u8HwOffset = 0U;

    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;

    /* Check Busoff flag if it's set. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    if ( FLEXCAN_ESR_BOFFINT_U32 == (FLEXCAN_ESR_BOFFINT_U32 & (uint32)REG_READ32( FLEXCAN_ESR(u8HwOffset))) )
    {
        /* Controller is in BusOff state. */
        eReturnValue = (uint8)E_OK;
    }

    return (eReturnValue);
}


/*================================================================================================*/
/**
* @brief          Process Rx Fifo FrameAvailable events.
* @details        This routine is called by:
*                  - Can_43_FLEXCAN_IPW_RxFifoFrameAvNotif() from Can.c file.
*
* @param[in]      controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
*
* @return        Std_ReturnType
* @retval        E_OK Notification detected
* @retval        E_NOT_OK Notification not detected
*
* @pre            Driver must be initialized and RxFifo should be enabled.
*
*/
#if ((CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON) && (CAN_43_FLEXCAN_RXFIFO_EVENT_UNIFIED == STD_OFF))
/* @violates @ref Can_Flexcan_c_REF_6 MISRA 2012 Advisory Rule 8.7 */
FUNC(void, CAN_CODE) Can_FlexCan_RxFifoFrameAvNotif( CONST(uint8, AUTOMATIC) controller)
{
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)  u8HwOffset = 0U;
    /* Variable for indexing the MBs. */
    VAR(uint8, AUTOMATIC)    u8MbIndex = 0U;
    /* Number of data bytes. */
    VAR(uint8, AUTOMATIC)    u8MbDataLength = 0U;
    /* Physical data bytes. */
    static VAR(uint8, AUTOMATIC)    u8CanMbData[8];
    /* Index for data byte of MB. */
    VAR(uint8, AUTOMATIC)    u8DatabyteIndex = 0U;
    /* Variable for storing the Hrh. */
    VAR(Can_HwHandleType, AUTOMATIC)    u32Hrh = 0U;
    /* Variables for storing the CanID. */
    VAR(Can_IdType, AUTOMATIC) u32MbMessageId = 0U;
    /* Temporary variable. */
    VAR(uint32, AUTOMATIC)   u32MbConfig = 0U;
    /* Identifies the HRH and its corresponding CAN Con-troller. */
    static VAR(Can_HwType, AUTOMATIC) Mailbox;
    /* Pointer to the received L-PDU. */
    static VAR(PduInfoType, AUTOMATIC) PduInfoPtr;

    VAR(uint16, AUTOMATIC)   u16MBGlobalIndex = 0U;
    /* Pointer to the MB container structure. */
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;

    pCanMbConfigContainer   = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Get the hardware offset for this controller. */
    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[controller].u8ControllerOffset;

    MCAL_FAULT_INJECTION_POINT(CAN_FIP_4_CHANGE_LENGTH_FIELD);
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    u32MbConfig = (uint32)REG_READ32( FLEXCAN_MB((u8HwOffset), (uint32)(u8MbIndex)));

    /* Create a local copy of the MB to ensure that it is locked out for minimum amount of time. Read the DLC; this read access also locks the MB. */
    u8MbDataLength = (uint8)((u32MbConfig & FLEXCAN_MBCS_LENGTH_U32) >> FLEXCAN_MBCS_LENGTH_SHIFT_U32);

    /*Prevents that a buffer overflow to be generated by a CAN bus error affecting length field*/
    if( u8MbDataLength > 8U )
    {
        u8MbDataLength = 8U;
    }

    /* Get the ID of the message.
    For extended IDs the most significant bit must be set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
    if (((uint32)0x0U == (u32MbConfig & (uint32)FLEXCAN_MBCS_IDE_U32)))
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u32MbMessageId = (Can_IdType)((uint32)((REG_READ32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u8MbIndex))) & (uint32)(FLEXCAN_MBID_ID_STANDARD_U32)) >> (uint32)(18U)));
    }
    else
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u32MbMessageId = (Can_IdType)((uint32)((uint32)(REG_READ32( FLEXCAN_MB_ID((u8HwOffset), (uint32)(u8MbIndex))) & (uint32)(FLEXCAN_MBID_ID_EXTENDED_U32)) | FLEXCAN_MBC_ID_IDE_U32));
    }

    /* Copy the data. */
    for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
        u8CanMbData[u8DatabyteIndex] = REG_READ8(FLEXCAN_MB_DATA((uint32)(u8HwOffset), (uint32)(u8MbIndex), (u8DatabyteIndex))) ;
    }

    /* Release the internal lock. Reading the Free Running Timer is not mandatory. If not executed the MB remains locked,
        unless the CPU reads the C/S word of another MB.*/
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    (void)REG_READ32( FLEXCAN_TIMER(u8HwOffset));

    /*
    Call the RxIndication function - This service is implemented in the CAN Interface and called by the CAN Driver after a CAN L-PDU has been received.
    Within this service, the CAN Interface translates the CanId into the configured target PDU ID and routes this indication to the configured upper layer target service(s).
    */

    /* Find the global index of the first MB (MB0) of this controller.*/
    while ( (u16MBGlobalIndex < (uint16)Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex) &&
            ((controller != ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId)) ||
            ((uint8)0U != ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex)))
          )
    {
        u16MBGlobalIndex++;
    }
    /* Get HW object ID of the first MB */
    u32Hrh = (Can_HwHandleType)(pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID;

    #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
    /*[CAN444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */
        if ((boolean)TRUE ==    CAN_43_FLEXCAN_LPduReceiveCalloutFunction((uint8)u32Hrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
        {
    #endif
            /* Standard/Extended CAN ID of CAN L-PDU */
            Mailbox.CanId = u32MbMessageId;
            /* ID of the corresponding Hardware Object Range */
            Mailbox.Hoh = u32Hrh;
            /* ControllerId provided by CanIf clearly identify the corresponding controller */
            Mailbox.ControllerId = controller;
            /* length of the SDU in bytes */
            PduInfoPtr.SduLength = u8MbDataLength;
            /* pointer to the SDU (i.e. payload data) of the PDU */
            PduInfoPtr.SduDataPtr = u8CanMbData;
            CanIf_RxIndication(&Mailbox, &PduInfoPtr );
    #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
        }
    #endif
    /* Ack interrupt flag - w1c bit. */
    /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
    /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
    /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
    REG_WRITE32( FLEXCAN_IFLAG1(u8HwOffset), (uint32)((FLEXCAN_FIFO_AVAILABLE_INT_MASK_U32)));
}
#endif /* (CAN_43_FLEXCAN_LEGACY_RXFIFO_ENABLE == STD_ON) */


/*================================================================================================*/
/*
* @brief          Process a transition from one clock source to another.
* @details        This function is configuring Can controllers to run on the same baudrate, but having a different MCU source clock.
*                 This routine is called by:
*                  - Can_SetClockMode() from Can.c file.
*
* @param[in]      u8Controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      can_clk_mode clock mode selection
*
* @return        Std_ReturnType Result of the clock switch operation.
* @retval        E_OK  Switch clock operation was ok.
* @retval        E_NOT_OK  Switch clock operation was not ok.
*
* @pre            Driver must be initialized and all the controllers must be in Stop state.
*
* @note           Not AUTOSAR required. This is user implementation.
*/

#if (CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON)

FUNC(Std_ReturnType, CAN_CODE) Can_FlexCan_SetClockMode( VAR(uint8, AUTOMATIC) u8Controller, VAR(Can_43_FLEXCAN_ClockModeType, AUTOMATIC) can_clk_mode)
{
    /* Return the operation success. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (uint8)E_NOT_OK;

    if ((can_clk_mode == CAN_43_FLEXCAN_NORMAL) || (can_clk_mode == CAN_43_FLEXCAN_ALTERNATE))
    {
        /* Set the controller clock mode*/
        Can_43_FLEXCAN_ControllerStatuses[u8Controller].CanClockMode = can_clk_mode;
        eReturnValue = (Std_ReturnType)E_OK;
    }

    return (eReturnValue);
}

#endif /* CAN_43_FLEXCAN_DUAL_CLOCK_MODE == STD_ON */


/*================================================================================================*/
/*
* @brief          Set controller into Pretended Networking mode with the ConfigurationID valid.
* @details        This function is API which support the Pretended Networking featrue. After this function is called, it will configure for controller with information in the configurationIDs (corresponding with ID valid )
*                 This routine is called by:
*                  - Can_SetIcomConfiguration() from Can.c file.
*
* @param[in]      Controller    CAN controller for which the init shall be done. Based on configuration order list (CanControllerId).
* @param[in]      u8ConfigIcomIndex the ID of CanIcomConfig
*
* @return        Std_ReturnType Result of the clock switch operation.
* @retval        E_OK  Configure was ok.
* @retval        E_NOT_OK  Configure was not ok.
*
* @pre            Driver must be initialized and all the controllers must be in Stop state.
*
* @note           At the momen, Just have Calypso to support this feature, base on ASR421.
*/

#if(CAN_43_FLEXCAN_PUBLIC_ICOM_SUPPORT == STD_ON)
FUNC(Std_ReturnType, CAN_CODE) Can_FlexCan_SetIcomConfig( VAR(uint8, AUTOMATIC) u8Controller, VAR(uint8, AUTOMATIC) u8ConfigIcomIndex )
{
    VAR(uint32, AUTOMATIC)          u32RegisterValue = 0U;

    /* Variable for store value of timeout*/
#if (CAN_43_FLEXCAN_PRETENDED_TIMEOUT_CHECK==STD_ON)
    VAR(uint32, AUTOMATIC)          u32Timercount = 0U;
#endif /* (CAN_43_FLEXCAN_PRETENDED_TIMEOUT_CHECK==STD_ON) */
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;
    /* Controller hardware offset on chip. */
    VAR(uint8, AUTOMATIC)           u8HwOffset = 0U;
    volatile P2CONST(Can_43_FLEXCAN_IcomConfigsType, CAN_CONST, CAN_APPL_CONST) CanIcomConfig;
    volatile P2CONST(Can_43_FLEXCAN_IcomRxMessageConfigsType, CAN_CONST, CAN_APPL_CONST) CanIcomRxMessageConfig;
    volatile P2CONST(Can_43_FLEXCAN_IcomRxMessageSignalType, CAN_CONST, CAN_APPL_CONST) CanIcomRxMessageSignalConfig;

    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8ControllerOffset;
    /* Get adress of structures of PNET mode. */
    CanIcomConfig = &(CanStatic_43_FLEXCAN_pCurrentConfig->pCanIcomConfigs[u8ConfigIcomIndex]);
    CanIcomRxMessageConfig = &(CanIcomConfig->pCanIcomRxMessageConfigs[0U]);
    CanIcomRxMessageSignalConfig = &(CanIcomRxMessageConfig->pCanIcomRxMessageSignalConfigs[0U]);
    /* [SWS_CAN_00464]CanDrv is responsible to perform reconfiguration of the CAN Controller (incl. ICOM) according to the CanIcomConfig parameters for the  selected configuration (CanIcomConfigId). */
    /*Put the controller in freeze*/
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);

    u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
    while ( (FLEXCAN_MCR_FRZACK_U32 != ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
            (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
          )
    {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        u32TotalElapsedTime++;
#else
        (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
        u32TotalElapsedTime += u32ElapsedTime;
#endif
    }

    if (u32TotalElapsedTime < Can_u32TicksDelayDuration)
    {
        /* Init PNET mode for controller */
        REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_PNET_ENABLE_U32);
        Can_43_FLEXCAN_ControllerStatuses[u8Controller].eCanIcomState = CAN_FLXCAN_ICOM_ACTIVATED;
        /* ======================================== Write all parameter for PNET================================================= */
        /* Write parameter for registers relate to PNET mode */

    #if (CAN_43_FLEXCAN_PRETENDED_TIMEOUT_CHECK==STD_ON)
        /* Write value for CAN_CTRL2_PN[MATCHTO] */
        u32Timercount = (uint32)(CanIcomRxMessageConfig->CanIcomMissingMessageTimerValue);
        REG_WRITE32(FLEXCAN_CAN_CTRL2_PN(u8HwOffset), (uint32)u32Timercount);
    #endif
        /* Write value for CAN_FLT_ID1 register */
        u32RegisterValue = (uint32)(CanIcomRxMessageConfig->CanIcomMessageId);
    #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
            u32RegisterValue = u32RegisterValue | (uint32)0x40000000U;
    #else
            u32RegisterValue = u32RegisterValue << FLEXCAN_STANDARD_ID_SHIFT_U32;
    #endif
        REG_WRITE32(FLEXCAN_CAN_FLT_ID1(u8HwOffset), (uint32)(u32RegisterValue));
        /* Write value for CAN_FLT_ID2_IDMASK register */
        u32RegisterValue = (uint32)(CanIcomRxMessageConfig->CanIcomMessageIdMask);
    #if (CAN_43_FLEXCAN_EXTENDEDID == STD_ON)
            u32RegisterValue = u32RegisterValue | (uint32)0x40000000U;
    #else
            u32RegisterValue = u32RegisterValue << FLEXCAN_STANDARD_ID_SHIFT_U32;
    #endif
        REG_WRITE32(FLEXCAN_CAN_FLT_ID2_IDMASK(u8HwOffset), (uint32)(u32RegisterValue));
        if ((boolean)TRUE == CanIcomRxMessageConfig->CanFiltPayload)
        {
             /* Write value for CAN_FLT_DLC register */
            u32RegisterValue = (uint32)(CanIcomRxMessageSignalConfig->DLCLowValue) << 16U;
            u32RegisterValue |= (uint32)(CanIcomRxMessageSignalConfig->DLCHighValue);
            REG_WRITE32(FLEXCAN_CAN_FLT_DLC(u8HwOffset), (uint32)(u32RegisterValue));
            u32RegisterValue = 0U;
            /* Write value for CAN_PL1_HI register */
            REG_WRITE32(FLEXCAN_CAN_PL1_HI(u8HwOffset), CanIcomRxMessageSignalConfig->CanIcomSignalValueHigh);
            /* Write value for CAN_PL1_LO register */
            REG_WRITE32(FLEXCAN_CAN_PL1_LO(u8HwOffset), CanIcomRxMessageSignalConfig->CanIcomSignalValueLow);

            /* Write value for CAN_PL2_PLMASK_HI register */
            REG_WRITE32(FLEXCAN_CAN_PL2_PLMASK_HI(u8HwOffset), CanIcomRxMessageSignalConfig->CanIcomSignalMaskHigh);
            /* Write value for CAN_PL2_PLMASK_LO register */
            REG_WRITE32(FLEXCAN_CAN_PL2_PLMASK_LO(u8HwOffset), CanIcomRxMessageSignalConfig->CanIcomSignalMaskLow);
        }
        /* ======================================== Configure mode for PNET================================================= */

        /* Configure the CAN_CTRL1_PN[WTOF_MSK] */
    #if (CAN_43_FLEXCAN_PRETENDED_TIMEOUT_CHECK==STD_ON)
        if (0U != u32Timercount)
        {
            u32RegisterValue = FLEXCAN_CTRL1_PN_WTOF_U32;
        }
        else
        {
            u32RegisterValue = 0U;
        }
    #endif
        /* Configure the CAN_CTRL1_PN[WUMF_MSK] */
        u32RegisterValue = u32RegisterValue | FLEXCAN_CTRL1_PN_WUMF_U32;
        /* Filtering by both ID and payload */
        if ((boolean)TRUE == CanIcomRxMessageConfig->CanFiltPayload)
        {
            /* Configure the CAN_CTRL1_PN[PLFS] */
            switch(CanIcomRxMessageSignalConfig->CanIcomSignalOperation)
            {
                case (EQUAL):
                    /* Excatly payload filtering type */
                    u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_EXACTLY_PAYLOAD_U32;
                    break;
                case (GREATER):
                    /* Greater payload filtering type */
                    u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_GREATER_PAYLOAD_U32;
                    break;
                case (SMALLER):
                    /* Smaller payload filtering type */
                    u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_SMALLER_PAYLOAD_U32;
                    break;
                case (XOR):
                    /* Inside range payload filtering type */
                    u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_INSIDE_RANGE_PAYLOAD_U32;
                    break;
                default:
                    /* Prevent misra */
                    break;
            }
            u32RegisterValue = u32RegisterValue | (uint32)0x01U; /* mask for payload */
        }
        /* Configure the CAN_CTRL1_PN[IDFS] */
        switch(CanIcomRxMessageConfig->CanIcomIdOperation)
        {
            case (EXACTLY):
                /* Excatly ID filtering type */
                u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_EXACTLY_ID_U32;
                break;
            case (GREATER_MINNUM):
                /* Greater ID filtering type */
                u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_GREATER_ID_U32;
                break;
            case (SMALLER_MAXNUM):
                /* Smaller ID filtering type */
                u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_SMALLER_ID_U32;
                break;
            case (INSIDE_RANGE):
                /* Inside range ID filtering type */
                u32RegisterValue = u32RegisterValue|(uint32)FLEXCAN_INSIDE_RANGE_ID_U32;
                break;
            default:
                /* Prevent misra */
                break;
        }
        /* Configuration information for the combination type */
    #if (CAN_43_FLEXCAN_PRETENDED_COUNT_MESSAGE==STD_ON)
        u32RegisterValue = u32RegisterValue | (uint32)0x02U | (((uint32)CanIcomRxMessageConfig->CanIcomCounterValue) << 8U);
    #endif
        /* Write the configuration information in the CAN_CTRL1_PN register */
        REG_WRITE32(FLEXCAN_CAN_CTRL1_PN(u8HwOffset), (uint32)u32RegisterValue);

        /* Change Can Controller back to normal mode */
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);
        u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif

        while ( (FLEXCAN_MCR_FRZACK_U32 == ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
                (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
            )
        {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            u32TotalElapsedTime++;
#else
            (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
            u32TotalElapsedTime += u32ElapsedTime;
#endif
        }

        if (u32TotalElapsedTime < Can_u32TicksDelayDuration)
        {
            eReturnValue = (Std_ReturnType)E_OK;
        }
    }
    return (eReturnValue);
}


/*================================================================================================*/
/*
* @brief          Set controller into normal mode with the ConfigurationID equal 0.
* @details        When the user use the Can_SetIcomConfiguration() with ConfigurationID equal 0. The Pretended Networking is disabled.
*                 This routine is called by:
*                  - Can_SetIcomConfiguration() from Can.c file.
*
* @param[in]      Controller    CAN controller for which the init shall be done.
*
* @return        Std_ReturnType Result of the clock switch operation.
* @retval        E_OK  Configure was ok.
* @retval        E_NOT_OK  Configure was not ok.
*
* @pre            Driver must be initialized and all the controllers must be in Stop state.
*
* @note           At the momen, Just have Calypso to support this feature, base on ASR421.
*/

FUNC(Std_ReturnType, CAN_CODE) Can_FlexCan_DeactivateIcom( VAR(uint8, AUTOMATIC) u8Controller)
{
    VAR(uint32, AUTOMATIC)          u8HwOffset = 0U;
    VAR(uint32, AUTOMATIC)          u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    static VAR(TickType, AUTOMATIC)        u32CurrentValue = 0U;
    static VAR(TickType, AUTOMATIC)        u32ElapsedTime = 0U;
#endif
    /* Variable for return status. */
    VAR(Std_ReturnType, AUTOMATIC) eReturnValue = (Std_ReturnType)E_NOT_OK;

    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8Controller].u8ControllerOffset;
    /* [SWS_CAN_00471] Pretended Networking shall be deactivated (i.e. CanDrv shall behave as when it is configured without Pretended Networking support) by calling Can_SetIcomConfiguration() with a configuration ID = 0. */
    /* put controller into the Freeze mode */

    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);
    REG_BIT_SET32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);

    u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
    (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
    while ( (FLEXCAN_MCR_FRZACK_U32 != ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
            (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
          )
    {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            u32TotalElapsedTime++;
#else
            (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
            u32TotalElapsedTime += u32ElapsedTime;
#endif
    }

    if (u32TotalElapsedTime < Can_u32TicksDelayDuration)
    {
        /* Deactivate the PNET mode */
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_PNET_ENABLE_U32);
        Can_43_FLEXCAN_ControllerStatuses[u8Controller].eCanIcomState = CAN_FLEXCAN_ICOM_DEACTIVATED;

        /* put controller out to the Freeze mode */
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_HALT_U32);
        REG_BIT_CLEAR32( FLEXCAN_MCR(u8HwOffset), FLEXCAN_MCR_FRZ_U32);

        u32TotalElapsedTime = 0U;
#ifndef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
        (void)GetCounterValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue);
#endif
        while ( (FLEXCAN_MCR_FRZACK_U32 == ((uint32)REG_READ32( FLEXCAN_MCR(u8HwOffset)) & FLEXCAN_MCR_FRZACK_U32)) && \
                (u32TotalElapsedTime < Can_u32TicksDelayDuration) \
            )
        {
#ifdef CAN_43_FLEXCAN_TIMEOUT_AS_LOOP
            u32TotalElapsedTime++;
#else
            (void)GetElapsedValue((CounterType)CAN_43_FLEXCAN_TIMEOUT_COUNTER_NAME, &u32CurrentValue, &u32ElapsedTime);
            u32TotalElapsedTime += u32ElapsedTime;
#endif
        }
        if (u32TotalElapsedTime <= Can_u32TicksDelayDuration)
        {
            eReturnValue = (Std_ReturnType)E_OK;
        }
    }

    return (eReturnValue);
}
/*================================================================================================*/
FUNC(void, CAN_CODE) Can_FlexCan_ProcessWakeupPN( CONST(uint8, AUTOMATIC) u8controller)
{
    VAR(uint32, AUTOMATIC) numbermbtemp = 0U;
    VAR(uint8, AUTOMATIC) u8HwOffset = 0U;
    volatile VAR(uint32, AUTOMATIC) can_numbermb = 0U;
    VAR(uint8, AUTOMATIC) u8CanMbData[8U];
    VAR(uint8, AUTOMATIC) u8DatabyteIndex = 0U;
    /* Identifies the HRH and its corresponding CAN Con-troller. */
    VAR(Can_HwType, AUTOMATIC) Mailbox;
    /* Pointer to the received L-PDU. */
    VAR(PduInfoType, AUTOMATIC) PduInfoPtr;

    u8HwOffset = CanStatic_43_FLEXCAN_pControlerDescriptors[u8controller].u8ControllerOffset;

    if(FLEXCAN_WU_MTC_WUMF_MSK_U32 ==((uint32)REG_READ32(FLEXCAN_CAN_WU_MTC(u8HwOffset)) & FLEXCAN_WU_MTC_WUMF_MSK_U32))
    {
        /* Wake-up by message wake-up */
        REG_WRITE32(FLEXCAN_CAN_WU_MTC(u8HwOffset), FLEXCAN_WU_MTC_WUMF_MSK_W1C);
        /* [SWS_CAN_00468]If Pretended Networking is activated CanDrv shall call CanIf_RxIndication() if and only if the received message matches the wakeup conditions of the CanIcomConfig (see CanIcomWakeupCauses). */
        can_numbermb = (uint32)(((uint32)REG_READ32(FLEXCAN_CAN_CTRL1_PN(u8HwOffset)) & FLEXCAN_CTRL1_PN_NMATCH_U32) >> 8U);

        if (4U>can_numbermb)
        {
            can_numbermb = can_numbermb;
        }
        else
        {
            can_numbermb = 3U;
        }
        for (numbermbtemp = 0U; numbermbtemp <= can_numbermb; numbermbtemp++)
        {
            if (FLEXCAN_CAN_WMB_CS_IDE_U32 == (uint32)(REG_READ32(FLEXCAN_CAN_WMB_CS(u8HwOffset, (numbermbtemp))) & FLEXCAN_CAN_WMB_CS_IDE_U32))
            {
                Mailbox.CanId = (Can_IdType)(REG_READ32(FLEXCAN_CAN_WMB_ID(u8HwOffset, (numbermbtemp))) & FLEXCAN_CAN_WMB_ID_IDMB_U32);
            }
            else
            {
                Mailbox.CanId = (Can_IdType)((REG_READ32(FLEXCAN_CAN_WMB_ID(u8HwOffset, (numbermbtemp))) & FLEXCAN_CAN_WMB_ID_IDMB_U32) >> FLEXCAN_STANDARD_ID_SHIFT_U32);
            }
            /* ID of the corresponding Hardware Object Range */
            Mailbox.Hoh = (Can_HwHandleType)numbermbtemp;
            /* ControllerId provided by CanIf clearly identify the corresponding controller */
            Mailbox.ControllerId = u8controller;
            /* length of the SDU in bytes */
            PduInfoPtr.SduLength = (uint32)((uint32)(REG_READ32(FLEXCAN_CAN_WMB_CS(u8HwOffset, (numbermbtemp))) & FLEXCAN_CAN_WMB_CS_DLC_U32) >> 16U);
            /* Read the data of wake-up MB */
            for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < (uint8)PduInfoPtr.SduLength; u8DatabyteIndex++)
            {
                switch (u8DatabyteIndex)
                {
                    case (0U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)((((uint32)REG_READ32(FLEXCAN_CAN_WMB_D03(u8HwOffset, (numbermbtemp)))) >> 24U)& (uint32)0xFF);
                        break;
                    case (1U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)((((uint32)REG_READ32(FLEXCAN_CAN_WMB_D03(u8HwOffset, (numbermbtemp)))) >> 16U)& (uint32)0xFF);
                        break;
                    case (2U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)((((uint32)REG_READ32(FLEXCAN_CAN_WMB_D03(u8HwOffset, (numbermbtemp)))) >> 8U)& (uint32)0xFF);
                        break;
                    case (3U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)((((uint32)REG_READ32(FLEXCAN_CAN_WMB_D03(u8HwOffset, (numbermbtemp)))) >> 0U) & (uint32)0xFF);
                        break;
                    case (4U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)(((uint32)REG_READ32(FLEXCAN_CAN_WMB_D47(u8HwOffset, (numbermbtemp))) >> 24U) & (uint32)0xFF);
                        break;
                    case (5U):
                         u8CanMbData[u8DatabyteIndex] = (uint8)(((uint32)REG_READ32(FLEXCAN_CAN_WMB_D47(u8HwOffset, (numbermbtemp))) >> 16U) & (uint32)0xFF);
                        break;
                    case (6U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)(((uint32)REG_READ32(FLEXCAN_CAN_WMB_D47(u8HwOffset, (numbermbtemp))) >> 8U) & (uint32)0xFF);
                        break;
                    case (7U):
                        u8CanMbData[u8DatabyteIndex] = (uint8)(((uint32)REG_READ32(FLEXCAN_CAN_WMB_D47(u8HwOffset, (numbermbtemp))) >> 0U) & (uint32)0xFF);
                        break;
                    default:
                        break;
                }
            }
            PduInfoPtr.SduDataPtr=&u8CanMbData[numbermbtemp];
            CanIf_RxIndication(&Mailbox, &PduInfoPtr );
        }
    }
    if(FLEXCAN_WU_MTC_WTOF_MSK_U32 ==((uint32)REG_READ32(FLEXCAN_CAN_WU_MTC(u8HwOffset)) & FLEXCAN_WU_MTC_WTOF_MSK_U32))
    {
        /* Wake-up by timeout */
        REG_WRITE32(FLEXCAN_CAN_WU_MTC(u8HwOffset), FLEXCAN_WU_MTC_WTOF_MSK_W1C);
    }
}
#endif

#ifdef CAN_43_FLEXCAN_DMA_USED
FUNC(void, CAN_CODE) Can_FlexCan_ProcessDMA(CONST(uint8, AUTOMATIC) u8ControllerId)
{
    /* Local copy of pointer to the controller descriptor. */
    VAR(Can_PtrControlerDescriptorType, AUTOMATIC) pCanControlerDescriptor = NULL_PTR;
    VAR(uint8, AUTOMATIC) u8DmaChannel = 0U;
    /* Number of data bytes. */
    VAR(uint8, AUTOMATIC)      u8MbDataLength = 0U;
    /* Index for data byte of MB. */
    VAR(uint8, AUTOMATIC)      u8DatabyteIndex = 0U;
    /* Physical data bytes. */
#if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
    static VAR(uint8, AUTOMATIC)      u8CanMbData[64U];
#else
    static VAR(uint8, AUTOMATIC)      u8CanMbData[8U];
#endif
    /* Variables for storing the CanID. */
    VAR(Can_IdType, AUTOMATIC) u32MbMessageId = 0U;
    /* Variable for storing the ConfigReg of the MB. */
    VAR(uint32, AUTOMATIC)     u32MbConfig = 0U;
    /* Variable for storing the Hrh. */
    VAR(Can_HwHandleType, AUTOMATIC)      u32MbHrh = 0U;
    /* Variable for indexing all the MBs fron hardware unit chain (all controllers). */
    VAR(uint16, AUTOMATIC)            u16MBGlobalIndex = 0U;
    /* Identifies the HRH and its corresponding CAN Con-troller. */
    static VAR(Can_HwType, AUTOMATIC) Mailbox;
    /* Pointer to the received L-PDU. */
    static VAR(PduInfoType, AUTOMATIC) PduInfoPtr;
    VAR(Can_PtrMBConfigContainerType, AUTOMATIC)   pCanMbConfigContainer = NULL_PTR;
    VAR(uint8, AUTOMATIC)            u8MbCount = 0U;
#if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
    VAR(uint32, AUTOMATIC) u32TimestanpValue = 0U;
#ifdef CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED
    VAR(uint8, AUTOMATIC)    u8TimeStampOffset = 0U;
#endif
#endif
    pCanControlerDescriptor = &Can_43_FLEXCAN_pControlerDescriptors[u8ControllerId];
    u8DmaChannel = pCanControlerDescriptor->u8EnhancedRxFifoDMAChanel;
    pCanMbConfigContainer = &(Can_43_FLEXCAN_pCurrentConfig->MBConfigContainer);

    /* Find the index of first HOH of this controller */
    while ( (u16MBGlobalIndex < (uint16)Can_43_FLEXCAN_pCurrentConfig->uCanFirstHTHIndex) && \
            ((u8ControllerId != ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8ControllerId)) || \
            ((uint8)0U != ((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8HWMBIndex))) \
          )
    {
        u16MBGlobalIndex++;
    }

    for (u8MbCount = 0U; u8MbCount < pCanControlerDescriptor->u8NumberMBTransfer; u8MbCount++)
    {
        /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
        /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
        u32MbConfig = REG_READ32((uint32)(&pCanControlerDescriptor->pDestBuffer[u8MbCount * 80U]));
        u8MbDataLength = (uint8)((u32MbConfig & FLEXCAN_MBCS_LENGTH_U32) >> FLEXCAN_MBCS_LENGTH_SHIFT_U32);
    #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
        if ((((uint8)u8MbDataLength)>=(uint8)FLEXCAN_DATA_LENGTH_MIN_U8) && (((uint8)u8MbDataLength)<=(uint8)FLEXCAN_DATA_LENGTH_MAX_U8))
        {
           u8MbDataLength = Can_Flexcan_aDataLengthMax[(uint8)u8MbDataLength - FLEXCAN_DATA_LENGTH_OFFSET_U8];
        }
    #endif
        /* Prevents that a buffer overflow to be generated by a CAN bus error affecting length field */
        if( u8MbDataLength > (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength )
        {
            u8MbDataLength = (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u8MBPayloadLength;
        }
        /* Get the ID of the message.
          For extended IDs the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
        /* condition to test */
        if ((uint32)0x0U == (u32MbConfig & (uint32)FLEXCAN_MBCS_IDE_U32))
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32MbMessageId = (Can_IdType)((uint32)((((REG_READ32((uint32)(&pCanControlerDescriptor->pDestBuffer[u8MbCount * 80U]) + (uint32)4U))) & (uint32)(FLEXCAN_MBID_ID_STANDARD_U32)) >> (uint32)(18U)));
        }
        else
        {
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32MbMessageId = (Can_IdType)((uint32)(((REG_READ32((uint32)(&pCanControlerDescriptor->pDestBuffer[u8MbCount * 80U]) + (uint32)4U))) & (uint32)(FLEXCAN_MBID_ID_EXTENDED_U32)) | FLEXCAN_MBC_ID_IDE_U32);
        }
        /* Get the ID of the message. For FD the most significant bit mus tbe set - according to Can_IdType requirement - chapter8.2.4 of SWS CAN.*/
        #if (CAN_43_FLEXCAN_FD_MODE_ENABLE == STD_ON)
            if ((uint32)0x0U != ((uint32)(u32MbConfig & (uint32)(FLEXCAN_FD_MB_MESSAGE_U32))))
            {
                u32MbMessageId |= (Can_IdType)CAN_FD_ID_DESCRIPTOR;
            }
        #endif
        
        for ( u8DatabyteIndex = (uint8)0U; u8DatabyteIndex < u8MbDataLength; u8DatabyteIndex++)
        {
            /* Copy the data  */
            u8CanMbData[u8DatabyteIndex] = (pCanControlerDescriptor->pDestBuffer[((uint32)u8MbCount * 80U) + FLEXCAN_DMA_DATA(u8DatabyteIndex)]);
        }
        
        /* Determine Hrh of the message. */
        u32MbHrh = (Can_HwHandleType)((pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).u32HWObjID);
        #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
         /*[SWS_Can_00444] If the L-PDU callout returns false, the L-PDU shall not be processed any further. */
        if ((boolean)TRUE == CAN_43_FLEXCAN_LPduReceiveCalloutFunction((uint8)u32MbHrh, u32MbMessageId, u8MbDataLength, u8CanMbData))
        {
        #endif
        /* Standard/Extended CAN ID of CAN L-PDU */
        Mailbox.CanId = u32MbMessageId;
        /* ID of the corresponding Hardware Object Range */
        Mailbox.Hoh = u32MbHrh;
        /* ControllerId provided by CanIf clearly identify the corresponding controller */
        Mailbox.ControllerId = u8ControllerId;
        /* length of the SDU in bytes */
        PduInfoPtr.SduLength = u8MbDataLength;
        /* pointer to the SDU (i.e. payload data) of the PDU */
        PduInfoPtr.SduDataPtr = u8CanMbData;
        CanIf_RxIndication(&Mailbox, &PduInfoPtr);
        #if (CAN_43_FLEXCAN_LPDU_NOTIFICATION_ENABLE == STD_ON)
        }
        #endif

    #if (defined(CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED) || defined(CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED))
        /* Just notify TS for last Message Buffer */
        if(((boolean)TRUE == (pCanMbConfigContainer->pMessageBufferConfigsPtr[u16MBGlobalIndex]).CanTimestampEnable) &&
            (u8MbCount == pCanControlerDescriptor->u8NumberMBTransfer - (uint8)1U))
        {
        #ifdef CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_USED
            u32TimestanpValue = u32MbConfig & CAN_43_FLEXCAN_MESSAGE_BUFFER_TIMESTAMP_MASK_U32;
        #endif
        
        #ifdef CAN_43_FLEXCAN_HIGH_RESOLUTION_TIMESTAMP_USED
            if ((u8MbDataLength >= (uint8)1U) && (u8MbDataLength <= (uint8)4U))
            {
                u8TimeStampOffset = (uint8)0x10U;
            }
            else if ((u8MbDataLength >= (uint8)5U) && (u8MbDataLength <= (uint8)8U))
            {
                u8TimeStampOffset = (uint8)0x14U;
            }
            else
            {
                /* u8TimeStampOffset = Arbitration length + u8MbDataLength + ID HIT length */
                u8TimeStampOffset = (uint8)8U + u8MbDataLength + (uint8)4U;
            }
            /* @violates @ref Can_Flexcan_c_REF_3 MISRA 2012 Advisory Rule 11.4 */
            /* @violates @ref Can_Flexcan_c_REF_4 MISRA 2012 Required Rule 11.6 */
            /* @violates @ref Can_Flexcan_c_REF_5 MISRA 2012 Required Rule 10.8 */
            u32TimestanpValue = REG_READ32((uint32)(&pCanControlerDescriptor->pDestBuffer[u8MbCount * 80U]) + (uint32)u8TimeStampOffset);
        #endif
            Can_43_FLEXCAN_pCurrentConfig->CanRxTimestampNotification(u32MbHrh, u32TimestanpValue);
        }
    #endif
    }
    Mcl_DmaEnableHwRequest(u8DmaChannel);
}
#endif

#define CAN_43_FLEXCAN_STOP_SEC_CODE
/* @violates @ref Can_Flexcan_c_REF_1 MISRA 2012 Required Directive 4.10 */
/* @violates @ref Can_Flexcan_c_REF_2 MISRA 2012 Advisory Rule 20.1 */
#include "Can_43_FLEXCAN_MemMap.h"

#ifdef __cplusplus
}
#endif

/** @} */
