/**
*   @file    Reg_eSys_Fccu.h
*   @implements     Reg_eSys_Fccu.h_Artifact
*
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcem - FCCU register definitions
*   @details FCCUv2 HW-related definitions
*
*   @addtogroup MCEM_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : Fccu
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifndef REG_ESYS_FCCU_H
#define REG_ESYS_FCCU_H

#ifdef __cplusplus
extern "C"{
#endif

/**
 *
 * @page misra_violations MISRA-C:2004 violations
 *
 * @section Reg_eSys_Fccu_h_REF_1
 * Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
 * Used to address array of similar registers.
 *
 * @section [global]
 * Violates MISRA 2004 Required Rule 5.1, Exceeds 31 characters due to AUTOSAR compatibility
 */


/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Reg_eSys.h"

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/

#define FCCU_REG_VENDOR_ID                    43
#define FCCU_REG_AR_RELEASE_MAJOR_VERSION     4
#define FCCU_REG_AR_RELEASE_MINOR_VERSION     3
#define FCCU_REG_AR_RELEASE_REVISION_VERSION  1
#define FCCU_REG_SW_MAJOR_VERSION             1
#define FCCU_REG_SW_MINOR_VERSION             0
#define FCCU_REG_SW_PATCH_VERSION             0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
/* Check if current file and Reg_eSys.h header file are the same Autosar version */
    #if ((FCCU_REG_AR_RELEASE_MAJOR_VERSION != REG_ESYS_AR_RELEASE_MAJOR_VERSION) || \
         (FCCU_REG_AR_RELEASE_MINOR_VERSION != REG_ESYS_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Reg_eSys_Fccu.h Reg_eSys.h are different"
    #endif
#endif

/*==================================================================================================
*                                          CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      DEFINES AND MACROS
==================================================================================================*/
/*
*  FCCU Key to enter Config State
*/
#define FCCU_OP1_KEY_U32                   ((uint32)0x913756AFUL)
/*
*  FCCU Key to enter Normal State
*/
#define FCCU_OP2_KEY_U32                   ((uint32)0x825A132BUL)
/*
*  FCCU Key to unlock the config registers
*/
#define FCCU_TRANS_LOCK_KEY_U32            ((uint32)0x000000BCUL)
/*
*  FCCU Key to Clear a fault
*/
#define FCCU_NCF_CLR_KEY_U32               ((uint32)0xAB3498FEUL)
/*
*  FCCU Key to Permanent lock the configuration
*/
#define FCCU_PERM_LOCK_KEY_U32             ((uint32)0x000000FFUL)



/*
*  FCCU Control Register - R/W always
*/
#define FCCU_CTRL_ADDR32                   ((uint32)(FCCU_BASEADDR))
/*
*  FCCU CTRL Key Register - W always
*/
#define FCCU_CTRLK_ADDR32                  ((uint32)(FCCU_BASEADDR + (uint32)0x0004UL))
/*
*  FCCU Configuration Register - R always;W in CONFIG state only
*/
#define FCCU_CFG_ADDR32                    ((uint32)(FCCU_BASEADDR + (uint32)0x0008UL))
/*
*  FCCU NCF Configuration Register - R always;W in CONFIG state only
*/
#define FCCU_NCF_CFG0_ADDR32               ((uint32)(FCCU_BASEADDR + (uint32)0x001CUL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_NCF_CFG_ADDR32(add)             ((uint32)(FCCU_NCF_CFG0_ADDR32 + (((uint32)(add))<<2U)))
/*
*  FCCU NCFS Configuration Register - R always;W in CONFIG state only
*/
#define FCCU_NCFS_CFG0_ADDR32              ((uint32)(FCCU_BASEADDR + (uint32)0x004CUL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_NCFS_CFG_ADDR32(add)             ((uint32)(FCCU_NCFS_CFG0_ADDR32 + (((uint32)(add))<<2U)))
/*
*  FCCU NCF Status Register - R/W always
*/
#define FCCU_NCF_S0_ADDR32                 ((uint32)(FCCU_BASEADDR + (uint32)0x0080UL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_NCF_S_ADDR32(add)             ((uint32)(FCCU_NCF_S0_ADDR32 + (((uint32)(add))<<2U)))
/*
*  FCCU NCF Key Register - W always
*/
#define FCCU_NCFK_ADDR32                   ((uint32)(FCCU_BASEADDR + (uint32)0x0090UL))
/*
*  FCCU NCF Enable Register - R always;W in CONFIG state only
*/
#define FCCU_NCF_E0_ADDR32                 ((uint32)(FCCU_BASEADDR + (uint32)0x0094UL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_NCF_E_ADDR32(add)             ((uint32)(FCCU_NCF_E0_ADDR32 + (((uint32)(add))<<2U)))

/*
*  FCCU NCF Time-out Enable Register - R always;W in CONFIG state only
*/
#define FCCU_NCF_TOE0_ADDR32               ((uint32)(FCCU_BASEADDR + (uint32)0x00A4UL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_NCF_TOE_ADDR32(add)            ((uint32)(FCCU_NCF_TOE0_ADDR32 + (((uint32)(add))<<2U)))

/*
*  FCCU NCF Time-out Register - R always;W in CONFIG state only
*/
#define FCCU_NCF_TO_ADDR32                 ((uint32)(FCCU_BASEADDR + (uint32)0x00B4UL))
/*
*  FCCU CFG Timeout Register - R always;W in CONFIG state only
*/
#define FCCU_CFG_TO_ADDR32                 ((uint32)(FCCU_BASEADDR + (uint32)0x00B8UL))
/*
*  FCCU IO Control Register
*/
#define FCCU_EINOUT_ADDR32                 ((uint32)(FCCU_BASEADDR + (uint32)0x00BCUL))
/*
*  FCCU Status Register - R always
*/
#define FCCU_STAT_ADDR32                   ((uint32)(FCCU_BASEADDR + (uint32)0x00C0UL))
/*
*  FCCU NA Freeze Status Register
*/
#define FCCU_N2AF_STATUS_ADDR32            ((uint32)(FCCU_BASEADDR + (uint32)0x00C4UL))
#define FCCU_A2FF_STATUS_ADDR32            ((uint32)(FCCU_BASEADDR + (uint32)0x00C8UL))
#define FCCU_N2FF_STATUS_ADDR32            ((uint32)(FCCU_BASEADDR + (uint32)0x00CCUL))
#define FCCU_F2A_STATUS_ADDR32             ((uint32)(FCCU_BASEADDR + (uint32)0x00D0UL))
/*
*  FCCU NCF Fake Register - W always
*/
#define FCCU_NCFF_ADDR32                   ((uint32)(FCCU_BASEADDR + (uint32)0x00DCUL))
/*
*  FCCU IRQ Status Register - R/W always
*/
#define FCCU_IRQ_STAT_ADDR32               ((uint32)(FCCU_BASEADDR + (uint32)0x00E0UL))
/*
*  FCCU IRQ Enable Register - R/W always
*/
#define FCCU_IRQ_EN_ADDR32                 ((uint32)(FCCU_BASEADDR + (uint32)0x00E4UL))
/*
*  FCCU XTMR Register - R always
*/
#define FCCU_XTMR_ADDR32                   ((uint32)(FCCU_BASEADDR + (uint32)0x00E8UL))
/*
*  FCCU MCS Register - R always
*/
#define FCCU_MCS_ADDR32                    ((uint32)(FCCU_BASEADDR + (uint32)0x00ECUL))
/*
*  FCCU Transient Lock Register - W always
*/
#define FCCU_TRANS_LOCK_ADDR32             ((uint32)(FCCU_BASEADDR + (uint32)0x00F0UL))
/*
*  FCCU Permanent Lock Register - W always
*/
#define FCCU_PERMNT_LOCK_ADDR32            ((uint32)(FCCU_BASEADDR + (uint32)0x00F4UL))
/*
*  FCCU Delta T Register - R always;W in CONFIG state only
*/
#define FCCU_DELTA_T_ADDR32                ((uint32)(FCCU_BASEADDR + (uint32)0x00F8UL))
/*
*  FCCU IRQ Alarm Enable registers
*/
#define FCCU_IRQ_ALARM_EN0_ADDR32          ((uint32)(FCCU_BASEADDR + (uint32)0x00FCUL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_IRQ_ALARM_EN_ADDR32(add)      ((uint32)(FCCU_IRQ_ALARM_EN0_ADDR32 + (((uint32)(add))<<2U)))

/*
*  FCCU NMI Enable Registers
*/
#define FCCU_NMI_EN0_ADDR32                ((uint32)(FCCU_BASEADDR + (uint32)0x010CUL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_NMI_EN_ADDR32(add)            ((uint32)(FCCU_NMI_EN0_ADDR32 + (((uint32)(add))<<2U)))

/*
*  FCCU EOUT Signaling Enable Registers
*/
#define FCCU_EOUT_SIG_EN0_ADDR32           ((uint32)(FCCU_BASEADDR + (uint32)0x011CUL))
/* @violates @ref Reg_eSys_Fccu_h_REF_1 Function-like macro defined. */
#define FCCU_EOUT_SIG_EN_ADDR32(add)      ((uint32)(FCCU_EOUT_SIG_EN0_ADDR32 + (((uint32)(add))<<2U)))

/* FCCU CTRL glitch filter bitfields masks */
#define FCCU_CTRL_GLITCH_FILTER_BYPASS_MASK_U32  ((uint32)(0x80000000UL))
#define FCCU_CTRL_GLITCH_FILTER_WIDTH_MASK_U32   ((uint32)(0x60000000UL))

/*FCCU CTRL Default values available to be written mask*/
#define FCCU_CTRL_DEFAULT_VALUES_MASK   ((uint32)(0xC0UL))

/* Fccu operation status description */
#define FCCU_OPS_IDLE_U32         ((uint32)(0x00000000UL))
#define FCCU_OPS_IN_PROGRESS_U32  ((uint32)(0x00000040UL))
#define FCCU_OPS_ABORT_U32        ((uint32)(0x00000080UL))
#define FCCU_OPS_SUCCESSFUL_U32   ((uint32)(0x000000C0UL))
#define FCCU_OPS_MASK_U32         ((uint32)(0x000000C0UL))

/* Fccu status field description */
#define FCCU_STATUS_MASK_U32      ((uint32)(0x00000007UL))
#define FCCU_NORMAL_STATE_U32     ((uint32)(0x00000000UL))
#define FCCU_CONFIG_STATE_U32     ((uint32)(0x00000001UL))
#define FCCU_ALARM_STATE_U32      ((uint32)(0x00000002UL))
#define FCCU_FAULT_STATE_U32      ((uint32)(0x00000003UL))

/* FCCU Configuration Timeout IRQ Status and Enable masks */
#define FCCU_TO_IRQ_MASK_U32             ((uint32)(0x00000001UL))
#define FCCU_TO_IRQ_ENABLE_MASK_U32      ((uint32)(0x00000001UL))

/* FCCU Alarm IRQ status mask */
#define FCCU_ALARM_IRQ_MASK_U32   ((uint32)1UL << 1)

/* FCCU NMI IRQ status mask */
#define FCCU_NMI_IRQ_MASK_U32   ((uint32)1UL << 2)

/* FCCU_DELTA_T reserved bits register mask */
#define FCCU_DELTA_T_RESERVED_MASK_U32   ((uint32)(0x00003FFFUL))

/* FCCU CFG WRITE ABLE mask */
#ifdef ERR_IPV_FCCU_0004
#if (ERR_IPV_FCCU_0004 == STD_ON)
#define FCCU_CFG_DIS_AFTER_RESET_BIT_MASK_U32   ((uint32)(0x00C007C0UL))
#define FCCU_CFG_EN_AFTER_RESET_BIT_MASK_U32    ((uint32)(0x01C007C0UL))
#endif
#endif

/*==================================================================================================
*                                             ENUMS
==================================================================================================*/
/**
* @brief          Fccu Operation type
* @details        Fccu can execute different operations, as changing it's state to Config or to Normal mode,
*                 read frozen registers, etc.
*/
typedef enum
{
    FCCU_NO_OPERATION                 =  0,
    FCCU_ENTER_CONFIG_STATE           =  1,
    FCCU_ENTER_NORMAL_STATE           =  2,
    FCCU_READ_FCCU_STATE              =  3,
    FCCU_READ_N2AF_STATUS             =  4,
    FCCU_READ_A2FF_STATUS             =  5,
    FCCU_READ_N2FF_STATUS             =  6,
    FCCU_READ_F2AF_STATUS             =  7,
    FCCU_READ_FCCU_SCFS               =  8,
    FCCU_RESERVED_0                   =  9,
    FCCU_READ_NCFS                    = 10,
    FCCU_RESERVED_1                   = 11,
    FCCU_NCF_CLEAR_IN_PROGRESS        = 12,
    FCCU_CLEAR_FREEZE_STATUS_REGS     = 13,
    FCCU_CONFIG_TO_NORMAL_IN_PROGRESS = 14,
    FCCU_CLEAR_OPERATION_STATUS       = 15,
    FCCU_RESERVED_2                   = 16,
    FCCU_READ_ALARM_TIMER             = 17,
    FCCU_RESERVED_3                   = 18,
    FCCU_READ_CFG_TIMER               = 19
} FccuOpType;                         

/*==================================================================================================
*                                STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/


/*==================================================================================================
*                                GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/


/*==================================================================================================
*                                    FUNCTION PROTOTYPES
==================================================================================================*/

#ifdef __cplusplus
}
#endif

#endif /*REG_ESYS_FCCU_H*/

/** @} */
