/**
*   @file    Mcl_Dma.h
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcl - eDMA low level header.
*   @details Low level header for eDMA module.
*
*   @addtogroup MCL_DMA_DRIVER
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/


#ifndef MCL_DMA_H
#define MCL_DMA_H

#ifdef __cplusplus
extern "C"{
#endif

/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and namespace shall be distinct.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, A function should be used in preference to a function-like macro where they are interchangeable.
* Function like macro are used to reduce code complexity.
*
* @section Mcl_Dma_h_REF_1
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once.
* This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement [SWS_MemMap_00003].
*
* @section Mcl_Dma_h_REF_2
* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
* Macros are used only in some configurations or for future releases.
*/

/*==================================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Std_Types.h"
#include "Mcl_Dma_Types.h"
#include "Reg_eSys_Dma.h"


/*==================================================================================================
*                               SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define MCL_DMA_VENDOR_ID                    43

#define MCL_DMA_AR_RELEASE_MAJOR_VERSION     4
#define MCL_DMA_AR_RELEASE_MINOR_VERSION     3
#define MCL_DMA_AR_RELEASE_REVISION_VERSION  1
#define MCL_DMA_SW_MAJOR_VERSION             1
#define MCL_DMA_SW_MINOR_VERSION             0
#define MCL_DMA_SW_PATCH_VERSION             0
/**@}*/

/*==================================================================================================
*                                      FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if source file and Std_Types.h are of the same Autosar version */
    #if ((MCL_DMA_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
         (MCL_DMA_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
        #error "AutoSar Version Numbers of Mcl_Dma.h and Std_Types.h are different"
    #endif
#endif

/* Check if header file and CDD_Mcl_Cfg.h header file are of the same vendor */
#if (MCL_DMA_VENDOR_ID != MCL_DMA_TYPES_VENDOR_ID)
    #error "Mcl_Dma.h and Mcl_Dma_Types.h have different vendor ids"
#endif
/* Check if header file and CDD_Mcl_Cfg.h header file are of the same Autosar version */
#if ((MCL_DMA_AR_RELEASE_MAJOR_VERSION    != MCL_DMA_TYPES_AR_RELEASE_MAJOR_VERSION) || \
     (MCL_DMA_AR_RELEASE_MINOR_VERSION    != MCL_DMA_TYPES_AR_RELEASE_MINOR_VERSION) || \
     (MCL_DMA_AR_RELEASE_REVISION_VERSION != MCL_DMA_TYPES_AR_RELEASE_REVISION_VERSION))
    #error "AutoSar Version Numbers of Mcl_Dma.h and Mcl_Dma_Types.h are different"
#endif
/* Check if header file and CDD_Mcl_Cfg.h header file are of the same software version */
#if ((MCL_DMA_SW_MAJOR_VERSION != MCL_DMA_TYPES_SW_MAJOR_VERSION) || \
     (MCL_DMA_SW_MINOR_VERSION != MCL_DMA_TYPES_SW_MINOR_VERSION) || \
     (MCL_DMA_SW_PATCH_VERSION != MCL_DMA_TYPES_SW_PATCH_VERSION))
    #error "Software Version Numbers of Mcl_Dma.h and Mcl_Dma_Types.h are different"
#endif

/* Check if header file and Reg_eSys_Dma.h header file are of the same vendor */
#if (MCL_DMA_VENDOR_ID != DMA_VENDOR_ID_REG)
    #error "Mcl_Dma.h and Reg_eSys_Dma.h have different vendor ids"
#endif
/* Check if header file and Reg_eSys_Dma.h header file are of the same Autosar version */
#if ((MCL_DMA_AR_RELEASE_MAJOR_VERSION    != DMA_AR_RELEASE_MAJOR_VERSION_REG) || \
     (MCL_DMA_AR_RELEASE_MINOR_VERSION    != DMA_AR_RELEASE_MINOR_VERSION_REG) || \
     (MCL_DMA_AR_RELEASE_REVISION_VERSION != DMA_AR_RELEASE_REVISION_VERSION_REG))
    #error "AutoSar Version Numbers of Mcl_Dma.h and Reg_eSys_Dma.h are different"
#endif
/* Check if header file and Reg_eSys_Dma.h header file are of the same software version */
#if ((MCL_DMA_SW_MAJOR_VERSION != DMA_SW_MAJOR_VERSION_REG) || \
     (MCL_DMA_SW_MINOR_VERSION != DMA_SW_MINOR_VERSION_REG) || \
     (MCL_DMA_SW_PATCH_VERSION != DMA_SW_PATCH_VERSION_REG))
    #error "Software Version Numbers of Mcl_Dma.h and Reg_eSys_Dma.h are different"
#endif

/*==================================================================================================
*                                           CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                       DEFINES AND MACROS
==================================================================================================*/

#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)

/**
* @brief enable DMA request for this channel
*/
#define DMA_ENABLE_REQUEST(CHANNEL)             (REG_WRITE8(DMAV2_SERQ_ADDR32(DMA_MOD_IDX_U32(CHANNEL)), (uint8)(((CHANNEL)) & DMA_CTRL_MAX_CHANNELS_MASK_U32)))
/**
* @brief disable DMA request for this channel
*/
#define DMA_DISABLE_REQUEST(CHANNEL)            (REG_WRITE8(DMAV2_CERQ_ADDR32(DMA_MOD_IDX_U32((CHANNEL))), (uint8)(((CHANNEL)) & DMA_CTRL_MAX_CHANNELS_MASK_U32)))
/**
* @brief clear the interrupt request for a given channel
*/
#define DMA_CLEAR_INT_REQ(CHANNEL)              (REG_WRITE8(DMAV2_CINT_ADDR32(DMA_MOD_IDX_U32((CHANNEL))), (uint8)(((CHANNEL)) & DMA_CTRL_MAX_CHANNELS_MASK_U32)))

#define DMA_CLEAR_INT_ERR_REQ(CHANNEL)          (REG_WRITE8(DMAV2_CERR_ADDR32((DMA_MOD_IDX_U32((CHANNEL)))), DMAV2_CERR_CAEI_U8))

/* ============================================================================================================================= */
/** @brief macros used to update certain fields of a TCD */
/* ============================================================================================================================= */
/**
* @brief update source address for a TCD
*/
#define DMA_TCD_UPDATE_SADDR(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE32((TCD_ADDR) + DMA_TCD_1ST_WORD_OFFSET_U32, ((NEW_VALUE))))


/**
* @brief Get source address for a CHANNEL
*/
#define DMA_GET_SADDR(TCD_ADDR) \
    (REG_READ32((TCD_ADDR) + DMA_TCD_1ST_WORD_OFFSET_U32))

/**
* @brief update source modulo for a TCD
*/
#define DMA_TCD_UPDATE_SMOD(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_2ND_WORD_OFFSET_U32, DMA_SMOD_MASK_U32 << DMA_SMOD_SHIFT_MASK_U32, ((NEW_VALUE)) << DMA_SMOD_SHIFT_MASK_U32))

/**
* @brief update source transfer size for a TCD
*/
#define DMA_TCD_UPDATE_SSIZE(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_2ND_WORD_OFFSET_U32, DMA_SSIZE_MASK_U32 << DMA_SSIZE_SHIFT_MASK_U32, ((NEW_VALUE)) << DMA_SSIZE_SHIFT_MASK_U32))


/**
* @brief update destination modulo for a TCD
*/
#define DMA_TCD_UPDATE_DMOD(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_2ND_WORD_OFFSET_U32, DMA_DMOD_MASK_U32 << DMA_DMOD_SHIFT_MASK_U32, ((NEW_VALUE)) << DMA_DMOD_SHIFT_MASK_U32))

/**
* @brief update destination transfer size for a TCD
*/
#define DMA_TCD_UPDATE_DSIZE(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_2ND_WORD_OFFSET_U32, DMA_DSIZE_MASK_U32 << DMA_DSIZE_SHIFT_MASK_U32, ((NEW_VALUE)) << DMA_DSIZE_SHIFT_MASK_U32))

/**
* @brief update source offset for a TCD
*/
#define DMA_TCD_UPDATE_SOFF(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_2ND_WORD_OFFSET_U32, DMA_SOFF_MASK_U32, ((NEW_VALUE))))

/**
* @brief update number of bytes to be transferred for a TCD
*/
#define DMA_TCD_UPDATE_NBYTES(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE32((TCD_ADDR) + DMA_TCD_3RD_WORD_OFFSET_U32, ((NEW_VALUE))))

/**
* @brief update number of bytes to be transferred for a TCD
*/
#define DMA_TCD_UPDATE_MLOFFYES(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE32((TCD_ADDR) + DMA_TCD_3RD_WORD_OFFSET_U32, ((NEW_VALUE))))

/**
* @brief update last source address adjustment for a TCD
*/
#define DMA_TCD_UPDATE_SLAST(TCD_ADDR, NEW_VALUE) \
   (REG_WRITE32((TCD_ADDR) + DMA_TCD_4TH_WORD_OFFSET_U32, ((NEW_VALUE))))

/**
* @brief update destination address for a TCD
*/
#define DMA_TCD_UPDATE_DADDR(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE32((TCD_ADDR) + DMA_TCD_5TH_WORD_OFFSET_U32, ((NEW_VALUE))))

/**
* @brief update destination address for a CHANNEL
*/
#define DMA_UPDATE_DADDR(CHANNEL, NEW_VALUE)    (DMA_TCD_UPDATE_DADDR(DMA_TCD((CHANNEL)), (NEW_VALUE)))

/**
* @brief Get destination address
*/
#define DMA_GET_DADDR(TCD_ADDR) \
    (REG_READ32((TCD_ADDR) + DMA_TCD_5TH_WORD_OFFSET_U32))

/**
* @brief update destination offset for a TCD
*/
#define DMA_TCD_UPDATE_DOFF(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32, DMA_DOFF_MASK_U32, ((NEW_VALUE))))

/**
* @brief update last destination address adjustment for a TCD
*/
#define DMA_TCD_UPDATE_DLAST_SGA(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE32((TCD_ADDR) + DMA_TCD_7TH_WORD_OFFSET_U32, (NEW_VALUE)))

/**
* @brief update last destination address adjustment for a CHANNEL
*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_UPDATE_DLAST_SGA(CHANNEL, NEW_VALUE)    (DMA_TCD_UPDATE_DLAST_SGA(DMA_TCD((CHANNEL)), (NEW_VALUE)))

/* ============================================================================================================================= */
/** @brief Macros for CITER field of TCD number 6 */
/* ============================================================================================================================= */
/** @brief set the citer.e_link bit for a TCD*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_SET_CITER_ELINK(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_6TH_WORD_OFFSET_U32, DMA_TCD_ITER_ELINK_U32))

/** @brief clear the citer.e_link bit for a CHANNEL*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_CLR_CITER_ELINK(CHANNEL) \
    (REG_BIT_CLEAR32(DMA_TCD((CHANNEL)) + DMA_TCD_6TH_WORD_OFFSET_U32, DMA_TCD_ITER_ELINK_U32))

/** @brief update TCD.citer_linkch*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_SET_CITER_LINKCH(CHANNEL, LINKED_CHANNEL) \
      (REG_RMW32(DMA_TCD(((CHANNEL))) + DMA_TCD_6TH_WORD_OFFSET_U32, DMA_MAJOR_LINKCH_MASK_U32 << DMA_MAJOR_LINKCH_SHIFT_MASK_U32, (LINKED_CHANNEL) << DMA_ITER_LINKCH_SHIFT_MASK_U32))

#define DMA_TCD_UPDATE_CITER(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32, DMA_CITER_MASK_U32 << DMA_ITER_SHIFT_MASK_U32, (NEW_VALUE)))

/** This macro will set CITER for Tcd the elink bit in TCD number 6 with elink bit = 1*/
#define DMA_TCD_SET_CITER_ELINK_ON(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32, (DMA_CITER_MASK_ON_U32 << DMA_ITER_SHIFT_MASK_U32), ((NEW_VALUE)) << DMA_ITER_SHIFT_MASK_U32))

/** This macro will set CITER for Tcd the elink bit in TCD number 6 with elink bit = 0 */
#define DMA_TCD_SET_CITER_ELINK_OFF(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32, (DMA_CITER_MASK_OFF_U32 << DMA_ITER_SHIFT_MASK_U32), ((NEW_VALUE)) << DMA_ITER_SHIFT_MASK_U32))

#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)
#define DMA_GET_CH_CITER(CHANNEL) \
    (REG_READ16((uint32)(DMA_TCD((CHANNEL))) + DMA_TCD_6TH_WORD_OFFSET_U32 + DMA_TCD_CITER_OFFSET_U32))
#else
#define DMA_GET_CH_CITER(CHANNEL) \
    (REG_READ32((uint32)(DMA_TCD((CHANNEL))) + DMA_TCD_6TH_WORD_OFFSET_U32 + DMA_TCD_CITER_OFFSET_U32) >> DMA_ITER_SHIFT_MASK_U32)
#endif

/** This macro will return the elink bit in TCD number 6 */
#define DMA_TCD_GET_CITER_ELINK(TCD_ADDR) \
    (REG_BIT_GET16((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32 + DMA_TCD_CITER_OFFSET_U32, DMA_TCD_ITER_ELINK_U16))

/** This macro will return the CITER field with elink_bit = 1 in TCD number 6 */
#define DMA_TCD_GET_CITER_ON(TCD_ADDR) \
    (REG_READ16((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32 + DMA_TCD_CITER_OFFSET_U32) & DMA_CITER_MASK_ON_U16)

/** This macro will return the CITER field with elink_bit = 0 in TCD number 6 */
#define DMA_TCD_GET_CITER_OFF(TCD_ADDR) \
    (REG_READ16((TCD_ADDR) + DMA_TCD_6TH_WORD_OFFSET_U32 + DMA_TCD_CITER_OFFSET_U32) & DMA_CITER_MASK_OFF_U16)

/* ============================================================================================================================= */
/** @brief Macros for BITER field of TCD number 8 */
/* ============================================================================================================================= */

#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)
#define DMA_TCD_UPDATE_BITER(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE16((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_BITER_OFFSET_U32, (NEW_VALUE)))
#else
#define DMA_TCD_UPDATE_BITER(TCD_ADDR, NEW_VALUE) \
    (REG_WRITE16((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32, (NEW_VALUE)))
#endif


/** @brief set the biter.e_link bit from a TCD */
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_SET_BITER_ELINK(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_ITER_ELINK_U32))

/** @brief clear the biter.e_link bit from a TCD */
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_CLR_BITER_ELINK(CHANNEL) \
    (REG_BIT_CLEAR32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_ITER_ELINK_U32))

/** @brief update TCD.biter_linkch from a TCD */
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_SET_BITER_LINKCH(CHANNEL, LINKED_CHANNEL) \
    (REG_RMW32(DMA_TCD(((CHANNEL))) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_MAJOR_LINKCH_MASK_U32 << DMA_MAJOR_LINKCH_SHIFT_MASK_U32, (LINKED_CHANNEL) << DMA_ITER_LINKCH_SHIFT_MASK_U32))

#define DMA_TCD_SET_BITER_ELINK_ON(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32, (DMA_BITER_MASK_ON_U32 << DMA_ITER_SHIFT_MASK_U32), ((NEW_VALUE)) << DMA_ITER_SHIFT_MASK_U32))

#define DMA_TCD_SET_BITER_ELINK_OFF(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32, (DMA_BITER_MASK_OFF_U32 << DMA_ITER_SHIFT_MASK_U32), ((NEW_VALUE)) << DMA_ITER_SHIFT_MASK_U32))

#if (LOW_BYTE_FIRST == CPU_BYTE_ORDER)
#define DMA_GET_CH_BITER(CHANNEL) \
    (REG_READ16((uint32)(DMA_TCD((CHANNEL))) + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_BITER_OFFSET_U32))
#else
#define DMA_GET_CH_BITER(CHANNEL) \
    (REG_READ32((uint32)(DMA_TCD((CHANNEL))) + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_BITER_OFFSET_U32) >> DMA_ITER_SHIFT_MASK_U32)
#endif

#define DMA_TCD_GET_BITER_ELINK(TCD_ADDR) \
    (REG_BIT_GET16((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_BITER_OFFSET_U32, DMA_TCD_ITER_ELINK_U16))

/* ============================================================================================================================= */
/** @brief Macros for CRS field of TCD number 8 */
/* ============================================================================================================================= */
/** @brief update TCD.major_linkch*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_UPDATE_MAJOR_LINKCH(CHANNEL, NEW_VALUE) \
    (REG_RMW32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_MAJOR_LINKCH_MASK_U32<<DMA_MAJOR_LINKCH_SHIFT_MASK_U32, ((NEW_VALUE))<<DMA_MAJOR_LINKCH_SHIFT_MASK_U32))
/** @brief returns the value of DONE bit from word 7 of TCD for eDMA2 or from CH_CSR for eDMA3*/
#define DMA_DONE(CHANNEL)           (REG_BIT_GET32(DMA_TCD_CHANNEL(((CHANNEL)), (uint32) DMA_TCD_8TH_WORD_OFFSET_U32), DMA_TCD_DONE_U32))
/** sets the EEI bit for the specified channel */
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMAV3_SET_EEI(CHANNEL) \
    (REG_BIT_SET32(DMAV3_CH_CSR_ADDR((CHANNEL)), DMAV3_CH_CSR_EEI_U32))

/** clears the EEI bit for the specified channel */
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMAV3_CLEAR_EEI(CHANNEL) \
    (REG_BIT_CLEAR32(DMAV3_CH_CSR_ADDR((CHANNEL)), DMAV3_CH_CSR_EEI_U32))

/** @brief returns the value of ACTIVE bit */
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_ACTIVE(CHANNEL)             (REG_BIT_GET32(DMA_TCD_CHANNEL(((CHANNEL)), (uint32) DMA_TCD_8TH_WORD_OFFSET_U32), DMA_TCD_ACTIVE_U32))
/** @brief clear DONE bit in TCD*/
#define DMA_CLR_DONE(CHANNEL)           (REG_BIT_CLEAR32(DMA_TCD_CHANNEL(((CHANNEL)), (uint32) DMA_TCD_8TH_WORD_OFFSET_U32), DMA_TCD_DONE_U32))

/** @brief set the TCD.e_sg bit*/
#define DMA_SET_E_SG(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_E_SG_U32))

/** @brief clear the TCD.e_sg bit*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_CLR_E_SG(CHANNEL) \
    (REG_BIT_CLEAR32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_E_SG_U32))

/** @brief set the major.e_link bit from TCD*/
#define DMA_SET_MAJOR_ELINK(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_MAJOR_E_LINK_U32))

/** @brief clear the major.e_link bit from TCD*/
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_CLR_MAJOR_ELINK(CHANNEL) \
    (REG_BIT_CLEAR32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_MAJOR_E_LINK_U32))

/** @brief set the TCD.int_maj bit*/
#define DMA_SET_INT_MAJ(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_INT_MAJOR_U32))

/** @brief set the TCD.int_maj bit*/
#define DMA_TCD_SET_INT_MAJ(TCD_ADDR) \
    (REG_BIT_SET32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_INT_MAJOR_U32))

/** @brief set the TCD.int_half bit */
#define DMA_SET_INT_HALF(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_INT_HALF_U32))

/** @brief clear the TCD.int_maj bit*/
#define DMA_CLR_INT_MAJ(CHANNEL) \
    (REG_BIT_CLEAR32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_INT_MAJOR_U32))

/** @brief clear the TCD.int_maj bit*/
#define DMA_TCD_CLR_INT_MAJ(TCD_ADDR) \
    (REG_BIT_CLEAR32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_INT_MAJOR_U32))

/** @brief clear the TCD.int_half bit*/
#define DMA_CLR_INT_HALF(CHANNEL) \
    (REG_BIT_CLEAR32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_INT_HALF_U32))

/** @brief start transfer*/
#define DMA_START(CHANNEL) \
    (REG_BIT_SET32(DMA_TCD((CHANNEL)) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_START_U32))

#define DMA_TCD_SR(Channel) \
    (REG_READ32((uint32)DMA_TCD_CHANNEL(((Channel)), DMA_TCD_8TH_WORD_OFFSET_U32)))

#define DMA_TCD_GET_INT_MAJ(channel) \
    ((boolean)(((uint32)DMA_TCD_INT_MAJOR_U32 == (uint32)(DMA_TCD_SR((channel)) & DMA_TCD_INT_MAJOR_U32))? TRUE : FALSE))

#define DMA_TCD_GET_INT_HALF(channel) \
    ((boolean)(((uint32)DMA_TCD_INT_HALF_U32 == (uint32)(DMA_TCD_SR((channel)) & DMA_TCD_INT_HALF_U32))? TRUE : FALSE))

#define DMA_TCD_SET_FLAGS(TCD_ADDR, NEW_VALUE) \
    (REG_RMW32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32, DMA_TCD_FLAGS_MASK_U32, (NEW_VALUE)))

#define DMA_TCD_GET_FLAGS(TCD_ADDR) \
    (REG_READ32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32) & DMA_TCD_FLAGS_MASK_U32)

/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_TCD_GET_CH(TCD_ADDR) \
    (REG_READ32((TCD_ADDR) + DMA_TCD_8TH_WORD_OFFSET_U32) & DMA_TCD_FLAGS_MASK_U32)
/* @violates @ref Mcl_Dma_h_REF_2 MISRA 2012 Advisory 2.5*/
#define DMA_REG_PROT_SIZE ((uint32)0x4U)
/** @} */
/*==================================================================================================
*                                             ENUMS
==================================================================================================*/

/*==================================================================================================
*                                 STRUCTURES AND OTHER TYPEDEFS
==================================================================================================*/


/*==================================================================================================
*                                 GLOBAL VARIABLE DECLARATIONS
==================================================================================================*/

/*==================================================================================================
*                                     FUNCTION PROTOTYPES
==================================================================================================*/
#define MCL_START_SEC_CODE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


FUNC(void, MCL_CODE) Mcl_Dma_Init( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance);

#if (MCL_DEINIT_API == STD_ON)
FUNC(void, MCL_CODE) Mcl_Dma_DeInit( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance);
#endif

FUNC(void, MCL_CODE) Mcl_Dma_ConfigChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                        P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor);

FUNC(void, MCL_CODE) Mcl_Dma_ConfigTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                    P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor);

FUNC(void, MCL_CODE) Mcl_Dma_ConfigLinkedChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                              P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                              VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel);

FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                                     P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                     P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd);

FUNC(void, MCL_CODE) Mcl_Dma_ConfigLinkedTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                          P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                          VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel);

FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                                 P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                 P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd);

FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherLinkedChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                                           P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                           P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd,
                                                           VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel);
FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherLinkedTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                                       P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                       P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd,
                                                       VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel);

FUNC(void, MCL_CODE) Mcl_Dma_SetChannelPriority( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel,
                                             VAR(Mcl_DmaPriorityType, AUTOMATIC) nPriority);

FUNC(void, MCL_CODE) Mcl_Dma_StartChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel);

FUNC(boolean, MCL_CODE) Mcl_Dma_IsTransferCompleted( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel);

FUNC(boolean, MCL_CODE) Mcl_Dma_IsTransferActive( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel);

#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
FUNC (void, MCL_CODE) Mcl_Dma_EnableNotification(VAR(Mcl_DmaChannelType,AUTOMATIC) nChannel,
                                             VAR(Mcl_DmaTransferNotifType,AUTOMATIC) Notification);

FUNC (void, MCL_CODE) Mcl_Dma_DisableNotification(VAR(Mcl_DmaChannelType,AUTOMATIC) nChannel);
#endif

FUNC (boolean, MCL_CODE) Mcl_Dma_GetMultiRegChInfo(VAR(Mcl_DmaChannelType,AUTOMATIC) nChannel,
                                                 VAR(Mcl_DmaRequestType,AUTOMATIC) request);
#if (MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON)
FUNC (void, MCL_CODE) Mcl_Dma_GetGlobalErrorStatus
(
    VAR(Mcl_DmaInstanceType, AUTOMATIC) dmaInstance,
    P2VAR(Mcl_DmaGlobalErrorStatusType, AUTOMATIC, MCL_APPL_DATA) dmaGlobalErrorStatus
);
#endif

#if ((MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON) || (MCL_DMA_GET_CH_ERR_STATUS_API == STD_ON))
FUNC(Mcl_DmaChannelErrorStatusType, MCL_CODE) Mcl_Dma_GetChannelErrorStatus
(
    VAR(Mcl_DmaChannelType,AUTOMATIC) hwChannel
);
#endif

#if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
FUNC (Mcl_DmaChannelType, MCL_CODE) Mcl_Dma_GetNumChannelError(Mcl_DmaInstanceType dma_instance);
#endif

#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
FUNC (uint32, MCL_CODE) Mcl_GetPhysicalAddress(VAR(uint32, AUTOMATIC) logicalAddr);
#endif /*MCL_LOGICAL_ADDRESS_USED == STD_ON*/

#if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
    #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
        FUNC(void, MCL_CODE) Mcl_Dma_Set_User_Access (VAR(uint32, AUTOMATIC) address);
    #endif
#endif
#define MCL_STOP_SEC_CODE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#endif
#endif

#ifdef __cplusplus
}
#endif

#endif /* MCL_DMA_H */

/** @} */

