/**
*   @file           Pwm_eMios.c
*   @version        1.0.0
*
*   @brief          AUTOSAR Pwm - PWM eMIOS API.
*   @details        PWM eMIOS API.
*
*   @addtogroup     PWM_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eMios
*   Dependencies         : none
*
*   AUTOSAR Version      : 4.3.1
*   AUTOSAR Revision     : ASR_REL_4_3_REV_0001
*   AUTOSAR Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifdef __cplusplus
extern "C" {
#endif

/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space shall be distinct.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
* The used compilers use more than 31 chars for identifiers.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
* The used compilers use more than 31 chars for identifiers.
*
* @section Pwm_eMios_c_REF_1
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor directives or comments.
* <MA>_MemMap.h is included after each section define in order to set the current memory section as defined by AUTOSAR.
*
* @section Pwm_eMios_c_REF_2
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header
* file being included more than once.
* This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement [SWS_MemMap_00003].
*
* @section Pwm_eMios_c_REF_3
* Violates MISRA 2012 Advisory Rule 8.7, Functions and objects should not be defined with external linkage 
* if they are referenced in only one translation unit.
* These functions represent the ISRs of the driver. External linkage is needed to "export" the ISRs
* to let the application register them in the IVT (interrupt vector table).
*
* @section Pwm_eMios_c_REF_4
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer 
* to object and an integer type.
* The cast is used to access memory mapped registers.
*
* @section Pwm_eMios_c_REF_5
* Violates MISRA 2012 Required Rule 11.6, Cast from unsigned long to pointer.
*
* @section Pwm_eMios_c_REF_6
* Violates MISRA 2012 Required Rule 10.8, Impermissible cast of composite expression (different essential type categories)
*
* @section Pwm_eMios_c_REF_7
* Violates MISRA 2012 Required Rule 2.2, There shall be no dead code
*
*/



/*===============================================================================================
*                                         INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
===============================================================================================*/

#include "Std_Types.h"

#include "Reg_eSys_eMios.h"
#include "eMios_Common_Types.h"
#include "eMios_Common.h"

#include "Pwm_eMios.h"

#include "Pwm_Ipw_Types.h"
#include "Pwm_Ipw_Notif.h"

#define USER_MODE_REG_PROT_ENABLED  (PWM_ENABLE_USER_MODE_SUPPORT)
#include "SilRegMacros.h"
#include "SchM_Pwm.h"



/*===============================================================================================
*                                        LOCAL MACROS
===============================================================================================*/

/**
* @{
* @file           Pwm_eMios.c
*/
#define PWM_EMIOS_C_VENDOR_ID                      43
#define PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION       4
#define PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION       3
#define PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION    1
#define PWM_EMIOS_C_SW_MAJOR_VERSION               1
#define PWM_EMIOS_C_SW_MINOR_VERSION               0
#define PWM_EMIOS_C_SW_PATCH_VERSION               0
/**@}*/



/*===============================================================================================
*                                      FILE VERSION CHECKS
===============================================================================================*/

/* Check if source file and Pwm_eMios.h are of the same vendor */
#if (PWM_EMIOS_C_VENDOR_ID != PWM_EMIOS_VENDOR_ID)
    #error "Pwm_eMios.c and Pwm_eMios.h have different vendor IDs."
#endif

/* Check if source file and Pwm_eMios.h are of the same AUTOSAR version */
#if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != PWM_EMIOS_AR_RELEASE_MAJOR_VERSION) || \
        (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != PWM_EMIOS_AR_RELEASE_MINOR_VERSION) || \
        (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != PWM_EMIOS_AR_RELEASE_REVISION_VERSION))
    #error "AUTOSAR Version Numbers of Pwm_eMios.c and Pwm_eMios.h are different"
#endif

/* Check if source file and Pwm_eMios.h are of the same software version */
#if ((PWM_EMIOS_C_SW_MAJOR_VERSION != PWM_EMIOS_SW_MAJOR_VERSION) || \
        (PWM_EMIOS_C_SW_MINOR_VERSION != PWM_EMIOS_SW_MINOR_VERSION) || \
        (PWM_EMIOS_C_SW_PATCH_VERSION != PWM_EMIOS_SW_PATCH_VERSION))
    #error "Software Version Numbers of Pwm_eMios.c and Pwm_eMios.h are different"
#endif

#if (PWM_EMIOS_C_VENDOR_ID != PWM_IPW_NOTIF_VENDOR_ID)
    #error "Pwm_Emios.c and Pwm_Ipw_Notif.h have different vendor ids"
#endif

/* Check if source file and Pwm_Ipw_Notif header file are of the same AUTOSAR version */
#if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != PWM_IPW_NOTIF_AR_RELEASE_MAJOR_VERSION) || \
        (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != PWM_IPW_NOTIF_AR_RELEASE_MINOR_VERSION) || \
        (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != PWM_IPW_NOTIF_AR_RELEASE_REVISION_VERSION))
    #error "AUTOSAR Version Numbers of Pwm_Emios.c and Pwm_Ipw_Notif.h are different"
#endif

/* Check if source file and Pwm_Ipw_Notif header file are of the same software version */
#if ((PWM_EMIOS_C_SW_MAJOR_VERSION != PWM_IPW_NOTIF_SW_MAJOR_VERSION) || \
        (PWM_EMIOS_C_SW_MINOR_VERSION != PWM_IPW_NOTIF_SW_MINOR_VERSION) || \
        (PWM_EMIOS_C_SW_PATCH_VERSION != PWM_IPW_NOTIF_SW_PATCH_VERSION))
    #error "Software Version Numbers of Pwm_eMios.c and Pwm_Ipw_Notif.h are different"
#endif

/* Check if source file and Pwm_Ipw_Types.h are of the same vendor */
#if (PWM_EMIOS_C_VENDOR_ID != PWM_IPW_TYPES_VENDOR_ID)
    #error "Pwm_eMios.c and Pwm_Ipw_Types.h have different vendor ids"
#endif

/* Check if source file and Pwm_Ipw_Types.h are of the same AUTOSAR version */
#if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != PWM_IPW_TYPES_AR_RELEASE_MAJOR_VERSION) || \
     (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != PWM_IPW_TYPES_AR_RELEASE_MINOR_VERSION) || \
     (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != PWM_IPW_TYPES_AR_RELEASE_REVISION_VERSION))
    #error "AUTOSAR Version Numbers of Pwm_eMios.c and Pwm_Ipw_Types.h are different"
#endif

/* Check if source file and Pwm_Ipw_Types.h are of the same software version */
#if ((PWM_EMIOS_C_SW_MAJOR_VERSION != PWM_IPW_TYPES_SW_MAJOR_VERSION) || \
     (PWM_EMIOS_C_SW_MINOR_VERSION != PWM_IPW_TYPES_SW_MINOR_VERSION)  || \
     (PWM_EMIOS_C_SW_PATCH_VERSION != PWM_IPW_TYPES_SW_PATCH_VERSION))
    #error "Software Version Numbers of Pwm_eMios.c and Pwm_Ipw_Types.h are different"
#endif

#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    /* Check if source file and Reg_eSys_eMios.h are of the same vendor */
    #if (PWM_EMIOS_C_VENDOR_ID != REG_ESYS_EMIOS_VENDOR_ID)
        #error "Pwm_eMios.c and Reg_eSys_eMios.h have different vendor ids"
    #endif

    /* Check if source file and Reg_eSys_eMios.h are of the same AUTOSAR version */
    #if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != REG_ESYS_EMIOS_AR_RELEASE_MAJOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != REG_ESYS_EMIOS_AR_RELEASE_MINOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != REG_ESYS_EMIOS_AR_RELEASE_REVISION_VERSION))
        #error "AUTOSAR Version Numbers of Pwm_eMios.c and Reg_eSys_eMios.h are different"
    #endif

    /* Check if source file and Reg_eSys_eMios.h are of the same software version */
    #if ((PWM_EMIOS_C_SW_MAJOR_VERSION != REG_ESYS_EMIOS_SW_MAJOR_VERSION) || \
            (PWM_EMIOS_C_SW_MINOR_VERSION != REG_ESYS_EMIOS_SW_MINOR_VERSION)  || \
            (PWM_EMIOS_C_SW_PATCH_VERSION != REG_ESYS_EMIOS_SW_PATCH_VERSION))
        #error "Software Version Numbers of Pwm_eMios.c and Reg_eSys_eMios.h are different"
    #endif

    /* Check if source file and eMios_Common_Types.h are of the same vendor */
    #if (PWM_EMIOS_C_VENDOR_ID != EMIOS_COMMON_TYPES_VENDOR_ID )
        #error "Pwm_eMios.c and eMios_Common_Types.h have different vendor ids"
    #endif
    
    /* Check if source file and eMios_Common_Types.h are of the same AUTOSAR version */
    #if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != EMIOS_COMMON_TYPES_AR_RELEASE_MAJOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != EMIOS_COMMON_TYPES_AR_RELEASE_MINOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != EMIOS_COMMON_TYPES_AR_RELEASE_REVISION_VERSION))
        #error "AUTOSAR Version Numbers of Pwm_eMios.c and eMios_Common_Types.h are different"
    #endif
    
    /* Check if source file and eMios_Common_Types.h are of the same software version */
    #if ((PWM_EMIOS_C_SW_MAJOR_VERSION != EMIOS_COMMON_TYPES_SW_MAJOR_VERSION) || \
            (PWM_EMIOS_C_SW_MINOR_VERSION != EMIOS_COMMON_TYPES_SW_MINOR_VERSION)  || \
            (PWM_EMIOS_C_SW_PATCH_VERSION != EMIOS_COMMON_TYPES_SW_PATCH_VERSION))
        #error "Software Version Numbers of Pwm_eMios.c and eMios_Common_Types.h are different"
    #endif

    /* Check if source file and SilRegMacros.h are of the same vendor */
    #if (PWM_EMIOS_C_VENDOR_ID != SILREGMACROS_VENDOR_ID )
        #error "Pwm_eMios.c and SilRegMacros.h have different vendor ids"
    #endif

    /* Check if source file and SilRegMacros.h are of the same AUTOSAR version */
    #if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != SILREGMACROS_AR_RELEASE_MAJOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != SILREGMACROS_AR_RELEASE_MINOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != SILREGMACROS_AR_RELEASE_REVISION_VERSION))
        #error "AUTOSAR Version Numbers of Pwm_eMios.c and SilRegMacros.h are different"
    #endif

    /* Check if source file and SilRegMacros.h are of the same software version */
    #if ((PWM_EMIOS_C_SW_MAJOR_VERSION != SILREGMACROS_SW_MAJOR_VERSION) || \
            (PWM_EMIOS_C_SW_MINOR_VERSION != SILREGMACROS_SW_MINOR_VERSION)  || \
            (PWM_EMIOS_C_SW_PATCH_VERSION != SILREGMACROS_SW_PATCH_VERSION))
        #error "Software Version Numbers of Pwm_eMios.c and SilRegMacros.h are different"
    #endif

    /* Check if source file and eMios_Common.h are of the same vendor */
    #if (PWM_EMIOS_C_VENDOR_ID != EMIOS_COMMON_VENDOR_ID )
        #error "Pwm_eMios.c and eMios_Common.h have different vendor ids"
    #endif

    /* Check if source file and eMios_Common.h are of the same AUTOSAR version */
    #if ((PWM_EMIOS_C_AR_RELEASE_MAJOR_VERSION != EMIOS_COMMON_AR_RELEASE_MAJOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_MINOR_VERSION != EMIOS_COMMON_AR_RELEASE_MINOR_VERSION) || \
            (PWM_EMIOS_C_AR_RELEASE_REVISION_VERSION != EMIOS_COMMON_AR_RELEASE_REVISION_VERSION))
        #error "AUTOSAR Version Numbers of Pwm_eMios.c and eMios_Common.h are different"
    #endif

    /* Check if source file and eMios_Common.h are of the same software version */
    #if ((PWM_EMIOS_C_SW_MAJOR_VERSION != EMIOS_COMMON_SW_MAJOR_VERSION) || \
            (PWM_EMIOS_C_SW_MINOR_VERSION != EMIOS_COMMON_SW_MINOR_VERSION)  || \
            (PWM_EMIOS_C_SW_PATCH_VERSION != EMIOS_COMMON_SW_PATCH_VERSION))
        #error "Software Version Numbers of Pwm_eMios.c and eMios_Common.h are different"
    #endif
#endif


#if (PWM_EMIOS_USED == STD_ON)



/*===============================================================================================
*                                       GLOBAL VARIABLES
===============================================================================================*/

#define PWM_START_SEC_VAR_NO_INIT_UNSPECIFIED
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"

/**
* @brief        Array holding the polarity for configured eMIOS channels
*
*/
static VAR(Pwm_OutputStateType, PWM_VAR) Pwm_eMios_aChannelPolarity[PWM_EMIOS_CHANNELS_MAX_U8];

#if ((PWM_DE_INIT_API == STD_ON) || (PWM_SET_OUTPUT_TO_IDLE_API == STD_ON) || (PWM_FEATURE_DAOC == STD_ON))
/**
* @brief        Array holding the idle state for configured eMIOS channels
*
*/
static VAR(Pwm_OutputStateType, PWM_VAR) Pwm_eMios_aChannelIdleState[PWM_EMIOS_CHANNELS_MAX_U8];
#endif

/**
* @brief        Array used to store the current period for all eMIOS channels
*
*/
static VAR(Pwm_PeriodType, PWM_VAR) Pwm_eMios_aChannelPeriod[PWM_EMIOS_CHANNEL_NO];

#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))
/**
* @brief        Array used to store the current offset for configured eMIOS channels
*
*/
static VAR(Pwm_PeriodType, PWM_VAR) Pwm_eMios_aChannelOffset[PWM_EMIOS_CHANNELS_MAX_U8];
#endif

#if (PWM_FEATURE_DAOC == STD_ON)
/**
* @brief        Array used to store the duty cycle for each PWM channel in DAOC mode
*
*/
static VAR(Pwm_PeriodType, PWM_VAR) Pwm_eMios_aDaocChannelDuty[PWM_EMIOS_CHANNEL_NO];
#endif

#if (PWM_FEATURE_DAOC == STD_ON)
/**
* @brief        Array used to store the current modulo for each PWM channel for updating the register A in DAOC mode
*
*/
static VAR(Pwm_PeriodType, PWM_VAR) Pwm_DAOC_aChannelModulo[PWM_EMIOS_CHANNEL_NO];
#endif

#if (PWM_FEATURE_OPWMT == STD_ON)
/**
* @brief        Array used to store the current trigger delay value
*
*/
static VAR(Pwm_PeriodType, PWM_VAR) Pwm_eMios_aTriggerDelay[PWM_EMIOS_CHANNELS_MAX_U8];
#endif

#define PWM_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"



#define PWM_START_SEC_VAR_NO_INIT_32
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
/**
* @brief        Array used to store the current duty cycle state
* @details      Allowable parameters are:
*               1 - duty cycle != 0%, 100% - signal toggling
*               0 - duty cycle == 0%, 100% - signal is stable state - no transition available
*/
static VAR(uint32, PWM_VAR) Pwm_eMios_aDutyState[PWM_EMIOS_MODULE_NO];
#endif

#define PWM_STOP_SEC_VAR_NO_INIT_32
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"



#define PWM_START_SEC_VAR_NO_INIT_16
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"

#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
/**
* @brief        Array of the duty value of configured eMIOS channels
*
*/
static VAR(uint16, PWM_VAR) Pwm_eMios_aChannelDuty[PWM_EMIOS_CHANNELS_MAX_U8];
#endif

#define PWM_STOP_SEC_VAR_NO_INIT_16
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"



#define PWM_START_SEC_VAR_NO_INIT_8
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
/**
* @brief        Array used to store the notification status (enabled/disabled) and type
* @details      Status and type of notification if enabled for each eMIOS channel
*               - PWM_RISING_EDGE,
*               - PWM_FALLING_EDGE,
*               - PWM_BOTH_EDGES,
*               - 0xFF for disabled
*/
static VAR(uint8, PWM_VAR) Pwm_eMios_aChannelNotifType[PWM_EMIOS_CHANNEL_NO];
#endif

#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
/**
* @brief        Array used to store next channel state
*
*/
static VAR(uint8, PWM_VAR) Pwm_eMios_aNextDutyState[PWM_EMIOS_CHANNELS_MAX_U8];

/**
* @brief        Array used to store the output update disable status
* @details      Allowable parameters are:
*               1 - disabled
*               0 - enabled
*/
static VAR(uint8, PWM_VAR) Pwm_eMios_aOutputUpdateDisable[PWM_EMIOS_CHANNELS_MAX_U8];
#endif

#define PWM_STOP_SEC_VAR_NO_INIT_8
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"



/*===============================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
===============================================================================================*/

LOCAL_INLINE FUNC(Pwm_eMios_ChannelType, PWM_CODE) Pwm_eMios_GetMasterBus
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32Bus
);



/*=============================================================================================*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_UpdateChannelAB
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    VAR         (uint32,                        AUTOMATIC)                      u32RegAVal,
    VAR         (uint32,                        AUTOMATIC)                      u32RegBVal
);



/*=============================================================================================*/
#if (PWM_FEATURE_OPWMT == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_UpdateChannelB
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    VAR         (uint32,                        AUTOMATIC)                      u32RegBVal
);
#endif /* PWM_FEATURE_OPWMT */



/*=============================================================================================*/
#if (PWM_FEATURE_OPWMCB == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWMCB_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_OPWMCB */



/*=============================================================================================*/
#if (PWM_FEATURE_DAOC == STD_ON)   
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_DAOC_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_DAOC */



/*=============================================================================================*/
#if (PWM_FEATURE_OPWMT == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWMT_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_OPWMT */



/*=============================================================================================*/
#if (PWM_FEATURE_OPWMB == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWMB_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_OPWMB */



/*=============================================================================================*/
#if (PWM_FEATURE_OPWM == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWM_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_OPWM */



/*=============================================================================================*/
#if (PWM_FEATURE_OPWFMB == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWFMB_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_OPWFMB */



/*=============================================================================================*/
#if (PWM_FEATURE_OPWFM == STD_ON)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWFM_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
);
#endif /* PWM_FEATURE_OPWFM */



/*===============================================================================================*/
#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
LOCAL_INLINE FUNC(Pwm_PeriodType, PWM_CODE) Pwm_eMios_ComputeDutycycle_16bits
(
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle
);
#else
LOCAL_INLINE FUNC(Pwm_PeriodType, PWM_CODE) Pwm_eMios_ComputeDutycycle_32bits
(
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle
);
#endif



/*===============================================================================================*/
#if ((PWM_SET_COUNTER_BUS_API == STD_ON) && \
     (PWM_EMIOS_16_BITS_VARIANT == STD_OFF) && \
     ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON)))
static FUNC(Pwm_uint64, PWM_CODE) Pwm_eMios_Div64
(
    VAR         (Pwm_uint64,                    AUTOMATIC)                      nNume, 
    VAR         (Pwm_uint64,                    AUTOMATIC)                      nDeno
);
#endif



/*===============================================================================================*/
#if ((PWM_FEATURE_OPWFM == STD_ON) || \
     (PWM_FEATURE_OPWM == STD_ON) || \
     (PWM_FEATURE_DAOC == STD_ON) || \
     (PWM_FEATURE_OPWMT == STD_ON) || \
     (PWM_FEATURE_OPWMCB == STD_ON))
static FUNC(void, PWM_CODE) Pwm_eMios_HandlePolarityBit
(
    VAR         (Pwm_OutputStateType,           AUTOMATIC)                      ePolarity,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal
);
#endif



/*===============================================================================================
*                                       LOCAL FUNCTIONS
===============================================================================================*/

#define PWM_START_SEC_CODE
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"


/**
* @brief        Function to return the channel ID that configured to be the 
*               master bus of current channel
*
* @param        u8ModuleIdx     eMIOS module index
*               u8ChannelIdx    eMIOS unified channel index
*               u32Bus          Channel bus type
*
* @return       Pwm_eMios_ChannelType
*
*/
LOCAL_INLINE FUNC(Pwm_eMios_ChannelType, PWM_CODE) Pwm_eMios_GetMasterBus
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32Bus
)
{
    /** @brief  Variable store return value for channel ID of master bus */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      n8MasterBusIdx;
    
    
    if (PWM_BUS_DIVERSE_U32 == u32Bus)
    {
        if (EMIOS_CHANNEL_7 >= u8ChannelIdx) /* Bus B */
        {
            n8MasterBusIdx = (Pwm_eMios_ChannelType)(((uint32)u8ModuleIdx << EMIOS_MOD_SHIFT) + EMIOS_CHANNEL_0);
        }
        else if (EMIOS_CHANNEL_15 >= u8ChannelIdx) /* Bus C */
        {
            n8MasterBusIdx = (Pwm_eMios_ChannelType)(((uint32)u8ModuleIdx << EMIOS_MOD_SHIFT) + EMIOS_CHANNEL_8);
        }
        else if (EMIOS_CHANNEL_23 >= u8ChannelIdx) /* Bus D */
        {
            n8MasterBusIdx = (Pwm_eMios_ChannelType)(((uint32)u8ModuleIdx << EMIOS_MOD_SHIFT) + EMIOS_CHANNEL_16);
        }
        else /* Bus E */
        {
            n8MasterBusIdx = (Pwm_eMios_ChannelType)(((uint32)u8ModuleIdx << EMIOS_MOD_SHIFT) + EMIOS_CHANNEL_24);
        }
    }
    else if (PWM_BUS_A_U32 == u32Bus) /* Bus A */
    {
        n8MasterBusIdx = (Pwm_eMios_ChannelType)(((uint32)u8ModuleIdx << EMIOS_MOD_SHIFT) + EMIOS_CHANNEL_23);
    } 
    else if (PWM_BUS_F_U32 == u32Bus) /* Bus F */
    {
        n8MasterBusIdx = (Pwm_eMios_ChannelType)(((uint32)u8ModuleIdx << EMIOS_MOD_SHIFT) + EMIOS_CHANNEL_22);
    }
    else
    {
        n8MasterBusIdx = (Pwm_eMios_ChannelType)0U;
    }
    
    return n8MasterBusIdx;
    
}



/*===============================================================================================*/
/**
* @brief        Function to update the A and B registers in a critical section
* @details      This function disables the transfer, updates the register A
*               and register B and enables the transfer
*
* @param        u8ModuleIdx     eMIOS module index
*               u8ChannelIdx    eMIOS unified channel index
*               u32RegAVal      eMIOS Reg A value to be updated
*               u32RegBVal      eMIOS Reg B value to be updated
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_UpdateChannelAB
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    VAR         (uint32,                        AUTOMATIC)                      u32RegAVal,
    VAR         (uint32,                        AUTOMATIC)                      u32RegBVal
)
{
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_BIT_SET32(EMIOS_OUDR_ADDR32(u8ModuleIdx), (uint32)((uint32)1 << (u8ChannelIdx)));

    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), (u32RegAVal));

    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), (u32RegBVal));

#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    if (eSyncUpdate == PWM_EMIOS_UPDATE_SYNCHRONOUS)
    {
        /* Do nothing */
    }
    else
    {
#endif
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_OUDR_ADDR32(u8ModuleIdx), (uint32)((uint32)1 << (u8ChannelIdx)));
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    }
#endif
}



/*===============================================================================================*/
#if (PWM_FEATURE_OPWMT == STD_ON)
/**
* @brief        Function to update the B registers in a critical section, only for OPWMT mode
* @details      This function disables the transfer, updates register B and enables the transfer
*
* @param        u8ModuleIdx     eMIOS module index
*               u8ChannelIdx    eMIOS unified channel index
*               u32RegAVal      eMIOS Reg A value to be updated
*               u32RegBVal      eMIOS Reg B value to be updated
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_UpdateChannelB
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    VAR         (uint32,                        AUTOMATIC)                      u32RegBVal
)
{
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_BIT_SET32(EMIOS_OUDR_ADDR32(u8ModuleIdx), (uint32)((uint32)1 << (u8ChannelIdx)));

    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), (u32RegBVal));
    
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    if (eSyncUpdate == PWM_EMIOS_UPDATE_SYNCHRONOUS)
    {
        /* Do nothing */
    }
    else
    {
#endif
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_OUDR_ADDR32(u8ModuleIdx), (uint32)((uint32)1 << (u8ChannelIdx)));
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    }
#endif
}
#endif /* PWM_FEATURE_OPWMT */



/*===============================================================================================*/
#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
/**
* @brief        Function to compute the duty cycle
* @details      This function computes the absolute 16-bit duty cycle value in ticks
*               that will be updated in eMIOS register
*
* @param        nPeriod         eMIOS unified channel period (ticks)
*               u16DutyCycle    eMIOS unified channel duty cycle (ticks)
*
* @return       Pwm_PeriodType
*
*/
LOCAL_INLINE FUNC(Pwm_PeriodType, PWM_CODE) Pwm_eMios_ComputeDutycycle_16bits
(
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle
)
{
    
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nDutyCycle;
    VAR         (uint32,                        AUTOMATIC)                      u32TempVal;

    
    u32TempVal = (uint32)((uint32)nPeriod * (uint32)u16DutyCycle);
    nDutyCycle = (Pwm_PeriodType)((uint32)u32TempVal >> (Pwm_PeriodType)15U);

    return nDutyCycle;
    
}

#else

/**
* @brief        Function to compute the duty cycle
* @details      This function computes the absolute 16-bit duty cycle value in ticks
*               that will be updated in eMIOS register
*
* @param        nPeriod         eMIOS unified channel period (ticks)
*               u16DutyCycle    eMIOS unified channel duty cycle (ticks)
*
* @return       Pwm_PeriodType
*
*/
LOCAL_INLINE FUNC(Pwm_PeriodType, PWM_CODE) Pwm_eMios_ComputeDutycycle_32bits
(
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle
)
{
    
    VAR         (uint32,                        AUTOMATIC)                      u32DutyCycle;
    VAR         (uint32,                        AUTOMATIC)                      u32PeriodHigh;
    VAR         (uint32,                        AUTOMATIC)                      u32PeriodLow;

    
    /* Get the 8-bit MSB of 24-bit value stored on nPeriod */
    u32PeriodHigh = (nPeriod >> (uint32)16U); 
    
    /* Get the 16-bit LSB of 24-bit value stored on nPeriod */
    u32PeriodLow  = (uint16)(nPeriod);
    
    u32DutyCycle  = (uint32)((uint32)(u32PeriodHigh * (uint32)u16DutyCycle) << 1U) + (uint32)((uint32)(u32PeriodLow * (uint32)u16DutyCycle) >> 15U);

    return u32DutyCycle;
    
}
#endif



/*===============================================================================================*/
#if (PWM_FEATURE_OPWMCB == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow OPWMCB mode
* @details      This function:
*                   - Calculate the duty tick follow nPeriod and u16DutyCycle
*                   - Disable the interrupt and clear the interrupt flags
*                   - Set the A register with value (nPeriod + 1) and B register with 0 for 0% duty cycle
*                   - Set the A register with value 1 and B register with 0 for 100% duty cycle
*                   - For duty cycle not equal to 0% and 100%, set the A with value indicating duty cycle 
*                     and B register with value indicating deadtime. In this case the period is indicated 
*                     by register A of master bus
*                   - In 0% duty, we need correct duty cycle when user switch 100% duty to 0% duty. In
*                     this case, the A register is switched from 1 to (nPeriod + 1), so the match A
*                     may be never occurred, so the output will be keep the old level. In this case, we
*                     need force match by set the FORCE_MATCH_A bit or FORCE_MATCH_B, follow the mode 
*                     is Lead Dead Time or Trail Dead Time
*                   - If notification is needed, setup EDGE selection with configuration of notification
*                   - If come from IDLE state or Un-Init state:
*                       + Write to RegControl with OPMCB mode
*                       + If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                         after that, EDPOL bit is restored valid value
*                       + Else, polarity and mode bits is written into Cn simultaneously
*                   - Reset counter to value 0, because in OPWMCB mode, internal counter alway start from 0
*                   - Enable prescaler and start counter
*
* @param        nPeriod             - PWM signal period value
*               u16DutyCycle        - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig - Pointer to channel configuration data
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWMCB_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nRegDuty;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nRegDeadtime;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempPeriod;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint32,                        AUTOMATIC)                      u32DutyCorrection;
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif


    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;

    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;
    
    nTempPeriod = nPeriod;
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];
#endif

#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nTempPeriod, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nTempPeriod, u16DutyCycle);
#endif

    /* Divide by 2 and increment with 1 as counter always starts at 1 */
    nTempPeriod = (nTempPeriod >> (Pwm_PeriodType)1U) + 1U;

    /* When duty is computed to 1, the output channel should be put to 0% */
    if ((Pwm_PeriodType)1U == nTempDuty)
    {
        nTempDuty = (Pwm_PeriodType)0U;
        nRegDuty = (Pwm_PeriodType)0U;
    }
    else
    {
        nRegDuty = nTempDuty >> 1U;
    }

    nRegDeadtime = (peMiosChannelConfig->nPwmDeadTime);

    if (((uint16)0U == u16DutyCycle) || ((uint16)0U == nTempDuty))
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        u32DutyCorrection = REG_READ32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx));
        
        /* Write regA with value greater than period to generate 0% duty cycle*/
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (nTempPeriod + (uint32)1U), 
            (uint32)nTempDuty
        );

        /* This statement is required to avoid limitation of 0% duty cycle (if call 100% to 0%) */
        if ((uint32)1U == u32DutyCorrection)
        {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
            {
                /* No transitions in the next signal status but change output level */
                Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)2U;
            }
            else
            {
#endif
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32((EMIOS_OUDR_ADDR32(u8ModuleIdx)), (uint32)((uint32)1 << (u8ChannelIdx)));
                
                if (PWM_MODE_OPWMCB_LEAD_DEADTIME_U32 == ((uint32)u32CtrlRegVal & CCR_MODE_MASK_U32))
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32);
                }
                else
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32);
                }
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            }
#endif
        }
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA with 1 to generate 100% duty cycle */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx,
            u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)1U,
            (uint32)0U
        );
    }
    else
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* Transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)1U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* Transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
        
            if ((uint8)0U != u8Notification) /* if notifications enabled */
            {
                /* FLAG event enabled */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
            else
            {
#endif
                /* Disable and clear interrupt flag */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32 );
             
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx) , CSR_FLAG_BIT_U32 );
                
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            }
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif

        /* Write regA and regB with values indicate duty cycle and dead time */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            ((uint32)nTempPeriod - (uint32)(nRegDuty)), 
            (uint32)nRegDeadtime
        );
    }
    
    /* Come from Idle or Un-init state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* If notifications enabled */
        if ((uint8)0U != u8Notification) 
        {
            /* Set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                REG_BIT_SET32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
        }
#endif
        
        /* Handling the EDPOL bit and mode to Control register */
        Pwm_eMios_HandlePolarityBit(Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx], u16DutyCycle, u8ModuleIdx, u8ChannelIdx, u32CtrlRegVal);
    }
}
#endif /* PWM_FEATURE_OPWMCB */



/*===============================================================================================*/
#if (PWM_FEATURE_DAOC == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow DAOC mode
* @details      This function:
*                   - Note: In DAOC mode, at the end of period, the A register and B register need re-calculated to
*                     enable next match A. This calculation and first pulse must be done by software.
*                   - Calculate the duty tick follow nPeriod tick and Duty cycle
*                   - Always enable interrupt. Because in this mode, the A register and B register is re-calculated
*                     with period and duty at the end of period by software.
*                   - If come from IDLE state or Un-Init state :
*                       + If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                         after that, EDPOL bit is restored valid value
*                       + Else, polarity and mode bits is written into Cn simultaneously
*                   - With 0% duty:
*                       + Force match B to generate first pulse
*                       + Write A register with 1 value and regB with (nTempDuty + 1)
*                       + Set EDPOL bit follow polarity of channel
*                   - With 100% duty:
*                       + Force match A to generate first pulse
*                       + Write B register and regB with same value and not equal 0
*                       + Set EDPOL bit follow polarity of channel
*                   - If not equal 0% and 100%:
*                       + To generate first pulse
*                           * If IdleState same Polarity, force match A
*                           * If IdleState not equal Polarity, force match B
*                       + set the regA with 1 values and set regB to nTempDuty + 1
*                       + Set EDPOL bit follow polarity of channel
*                   - Reset counter to value 0, because in OPWMCB mode, counter alway start from 0
*                   - Enable prescaler and start counter
*
* @param        nPeriod             - PWM signal period value
*               u16DutyCycle        - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig - Pointer to channel configuration data
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_DAOC_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty = 0U;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx; 
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx; 
    VAR         (uint32,                        AUTOMATIC)                      u32RegAValue;
    VAR         (uint32,                        AUTOMATIC)                      u32PolarityBit;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;

    
    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;

    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];
#endif
    
    if (PWM_HIGH == Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx])
    {
        u32PolarityBit = (uint32)0x80;
    } 
    else
    {
        u32PolarityBit = (uint32)0;
    }
    
    /* FLAG event enabled */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

    /* Come from Idle or Uninit state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* If notifications enabled */
        if ((uint8)0U != u8Notification) 
        {
            /* Set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                /* Notification on both edges */
                REG_BIT_SET32(&u32CtrlRegVal, CCR_DAOC_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_DAOC_MODE_EDGE_SELECT_MASK_U32 );
            }
        }
#endif

        /* Handling the EDPOL bit and mode to Control register */
        Pwm_eMios_HandlePolarityBit(Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx], u16DutyCycle, u8ModuleIdx, u8ChannelIdx, u32CtrlRegVal);
    }

    if (((uint16)0U == u16DutyCycle) || ((uint16)0U == nTempDuty))
    {
        Pwm_eMios_aDaocChannelDuty[u8HwChannel] = (uint16)0U;
        
        /* Force match B */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32 );

        /* Write regA and regB with 1 to generate 0% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
            (uint32)1U, 
            ((uint32)nTempDuty + (uint32)1U)
        );

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), (CCR_EDPOL_MASK_U32), ((u32PolarityBit) & CCR_EDPOL_MASK_U32));
        
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* No transitions in the current signal status */
        Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
#endif
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
        Pwm_eMios_aDaocChannelDuty[u8HwChannel] = (uint16)0U;
        
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32);
        
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        u32RegAValue = ((Pwm_eMios_aChannelPeriod[u8HwChannel] +
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_READ32( EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx))) % Pwm_DAOC_aChannelModulo[u8HwChannel]);
        
        if ((uint32)0U != u32RegAValue)
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32( EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx),  u32RegAValue);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32( EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx),  u32RegAValue);
        }
        else
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32( EMIOS_CADR_ADDR32(u8ModuleIdx,(uint32)u8ChannelIdx),Pwm_DAOC_aChannelModulo[u8HwChannel]);
            
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32( EMIOS_CBDR_ADDR32(u8ModuleIdx,(uint32)u8ChannelIdx),Pwm_DAOC_aChannelModulo[u8HwChannel]);
        }
        
        /* Invert the EDGE POLARITY in control register */        
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), (CCR_EDPOL_MASK_U32), ((~u32PolarityBit) & CCR_EDPOL_MASK_U32));
        
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* No transitions in the current signal status */
        Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
#endif
    }
    else
    {
        Pwm_eMios_aDaocChannelDuty[u8HwChannel] = (uint16)nTempDuty;
        
        if (Pwm_eMios_aChannelIdleState[u8eMiosChannelIdx] == Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx])
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32 );
        }
        else
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32 );
        }
        
        /* Write regA with 1, write regB with calculated value of duty plus one */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
            (uint32)1U, 
            ((uint32)nTempDuty + (uint32)1U)
        );

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), (CCR_EDPOL_MASK_U32), ((u32PolarityBit) & CCR_EDPOL_MASK_U32));
        
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* Transitions in the current signal status */
        Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
#endif
    }
}
#endif /* PWM_FEATURE_DAOC */



/*================================================================================================*/
#if (PWM_FEATURE_OPWMT == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow OPWMT mode
* @details      This function:
*                   - With 0% duty:
*                       + If come from IDLE state or Un-Init state, set regA and regB to same 1 value
*                       + If not, set regB to same the current value of regA
*                   - With 100% duty:
*                       + If come from IDLE state or Un-Init state, set regA and regB to same 1 value
*                       + If not, set regB with nPeriod + 1
*                   - If not equal 0% and 100%:
*                       + Set regA with Offset + 1 and set regB follow the current of offset and the
*                         current of duty
*                   - If notification is needed, setup EDGE selection with configuration of notification
*                   - If come from IDLE state or Un-Init state :
*                       + Enable interrupt to enable trigger
*                       + Write to RegControl with OPMCB mode
*                       + If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                         after that, EDPOL bit is restored valid value
*                       + Else, polarity and mode bits is written into Cn simultaneously
*                   - To generate first edge
*                       + If duty = 0%, force match B
*                       + If duty not equal 0%, force match A
*
* @param        nPeriod               - PWM signal period value
*               u16DutyCycle          - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig   - Pointer to channel configuration data
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWMT_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
#if (PWM_CHANGE_REGISTER_A_SWITCH == STD_ON)
    VAR         (uint16,                        AUTOMATIC)                      u16TempRegB;
#endif
    VAR         (uint32,                        AUTOMATIC)                      u32RegBValue;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif
#if (PWM_CHANGE_REGISTER_A_SWITCH == STD_OFF)
    VAR         (uint32,                        AUTOMATIC)                      u32TempDutyOffset;
#endif
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;

    
    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;
    
    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif

    if (((uint16)0x0U == u16DutyCycle) || ((uint16)0x0U == nTempDuty))
    {
        /* Come from Idle and Uninit state */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
        {
            /* Write regA and regB with the same value to achieve 0% duty */
            Pwm_eMios_UpdateChannelAB
            (
                u8ModuleIdx, 
                u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                (uint32)1U, 
                (uint32)1U
            );
        }
        else
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            u32RegBValue = REG_READ32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx));

            Pwm_eMios_UpdateChannelB
            (
                u8ModuleIdx, 
                u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                u32RegBValue
            );
        }
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
        /* Come from Idle and Uninit state */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
        {
            /* Write regB with the value greater than nPriod to achieve 100% duty */
            Pwm_eMios_UpdateChannelAB
            (
                u8ModuleIdx, 
                u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                (uint32)1U, 
                (uint32)(nPeriod + (uint32)1U)
            );
        }
        else
        {
            Pwm_eMios_UpdateChannelB
            (
                u8ModuleIdx, 
                u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                (uint32)(nPeriod + (uint32)1U)
            );
        }
    }
    else
    {
#if (PWM_CHANGE_REGISTER_A_SWITCH == STD_ON)
        /* Calculate the B-register value */
        if ((Pwm_PeriodType)0U != nOffset)
        {
            u16TempRegB = ((uint16)nPeriod - (uint16)nOffset) + (uint16)1U;
        }
        else
        {
            u16TempRegB = (uint16)1U;
        }

        /* Calculate the A-register value */
        if (u16TempRegB > nTempDuty)
        {
            nTempDuty = u16TempRegB - nTempDuty;
        }
        else
        {
            nTempDuty = ((uint16)nPeriod - (uint16)nTempDuty) + (uint16)1U;
        }
        
        /* Write regA with the calculated of duty offset and regB with the calculated of offset */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif            
            (uint32)nTempDuty, 
            (uint32)u16TempRegB
        );
#else
    
        /* Register B is updated on duty cycle change */
        u32TempDutyOffset = ((uint32)nTempDuty + (uint32)nOffset) % nPeriod;
        
        /* Write regA with the calculated value of offset and regB with calculated value of duty offset */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx,
            u8ChannelIdx,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nOffset + (uint32)1U, 
            (uint32)u32TempDutyOffset + (uint32)1U
        );
#endif

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_ALTA_ADDR32(u8ModuleIdx, u8ChannelIdx), (uint32)(Pwm_eMios_aTriggerDelay[u8eMiosChannelIdx] + (uint32)1U));
    }
    
    /* Come from Idle and Uninit state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_DMA_MASK_U32);
        
        /* FLAG event enabled */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
    }

    /* come from Idle and Uninit state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        u8Notification =  Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];

        /* If notifications enabled */
        if ((uint8)0U != u8Notification) 
        {
            /* Set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                /* notification on both edges */
                REG_BIT_SET32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
        }
#endif

        /* Handling the EDPOL bit and mode to Control register */
        Pwm_eMios_HandlePolarityBit(Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx], u16DutyCycle, u8ModuleIdx, u8ChannelIdx, u32CtrlRegVal);
        
        /* Force match on the first edge - this also sets the signal level */
        if (((uint16)0U != u16DutyCycle) && ((Pwm_PeriodType)0U != nTempDuty))
        {
            /* Force match A */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32); 
        }
        else
        {
            /* Force match B */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32); 
        }
    }
}
#endif /* PWM_FEATURE_OPWMT */



/*===============================================================================================*/
#if (PWM_FEATURE_OPWMB == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow OPWMB mode
* @details      This function:
*                   - With 0% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA and regB with same value 0
*                   - With 100% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA with 0 value and regB with nPeriod value
*                   - If not equal 0% and 100%:
*                       + Enable interrupt if notification is enabled
*                       + Set regA with Offset and set regB follow the current of offset and the
*                         current of duty
*                   - If notification is needed, setup EDGE selection with configuration of notification
*                   - If come from IDLE state or Un-Init state :
*                       + Write to RegControl with OPWMB mode
*                       + If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                         after that, EDPOL bit is restored valid value
*                       + Else, polarity and mode bits is written into Cn simultaneously
*                   - To generate first edge
*                       + If duty = 0%, force match B
*                       + If duty not equal 0%, force match A
*
* @param        nPeriod               - PWM signal period value
*               u16DutyCycle          - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig   - Pointer to channel configuration data
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWMB_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint32,                        AUTOMATIC)                      u32PolarityBit;
    VAR         (uint32,                        AUTOMATIC)                      u32TempDutyOffset;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;

    
    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];
#endif

    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif

    if (((uint16)0U == u16DutyCycle) || ((uint16)0U == nTempDuty))
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write 0 to regA and regB to generate 0% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)0U, 
            (uint32)0U
        );
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA with 0 and regB with nPeriod to achieve 100% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)0U, 
            (uint32)nPeriod
        );
    }
    else
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* Transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)1U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* Transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
        
            if ((uint8)0U != u8Notification) /* if notifications enabled */
            {
                /* FLAG event enabled */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
            else
            {
#endif
                /* Disable and clear interrupt flag */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32 );
             
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx) , CSR_FLAG_BIT_U32 );
                
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            }
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif

        u32TempDutyOffset = (uint32)nTempDuty + nOffset;
        
        /* Write regA with offset and regB with duty offset has been calculated */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nOffset, 
            (uint32)u32TempDutyOffset
        );
    }
    
    /* Come from Idle or Uninit state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)    
        /* If notifications enabled */
        if ((uint8)0U != u8Notification) 
        {
            /* Set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                REG_BIT_SET32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
        }
#endif

        if (PWM_HIGH == Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx])
        {
            u32PolarityBit = (uint32)0x80;
        }
        else
        {
            u32PolarityBit = (uint32)0U;
        }
        
        REG_RMW32
        (
            EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx),
            (CCR_MODE_MASK_U32 | CCR_EDPOL_MASK_U32),
            ((u32CtrlRegVal & CCR_MODE_MASK_U32) | (u32PolarityBit & CCR_EDPOL_MASK_U32 ))
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        );
        
        /* Force match on the first edge - this also sets the signal level */
        /* Do not force event A for OPWMB/OPWMT and 0% duty */
        if (((uint16)0U != u16DutyCycle) && (0U != nTempDuty))
        {
            /* Force match A */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32); 
        }
        else
        {
            /* Force match B */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32); 
        }
    }
}
#endif /* PWM_FEATURE_OPWMB */



/*================================================================================================*/
#if (PWM_FEATURE_OPWM == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow OPWM mode
* @details      This function:
*                   - With 0% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA and regB with same value 0
*                   - With 100% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA and regB with same nPeriod - 1
*                   - If not equal 0% and 100%:
*                       + Enable interrupt if notification is enabled
*                       + Set regA with Offset and set regB follow the current of offset and the
*                         current of duty
*                   - If notification is needed, setup EDGE selection with configuration of notification
*                   - If come from IDLE state or Un-Init state :
*                       + Write to RegControl with OPWM mode
*                       + If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                         after that, EDPOL bit is restored valid value
*                       + Else, polarity and mode bits is written into Cn simultaneously
*                   - To generate first edge
*                       + If duty = 0%, force match B
*                       + If duty not equal 0%, force match A
*
* @param        nPeriod               - PWM signal period value
*               u16DutyCycle          - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig   - Pointer to channel configuration data
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWM_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempOffset;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint32,                        AUTOMATIC)                      u32TempDutyOffset;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)                          
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif                          
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;

    
    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];
#endif

    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;
    
    nTempOffset = nOffset;

#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod - (Pwm_PeriodType)1U, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod - (Pwm_PeriodType)1U, u16DutyCycle);
#endif


    if (((uint16)0U == u16DutyCycle) || ((uint16)0U == nTempDuty))
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA with 0 and regB with 0 to achieve 0% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)0U, 
            (uint32)0U
        );
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA and regB with the same values to achieve 100% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nPeriod - (uint32)1U, 
            (uint32)nPeriod - (uint32)1U
        );
    }
    else
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* Transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)1U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* Transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
        
            if ((uint8)0U != u8Notification) /* if notifications enabled */
            {
                /* FLAG event enabled */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
            else
            {
#endif
                /* Disable and clear interrupt flag */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32 );
             
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx) , CSR_FLAG_BIT_U32 );
                
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            }
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif

        /* It is impossible to write 0 to register A, because match even does not occur. 
            So nOffset must be plus one before write to register A */
        nTempOffset = nTempOffset + (Pwm_PeriodType)1U;
        
        u32TempDutyOffset = (uint32)nTempDuty + nTempOffset;
        
        /* Write regA with the calculated value of offset and regB with calculated value of duty offset */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nTempOffset, 
            (uint32)u32TempDutyOffset
        );
    }
    
    /* Come from Idle or Un-init state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* If notifications enabled */
        if ((uint8)0U != u8Notification)
        {
            /* Set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                REG_BIT_SET32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
        }
#endif

        /* Handling the EDPOL bit and mode to Control register */
        Pwm_eMios_HandlePolarityBit(Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx], u16DutyCycle, u8ModuleIdx, u8ChannelIdx, u32CtrlRegVal);
        
        /* Force match on the first edge - this also sets the signal level */
        /* Do not force event A for OPWMB/OPWMT and 0% duty */
        if (((uint16)0U != u16DutyCycle) && (0U != nTempDuty))
        {
            /* Force match A */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32); 
        }
        else
        {
            /* Force match B */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32); 
        }
    }
}
#endif /* PWM_FEATURE_OPWM */



/*================================================================================================*/
#if (PWM_FEATURE_OPWFMB == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow OPWFMB mode
* @details      This function:
*                   - With 0% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA and regB with same nPeriod value
*                   - With 100% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA with 0 value and regB with nPeriod
*                   - If not equal 0% and 100%:
*                       + Enable interrupt if notification is enabled
*                       + Set regB with nPeriod and regA with Duty
*                   - If notification is needed, setup EDGE selection with configuration of notification
*                   - If come from IDLE state or Un-Init state :
*                       + Write to RegControl with OPWFMB mode
*                   - Force match B to generate first edge
*                   - Enable prescaler and start internal counter
*
* @param        nPeriod               - PWM signal period value
*               u16DutyCycle          - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig   - Pointer to channel configuration data

* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWFMB_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx; 
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    /** @brief  Status of polarity bit */
    VAR         (uint32,                        AUTOMATIC)                      u32PolarityBit;  
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;

    
    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];
#endif

    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

#if  (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif

    if (((uint16)0U == u16DutyCycle) || ((uint16)0U == nTempDuty))
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA and regB with nPeriod to achieve 0% duty*/
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nPeriod, 
            (uint32)nPeriod
        );
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA with 0 and regB with nPeriod to achieve 100% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)0U, 
            (uint32)nPeriod
        );
    }
    else
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* Transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)1U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* Transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
        
            if ((uint8)0U != u8Notification) /* if notifications enabled */
            {
                /* FLAG event enabled */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
            else
            {
#endif
                /* Disable and clear interrupt flag */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32 );
             
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx) , CSR_FLAG_BIT_U32 );
                
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            }
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif


        nTempDuty = nPeriod - nTempDuty;
        
        /* Write regA with calculated value of duty and regB with period */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nTempDuty, 
            (uint32)nPeriod
        );
    }
    
    /* Come from Idle or Uninit State */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* if notifications enabled */
        if ((uint8)0U != u8Notification)
        {
            /* set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                /* notification on both edges */
                REG_BIT_SET32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
        }
#endif

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CCNTR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), 1U);

        if (PWM_HIGH == Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx])
        {
            u32PolarityBit = (uint32)0x80;
        } 
        else
        {
            u32PolarityBit = (uint32)0U;
        }

        
        REG_RMW32
        (
            EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx),
            (CCR_MODE_MASK_U32 | CCR_EDPOL_MASK_U32),
            ((u32CtrlRegVal & CCR_MODE_MASK_U32) | ((u32PolarityBit) & CCR_EDPOL_MASK_U32))
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        );
        
        /* force match on the first edge - this also sets the signal level */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32);
        
        /* set the prescaler divide value */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPRE_MASK_U32, u32CtrlRegVal & CCR_UCPRE_MASK_U32);
        
        /* enable prescaler - this will start the internal counter */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);
    }
}
#endif /* PWM_FEATURE_OPWFMB */



/*================================================================================================*/
#if (PWM_FEATURE_OPWFM == STD_ON)
/**
* @brief        This function configure for one EMIOS hardware channel follow OPWFM mode
* @details      This function:
*                   - With 0% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA and regB with same 0 value
*                   - With 100% duty:
*                       + Disable and clear interrupt flag
*                       + Set regA and regB with same nPeriod - 1 value
*                   - If not equal 0% and 100%:
*                       + Enable interrupt if notification is enabled
*                       + Set regB with nPeriod - 1 and regA with Duty
*                   - If notification is needed, setup EDGE selection with configuration of notification
*                   - If come from IDLE state or Un-Init state :
*                       + Write to RegControl with OPWFM mode
*                       + If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                         after that, EDPOL bit is restored valid value
*                       + Else, polarity and mode bits is written into Cn simultaneously
*                   - Force match B to generate first edge
*                   - Enable prescaler and start internal counter
*
* @param        nPeriod               - PWM signal period value
*               u16DutyCycle          - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosChannelConfig   - Pointer to channel configuration data
*
* @return       void
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_eMios_SetRegs_OPWFM_mode
(
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8eMiosChannelIdx,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig
)
{
    
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempDuty = 0U;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx; 
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif
    VAR         (uint8,                         AUTOMATIC)                      u8HwChannel;

    
    u8HwChannel = (uint8)peMiosChannelConfig->u8HwChannel;
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[(Pwm_eMios_ChannelType)u8HwChannel];
#endif

    u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    nTempDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
    nTempDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif

    if (((uint16)0U == u16DutyCycle) || ((uint16)0U == nTempDuty))
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA with 0 to achieve 0% duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)0U, 
            (uint32)nPeriod - (uint32)1U
        );
    }
    else if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* No transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)0U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* No transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
            
            /* Disable and clear interrupt flag */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif
        
        /* Write regA and regB with the same values to achieve 100& duty */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nPeriod - (uint32)1U, 
            (uint32)nPeriod - (uint32)1U
        );
    }
    else
    {
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
        if (PWM_EMIOS_UPDATE_SYNCHRONOUS == eSyncUpdate)
        {
            /* Transitions in the next signal status */
            Pwm_eMios_aNextDutyState[u8eMiosChannelIdx] = (uint8)1U;
            
            /* Output update disabled to perform synchronization later */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)1U;
        }
        else
        {
#endif
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            /* Transitions in the current signal status */
            Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
        
            if ((uint8)0U != u8Notification) /* if notifications enabled */
            {
                /* FLAG event enabled */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
            else
            {
#endif
                /* Disable and clear interrupt flag */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32 );
             
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx) , CSR_FLAG_BIT_U32 );
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
            }
#endif
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            /* Output update enabled so no need for synchronization */
            Pwm_eMios_aOutputUpdateDisable[u8eMiosChannelIdx] = (uint8)0U;
        }
#endif

        nTempDuty = ((Pwm_PeriodType)nPeriod - (Pwm_PeriodType)nTempDuty) - (Pwm_PeriodType)1U;
        
        /* Write regA with the calculated value of duty and regB with calculated value of period */
        Pwm_eMios_UpdateChannelAB
        (
            u8ModuleIdx, 
            u8ChannelIdx, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            (uint32)nTempDuty, 
            (uint32)nPeriod - (uint32)1U
        );
    }
        
    /* Come from Idle or Un-init State */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* If notifications enabled */
        if ((uint8)0U != u8Notification) 
        {
            /* Set notification edge in u32CtrlRegVal */
            if ((uint8)PWM_BOTH_EDGES == u8Notification)
            {
                REG_BIT_SET32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
            else
            {
                REG_BIT_CLEAR32(&u32CtrlRegVal, CCR_MODE_EDGE_SELECT_MASK_U32);
            }
        }
#endif

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CCNTR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), 1U);
        
        /* Handling the EDPOL bit and mode to Control register */
        Pwm_eMios_HandlePolarityBit(Pwm_eMios_aChannelPolarity[u8eMiosChannelIdx], u16DutyCycle, u8ModuleIdx, u8ChannelIdx, u32CtrlRegVal);
        
        /* Force match on the first edge - this also sets the signal level */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32);
        
        /* Set the prescaler value */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPRE_MASK_U32, u32CtrlRegVal & CCR_UCPRE_MASK_U32);
        
        /* Enable prescaler - this will start the internal counter */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);
    }
}
#endif /* PWM_FEATURE_OPWFM */



/*===============================================================================================*/
#if ((PWM_SET_COUNTER_BUS_API == STD_ON) && \
     (PWM_EMIOS_16_BITS_VARIANT == STD_OFF) && \
     ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON)))
/**
* @brief        Function to get the division of 64 bit unsigned integers.
* @details      This function returns the division value of 64 bit unsigned integers.
*
* @param        nNume - Numerator
*               nDeno - Denominator
*
* @return       Pwm_uint64 - division value of 64 bit unsigned integers.
*
*/
static FUNC(Pwm_uint64, PWM_CODE) Pwm_eMios_Div64
(
    VAR         (Pwm_uint64,                    AUTOMATIC)                      nNume, 
    VAR         (Pwm_uint64,                    AUTOMATIC)                      nDeno
)
{
    
    VAR         (Pwm_uint64,                    AUTOMATIC)                      u64Mask;
    VAR         (Pwm_uint64,                    AUTOMATIC)                      u64Temp;
    VAR         (Pwm_uint64,                    AUTOMATIC)                      u64RetNumeric;
    VAR         (uint32,                        AUTOMATIC)                      u32TempDeno;

    
    if (0ULL == nDeno) 
    {
        u64RetNumeric = ~(Pwm_uint64)0ULL;
    }
    else
    { 
        if (0ULL == ((nDeno - 1ULL) & nDeno))
        {
            /* Divide by power of 2. */
            u64RetNumeric = nNume;
            
            if (0ULL == (nDeno & 0x00000000ffffffffULL))
            {
                nDeno >>= 32U;
                u64RetNumeric >>= 32U;
            }
            
            u32TempDeno = (uint32)nDeno;
            
            if (0U == (u32TempDeno & 0xffffU))
            {
                u32TempDeno >>= 16U;
                u64RetNumeric >>= 16U;
            }
            
            if (0U == (u32TempDeno & 0xffU))
            {
                u32TempDeno >>= 8U;
                u64RetNumeric >>= 8U;
            }
            
            do
            {
                u32TempDeno >>= 1U;
                u64RetNumeric >>= 1U;
            } while ((uint32)0U != u32TempDeno);
        } 
        
        else
        {
            u64Temp = nNume | nDeno;
            
            if (0ULL == (u64Temp & 0xffffffff00000000ULL))
            {
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                u64RetNumeric = (Pwm_uint64)((uint32)nNume/(uint32)nDeno);
            }
            else
            {
                u64Mask = 0xff00000000000000ULL;
                
                if (0ULL == (u64Temp & u64Mask)) 
                {
                    u64Mask >>= 8U;
                    
                    if ((u64Temp & u64Mask) == 0ULL) 
                    {
                        u64Mask >>= 8U;
                        
                        if ((u64Temp & u64Mask) == 0ULL) 
                        {
                            u64Mask >>= 8U;
                        }
                    }
                }
                
                u32TempDeno = 0U;
                
                while ((nDeno & u64Mask) == 0ULL) 
                {
                    nDeno <<= 8U;
                    u32TempDeno += 8U;
                }
                
                if (0ULL != (nNume & 0x8000000000000000ULL))
                {
                    while (0ULL == (nDeno & 0x8000000000000000ULL)) 
                    {
                        nDeno <<= 1U;
                        u32TempDeno++;
                    }
                    
                    u64RetNumeric = 0ULL;
                    
                    if (nNume >= nDeno) 
                    {
                        nNume -= nDeno;
                        u64RetNumeric |= 1ULL;
                    }
                }
                else 
                {
                    while (nDeno <= nNume) 
                    {
                        nDeno <<= 1U;
                        u32TempDeno++;
                    }
                    
                    u64RetNumeric = 0ULL;
                }
                
                while (u32TempDeno > 0U) 
                {
                    u32TempDeno--;
                    nDeno >>= 1U;
                    u64RetNumeric <<= 1U;
                    
                    if (nNume >= nDeno) 
                    {
                        nNume -= nDeno;
                        u64RetNumeric |= 1ULL;
                    }
                }
                
                u32TempDeno--;
            }
        }
    }
    
    /* @violates @ref Pwm_eMios_c_REF_7 This is not dead code */
    return u64RetNumeric;
    
}
#endif



/*================================================================================================*/
#if ((PWM_FEATURE_OPWFM == STD_ON) || \
     (PWM_FEATURE_OPWM == STD_ON) || \
     (PWM_FEATURE_DAOC == STD_ON) || \
     (PWM_FEATURE_OPWMT == STD_ON) || \
     (PWM_FEATURE_OPWMCB == STD_ON))
/**
* @brief        This function used to handling the EDPOL bit and mode bits
* @details      This function:
*                   - With ePolarity is HIGH, the u32PolarityBit should be set to 0x80 value, otherwise,
*                     the u32PolarityBit should be set to 0x0 value
*                   - Write to RegControl with mode and polarity
*                   - If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
*                     after that, EDPOL bit is restored valid value
*                   - Else, polarity and mode bits is written into Cn simultaneously
*
* @param        ePolarity         - Polarity of PWM channel
*               u16DutyCycle      - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               u8ModuleIdx            - module index of eMIOS channel
*               u8ChannelIdx           - channel index of eMIOS channel
*               u32CtrlRegVal     - eMios channel control parameters
*
* @return       void
*
*/
static FUNC(void, PWM_CODE) Pwm_eMios_HandlePolarityBit
(
    VAR         (Pwm_OutputStateType,           AUTOMATIC)                      ePolarity,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx,
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx,
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal
)
{
    
    VAR         (uint32,                        AUTOMATIC)                      u32PolarityBit;

    
    if (PWM_HIGH == ePolarity)
    {
        u32PolarityBit = (uint32)0x80;
    }
    else
    {
        u32PolarityBit = (uint32)0;
    }
    
    /* To avoid spike pulse 
       - If duty cycle = 100%, when enter mode, EDPOL bit get complement of polarity 
         after that, EDPOL bit is restored valid value
       - Else, polarity and mode bits is written into Cn simultaneously
    */
    if (PWM_DUTY_CYCLE_100 == u16DutyCycle)
    {
        REG_RMW32
        (
            EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx),
            (CCR_MODE_MASK_U32 | CCR_EDPOL_MASK_U32),
            (u32CtrlRegVal & CCR_MODE_MASK_U32) | ((~u32PolarityBit) & CCR_EDPOL_MASK_U32)
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        );
        
        REG_RMW32
        (
            EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), 
            CCR_EDPOL_MASK_U32,
            u32PolarityBit & CCR_EDPOL_MASK_U32 
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        );
    }
    else
    {
        REG_RMW32
        (
            EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx),
            (CCR_MODE_MASK_U32 | CCR_EDPOL_MASK_U32),
            (u32CtrlRegVal & CCR_MODE_MASK_U32) | (u32PolarityBit & CCR_EDPOL_MASK_U32)
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        );
    }
}
#endif


#define PWM_STOP_SEC_CODE
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"



/*===============================================================================================
*                                       GLOBAL FUNCTIONS
===============================================================================================*/

#define PWM_START_SEC_CODE
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"


/**
* @brief        Service for initializing the hardware timer module (low level)
* @details      This function initializes all the configured hardware channels as per the configured mode
*                   - puts the channel in GPIO mode
*                   - disables the interrupt corresponding to eMIOS channel
*                   - clear pending interrupt flag for the channel
*                   - enables/disables the Freeze Mode
*                   - clears the (pending) interrupt flag corresponding to eMIOS channel
*                   - get the Period that the current UC is using and also calculates the duty cycle
*                   - update registers A and B with the duty cycle and period value for the configured mode
*                   - force a match on B register for OPWFMB mode
*                   - force a match on A register for OPWMB and OPWMT modes
*                   - write trigger delay to alternate A register for OPWMT mode and offset to A register
*                     for OPWMB and OPWMT modes
*                   - FLAG assigned to DMA request and FLAG event is enabled for OPWMT mode
*                   - FLAG event is disabled for OPWMB and OPWFMB modes
*                   - sets the prescaler value
*                   - enable prescaler which will start the internal counter, for Counter Bus
*
* @param        ConfigPtr - pointer to PWM top configuration structure
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_Init
(
    P2CONST     (Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    
    /** @brief  Pointer to eMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;    
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod;
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8Counter;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterModule;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterChannel;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx;
    VAR         (uint8,                         AUTOMATIC)                      aMasterBusMode[PWM_EMIOS_CHANNEL_NO];
    VAR         (uint32,                        AUTOMATIC)                      aPrescaler[PWM_EMIOS_CHANNEL_NO];

    
    for (u8Counter = 0U; u8Counter < (Pwm_eMios_ChannelType)PWM_EMIOS_CHANNEL_NO; u8Counter++)
    {
        aMasterBusMode[u8Counter] = (uint8)0xFFU;       
        aPrescaler[u8Counter] = (uint32)0U;
    }

    /* Configuration for unified channel */
    for (u8Counter = 0U; u8Counter < peMiosIpConfig->u8NumChannels; u8Counter++)
    {
        /* Only handle EMIOS channels */
        peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8Counter];

        u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

        Pwm_eMios_aChannelPolarity[u8Counter] = peMiosChannelConfig->ePwmPolarity;

#if ((PWM_DE_INIT_API == STD_ON)||\
     (PWM_SET_OUTPUT_TO_IDLE_API == STD_ON)||\
     (PWM_FEATURE_DAOC == STD_ON))
        Pwm_eMios_aChannelIdleState[u8Counter] = peMiosChannelConfig->ePwmIdleState;
#endif

        u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;
        nPeriod = peMiosChannelConfig->nPwmDefaultPeriod;
        u16DutyCycle = peMiosChannelConfig->u16PwmDefaultDutyCycle;

        u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, ((uint32)u32CtrlRegVal & CCR_BSL_MASK_U32));

#ifdef EMIOS_UCDIS_AVAILABLE
    #if (EMIOS_UCDIS_AVAILABLE == STD_ON)
        eMios_StartChannel((uint8)peMiosChannelConfig->u8HwChannel);
    #endif
#endif

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FREN_MASK_U32, CCR_FREN_MASK_U32 & u32CtrlRegVal);
        
        /* Before entering GPIO mode set the EDPOL bit to the configured IDLE value */
        if (PWM_HIGH == peMiosChannelConfig->ePwmIdleState)
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_EDPOL_MASK_U32);
        }
        else
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_EDPOL_MASK_U32);
        }
        
        /* Enter GPIO output mode */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_MODE_MASK_U32, CCR_MODE_GPO_U32);
        
        /* Disable channel interrupts  */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
        
        /* Clear pending interrupt flag for the channel */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);

        /* Store the nPeriod that the current unified channel is using */
        Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel] = nPeriod;
        
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
        /* Store the duty cycle */
        Pwm_eMios_aChannelDuty[u8Counter] = u16DutyCycle;
#endif

        /* Write selected bus to the control register */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_BSL_MASK_U32, u32CtrlRegVal & CCR_BSL_MASK_U32);

        /* If channel uses internal counter for bus */
        if (PWM_BUS_INTERNAL_COUNTER_U32 == ((uint32)u32CtrlRegVal & CCR_BSL_MASK_U32))
        {
            /* This will stop the internal counter */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);

            if (PWM_MODE_OPWFMB_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#if (PWM_FEATURE_OPWFMB == STD_ON)
                Pwm_eMios_SetRegs_OPWFMB_mode
                (
                    u8Counter, 
                    nPeriod, 
                    u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                    PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
                    peMiosChannelConfig
                );
#endif
            }
            else if (PWM_MODE_OPWFM_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#if (PWM_FEATURE_OPWFM == STD_ON)
                Pwm_eMios_SetRegs_OPWFM_mode
                (
                    u8Counter, 
                    nPeriod, 
                    u16DutyCycle, 
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                    PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
                    peMiosChannelConfig
                );
#endif
            }
            else
            {
                /* Do nothing */
            }
        }
        /* If channel uses bus A or bus Diverse */
        else
        { 
            if ((PWM_MODE_OPWMCB_LEAD_DEADTIME_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32)) || \
                (PWM_MODE_OPWMCB_TRAIL_DEADTIME_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32)))
            {
#if (PWM_FEATURE_OPWMCB == STD_ON)   
                /* Store the nPeriod that the master UC is using */
                Pwm_eMios_aChannelPeriod[u8MasterBusIdx] = nPeriod;
                
                Pwm_eMios_SetRegs_OPWMCB_mode
                (
                    u8Counter, 
                    nPeriod,
                    u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                    PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
                    peMiosChannelConfig
                );
#endif
            }
            else if (PWM_MODE_DAOC_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#if (PWM_FEATURE_DAOC == STD_ON)   
                /* Store the nPeriod that the master UC is using */
                Pwm_eMios_aChannelPeriod[u8MasterBusIdx] = peMiosChannelConfig->nPwmDaocModulo;
                
                /* Store the modulo of DAOC channel */
                Pwm_DAOC_aChannelModulo[peMiosChannelConfig->u8HwChannel] = peMiosChannelConfig->nPwmDaocModulo;
                
                Pwm_eMios_SetRegs_DAOC_mode
                (
                    u8Counter,
                    nPeriod,
                    u16DutyCycle,
                    peMiosChannelConfig
                );
#endif
            }
            else if (PWM_MODE_OPWMT_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#if (PWM_FEATURE_OPWMT == STD_ON)   
                /* Store the nPeriod that the master UC is using */
                Pwm_eMios_aChannelPeriod[u8MasterBusIdx] = nPeriod;
                
                /* Store the Trigger Delay that the master UC is using */
                Pwm_eMios_aTriggerDelay[u8Counter] = peMiosChannelConfig->nPwmTriggerDelay;
                
                /* Store the offset channel that the master UC is using */
                Pwm_eMios_aChannelOffset[u8Counter] = peMiosChannelConfig->nPwmOffset;
                
                Pwm_eMios_SetRegs_OPWMT_mode
                (
                    u8Counter, 
                    nPeriod,
                    u16DutyCycle,
                    Pwm_eMios_aChannelOffset[u8Counter],
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                    PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
                    peMiosChannelConfig
                );
#endif
            }
            else if (PWM_MODE_OPWMB_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#if (PWM_FEATURE_OPWMB == STD_ON)
                /* Store the nPeriod that the master UC is using */
                Pwm_eMios_aChannelPeriod[u8MasterBusIdx] = nPeriod;
                
                /* Store the offset channel that the master UC is using */
                Pwm_eMios_aChannelOffset[u8Counter] = peMiosChannelConfig->nPwmOffset;

                Pwm_eMios_SetRegs_OPWMB_mode
                (
                    u8Counter,
                    nPeriod,
                    u16DutyCycle,
                    Pwm_eMios_aChannelOffset[u8Counter],
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                    PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
                    peMiosChannelConfig);
#endif
            }
            else if (PWM_MODE_OPWM_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#if (PWM_FEATURE_OPWM == STD_ON)
                /* Store the nPeriod that the master UC is using */
                Pwm_eMios_aChannelPeriod[u8MasterBusIdx] = nPeriod;
                
                /* Store the offset channel that the master UC is using */
                Pwm_eMios_aChannelOffset[u8Counter] = peMiosChannelConfig->nPwmOffset;

                Pwm_eMios_SetRegs_OPWM_mode
                (
                    u8Counter,
                    nPeriod,
                    u16DutyCycle,
                    Pwm_eMios_aChannelOffset[u8Counter],
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                    PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
                    peMiosChannelConfig
                );
#endif
            }
            else
            {
                /* Do nothing */
            }
            
            if ((uint8)0xFFU == aMasterBusMode[u8MasterBusIdx])
            {
                /* Store master bus mode and master bus prescaler*/
                aMasterBusMode[u8MasterBusIdx] = peMiosChannelConfig->u8MasterMode;
                
                aPrescaler[u8MasterBusIdx] = peMiosChannelConfig->u32ControlValue & CCR_UCPRE_MASK_U32;

#ifdef EMIOS_UCDIS_AVAILABLE
    #if (EMIOS_UCDIS_AVAILABLE == STD_ON)
                /* Enable unified channel to make registers writable */
                eMios_StartChannel((uint8)u8MasterBusIdx);
    #endif
#endif
            }
        }
        
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        if (((uint16)0U == u16DutyCycle) || (PWM_DUTY_CYCLE_100 == u16DutyCycle))
        {
            /* No transitions in the signal */
            Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
        }
        else
        {
            /* Transitions available in the signal */
            Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
        }
#endif
    }

    /* Configuration for master bus */
    for (u8Counter = 0U; u8Counter < PWM_EMIOS_CHANNEL_NO; u8Counter++)
    {
        /* If master bus is used */
        if ((uint8)0xFFU != aMasterBusMode[u8Counter]) 
        {
            u8MasterModule  = EMIOS_MODULE_INDEX_U8(u8Counter);
            u8MasterChannel = EMIOS_CHANNEL_INDEX_U8(u8Counter);

            /* Enter GPIO output mode */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_RMW32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_MODE_MASK_U32, CCR_MODE_GPO_U32);
            
            /* Disable prescaler - this will stop the internal counter */           
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_UCPREN_MASK_U32);
            
            /* Update prescaler values */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_RMW32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_UCPRE_MASK_U32, aPrescaler[u8Counter]);

            /* Disable interrupts */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel),CCR_FEN_MASK_U32);

            switch (aMasterBusMode[u8Counter])
            {
                case (uint8)MASTER_MODE_UP_DOWN_BUFFERED_COUNTER_U32:
                {
                    /* Update period value to EMIOS A register */
                    nPeriod = (Pwm_eMios_aChannelPeriod[u8Counter] >> (Pwm_PeriodType)1U) + 1U;
                    
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CADR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), nPeriod);
                    
                    /* Set internal counter to 1 */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CCNTR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (uint32)1U);
                    
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */        
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_RMW32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_MODE_MASK_U32, (MASTER_MODE_UP_DOWN_BUFFERED_COUNTER_U32 & CCR_MODE_MASK_U32));
                    
                    break;
                }
                case (uint8)MASTER_MODE_UP_BUFFERED_COUNTER_U32:
                {
                    /* Update period value to EMIOS A register */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CADR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (Pwm_eMios_aChannelPeriod[u8Counter]));
                    
                    /* Set internal counter to 1 */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CCNTR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (uint32)1U);

                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */        
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_RMW32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_MODE_MASK_U32, (MASTER_MODE_UP_BUFFERED_COUNTER_U32 & CCR_MODE_MASK_U32));
                    
                    break;
                }
                case (uint8)MASTER_MODE_UP_COUNTER_U32:
                {
                    /* Update period value to EMIOSA register */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CADR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (Pwm_eMios_aChannelPeriod[u8Counter]) - (uint32)1U);
                    
                    /* Set internal counter to 1 */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CCNTR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (uint32)0U);
                    
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */    
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_RMW32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_MODE_MASK_U32, (MASTER_MODE_UP_COUNTER_U32 & CCR_MODE_MASK_U32)); 
                    
                    break;
                }
                default:
                {
                    /* Do nothing */
                    break;
                }
            }

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_UCPREN_MASK_U32);
        }
    }
}



/*===============================================================================================*/
#if (PWM_DE_INIT_API == STD_ON)
/**
* @brief        This function de-initializes all eMIOS channels assigned to PWM
* @details      This function
*                   - sets the channel output to the configured Idle state
*                   - Reset Timer control register, Internal Counter, A, B registers
*                   - clears the (pending) interrupt flag corresponding to eMIOS channel
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_DeInit
(
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    
    /** @brief  Pointer to eMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8Counter = (Pwm_eMios_ChannelType)0U;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterChannel;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx = 0xFFU;
    VAR         (uint8,                         AUTOMATIC)                      aMasterBusUse[PWM_EMIOS_CHANNEL_NO];
    
    
    for (u8Counter = 0U; u8Counter < (Pwm_eMios_ChannelType)PWM_EMIOS_CHANNEL_NO; u8Counter++)
    {
        
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
        /* Disable notifications */
        Pwm_eMios_aChannelNotifType[u8Counter] = (uint8)0U;
#endif

#if (PWM_FEATURE_DAOC == STD_ON)
        Pwm_eMios_aDaocChannelDuty[u8Counter] = (uint16)0U;
        Pwm_DAOC_aChannelModulo[u8Counter] = (Pwm_PeriodType)0U;
#endif

        /* Set 0 for array used to store the current period for each PWM channel */
        Pwm_eMios_aChannelPeriod[u8Counter] = (Pwm_PeriodType)0U;

        aMasterBusUse[u8Counter] = (uint8)0xFFU;
    }
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    for (u8Counter = 0U; u8Counter < PWM_EMIOS_MODULE_NO; u8Counter++)
    {
        /* Set 0 for array used to store the current duty cycle state */
        Pwm_eMios_aDutyState[u8Counter] = (uint32)0U;
    }
#endif

    for (u8Counter = 0U; u8Counter < peMiosIpConfig->u8NumChannels; u8Counter++)
    {
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
        Pwm_eMios_aChannelDuty[u8Counter] = (uint16)0U;
#endif

#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))
        Pwm_eMios_aChannelOffset[u8Counter] = (Pwm_PeriodType)0U;
#endif
        
#if (PWM_FEATURE_OPWMT == STD_ON)
        Pwm_eMios_aTriggerDelay[u8Counter] = (Pwm_PeriodType)0x00;
#endif

        peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8Counter];

        u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

        u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

        /* Set the channel output to the configured Idle state */
        if (PWM_HIGH == Pwm_eMios_aChannelIdleState[u8Counter])
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_EDPOL_MASK_U32);
        }
        else
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_EDPOL_MASK_U32);
        }

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), 0U);

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), 0U);
        
        /* Enter GPIO output mode - this will set the output pin to the EDPOL value */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_MODE_MASK_U32, CCR_MODE_GPO_U32);

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), (~(CCR_EDPOL_MASK_U32 | CCR_MODE_MASK_U32)));
        
        /* Disable interrupt */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
        
        /* Clear interrupt flag */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
        
        /* Only write UCDIS register if it's available */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
#ifdef EMIOS_UCDIS_AVAILABLE
    #if (EMIOS_UCDIS_AVAILABLE == STD_ON)
        /* Disable unified channel */
        eMios_StopChannel((uint8)peMiosChannelConfig->u8HwChannel);
    #endif
#endif

        /* If channel using master bus, so de-init for master bus */
        if (PWM_BUS_INTERNAL_COUNTER_U32 != ((uint32)u32CtrlRegVal & CCR_BSL_MASK_U32))
        {
            u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, ((uint32)u32CtrlRegVal & CCR_BSL_MASK_U32));
            u8MasterChannel = EMIOS_CHANNEL_INDEX_U8(u8MasterBusIdx);
            
            if ((uint8)0xFFU == aMasterBusUse[u8MasterBusIdx])
            {
                aMasterBusUse[u8MasterBusIdx] = (uint8)1U;

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8MasterChannel) , 0U );

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8MasterChannel) , 0U );
                
                /* Enter GPIO output mode - this will set the output pin to the EDPOL value */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8MasterChannel), CCR_MODE_MASK_U32, CCR_MODE_GPO_U32 );

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8MasterChannel), (~(CCR_EDPOL_MASK_U32 | CCR_MODE_MASK_U32)));
                
                /* Disable interrupt */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8MasterChannel), CCR_FEN_MASK_U32);
                
                /* Clear interrupt flag */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, (uint32)u8MasterChannel), CSR_FLAG_BIT_U32);
                
#ifdef EMIOS_UCDIS_AVAILABLE
    #if (EMIOS_UCDIS_AVAILABLE == STD_ON)
                /* Disable unified channel */
                eMios_StopChannel(u8MasterBusIdx);
    #endif
#endif
            }
        }
    }
}
#endif /* PWM_DE_INIT_API */



/*===============================================================================================*/
#if ((PWM_SET_DUTY_CYCLE_API == STD_ON) || (PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON))
/**
* @brief        This function sets the duty cycle for the specified eMIOS channel
* @details      This function:
*                   - disable the interrupt and clear the interrupt flag
*                   - sets the A register with value 0 for OPWFMB mode for 0% duty cycle
*                   - sets the A and B registers with value 0 for OPWMB mode for 0% duty cycle
*                   - sets the A and B registers with value 1 for OPWMT mode for 0% duty cycle
*                   - sets the A register with value period for OPWFMB mode for 100% duty cycle
*                   - sets the A register with 0 and B register with period for OPWMB mode for
*                     100% duty cycle
*                   - sets the A register with 1 and B register with period+1 for OPWMT mode for
*                     100% duty cycle
*                   - for duty cycle not equal to 0% and 100%, FLAG event is enabled
*                   - sets the A register with value duty cycle for OPWFMB mode
*                   - sets the A register with value offset+1 and B register with duty cycle + offset
*                     for OPWMB mode
*                   - sets the A register with value offset+1 and B register with
*                     (duty cycle + offset) % period for OPWMT mode
*
* @param        u8IdxChannelConfig  - PWM channel id
*               u16DutyCycle        - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*               peMiosIpConfig      - pointer to EMIOS IP configuration
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetDutyCycle
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlBus;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx = 0xFFU;
    
    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    
    /* Save current channel control register configured value in local variable */
    u32CtrlMode = (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);
    
    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_32();
    
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
    Pwm_eMios_aChannelDuty[u8IdxChannelConfig] = u16DutyCycle;
#endif
    
    if ((PWM_MODE_OPWFMB_U32 == u32CtrlMode) || (PWM_MODE_OPWFM_U32 == u32CtrlMode))
    {
        nPeriod = Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel];
    }
    else
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        u32CtrlBus = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_BSL_MASK_U32);
        
        u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, u32CtrlBus);
        nPeriod = Pwm_eMios_aChannelPeriod[u8MasterBusIdx];
    }

    if ((PWM_MODE_OPWMCB_LEAD_DEADTIME_U32 == u32CtrlMode) || (PWM_MODE_OPWMCB_TRAIL_DEADTIME_U32 == u32CtrlMode))
    {
#if (PWM_FEATURE_OPWMCB == STD_ON)   
        Pwm_eMios_SetRegs_OPWMCB_mode
        (
            u8IdxChannelConfig, 
            nPeriod, 
            u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_DAOC_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_DAOC == STD_ON)   
        Pwm_eMios_SetRegs_DAOC_mode
        (
            u8IdxChannelConfig, 
            nPeriod, 
            u16DutyCycle,
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWMT_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWMT == STD_ON)   
        Pwm_eMios_SetRegs_OPWMT_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            u16DutyCycle,
            Pwm_eMios_aChannelOffset[u8IdxChannelConfig],
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWMB_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWMB == STD_ON)
        Pwm_eMios_SetRegs_OPWMB_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            u16DutyCycle,
            Pwm_eMios_aChannelOffset[u8IdxChannelConfig],
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWM_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWM == STD_ON)
        Pwm_eMios_SetRegs_OPWM_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            u16DutyCycle,
            Pwm_eMios_aChannelOffset[u8IdxChannelConfig],
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWFMB_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWFMB == STD_ON)
        Pwm_eMios_SetRegs_OPWFMB_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWFM_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWFM == STD_ON)
        Pwm_eMios_SetRegs_OPWFM_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else 
    {
        /* Do nothing */
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_32();
    
}
#endif /* PWM_SET_DUTY_CYCLE_API || PWM_SET_DUTY_CYCLE_NO_UPDATE_API */



/*===============================================================================================*/
#if ((PWM_SET_PERIOD_AND_DUTY_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON))
/**
* @brief        This function sets the period and the duty cycle for the specified eMIOS channel
* @details      This function is applicable for mode OPWFMB
*                   - disable the interrupt and clear the interrupt flag
*                   - sets the A register with value 0 and B register with period for 0% duty cycle
*                   - sets the A and B registers with value period for 100% duty cycle
*                   - for duty cycle not equal to 0% and 100% set the A register with value duty cycle
*                     and B register with value period
*
* @param        u8IdxChannelConfig - PWM channel id
*               nPeriod            - PWM signal period value
*               u16DutyCycle       - PWM duty cycle value 0x0000 for 0% ... 0x8000 for 100%
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetPeriodAndDuty
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    /** @brief  Assigned eMIOS hardware module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS hardware channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
#endif
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempPeriod;
    VAR         (uint16,                        AUTOMATIC)                      u16TempDutyCycle;

    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
#endif
    
    nTempPeriod = nPeriod;
    u16TempDutyCycle = u16DutyCycle;
    
    /* Save current mode in local variable */
    u32CtrlMode = peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32;
    
    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_33();
    
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
    Pwm_eMios_aChannelDuty[u8IdxChannelConfig] = u16TempDutyCycle;
#endif

    /* If new period is 0, save previous period value and set duty cycle to 0 */
    if ((Pwm_PeriodType)0U == nTempPeriod)
    {
        nTempPeriod = Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel];
        u16TempDutyCycle = (uint16)0U;
    }

    /* Store new period value for current channel */
    Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel] = nTempPeriod;
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    if (((uint16)0U == u16TempDutyCycle) || (PWM_DUTY_CYCLE_100 == u16TempDutyCycle))
    {
        /* No transitions in the signal */
        Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
    }
    else
    {
        /* Transitions available in the signal */
        Pwm_eMios_aDutyState[u8ModuleIdx] |= ((uint32)1U << u8ChannelIdx);
    }
#endif
    
    if (PWM_MODE_DAOC_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_DAOC == STD_ON)   
        Pwm_eMios_SetRegs_DAOC_mode
        (
            u8IdxChannelConfig, 
            nTempPeriod, 
            u16TempDutyCycle, 
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWFMB_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWFMB == STD_ON)
        Pwm_eMios_SetRegs_OPWFMB_mode
        (
            u8IdxChannelConfig,
            nTempPeriod,
            u16TempDutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWFM_U32 == u32CtrlMode)
    {
#if (PWM_FEATURE_OPWFM == STD_ON)
        Pwm_eMios_SetRegs_OPWFM_mode
        (
            u8IdxChannelConfig,
            nTempPeriod,
            u16TempDutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            eSyncUpdate,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else 
    {
        /* Do nothing */
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_33();
    
}
#endif /* PWM_SET_PERIOD_AND_DUTY_API || PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API */



/*===============================================================================================*/
#if (PWM_SET_OUTPUT_TO_IDLE_API == STD_ON)
/**
* @brief        This function sets the generated eMIOS channel to the idle value configured
* @details      This function
*                   - puts the channel in High or Low state by writing to the Control Register
*                     based on the configured Idle state
*                   - puts the eMIOS channel into GPIO mode
*
* @param        u8IdxChannelConfig - PWM channel id
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetOutputToIdle
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{

    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;  
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;  

    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_34();
    
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
    Pwm_eMios_aChannelDuty[u8IdxChannelConfig] = (uint16)0U;
#endif

    if (PWM_HIGH == Pwm_eMios_aChannelIdleState[u8IdxChannelConfig])
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_EDPOL_MASK_U32);
    }
    else
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_EDPOL_MASK_U32);
    }
    
    /* Enter GPIO output mode */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_MODE_MASK_U32, CCR_MODE_GPO_U32);
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    /* No transitions in the current signal status */
    Pwm_eMios_aDutyState[u8ModuleIdx] &= ~((uint32)1U << u8ChannelIdx);
#endif
    
    /* Disable channel interrupts */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
    
    /* Clear pending interrupt flag for the channel */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
    
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    if ((uint8)0U != Pwm_eMios_aOutputUpdateDisable[u8IdxChannelConfig])
    {
        /* Output update enabled so no need for synchronization */
        Pwm_eMios_aOutputUpdateDisable[u8IdxChannelConfig] = (uint8)0U;
        
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_OUDR_ADDR32(u8ModuleIdx), (uint32)((uint32)1 << (u8ChannelIdx)));
    }
#endif
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_34();
    
}
#endif /* PWM_SET_OUTPUT_TO_IDLE_API */



/*===============================================================================================*/
#if (PWM_GET_OUTPUT_STATE_API == STD_ON)
/**
* @brief        This function returns the PWM signal output state
* @details      This function returns the PWM Channel state as High or Low
*
* @param        u8IdxChannelConfig - PWM channel id
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*
* @return       Pwm_OutputStateType - PWM signal output logic value
*                   PWM_LOW - The output state of PWM channel is low
*                   PWM_HIGH - The output state of PWM channel is high
*
*/
FUNC(Pwm_OutputStateType, PWM_CODE) Pwm_eMios_GetOutputState
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{

    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST) peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                  u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                  u8ChannelIdx;
    VAR         (Pwm_OutputStateType,           AUTOMATIC)                  eOutputState;

    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (0U != (REG_READ32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CSR_UCOUT_MASK_U32))
    {
        eOutputState = PWM_HIGH;
    }
    else
    {
        eOutputState = PWM_LOW;
    }

    return eOutputState;
}
#endif /* PWM_GET_OUTPUT_STATE_API */



/*===============================================================================================*/
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
/**
* @brief        This function disables the user notifications
* @details      This function
*                   - disables the notification
*                   - disables the FEN bit in Control register for OPWMB and OPWFMB modes
*                   - clear interrupt flag in Status register and Set the DMA bit in
*                     Control register for OPWMT mode
*
* @param        u8IdxChannelConfig - PWM channel id
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_DisableNotification
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;

    
    /* Extract the generic channel information from configuration structure */
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_36();
    
#if (PWM_FEATURE_OPWMT == STD_ON)
    if (PWM_MODE_OPWMT_U32 != (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32))
    {
#endif

#if (PWM_FEATURE_DAOC == STD_ON)
        if (PWM_MODE_DAOC_U32 != (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32))
        {
#endif
            /* No need to clear the flag as it will be cleared in EnableNotification before interrupts are enabled */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
#if (PWM_FEATURE_DAOC == STD_ON)
        }
#endif
    
#if (PWM_FEATURE_OPWMT == STD_ON)
    }
    else
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32 );

        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_DMA_MASK_U32 );
    }
#endif

    /* Note that notifications are disabled for this channel */
    Pwm_eMios_aChannelNotifType[(uint8)peMiosChannelConfig->u8HwChannel] = (uint8)0U;
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_36();
}
#endif /* PWM_NOTIFICATION_SUPPORTED */



/*===============================================================================================*/
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
/**
* @brief        This function disables the user notifications
* @details      This function
*                   - enables the notification
*                   - sets the Edge select bit in control register if notification is both edges
*                   - clears the Edge select bit in control register if notification is both edges
*                   - clears the interrupt flag and enables the FLAG event for OPWMB and OPWFMB modes
*                   - clear interrupt flag in Status register and clear the DMA bit in
*                     Control register for OPWMT mode
*
* @param        u8IdxChannelConfig - PWM channel id
*               eNotification      - notification type to be enabled
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_EnableNotification
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    VAR         (Pwm_EdgeNotificationType,      AUTOMATIC)                      eNotification,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{

    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
#if ((PWM_FEATURE_OPWMT == STD_ON) || (PWM_FEATURE_DAOC == STD_ON))
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
#endif


    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

    /* Save current channel control register configured value in local variable */
#if ((PWM_FEATURE_OPWMT == STD_ON) || (PWM_FEATURE_DAOC == STD_ON))
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;
#endif
    
    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_35();
    
    /* Note that notifications are enabled for this channel */
    Pwm_eMios_aChannelNotifType[(uint8)peMiosChannelConfig->u8HwChannel] = (uint8)eNotification;
    
    /* Only enable notifications if channel is not in idle state */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    if (CCR_MODE_GPO_U32 != (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
    {
        
#if (PWM_FEATURE_OPWMT == STD_ON)
        /* Activation edge not available in OPWMT */
        if (PWM_MODE_OPWMT_U32 != (u32CtrlRegVal & CCR_MODE_MASK_U32))
        {
#endif

            /* Change activation edge if required */
            if (PWM_BOTH_EDGES == eNotification)
            {
#if (PWM_FEATURE_DAOC == STD_ON)
                if (PWM_MODE_DAOC_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_DAOC_MODE_EDGE_SELECT_MASK_U32);
                }
                else
                {
#endif
                    /* Notification on both edges */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_MODE_EDGE_SELECT_MASK_U32);
#if (PWM_FEATURE_DAOC == STD_ON)
                }
#endif
            }
            else
            {
#if (PWM_FEATURE_DAOC == STD_ON)
                if (PWM_MODE_DAOC_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_DAOC_MODE_EDGE_SELECT_MASK_U32);
                }
                else
                {
#endif
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_MODE_EDGE_SELECT_MASK_U32);
#if (PWM_FEATURE_DAOC == STD_ON)
                }
#endif
            }
            
#if (PWM_FEATURE_DAOC == STD_ON)
            if (PWM_MODE_DAOC_U32 != (u32CtrlRegVal & CCR_MODE_MASK_U32))
            {
#endif
                /* Clear interrupt flag by writing 1 to this bit */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);
#if (PWM_FEATURE_DAOC == STD_ON)
            }
#endif

            /* Transitions are present in the signal (duty != 0%, 100%), u16DutyCycle doesn't affect trigger in OPWMT mode */
            if ((uint32)0U != (((uint32)1U << u8ChannelIdx) & Pwm_eMios_aDutyState[u8ModuleIdx]))
            {
                /* Enable interrupts */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
            else
            {
                /* Disable interrupts */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FEN_MASK_U32);
            }
    
#if (PWM_FEATURE_OPWMT == STD_ON)
        }
        /* OPWMT */
        else
        { 
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);

            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_DMA_MASK_U32);
        }
#endif
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_35();
}
#endif /* PWM_NOTIFICATION_SUPPORTED */








/*===============================================================================================*/
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
/**
* @brief        Implementation specific function to get the Duty cycle of the given PWM channel
*
* @param        u8IdxChannelConfig - PWM channel id
*
* @return       uint16 
*
*/
FUNC(uint16, PWM_CODE)  Pwm_eMios_GetChannelState
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig
)
{
    
    return Pwm_eMios_aChannelDuty[u8IdxChannelConfig];
    
}
#endif /* PWM_GET_CHANNEL_STATE_API */



/*================================================================================================*/
#if (PWM_SET_CLOCK_MODE_API == STD_ON)
/**
* @brief        This function set the value of the prescaler on all eMios channels
* @details      This function set the channel prescaler depending on the value ePrescaler parameter. 
*               - ePrescaler value is either PWM_PRIMARY_PRESCALER or PWM_ALTERNATIVE_PRESCALER
*               - The values associated to either types are configured by tooling and the physical values 
*                 associated are written to hardware registry.
*
* @param        ePrescaler     - prescaler logical values selectable between PWM_PRIMARY_PRESCALER or PWM_ALTERNATIVE_PRESCALER
*               peMiosIpConfig - Pointer to configuration structure of eMios channels
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetClockMode
(
    VAR         (Pwm_PrescalerType,             AUTOMATIC)                      ePrescaler,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;    
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32tempctrlRegVal;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8Counter;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlBus;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterModule;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterChannel;
    VAR         (uint8,                         AUTOMATIC)                      aMasterBusUse[PWM_EMIOS_CHANNEL_NO];
    
    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_39();
    
    for (u8Counter = 0U; u8Counter < (Pwm_eMios_ChannelType)PWM_EMIOS_CHANNEL_NO; u8Counter++)
    {
        aMasterBusUse[u8Counter] = (uint8)0xFFU;
    }

    /* Modify prescaler of each eMios channel */
    for (u8Counter = 0U; u8Counter < peMiosIpConfig->u8NumChannels; u8Counter++)
    {
        /* Only handle EMIOS channels */
        peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8Counter];

        u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        u32CtrlBus = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_BSL_MASK_U32);
        
        if (PWM_BUS_INTERNAL_COUNTER_U32 == u32CtrlBus)
        {
            /* Stop eMios channel - this will stop the internal counter */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), CCR_UCPREN_MASK_U32);
            
            /* Set internal counter to 1 */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CCNTR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)1U);
            
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            u32CtrlRegVal = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx)) & ((uint32)(~(CCR_UCPRE_MASK_U32))));
            
            if (PWM_ALTERNATIVE_PRESCALER == ePrescaler)
            {
                u32tempctrlRegVal = (uint32)(((uint32)peMiosChannelConfig->u32ControlValue >> (uint32)23U) & ((uint32)0x3U)); 
            }
            else 
            {
                u32tempctrlRegVal = (uint32)(((uint32)peMiosChannelConfig->u32ControlValue >> CCR_UCPRE_SHIFT) & ((uint32)0x3U));           
            }

            /* Write the new prescaler value to the control register buffer value */
            u32CtrlRegVal |= (uint32)((uint32)u32tempctrlRegVal << CCR_UCPRE_SHIFT);
            
            /* Write to the control register buffer value */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_WRITE32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)u32CtrlRegVal);

            /* Re-start eMios channel */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), CCR_UCPREN_MASK_U32);
        }
        else
        {
            u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, u32CtrlBus);
            
            if (aMasterBusUse[u8MasterBusIdx] == (uint8)0xFFU)
            {
                aMasterBusUse[u8MasterBusIdx] = (uint8)1U;
                
                /* Get module id and channel id of master bus */
                u8MasterModule  = EMIOS_MODULE_INDEX_U8(u8MasterBusIdx);
                u8MasterChannel = EMIOS_CHANNEL_INDEX_U8(u8MasterBusIdx);

                /* Stop eMios channel - this will stop the internal counter */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_UCPREN_MASK_U32);
                
                /* Set internal counter to 1 */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CCNTR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (uint32)1U);

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                u32CtrlRegVal = (REG_READ32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel)) & ((uint32)(~(CCR_UCPRE_MASK_U32))));
            
                if (PWM_ALTERNATIVE_PRESCALER == ePrescaler)
                {
                    u32tempctrlRegVal = (uint32)(((uint32)peMiosChannelConfig->u32ControlValue >> (uint32)23U) & ((uint32)0x3U)); 
                }
                else 
                {
                    u32tempctrlRegVal = (uint32)(((uint32)peMiosChannelConfig->u32ControlValue >> CCR_UCPRE_SHIFT) & ((uint32)0x3U));           
                }
    
                /* Write the new prescaler value to the control register buffer value */
                u32CtrlRegVal |= (uint32)((uint32)u32tempctrlRegVal << CCR_UCPRE_SHIFT);
                
                /* Write to the control register buffer value */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_WRITE32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), (uint32)u32CtrlRegVal);

                /* Re-start eMios channel */
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_UCPREN_MASK_U32);
            }
        }
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_39();
}
#endif /* PWM_SET_CLOCK_MODE_API */



/*===============================================================================================*/
#if (PWM_SET_COUNTER_BUS_API == STD_ON)
/**
* @brief        Implementation specific function to set the frequency of PWM channel
*               running on PWM_MODE_OPWMB_U32, PWM_MODE_OPWM_U32 or PWM_MODE_OPWMT_U32 mode
* @details      This function
*                   - changes the counter bus from Bus A to Bus Diverse or vice versa
*                   - Bus selection bits will be configured in Control register
*                   - update duty cycle to the configured default value
*
* @param        u8IdxChannelConfig - PWM channel id
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*               u32Bus             - the eMIOS bus to change to
*
* @return       void
*
* @implements   Pwm_eMios_SetCounterBus_Activity
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetCounterBus
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig,
    VAR         (uint32,                        AUTOMATIC)                      u32Bus
)
{
    
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nOffset = (Pwm_PeriodType)0U;
#endif
#if (PWM_FEATURE_OPWMT == STD_ON)
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTrigger = (Pwm_PeriodType)0U;
#endif
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx = 0xFFU;
#if ((PWM_EMIOS_16_BITS_VARIANT == STD_OFF) && ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON)))
    VAR         (Pwm_uint64,                    AUTOMATIC)                      u64Temp = 0U;
#endif


    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);  
    
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_37();
    
    /* Get new period from new master bus */
    u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, u32Bus);
    nPeriod = Pwm_eMios_aChannelPeriod[u8MasterBusIdx];
    
    if ((boolean)TRUE == (peMiosChannelConfig->bPwmOffsetTriggerDelay))
    {
#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
    
#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))
        nOffset = Pwm_eMios_aChannelOffset[u8IdxChannelConfig];
        nOffset = ((nOffset * nPeriod) / Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel]);
#endif
    
#if (PWM_FEATURE_OPWMT == STD_ON)
        nTrigger = Pwm_eMios_aTriggerDelay[u8IdxChannelConfig];
        nTrigger = ((nTrigger * nPeriod) / Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel]);
#endif

#else
    
#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))
        nOffset = Pwm_eMios_aChannelOffset[u8IdxChannelConfig];
        u64Temp = ((Pwm_uint64)nOffset * (Pwm_uint64)nPeriod);
        nOffset = (Pwm_PeriodType)Pwm_eMios_Div64((Pwm_uint64)u64Temp, (Pwm_uint64)Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel]);
#endif
        
#if (PWM_FEATURE_OPWMT == STD_ON)
        nTrigger = Pwm_eMios_aTriggerDelay[u8IdxChannelConfig];
        u64Temp = ((Pwm_uint64)nTrigger * (Pwm_uint64)nPeriod);
        nTrigger = (Pwm_PeriodType)Pwm_eMios_Div64((Pwm_uint64)u64Temp, (Pwm_uint64)Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel]);
#endif

#endif

#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))
        /* Update the channel period with the period of the new selected counter bus */
        Pwm_eMios_aChannelOffset[u8IdxChannelConfig] = nOffset;
#endif
        
#if (PWM_FEATURE_OPWMT == STD_ON)
        /* Update new trigger delay */
        Pwm_eMios_aTriggerDelay[u8IdxChannelConfig] = nTrigger;
#endif
    }
    
    

    /* Set the new counter bus */
    if (PWM_BUS_DIVERSE_U32 == u32Bus)
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_BSL_MASK_U32, CCR_BSL_BUS_DIVERSE_U32 << CCR_BSL_SHIFT);
    }
    else if (PWM_BUS_A_U32 == u32Bus)
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_BSL_MASK_U32 );
    }
    else if (PWM_BUS_F_U32 == u32Bus)
    {
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        REG_RMW32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_BSL_MASK_U32, CCR_BSL_BUS_F_U32 << CCR_BSL_SHIFT);
    }
    else
    {
        /* Do nothing */
    }

    /* Update duty cycle to the configured default value */
    if ((PWM_MODE_OPWMCB_LEAD_DEADTIME_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32)) || \
        (PWM_MODE_OPWMCB_TRAIL_DEADTIME_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32)))
    {
#if (PWM_FEATURE_OPWMCB == STD_ON)
        /* Update new period */
        Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel] = nPeriod;
        
        Pwm_eMios_SetRegs_OPWMCB_mode
        (
            u8IdxChannelConfig, 
            nPeriod, 
            peMiosChannelConfig->u16PwmDefaultDutyCycle,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_DAOC_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
    {
#if (PWM_FEATURE_DAOC == STD_ON)
        /* Update new modulo */
        Pwm_DAOC_aChannelModulo[peMiosChannelConfig->u8HwChannel] = nPeriod;
        nPeriod = Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel];
        
        Pwm_eMios_SetRegs_DAOC_mode
        (
            u8IdxChannelConfig, 
            nPeriod, 
            peMiosChannelConfig->u16PwmDefaultDutyCycle, 
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWMT_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
    {
#if (PWM_FEATURE_OPWMT == STD_ON)   
        /* Update new period */
        Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel] = nPeriod;

        Pwm_eMios_SetRegs_OPWMT_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            peMiosChannelConfig->u16PwmDefaultDutyCycle,
            nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWMB_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
    {
#if (PWM_FEATURE_OPWMB == STD_ON)
        /* Update new period */
        Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel] = nPeriod;

        Pwm_eMios_SetRegs_OPWMB_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            peMiosChannelConfig->u16PwmDefaultDutyCycle,
            nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else if (PWM_MODE_OPWM_U32 == (u32CtrlRegVal & CCR_MODE_MASK_U32))
    {
#if (PWM_FEATURE_OPWM == STD_ON) 
        /* Store the nPeriod that the master UC is using */
        Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel] = nPeriod;
        
        Pwm_eMios_SetRegs_OPWM_mode
        (
            u8IdxChannelConfig,
            nPeriod,
            peMiosChannelConfig->u16PwmDefaultDutyCycle,
            nOffset,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
            PWM_EMIOS_UPDATE_ASYNCHRONOUS,
#endif
            peMiosChannelConfig
        );
#endif
    }
    else    
    {
        /* Do nothing */
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_37();
    
}
#endif /* PWM_SET_COUNTER_BUS_API */



/*===============================================================================================*/
#if (PWM_SET_CHANNEL_OUTPUT_API == STD_ON)
/**
* @brief        Implementation specific function to set the state of the PWM pin as requested
*               for the current cycle
* @details      This function is useful to to set the state of the PWM pin as requested for the 
*               current cycle and continues with normal PWM operation from the next cycle
*                   - OPWFMB, OPWFM: if the passed state is Active, force a match on B Register 
*                     otherwise force a match on A Register
*                   - OPWMB, OPWM or OPWMT: if the passed state is Active, force a match on A Register
*                     otherwise force a match on B Register
*                   - The force match is done by setting the FORCMA and FORCMB bits is Control Register
*
* @param        u8IdxChannelConfig - PWM channel id
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*               eState             - Active - Inactive state of the channel
*
* @return       void
*
* @implements   Pwm_eMios_SetChannelOutput_Activity
*
*/
FUNC(void,PWM_CODE) Pwm_eMios_SetChannelOutput
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig,
    VAR         (Pwm_StateType,                 AUTOMATIC)                      eState
)
{
    
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    
    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    
    /* Save current channel control register configured value in local variable */
    u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;

    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_38();
    
    if ((PWM_MODE_OPWFMB_U32 == ((uint32)u32CtrlRegVal & CCR_MODE_MASK_U32)) || \
        (PWM_MODE_OPWFM_U32 == ((uint32)u32CtrlRegVal & CCR_MODE_MASK_U32)))
    {
        if (PWM_EMIOS_ACTIVE == eState) 
        {
            /* Force match B */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32);
        }
        else if (PWM_EMIOS_INACTIVE == eState)
        {
            /* Force match A */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32);
        }
        else
        {
            /* Do nothing */
        }
    }
    else 
    {
        if (PWM_EMIOS_ACTIVE == eState) 
        {
            /* Force match A */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMA_MASK_U32);
        }
        else if (PWM_EMIOS_INACTIVE == eState)
        {
            /* Force match B */
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_FORCMB_MASK_U32);
        }
        else
        {
            /* Do nothing */
        }
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_38();
    
}
#endif /* PWM_SET_CHANNEL_OUTPUT_API */



/*===============================================================================================*/
#if (PWM_SET_TRIGGER_DELAY_API == STD_ON)
/**
* @brief        Implementation specific function to set the trigger delay for PWM channel
*               running on PWM_MODE_OPWMT_U32 mode
*                   - write trigger delay to alternate A register for OPWMT mode
*
* @param        u8IdxChannelConfig - PWM channel id
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*               nTriggerDelay      - trigger delay
*
* @return       void
*
* @implements   Pwm_eMios_SetTriggerDelay_Activity
*
*/
FUNC(void,PWM_CODE) Pwm_eMios_SetTriggerDelay
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTriggerDelay
)
{
    
#if (PWM_FEATURE_OPWMT == STD_ON)
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    

    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

    Pwm_eMios_aTriggerDelay[u8IdxChannelConfig] = (Pwm_PeriodType)nTriggerDelay;

    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32(EMIOS_ALTA_ADDR32(u8ModuleIdx, u8ChannelIdx),(uint32)( (uint32)nTriggerDelay + (uint32)1U));
#else
    (void) u8IdxChannelConfig;
    (void) peMiosIpConfig;
    (void) nTriggerDelay;
#endif

}
#endif /* PWM_SET_TRIGGER_DELAY_API */



/*=============================================================================================*/
#if ((PWM_SET_PHASE_SHIFT_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
/**
* @brief        Implementation specific function to set phase shift for PWM channel
*               running on OPWMB, OPWM and OPWMT mode.
*               For current implementation, the u16Period parameter is ignored.
*
* @param        u8IdxChannelConfig - PWM channel id
*               u16Period          - period value
*               u16PhaseShift      - phase shift value
*               peMiosIpConfig     - pointer to EMIOS IP Configuration
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetPhaseShift
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      u16Period,
    VAR         (uint16,                        AUTOMATIC)                      u16PhaseShift,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    VAR         (Pwm_eMios_UpdateType,          AUTOMATIC)                      eSyncUpdate,
#endif
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to eMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlBus;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nTempPeriod;
    VAR         (uint16,                        AUTOMATIC)                      u16TempDutyCycle;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPhaseShift;

    
    (void)u16Period;
    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    
    u16TempDutyCycle = (uint16)0x4000U;
    
    /* Save current mode in local variable */
    u32CtrlMode = peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32;
    
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    u32CtrlBus = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_BSL_MASK_U32);
    
    u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, u32CtrlBus);
    
    nTempPeriod = Pwm_eMios_aChannelPeriod[u8MasterBusIdx];
    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_49();

    /* If new period is 0, save previous period value and set duty cycle to 0 */
    if ((Pwm_PeriodType)0U != nTempPeriod)
    {
#if (PWM_GET_CHANNEL_STATE_API == STD_ON)
        Pwm_eMios_aChannelDuty[u8IdxChannelConfig] = u16TempDutyCycle;
#endif

        /* Calculate the offset value which is proporation of phase shift value in period */
#if ((PWM_FEATURE_OPWMB == STD_ON) || (PWM_FEATURE_OPWM == STD_ON) || (PWM_FEATURE_OPWMT == STD_ON))        
#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
        nPhaseShift = Pwm_eMios_ComputeDutycycle_16bits(nTempPeriod, u16PhaseShift);
#else
        nPhaseShift = Pwm_eMios_ComputeDutycycle_32bits(nTempPeriod, u16PhaseShift);
#endif
#endif
    
        if (PWM_MODE_OPWMT_U32 == u32CtrlMode)
        {
#if (PWM_FEATURE_OPWMT == STD_ON)   
            Pwm_eMios_SetRegs_OPWMT_mode
            (
                u8IdxChannelConfig,
                nTempPeriod,
                u16TempDutyCycle,
                nPhaseShift,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                peMiosChannelConfig
            );
#endif
        }
        else if (PWM_MODE_OPWMB_U32 == u32CtrlMode)
        {
#if (PWM_FEATURE_OPWMB == STD_ON) 
            Pwm_eMios_SetRegs_OPWMB_mode
            (
                u8IdxChannelConfig,
                nTempPeriod,
                u16TempDutyCycle,
                nPhaseShift,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                peMiosChannelConfig
            );
#endif
        }
        else if (PWM_MODE_OPWM_U32 == u32CtrlMode)
        {
#if (PWM_FEATURE_OPWM == STD_ON) 
            Pwm_eMios_SetRegs_OPWM_mode
            (
                u8IdxChannelConfig,
                nTempPeriod,
                u16TempDutyCycle,
                nPhaseShift,
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
                eSyncUpdate,
#endif
                peMiosChannelConfig
            );
#endif
        }
        else 
        {
            /* Do nothing */
        }
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_49();
}
#endif /* PWM_SET_PHASE_SHIFT_API || PWM_SET_PHASE_SHIFT_NO_UPDATE_API */



/*=============================================================================================*/
#if (PWM_SYNC_UPDATE_API == STD_ON)
/**
* @brief        This function updates the duty cycle and-or period for the specified PWM channel.
*               The value written does not take effect until calling SyncUpdate API.
*
* @param        u8HwModule          eMIOS hardware module index
*
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SyncUpdate
(
    VAR         (uint8,                         AUTOMATIC)                      u8ModuleIndex,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to eMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS hardware module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS hardware channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint8,                         AUTOMATIC)                      u8Index;
    VAR         (uint32,                        AUTOMATIC)                      OudisRegVal = (uint32)0U;

    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_40();
    
    /* Read OUDIS register */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    OudisRegVal = REG_READ32(EMIOS_OUDR_ADDR32(u8ModuleIndex));
    
#if ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON))
    /* Loop all channels in given configuration */
    for (u8Index = (uint8)0U; u8Index < (uint8)PWM_EMIOS_CHANNELS_MAX_U8; u8Index++)
    {
        if ((uint8)0U != Pwm_eMios_aOutputUpdateDisable[u8Index])
        {
            peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8Index];
    
            u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
            u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
            
            if (u8ModuleIdx == u8ModuleIndex)
            {
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
                /* If current state transition is occurred and next state is no transition */
                if (((uint32)0U != (uint32)(Pwm_eMios_aDutyState[u8ModuleIndex] & ((uint32)1U << u8ChannelIdx))) && \
                    ((uint8)0U == Pwm_eMios_aNextDutyState[u8Index]))
                {
                    /* Disable and clear interrupt flag */
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIndex, u8Index), CCR_FEN_MASK_U32);
                 
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIndex, u8Index) , CSR_FLAG_BIT_U32);
                    
                    /* No transition in the current signal status */
                    Pwm_eMios_aDutyState[u8ModuleIndex] &= ~((uint32)1U << u8ChannelIdx);
                }
                /* If current state is no transition and next state is transition */
                else if (((uint32)0U == (uint32)(Pwm_eMios_aDutyState[u8ModuleIndex] & ((uint32)1U << u8ChannelIdx))) && \
                         ((uint8)1U == Pwm_eMios_aNextDutyState[u8Index]))
                {
                    /* if notifications enabled */
                    if ((uint8)0U != Pwm_eMios_aChannelNotifType[peMiosChannelConfig->u8HwChannel])
                    {
                        /* FLAG event enabled */
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIndex, u8ChannelIdx), CCR_FEN_MASK_U32);
                    }
                    else
                    {
#endif
                        /* Disable and clear interrupt flag */
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIndex, u8ChannelIdx), CCR_FEN_MASK_U32);
                     
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_WRITE32(EMIOS_CSR_ADDR32(u8ModuleIndex, u8ChannelIdx), CSR_FLAG_BIT_U32);
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
                    }
                
                    /* Transitions in the current signal status */
                    Pwm_eMios_aDutyState[u8ModuleIndex] |= ((uint32)1U << u8ChannelIdx);
                }
                else
                {
                    /* Do nothing */
                }
#endif
                
                /* If current state is no transition and next state is no transition but output level changed, 
                   This case is for OPWMCB mode when changing from 100% duty to 0% duty */
                if ((uint8)2U == Pwm_eMios_aNextDutyState[u8Index])
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_BIT_CLEAR32((EMIOS_OUDR_ADDR32(u8ModuleIndex)), (uint32)((uint32)1 << (u8ChannelIdx)));
                    
                    if (PWM_MODE_OPWMCB_LEAD_DEADTIME_U32 == ((uint32)(peMiosChannelConfig->u32ControlValue) & CCR_MODE_MASK_U32))
                    {
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIndex, u8ChannelIdx), CCR_FORCMA_MASK_U32);
                    }
                    else
                    {
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIndex, u8ChannelIdx), CCR_FORCMB_MASK_U32);
                    }
                }
                
                
                /* Update OUDIS register value for synchronization */
                OudisRegVal &= ~((uint32)1U << u8ChannelIdx);
            }
        }
    }
#endif
    
    /* Write OUDIS register */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32(EMIOS_OUDR_ADDR32(u8ModuleIndex), OudisRegVal);

    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_40();
    
}
#endif /* PWM_SYNC_UPDATE_API */








/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON)  && (PWM_NOTIFICATION_SUPPORTED == STD_ON))
/**
* @brief        Pwm_eMios_ValidateNotification
* @details      This function will check validate of Edge type with polarity
*
* @param        u8IdxChannelConfig  PWM channel id in top configuration structure
*               eNotification       Notification edge type
*
* @return       E_NOT_OK            Notification handler is not valid
*
*/
FUNC(Std_ReturnType, PWM_CODE) Pwm_eMios_ValidateNotification
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    VAR         (Pwm_EdgeNotificationType,      AUTOMATIC)                      eNotification
)
{
    
    VAR         (Std_ReturnType,                AUTOMATIC)                      nRetVal = (Std_ReturnType)E_OK;

    
    if (
         ((PWM_LOW == Pwm_eMios_aChannelPolarity[u8IdxChannelConfig]) && (PWM_FALLING_EDGE == eNotification))||
         ((PWM_HIGH == Pwm_eMios_aChannelPolarity[u8IdxChannelConfig]) && (PWM_RISING_EDGE == eNotification))
       )
    {
        nRetVal = (Std_ReturnType)E_NOT_OK;
    }
    
    return nRetVal;
}
#endif



/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON) && (PWM_SET_COUNTER_BUS_API == STD_ON))
/**
* @brief        Pwm_eMios_ValidateCounterBus
* @details      This function will check validate of Edge type with polarity
*
* @param        u8IdxChannelConfig  PWM channel id in top configuration structure
*               u32Bus              Current counter bus
*               peMiosIpConfig      Pointer to PWM top configuration structure
*
* @return       E_NOT_OK            Notification handler is not valid
*
*/
FUNC(Std_ReturnType, PWM_CODE) Pwm_eMios_ValidateCounterBus
(
    VAR         (uint32,                        AUTOMATIC)                      u32Bus
)
{
    
    VAR         (Std_ReturnType,                AUTOMATIC)                      nRetval = (Std_ReturnType)E_OK;
    
    
    if (PWM_BUS_INTERNAL_COUNTER_U32 == u32Bus)
    {
        nRetval = (Std_ReturnType)E_NOT_OK;
    }
    
    return nRetval;
}
#endif



/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON) && (PWM_SET_TRIGGER_DELAY_API == STD_ON))
/**
* @brief        This function get the current period value.
*
* @param        u8IdxChannelConfig   EMIOS channel id
*               peMiosIpConfig       Pointer to EMIOS channels configuration structure
*
* @return       Pwm_PeriodType
*
*/
FUNC(Pwm_PeriodType, PWM_CODE) Pwm_eMios_GetCurrentPeriodValue
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlBus;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusIdx;
    

    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

    /* Save current channel control register configured value in local variable */
    u32CtrlMode = (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);

    if ((PWM_MODE_DAOC_U32 == u32CtrlMode) || (PWM_MODE_OPWFMB_U32 == u32CtrlMode) || (PWM_MODE_OPWFM_U32 == u32CtrlMode))
    {
        nPeriod = Pwm_eMios_aChannelPeriod[peMiosChannelConfig->u8HwChannel];
    }
    else 
    {
        /* Using master bus */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        u32CtrlBus = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_BSL_MASK_U32);
        
        u8MasterBusIdx = (uint8)Pwm_eMios_GetMasterBus(u8ModuleIdx, u8ChannelIdx, u32CtrlBus);
        nPeriod = Pwm_eMios_aChannelPeriod[u8MasterBusIdx];
    }
    
    return nPeriod;
}



/*===============================================================================================*/
/**
* @brief        This function validate the mode of current channel
*
* @param        u8IdxChannelConfig   EMIOS channel id
*               peMiosIpConfig       Pointer to EMIOS channels configuration structure
*
* @return       Std_ReturnType
*
*/
FUNC(Std_ReturnType, PWM_CODE) Pwm_eMios_ValidateTriggerMode
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;   
    VAR         (Std_ReturnType,                AUTOMATIC)                      nRetVal = (Std_ReturnType)E_OK;

    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    /* Save current channel control register configured value in local variable */
    u32CtrlMode = (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);
    
    if (PWM_MODE_OPWMT_U32 == u32CtrlMode)
    {
        nRetVal = (Std_ReturnType)E_OK;
    }
    else
    {
        nRetVal = (Std_ReturnType)E_NOT_OK;
    }

    return nRetVal;
}
#endif



/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON) && ((PWM_SET_PERIOD_AND_DUTY_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON)))
FUNC(Pwm_PeriodType, PWM_CODE) Pwm_eMios_GetMaxPeriodValue
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{

#if (PWM_FEATURE_DAOC == STD_ON)
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
#endif
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nMaxPeriod;
    
    
#if (PWM_FEATURE_DAOC == STD_OFF)
    (void) u8IdxChannelConfig;
    (void) peMiosIpConfig;
#endif

#if (PWM_FEATURE_DAOC == STD_ON)    
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    /* Save current channel control register configured value in local variable */
    u32CtrlMode = (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);

    if (PWM_MODE_DAOC_U32 == u32CtrlMode)
    {
        nMaxPeriod = (Pwm_PeriodType)Pwm_DAOC_aChannelModulo[peMiosChannelConfig->u8HwChannel];
    }
    else
    {
#endif
        nMaxPeriod = (Pwm_PeriodType)PWM_MAX_PERIOD;
#if (PWM_FEATURE_DAOC == STD_ON)
    }
#endif

    return nMaxPeriod;
}
#endif



/*===============================================================================================*/
#if (PWM_PARAM_CHECK == STD_ON)
/**
* @brief        This function validate offset parameter with duty and period default
*
* @param        peMiosIpConfig       Pointer to EMIOS channels configuration structure
*
* @return       uint8
*
*/
FUNC(uint8, PWM_CODE) Pwm_eMios_ValidateParamOffset
(
    P2CONST     (Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlRegVal;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nRegDuty;
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8Counter;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32ControlReg;
    /** @brief  Return value */
    VAR         (uint8,                         AUTOMATIC)                      u8RetVal = (uint8)0U;


    for (u8Counter = 0U; u8Counter < peMiosIpConfig->u8NumChannels; u8Counter++)
    {
        peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8Counter];

        nPeriod = peMiosChannelConfig->nPwmDefaultPeriod;
        u16DutyCycle = peMiosChannelConfig->u16PwmDefaultDutyCycle;
        
        /* Save current channel control register configured value in local variable */
        u32CtrlRegVal = peMiosChannelConfig->u32ControlValue;
        u32ControlReg = (uint32)(u32CtrlRegVal & CCR_MODE_MASK_U32);

        if ((PWM_MODE_OPWMB_U32 == u32ControlReg) || (PWM_MODE_OPWM_U32 == u32ControlReg) || (PWM_MODE_OPWMT_U32 == u32ControlReg))
        {
            if (peMiosChannelConfig->nPwmOffset >= peMiosChannelConfig->nPwmDefaultPeriod)
            {
                u8RetVal = (uint8)PWM_E_CHANNEL_OFFSET_VALUE;
            }
            else
            {
#if (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
                nRegDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
                nRegDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif
                /* Duty Cycle != 0 and != 100% */
                if (((Pwm_PeriodType)0U != nRegDuty) && (PWM_DUTY_CYCLE_100 != u16DutyCycle) && ((uint16)0U != u16DutyCycle))
                {
                    if ((nRegDuty + peMiosChannelConfig->nPwmOffset) >= nPeriod)
                    {
                        u8RetVal = (uint8)PWM_E_OPWMB_CHANNEL_OFFSET_DUTYCYCLE_RANGE;
                    }
                }
            }
        }
    }
    
    return u8RetVal;
}
#endif

/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON) && ((PWM_SET_DUTY_CYCLE_API == STD_ON) || (PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON)))
/**
* @brief        This function validate offset parameter with duty cycle input
*
* @param        peMiosIpConfig - Structure of EMIOS channels configuration
*
* @return       uint8
*
*/
FUNC(uint8, PWM_CODE) Pwm_eMios_ValidateParamOffsetDuty
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    VAR         (uint16,                        AUTOMATIC)                      u16DutyCycle,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nPeriod;
    VAR         (Pwm_PeriodType,                AUTOMATIC)                      nRegDuty;
    /** @brief  Return value */
    VAR         (uint8,                         AUTOMATIC)                      u8RetVal;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32ControlReg;
    

    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];

    nPeriod = peMiosChannelConfig->nPwmDefaultPeriod;

    u8RetVal = (uint8)0U;
    
    u32ControlReg = (uint32)(peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);
    
    if ((PWM_MODE_OPWMB_U32 == u32ControlReg) || (PWM_MODE_OPWM_U32 == u32ControlReg) || (PWM_MODE_OPWMT_U32 == u32ControlReg))
    {
        if (peMiosChannelConfig->nPwmOffset >= peMiosChannelConfig->nPwmDefaultPeriod)
        {
            u8RetVal = (uint8)PWM_E_CHANNEL_OFFSET_VALUE;
        }
        else
        {
            if ((PWM_MODE_OPWMB_U32 == (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32)) || \
                (PWM_MODE_OPWM_U32 == (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32)))
            {
#if  (PWM_EMIOS_16_BITS_VARIANT == STD_ON)
                nRegDuty = Pwm_eMios_ComputeDutycycle_16bits(nPeriod, u16DutyCycle);
#else
                nRegDuty = Pwm_eMios_ComputeDutycycle_32bits(nPeriod, u16DutyCycle);
#endif
                /* Duty Cycle != 0 and != 100% */
                if (((Pwm_PeriodType)0U != nRegDuty) && (PWM_DUTY_CYCLE_100 != u16DutyCycle) && ((uint16)0U != u16DutyCycle))
                {
                    if ((nRegDuty + peMiosChannelConfig->nPwmOffset) >= nPeriod)
                    {
                        u8RetVal = (uint8)PWM_E_OPWMB_CHANNEL_OFFSET_DUTYCYCLE_RANGE;
                    }
                }
            }
        }
    }
    
    return u8RetVal;
}
#endif



/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON) && ((PWM_SET_PHASE_SHIFT_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON)))
/**
* @brief        Pwm_eMios_ValidateChannelSetPhaseShift
* @details      This function will check given channel with Pwm_SetPhaseShift supported
*
* @param        u8IdxChannelConfig  Channel index in configuration structure
*               peMiosIpConfig      Pointer to eMIOS channels configuration structure
*
* @return       Std_ReturnType      E_NOT_OK - Pwm_SetPhaseShift is not supported this channel
*
*/
FUNC(Std_ReturnType, PWM_CODE) Pwm_eMios_ValidateChannelSetPhaseShift
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{

    /** @brief  Return value for function */
    VAR         (Std_ReturnType,                AUTOMATIC)                      u8RetVal = (Std_ReturnType)E_OK;
    /** @brief  Pointer to eMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
    
    
    /* Get eMIOS channel configuration */
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    /* Get eMIOS channel operation mode */
    u32CtrlMode = (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);


    if ((PWM_MODE_OPWMB_U32 != u32CtrlMode) && (PWM_MODE_OPWM_U32 != u32CtrlMode) && (PWM_MODE_OPWMT_U32 != u32CtrlMode))
    {
        u8RetVal = (Std_ReturnType)E_NOT_OK;
    }

    return u8RetVal;
    
}
#endif /* PWM_PARAM_CHECK && PWM_SET_PHASE_SHIFT_API */



/*===============================================================================================*/
#if ((PWM_PARAM_CHECK == STD_ON) && ((PWM_SET_DUTY_CYCLE_NO_UPDATE_API == STD_ON) || (PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API == STD_ON) || (PWM_SET_PHASE_SHIFT_NO_UPDATE_API == STD_ON)))
/**
* @brief        Pwm_eMios_ValidateChannelSync
* @details      This function will check given channel with synchronization supported
*
* @param        u8IdxChannelConfig  Channel index in configuration structure
*               peMiosIpConfig      Pointer to eMIOS channels configuration structure
*
* @return       Std_ReturnType      E_NOT_OK - Synchronization is not supported this channel
*
*/
FUNC(Std_ReturnType, PWM_CODE) Pwm_eMios_ValidateChannelSync
(
    VAR         (uint8,                         AUTOMATIC)                      u8IdxChannelConfig,
    CONSTP2CONST(Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{

    /** @brief  Return value for function */
    VAR         (Std_ReturnType,                AUTOMATIC)                      u8RetVal = (Std_ReturnType)E_OK;
    /** @brief  Pointer to eMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      u32CtrlMode;
    
    
    /* Get eMIOS channel configuration */
    peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[u8IdxChannelConfig];
    
    /* Get eMIOS channel operation mode */
    u32CtrlMode = (peMiosChannelConfig->u32ControlValue & CCR_MODE_MASK_U32);


    /* Synchronization feature does not support DAOC mode */
    if (PWM_MODE_DAOC_U32 == u32CtrlMode)
    {
        u8RetVal = (Std_ReturnType)E_NOT_OK;
    }
    else 
    {    
        uint8 u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        uint8 u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        
        /* Synchronization feature does not support channel which is in idle state */
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        if (CCR_MODE_GPO_U32 == (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
        {
            u8RetVal = (Std_ReturnType)E_NOT_OK;
        }
    }

    return u8RetVal;
    
}
#endif /* PWM_PARAM_CHECK && (PWM_SET_DUTY_CYCLE_NO_UPDATE_API || PWM_SET_PERIOD_AND_DUTY_NO_UPDATE_API) */



/*================================================================================================*/
/**
* @brief        This function validate the state of pwm channel is idle or not, and the notification
*               is enabled or not
*
* @param        peMiosIpConfig - Structure of EMIOS channels configuration
*
* @return       uint8
*
*/
#if (PWM_POWER_STATE_SUPPORTED == STD_ON)
FUNC(Std_ReturnType, PWM_CODE) Pwm_eMios_ValidateIdleState
(
    P2CONST     (Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig
)
{
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;    
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      nCounter;
    VAR         (Std_ReturnType,                AUTOMATIC)                      nRetVal = (Std_ReturnType)E_OK;

    
    for (nCounter = 0U; nCounter < peMiosIpConfig->u8NumChannels; nCounter++)
    {
        /* Only handle eMIOS channels */
        peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[nCounter];

        u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
        if (CCR_MODE_GPO_U32 != (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32))
        {
            nRetVal = (Std_ReturnType)E_NOT_OK;
            break;
        }
    }
    
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    for (nCounter = 0U; nCounter < (Pwm_eMios_ChannelType)PWM_EMIOS_CHANNEL_NO; nCounter++)
    {
        if((uint8)0U != Pwm_eMios_aChannelNotifType[nCounter])
        {
            nRetVal = (Std_ReturnType)E_NOT_OK;
            break;
        }
    }
#endif

    return nRetVal;
}



/*================================================================================================*/
/**
* @brief        Put PWM channel based on eMIOS to target power mode.
* @details      This function will disable clock if target power mode is Low power, and enable clock
*               if target power mode is full power
*               - ePowerState value is either PWM_LOW_POWER or PWM_FULL_POWER
*               - the values associated to either types are configured by tooling and the phisical values 
*                 associated are written to hardware registry.
*
* @param        ePowerState    - target mode value selectable between PWM_LOW_POWER or PWM_FULL_POWER
*               peMiosIpConfig - Pointer to configuration structure of eMios channels
*                 
* @return       void
*
*/
FUNC(void, PWM_CODE) Pwm_eMios_SetPowerState
(
    P2CONST     (Pwm_eMios_IpConfigType,        AUTOMATIC,  PWM_APPL_CONST)     peMiosIpConfig,
    VAR         (Pwm_PowerStateType,            AUTOMATIC)                      ePowerState
)
{
    /** @brief  Pointer to EMIOS channel specific configuration */
    P2CONST     (Pwm_eMios_ChannelConfigType,   AUTOMATIC,  PWM_APPL_CONST)     peMiosChannelConfig;    
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (Pwm_eMios_ControlType,         AUTOMATIC)                      nCtrlRegVal;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      nCounter;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterModule;
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8MasterChannel;
    VAR         (uint8,                         AUTOMATIC)                      u8MasterBusMode[PWM_EMIOS_CHANNEL_NO];

    
    SchM_Enter_Pwm_PWM_EXCLUSIVE_AREA_41();
    
    for (nCounter = 0U; nCounter < (Pwm_eMios_ChannelType)PWM_EMIOS_CHANNEL_NO; nCounter++)
    {
        u8MasterBusMode[nCounter] = (uint8)0xFFU;
    }

    for (nCounter = 0U; nCounter < peMiosIpConfig->u8NumChannels; nCounter++)
    {
        /* Only handle EMIOS channels */
        peMiosChannelConfig = &(*peMiosIpConfig->pChannelsConfig)[nCounter];

        u8ModuleIdx = (uint8)EMIOS_MODULE_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);
        u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8((uint8)peMiosChannelConfig->u8HwChannel);

        /* Save current channel control register configured value in local variable */
        nCtrlRegVal = peMiosChannelConfig->u32ControlValue;

        if (PWM_BUS_INTERNAL_COUNTER_U32 == ((uint32)nCtrlRegVal & CCR_BSL_MASK_U32))
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            if (PWM_LOW_POWER == ePowerState)
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);
            }
            else
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);
            }
        }
        else
        {
            u8MasterBusMode[nCounter] = 0x00U;
        }
        if ((PWM_MODE_OPWMCB_TRAIL_DEADTIME_U32 == (nCtrlRegVal & CCR_MODE_MASK_U32)) ||
            (PWM_MODE_OPWMCB_LEAD_DEADTIME_U32 == (nCtrlRegVal & CCR_MODE_MASK_U32))
           )
        {
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            if (PWM_LOW_POWER == ePowerState)
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);
            }
            else
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx), CCR_UCPREN_MASK_U32);
            }
        }
    }

    /* Configuration for master bus */
    for (nCounter = 0U; nCounter < PWM_EMIOS_CHANNEL_NO; nCounter++)
    {
        /* Master bus is used */
        if ((uint8)0U == u8MasterBusMode[nCounter]) 
        {
            u8MasterModule  = EMIOS_MODULE_INDEX_U8(nCounter);
            u8MasterChannel = EMIOS_CHANNEL_INDEX_U8(nCounter);

            if (PWM_LOW_POWER == ePowerState)
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_CLEAR32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel),CCR_UCPREN_MASK_U32);
            }
            else
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                REG_BIT_SET32(EMIOS_CCR_ADDR32(u8MasterModule, (uint32)u8MasterChannel), CCR_UCPREN_MASK_U32 );
            }
        }
    }
    
    SchM_Exit_Pwm_PWM_EXCLUSIVE_AREA_41();
}
#endif







/*===============================================================================================*/
#if ((PWM_NOTIFICATION_SUPPORTED == STD_ON) || (PWM_FEATURE_DAOC == STD_ON))
/**
* @brief        Interrupt service routine to process the eMIOS interrupt
* @details      This function
*                   - clears the unified channel interrupt flag bit in Control register
*                   - calls the IPW layer handler
*                   - re-calculate and update register A,B for channel use DAOC mode
*
* @param        u8HwChannel      EMIOS channel ID that triggered the interrupt
*
* @return       void
*
* @implements   Pwm_eMios_ProcessCommonInterrupt_Activity
*
*/
/* @violates @ref Pwm_eMios_c_REF_3 These functions represent the ISRs of the driver. */
FUNC(void,PWM_CODE) Pwm_eMios_ProcessCommonInterrupt
(
    VAR         (Pwm_ChannelType,               AUTOMATIC)                      u8HwChannel
)
{
    /** @brief  Assigned eMIOS HW module index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ModuleIdx;
    /** @brief  Assigned eMIOS HW channel index */
    VAR         (Pwm_eMios_ChannelType,         AUTOMATIC)                      u8ChannelIdx;
    VAR         (uint32,                        AUTOMATIC)                      u32TempStatus;
#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    VAR         (uint8,                         AUTOMATIC)                      u8Notification;
#endif   
#if (PWM_FEATURE_DAOC == STD_ON)
    /** @brief  Channel mode */
    VAR         (uint32,                        AUTOMATIC)                      u32ChMode;   
    /** @brief  Edge polarity value */
    VAR         (uint32,                        AUTOMATIC)                      u32EdpolValue;   
    /** @brief  ucout bit value */
    VAR         (uint32,                        AUTOMATIC)                      u32UcoutValue;   
    /** @brief  Store the calculated register A value */
    VAR         (uint32,                        AUTOMATIC)                      u32RegAValue;   
    /** @brief  Store the calculated register B value */
    VAR         (uint32,                        AUTOMATIC)                      u32RegBValue;   
    /** @brief  Store the duty is apply to register */
    VAR         (uint32,                        AUTOMATIC)                      u32RegDuty;   
#endif


    u8ModuleIdx  = (uint8)EMIOS_MODULE_INDEX_U8(u8HwChannel);
    u8ChannelIdx = (uint8)EMIOS_CHANNEL_INDEX_U8(u8HwChannel);

    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    u32TempStatus = ((REG_READ32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx))) & CSR_FLAG_MASK_U32);

    /* Clear unified channel interrupt flag */
    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
    REG_WRITE32( EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx), CSR_FLAG_BIT_U32);

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
    u8Notification = Pwm_eMios_aChannelNotifType[u8HwChannel];
#endif

    /* Call Common Interrupt Routine */
    if (
        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */    
        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
         (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & (CCR_DMA_MASK_U32 | CCR_FEN_MASK_U32)) ==
         ((CCR_DMA_ASSIGN_INT_U32 << CCR_DMA_SHIFT) | ( CCR_FEN_ENABLE_U32 << CCR_FEN_SHIFT))
       )
    {
        if ((uint32)0U != u32TempStatus)
        {
#if (PWM_FEATURE_DAOC == STD_ON)
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            u32ChMode = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_MODE_MASK_U32);
        
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            u32EdpolValue = (REG_READ32(EMIOS_CCR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CCR_EDPOL_MASK_U32);
           
            /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
            /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
            /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
            u32UcoutValue = (REG_READ32(EMIOS_CSR_ADDR32(u8ModuleIdx, u8ChannelIdx)) & CSR_UCOUT_MASK_U32);
            
            if (PWM_MODE_DAOC_U32 == u32ChMode)
            {
                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                u32RegDuty = (uint32)(Pwm_eMios_aChannelPeriod[u8HwChannel] - Pwm_eMios_aDaocChannelDuty[u8HwChannel]);

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                u32RegAValue = (((u32RegDuty) + REG_READ32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx))) % Pwm_DAOC_aChannelModulo[u8HwChannel]);
                
                if ((uint32)0U != u32RegAValue)
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), u32RegAValue);
                }
                else
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), Pwm_DAOC_aChannelModulo[u8HwChannel]);
                }

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                u32RegDuty = REG_READ32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx));

                /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                u32RegBValue = ((Pwm_eMios_aChannelPeriod[u8HwChannel]+u32RegDuty)%Pwm_DAOC_aChannelModulo[u8HwChannel]);
                
                if ((uint32)0U != u32RegBValue)
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), u32RegBValue);
                }
                else
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), Pwm_DAOC_aChannelModulo[u8HwChannel]);
                }
            }
            else if (CCR_MODE_DAOC_BOTH_U32 == u32ChMode)
            {
                if (u32EdpolValue != (u32UcoutValue << 6U))
                {
                    u32RegAValue = ((Pwm_eMios_aChannelPeriod[u8HwChannel] + 
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    REG_READ32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx))) % Pwm_DAOC_aChannelModulo[u8HwChannel]);
                    
                    if ((uint32)0U != u32RegAValue)
                    {
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), u32RegAValue);
                    } 
                    else
                    {
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_WRITE32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), Pwm_DAOC_aChannelModulo[u8HwChannel]);
                    }
                }
                else
                {
                    /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                    /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                    /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                    u32RegBValue = ((Pwm_eMios_aDaocChannelDuty[u8HwChannel] + REG_READ32(EMIOS_CADR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx))) % Pwm_DAOC_aChannelModulo[u8HwChannel]);
                    
                    if ((uint32)0U != u32RegBValue)
                    {
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), u32RegBValue);
                    }
                    else
                    {
                        /* @violates @ref Pwm_eMios_c_REF_4 Cast from unsigned long to pointer */
                        /* @violates @ref Pwm_eMios_c_REF_5 Cast between a pointer type and an integral type */
                        /* @violates @ref Pwm_eMios_c_REF_6 Impermissible cast of composite expression */
                        REG_WRITE32(EMIOS_CBDR_ADDR32(u8ModuleIdx, (uint32)u8ChannelIdx), Pwm_DAOC_aChannelModulo[u8HwChannel]);
                    }
                }
            }
            else
            {
                /* Do nothing */
            }
#endif

#if ((PWM_NOTIFICATION_SUPPORTED == STD_ON) && (PWM_FEATURE_DAOC == STD_ON))
            /* Call IPW interrupt handler at valid edge match */
            if (CCR_MODE_DAOC_BOTH_U32 == u32ChMode) 
            {
                if ((Pwm_PeriodType)0U != Pwm_eMios_aDaocChannelDuty[u8HwChannel])
                {
                    if ((uint8)0U != u8Notification)
                    {
                        Pwm_Ipw_eMiosChannelNotification(u8HwChannel);
                    }
                }
            }
            else if (PWM_MODE_DAOC_U32 == u32ChMode)
            {
                if ((Pwm_PeriodType)0U != Pwm_eMios_aDaocChannelDuty[u8HwChannel])
                {
                    if ((uint8)0U != u8Notification)
                    {
                        if (u32EdpolValue != (u32UcoutValue << 6U))
                        {
                            Pwm_Ipw_eMiosChannelNotification(u8HwChannel);
                        }
                    }
                }
            }
            else
            {
#endif 

#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)
                if ((uint8)0U != u8Notification)
                {
                    /* Note: For PWM, interrupts are not enabled if the u8Notification function is a NULL_PTR. 
                       Therefore the code does not check for NULL_PTR before calling the u8Notification function */
                    Pwm_Ipw_eMiosChannelNotification(u8HwChannel);
                }
#endif

#if ((PWM_NOTIFICATION_SUPPORTED == STD_ON) && (PWM_FEATURE_DAOC == STD_ON))
            }
#endif
        }
    }
}
#endif /* PWM_NOTIFICATION_SUPPORTED || PWM_FEATURE_DAOC */



#define PWM_STOP_SEC_CODE
/*
* @violates @ref Pwm_eMios_c_REF_2 This violation is not fixed since the inclusion
*                of Pwm_MemMap.h is as per AUTOSAR requirement 
* @violates @ref Pwm_eMios_c_REF_1 Pwm_MemMap.h is included after each section define
*                in order to set the current memory section as defined by AUTOSAR
*/
#include "Pwm_MemMap.h"


#endif /* PWM_EMIOS_USED */

#ifdef __cplusplus
}
#endif

/** @} */
