/**
*   @file    Mcl_Dma.c
*   @version 1.0.0
*
*   @brief   AUTOSAR Mcl - eDMA low level driver.
*   @details eDMA module low level functions.
*
*   @addtogroup MCL_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eDMA
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/


#ifdef __cplusplus
extern "C"{
#endif

/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct.
* This violation is due to the requirement that requests to have a file version check.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and namespace shall be distinct.
* This violation is due to the requirement that requests to have a file version check.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
* This violation is due to the requirement that requests to have a file version check.
*
* @section [global]
* Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
* This violation is due to the requirement that requests to have a file version check.
*
* @section Mcl_Dma_c_REF_1
* Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once.
* This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement [SWS_MemMap_00003].
*
* @section Mcl_DMA_c_REF_2
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer to object and an integer type.
* The cast is used to access memory mapped registers.
*
* @section Mcl_DMA_c_REF_3
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void and an arithmetic type.
* This macro computes the address of any register by using the hardware offset of the controller. The address calculated as an unsigned int is passed to a macro for initializing the pointer with that address.
*
* @section Mcl_DMA_c_REF_4
* Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by preprocessor directives or comments.
* <MA>_MemMap.h is included after each section define in order to set the current memory section as defined by AUTOSAR.
*
* @section Mcl_DMA_c_REF_5
* Violates MISRA 2012 Advisory Rule 8.7, Objects shall be defined at block scope if they are only accessed from within a single function.
* These objects are used in various parts of the code.
*
* @section Mcl_DMA_c_REF_6
* Violates MISRA 2012 Advisory Rule 13.4, The result of an assignment operator should not be used.
* They are use to reduce code complexity.
*
* @section Mcl_DMA_c_REF_7
* Violates MISRA 2012 Required Rule 10.8, The value of a composite expression shall no be cast to a different essential type category or a wider essential type.
* This violation is due to the complex expression (macro) is given as parameter is not evaluated at preprocessing step.
*
* @section Mcl_DMA_c_REF_8
* Violates MISRA 2012 Advisory Rule 12.3, The comma operator should not be used.
* The comma is used  to abstract the trusted call function and to determine when the return into user mode is needed.
*
* @section Mcl_DMA_c_REF_9
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable code.
* This violation due to the fact that the value of defined macro is gotten from resource and always be a fixed value.
*
* @section Mcl_DMA_c_REF_10
* Violates MISRA 2012 Required Rule 14.3, Controlling expressions shall not be invariant.
* This violation due to the fact that the value of defined macro is gotten from resource and always be a fixed value.
*
*
*/

/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Mcal.h"
#include "Mcl_Dma.h"
#include "StdRegMacros.h"
#include "CDD_Mcl.h"
#include "CDD_Mcl_Cfg.h"
#include "SchM_Mcl.h"
#ifdef MCL_ENABLE_USER_MODE_SUPPORT
    #if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
        #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
            #define USER_MODE_REG_PROT_ENABLED               (STD_ON)
            #include "RegLockMacros.h"
        #endif
    #endif
#endif
#ifdef MCL_DISABLE_DEM_REPORT_ERROR_STATUS
#if (MCL_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
#include "Dem.h"
#endif
#endif

#include "Mcl_IPW.h"
#include "Mcl_IPW_Notif.h"
/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define MCL_DMA_VENDOR_ID_C                    43
#define MCL_DMA_AR_RELEASE_MAJOR_VERSION_C     4
#define MCL_DMA_AR_RELEASE_MINOR_VERSION_C     3
#define MCL_DMA_AR_RELEASE_REVISION_VERSION_C  1
#define MCL_DMA_SW_MAJOR_VERSION_C             1
#define MCL_DMA_SW_MINOR_VERSION_C             0
#define MCL_DMA_SW_PATCH_VERSION_C             0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/

#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    #if ((MCL_DMA_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
         (MCL_DMA_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Mcl_Dma.c and Mcal.h are different"
    #endif
#endif

/* Check if source file and StdRegMacros header file are of the same Autosar version */
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
    #if ((MCL_DMA_AR_RELEASE_MAJOR_VERSION_C != STDREGMACROS_AR_RELEASE_MAJOR_VERSION) || \
         (MCL_DMA_AR_RELEASE_MINOR_VERSION_C != STDREGMACROS_AR_RELEASE_MINOR_VERSION))
            #error "AutoSar Version Numbers of Mcl_Dma.c and StdRegMacros.h are different"
    #endif
#endif

#if (MCL_DMA_VENDOR_ID_C != MCL_DMA_VENDOR_ID)
    #error "Mcl_Dma.c and Mcl_Dma.h have different vendor IDs"
#endif
/* Check if source file and Mcl_Dma header file are of the same Autosar version */
#if ((MCL_DMA_AR_RELEASE_MAJOR_VERSION_C != MCL_DMA_AR_RELEASE_MAJOR_VERSION) || \
     (MCL_DMA_AR_RELEASE_MINOR_VERSION_C != MCL_DMA_AR_RELEASE_MINOR_VERSION) || \
     (MCL_DMA_AR_RELEASE_REVISION_VERSION_C != MCL_DMA_AR_RELEASE_REVISION_VERSION))
    #error "AutoSar Version Numbers of Mcl_Dma.h and Mcl_Dma.c are different"
#endif
/* Check if source file and Mcl_Dma header file are of the same Software version */
#if ((MCL_DMA_SW_MAJOR_VERSION_C != MCL_DMA_SW_MAJOR_VERSION) || \
     (MCL_DMA_SW_MINOR_VERSION_C != MCL_DMA_SW_MINOR_VERSION) || \
     (MCL_DMA_SW_PATCH_VERSION_C != MCL_DMA_SW_PATCH_VERSION))
    #error "Software Version Numbers of Mcl_Dma.h and Mcl_Dma.c are different"
#endif
#ifdef MCL_DISABLE_DEM_REPORT_ERROR_STATUS
#if (MCL_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
     /* Check if source file and Dem header file are of the same Autosar version */
     #if (( MCL_DMA_AR_RELEASE_MAJOR_VERSION_C != DEM_AR_RELEASE_MAJOR_VERSION) || \
          ( MCL_DMA_AR_RELEASE_MINOR_VERSION_C != DEM_AR_RELEASE_MINOR_VERSION))
         #error "AutoSar Version Numbers of Mcl_Dma.c and Dem.h are different"
     #endif
 #endif
#endif
#endif

/*==================================================================================================
*                                       LOCAL MACROS
==================================================================================================*/


/*==================================================================================================
*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/

/*==================================================================================================
*                                      LOCAL CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                      LOCAL VARIABLES
==================================================================================================*/
#ifdef MCL_ENABLE_DMA
#if (MCL_ENABLE_DMA == STD_ON)

#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
static P2CONST(Mcl_LogicalMemoryConfigType, MCL_VAR,  MCL_APPL_CONST)  Mcl_Dma_pLogicalMemoryConfig  = NULL_PTR;
#endif
/*==================================================================================================
*                                      GLOBAL CONSTANTS
==================================================================================================*/


/*==================================================================================================
*                                      GLOBAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/
#define MCL_START_SEC_CODE
/* @violates @ref Mcl_Dma_c_REF_1 MISRA 2012 Required 4.10*/
/* @violates @ref Mcl_DMA_c_REF_4 MISRA 2012 Advisory 20.1*/
#include "Mcl_MemMap.h"

#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
static FUNC(void, MCL_CODE) Mcl_Dmav2_Init( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance);
#endif
#if (MCL_DMA_V3_INSTANCE_AVAILABLE == STD_ON)
static FUNC(void, MCL_CODE) Mcl_Dmav3_Init( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance);
#endif
#if (MCL_DEINIT_API == STD_ON)
    #if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
static FUNC(void, MCL_CODE) Mcl_Dmav2_DeInit( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance);
    #endif
#if (MCL_DMA_V3_INSTANCE_AVAILABLE == STD_ON)
static FUNC(void, MCL_CODE) Mcl_Dmav3_DeInit( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance);
    #endif
#endif
/*==================================================================================================
*                                       LOCAL FUNCTIONS
==================================================================================================*/

#if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
    #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
        /* @violates @ref Mcl_DMA_c_REF_5 MISRA 2012 Advisory 8.7*/
        FUNC(void, MCL_CODE) Mcl_Dma_Set_User_Access (VAR(uint32, AUTOMATIC) address)
        {
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            SET_USER_ACCESS_ALLOWED(address,DMA_REG_PROT_SIZE);
        }
    #endif        
#endif
/*==================================================================================================
*                                       GLOBAL FUNCTIONS
==================================================================================================*/
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
/**
* @brief        Function that initializes the eDMA module.
* @details      This function sets the DMACR register with the value of "config" and set
*               the channel's priority, ECP and DPA
*
* @param[in]    pConfig - pointer to DMA configuration structure
*
* @return void
*
*/
static FUNC(void, MCL_CODE) Mcl_Dmav2_Init( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance)
{
    /* @brief Variable used for storing used priorities flags */
    VAR(uint16, AUTOMATIC) u16PriorityGrFlags[DMA_GROUPS];
    /* @brief Variable used for storing used channels flags */
    VAR(uint16, AUTOMATIC) u16ChannelGrFlags[DMA_GROUPS];
    /* @brief Variable used for storing current available priority */
    VAR(uint8, AUTOMATIC) u8CurrentPriority = 0U;
    /* @brief Variable used for storing the current channel number from within a DMA instance */
    VAR(uint8, AUTOMATIC) u8CurrentRelativeChannel = 0U;
    /* @brief Variable used for storing the current absolute channel number from all DMA instances */
    VAR(uint8, AUTOMATIC) u8CurrentAbsoluteChannel = 0U;
     /* @brief Variable used for storing the current group from the current DMA instances */
    VAR(uint8, AUTOMATIC) u8CurrentGroup = 0U;
    /* @brief Counter value used in loops */
    VAR(uint8, AUTOMATIC) u8Counter;
    /* @brief u8Reach value used in loops*/
    VAR(uint8, AUTOMATIC) u8Reach = 0U;
    /* @brief u8Reach value used in loops*/
    VAR(uint8, AUTOMATIC) u8StartCounter;
    /* @brief Pointer to DMA channel specific configuration */
    P2CONST(Mcl_DmaChannelConfigType, AUTOMATIC, MCL_APPL_CONST) pDmaChannelConfig;

    for (u8Counter = 0U;u8Counter < DMA_GROUPS;u8Counter++)
    {
        u16PriorityGrFlags[u8Counter] = 0U;
        u16ChannelGrFlags[u8Counter] = 0U;
    }

     /* Enter exclusive area to protect DMA_CR and DMAV2_CPR */
     SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_12();
     /* Dma_Init() should enable minor loop mapping*/
     /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
     /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
     /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
     REG_WRITE32(DMAV2_CR_ADDR32((uint32)dma_instance), (uint32)((*(pConfig->pDmaConfigInstance))[dma_instance].pDmaControl) | DMAV2_MINOR_LOOP_MAPPING_EN_U32);


    /* Initializing channels priorities, ECP and DPA */
    for (u8Counter = 0U; u8Counter < pConfig->NumChannels; u8Counter++)
    {

        pDmaChannelConfig = &((*(pConfig->pChannelsConfig))[u8Counter]);
        if (DMA_MOD_IDX_U32((uint32)pDmaChannelConfig->Dma_Channel) == dma_instance)
        {
            /* Update the DCHPRIn registers. */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE8(DMAV2_CPR((uint32)pDmaChannelConfig->Dma_Channel), (uint8)pDmaChannelConfig->Dma_ChannelPriority);
            #if (MCL_DMA_ENABLE_INIT_DCHMID == STD_ON)
            /* Update the DCHMIDn registers. */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE8(DMAV2_DCHMID((uint32)pDmaChannelConfig->Dma_Channel), (uint8)pDmaChannelConfig->Dma_MasterId);
            #endif

            u8CurrentRelativeChannel = pDmaChannelConfig->Dma_Channel - MCL_EDMAV3_CHANNELS_NO;

            #ifdef MCL_DMA_SETUP_EARS
            #if (MCL_DMA_SETUP_EARS == STD_ON)
            /* Update the EARS register. */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            REG_RMW32(DMAV2_EARS((uint32)u8CurrentRelativeChannel), ((1UL) << (uint32)u8CurrentRelativeChannel), ((pDmaChannelConfig->Dma_AsynchronousRequest) << (uint32)u8CurrentRelativeChannel));
            #endif
            #endif

            #if ( MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON )
            /* Set Error Enable Interrupts register for the corresponding configured channel */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE8(DMAV2_SEEI_ADDR32((uint32)dma_instance), u8CurrentRelativeChannel);
            #endif
            /* calculate to which group u8CurrentRelativeChannel belongs */
            u8CurrentGroup = (uint8)(u8CurrentRelativeChannel / MCL_EDMA_CHANNELS_IN_GROUP) ;
            /* Set the corresponding priority flags - keep only last 4 bits from Dma_ChannelPriority */
            u16PriorityGrFlags[u8CurrentGroup] |=  (uint16)((uint16)0x1U << (uint16)((pDmaChannelConfig->Dma_ChannelPriority) & (((uint16)0x1U << DMA_CH_PRI_MASK_U8) - 0x1U)));
            /* Set the corresponding used channel flags */
            u16ChannelGrFlags[u8CurrentGroup] |=  (uint16)((uint32)0x1U << (u8CurrentRelativeChannel % MCL_EDMA_CHANNELS_IN_GROUP));
        }
        else
        {
          /* Empty else to fix misra */
        }
    }
    if(dma_instance == (DMAV3_INSTANCES_NUMBER_U32))
    {
        u8Reach = DMAV2_CHANNELS_PER_MODULE_U8;
        u8StartCounter = 0U;
    }
    else
    {
       u8Reach = (uint8)(DMAV2_CHANNELS_PER_MODULE_U8 * 2U);
        u8StartCounter = DMAV2_CHANNELS_PER_MODULE_U8;
    }

   /*  the following loop is used for computing the priorities for the channels which didn't have prio configured,
    *  considering the already configured priorities and the fact that all priorities from within a group
    *  must be different, higher than 0, lower than 16 */
    for (u8Counter = u8StartCounter; u8Counter < u8Reach; u8Counter++)
    {
         u8CurrentAbsoluteChannel = u8Counter;
        /* calculate to which group u8Counter belongs */
        u8CurrentGroup = (uint8)(u8Counter / MCL_EDMA_CHANNELS_IN_GROUP);

        /* if channel has no priority assigned */
        if((uint16)0x0U == (u16ChannelGrFlags[u8CurrentGroup] & (uint16)((uint32)0x1U << (u8Counter % MCL_EDMA_CHANNELS_IN_GROUP))))
        {
            u8CurrentPriority = 0U;
            /* Priority not configured for channel, compute corresponding priority */
            while(((uint16)0x0U != (u16PriorityGrFlags[u8CurrentGroup] & (uint16)((uint32)0x1U << u8CurrentPriority))) && (MCL_EDMA_CHANNELS_IN_GROUP >= u8CurrentPriority))
            {
                /* Priority flag is set, increase current priority */
                u8CurrentPriority++;
            }

            /* Set the flag for the corresponding found priority */
            u16PriorityGrFlags[u8CurrentGroup] |= (uint16)((uint32)0x1U << u8CurrentPriority);
            /* Update the DCHPRIn register. */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/             
            REG_WRITE8(DMAV2_CPR((uint32)u8CurrentAbsoluteChannel), u8CurrentPriority);
        }
        else
        {
          /* Empty else to fix misra */
        }
    }

    /* Exit exclusive area */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_12();

}
#endif
#if (MCL_DMA_V3_INSTANCE_AVAILABLE == STD_ON)
/**
* @brief        Function that initializes the eDMA3 module.
* @details
*
* @param[in]    pConfig - pointer to DMA configuration structure
*               dma_instance - dma hardware instance number
* @return void
*
*/

static FUNC(void, MCL_CODE) Mcl_Dmav3_Init( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance)
{
    /** @brief Counter value used in loops */
    VAR(uint8, AUTOMATIC) u8Counter;
    /** Pointer to DMA channel specific configuration */
    P2CONST(Mcl_DmaChannelConfigType, AUTOMATIC, MCL_APPL_CONST) pDmaChannelConfig;
#if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
    #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
        /* @violates @ref Mcl_DMA_c_REF_8 MISRA 2012 Advisory 12.3*/
        Mcal_Trusted_Call1param(Mcl_Dma_Set_User_Access,DMA_0_BASEADDR);
    #endif
#endif
    /* initialize eDMA3_CSR*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_RMW32((DMAV3_CSR_ADDR32((uint32)(dma_instance))), (uint32)DMAV3_CSR_MASK_U32, (uint32)(*(pConfig->pDmaConfigInstance))[dma_instance].pDmaControl);

    /* initialize eDMA3 channel registers*/
    for (u8Counter = 0U; u8Counter < pConfig->NumChannels; u8Counter++)
    {
        pDmaChannelConfig = &((*(pConfig->pChannelsConfig))[u8Counter]);
        if (DMA_MOD_IDX_U32((uint32)pDmaChannelConfig->Dma_Channel) == dma_instance)
        {
            #if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
                #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
                    /* @violates @ref Mcl_DMA_c_REF_8 MISRA 2012 Advisory 12.3*/
                    Mcal_Trusted_Call1param(Mcl_Dma_Set_User_Access,DMAV3_CH_PRI((uint32)pDmaChannelConfig->Dma_Channel));
                #endif
            #endif
            /* Update the CHnPRI registers */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE32(DMAV3_CH_PRI((uint32)pDmaChannelConfig->Dma_Channel), pDmaChannelConfig->Dma_ChannelPriority);
            /* Initialize group priorities */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE32(DMAV3_CH_GRPRI((uint32)pDmaChannelConfig->Dma_Channel), pDmaChannelConfig->Dma_ChannelGroupPriority);
            /* Update the CH_SBR registers. */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE32(DMAV3_CH_SBR((uint32)pDmaChannelConfig->Dma_Channel), pDmaChannelConfig->Dma_MasterId);
            /* Enable interrupt */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            DMAV3_SET_EEI((uint32)pDmaChannelConfig->Dma_Channel);

        }
    }
}
#endif
/**
* @brief        Function that initializes the eDMA2 module.
* @details
*
* @param[in]    pConfig - pointer to DMA configuration structure
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_Init( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance)
{
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    if (MCL_EDMA_V2 == (*(pConfig->pDmaConfigInstance))[dma_instance].dmaVersion )
    {
        /* if the version of the DMA instance is eDMA2 */
        Mcl_Dmav2_Init(pConfig, dma_instance);
    }
#endif
#if (MCL_DMA_V3_INSTANCE_AVAILABLE == STD_ON)
    if (MCL_EDMA_V3 == (*(pConfig->pDmaConfigInstance))[dma_instance].dmaVersion )
    {
        /* if the version of the DMA instance is eDMA3 */
        Mcl_Dmav3_Init(pConfig, dma_instance);
    }
#endif
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    Mcl_Dma_pLogicalMemoryConfig = pConfig->pMclLogicalMemoryConfig ;
#endif
}
#if (MCL_DEINIT_API == STD_ON)
    /**
* @brief        Function that initializes the eDMA3 module.
* @details
*
* @param[in]    pConfig - pointer to DMA configuration structure
*               dma_instance - dma hardware instance number
* @return void
*
*/
#if (MCL_DMA_V3_INSTANCE_AVAILABLE == STD_ON)
static FUNC(void, MCL_CODE) Mcl_Dmav3_DeInit( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance)
{
    /** @brief Counter value used in loops */
    VAR(uint8, AUTOMATIC) u8Counter;
    /** Pointer to DMA channel specific configuration */
    P2CONST(Mcl_DmaChannelConfigType, AUTOMATIC, MCL_APPL_CONST) pDmaChannelConfig;
#if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
    #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
        /* @violates @ref Mcl_DMA_c_REF_8 MISRA 2012 Advisory 12.3*/
        Mcal_Trusted_Call1param(Mcl_Dma_Set_User_Access,DMA_0_BASEADDR);
    #endif
#endif
    /* initialize eDMA3_CSR*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((DMAV3_CSR_ADDR32((uint32)(dma_instance))), (uint32)DMAV3_CSR_DEINIT_VAL_U32);
    /* initialize eDMA3 channel registers*/
    for (u8Counter = 0U; u8Counter < pConfig->NumChannels; u8Counter++)
    {
        pDmaChannelConfig = &((*(pConfig->pChannelsConfig))[u8Counter]);
        if (DMA_MOD_IDX_U32((uint32)pDmaChannelConfig->Dma_Channel) == dma_instance)
        {
        #if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
            #if (MCL_DMA_REG_PROT_AVAILABLE == STD_ON)
                /* @violates @ref Mcl_DMA_c_REF_8 MISRA 2012 Advisory 12.3*/
                Mcal_Trusted_Call1param(Mcl_Dma_Set_User_Access,DMAV3_CH_PRI((uint32)pDmaChannelConfig->Dma_Channel));
            #endif
        #endif
            /* Deinitialize the CHnPRI registers */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE32(DMAV3_CH_PRI((uint32)pDmaChannelConfig->Dma_Channel), DMAV3_DEFAULT_VAL_U32);
            /* Deinitialize group priorities */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE32(DMAV3_CH_GRPRI((uint32)pDmaChannelConfig->Dma_Channel), DMAV3_DEFAULT_VAL_U32);
            /* Disable interrupt bits */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            DMAV3_CLEAR_EEI((uint32)pDmaChannelConfig->Dma_Channel);

        }
    }
}
#endif
/**
* @brief        Function that deinitializes the eDMA2 modules.
* @details      This function deinitialized the underlaying hardware, sets default values to registers.
*
* @param[in]    pConfig - pointer to DMA configuration structure
*               dma_instance - number of the DMA instance to deinitialize
*
* @return void
*
*/
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
static FUNC(void, MCL_CODE) Mcl_Dmav2_DeInit( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance)
{
    /** Pointer to DMA channel specific configuration */
    P2CONST(Mcl_DmaChannelConfigType, AUTOMATIC, MCL_APPL_CONST) pDmaChannelConfig;
    /** Variable used for storing the current channel number from a DMA instance */
    VAR(uint8, AUTOMATIC) u8CurrentRelativeChannel = 0U;
    /** Variable used for storing the current absolute channel number from all existing DMA instances */
    VAR(uint8, AUTOMATIC) u8CurrentAbsoluteChannel = 0U;
    /** Variable used for storing current available priority */
    VAR(uint8, AUTOMATIC) u8CurrentPriority = 0U;
    /** @brief Variable used for storing the current group from the current DMA instances */
    VAR(uint8, AUTOMATIC) u8CurrentGroup = 0U;
    /** @brief Variable used for storing the default value applied to the DCHPRI register */
    VAR(uint8, AUTOMATIC) u8ChPriRegDefaultVal = 0U;
    /** @brief Counter value used in loops */
    VAR(uint8, AUTOMATIC) u8logicalChannel = 0U;

    /** Enter exclusive area to protect DMA_CR and DMAV2_CPR */
     SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_13();
    /** De-initialize DMA_CR */
    /** ERGA and ERCA are set to prepare for changing the channel priorities */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32(DMAV2_CR_ADDR32((uint32)(dma_instance)), (uint32)(DMAV2_CR_DEFAULT_VAL_U32|DMAV2_CR_ERCA_U32|DMAV2_CR_ERGA_U32));
    /** De-initialize channel registers EEI and DCHMID */
    /** Loop through all MCL logical channels configured */
    for (u8logicalChannel = 0U; u8logicalChannel < pConfig->NumChannels; u8logicalChannel++)
    {
        pDmaChannelConfig = &((*(pConfig->pChannelsConfig))[u8logicalChannel]);
        /** set absolute channel */
        u8CurrentAbsoluteChannel = pDmaChannelConfig->Dma_Channel;
        /** if channel corresponds to current dma_instance */         
        if (DMA_MOD_IDX_U32((uint32)u8CurrentAbsoluteChannel) == dma_instance)
        {
            /** set relative channel */
            u8CurrentRelativeChannel = u8CurrentAbsoluteChannel - MCL_EDMAV3_CHANNELS_NO;
            /** Clear Enable Request Register for the corresponding configured channel */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE8(DMAV2_CERQ_ADDR32((uint32)(dma_instance)), u8CurrentRelativeChannel);
            #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
            /** Clear EEI register bit for the corresponding configured channel by using CEEI for atomic operation */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE8(DMAV2_CEEI_ADDR32((uint32)(dma_instance)), u8CurrentRelativeChannel);
            #endif
            #if (MCL_DMA_ENABLE_INIT_DCHMID == STD_ON)
            /** De-initialize the DCHMID register */
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            REG_WRITE8(DMAV2_DCHMID((uint32)u8CurrentAbsoluteChannel), DMAV2_EMI_DIS_U8);
            #endif
        }
    }
    /** De-initialize DCHPRI registers, set default priorities, default TCD for all channels of the current Dma instance */
    /** Loop through all MCL DMA hardware channels from the current Dma instance */
    for (u8CurrentRelativeChannel = 0U; u8CurrentRelativeChannel < MCL_DMA_INSTANCE_CHANNELS_NO; u8CurrentRelativeChannel++)
    {
        u8CurrentPriority = (uint8)(u8CurrentRelativeChannel % MCL_EDMA_CHANNELS_IN_GROUP) ;
        /** Calculate to which group u8CurrentRelativeChannel belongs */
        u8CurrentGroup = (uint8)(u8CurrentRelativeChannel / MCL_EDMA_CHANNELS_IN_GROUP);
        /** Calculate the default value for the DCHPRI register */
        u8ChPriRegDefaultVal = (uint8)(u8CurrentGroup << DMAV2_DCHPRI_GRPPRI_SHIFT_LEFT_U8) | u8CurrentPriority ;
        /** initialize absolute number of the channel */
        u8CurrentAbsoluteChannel = u8CurrentRelativeChannel + MCL_EDMAV3_CHANNELS_NO;
        /** De-initialize the DCHPRI register, write the priority corresponding to the channel number */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_WRITE8(DMAV2_CPR((uint32)u8CurrentAbsoluteChannel), u8ChPriRegDefaultVal);
        /** De-initialize the TCD number 8 to reset the value of biter, channel control/status fields in TCD register */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_WRITE32(DMA_TCD_CHANNEL(u8CurrentAbsoluteChannel,DMA_TCD_8TH_WORD_OFFSET_U32), DMA_TCD_8TH_DEFAULT_VAL_U32);
        /** De-initialize the TCD number 6 to reset the value of citer, doff fields in TCD register */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_WRITE32(DMA_TCD_CHANNEL(u8CurrentAbsoluteChannel,DMA_TCD_6TH_WORD_OFFSET_U32), DMA_TCD_6TH_DEFAULT_VAL_U32);
    }
    /** De-initialize DMA_CR: set ERGA and ERCA to 0 */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32(DMAV2_CR_ADDR32((uint32)(dma_instance)), DMAV2_CR_DEFAULT_VAL_U32);
    /** Exit exclusive area */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_13();
}
#endif
/**
* @brief        Function that deinitializes the eDMA module.
* @details      This function deinitialized the underlaying hardware, sets default values to registers.
*
* @param[in]    pConfig - pointer to DMA configuration structure
*               dma_instance - number of the DMA instance to deinitialize
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_DeInit( P2CONST(Mcl_DmaConfigType, AUTOMATIC, MCL_APPL_CONST) pConfig, Mcl_DmaInstanceType dma_instance)
{
    #if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    if (MCL_EDMA_V2 == (*(pConfig->pDmaConfigInstance))[dma_instance].dmaVersion )
    {
        /* if the version of the DMA instance is eDMA2 */
        Mcl_Dmav2_DeInit(pConfig, dma_instance);
    }
    #endif
    #if (MCL_DMA_V3_INSTANCE_AVAILABLE == STD_ON)
    if (MCL_EDMA_V3 == (*(pConfig->pDmaConfigInstance))[dma_instance].dmaVersion )
    {
        /* if the version of the DMA instance is eDMA3 */
        Mcl_Dmav3_DeInit(pConfig, dma_instance);
    }
    #endif

}
#endif
/*================================================================================================*/
/**
* @brief        Basic configuration of a TCD.
* @details      This function configures the basic fields of a TCD.
*               You can use it in a scatter/gather operations, where you need to configure a TCD, but not one loaded into a channel.
*
* @param[in]      pTcdAddress        - pointer to the address of the TCD.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                    P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor)
{
    VAR(uint32, AUTOMATIC) u32Reg_value;
    VAR(uint32, AUTOMATIC) u32Saddr_value;
    VAR(uint32, AUTOMATIC) u32Daddr_value;
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    u32Saddr_value = Mcl_GetPhysicalAddress((uint32)(config_descriptor->u32saddr));
    u32Daddr_value = Mcl_GetPhysicalAddress((uint32)(config_descriptor->u32daddr));
#else
    u32Saddr_value = (uint32)(config_descriptor->u32saddr);
    u32Daddr_value = (uint32)(config_descriptor->u32daddr);
#endif
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    if((uint32)pTcdAddress > DMAV2_OFFSET_AE_AREA)
    {
        u32Saddr_value = u32Saddr_value - DMAV2_OFFSET_AE_AREA;
        u32Daddr_value = u32Daddr_value - DMAV2_OFFSET_AE_AREA;
    }
#endif

    /* Set saddr */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)(pTcdAddress) + DMA_TCD_1ST_WORD_OFFSET_U32, u32Saddr_value);

    u32Reg_value = (config_descriptor->u32smod<<DMA_SMOD_SHIFT_MASK_U32) |
                   (config_descriptor->u32ssize<<DMA_SSIZE_SHIFT_MASK_U32) |
                   (config_descriptor->u32dmod<<DMA_DMOD_SHIFT_MASK_U32) |
                   (config_descriptor->u32dsize<<DMA_DSIZE_SHIFT_MASK_U32) |
                   (config_descriptor->u32soff);
    /* Enter exclusive area to protect words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_15();

    /* Set smod, ssize, dmod, dsize, soff */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_2ND_WORD_OFFSET_U32, (uint32)u32Reg_value);
    /* Set nbytes */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_3RD_WORD_OFFSET_U32, (uint32)(config_descriptor->u32num_bytes));
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_4TH_WORD_OFFSET_U32, (uint32)(0x0U));
    /* Set daddr */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_5TH_WORD_OFFSET_U32, u32Daddr_value);

    u32Reg_value = (config_descriptor->u32iter<<DMA_ITER_SHIFT_MASK_U32) | config_descriptor->u32doff;
    /* Set citer and doff */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_6TH_WORD_OFFSET_U32, u32Reg_value);
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_7TH_WORD_OFFSET_U32, (uint32)(0x0U));

    u32Reg_value = (uint32)0x0U | (config_descriptor->u32iter<<DMA_ITER_SHIFT_MASK_U32);
    /* Set biter */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_8TH_WORD_OFFSET_U32, u32Reg_value);

    /* Exit exclusive area to protect words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_15();

}


/*================================================================================================*/
/**
* @brief        Basic DMA channel configuration.
* @details      This function configures the basic TCD fields of a channel.
*
* @param[in]      dma_channel        - the number of the channel that will be configured.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                        P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor)
{


    /* Call ConfigTcd with the corresponding channel's TCD address */
    /* Compiler_Warning: This is a cast from uint32 to pointer type (can be 32bit or 64 bit). There is no loss of information, no functional problem. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    Mcl_Dma_ConfigTcd((Mcl_DmaTcdType*)DMA_TCD((uint32)(dma_channel)), config_descriptor);

}


/*================================================================================================*/
/**
* @brief        Function that configures a channel for linking with another channel.
* @details      This function configures a channel with channel-linking functionality.
*
* @param[in]      dma_channel        - the number of the channel that will be configured.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
* @param[in]      next_channel       - is the channel that will be linked.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigLinkedChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                              P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                              VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel)
{
    /* Config TCD according to config_descriptor */
    /* Compiler_Warning: This is a cast from uint32 to pointer type (can be 32bit or 64 bit). There is no loss of information, no functional problem. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    Mcl_Dma_ConfigTcd((Mcl_DmaTcdType*)DMA_TCD((uint32)(dma_channel)), config_descriptor);

    /* Enter exclusive area to protect TCD words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_31();

    /* set major_linkch */
    /* @violates @ref Mcl_DMA_c_REF_9 MISRA 2012 Required 2.1*/
    /* @violates @ref Mcl_DMA_c_REF_10 MISRA 2012 Required 14.3*/
    if ((DMAV3_INSTANCES_NUMBER_U32 != 0U) && (DMAV3_INSTANCES_NUMBER_U32 > DMA_MOD_IDX_U32((uint32)next_channel)))
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_WRITE8(DMA_TCD((uint32)(dma_channel)) + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_CSR_OFFSET_U32, (uint8)next_channel);
    }
    else
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_WRITE8(DMA_TCD((uint32)(dma_channel)) + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_CSR_OFFSET_U32, (uint8)(next_channel - MCL_EDMAV3_CHANNELS_NO));
    }
    /*if the DONE bit is not reset, then seting ELINK is not possible */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLR_DONE((uint32)(dma_channel));
    /** @brief  set the TCD.major_elink bit. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_SET_MAJOR_ELINK((uint32)dma_channel);

    /* Exit exclusive area to protect TCD words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_31();
}



/*================================================================================================*/
/**
* @brief        Function that sets up a channel with scatter/gather functionality.
* @details      This function configures a channel with scatter/gather functionality.
*
* @param[in]      dma_channel        - the number of the channel that will be configured.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
* @param[in]      pNext_tcd          - pointer to the address of the next TCD that will be loaded into the channel.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                                     P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                     P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd)
{
    VAR(uint32, AUTOMATIC) u32pNext_tcd_value;
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = Mcl_GetPhysicalAddress((uint32)(pNext_tcd));
#else
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = (uint32)(pNext_tcd);
#endif
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
        if( (dma_channel > (uint32)(MCL_EDMAV3_CHANNELS_NO)) ||  (dma_channel == (uint32)(MCL_EDMAV3_CHANNELS_NO)))
        {
            u32pNext_tcd_value = u32pNext_tcd_value - DMAV2_OFFSET_AE_AREA;
        }
#endif
    /* Config TCD according to config_descriptor */
    /* Compiler_Warning: This is a cast from uint32 to pointer type (can be 32bit or 64 bit). There is no loss of information, no functional problem. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    Mcl_Dma_ConfigTcd((Mcl_DmaTcdType*)DMA_TCD((uint32)(dma_channel)), config_descriptor);

    /* Set Scatter Gather Address with the address of the next TCD */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)(DMA_TCD((uint32)(dma_channel))) + DMA_TCD_7TH_WORD_OFFSET_U32, u32pNext_tcd_value);

    /* Enter exclusive area to protect TCD words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_30();

    /* the DONE bit must be reset before updating the ESG bit */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLR_DONE((uint32)dma_channel);
    /** @brief set the e_sg bit */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_SET_E_SG((uint32)dma_channel);

    /* Exit exclusive area to protect TCD words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_30();
}




/*================================================================================================*/
/**
* @brief        Function that configures a TCD with channel-linking functionality.
* @details      This function configures a TCD with channel-linking functionality.
*
* @param[in]      pTcdAddress        - pointer to the address of the TCD.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
* @param[in]      next_channel       - is the channel that will be linked.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigLinkedTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                          P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                          VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel)
{

    /* Config TCD according to config_descriptor */
    /* Compiler_Warning: This is a cast from uint32 to pointer type (can be 32bit or 64 bit). There is no loss of information, no functional problem. */
    Mcl_Dma_ConfigTcd(pTcdAddress, config_descriptor);

    /* Enter exclusive area to protect TCD words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_26();
    /* set major_linkch */
    /* Compiler_Warning: The cast is needed to access only the major link part of the word without accessing the flags. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE8((uint32)((uint32)pTcdAddress + DMA_TCD_8TH_WORD_OFFSET_U32 + DMA_TCD_CSR_OFFSET_U32), (uint8)next_channel);

    /** @brief  set the TCD.major_elink bit. */
    /* Compiler_Warning: The cast is needed to access only the major link part of the word without accessing the flags. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_BIT_SET32((uint32)pTcdAddress + DMA_TCD_8TH_WORD_OFFSET_U32, (uint32)DMA_TCD_MAJOR_E_LINK_MASK_U32);

    /* Exit exclusive area to protect TCD words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_26();
}



/*================================================================================================*/
/**
* @brief        Function that configures a TCD with scatter/gather functionality.
* @details      This function configures a TCD with scatter/gather functionality.
*
* @param[in]      pTcdAddress        - pointer to the address of the TCD.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
* @param[in]      pNext_tcd          - pointer to the address of the next TCD that will be loaded into the channel.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                                 P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                 P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd)
{
    VAR(uint32, AUTOMATIC) u32pNext_tcd_value;
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = Mcl_GetPhysicalAddress((uint32)(pNext_tcd));
#else
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = (uint32)(pNext_tcd);
#endif
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    if((uint32)pTcdAddress > DMAV2_OFFSET_AE_AREA)
    {
        u32pNext_tcd_value = u32pNext_tcd_value - DMAV2_OFFSET_AE_AREA;
    }
#endif
    /* Config TCD according to config_descriptor */
    /* Compiler_Warning: This is a cast from uint32 to pointer type (can be 32bit or 64 bit). There is no loss of information, no functional problem. */
    Mcl_Dma_ConfigTcd(pTcdAddress, config_descriptor);

    /* Set Scatter Gather Address with the address of the next TCD */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_7TH_WORD_OFFSET_U32, u32pNext_tcd_value);

    /* Enter exclusive area to protect TCD words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_27();

    /* Set Enable Scatter/Gather Processing */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_BIT_SET32((uint32)pTcdAddress + DMA_TCD_8TH_WORD_OFFSET_U32, (uint32)DMA_TCD_E_SG_MASK_U32);

    /* Exit exclusive area to protect TCD words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_27();
}

/*================================================================================================*/
/**
* @brief        Function that configures a channel for scatter gather and linking with another channel.
* @details      This function configures a channel for scatter gather  with channel-linking functionality.
*
* @param[in]      dma_channel        - the number of the channel that will be configured.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
* @param[in]      next_channel       - is the channel that will be linked.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherLinkedChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) dma_channel,
                                                           P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                           P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd,
                                                           VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel)
{
    VAR(uint32, AUTOMATIC) u32pNext_tcd_value;
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = Mcl_GetPhysicalAddress((uint32)(pNext_tcd));
#else
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = (uint32)(pNext_tcd);
#endif
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    if(( dma_channel > (uint32)(MCL_EDMAV3_CHANNELS_NO)) ||  (dma_channel == (uint32)(MCL_EDMAV3_CHANNELS_NO)))
    {
        u32pNext_tcd_value = u32pNext_tcd_value - DMAV2_OFFSET_AE_AREA;
    }
#endif
    /* Configure linked channel */
    Mcl_Dma_ConfigLinkedChannel(dma_channel, config_descriptor, next_channel);

    /* Set Scatter Gather Address with the address of the next TCD */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)(DMA_TCD(dma_channel)) + DMA_TCD_7TH_WORD_OFFSET_U32, u32pNext_tcd_value);

   /* the DONE bit must be reset before updating the ESG bit */
   /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
   /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
   /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
   /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLR_DONE((uint32)dma_channel);
    /* set the TCD.esg bit. */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_SET_E_SG((uint32)dma_channel);

}

/*================================================================================================*/
/**
* @brief        Function that configures a TCD for scatter gather and linking with another channel.
* @details      This function configures a TCD for scatter gather  with channel-linking functionality.
*
 * @param[in]     pTcdAddress        - Tcd address used for configuring SGA with linking.
* @param[in]      config_descriptor  - a pointer to a structure that contains the necessary data for a basic configuration
*                                      of a  Transfer Control Descriptor (TCD).
* @param[in]      pNext_tcd            - Pointer to the TCD address used for scatter gather
* @param[in]      next_channel       - is the channel that will be linked.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_ConfigScatterGatherLinkedTcd( P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pTcdAddress,
                                                       P2CONST(Mcl_DmaTcdAttributesType, AUTOMATIC, MCL_APPL_CONST) config_descriptor,
                                                       P2VAR(Mcl_DmaTcdType, AUTOMATIC, MCL_APPL_DATA) pNext_tcd,
                                                       VAR(Mcl_DmaChannelType, AUTOMATIC) next_channel)
{
    VAR(uint32, AUTOMATIC) u32pNext_tcd_value;
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = Mcl_GetPhysicalAddress((uint32)(pNext_tcd));
#else
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    u32pNext_tcd_value = (uint32)(pNext_tcd);
#endif
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    if( (uint32)pTcdAddress > DMAV2_OFFSET_AE_AREA)
    {
        u32pNext_tcd_value = u32pNext_tcd_value - DMAV2_OFFSET_AE_AREA;
    }
#endif

    /* Configure linked channel */
    Mcl_Dma_ConfigLinkedTcd(pTcdAddress, config_descriptor, next_channel);

    /* Set Scatter Gather Address with the address of the next TCD */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_WRITE32((uint32)pTcdAddress + DMA_TCD_7TH_WORD_OFFSET_U32, u32pNext_tcd_value);

    /* Set Enable Scatter/Gather Processing */
    /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe. The application should ensure that only addresses that fit in uint32 are used for configuring DMA.*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    REG_BIT_SET32((uint32)pTcdAddress + DMA_TCD_8TH_WORD_OFFSET_U32, (uint32)DMA_TCD_E_SG_MASK_U32);
}

/*================================================================================================*/
/**
* @brief        Function that sets the priority for the DMA channel passed as parameter.
* @details      This function sets the priority for the DMA channel passed as parameter.
*
* @param[in]      nChannel    - the channel number for which the priority is changed.
* @param[in]      nPriority   -  the priority that is assigned to the specified channel.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_SetChannelPriority( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel,
                                             VAR(Mcl_DmaPriorityType, AUTOMATIC) nPriority)
{
    VAR(uint32, AUTOMATIC) u32ChArbitration = 0UL;
    VAR(Mcl_DmaInstanceType, AUTOMATIC) dma_instance = (uint8)DMA_MOD_IDX_U32((uint32)nChannel);
    /* Enter exclusive area to protect DMA_CR and DMAV2_CPR */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_14();
    /* @violates @ref Mcl_DMA_c_REF_9 MISRA 2012 Required 2.1*/
    /* @violates @ref Mcl_DMA_c_REF_10 MISRA 2012 Required 14.3*/
    if (((uint8)DMAV3_INSTANCES_NUMBER_U32 != 0U) && ((uint8)DMAV3_INSTANCES_NUMBER_U32 > dma_instance))
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32ChArbitration = REG_READ32(DMAV3_CSR_ADDR32((uint32)(dma_instance)));

        /* Switch to Round Robin channel arbitration*/
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_RMW32(DMAV3_CSR_ADDR32((uint32)dma_instance), DMAV3_CSR_ERCA_U32, DMAV3_CSR_ERCA_U32);

        /* Set DMAV3_CH_PRI with the priority specified by nPriority to channel nChannel*/
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_RMW32(DMAV3_CH_PRI((uint32)(nChannel)), DMAV3_PRIORITY_MASK_U32, nPriority);

        /* Switch back to initial channel arbitration */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_RMW32(DMAV3_CSR_ADDR32((uint32)dma_instance), DMAV3_CSR_ERCA_U32, (uint32)(u32ChArbitration & DMAV3_CSR_ERCA_U32));
    }
    else
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32ChArbitration = REG_READ32(DMAV2_CR_ADDR32((uint32)dma_instance));

        /* Switch to Round Robin channel arbitration*/
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_RMW32(DMAV2_CR_ADDR32((uint32)dma_instance), DMAV2_CR_ERCA_U32, DMAV2_CR_ERCA_U32);

        /* Set DMAV2_CPR with the priority specified by nPriority to channel nChannel*/
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_RMW8(DMAV2_CPR((uint32)(nChannel)), DMAV2_PRIORITY_MASK_U8, (uint8)nPriority);

        /* Switch back to initial channel arbitration */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        REG_RMW32(DMAV2_CR_ADDR32((uint32)dma_instance), DMAV2_CR_ERCA_U32, (uint32)(u32ChArbitration & DMAV2_CR_ERCA_U32));
    }
    /* Exit exclusive area to protect DMA_CR and DMAV2_CPR */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_14();
}


/*================================================================================================*/
/**
* @brief        Function that starts a transfer on a DMA channel.
* @details      This function starts a transfer on a DMA channel.
*
* @param[in]      nChannel    - the DMA channel to be started.
*
* @return void
*
*/
FUNC(void, MCL_CODE) Mcl_Dma_StartChannel( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel)
{


    #ifdef MCAL_CACHE_RUNTIME_MNGMNT
    #if (STD_ON == MCAL_CACHE_RUNTIME_MNGMNT)
    #ifdef MCL_SYNCRONIZE_CACHE
    #if (STD_ON == MCL_SYNCRONIZE_CACHE)
    VAR(Std_ReturnType, AUTOMATIC) retVal = (Std_ReturnType)E_NOT_OK;
    /* Flush DCACHE to synchronize data */
    retVal = Mcl_IPW_CacheClear(MCL_LMEM_CACHE_ALL);
    if ((Std_ReturnType)E_NOT_OK == retVal)
    {   /* memory synchronization failed, notify user */
        #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
        Mcl_IPW_ErrorNotification(0xFFU, MCL_DMA_MEM_SYNC_ERROR);
        #endif
    }
    else
    {
        /* cache memory sync successful */
    }
    #endif
    #endif
    #endif
    #endif
    /* clear done bit; otherwise on eDMA3 a new transfer is not started */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLR_DONE((uint32)nChannel);
    /* Start the DMA channel nChannel*/
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_START((uint32)nChannel);

}


/*================================================================================================*/
/**
* @brief        Function that indicates if a DMA channel transfer is completed.
* @details      This function indicates if a DMA channel transfer is completed.
*
* @param[in]      nChannel    - the DMA channel to be checked for transfer completed.
* @param[out]     bCompleted  - the status of the DMA transfer.
*
* @return boolean
*
*/
FUNC(boolean, MCL_CODE) Mcl_Dma_IsTransferCompleted( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel)
{
    VAR(boolean, AUTOMATIC) bCompleted = (boolean)FALSE;

    #ifdef MCAL_CACHE_RUNTIME_MNGMNT
    #if (STD_ON == MCAL_CACHE_RUNTIME_MNGMNT)
    #ifdef MCL_SYNCRONIZE_CACHE
    #if (STD_ON == MCL_SYNCRONIZE_CACHE)
    VAR(Std_ReturnType, AUTOMATIC) retVal = (Std_ReturnType)E_NOT_OK;
    #endif
    #endif
    #endif
    #endif


    /* Check if transfer is DONE */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    if((uint32)0UL != DMA_DONE(nChannel))
    {
        /* Transfer is completed */
        bCompleted = (boolean)TRUE;

        #ifdef MCAL_CACHE_RUNTIME_MNGMNT
        #if (STD_ON == MCAL_CACHE_RUNTIME_MNGMNT)
        #ifdef MCL_SYNCRONIZE_CACHE
        #if (STD_ON == MCL_SYNCRONIZE_CACHE)
        /* invalidate DCACHE to synchronize data */
        retVal = Mcl_IPW_CacheClear(MCL_LMEM_CACHE_ALL);
        if ((Std_ReturnType)E_NOT_OK == retVal)
        {   /* memory synchronization failed, notify user */
            #if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
            Mcl_IPW_ErrorNotification(0xFFU, MCL_DMA_MEM_SYNC_ERROR);
            #endif
        }
        else
        {
            /* cache memory sync successful */
        }
        #endif
        #endif
        #endif
        #endif
    }
    else
    {
        /* Transfer is not completed */
        bCompleted = (boolean)FALSE;
    }
    /* Return the transfer status */
    return (bCompleted);

}


/*================================================================================================*/
/**
* @brief        Function that indicates if DMA transfer is in execution.
* @details      This function indicates if DMA transfer corresponding to the DMA channel
*               passed as parameter is in execution.
*
* @param[in]      nChannel    - the DMA channel to be checked for transfer in execution.
* @param[out]     bCompleted  - the status of the DMA transfer.
*
* @return boolean
*
*/
FUNC(boolean, MCL_CODE) Mcl_Dma_IsTransferActive( VAR(Mcl_DmaChannelType, AUTOMATIC) nChannel)
{
    VAR(boolean, AUTOMATIC) bActive = (boolean)FALSE;

    /* Check ACTIVE bit from DMA_TCD_CSR */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    if(0UL != DMA_ACTIVE(nChannel))
    {
        /* Transfer is active */
        bActive = (boolean)TRUE;
    }
    else
    {
        /* Transfer is not active */
        bActive = (boolean)FALSE;
    }
    /* Return the transfer status */
    return (bActive);
}


#if (MCL_DMA_NOTIFICATION_SUPPORTED == STD_ON)
/*===============================================================================================*/
/**
* @brief        This function enables the user notifications
* @details      This function
*               - clears Dma interrupt flags
*               - enables selected interrupts
*
* @param[in]    Dma hardware channel number
*
* @param[in]    Notification            notification type to be enabled
*
* @return       void
*
*
*/
FUNC (void, MCL_CODE) Mcl_Dma_EnableNotification( VAR(Mcl_DmaChannelType,AUTOMATIC) nChannel,
                                              VAR(Mcl_DmaTransferNotifType,AUTOMATIC) Notification)
{
    /* Clear Dma interrupt request for the corresponging channel */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLEAR_INT_REQ(nChannel);

    /* Enter exclusive area to protect TCD words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_29();

    if(MCL_DMA_TRANSFER_COMPLETE == Notification)
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        DMA_SET_INT_MAJ((uint32)nChannel);
    }
    else if (MCL_DMA_TRANSFER_HALF_COMPLETE == Notification)
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        DMA_SET_INT_HALF((uint32)nChannel);
    }
    else
    {
        /*Empty else to fix misra*/
    }

    /* Exit exclusive area to protect TCD words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_29();
}

/*===============================================================================================*/
/**
* @brief        This function disables the user notifications
* @details      This function
*               - clears Dma interrupt flags
*               - disables selected interrupts
*
* @param[in]    Dma hardware channel number
*
* @return       void
*
*
*/
FUNC (void, MCL_CODE) Mcl_Dma_DisableNotification( VAR(Mcl_DmaChannelType,AUTOMATIC) nChannel)
{
    /* Clear Dma interrupt request for the corresponging channel */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_6 MISRA 2012 Advisory 13.4*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLEAR_INT_REQ(nChannel);

    /* Enter exclusive area to protect TCD words 2,6,8 */
    SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_28();

    /* Clear the transfer completion inetrrupt flag */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLR_INT_MAJ((uint32)nChannel);

    /* Clear the half transfer completion interrupt flag */
    /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
    /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
    /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
    DMA_CLR_INT_HALF((uint32)nChannel);

    /* Exit exclusive area to protect TCD words 2,6,8 */
    SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_28();
}
#endif /* MCL_DMA_NOTIFICATION_SUPPORTED */

/*================================================================================================*/
/**
* @brief        Function that indicates if an interrupt request was set.
* @details      This function indicates if an interrupt request was set
*               for the corresponding channel.
*
* @param[in]      nChannel    - the DMA channel to be checked for interrupt request.
*
* @return boolean
*
*/
FUNC (boolean, MCL_CODE) Mcl_Dma_GetMultiRegChInfo(VAR(Mcl_DmaChannelType,AUTOMATIC) nChannel, VAR(Mcl_DmaRequestType,AUTOMATIC) request)
{
    VAR(boolean, AUTOMATIC) bChBitSet = (boolean)FALSE;
    VAR(uint8, AUTOMATIC) u8relativeChannelInDmaInstance = (uint8)(nChannel % DMA_CHANNELS_PER_MODULE_U8) ;
    VAR(uint8, AUTOMATIC) u8lastChannelInIntLowRegister = (uint8)(DMA_CHANNELS_PER_MODULE_U8);
    VAR(uint32, AUTOMATIC) u32multiRegisterValue = (uint32)0;

/*Check for DMA V3*/
/* @violates @ref Mcl_DMA_c_REF_9 MISRA 2012 Required 2.1*/
/* @violates @ref Mcl_DMA_c_REF_10 MISRA 2012 Required 14.3*/
if ((DMAV3_INSTANCES_NUMBER_U32 != 0U) && (DMAV3_INSTANCES_NUMBER_U32 > DMA_MOD_IDX_U32((uint32)nChannel)))
{
    if (MCL_DMA_GET_INT == request)
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32multiRegisterValue = REG_READ32(DMAV3_CH_INT_ADDR(nChannel));
        if((uint32)0U != (u32multiRegisterValue & DMAV3_CH_INT_U32))
        {
            /* Interrupt request is set. */
            bChBitSet = (boolean)TRUE;
        }
        else
        {
            /* do nothing */
        }
    }
    else if(MCL_DMA_GET_ERR == request)
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32multiRegisterValue = REG_READ32(DMAV3_CH_ES_ADDR32((uint32)nChannel));
        if((uint32)0U != (u32multiRegisterValue & DMAV3_CH_ES_ERR_U32))
        {
            /* Interrupt request is set. */
            bChBitSet = (boolean)TRUE;
        }
        else
        {
            /* do nothing */
        }
    }
    else
    {
        /* do nothing */
    }
}
else
{
/*Check for DMA V2*/
#if (MCL_DMA_INSTANCE_CHANNELS_NO == 0x40UL)
    u8lastChannelInIntLowRegister = (uint8)(DMA_CHANNELS_PER_MODULE_U8 / 2U);
#endif
    if ((MCL_DMA_GET_INT == request) || (MCL_DMA_GET_ERR == request))
    {
        if((u8lastChannelInIntLowRegister) > (u8relativeChannelInDmaInstance))
        {
            /* find register*/
            if (MCL_DMA_GET_INT == request)
            {
                /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
                /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
                /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
                u32multiRegisterValue = REG_READ32(DMAV2_INTL_ADDR32(DMA_MOD_IDX_U32((uint32)nChannel))) ;

            }
            else /* (MCL_DMA_GET_ERR == request) */
            {
                /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
                /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
                /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
                u32multiRegisterValue = REG_READ32(DMAV2_EERL_ADDR32(DMA_MOD_IDX_U32((uint32)nChannel))) ;
            }


            if (0UL != (u32multiRegisterValue & (uint32)((uint32)1u << u8relativeChannelInDmaInstance)))
            {
                /* Interrupt request is set. */
                bChBitSet = (boolean)TRUE;
            }
            else
            {
                /* do nothing */
            }
        }
        else
        {
            if (MCL_DMA_GET_INT == request)
            {
                /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
                /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
                /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
                u32multiRegisterValue = REG_READ32(DMAV2_INTH_ADDR32(DMA_MOD_IDX_U32((uint32)nChannel)));

            }
            else /*(MCL_DMA_GET_ERR == request)*/
            {
                /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
                /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
                /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/                 
                u32multiRegisterValue = REG_READ32(DMAV2_EERH_ADDR32(DMA_MOD_IDX_U32((uint32)nChannel)));
            }


            if (0UL != (u32multiRegisterValue & (uint32)((uint32)1U << (u8relativeChannelInDmaInstance % (DMA_CHANNELS_PER_MODULE_U8 / 2U)))))
            {
                /* Interrupt request is set. */
                bChBitSet = (boolean)TRUE;
            }
            else
            {
                /* do nothing */
            }
        }
    }
}
    /* Return the interrupt request status */
    return (bChBitSet);
}
#if (MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON)
/*================================================================================================*/
/**
* @brief        Function reports error status in the DMA_ES and DMA_ERR registers.
* @details      Function reports error status in the DMA_ES and DMA_ERR registers
*               for the corresponding dma instance.
*
* @param[in]      nChannel    - the DMA channel to be checked for interrupt request.
*
* @return boolean
*
*/
FUNC (void, MCL_CODE) Mcl_Dma_GetGlobalErrorStatus
(
    VAR(Mcl_DmaInstanceType, AUTOMATIC) dmaInstance,
    P2VAR(Mcl_DmaGlobalErrorStatusType, AUTOMATIC, MCL_APPL_DATA) dmaGlobalErrorStatus
)
{
    VAR(uint32,AUTOMATIC) u32GlobalErrorStatus   = (uint32)MCL_DMA_NO_ERROR;
    VAR(uint32,AUTOMATIC) u32ErrChannel          = (uint32)MCL_DMA_NO_CHANNEL_U16;

    /* get global error status from DMAV3 ES MP register */
    /* @violates @ref Mcl_DMA_c_REF_9 MISRA 2012 Required 2.1*/
    /* @violates @ref Mcl_DMA_c_REF_10 MISRA 2012 Required 14.3*/
    if ((DMAV3_INSTANCES_NUMBER_U32 !=0U) && (DMAV3_INSTANCES_NUMBER_U32 > dmaInstance))
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32GlobalErrorStatus = REG_READ32(DMAV3_ES_ADDR32((uint32)(dmaInstance)));
        u32ErrChannel = (u32GlobalErrorStatus & DMAV3_ES_ERRCHN_U32) >> DMAV3_ES_ERRCHN_SHIFT_RIGTH_U8;
        if (DMA_INSTANCE1 == dmaInstance)
        {
            u32ErrChannel = u32ErrChannel + DMA_CHANNELS_PER_MODULE_U8;
        }
    }
    else
    {
        /* get global error status from DMAV2 ES register */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32GlobalErrorStatus = REG_READ32(DMAV2_ES_ADDR32((uint32)(dmaInstance)));

        /* get erroneous channel specified by DMA_ES register*/
        u32ErrChannel = (u32GlobalErrorStatus & DMAV2_ES_ERRCHN_U32) >> DMAV2_ES_ERRCHN_SHIFT_RIGTH_U8;
#if (DMAV2_INSTANCES_NUMBER_U32 == 0x02U)
        if (DMAV3_INSTANCES_NUMBER_U32 < dmaInstance)
        {
            u32ErrChannel = u32ErrChannel + DMA_CHANNELS_PER_MODULE_U8;
        }
#else
    (void)dmaInstance;
#endif

        u32ErrChannel = u32ErrChannel + MCL_EDMAV3_CHANNELS_NO;
    }
    /* get error information about channel u32ErrChannel from DMA_ERR register */
    dmaGlobalErrorStatus->errorId = Mcl_Dma_GetChannelErrorStatus((Mcl_DmaChannelType)u32ErrChannel);

    /* set erroneous channel */
    if ((MCL_DMA_NO_ERROR == dmaGlobalErrorStatus->errorId) || (MCL_DMA_HW_INCONSISTENCY_ERROR == dmaGlobalErrorStatus->errorId))
    {
        dmaGlobalErrorStatus->erroneousChannel = MCL_DMA_NO_CHANNEL_U16;

    }else
    {
        dmaGlobalErrorStatus->erroneousChannel = (Mcl_DmaErroneousChannelType)u32ErrChannel;
    }
}
#endif

#if ((MCL_DMA_GET_GLOBAL_ERR_STATUS_API == STD_ON) || (MCL_DMA_GET_CH_ERR_STATUS_API == STD_ON))
/*================================================================================================*/
/**
* @brief        Function reports the error status from the DMA_ES and DMA_ERR registers.
* @details      Function reports error status in the DMA_ES and DMA_ERR registers
*               for the corresponding channel.
*
* @param[in]      hwChannel    the DMA hardware channel to be checked for report the status.
*
* @return Mcl_DmaChannelErrorStatusType
*/
/* @violates @ref Mcl_DMA_c_REF_5 MISRA 2012 Advisory 8.7*/
FUNC(Mcl_DmaChannelErrorStatusType, MCL_CODE) Mcl_Dma_GetChannelErrorStatus
(
    VAR(Mcl_DmaChannelType,AUTOMATIC) hwChannel
)
{
    VAR(uint32,AUTOMATIC) u32GlobalErrorStatus               = (uint32)MCL_DMA_NO_ERROR;
    VAR(uint32,AUTOMATIC) u32ErrChannel                      = (uint32)MCL_DMA_NO_CHANNEL_U16;
    VAR(uint8,AUTOMATIC) u8ChannelErrorStatus                = (uint8)MCL_DMA_NO_ERROR;
    VAR(Mcl_DmaChannelErrorStatusType,AUTOMATIC) errorStatus =  MCL_DMA_NO_ERROR;

    /* get global error status from DMAV3 ES MP register */
    /* @violates @ref Mcl_DMA_c_REF_9 MISRA 2012 Required 2.1*/
    /* @violates @ref Mcl_DMA_c_REF_10 MISRA 2012 Required 14.3*/
    if ((DMAV3_INSTANCES_NUMBER_U32 != 0U) && (DMAV3_INSTANCES_NUMBER_U32 > DMA_MOD_IDX_U32((uint32)hwChannel)))
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32GlobalErrorStatus = REG_READ32(DMAV3_ES_ADDR32((DMA_MOD_IDX_U32(hwChannel))));
        u32ErrChannel = (u32GlobalErrorStatus & DMAV3_ES_ERRCHN_U32) >> DMAV3_ES_ERRCHN_SHIFT_RIGTH_U8;
        if (DMA_INSTANCE1 == DMA_MOD_IDX_U32((uint32)hwChannel))
        {
            u32ErrChannel = u32ErrChannel + DMA_CHANNELS_PER_MODULE_U8;
        }
    }
    else
    {
        /* get global error status from DMAV2 ES register */
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
        u32GlobalErrorStatus = REG_READ32(DMAV2_ES_ADDR32((DMA_MOD_IDX_U32(hwChannel))));

        /* get erroneous channel specified by DMA_ES register*/
        u32ErrChannel = (u32GlobalErrorStatus & DMAV2_ES_ERRCHN_U32) >> DMAV2_ES_ERRCHN_SHIFT_RIGTH_U8;

#if (DMAV2_INSTANCES_NUMBER_U32 == 0x02U)      
        if (DMAV3_INSTANCES_NUMBER_U32 < DMA_MOD_IDX_U32((uint32)hwChannel))
        {
            u32ErrChannel = u32ErrChannel + DMA_CHANNELS_PER_MODULE_U8;
        }
#endif
        u32ErrChannel = u32ErrChannel + MCL_EDMAV3_CHANNELS_NO;
    }
    /* get channel error status from DMA_ERR register */
    u8ChannelErrorStatus = (uint8)Mcl_Dma_GetMultiRegChInfo(hwChannel, MCL_DMA_GET_ERR);
    /* report errorstatus */
    if(((((uint32)MCL_DMA_NO_ERROR != u32GlobalErrorStatus) && ((uint32)hwChannel == u32ErrChannel)) && ((uint8)MCL_DMA_NO_ERROR == u8ChannelErrorStatus))||
        ((((uint32)MCL_DMA_NO_ERROR != u32GlobalErrorStatus)&& ((uint32)hwChannel != u32ErrChannel)) && ((uint8)MCL_DMA_NO_ERROR != u8ChannelErrorStatus))||
        (((uint32)MCL_DMA_NO_ERROR == u32GlobalErrorStatus) && ((uint8)MCL_DMA_NO_ERROR != u8ChannelErrorStatus))
        )
    /* registers DMA_ES and DMA_ERR report inconsistent information
     * (DMA_ES reports error for channel hwChannel and DMA_ERR reports no error for hwChannel) or
     * (DMA_ES reports error for another channel and DMA_ERR reports error for hwChannel) or
     * (DMA_ES reports reports no error and DMA_ERR reports error for hwChannel)*/
    {
        errorStatus = MCL_DMA_HW_INCONSISTENCY_ERROR;
    }
    else if ((uint8)MCL_DMA_NO_ERROR == u8ChannelErrorStatus)
    {
         errorStatus = MCL_DMA_NO_ERROR;
    }
    #if (MCL_DMA_ECC_REPORTING_ENABLED == STD_ON)
    else if ((uint32)0U != (u32GlobalErrorStatus & DMA_ES_UCE_U32))
    {
        errorStatus = MCL_DMA_ECC_ERROR;
    }
    #endif
    else if ((uint32)0U != (u32GlobalErrorStatus & DMA_ES_BUS_U32))
    {
        errorStatus = MCL_DMA_BUS_ERROR;
    }
    else if ((uint32)0U != (u32GlobalErrorStatus & DMA_ES_DESCRIPTOR_U32))
    {
        errorStatus = MCL_DMA_DESCRIPTOR_ERROR;
    }
    else if ((uint32)0U != (u32GlobalErrorStatus & (DMAV2_ES_GPE_U32 | DMAV2_ES_CPE_U32)))
    {
        errorStatus = MCL_DMA_PRIORITY_ERROR;
    }
    else
    {
        errorStatus = MCL_DMA_UNRECOGNIZED_ERROR;
    }
#if (MCL_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
    /* Dem reporting section */
    if((uint32)STD_ON == Mcl_pDemCfgPtr->Mcl_E_Dma_Inconsistency.state)
    {
        if(MCL_DMA_HW_INCONSISTENCY_ERROR == errorStatus)
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Inconsistency.id, DEM_EVENT_STATUS_FAILED);
        }
        else
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Inconsistency.id, DEM_EVENT_STATUS_PASSED);
        }
    }
    else
    {
        /*do nothing*/
    }

#if (MCL_DMA_ECC_REPORTING_ENABLED == STD_ON)
    if((uint32)STD_ON == Mcl_pDemCfgPtr->Mcl_E_Dma_Ecc.state)
    {
        if((uint32)0U != (u32GlobalErrorStatus & DMA_ES_UCE_U32))
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Ecc.id, DEM_EVENT_STATUS_FAILED);
        }
        else
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Ecc.id, DEM_EVENT_STATUS_PASSED);
        }
    }
    else
    {
        /*do nothing*/
    }
#endif
    if((uint32)STD_ON == Mcl_pDemCfgPtr->Mcl_E_Dma_Bus.state)
    {
        if ((uint32)0U != (u32GlobalErrorStatus & DMA_ES_BUS_U32))
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Bus.id, DEM_EVENT_STATUS_FAILED);
        }

        else
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Bus.id, DEM_EVENT_STATUS_PASSED);
        }
    }
    else
    {
        /*do nothing*/
    }

    if((uint32)STD_ON == Mcl_pDemCfgPtr->Mcl_E_Dma_Descriptor.state)
    {
        if ((uint32)0U != (u32GlobalErrorStatus & DMA_ES_DESCRIPTOR_U32))
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Descriptor.id, DEM_EVENT_STATUS_FAILED);
        }
        else
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Descriptor.id, DEM_EVENT_STATUS_PASSED);
        }
    }
    else
    {
        /*do nothing*/
    }

    if((uint32)STD_ON == Mcl_pDemCfgPtr->Mcl_E_Dma_Priority.state)
    {
        if ((uint32)0U != (u32GlobalErrorStatus & (DMAV2_ES_GPE_U32 | DMAV2_ES_CPE_U32)))
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Priority.id, DEM_EVENT_STATUS_FAILED);
        }
        else
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Priority.id, DEM_EVENT_STATUS_PASSED);
        }
    }
    else
    {
        /*do nothing*/
    }
    if((uint32)STD_ON == Mcl_pDemCfgPtr->Mcl_E_Dma_Unrecognized.state)
    {
        if (errorStatus == MCL_DMA_UNRECOGNIZED_ERROR)
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Unrecognized.id, DEM_EVENT_STATUS_FAILED);
        }
        else if (errorStatus == MCL_DMA_NO_ERROR)
        {
            (void)Dem_SetEventStatus((Dem_EventIdType)Mcl_pDemCfgPtr->Mcl_E_Dma_Unrecognized.id, DEM_EVENT_STATUS_PASSED);
        }
        else
        {
            /*do nothing*/
        }
    }
    else
    {
        /*do nothing*/
    }

#endif
    return errorStatus;
}
#endif

#if (MCL_DMA_ERROR_INTERRUPTS_USED == STD_ON)
FUNC (Mcl_DmaChannelType, MCL_CODE) Mcl_Dma_GetNumChannelError(Mcl_DmaInstanceType dma_instance)
{
    /* @brief variable store error channel */
    VAR(uint8,AUTOMATIC) u8ErrChannel = 0xFFU;
    /* @violates @ref Mcl_DMA_c_REF_9 MISRA 2012 Required 2.1*/
    /* @violates @ref Mcl_DMA_c_REF_10 MISRA 2012 Required 14.3*/
    if ((DMAV3_INSTANCES_NUMBER_U32 != 0U) && (DMAV3_INSTANCES_NUMBER_U32 > dma_instance))
    {
        if (DMA_INSTANCE0 == dma_instance)
        {
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            u8ErrChannel = (uint8)((REG_READ32(DMAV3_ES_ADDR32((uint32)(dma_instance))) & DMAV3_ES_ERRCHN_U32) >> DMAV3_ES_ERRCHN_SHIFT_RIGTH_U8);
        }
        else if(DMA_INSTANCE1 == dma_instance)
        {
            /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
            /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
            /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
            u8ErrChannel = (uint8)((REG_READ32(DMAV3_ES_ADDR32((uint32)(dma_instance))) & DMAV3_ES_ERRCHN_U32) >> DMAV3_ES_ERRCHN_SHIFT_RIGTH_U8) + DMA_CHANNELS_PER_MODULE_U8;
        }
        else
        {
            /*do nothing*/
        }
    }
#if (MCL_DMA_V2_INSTANCE_AVAILABLE == STD_ON)
    else if(DMAV3_INSTANCES_NUMBER_U32 == dma_instance)
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
         u8ErrChannel = (uint8)((REG_READ32(DMAV2_ES_ADDR32(dma_instance)) & DMAV2_ES_ERRCHN_U32) >> DMAV2_ES_ERRCHN_SHIFT_RIGTH_U8) + MCL_EDMAV3_CHANNELS_NO;
    }
    else
    {
        /* @violates @ref Mcl_DMA_c_REF_2 MISRA 2012 Advisory 11.4*/
        /* @violates @ref Mcl_DMA_c_REF_3 MISRA 2012 Required 11.6*/
        /* @violates @ref Mcl_DMA_c_REF_7 MISRA 2012 Required 10.8*/
         u8ErrChannel = (uint8)((REG_READ32(DMAV2_ES_ADDR32(dma_instance)) & DMAV2_ES_ERRCHN_U32) >> DMAV2_ES_ERRCHN_SHIFT_RIGTH_U8) + MCL_EDMAV3_CHANNELS_NO + MCL_DMAV2_INSTANCE_CHANNELS_NO;
    }
#else
    else
    {
        /*do nothing*/
    }
#endif
    return u8ErrChannel;
}
#endif
#if (MCL_LOGICAL_ADDRESS_USED == STD_ON)
FUNC(uint32, MCL_CODE) Mcl_GetPhysicalAddress(VAR(uint32, AUTOMATIC) logicalAddr)
{
    VAR(uint32, AUTOMATIC) phyisicalAddr= logicalAddr;
    VAR(uint16, AUTOMATIC) i;

    for(i=0;i<Mcl_Dma_pLogicalMemoryConfig->NumOfSection;i++)
    {
        if((logicalAddr >= (*(Mcl_Dma_pLogicalMemoryConfig->pSectionConfig))[i].MclLogicalAddrStart) &&
           (logicalAddr < (*(Mcl_Dma_pLogicalMemoryConfig->pSectionConfig))[i].MclLogicalAddrEnd)
        )
        {
            phyisicalAddr = (logicalAddr - (*(Mcl_Dma_pLogicalMemoryConfig->pSectionConfig))[i].MclLogicalAddrStart) + (*(Mcl_Dma_pLogicalMemoryConfig->pSectionConfig))[i].MclPhysicalAddrStart;
        }
    }
    return phyisicalAddr;
}

#endif /*MCL_LOGICAL_ADDRESS_USED == STD_ON*/

#define MCL_STOP_SEC_CODE
/* @violates @ref Mcl_Dma_c_REF_1 MISRA 2012 Required 4.10*/
/* @violates @ref Mcl_DMA_c_REF_4 MISRA 2012 Advisory 20.1*/
#include "Mcl_MemMap.h"

#endif
#endif

#ifdef __cplusplus
}
#endif

/** @} */

