/**
*   @file    Gpt_Pit.c
*   @version 1.0.0
*
*   @brief   AUTOSAR Gpt - PIT driver source file.
*   @details Detailed file description (can be multiple lines).
*
*   @addtogroup GPT_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.3 MCAL
*   Platform             : PA
*   Peripheral           : eMios_Stm_Pit
*   Dependencies         : none
*
*   Autosar Version      : 4.3.1
*   Autosar Revision     : ASR_REL_4_3_REV_0001
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC5777C_MCAL_1_0_0_RTM_ASR_REL_4_3_REV_0001_20190315
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2019 NXP
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifdef __cplusplus
extern "C"{
#endif
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.1, External identifiers shall be distinct. 
*     The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.2, Identifiers declared in the same scope and name space
*     shall be distinct.
*     The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.4, Macro identifiers shall be distinct.
*     The used compilers use more than 31 chars for identifiers.
*
* @section [global]
*     Violates MISRA 2012 Required Rule 5.5, Identifiers shall be distinct from macro names.
*     The used compilers use more than 31 chars for identifiers.
*
* @section GPT_PIT_C_REF_1
*     Violates MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent
*     the contents of a header file being included more than once.
*     This violation is not fixed since the inclusion of <MA>_MemMap.h is as per AUTOSAR requirement
*     [SWS_MemMap_00003].
*
* @section GPT_PIT_C_REF_2
*     Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed between pointer to void
*     and an arithmetic type.
*     This macro computes the address of any register by using the hardware offset of the controller.
*     The address calculated as an unsigned INT is passed to a macro for initializing the pointer 
*     with that address
*
* @section GPT_PIT_C_REF_3
*     Violates MISRA 2012 Advisory Rule 8.7, Functions and objects should not be defined with 
*     external linkage if they are referenced in only one translation unit.
*
* @section GPT_PIT_C_REF_4
*     Violates MISRA 2012 Advisory Rule 20.1, #include directives should only be preceded by
*     preprocessor directives or comments.
*     <MA>_MemMap.h is included after each section define in order to set the current memory section
*     as defined by AUTOSAR
*
* @section GPT_PIT_C_REF_5
*     Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed between a pointer
*     to object and an integer type.
*     The cast is used to access memory mapped registers.
*
* @section GPT_PIT_C_REF_6
*     Violates MISRA 2012 Required Rule 10.8, The value of a composite expression shall not be cast
*     to a different essential type or a wider essential type.
*     The cast is used to access memory mapped registers.
*
* @section GPT_PIT_C_REF_7
*     Violates MISRA 2012 Required Rule 14.4, The controlling expression of an if statement and 
*     the controlling expression of an iteration-statement shall have essentially Boolean type.
*     Multi-statement macros shall be wrapped in a do–while loop, so the macro can appear safely inside if 
*     clauses or other places that expect a single statement or a statement block
*
*/
/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Std_Types.h"
#include "Gpt_Ipw_Irq.h"
#include "Gpt_Pit.h"
#include "Reg_eSys_Pit.h"
#include "SchM_Gpt.h"

#ifdef GPT_ENABLE_USER_MODE_SUPPORT
   #define USER_MODE_REG_PROT_ENABLED   GPT_ENABLE_USER_MODE_SUPPORT
   #include "RegLockMacros.h"
#endif

#include "SilRegMacros.h"

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/

#define GPT_PIT_VENDOR_ID_C                    43

#define GPT_PIT_AR_RELEASE_MAJOR_VERSION_C     4

#define GPT_PIT_AR_RELEASE_MINOR_VERSION_C     3

#define GPT_PIT_AR_RELEASE_REVISION_VERSION_C  1
#define GPT_PIT_SW_MAJOR_VERSION_C             1
#define GPT_PIT_SW_MINOR_VERSION_C             0
#define GPT_PIT_SW_PATCH_VERSION_C             0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/
#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
     /* Check if header file and Std_Types.h file are of the same Autosar version */
    #if ((GPT_PIT_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \
         (GPT_PIT_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION) \
        )
        #error "AutoSar Version Numbers of Gpt_Pit.c and Std_Types.h are different"
    #endif
#endif

#if ( GPT_PIT_VENDOR_ID_C!= GPT_IPW_IRQ_VENDOR_ID)
    #error "Gpt_Pit.c and Gpt_Ipw_Irq.h have different vendor ids"
#endif

/* Check if source file and Gpt header file are of the same Autosar version */
#if ((GPT_PIT_AR_RELEASE_MAJOR_VERSION_C != GPT_IPW_IRQ_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_PIT_AR_RELEASE_MINOR_VERSION_C != GPT_IPW_IRQ_AR_RELEASE_MINOR_VERSION) || \
     (GPT_PIT_AR_RELEASE_REVISION_VERSION_C != GPT_IPW_IRQ_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Pit.c and Gpt_Ipw_Irq.h are different"
#endif

/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_PIT_SW_MAJOR_VERSION_C != GPT_IPW_IRQ_SW_MAJOR_VERSION) || \
     (GPT_PIT_SW_MINOR_VERSION_C != GPT_IPW_IRQ_SW_MINOR_VERSION) || \
     (GPT_PIT_SW_PATCH_VERSION_C != GPT_IPW_IRQ_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Pit.c and Gpt_Ipw_Irq.h are different"
#endif

#if (GPT_PIT_VENDOR_ID_C!= GPT_PIT_VENDOR_ID)
    #error "Gpt_Pit.c and Gpt_Pit.h have different vendor ids"
#endif

/* Check if source file and Gpt header file are of the same Autosar version */
#if ((GPT_PIT_AR_RELEASE_MAJOR_VERSION_C != GPT_PIT_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_PIT_AR_RELEASE_MINOR_VERSION_C != GPT_PIT_AR_RELEASE_MINOR_VERSION) || \
     (GPT_PIT_AR_RELEASE_REVISION_VERSION_C != GPT_PIT_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Pit.c and Gpt_Pit.h are different"
#endif

/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_PIT_SW_MAJOR_VERSION_C != GPT_PIT_SW_MAJOR_VERSION) || \
     (GPT_PIT_SW_MINOR_VERSION_C != GPT_PIT_SW_MINOR_VERSION) || \
     (GPT_PIT_SW_PATCH_VERSION_C != GPT_PIT_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Pit.c and Gpt_Pit.h are different"
#endif

#if ( GPT_PIT_VENDOR_ID_C!= REG_ESYS_PIT_VENDOR_ID)
    #error "Gpt_Pit.c and Reg_eSys_Pit.h have different vendor ids"
#endif

/* Check if source file and Gpt header file are of the same Autosar version */
#if ((GPT_PIT_AR_RELEASE_MAJOR_VERSION_C != REG_ESYS_PIT_AR_RELEASE_MAJOR_VERSION) || \
     (GPT_PIT_AR_RELEASE_MINOR_VERSION_C != REG_ESYS_PIT_AR_RELEASE_MINOR_VERSION) || \
     (GPT_PIT_AR_RELEASE_REVISION_VERSION_C != REG_ESYS_PIT_AR_RELEASE_REVISION_VERSION) \
    )
    #error "AutoSar Version Numbers of Gpt_Pit.c and Reg_eSys_Pit.h are different"
#endif

/* Check if source file and GPT header file are of the same Software version */
#if ((GPT_PIT_SW_MAJOR_VERSION_C != REG_ESYS_PIT_SW_MAJOR_VERSION) || \
     (GPT_PIT_SW_MINOR_VERSION_C != REG_ESYS_PIT_SW_MINOR_VERSION) || \
     (GPT_PIT_SW_PATCH_VERSION_C != REG_ESYS_PIT_SW_PATCH_VERSION) \
    )
    #error "Software Version Numbers of Gpt_Pit.c and Reg_eSys_Pit.h are different"
#endif

#ifdef GPT_ENABLE_USER_MODE_SUPPORT
    #if (GPT_PIT_VENDOR_ID_C != REGLOCKMACROS_VENDOR_ID)
    #error "Gpt_Pit.c and RegLockMacros.h have different vendor ids"
    #endif
#else
    #if (GPT_PIT_VENDOR_ID_C != SILREGMACROS_VENDOR_ID)
    #error "Gpt_Pit.c and SilRegMacros.h have different vendor ids"
    #endif
#endif

#ifdef GPT_ENABLE_USER_MODE_SUPPORT
/* Check if the files source file and RegLockMacros.h are of the same version */
    #if ((GPT_PIT_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
         (GPT_PIT_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION)    \
        )
        #error "AutoSar Version Numbers of Gpt_Pit.c and RegLockMacros.h are different"
    #endif
#else
/* Check if source file and SilRegMacros.h are of the same Autosar version */
    #if ((GPT_PIT_AR_RELEASE_MAJOR_VERSION_C    != SILREGMACROS_AR_RELEASE_MAJOR_VERSION) || \
        (GPT_PIT_AR_RELEASE_MINOR_VERSION_C    != SILREGMACROS_AR_RELEASE_MINOR_VERSION) || \
        (GPT_PIT_AR_RELEASE_REVISION_VERSION_C != SILREGMACROS_AR_RELEASE_REVISION_VERSION) \
        )
    #error "AutoSar Version Numbers of Gpt_Pit.c and SilRegMacros.h are different"
    #endif
#endif

#ifdef GPT_ENABLE_USER_MODE_SUPPORT
    /* Check if source file and RegLockMacros.h are of the same software version */
    #if ((GPT_PIT_SW_MAJOR_VERSION_C != REGLOCKMACROS_SW_MAJOR_VERSION) || \
        (GPT_PIT_SW_MINOR_VERSION_C != REGLOCKMACROS_SW_MINOR_VERSION) || \
        (GPT_PIT_SW_PATCH_VERSION_C != REGLOCKMACROS_SW_PATCH_VERSION) \
        )
    #error "Software Version Numbers of Gpt_Pit.c and SilRegMacros.h are different"
    #endif
#else   
    /* Check if source file and SilRegMacros.h are of the same software version */
    #if ((GPT_PIT_SW_MAJOR_VERSION_C != SILREGMACROS_SW_MAJOR_VERSION) || \
        (GPT_PIT_SW_MINOR_VERSION_C != SILREGMACROS_SW_MINOR_VERSION) || \
        (GPT_PIT_SW_PATCH_VERSION_C != SILREGMACROS_SW_PATCH_VERSION) \
        )
    #error "Software Version Numbers of Gpt_Pit.c and SilRegMacros.h are different"
    #endif
#endif

/*==================================================================================================
*                         LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/
/*=================================================================================================
*                                       LOCAL MACROS
=================================================================================================*/
/*==================================================================================================
*                                      LOCAL CONSTANTS
==================================================================================================*/
#if (GPT_PIT_USED == STD_ON)
/**
* @brief Number of timers for each PIT module
*/

#define GPT_START_SEC_CONST_32
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/**
* @brief base address array for PIT
*/
/** @violates @ref GPT_PIT_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
*   of the driver. External linkage is needed to "export" the API.*/
CONST(uint32, GPT_CONST) PIT_BASE_ADDR32[PIT_MODULE_NUM_MAX_U8] = 
{
#ifdef PIT_0_BASEADDR
    PIT_0_BASEADDR
#else
    (uint32)(0x00000000UL)
#endif
#ifdef PIT_1_BASEADDR
    ,PIT_1_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef PIT_2_BASEADDR
    ,PIT_2_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif
#ifdef PIT_3_BASEADDR
    ,PIT_3_BASEADDR
#else
    ,(uint32)(0x00000000UL)
#endif

};

#define GPT_STOP_SEC_CONST_32
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/*==================================================================================================
*                                      LOCAL VARIABLES
==================================================================================================*/
#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)

#define GPT_START_SEC_VAR_INIT_32
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/**
* @brief          Local variable used to store the previous target time value after call 
*                 Gpt_ChangeNextTimeout.
*/
static VAR(uint32, AUTOMATIC) Gpt_Pit_u32OldTargetValue = 0U;

#define GPT_STOP_SEC_VAR_INIT_32
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#define GPT_START_SEC_VAR_NO_INIT_BOOLEAN
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

/**
* @brief          Local variable used to check that whether this channel called Gpt_ChangeNextTimeout.
*/
static VAR(boolean, AUTOMATIC) Gpt_Pit_bIsChangedTimeout;


#define GPT_STOP_SEC_VAR_NO_INIT_BOOLEAN
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#endif /* (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON) */

/*==================================================================================================
*                                      GLOBAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
*                                      GLOBAL VARIABLES
==================================================================================================*/

/*==================================================================================================
*                                  LOCAL FUNCTION PROTOTYPES
==================================================================================================*/

#define GPT_START_SEC_CODE
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#if (GPT_PIT_MODULE_SINGLE_INTERRUPT == STD_ON)
#ifdef GPT_PIT_0_ISR_USED
ISR(Gpt_PIT_0_ISR);
#endif
#ifdef GPT_PIT_1_ISR_USED
ISR(Gpt_PIT_1_ISR);
#endif
#ifdef GPT_PIT_2_ISR_USED
ISR(Gpt_PIT_2_ISR);
#endif
#ifdef GPT_PIT_3_ISR_USED
ISR(Gpt_PIT_3_ISR);
#endif

#else

#ifdef GPT_PIT_0_CH_RTI_ISR_USED
ISR(Gpt_PIT_0_TIMER_RTI_ISR);
#endif

#ifdef GPT_PIT_0_CH_0_ISR_USED
ISR(Gpt_PIT_0_TIMER_0_ISR);
#endif

#ifdef GPT_PIT_0_CH_1_ISR_USED
ISR(Gpt_PIT_0_TIMER_1_ISR);
#endif

#ifdef GPT_PIT_0_CH_2_ISR_USED
ISR(Gpt_PIT_0_TIMER_2_ISR);
#endif

#ifdef GPT_PIT_0_CH_3_ISR_USED
ISR(Gpt_PIT_0_TIMER_3_ISR);
#endif

#ifdef GPT_PIT_0_CH_4_ISR_USED
ISR(Gpt_PIT_0_TIMER_4_ISR);
#endif

#ifdef GPT_PIT_0_CH_5_ISR_USED
ISR(Gpt_PIT_0_TIMER_5_ISR);
#endif

#ifdef GPT_PIT_0_CH_6_ISR_USED
ISR(Gpt_PIT_0_TIMER_6_ISR);
#endif

#ifdef GPT_PIT_0_CH_7_ISR_USED
ISR(Gpt_PIT_0_TIMER_7_ISR);
#endif

#ifdef GPT_PIT_0_CH_8_ISR_USED
ISR(Gpt_PIT_0_TIMER_8_ISR);
#endif

#ifdef GPT_PIT_0_CH_9_ISR_USED
ISR(Gpt_PIT_0_TIMER_9_ISR);
#endif

#ifdef GPT_PIT_0_CH_10_ISR_USED
ISR(Gpt_PIT_0_TIMER_10_ISR);
#endif

#ifdef GPT_PIT_0_CH_11_ISR_USED
ISR(Gpt_PIT_0_TIMER_11_ISR);
#endif

#ifdef GPT_PIT_0_CH_12_ISR_USED
ISR(Gpt_PIT_0_TIMER_12_ISR);
#endif

#ifdef GPT_PIT_0_CH_13_ISR_USED
ISR(Gpt_PIT_0_TIMER_13_ISR);
#endif

#ifdef GPT_PIT_0_CH_14_ISR_USED
ISR(Gpt_PIT_0_TIMER_14_ISR);
#endif

#ifdef GPT_PIT_0_CH_15_ISR_USED
ISR(Gpt_PIT_0_TIMER_15_ISR);
#endif

#ifdef GPT_PIT_1_CH_RTI_ISR_USED
ISR(Gpt_PIT_1_TIMER_RTI_ISR);
#endif

#ifdef GPT_PIT_1_CH_0_ISR_USED
ISR(Gpt_PIT_1_TIMER_0_ISR);
#endif

#ifdef GPT_PIT_1_CH_1_ISR_USED
ISR(Gpt_PIT_1_TIMER_1_ISR);
#endif

#ifdef GPT_PIT_1_CH_2_ISR_USED
ISR(Gpt_PIT_1_TIMER_2_ISR);
#endif

#ifdef GPT_PIT_1_CH_3_ISR_USED
ISR(Gpt_PIT_1_TIMER_3_ISR);
#endif

#ifdef GPT_PIT_1_CH_4_ISR_USED
ISR(Gpt_PIT_1_TIMER_4_ISR);
#endif

#ifdef GPT_PIT_1_CH_5_ISR_USED
ISR(Gpt_PIT_1_TIMER_5_ISR);
#endif

#ifdef GPT_PIT_1_CH_6_ISR_USED
ISR(Gpt_PIT_1_TIMER_6_ISR);
#endif

#ifdef GPT_PIT_1_CH_7_ISR_USED
ISR(Gpt_PIT_1_TIMER_7_ISR);
#endif

#ifdef GPT_PIT_1_CH_8_ISR_USED
ISR(Gpt_PIT_1_TIMER_8_ISR);
#endif

#ifdef GPT_PIT_1_CH_9_ISR_USED
ISR(Gpt_PIT_1_TIMER_9_ISR);
#endif

#ifdef GPT_PIT_1_CH_10_ISR_USED
ISR(Gpt_PIT_1_TIMER_10_ISR);
#endif

#ifdef GPT_PIT_1_CH_11_ISR_USED
ISR(Gpt_PIT_1_TIMER_11_ISR);
#endif

#ifdef GPT_PIT_1_CH_12_ISR_USED
ISR(Gpt_PIT_1_TIMER_12_ISR);
#endif

#ifdef GPT_PIT_1_CH_13_ISR_USED
ISR(Gpt_PIT_1_TIMER_13_ISR);
#endif

#ifdef GPT_PIT_1_CH_14_ISR_USED
ISR(Gpt_PIT_1_TIMER_14_ISR);
#endif

#ifdef GPT_PIT_1_CH_15_ISR_USED
ISR(Gpt_PIT_1_TIMER_15_ISR);
#endif


#ifdef GPT_PIT_2_CH_RTI_ISR_USED
ISR(Gpt_PIT_2_TIMER_RTI_ISR);
#endif

#ifdef GPT_PIT_2_CH_0_ISR_USED
ISR(Gpt_PIT_2_TIMER_0_ISR);
#endif

#ifdef GPT_PIT_2_CH_1_ISR_USED
ISR(Gpt_PIT_2_TIMER_1_ISR);
#endif

#ifdef GPT_PIT_2_CH_2_ISR_USED
ISR(Gpt_PIT_2_TIMER_2_ISR);
#endif
#ifdef GPT_PIT_2_CH_3_ISR_USED
ISR(Gpt_PIT_2_TIMER_3_ISR);
#endif


#ifdef GPT_PIT_3_CH_RTI_ISR_USED
ISR(Gpt_PIT_3_TIMER_RTI_ISR);
#endif

#ifdef GPT_PIT_3_CH_0_ISR_USED
ISR(Gpt_PIT_3_TIMER_0_ISR);
#endif

#ifdef GPT_PIT_3_CH_1_ISR_USED
ISR(Gpt_PIT_3_TIMER_1_ISR);
#endif

#ifdef GPT_PIT_3_CH_2_ISR_USED
ISR(Gpt_PIT_3_TIMER_2_ISR);
#endif

#ifdef GPT_PIT_3_CH_3_ISR_USED
ISR(Gpt_PIT_3_TIMER_3_ISR);
#endif





#endif /*GPT_PIT_MODULE_SINGLE_INTERRUPT == STD_ON*/

#if ((defined GPT_PIT_0_ISR_USED      ) ||(defined GPT_PIT_1_ISR_USED      )||(defined GPT_PIT_2_ISR_USED      )||(defined GPT_PIT_3_ISR_USED      )|| \
     (defined GPT_PIT_0_CH_RTI_ISR_USED)||(defined GPT_PIT_0_CH_0_ISR_USED )||(defined GPT_PIT_0_CH_1_ISR_USED )||(defined GPT_PIT_0_CH_2_ISR_USED )|| \
     (defined GPT_PIT_0_CH_3_ISR_USED  )||(defined GPT_PIT_0_CH_4_ISR_USED )||(defined GPT_PIT_0_CH_5_ISR_USED )||(defined GPT_PIT_0_CH_6_ISR_USED )|| \
     (defined GPT_PIT_0_CH_7_ISR_USED  )||(defined GPT_PIT_0_CH_8_ISR_USED )||(defined GPT_PIT_0_CH_9_ISR_USED )||(defined GPT_PIT_0_CH_10_ISR_USED)|| \
     (defined GPT_PIT_0_CH_11_ISR_USED )||(defined GPT_PIT_0_CH_12_ISR_USED)||(defined GPT_PIT_0_CH_13_ISR_USED)||(defined GPT_PIT_0_CH_14_ISR_USED)|| \
     (defined GPT_PIT_0_CH_15_ISR_USED )||(defined GPT_PIT_1_CH_0_ISR_USED )||(defined GPT_PIT_1_CH_1_ISR_USED )||(defined GPT_PIT_1_CH_2_ISR_USED )|| \
     (defined GPT_PIT_1_CH_3_ISR_USED  )||(defined GPT_PIT_1_CH_4_ISR_USED )||(defined GPT_PIT_1_CH_5_ISR_USED )||(defined GPT_PIT_1_CH_6_ISR_USED )|| \
     (defined GPT_PIT_1_CH_7_ISR_USED  )||(defined GPT_PIT_1_CH_8_ISR_USED )||(defined GPT_PIT_1_CH_9_ISR_USED )||(defined GPT_PIT_1_CH_10_ISR_USED)|| \
     (defined GPT_PIT_1_CH_11_ISR_USED )||(defined GPT_PIT_1_CH_12_ISR_USED)||(defined GPT_PIT_1_CH_13_ISR_USED)||(defined GPT_PIT_1_CH_14_ISR_USED)|| \
     (defined GPT_PIT_1_CH_15_ISR_USED )||(defined GPT_PIT_2_CH_0_ISR_USED )||(defined GPT_PIT_2_CH_1_ISR_USED )||(defined GPT_PIT_2_CH_2_ISR_USED )|| \
     (defined GPT_PIT_2_CH_3_ISR_USED  )||(defined GPT_PIT_3_CH_0_ISR_USED )||(defined GPT_PIT_3_CH_1_ISR_USED )||(defined GPT_PIT_3_CH_2_ISR_USED )||\
     (defined GPT_PIT_3_CH_3_ISR_USED)\
    )
static FUNC (void, GPT_CODE) Gpt_Pit_ProcessCommonInterrupt(VAR(uint8, AUTOMATIC) u8HwChannel);
#endif
/*==================================================================================================
*                                      LOCAL FUNCTIONS
==================================================================================================*/
#if ((defined GPT_PIT_0_ISR_USED      ) ||(defined GPT_PIT_1_ISR_USED      )||(defined GPT_PIT_2_ISR_USED      )||(defined GPT_PIT_3_ISR_USED      )|| \
     (defined GPT_PIT_0_CH_RTI_ISR_USED)||(defined GPT_PIT_0_CH_0_ISR_USED )||(defined GPT_PIT_0_CH_1_ISR_USED )||(defined GPT_PIT_0_CH_2_ISR_USED )|| \
     (defined GPT_PIT_0_CH_3_ISR_USED  )||(defined GPT_PIT_0_CH_4_ISR_USED )||(defined GPT_PIT_0_CH_5_ISR_USED )||(defined GPT_PIT_0_CH_6_ISR_USED )|| \
     (defined GPT_PIT_0_CH_7_ISR_USED  )||(defined GPT_PIT_0_CH_8_ISR_USED )||(defined GPT_PIT_0_CH_9_ISR_USED )||(defined GPT_PIT_0_CH_10_ISR_USED)|| \
     (defined GPT_PIT_0_CH_11_ISR_USED )||(defined GPT_PIT_0_CH_12_ISR_USED)||(defined GPT_PIT_0_CH_13_ISR_USED)||(defined GPT_PIT_0_CH_14_ISR_USED)|| \
     (defined GPT_PIT_0_CH_15_ISR_USED )||(defined GPT_PIT_1_CH_0_ISR_USED )||(defined GPT_PIT_1_CH_1_ISR_USED )||(defined GPT_PIT_1_CH_2_ISR_USED )|| \
     (defined GPT_PIT_1_CH_3_ISR_USED  )||(defined GPT_PIT_1_CH_4_ISR_USED )||(defined GPT_PIT_1_CH_5_ISR_USED )||(defined GPT_PIT_1_CH_6_ISR_USED )|| \
     (defined GPT_PIT_1_CH_7_ISR_USED  )||(defined GPT_PIT_1_CH_8_ISR_USED )||(defined GPT_PIT_1_CH_9_ISR_USED )||(defined GPT_PIT_1_CH_10_ISR_USED)|| \
     (defined GPT_PIT_1_CH_11_ISR_USED )||(defined GPT_PIT_1_CH_12_ISR_USED)||(defined GPT_PIT_1_CH_13_ISR_USED)||(defined GPT_PIT_1_CH_14_ISR_USED)|| \
     (defined GPT_PIT_1_CH_15_ISR_USED )||(defined GPT_PIT_2_CH_0_ISR_USED )||(defined GPT_PIT_2_CH_1_ISR_USED )||(defined GPT_PIT_2_CH_2_ISR_USED )|| \
     (defined GPT_PIT_2_CH_3_ISR_USED  )||(defined GPT_PIT_3_CH_0_ISR_USED )||(defined GPT_PIT_3_CH_1_ISR_USED )||(defined GPT_PIT_3_CH_2_ISR_USED )||\
     (defined GPT_PIT_3_CH_3_ISR_USED)\
    )
/**
* @brief   Driver routine to process all the interrupts of PIT.
* @details Support function used by interrupt service routines to implement PIT specific operations
*          and call the GPT upper layer handler to implement non-hardware specific operations.
*
* @param[in]     u8ModuleIdx      hardware module index
* @param[in]     u8ChannelIdx     hardware channel index
*
* @implements   Gpt_Pit_ProcessCommonInterrupt_Activity
*/
static FUNC(void, GPT_CODE) Gpt_Pit_ProcessCommonInterrupt(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(uint32,AUTOMATIC) u32Temp1;
    VAR(uint32,AUTOMATIC) u32Temp2;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    /*Checks for spurious interrupts*/
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32Temp1 = REG_BIT_GET32(PIT_TFLG_ADDR32(u8ModuleIdx,u8ChannelIdx),PIT_TFLG_TIF_MASK_U32);
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/    
    u32Temp2 = REG_BIT_GET32(PIT_TCTRL_ADDR32(u8ModuleIdx,u8ChannelIdx), PIT_TCTRL_TIE_MASK_U32);

    if ((PIT_TFLG_TIF_ON_U32 == u32Temp1) && (((uint32)PIT_TCTRL_TIE_ON_U32 << PIT_TCTRL_TIE_SHIFT) == u32Temp2))
    {
#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
        Gpt_Pit_bIsChangedTimeout = (boolean)FALSE;
#endif
        /* Call GPT upper layer handler */
        Gpt_Ipw_ProcessCommonInterrupt(u8ChannelIdx, (uint8)GPT_PIT_MODULE + (uint8)((uint8)GPT_PIT_CHANNELS_PER_MODULE_U8 * u8ModuleIdx));
    /* (uint8)GptPitChannelsPos[u8ModuleIdx]);*/
    }

    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_06();
    {
        /*Clear interrupt flag*/
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/ 
        REG_BIT_SET32(PIT_TFLG_ADDR32(u8ModuleIdx,u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_06();
}
#endif
/*==================================================================================================
*                                      GLOBAL FUNCTIONS
==================================================================================================*/
/**
* @brief   Gpt driver initialization function for Pit module.
* @details This function is called separately for each PIT hw channel corresponding to the configured
*          timer channels, and:
*          - enables the PIT module
*          - configures the freeze mode (enabled or disabled)
*          - disables the IRQ correpsonding to the PIT channel
*          - clears the (pending) interrupt flag corresponding to Pit channel
*          - disables the PIT timer channel
*          - clears the Load Value register correponding to the Pit channel.
*
*
* @param[in]     u8HwChannel        Pit hw channel ID
* @param[in]     bFreezeEnable     indicates if the Freeze mode is enabled
*
*
*/
FUNC(void, GPT_CODE) Gpt_Pit_Init(VAR(uint8, AUTOMATIC) u8HwChannel, 
                                  #if(GPT_CHAIN_MODE == STD_ON)
                                  VAR(boolean, AUTOMATIC) bChainMode,
                                  #endif
                                  VAR(boolean, AUTOMATIC) bFreezeEnable)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);

    /* Enable hardware module clock. This shall be be executed before any other setup is made */
    if((uint32)0 == (uint32)PIT_CHANNEL_INDEX_U32((uint32)u8ChannelIdx))
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_MDIS_RTI_MASK_U32);
    }
    else
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_MDIS_MASK_U32);
    }

    /* Stop Channel to Configure Channel */
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TEN_MASK_U32);

    /* Disable interrupts*/
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TIE_MASK_U32);

    /* Clear pending interrupts */
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_SET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx,(uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);

    /* Set Compare Value to 0 */
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_WRITE32(PIT_LDVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), 0xFFFFFFFFU);

    /* Check freeze enable */
    if ((boolean)TRUE == bFreezeEnable)
    {
        /* Allow timer to be stopped when the device enters debug mode */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_FRZ_MASK_U32);
    }
    else
    {
        /* Pit counter continues to run in debug mode */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_FRZ_MASK_U32);
    }
 
#if (GPT_CHAIN_MODE == STD_ON)
    /* Check chain mode */
    if((boolean)TRUE == bChainMode)
    {
        /* Enable Chain Mode*/
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/        
        REG_BIT_SET32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_CHN_MASK_U32);
    }
    else
    {
        /* Disable Chain Mode */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/        
        REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_CHN_MASK_U32);        
    }
#endif     
    return;
}

/*================================================================================================*/
#if (GPT_DEINIT_API == STD_ON)
/**
* @brief   Gpt driver de-initialization function for Pit module.
* @details This function is called separately for each PIT hw channel corresponding to the configured
*          timer channels, and:
*          - disables the PIT channel
*          - disables the freeze mode
*          - disables IRQ corresponding to Pit channel
*          - clears the (pending) interrupt flag corresponding to Pit channel
*
* @param[in]     u8HwChannel        Pit hw channel ID
*
*
*
*/
FUNC(void, GPT_CODE) Gpt_Pit_DeInit(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    /* Enable hardware module clock. This shall be be executed before any other setup is made */
    if((uint32)0 == (uint32)PIT_CHANNEL_INDEX_U32((uint32)u8ChannelIdx))
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_MDIS_RTI_MASK_U32);
    }
    else
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_MDIS_MASK_U32);
    }

    /* Reset Status and Control Register */
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TEN_MASK_U32);
    
    /* Disable channel interrupts*/
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TIE_MASK_U32);
    
    /* Clear Load Value Register */
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_WRITE32(PIT_LDVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), 0UL);
    
    /* Clear Interrupt Flag */
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_SET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);
    
    /* Pit counter continues to run in debug mode */ 
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_BIT_CLEAR32(PIT_MCR_ADDR32((uint32)u8ModuleIdx), PIT_MCR_FRZ_MASK_U32);
    
    return;
}
#endif

/*================================================================================================*/
/**
* @brief   Gpt driver function for starting the Pit timer channel.
* @details This function:
*          - clears the (pending) interrupt flag corresponding to Pit channel
*          - disables the PIT timer channel
*          - sets the timeout value into the PIT timer channel register
*          - enables the PIT timer channel
*          - enables the IRQ corresponding to the PIT timer channel,if channel configured in One Shot mode.
*
* @param[in]     u8HwChannel       Pit hw channel ID
* @param[in]     u32Value          Channel timeout value
* @param[in]     eChannelMode      One Shot or Continuous
*
*
*/
FUNC(void, GPT_CODE) Gpt_Pit_StartTimer(VAR(uint8, AUTOMATIC) u8HwChannel, VAR(uint32, AUTOMATIC) u32Value)
{
#ifdef GPT_PIT_RTI_USED
#if (GPT_PIT_RTI_USED == STD_ON)
    VAR(uint32, AUTOMATIC) u32Timeout = (uint32)GPT_TIMEOUT_COUNTER;
#endif
#endif
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_07();
    {
        /* Disable pit timer */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TEN_MASK_U32);
        
        /* Write period value to register */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_WRITE32(PIT_LDVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), u32Value);
        
#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
        Gpt_Pit_bIsChangedTimeout = (boolean)FALSE;
#endif 
        
#if (defined (GPT_PIT_RTI_USED) && (GPT_PIT_RTI_USED == STD_ON))
        if(PIT_0_CH_RTI == u8HwChannel)
        {
            /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
            *   of any register by using the hardware offset of the controller.*/
            /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
            *   memory mapped registers.*/
            /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
            *   memory mapped registers.*/
            while ((REG_READ32(PIT_CVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx)) != u32Value) && (u32Timeout > 0UL))
            {
                u32Timeout--;
            }
            if (0UL == u32Timeout)
            {
            #if (GPT_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
                if((uint32)STD_ON == Gpt_E_TimeoutCfg.state)
                {
                    /* Report production error and return from function. */
                    (void)Dem_SetEventStatus((Dem_EventIdType)Gpt_E_TimeoutCfg.id, DEM_EVENT_STATUS_FAILED);
                }
            #endif /* (GPT_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF) */
            }
        }
       
        if (0U != u32Timeout)
        {
#endif 
        
        /*Enable pit timer*/
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TEN_MASK_U32);
        
#if (defined (GPT_PIT_RTI_USED) && (GPT_PIT_RTI_USED == STD_ON))
        }
#endif
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_07();
    
    return;
}

/*================================================================================================*/
/**
* @brief   Gpt driver function for stopping the Pit timer channel.
* @details This function disables the PIT channel
*
* @param[in]     u8HwChannel        Pit hw channel ID
*
*
*/
FUNC(void, GPT_CODE) Gpt_Pit_StopTimer(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);

    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_08();
    {
        /* Disable pit timer */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TEN_MASK_U32);
        
        /* Clear pit interrupt flag */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_08();
    
    return;
}

/*================================================================================================*/

/**
* @brief   Gpt driver function for getting the time elapsed for an Pit timer channel.
* @details This function:
*          - reads the PIT channel load register
*          - reads the PIT counter register
*          - depending on above it calculates and returns the elapsed time
*          - reads and return the interrupt status flag value
*          - reads and return the current target time value
*
* @param[in]     u8HwChannel                Pit hw channel ID
* @param[out]    pbReturnChannelRollover    Interrupt status flag value
* @param[out]    pu32TargetValue            current target time value
*
* @return        Elapsed time since the last roll-over or start time.
*
*/
FUNC(uint32, GPT_CODE) Gpt_Pit_GetTimeElapsed(VAR(uint8, AUTOMATIC) u8HwChannel,
                                              P2VAR(boolean, AUTOMATIC, GPT_APPL_DATA) pbReturnChannelRollover,
                                              P2VAR(uint32, AUTOMATIC, GPT_APPL_DATA) pu32TargetValue
                                             )
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    VAR(uint32, AUTOMATIC)  u32ReturnValue;
    VAR(uint32, AUTOMATIC)  u32Flag;

#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
    if((boolean)TRUE == Gpt_Pit_bIsChangedTimeout) 
    {
        *pu32TargetValue = Gpt_Pit_u32OldTargetValue;
    } 
    else
    {
#endif
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    *pu32TargetValue = REG_READ32(PIT_LDVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx));
#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)   
    }
#endif

    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32ReturnValue = *pu32TargetValue - REG_READ32(PIT_CVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx));
    
    /*Check interrupt status flag*/
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    u32Flag = (uint32)REG_BIT_GET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);
    
    if (u32Flag != 0U)
    {
        /* Channel counter was roll-over */
        *pbReturnChannelRollover = (boolean)TRUE;
    }
    else
    {
        /* Channel counter was not roll-over */
        *pbReturnChannelRollover = (boolean)FALSE;
    }
    
    return u32ReturnValue;
}

/*================================================================================================*/
/**
* @brief   Gpt driver function for enabling the Pit timer channel IRQ.
* @details This function enables the IRQ corresponding to the Pit timer channel
*
* @param[in]     u8HwChannel        Pit hw channel ID
*
*
*/
FUNC(void, GPT_CODE) Gpt_Pit_EnableInterrupt(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_09();
    {
        /* Clear pit interrupt flag */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);
        
        /* Enable pit timer interrupt */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TIE_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_09();
    
    return;
}

/*================================================================================================*/
#if ((GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON) || (GPT_WAKEUP_FUNCTIONALITY_API == STD_ON))
/**
* @brief   Gpt driver function for disabling the Pit timer channel IRQ.
* @details This function disables the IRQ corresponding to the Pit timer channel
*
* @param[in]     u8HwChannel        Pit hw channel ID
*
*
*/
FUNC(void, GPT_CODE) Gpt_Pit_DisableInterrupt(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_10();
    {
        /* Disable pit timer interrupt */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_TIE_MASK_U32);
        
        /* Clear pit interrupt flag */
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        REG_BIT_SET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);
    }
    SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_10();
}
#endif

/*================================================================================================*/
#if (GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
/**
* @brief      The function changes the Pit Timer Load Value Register value.
* @details This function:
*          - sets the next timeout value to PIT_RTI_LDVAL.
*
* @param[in]     u8HwChannel        Pit hw channel ID
* @param[in]     u32Value            channel timeout value
* @implements    Gpt_Pit_ChangeNextTimeoutValue_Activity
*/

FUNC(void, GPT_CODE) Gpt_Pit_ChangeNextTimeoutValue(VAR(uint8, AUTOMATIC) u8HwChannel, VAR(uint32, AUTOMATIC) u32Value)
{
    VAR(uint8, AUTOMATIC) u8ModuleIdx;   /* assigned PIT HW module  index */
    VAR(uint8, AUTOMATIC) u8ChannelIdx;  /* assigned PIT HW channel index */

    u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);

    if((boolean)FALSE == Gpt_Pit_bIsChangedTimeout) 
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        Gpt_Pit_u32OldTargetValue = REG_READ32(PIT_LDVAL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx));
        Gpt_Pit_bIsChangedTimeout = (boolean)TRUE;
    } 
    /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
    *   of any register by using the hardware offset of the controller.*/
    /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
    *   memory mapped registers.*/
    /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
    *   memory mapped registers.*/
    REG_WRITE32(PIT_LDVAL_ADDR32(u8ModuleIdx,u8ChannelIdx), u32Value);

}
#endif /* GPT_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON */
/*================================================================================================*/
#if (GPT_CHAIN_MODE == STD_ON)
FUNC(Std_ReturnType, GPT_CODE) Gpt_Pit_EnableChainMode(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(Std_ReturnType,AUTOMATIC) returnValue = (Std_ReturnType)E_NOT_OK;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);
    
    /* Can not enable chain mode for PIT_RTI and CH_0) */
    if((uint8) 0x01 < u8ChannelIdx)
    {
        /* Enable Chain Mode*/
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/        
        REG_BIT_SET32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_CHN_MASK_U32);
        returnValue = (Std_ReturnType)E_OK;
    }
    
    return returnValue;
}
#endif /*(GPT_CHAIN_MODE == STD_ON)*/  
/*================================================================================================*/
#if (GPT_CHAIN_MODE == STD_ON)
FUNC(Std_ReturnType, GPT_CODE) Gpt_Pit_DisableChainMode(VAR(uint8, AUTOMATIC) u8HwChannel)
{
    VAR(Std_ReturnType,AUTOMATIC) returnValue = (Std_ReturnType)E_NOT_OK;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = (uint8)PIT_MODULE_INDEX_U32(u8HwChannel);
    VAR(uint8, AUTOMATIC) u8ChannelIdx = (uint8)PIT_CHANNEL_INDEX_U32(u8HwChannel);

    /* Can not use chain mode for PIT_RTI and CH_0) */
    if((uint8) 0x01 < u8ChannelIdx)
    {
        /* Disable Chain Mode*/
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/        
        REG_BIT_CLEAR32(PIT_TCTRL_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), (uint32)PIT_TCTRL_CHN_MASK_U32);
        returnValue =(Std_ReturnType)E_OK;
    }
    
    return returnValue;
}
#endif /*(GPT_CHAIN_MODE == STD_ON)*/  
/*================================================================================================*/
#if (GPT_PIT_MODULE_SINGLE_INTERRUPT == STD_ON)
#ifdef GPT_PIT_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT_0 channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0 hw module.
*
* @isr
*/
ISR(Gpt_PIT_0_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp1;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = 0U;

    for (u8ChannelIdx = 0U; u8ChannelIdx < GPT_PIT_0_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp1 = REG_BIT_GET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);

        if (PIT_TFLG_TIF_ON_U32 == u32Temp1)
        {
            Gpt_Pit_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << PIT_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif
#ifdef GPT_PIT_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT_1 channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1 hw module.
*
* @isr
*/
ISR(Gpt_PIT_1_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp1;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = 1U;

    for (u8ChannelIdx = 1U; u8ChannelIdx < GPT_PIT_1_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp1 = REG_BIT_GET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);

        if (PIT_TFLG_TIF_ON_U32 == u32Temp1)
        {
            Gpt_Pit_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << PIT_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif
#ifdef GPT_PIT_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT_2 channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_2 hw module.
*
* @isr
*/
ISR(Gpt_PIT_2_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp1;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = 2U;

    for (u8ChannelIdx = 1U; u8ChannelIdx < GPT_PIT_2_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp1 = REG_BIT_GET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);

        if (PIT_TFLG_TIF_ON_U32 == u32Temp1)
        {
            Gpt_Pit_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << PIT_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif
#ifdef GPT_PIT_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT_3 channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_3 hw module.
*
* @isr
*/
ISR(Gpt_PIT_3_ISR)
{
    VAR(uint32,AUTOMATIC) u32Temp1;
    VAR(uint8, AUTOMATIC) u8ChannelIdx;
    VAR(uint8, AUTOMATIC) u8ModuleIdx  = 3U;

    for (u8ChannelIdx = 1U; u8ChannelIdx < GPT_PIT_3_NUM_CHANNEL_U8; u8ChannelIdx++)
    {
        /** @violates @ref GPT_PIT_C_REF_2 MISRA 2012  Required Rule 11.6, This macro computes the address
        *   of any register by using the hardware offset of the controller.*/
        /** @violates @ref GPT_PIT_C_REF_5 MISRA 2012 Advisory Rule 11.4, The cast is used to access
        *   memory mapped registers.*/
        /** @violates @ref GPT_PIT_C_REF_6 MISRA 2012 Advisory Rule 10.8, The cast is used to access
        *   memory mapped registers.*/
        u32Temp1 = REG_BIT_GET32(PIT_TFLG_ADDR32((uint32)u8ModuleIdx, (uint32)u8ChannelIdx), PIT_TFLG_TIF_MASK_U32);

        if (PIT_TFLG_TIF_ON_U32 == u32Temp1)
        {
            Gpt_Pit_ProcessCommonInterrupt((uint8)((uint8)(u8ModuleIdx << PIT_MOD_SHIFT) + u8ChannelIdx));
        }
    }
    EXIT_INTERRUPT();
}
#endif

#else
#ifdef GPT_PIT_0_CH_RTI_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_RTI hw channel.
*
* @isr
*
* @violates @ref GPT_PIT_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*/
ISR(Gpt_PIT_0_TIMER_RTI_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_RTI);
    
/** @violates @ref GPT_PIT_C_REF_7 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/
    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_0 hw channel.
*
* @isr
*
* @violates @ref GPT_PIT_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*/
ISR(Gpt_PIT_0_TIMER_0_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_0);
    
/** @violates @ref GPT_PIT_C_REF_7 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/
    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_1 hw channel.
*
* @isr
*
* @violates @ref GPT_PIT_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*/
ISR(Gpt_PIT_0_TIMER_1_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_1);
/** @violates @ref GPT_PIT_C_REF_7 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/
    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_2 hw channel.
*
* @isr
*
* @violates @ref GPT_PIT_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*/
ISR(Gpt_PIT_0_TIMER_2_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_2);

/** @violates @ref GPT_PIT_C_REF_7 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/    
    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_3 hw channel.
*
* @isr
*
* @violates @ref GPT_PIT_C_REF_3 MISRA 2012  Advisory Rule 8.7, These functions represent the API 
* of the driver. External linkage is needed to "export" the API.
*/
ISR(Gpt_PIT_0_TIMER_3_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_3);

/** @violates @ref GPT_PIT_C_REF_7 MISRA 2012 Required Rule 14.4, The controlling expression of an if statement
*   and the controlling expression of an iteration-statement shall have essentially Boolean type.*/    
    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_4_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_4 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_4_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_4);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_5_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_5 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_5_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_5);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_6_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_6 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_6_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_6);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_7_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_7 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_7_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_7);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_8_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_8 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_8_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_8);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_9_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_9 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_9_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_9);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_10_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_10 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_10_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_10);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_11_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_11 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_11_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_11);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_12_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_12 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_12_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_12);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_13_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_13 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_13_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_13);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_14_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_14 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_14_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_14);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_0_CH_15_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_0_TIMER_15 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_0_TIMER_15_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_0_CH_15);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_RTI_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_RTI hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_RTI_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_RTI);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_0 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_0_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_0);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_1 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_1_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_1);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_2 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_2_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_2);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_3 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_3_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_3);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_4_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_4 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_4_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_4);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_5_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_5 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_5_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_5);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_6_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_6 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_6_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_6);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_7_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_7 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_7_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_7);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_8_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_8 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_8_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_8);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_9_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_9 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_9_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_9);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_10_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_10 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_10_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_10);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_11_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_11 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_11_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_11);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_12_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_12 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_12_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_12);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_13_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_13 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_13_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_13);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_14_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_14 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_14_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_14);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_1_CH_15_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_15 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_1_TIMER_15_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_1_CH_15);

    EXIT_INTERRUPT();

}
#endif


#ifdef GPT_PIT_2_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_2_TIMER_0 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_2_TIMER_0_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_2_CH_0);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_2_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_2_TIMER_1 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_2_TIMER_1_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_2_CH_1);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_2_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_1_TIMER_2 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_2_TIMER_2_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_2_CH_2);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_2_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_3_TIMER_RTI hw channel.
*
* @isr
*/
ISR(Gpt_PIT_2_TIMER_3_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_2_CH_3);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_3_CH_0_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_3_TIMER_0 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_3_TIMER_0_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_3_CH_0);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_3_CH_1_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_3_TIMER_1 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_3_TIMER_1_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_3_CH_1);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_3_CH_2_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_3_TIMER_2 hw channel.
*
* @isr
*/
ISR(Gpt_PIT_3_TIMER_2_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_3_CH_2);

    EXIT_INTERRUPT();

}
#endif

#ifdef GPT_PIT_3_CH_3_ISR_USED
/*================================================================================================*/
/**
* @brief   Interrupt handler for PIT channels.
* @details Interrupt Service Routine corresponding to Gpt_PIT_3_TIMER_RTI hw channel.
*
* @isr
*/
ISR(Gpt_PIT_3_TIMER_3_ISR)
{
    Gpt_Pit_ProcessCommonInterrupt((uint8)PIT_3_CH_3);

    EXIT_INTERRUPT();

}
#endif

#endif /*GPT_PIT_MODULE_SINGLE_INTERRUPT == STD_ON*/

#define GPT_STOP_SEC_CODE
/** @violates @ref GPT_PIT_C_REF_1 MISRA 2012 Required Directive 4.10, the contents of a header 
*   file being included more than once.*/
/** @violates @ref GPT_PIT_C_REF_4 MISRA 2012 Advisory Rule 20.1, <MA>_MemMap.h is included
*   after each section define in order to set the current memory section as defined by AUTOSAR.*/
#include "Gpt_MemMap.h"

#endif/*GPT_PIT_USED == STD_ON*/

#ifdef __cplusplus
}
#endif

/** @} */
