{"text_format":"1","workbook":"xlsx","n_sheets":5,"sheets":["Release_Notes","Clocks","PLLconfig","Sheet2","Sheet3"],"not_rendered":{"charts":0,"images":2,"macros":1,"external_links":0,"defined_names":89,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900"}

{"sheet":"Release_Notes","index":0,"n_rows":59,"n_cols":9,"rows_kept":59,"cut":false,"hidden":false,"merged":[[35,5,35,6],[35,8,35,9],[40,2,40,3]]}
["*******************************************************************************"]
["NXP Semiconductor Inc."]
["(c) Copyright 2012 NXP Semiconductor, Inc."]
["ALL RIGHTS RESERVED."]
["********************************************************************************"]
["Services performed by NXP in this matter are performed AS IS and without"]
["any warranty. CUSTOMER retains the final decision relative to the total design"]
["and functionality of the end product. NXP neither guarantees nor will be"]
["held liable by CUSTOMER for the success of this project."]
["NXP DISCLAIMS ALL WARRANTIES, EXPRESSED, IMPLIED OR STATUTORY INCLUDING,"]
["BUT NOT LIMITED TO, IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR"]
["A PARTICULAR PURPOSE ON ANY HARDWARE, SOFTWARE ORE ADVISE SUPPLIED "]
["TO THE PROJECT BY NXP, AND OR NAY PRODUCT RESULTING FROM NXP "]
["SERVICES. IN NO EVENT SHALL NXP BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL "]
["DAMAGES ARISING OUT OF THIS AGREEMENT."]
["CUSTOMER agrees to hold NXP harmless against any and all claims demands "]
["or actions by anyone on account of any damage, or injury, whether commercial,"]
["contractual, or tortuous, rising directly or indirectly as a result "]
["of the advise or assistance supplied CUSTOMER in connection with product, "]
["services or goods supplied under this Agreement."]
["********************************************************************************"]
["File:                 MPC5777C Clock Configurator.xls"]
["Owner:           Petr Stancik"]
["Classification:   General Business Information"]
["********************************************************************************"]
["Detailed Description: "]
[]
["This config tool simplifies PLL setting calculation and clock configuration for MPC5777C device."]
[]
["Follow these steps"]
[]
["Note: Macros have to be enabled!"]
[]
["1. Enter frequency of used XOSC and desired PLL0 and PLL1 output."]
[null,"- put values into cells B14, Q13 and Q20 of the \"Clocks\" sheet"]
[null,"- check if it is ",null,null,null,"Valid",null,"or ","Invalid"]
[null,"- \"PLLconfig\" sheet shows possible PLLs configurations"]
[]
["2. Configure System and AUX clock selectors and its Dividers"]
[null,"- check calculated frequency of System/Peripheral clocks"]
[null,"- if ","Invalid",null,"change source clock and Divider value to keep Max freq."]
[]
["3. Copy generated code by pressing \"Copy Code\" button"]
[]
[]
["********************************************************************************"]
[]
["Revision History:"]
[]
["Version 1.0     May-10-2016     PetrS"]
[]
["Version 1.1     Aug-1-2016     PetrS"]
["- fixed PLL0_PHI and PLL1_PHI calculation"]
[]
["Version 1.2    Apr-17-2018    PetrS"]
["- fixed MCAN PE clock selection to be either XOSC or FM_PER_CLK"]
[]
["Version 1.3    Apr-1-2020    PetrS"]
["- added option to select between 264/300 MHz MCU versions"]

{"sheet":"Clocks","index":1,"n_rows":57,"n_cols":59,"rows_kept":57,"cut":false,"hidden":false,"merged":[[39,36,40,37],[36,36,37,37],[33,36,34,37],[30,36,31,37],[27,36,28,37],[27,33,30,33],[80,21,83,23],[80,24,83,24],[58,20,59,22],[47,24,47,25],[46,23,46,26],[36,20,36,22],[36,23,36,25],[82,41,82,44],[75,26,78,29],[75,30,78,30],[77,41,77,44],[10,25,22,25],[10,27,22,28],[91,41,91,44],[47,41,47,44],[66,41,66,44],[7,34,10,34],[85,41,85,44],[88,41,88,44],[19,36,20,37],[68,37,68,40],[74,41,74,44],[48,37,48,40],[50,33,53,33],[44,33,47,33],[7,36,8,37],[10,36,11,37],[21,36,22,37],[44,36,45,39],[58,23,59,25],[15,30,16,31],[121,41,121,44],[94,41,94,44],[97,41,97,44],[100,41,100,44],[103,41,103,44],[106,41,106,44],[118,41,118,44],[109,41,109,44],[112,41,112,44],[115,41,115,44],[32,14,34,16],[60,3,61,7],[62,3,62,7],[58,3,59,7],[14,14,14,20],[21,14,21,20],[12,3,14,5],[10,9,13,11],[10,12,13,12],[12,16,12,18],[10,16,10,18],[17,16,17,18],[15,15,15,19],[23,3,25,5],[17,9,20,11],[17,12,20,12],[19,16,19,18],[22,15,22,19],[42,5,42,6],[42,8,42,9],[47,3,47,4],[52,18,52,19],[51,17,51,20],[58,17,59,19],[58,14,59,16],[58,11,59,13],[58,8,59,10],[62,17,62,19],[62,20,62,22],[62,23,62,25],[60,8,60,10],[61,8,61,10],[62,8,62,10],[60,11,60,13],[60,14,60,16],[60,17,60,19],[60,20,60,22],[60,23,60,25],[61,11,61,13],[61,14,61,16],[61,17,61,19],[61,20,61,22],[61,23,61,25],[62,11,62,13],[62,14,62,16],[32,11,34,13],[32,8,34,10],[32,3,34,7],[37,20,37,22],[37,23,37,25],[32,23,34,25],[32,20,34,22],[32,17,34,19],[37,3,37,7],[37,8,37,10],[37,11,37,13],[37,14,37,16],[37,17,37,19],[35,3,36,7],[35,8,35,10],[35,11,35,13],[35,14,35,16],[35,17,35,19],[35,20,35,22],[35,23,35,25],[36,8,36,10],[36,11,36,13],[36,14,36,16],[36,17,36,19]]}
[]
[null,"! Macros has to be enabled !",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MPC5777C Clock configurator"]
[]
[null,"! Choose operating frequency of used device ! "]
[null,null,"(according datasheet, section 5)"]
[]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"code","v":" // Enable PLL0, PLL1 and select PLL1 as sys clk (300 MHz) "}]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ECSS",null,{"$f":"Sheet2!E22","v":"ENGDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"void SysClk_Init(void)"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G22&\" MHz\"","v":"4.69 MHz"},null,null,null,null,{"$f":"Sheet2!J22","v":"ENG_CLK"},null,null,null,null,null,null,null,null,null,null,null,"{"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F22&\" MHz\"","v":"max 80 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.SYSDIV.B.SYSCLKSEL = 0;\t\t    //run system clock from IRC"]
[null,null,null,null,null,null,null,null,null,null,null,null,"PLL1 Sel",null,null,null,"PLL1",null,null,null,null,null,null,null,null,"System Clock Selector",null,"PCS",null,null,null,null,null,null,null,null,{"$f":"Sheet2!E9","v":"EBDF"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      PLLDIG.PLL0CR.B.CLKCFG = 0;\t\t    //disable PLL0"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PHI",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G9&\" MHz\"","v":"50 MHz"},null,null,null,null,{"$f":"Sheet2!J9","v":"CLKOUT"},null,null,null,null,null,null,null,null,null,null,null,"      PLLDIG.PLL1CR.B.CLKCFG = 0;\t\t    //disable PLL1"]
[null,null,null,"Oscillator \nXOSC",null,null,null,null,null,null,null,null,null,null,null,null,300,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F9&\" MHz\"","v":"max 66 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.SYSDIV.B.PLL0SEL = 0x00;\t\t    //connect XOSC to the PLL0 input"]
[null,40,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.SYSDIV.B.PLL1SEL = 0x01;\t\t    //connect PLL0-PHI1 to the PLL1 input"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"IF(pll1closest<>0,\"closest \"&pll1closest&\" MHz\",IF(Sheet3!M9=1,\"check PLL1 input (38-78Mhz)\",\"no valid PLL0 setting\"))","v":"closest 300 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,{"$f":"\"check XOSC (8-40Mhz)\"","v":"check XOSC (8-40Mhz)"},null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"           \"&pll1closestInt&\" MHz\"","v":"           300 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!E6","v":"SYSCLKDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      // Set PLL0 to 240 MHz with 40MHz XOSC reference"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"ROUND(coreclkval,2)&\" MHz\"","v":"300 MHz"},null,null,null,null,"CORE_CLK",null,null,null,null,null,null,null,null,null,null,null,"      PLLDIG.PLL0DV.R = 0x4002100C;\t     // PREDIV =  1, MFD = 12, RFDPHI = 2, RFDPHI1 = 8"]
[null,null,null,null,null,null,null,null,null,null,null,null,"PLL0 Sel",null,null,null,"PLL0",null,null,null,"PHI1",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&coreclkmax&\" MHz\"","v":"max 300 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      while(SIU.RSR.B.XOSC==0){};\t\t    //wait for stable XOSC"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,240,null,null,null,"PHI",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"/ 2",null,null,null,null,{"$f":"ROUND(sc_ssVal/2,2)&\" MHz\"","v":"150 MHz"},null,null,null,null,"PLAT_CLK",null,null,null,null,null,null,null,null,null,null,null,"      PLLDIG.PLL0CR.B.CLKCFG = 3;\t\t    //turn on PLL0"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&sc_ssMax/2&\" MHz\"","v":"max 100 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      while(PLLDIG.PLL0SR.B.LOCK==0){};\t\t    //wait for PLL0 lock"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"IF(pll0closest<>0,\"closest \"&pll0closest&\" MHz\",IF(AND(osc>=oscmin,osc<=oscmax),\"no valid PLL0 setting\",\"check PLL0 input (8-44Mhz)\"))","v":"closest 240 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!E8","v":"FMPERDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"           \"&pll0closestInt&\" MHz\"","v":"           240 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"ROUND(Sheet2!G8,2)&\" MHz\"","v":"150 MHz"},null,null,null,null,{"$f":"Sheet2!J8","v":"FM_PER_CLK"},null,null,null,null,null,null,null,null,null,null,null,"      // Set PLL1 to 300 MHz with 60MHz PLL0-PHI1 reference"]
[null,null,null,"16 MHz IRC",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F8&\" MHz\"","v":"max 150 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      PLLDIG.PLL1DV.R = 0x00020014;\t     // MFD = 20, RFDPHI = 2"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      PLLDIG.PLL1CR.B.CLKCFG = 3;\t\t    //turn on PLL1"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      while(PLLDIG.PLL1SR.B.LOCK==0){};\t\t    //wait for PLL1 lock"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PerClkSel",null,null,{"$f":"Sheet2!E14","v":"ETPUDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G14&\" MHz\"","v":"240 MHz"},null,null,null,null,{"$f":"Sheet2!J14","v":"ETPU_CLK"},null,null,null,null,null,null,null,null,null,null,null,"      // Select clock dividers and sources"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F14&\" MHz\"","v":"max 240 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    PLL0 SEL = 0 … XOSC selected"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!E15","v":"PERDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    PLL1 SEL = 1 … PLL0-PHI1 selected"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G15&\" MHz\"","v":"120 MHz"},null,null,null,null,{"$f":"Sheet2!J15","v":"PER_CLK"},null,null,null,null,null,null,null,null,null,null,null,"      //    PERCLKSEL = 1 … PLL0 selected"]
[null,null,null,"Clock Domain",null,null,null,null,"Mode",null,null,"Core CORE_CLK",null,null,"eTPU eTPU_CLK",null,null,"Platform PLAT_CLK",null,null,"Per. memory mapped regs FM_PER_CLK",null,null,"Peripherals protocol engines PER_CLK",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F15&\" MHz\"","v":"max 120 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    FMPERDIV = 0 … div by 2"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!E16","v":"SDDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    PERDIV = 0 … div by 2"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G16&\" MHz\"","v":"16 MHz"},null,null,null,null,{"$f":"Sheet2!J16","v":"SD_CLK"},null,null,null,null,null,null,null,null,null,null,null,"      //    MCALSEL = 0 … XOSC selected"]
[null,null,null,"Backward compatible: one clock domain",null,null,null,null,"Double",null,null,{"$f":"Sheet2!F85","v":300},null,null,{"$f":"Sheet2!G85","v":150},null,null,{"$f":"Sheet2!H85","v":150},null,null,{"$f":"Sheet2!I85","v":150},null,null,{"$f":"Sheet2!J85","v":150},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F16&\" MHz\"","v":"max 16 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    SYSCLKSEL = 2 … PLL1"]
[null,null,null,null,null,null,null,null,"eTPU",null,null,{"$f":"Sheet2!F86","v":240},null,null,{"$f":"Sheet2!G86","v":240},null,null,{"$f":"Sheet2!H86","v":120},null,null,{"$f":"Sheet2!I86","v":120},null,null,{"$f":"Sheet2!J86","v":120},null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!E17","v":"PSDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    ETPUDIV = 1 … div by 1"]
[null,null,null,"Enhanced: dual clock",null,null,null,null,"Normal",null,null,{"$f":"Sheet2!F87","v":300},null,null,{"$f":"Sheet2!G87","v":240},null,null,{"$f":"Sheet2!H87","v":150},null,null,{"$f":"Sheet2!I87","v":150},null,null,{"$f":"Sheet2!J87","v":120},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G17&\" MHz\"","v":"80 MHz"},null,null,null,null,{"$f":"Sheet2!J17","v":"PSI5_RX_CLK"},null,null,null,null,null,null,null,null,null,null,null,"      //    SYSCLKDIV = 4 … div by 1"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F17&\" MHz\"","v":"max 100 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    PCS = 0 … Disabled"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!E18","v":"PSDIV1M"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.SYSDIV.R = 0x05002110; "]
[null,"1. Enter frequency of used XOSC and desired PLL0 and PLL1 output.",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G18&\" MHz\"","v":"1 MHz"},null,null,null,null,{"$f":"Sheet2!J18","v":"PSI5_1US_CLK"},null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,{"$f":"\"- put values into cells B14, Q13 and Q20\"","v":"- put values into cells B14, Q13 and Q20"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F18&\" MHz\"","v":"max 1 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    ENGDIV = 16 … div by 32"]
[null,null,{"$f":"\"- check if it is \"","v":"- check if it is "},null,null,"Valid",null,"or ","Invalid",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    ECCS = 0 … PLAT_CLK selected"]
[null,null,{"$f":"\"- PLL config sheet shows possible PLLs configurations\"","v":"- PLL config sheet shows possible PLLs configurations"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    EBDF = 2 … div by 3"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LF CLK SEL",null,null,{"$f":"Sheet2!E34","v":"LFDIV"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.ECCR.R = 0x00001002; "]
[null,"2. Configure System and AUX clock selectors and its Dividers",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!G34&\" MHz\"","v":"20 MHz"},null,null,null,null,{"$f":"Sheet2!J34","v":"LFAST_CLK"},null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,{"$f":"\"- check calculated frequency of System/Peripheral clocks\"","v":"- check calculated frequency of System/Peripheral clocks"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SIPI_REF_CLK",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F34&\" MHz\"","v":"max 26 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    SDDIV = 14 … div by 15"]
[null,null,{"$f":"\"- if \"","v":"- if "},"Invalid",null,"change source clock and Divider value to keep Max freq.",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,50,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.SDCLKCFG.R = 0x0000000E; "]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"(external signal)",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,"3. Copy generated code by pressing \"Copy Code\" button",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    LFCLKSEL = 0 … XOSC selected"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCANSel",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //    LFDIV = 1 … div by 2"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"Sheet2!H25&\" MHz\"","v":"40 MHz"},null,null,null,null,{"$f":"Sheet2!J26","v":"MCAN_CPI_CLK"},null,null,null,null,null,null,null,null,null,null,null,"      SIU.LFCLKCFG.R = 0x00000001; "]
[null,null,null,null,{"$f":"\"- set aux clk sel/div to its reset value\"","v":"- set aux clk sel/div to its reset value"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"max \"&Sheet2!F25&\" MHz\"","v":"max 150 MHz"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //   PSDIV = 2 … div by 3"]
[null,null,null,null,{"$f":"\"- set aux clk sel/div to Max value\"","v":"- set aux clk sel/div to Max value"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      //   PSDIV1M = 239 … div by 240"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"      SIU.PSCLKCFG.R = 0x000200EF; "]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"}"]

{"sheet":"PLLconfig","index":2,"n_rows":47,"n_cols":25,"rows_kept":47,"cut":false,"hidden":false,"merged":[[21,1,21,4],[21,14,21,17]]}
[]
[]
[]
[]
[]
[]
[]
[]
[]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Fractional divider not used"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"in this version"]
[]
[]
[]
[]
[]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Fractional divider not used"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"in this version"]
[]
[null,"Select possible PLL0 configurations",null,null,null,null,null,null,null,null,null,null,null,null,"Select possible PLL1 configurations"]
[]
[null,"Selected PLL_0 configurations",null,null,null,1,null,null,null,null,null,null,null,null,"Selected PLL_1 configurations",null,null,null,1]
[]
[null,{"$f":"INDIRECT(\"PLL0_result\"&Sheet3!M9)","v":""},"MFD","PREDIV","RFDPHI","RFDPHI1","","fPLLin","fVCO","fphi",0,"PLL0DV","",null,{"$f":"INDIRECT(\"PLL1_result\"&Sheet3!M9)","v":""},"MFD","","RFDPHI","","","fPLLin","fVCO","fphi","","PLL1DV"]
[null,1,12,1,2,8,0,40,960,240,0,"0x4002100C","",null,1,20,"",2,"","",60,1200,300,"","0x00020014"]
[null,2,24,2,2,8,0,40,960,240,0,"0x40022018","",null,2,20,"",2,"","",60,1200,300,"","0x00020014"]
[null,3,36,3,2,8,0,40,960,240,0,"0x40023024","",null,3,20,"",2,"","",60,1200,300,"","0x00020014"]
[null,4,48,4,2,8,0,40,960,240,0,"0x40024030","",null,4,20,"",2,"","",60,1200,300,"","0x00020014"]
[null,5,60,5,2,8,0,40,960,240,0,"0x4002503C","",null,5,20,"",2,"","",60,1200,300,"","0x00020014"]
[null,6,72,6,2,8,0,40,960,240,0,"0x40026048","",null,6,20,"",2,"","",60,1200,300,"","0x00020014"]
[null,7,84,7,2,8,0,40,960,240,0,"0x40027054","",null,7,20,"",2,"","",60,1200,300,"","0x00020014"]
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{"sheet":"Sheet2","index":3,"n_rows":1035,"n_cols":20,"rows_kept":1035,"cut":false,"hidden":true,"merged":[]}
[]
[null,null,null,"Control","Name","Max","Value","Selected","list",null,null,null,null,null,null,"reset","max 264","max 300"]
[null,null,null,4,"SYSCLKSEL",600,null,{"$f":"INDEX(I3:L3,1,$D$3)","v":"PLL1"},"IRC","XOSC","PLL0","PLL1",null,null,null,1,4,4,null,{"$f":"\" // Enable PLL0, PLL1 and select \"&$H$3&\" as sys clk (\"&$H$5&\" MHz) \"","v":" // Enable PLL0, PLL1 and select PLL1 as sys clk (300 MHz) "}]
[null,null,null,240,null,null,null,{"$f":"INDEX(I4:L4,1,$D$3)","v":2},0,1,3,2,null,null,null,160,192,240,null,{"$f":"\"void SysClk_Init(void)\"","v":"void SysClk_Init(void)"}]
[null,null,null,300,null,200,null,300,16,{"$f":"osc","v":40},{"$f":"pll_0","v":240},{"$f":"pll_1","v":300},null,null,null,200,264,300,null,{"$f":"\"{\"","v":"{"}]
["disabled",0,null,5,"SYSCLKDIV",{"$f":"$F$89","v":300},{"$f":"ROUNDUP($H$5/(H6),2)","v":300},{"$f":"INDEX(listsysval1,D6)","v":1},null,"CORE_CLK",null,null,null,null,null,5,5,5,null,{"$f":"\"      SIU.SYSDIV.B.SYSCLKSEL = 0;\"&CHAR(9)&CHAR(9)&\"    //run system clock from IRC\"","v":"      SIU.SYSDIV.B.SYSCLKSEL = 0;\t\t    //run system clock from IRC"}]
[{"$f":"\"div by \"&B7","v":"div by 1"},1,null,null,null,{"$f":"$H$89","v":150},{"$f":"coreclkval/2","v":150},null,null,"PLAT_CLK",null,null,null,null,null,null,null,null,null,{"$f":"\"      PLLDIG.PLL0CR.B.CLKCFG = 0;\"&CHAR(9)&CHAR(9)&\"    //disable PLL0\"","v":"      PLLDIG.PLL0CR.B.CLKCFG = 0;\t\t    //disable PLL0"}]
[{"$f":"\"div by \"&B8","v":"div by 2"},2,null,1,"FMPERDIV",{"$f":"$I$89","v":150},{"$f":"ROUNDUP($H$5/(H8),2)","v":150},{"$f":"POWER(2,INDEX(listpow2val,$D$8)+1)","v":2},null,"FM_PER_CLK",null,null,null,null,null,1,1,1,null,{"$f":"\"      PLLDIG.PLL1CR.B.CLKCFG = 0;\"&CHAR(9)&CHAR(9)&\"    //disable PLL1\"","v":"      PLLDIG.PLL1CR.B.CLKCFG = 0;\t\t    //disable PLL1"}]
["div by 3",3,null,3,"EBDF",66,{"$f":"ROUNDUP($H$5/2/(H9),2)","v":50},{"$f":"INDEX(list4enval,D9)","v":3},null,"CLKOUT",null,null,null,null,null,2,2,3,null,{"$f":"\"      SIU.SYSDIV.B.PLL0SEL = 0x\"&DEC2HEX($H$65,2)&\";\"&CHAR(9)&CHAR(9)&\"    //connect \"&$H$64&\" to the PLL0 input\"","v":"      SIU.SYSDIV.B.PLL0SEL = 0x00;\t\t    //connect XOSC to the PLL0 input"}]
["div by 4",4,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      SIU.SYSDIV.B.PLL1SEL = 0x\"&DEC2HEX($H$68,2)&\";\"&CHAR(9)&CHAR(9)&\"    //connect \"&$H$67&\" to the PLL1 input\"","v":"      SIU.SYSDIV.B.PLL1SEL = 0x01;\t\t    //connect PLL0-PHI1 to the PLL1 input"}]
["div by 5",5,null,2,"PERCLKSEL",null,null,{"$f":"INDEX(I11:K11,1,$D$11)","v":"PLL0"},"CORE_CLK","PLL0",null,null,null,null,null,1,2,2,null,{"$f":"\"\"","v":""}]
["div by 6",6,null,null,null,null,null,{"$f":"INDEX(I12:K12,1,$D$11)","v":1},0,1,null,null,null,null,null,null,null,null,null,{"$f":"\"      // Set PLL0 to \"&INDEX(PLLconfig!J25:J47,PLLconfig!$F$22,1)&\" MHz with \"&INDEX(PLLconfig!H25:H47,PLLconfig!$F$22,1)&\"MHz \"&H64&\" reference\"","v":"      // Set PLL0 to 240 MHz with 40MHz XOSC reference"}]
["div by 7",7,null,null,null,null,null,240,{"$f":"coreclkval","v":300},{"$f":"pll_0","v":240},null,null,null,null,null,null,null,null,null,{"$f":"\"      PLLDIG.PLL0DV.R = \"&INDEX(PLLconfig!L25:L47,PLLconfig!$F$22,1)&\";\"&CHAR(9)&\"     // PREDIV =  \"&INDEX(PLLconfig!D25:D47,PLLconfig!$F$22,1)&\", MFD = \"&INDEX(PLLconfig!C25:C47,PLLconfig!$F$22,1)&\", RFDPHI = \"&INDEX(PLLconfig!E25:E47,PLLconfig!$F$22,1)&\", RFDPHI1 = \"&INDEX(PLLconfig!F25:F47,PLLconfig!$F$22,1)","v":"      PLLDIG.PLL0DV.R = 0x4002100C;\t     // PREDIV =  1, MFD = 12, RFDPHI = 2, RFDPHI1 = 8"}]
["div by 8",8,null,1,"ETPUDIV",{"$f":"$G$89","v":240},{"$f":"ROUNDUP($H$13/(H14),2)","v":240},{"$f":"INDEX(list2enval,D14)","v":1},null,"ETPU_CLK",null,null,null,null,null,1,1,1,null,{"$f":"\"\"","v":""}]
["div by 9",9,null,1,"PERDIV",{"$f":"$J$89","v":120},{"$f":"ROUNDUP($H$13/(H15),2)","v":120},{"$f":"POWER(2,INDEX(listpow2val,$D$15)+1)","v":2},null,"PER_CLK",null,null,null,null,null,1,1,1,null,{"$f":"\"      while(SIU.RSR.B.XOSC==0){};\"&CHAR(9)&CHAR(9)&\"    //wait for stable XOSC\"","v":"      while(SIU.RSR.B.XOSC==0){};\t\t    //wait for stable XOSC"}]
["div by 10",10,null,15,"SDDIV",16,16,{"$f":"INDEX(list128enval,D16)","v":15},null,"SD_CLK",null,null,null,null,null,1,12,15,null,{"$f":"\"      PLLDIG.PLL0CR.B.CLKCFG = 3;\"&CHAR(9)&CHAR(9)&\"    //turn on PLL0\"","v":"      PLLDIG.PLL0CR.B.CLKCFG = 3;\t\t    //turn on PLL0"}]
["div by 11",11,null,3,"PSDIV",100,80,{"$f":"INDEX(list256enval,D17)","v":3},null,"PSI5_RX_CLK",null,null,null,null,null,1,2,3,null,{"$f":"\"      while(PLLDIG.PLL0SR.B.LOCK==0){};\"&CHAR(9)&CHAR(9)&\"    //wait for PLL0 lock\"","v":"      while(PLLDIG.PLL0SR.B.LOCK==0){};\t\t    //wait for PLL0 lock"}]
["div by 12",12,null,240,"PSDIV1M",1,1,{"$f":"INDEX(list1024enval,D18)","v":240},null,"PSI5_1US_CLK",null,null,null,null,null,1,192,240,null,{"$f":"\"\"","v":""}]
["div by 13",13,null,2,"ECSS",null,null,{"$f":"INDEX(I19:L19,1,$D$19)","v":"PLAT_CLK"},"XOSC","PLAT_CLK",null,null,null,null,null,2,2,2,null,{"$f":"\"      // Set PLL1 to \"&INDEX(PLLconfig!W25:W47,IF(Sheet3!M9=2,PLLconfig!$F$22,PLLconfig!$S$22),1)&\" MHz with \"&INDEX(PLLconfig!U25:U47,IF(Sheet3!M9=2,PLLconfig!$F$22,PLLconfig!$S$22),1)&\"MHz \"&H67&\" reference\"","v":"      // Set PLL1 to 300 MHz with 60MHz PLL0-PHI1 reference"}]
["div by 14",14,null,null,null,null,null,{"$f":"INDEX(I20:L20,1,$D$19)","v":0},1,0,null,null,null,null,null,null,null,null,null,{"$f":"\"      PLLDIG.PLL1DV.R = \"&INDEX(PLLconfig!Y25:Y47,IF(Sheet3!M9=2,PLLconfig!$F$22,PLLconfig!$S$22),1)&\";\"&CHAR(9)&\"     // MFD = \"&INDEX(PLLconfig!P25:P47,PLLconfig!$S$22,1)&\", RFDPHI = \"&INDEX(PLLconfig!R25:R47,PLLconfig!$S$22,1)","v":"      PLLDIG.PLL1DV.R = 0x00020014;\t     // MFD = 20, RFDPHI = 2"}]
["div by 15",15,null,null,null,null,null,{"$f":"INDEX(I21:L21,1,$D$19)","v":150},{"$f":"osc","v":40},{"$f":"$G$7","v":150},null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 16",16,null,16,"ENGDIV",80,{"$f":"ROUNDUP(H21/(H22),2)","v":4.6899999999999995},{"$f":"INDEX(listodd510val,D22)","v":32},null,"ENG_CLK",null,null,null,null,null,16,16,16,null,{"$f":"\"      PLLDIG.PLL1CR.B.CLKCFG = 3;\"&CHAR(9)&CHAR(9)&\"    //turn on PLL1\"","v":"      PLLDIG.PLL1CR.B.CLKCFG = 3;\t\t    //turn on PLL1"}]
["div by 17",17,null,1,"MCANSEL",null,null,{"$f":"INDEX(I23:L23,1,$D$23)","v":"XOSC"},"XOSC","PER_CLK",null,null,null,null,null,1,1,1,null,{"$f":"\"      while(PLLDIG.PLL1SR.B.LOCK==0){};\"&CHAR(9)&CHAR(9)&\"    //wait for PLL1 lock\"","v":"      while(PLLDIG.PLL1SR.B.LOCK==0){};\t\t    //wait for PLL1 lock"}]
["div by 18",18,null,null,null,null,null,{"$f":"INDEX(I24:L24,1,$D$23)","v":0},0,1,null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 19",19,null,null,null,{"$f":"$H$89","v":150},null,{"$f":"INDEX(I25:L25,1,$D$23)","v":40},{"$f":"osc","v":40},{"$f":"$G$15","v":120},null,null,null,null,null,null,null,null,null,{"$f":"\"      // Select clock dividers and sources\"","v":"      // Select clock dividers and sources"}]
["div by 20",20,null,1,null,null,null,null,null,"MCAN_CPI_CLK",null,null,null,null,null,1,1,1,null,{"$f":"\"      //    PLL0 SEL = \"&$H$65&\" … \"&$H$64&\" selected\"","v":"      //    PLL0 SEL = 0 … XOSC selected"}]
["div by 21",21,null,1,null,null,null,null,null,null,null,null,null,null,null,1,1,1,null,{"$f":"\"      //    PLL1 SEL = \"&$H$68&\" … \"&$H$67&\" selected\"","v":"      //    PLL1 SEL = 1 … PLL0-PHI1 selected"}]
["div by 22",22,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    PERCLKSEL = \"&$H$12&\" … \"&$H$11&\" selected\"","v":"      //    PERCLKSEL = 1 … PLL0 selected"}]
["div by 23",23,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    FMPERDIV = \"&INDEX(listpow2val,$D$8)&\" … \"&INDEX(listpow2,$D$8)","v":"      //    FMPERDIV = 0 … div by 2"}]
["div by 24",24,null,1,null,null,null,null,null,null,null,null,null,null,null,1,1,1,null,{"$f":"\"      //    PERDIV = \"&INDEX(listpow2val,$D$15)&\" … \"&INDEX(listpow2,$D$15)","v":"      //    PERDIV = 0 … div by 2"}]
["div by 25",25,null,1,"LFCLKSEL",null,null,{"$f":"INDEX(I31:L31,1,$D$31)","v":"XOSC"},"XOSC","PER_CLK","SIPI_REF_CLK",null,null,null,null,1,1,1,null,{"$f":"\"      //    MCALSEL = \"&$H$24&\" … \"&$H$23&\" selected\"","v":"      //    MCALSEL = 0 … XOSC selected"}]
["div by 26",26,null,null,null,null,null,{"$f":"INDEX(I32:L32,1,$D$31)","v":0},0,2,1,null,null,null,null,null,null,null,null,{"$f":"\"      //    SYSCLKSEL = \"&$H$4&\" … \"&$H$3","v":"      //    SYSCLKSEL = 2 … PLL1"}]
["div by 27",27,null,null,null,null,null,40,{"$f":"osc","v":40},{"$f":"H13","v":240},{"$f":"drclk_io","v":50},null,null,null,null,null,null,null,null,{"$f":"\"      //    ETPUDIV = \"&INDEX(list2enval,D14)&\" … \"&INDEX(list2en,D14)","v":"      //    ETPUDIV = 1 … div by 1"}]
["div by 28",28,null,2,"LFDIV",26,{"$f":"ROUNDUP($H$33/(H34),2)","v":20},{"$f":"INDEX(list128enval,D34)","v":2},null,"LFAST_CLK",null,null,null,null,null,1,2,2,null,{"$f":"\"      //    SYSCLKDIV = \"&INDEX(listsysval,D6)&\" … \"&INDEX(listsys,D6)","v":"      //    SYSCLKDIV = 4 … div by 1"}]
["div by 29",29,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    PCS = 0 … Disabled\"","v":"      //    PCS = 0 … Disabled"}]
["div by 30",30,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      SIU.SYSDIV.R = 0x\"&DEC2HEX($H$65*2^28+$H$68*2^26+$H$12*2^24+INDEX(listpow2val,$D$8)*2^20+INDEX(listpow2val,$D$15)*2^16+$H$24*2^15+$H$4*2^12+INDEX(list2enval,D14)*2^8+INDEX(listsysval,D6)*2^2,8)&\"; \"","v":"      SIU.SYSDIV.R = 0x05002110; "}]
["div by 31",31,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 32",32,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    ENGDIV = \"&INDEX(listodd510val,D22)/2&\" … \"&INDEX(listodd510,D22)","v":"      //    ENGDIV = 16 … div by 32"}]
["div by 33",33,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    ECCS = \"&$H$20&\" … \"&$H$19&\" selected\"","v":"      //    ECCS = 0 … PLAT_CLK selected"}]
["div by 34",34,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    EBDF = \"&INDEX(list4enval,D9)-1&\" … \"&INDEX(list4en,D9)","v":"      //    EBDF = 2 … div by 3"}]
["div by 35",35,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      SIU.ECCR.R = 0x\"&DEC2HEX(INDEX(listodd510val,D22)/2*2^8+$H$20*2^7+INDEX(list4enval,D9)-1,8)&\"; \"","v":"      SIU.ECCR.R = 0x00001002; "}]
["div by 36",36,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 37",37,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    SDDIV = \"&H16-1&\" … \"&INDEX(list128en,D16)","v":"      //    SDDIV = 14 … div by 15"}]
["div by 38",38,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      SIU.SDCLKCFG.R = 0x\"&DEC2HEX(H16-1,8)&\"; \"","v":"      SIU.SDCLKCFG.R = 0x0000000E; "}]
["div by 39",39,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 40",40,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    LFCLKSEL = \"&$H$32&\" … \"&$H$31&\" selected\"","v":"      //    LFCLKSEL = 0 … XOSC selected"}]
["div by 41",41,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //    LFDIV = \"&H34-1&\" … \"&INDEX(list128en,D34)","v":"      //    LFDIV = 1 … div by 2"}]
["div by 42",42,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      SIU.LFCLKCFG.R = 0x\"&DEC2HEX($H$32*2^12+H34-1,8)&\"; \"","v":"      SIU.LFCLKCFG.R = 0x00000001; "}]
["div by 43",43,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 44",44,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //   PSDIV = \"&H17-1&\" … \"&INDEX(list256en,D17)","v":"      //   PSDIV = 2 … div by 3"}]
["div by 45",45,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      //   PSDIV1M = \"&H18-1&\" … \"&INDEX(list1024en,D18)","v":"      //   PSDIV1M = 239 … div by 240"}]
["div by 46",46,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"      SIU.PSCLKCFG.R = 0x\"&DEC2HEX(($H$17-1)*2^16+H18-1,8)&\"; \"","v":"      SIU.PSCLKCFG.R = 0x000200EF; "}]
["div by 47",47,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"}\"","v":"}"}]
["div by 48",48]
["div by 49",49,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"\"\"","v":""}]
["div by 50",50]
["div by 51",51]
["div by 52",52]
["div by 53",53]
["div by 54",54]
["div by 55",55]
["div by 56",56]
["div by 57",57]
["div by 58",58,null,2,"PLL0SEL",null,null,{"$f":"INDEX(I64:L64,1,$D$64)","v":"XOSC"},"IRC","XOSC",null,null,null,null,null,2,2,2]
["div by 59",59,null,null,null,null,null,{"$f":"INDEX(I65:L65,1,$D$64)","v":0},1,0]
["div by 60",60,null,null,null,null,null,40,16,{"$f":"osc","v":40}]
["div by 61",61,null,2,"PLL1SEL",null,null,{"$f":"INDEX(I67:L67,1,$D$67)","v":"PLL0-PHI1"},"XOSC","PLL0-PHI1",null,null,null,null,null,1,2,2]
["div by 62",62,null,null,null,null,null,{"$f":"INDEX(I68:L68,1,$D$67)","v":1},0,1]
["div by 63",63,null,null,null,null,null,0,{"$f":"osc","v":40}]
["div by 64",64]
["div by 65",65]
[{"$f":"\"div by \"&B72","v":"div by 66"},66]
["div by 67",67,null,"div by 2",0,2]
["div by 68",68,null,"div by 4",1,4]
["div by 69",69,null,"div by 8",2,8]
["div by 70",70,null,"div by 16",3,16]
["div by 71",71,null,"div by 1",4,1]
["div by 72",72,null,"div by 1",5,1]
["div by 73",73,null,"div by 1",6,1]
["div by 74",74,null,"div by 1",7,1]
["div by 75",75]
["div by 76",76,null,null,null,null,null,null,null,null,null,null,null,null,null,2]
["div by 77",77]
["div by 78",78,null,null,"mode","CORECLK","eTPU CLK","PLATCLK","FM_PER_CKL","PER_CLK",null,null,"fsys",264,300,{"$f":"IF($P$82=1,N84,O84)","v":300}]
["div by 79",79,null,null,"double",{"$f":"P84","v":300},{"$f":"$F$85/2","v":150},{"$f":"$F$85/2","v":150},150,150,null,null,"fplatf",132,150,{"$f":"IF($P$82=1,N85,O85)","v":150}]
["div by 80",80,null,null,"eTPU",{"$f":"P86","v":240},{"$f":"P86","v":240},{"$f":"$G$86/2","v":120},{"$f":"$G$86/2","v":120},120,null,null,"fetpu",200,240,240]
["div by 81",81,null,null,"Normal",{"$f":"P84","v":300},{"$f":"P86","v":240},{"$f":"$F$87/2","v":150},{"$f":"$F$87/2","v":150},{"$f":"G87/2","v":120},null,null,"febi",66,66,66]
["div by 82",82,null,null,null,null,null,null,null,null,null,null,"fper",132,150,150]
["div by 83",83,null,null,{"$f":"INDEX(E85:E87,IF($D$11=2,3,IF($D$14=1,2,1)),1)","v":"Normal"},{"$f":"INDEX(F85:F87,IF($D$11=2,3,IF($D$14=1,2,1)),1)","v":300},{"$f":"INDEX(G85:G87,IF($D$11=2,3,IF($D$14=1,2,1)),1)","v":240},150,150,120,null,null,"ffmper",132,150,150]
["div by 84",84]
["div by 85",85]
["div by 86",86]
["div by 87",87]
["div by 88",88]
["div by 89",89]
["div by 90",90]
["div by 91",91]
["div by 92",92]
["div by 93",93]
["div by 94",94]
["div by 95",95]
["div by 96",96]
["div by 97",97]
["div by 98",98]
["div by 99",99]
["div by 100",100,null,"div by 2",2]
["div by 101",101,null,"div by 4",4]
["div by 102",102,null,"div by 6",6]
["div by 103",103,null,"div by 8",8]
["div by 104",104,null,"div by 10",10]
["div by 105",105,null,"div by 12",12]
["div by 106",106,null,"div by 14",14]
["div by 107",107,null,"div by 16",16]
["div by 108",108,null,"div by 18",18]
["div by 109",109,null,"div by 20",20]
["div by 110",110,null,"div by 22",22]
["div by 111",111,null,"div by 24",24]
["div by 112",112,null,"div by 26",26]
["div by 113",113,null,"div by 28",28]
["div by 114",114,null,"div by 30",30]
["div by 115",115,null,"div by 32",32]
["div by 116",116,null,"div by 34",34]
["div by 117",117,null,"div by 36",36]
["div by 118",118,null,"div by 38",38]
["div by 119",119,null,"div by 40",40]
["div by 120",120,null,"div by 42",42]
["div by 121",121,null,"div by 44",44]
["div by 122",122,null,"div by 46",46]
["div by 123",123,null,"div by 48",48]
["div by 124",124,null,"div by 50",50]
["div by 125",125,null,"div by 52",52]
["div by 126",126,null,"div by 54",54]
["div by 127",127,null,"div by 56",56]
["div by 128",128,null,"div by 58",58]
["div by 129",129,null,"div by 60",60]
[{"$f":"\"div by \"&B136","v":"div by 130"},130,null,"div by 62",62]
["div by 131",131,null,"div by 64",64]
["div by 132",132,null,"div by 66",66]
["div by 133",133,null,"div by 68",68]
["div by 134",134,null,"div by 70",70]
["div by 135",135,null,"div by 72",72]
["div by 136",136,null,"div by 74",74]
["div by 137",137,null,"div by 76",76]
["div by 138",138,null,"div by 78",78]
["div by 139",139,null,"div by 80",80]
["div by 140",140,null,"div by 82",82]
["div by 141",141,null,"div by 84",84]
["div by 142",142,null,"div by 86",86]
["div by 143",143,null,"div by 88",88]
["div by 144",144,null,"div by 90",90]
["div by 145",145,null,"div by 92",92]
["div by 146",146,null,"div by 94",94]
["div by 147",147,null,"div by 96",96]
["div by 148",148,null,"div by 98",98]
["div by 149",149,null,"div by 100",100]
["div by 150",150,null,"div by 102",102]
["div by 151",151,null,"div by 104",104]
["div by 152",152,null,"div by 106",106]
["div by 153",153,null,"div by 108",108]
["div by 154",154,null,"div by 110",110]
["div by 155",155,null,"div by 112",112]
["div by 156",156,null,"div by 114",114]
["div by 157",157,null,"div by 116",116]
["div by 158",158,null,"div by 118",118]
["div by 159",159,null,"div by 120",120]
["div by 160",160,null,"div by 122",122]
["div by 161",161,null,"div by 124",124]
["div by 162",162,null,"div by 126",126]
["div by 163",163,null,"div by 128",128]
["div by 164",164,null,"div by 130",130]
["div by 165",165,null,"div by 132",132]
["div by 166",166,null,"div by 134",134]
["div by 167",167,null,"div by 136",136]
["div by 168",168,null,"div by 138",138]
["div by 169",169,null,"div by 140",140]
["div by 170",170,null,"div by 142",142]
["div by 171",171,null,"div by 144",144]
["div by 172",172,null,"div by 146",146]
["div by 173",173,null,"div by 148",148]
["div by 174",174,null,"div by 150",150]
["div by 175",175,null,"div by 152",152]
["div by 176",176,null,"div by 154",154]
["div by 177",177,null,"div by 156",156]
["div by 178",178,null,"div by 158",158]
["div by 179",179,null,"div by 160",160]
["div by 180",180,null,"div by 162",162]
["div by 181",181,null,"div by 164",164]
["div by 182",182,null,"div by 166",166]
["div by 183",183,null,"div by 168",168]
["div by 184",184,null,"div by 170",170]
["div by 185",185,null,"div by 172",172]
["div by 186",186,null,"div by 174",174]
["div by 187",187,null,"div by 176",176]
["div by 188",188,null,"div by 178",178]
["div by 189",189,null,"div by 180",180]
["div by 190",190,null,"div by 182",182]
["div by 191",191,null,"div by 184",184]
["div by 192",192,null,"div by 186",186]
["div by 193",193,null,"div by 188",188]
[{"$f":"\"div by \"&B200","v":"div by 194"},194,null,"div by 190",190]
["div by 195",195,null,"div by 192",192]
["div by 196",196,null,"div by 194",194]
["div by 197",197,null,"div by 196",196]
["div by 198",198,null,"div by 198",198]
["div by 199",199,null,"div by 200",200]
["div by 200",200,null,"div by 202",202]
["div by 201",201,null,"div by 204",204]
["div by 202",202,null,"div by 206",206]
["div by 203",203,null,"div by 208",208]
["div by 204",204,null,"div by 210",210]
["div by 205",205,null,"div by 212",212]
["div by 206",206,null,"div by 214",214]
["div by 207",207,null,"div by 216",216]
["div by 208",208,null,"div by 218",218]
["div by 209",209,null,"div by 220",220]
["div by 210",210,null,"div by 222",222]
["div by 211",211,null,"div by 224",224]
["div by 212",212,null,"div by 226",226]
["div by 213",213,null,"div by 228",228]
["div by 214",214,null,"div by 230",230]
["div by 215",215,null,"div by 232",232]
["div by 216",216,null,"div by 234",234]
["div by 217",217,null,"div by 236",236]
["div by 218",218,null,"div by 238",238]
["div by 219",219,null,"div by 240",240]
["div by 220",220,null,"div by 242",242]
["div by 221",221,null,"div by 244",244]
["div by 222",222,null,"div by 246",246]
["div by 223",223,null,"div by 248",248]
["div by 224",224,null,"div by 250",250]
["div by 225",225,null,"div by 252",252]
["div by 226",226,null,"div by 254",254]
["div by 227",227,null,"div by 256",256]
["div by 228",228,null,"div by 258",258]
["div by 229",229,null,"div by 260",260]
["div by 230",230,null,"div by 262",262]
["div by 231",231,null,"div by 264",264]
["div by 232",232,null,"div by 266",266]
["div by 233",233,null,"div by 268",268]
["div by 234",234,null,"div by 270",270]
["div by 235",235,null,"div by 272",272]
["div by 236",236,null,"div by 274",274]
["div by 237",237,null,"div by 276",276]
["div by 238",238,null,"div by 278",278]
["div by 239",239,null,"div by 280",280]
["div by 240",240,null,"div by 282",282]
["div by 241",241,null,"div by 284",284]
["div by 242",242,null,"div by 286",286]
["div by 243",243,null,"div by 288",288]
["div by 244",244,null,"div by 290",290]
["div by 245",245,null,"div by 292",292]
["div by 246",246,null,"div by 294",294]
["div by 247",247,null,"div by 296",296]
["div by 248",248,null,"div by 298",298]
["div by 249",249,null,"div by 300",300]
["div by 250",250,null,"div by 302",302]
["div by 251",251,null,"div by 304",304]
["div by 252",252,null,"div by 306",306]
["div by 253",253,null,"div by 308",308]
["div by 254",254,null,"div by 310",310]
["div by 255",255,null,"div by 312",312]
["div by 256",256,null,"div by 314",314]
["div by 257",257,null,"div by 316",316]
[{"$f":"\"div by \"&B264","v":"div by 258"},258,null,"div by 318",318]
["div by 259",259,null,"div by 320",320]
["div by 260",260,null,"div by 322",322]
["div by 261",261,null,"div by 324",324]
["div by 262",262,null,"div by 326",326]
["div by 263",263,null,"div by 328",328]
["div by 264",264,null,"div by 330",330]
["div by 265",265,null,"div by 332",332]
["div by 266",266,null,"div by 334",334]
["div by 267",267,null,"div by 336",336]
["div by 268",268,null,"div by 338",338]
["div by 269",269,null,"div by 340",340]
["div by 270",270,null,"div by 342",342]
["div by 271",271,null,"div by 344",344]
["div by 272",272,null,"div by 346",346]
["div by 273",273,null,"div by 348",348]
["div by 274",274,null,"div by 350",350]
["div by 275",275,null,"div by 352",352]
["div by 276",276,null,"div by 354",354]
["div by 277",277,null,"div by 356",356]
["div by 278",278,null,"div by 358",358]
["div by 279",279,null,"div by 360",360]
["div by 280",280,null,"div by 362",362]
["div by 281",281,null,"div by 364",364]
["div by 282",282,null,"div by 366",366]
["div by 283",283,null,"div by 368",368]
["div by 284",284,null,"div by 370",370]
["div by 285",285,null,"div by 372",372]
["div by 286",286,null,"div by 374",374]
["div by 287",287,null,"div by 376",376]
["div by 288",288,null,"div by 378",378]
["div by 289",289,null,"div by 380",380]
["div by 290",290,null,"div by 382",382]
["div by 291",291,null,"div by 384",384]
["div by 292",292,null,"div by 386",386]
["div by 293",293,null,"div by 388",388]
["div by 294",294,null,"div by 390",390]
["div by 295",295,null,"div by 392",392]
["div by 296",296,null,"div by 394",394]
["div by 297",297,null,"div by 396",396]
["div by 298",298,null,"div by 398",398]
["div by 299",299,null,"div by 400",400]
["div by 300",300,null,"div by 402",402]
["div by 301",301,null,"div by 404",404]
["div by 302",302,null,"div by 406",406]
["div by 303",303,null,"div by 408",408]
["div by 304",304,null,"div by 410",410]
["div by 305",305,null,"div by 412",412]
["div by 306",306,null,"div by 414",414]
["div by 307",307,null,"div by 416",416]
["div by 308",308,null,"div by 418",418]
["div by 309",309,null,"div by 420",420]
["div by 310",310,null,"div by 422",422]
["div by 311",311,null,"div by 424",424]
["div by 312",312,null,"div by 426",426]
["div by 313",313,null,"div by 428",428]
["div by 314",314,null,"div by 430",430]
["div by 315",315,null,"div by 432",432]
["div by 316",316,null,"div by 434",434]
["div by 317",317,null,"div by 436",436]
["div by 318",318,null,"div by 438",438]
["div by 319",319,null,"div by 440",440]
["div by 320",320,null,"div by 442",442]
["div by 321",321,null,"div by 444",444]
[{"$f":"\"div by \"&B328","v":"div by 322"},322,null,"div by 446",446]
["div by 323",323,null,"div by 448",448]
["div by 324",324,null,"div by 450",450]
["div by 325",325,null,"div by 452",452]
["div by 326",326,null,"div by 454",454]
["div by 327",327,null,"div by 456",456]
["div by 328",328,null,"div by 458",458]
["div by 329",329,null,"div by 460",460]
["div by 330",330,null,"div by 462",462]
["div by 331",331,null,"div by 464",464]
["div by 332",332,null,"div by 466",466]
["div by 333",333,null,"div by 468",468]
["div by 334",334,null,"div by 470",470]
["div by 335",335,null,"div by 472",472]
["div by 336",336,null,"div by 474",474]
["div by 337",337,null,"div by 476",476]
["div by 338",338,null,"div by 478",478]
["div by 339",339,null,"div by 480",480]
["div by 340",340,null,"div by 482",482]
["div by 341",341,null,"div by 484",484]
["div by 342",342,null,"div by 486",486]
["div by 343",343,null,"div by 488",488]
["div by 344",344,null,"div by 490",490]
["div by 345",345,null,"div by 492",492]
["div by 346",346,null,"div by 494",494]
["div by 347",347,null,"div by 496",496]
["div by 348",348,null,"div by 498",498]
["div by 349",349,null,"div by 500",500]
["div by 350",350,null,"div by 502",502]
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["div by 352",352,null,"div by 506",506]
["div by 353",353,null,"div by 508",508]
["div by 354",354,null,"div by 510",510]
["div by 355",355]
["div by 356",356]
["div by 357",357]
["div by 358",358]
["div by 359",359]
["div by 360",360]
["div by 361",361]
["div by 362",362]
["div by 363",363]
["div by 364",364]
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[]
[{"$f":"\"/ 1\"","v":"/ 1"},0]
[{"$f":"\"/ 10\"","v":"/ 10"},1]
[{"$f":"\"/ 100\"","v":"/ 100"},2]
[{"$f":"\"/ 1000\"","v":"/ 1000"},3]

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[]
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[null,null,null,null,"min","max","min","max","min","max","min","max","min","max","min","max","min","max"]
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[]
[null,null,null,null,null,null,null,null,null,null,null,"closest"]
[]
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[null,null,null,null,null,null,null,null,null,null,null,"aux sel 4",{"$f":"Sheet2!D67","v":2}]
[null,"Fin",{"$f":"IF(M8=1,16,osc)","v":40},null,"closest",240]
[null,"Fsys",{"$f":"pll_0","v":240},null,"closest int",240]
[]
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