/*
 * File: adc_dma_bctu.c
 *
 * Code generated for Simulink model 'adc_dma_bctu'.
 *
 * Model version                   : 4.44
 * Simulink Coder version          : 24.1 (R2024a) 19-Nov-2023
 * MBDT for S32K3 Series Version  :  Version 1.8.0 (R2023b-R2025b) 11-Dec-2025
 * C/C++ source code generated on  : Thu Mar 12 15:19:47 2026
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: ARM Compatible->ARM Cortex
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "adc_dma_bctu_private.h"
#include "rtwtypes.h"
#include "CDD_Mcl.h"
#include "adc_dma_bctu.h"

/* Storage class 'noCacheable' */
#define ADC_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
#include "Adc_MemMap.h"

uint16_T Adc1G0_ResBuff;               /* '<S2>/ResultBuffer' */

#define ADC_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
#include "Adc_MemMap.h"

/* Exported data definition */

/* Volatile memory section */
/* Definition for custom storage class: Volatile */
volatile uint16_T ADC_BCTU_Result;     /* '<Root>/Data Store Memory6' */
volatile uint16_T ADC_POT0;            /* '<Root>/Data Store Memory2' */
volatile uint8_T ActiveId_Instance;    /* '<Root>/Data Store Memory13' */
volatile boolean_T Active_Channel;     /* '<Root>/Data Store Memory18' */
volatile boolean_T Active_Instance;    /* '<Root>/Data Store Memory14' */
volatile uint32_T Adc0_ReadStatus;     /* '<Root>/Data Store Memory7' */
volatile uint32_T Adc1_BufReadStatus;  /* '<Root>/Data Store Memory4' */
volatile uint16_T Adc1_ChansArray;     /* '<Root>/Data Store Memory20' */
volatile uint32_T Adc1_ReadStatus;     /* '<Root>/Data Store Memory3' */
volatile boolean_T Bctu_NDataFlag;     /* '<Root>/Data Store Memory10' */
volatile boolean_T Bctu_OvrDataFlag;   /* '<Root>/Data Store Memory11' */
volatile boolean_T Bctu_TriggerFlag;   /* '<Root>/Data Store Memory9' */
volatile uint8_T Calibration_ADC1_Status;/* '<Root>/Data Store Memory8' */
volatile Mcl_DmaChannelStateType ChannelState;/* '<Root>/Data Store Memory16' */
volatile boolean_T Done_Channel;       /* '<Root>/Data Store Memory19' */
volatile uint32_T Error_Channel;       /* '<Root>/Data Store Memory17' */
volatile uint32_T Errors_Instance;     /* '<Root>/Data Store Memory12' */
volatile uint32_T GroupStatus;         /* '<Root>/Data Store Memory1' */
volatile uint8_T Version_Instance;     /* '<Root>/Data Store Memory15' */

/* Block signals (default storage) */
B_adc_dma_bctu_T adc_dma_bctu_B;

/* Real-time model */
static RT_MODEL_adc_dma_bctu_T adc_dma_bctu_M_;
RT_MODEL_adc_dma_bctu_T *const adc_dma_bctu_M = &adc_dma_bctu_M_;
static void rate_monotonic_scheduler(void);
static void init_freemaster_lpuart(void)
{
  LPUART_Type * const uart_base = Lpuart_apBases[13];
  Lpuart_Uart_Ip_Hw_Init(uart_base);
  LPUART_Uart_SetBaudRate(13, 115200U);

  /* Set 8 bit counts per char */
  Lpuart_Uart_Ip_SetBitCountPerChar(uart_base, LPUART_UART_IP_8_BITS_PER_CHAR,
    FALSE);

  /* Set no parity mode */
  Lpuart_Uart_Ip_SetParityMode(uart_base, LPUART_UART_IP_PARITY_DISABLED);

  /* One stop bit */
  Lpuart_Uart_Ip_SetStopBitCount(uart_base, LPUART_UART_IP_ONE_STOP_BIT);
  sys_disableIsrSource(Lpuart_RxTxIrqId[13]);
  sys_registerIsrHandler(Lpuart_RxTxIrqId[13], &FMSTR_SerialIsr);
  sys_enableIsrSource(Lpuart_RxTxIrqId[13], 0U);
}

void Adc_Adc1Group0_Callback (void)
{
  /* Output and update for function-call system: '<Root>/Triggered Subsystem' */

  /* S-Function (s32k3_adc): '<S3>/Adc1' */
  adc_dma_bctu_B.Adc1G0_Read = Adc_ReadGroup(Adc1Group_0,
    &adc_dma_bctu_B.Adc1G0_Read_j);

  /* DataStoreWrite: '<S3>/Data Store Write' */
  Adc1_ReadStatus = adc_dma_bctu_B.Adc1G0_Read;

  /* DataStoreWrite: '<S3>/Data Store Write10' */
  ADC_POT0 = adc_dma_bctu_B.Adc1G0_Read_j;

  /* S-Function (s32k3_mcl): '<S3>/Mcl' */
  Mcl_GetDmaChannelStatus(DMA_LOGIC_CH_0, &adc_dma_bctu_B.Mcl);

  /* DataStoreWrite: '<S3>/Data Store Write6' */
  Error_Channel = adc_dma_bctu_B.Mcl.Errors;

  /* DataStoreWrite: '<S3>/Data Store Write7' */
  Done_Channel = adc_dma_bctu_B.Mcl.Done;

  /* DataStoreWrite: '<S3>/Data Store Write8' */
  Active_Channel = adc_dma_bctu_B.Mcl.Active;

  /* DataStoreWrite: '<S3>/Data Store Write9' */
  ChannelState = adc_dma_bctu_B.Mcl.ChannelState;

  /* S-Function (s32k3_dio): '<S3>/Dio' */
  adc_dma_bctu_B.Dio = Dio_FlipChannel(DioConf_DioChannel_RGBLED0_GREEN);

  /* S-Function (s32k3_mcl): '<S3>/Mcl2' */
  Mcl_SetDmaChannelCommand(DMA_LOGIC_CH_0, MCL_DMA_CH_ACK_DONE);
}

/*
 * Set which subrates need to run this base step (base rate always runs).
 * This function must be called prior to calling the model step function
 * in order to remember which rates need to run this base step.  The
 * buffering of events allows for overlapping preemption.
 */
void adc_dma_bctu_SetEventsForThisBaseStep(boolean_T *eventFlags)
{
  /* Task runs when its counter is zero, computed via rtmStepTask macro */
  eventFlags[1] = ((boolean_T)rtmStepTask(adc_dma_bctu_M, 1));
}

/*
 *         This function updates active task flag for each subrate
 *         and rate transition flags for tasks that exchange data.
 *         The function assumes rate-monotonic multitasking scheduler.
 *         The function must be called at model base rate so that
 *         the generated code self-manages all its subrates and rate
 *         transition flags.
 */
static void rate_monotonic_scheduler(void)
{
  /* Compute which subrates run during the next base time step.  Subrates
   * are an integer multiple of the base rate counter.  Therefore, the subtask
   * counter is reset when it reaches its limit (zero means run).
   */
  (adc_dma_bctu_M->Timing.TaskCounters.TID[1])++;
  if ((adc_dma_bctu_M->Timing.TaskCounters.TID[1]) > 9) {/* Sample time: [0.01s, 0.0s] */
    adc_dma_bctu_M->Timing.TaskCounters.TID[1] = 0;
  }
}

/* Model step function for TID0 */
void adc_dma_bctu_step0(void)          /* Sample time: [0.001s, 0.0s] */
{
  {                                    /* Sample time: [0.001s, 0.0s] */
    rate_monotonic_scheduler();
  }
}

/* Model step function for TID1 */
void adc_dma_bctu_step1(void)          /* Sample time: [0.01s, 0.0s] */
{
  /* End of Outputs for S-Function (s32k3_isr_handler): '<Root>/Hardware_Interrupt_Handler' */

  /* Outputs for Atomic SubSystem: '<Root>/10ms' */
  /* S-Function (s32k3_adc): '<S1>/Adc2' */
  Adc_StartGroupConversion(Adc1Group_0);

  /* S-Function (s32k3_adc): '<S1>/Adc1' */
  adc_dma_bctu_B.Adc1 = Adc_GetGroupStatus(Adc1Group_0);

  /* DataStoreWrite: '<S1>/Data Store Write' */
  GroupStatus = adc_dma_bctu_B.Adc1;

  /* End of Outputs for SubSystem: '<Root>/10ms' */
}

/* Model initialize function */
void adc_dma_bctu_initialize(void)
{
  {
    uint16_T Adc1_Group0_ResoultBuffer;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory10' */
    Bctu_NDataFlag = adc_dma_bctu_P.DataStoreMemory10_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory11' */
    Bctu_OvrDataFlag = adc_dma_bctu_P.DataStoreMemory11_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory12' */
    Errors_Instance = adc_dma_bctu_P.DataStoreMemory12_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory13' */
    ActiveId_Instance = adc_dma_bctu_P.DataStoreMemory13_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory14' */
    Active_Instance = adc_dma_bctu_P.DataStoreMemory14_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory15' */
    Version_Instance = adc_dma_bctu_P.DataStoreMemory15_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory20' */
    Adc1_ChansArray = adc_dma_bctu_P.DataStoreMemory20_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory6' */
    ADC_BCTU_Result = adc_dma_bctu_P.DataStoreMemory6_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory7' */
    Adc0_ReadStatus = adc_dma_bctu_P.DataStoreMemory7_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory8' */
    Calibration_ADC1_Status = adc_dma_bctu_P.DataStoreMemory8_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory9' */
    Bctu_TriggerFlag = adc_dma_bctu_P.DataStoreMemory9_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory1' */
    GroupStatus = adc_dma_bctu_P.DataStoreMemory1_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory16' */
    ChannelState = adc_dma_bctu_P.DataStoreMemory16_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory17' */
    Error_Channel = adc_dma_bctu_P.DataStoreMemory17_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory18' */
    Active_Channel = adc_dma_bctu_P.DataStoreMemory18_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory19' */
    Done_Channel = adc_dma_bctu_P.DataStoreMemory19_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory2' */
    ADC_POT0 = adc_dma_bctu_P.DataStoreMemory2_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory3' */
    Adc1_ReadStatus = adc_dma_bctu_P.DataStoreMemory3_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory' */
    Adc1_Group0_ResoultBuffer = adc_dma_bctu_P.DataStoreMemory_InitialValue;

    /* Start for DataStoreMemory: '<Root>/Data Store Memory4' */
    Adc1_BufReadStatus = adc_dma_bctu_P.DataStoreMemory4_InitialValue;

    /* End of SystemInitialize for S-Function (s32k3_isr_handler): '<Root>/Hardware_Interrupt_Handler' */
    /* Start for S-Function (s32k3_fm_config): '<S2>/FreeMASTER Config' */
    init_freemaster_lpuart();
    FMSTR_Init();

    /* End of SystemInitialize for SubSystem: '<Root>/Initialize Function' */

    /* Outputs for Atomic SubSystem: '<Root>/Initialize Function' */
    /* DataStoreRead: '<S2>/ResultBuffer' */
    Adc1G0_ResBuff = Adc1_Group0_ResoultBuffer;

    /* S-Function (s32k3_adc): '<S2>/Adc' */
    adc_dma_bctu_B.Adc = Adc_SetupResultBuffer(Adc1Group_0, &Adc1G0_ResBuff);
    Adc1Group_0_ResultBufferPtr = &Adc1G0_ResBuff;
    Adc1Group_0_ResultBufferLength = 1;

    /* DataStoreWrite: '<S2>/Data Store Write' */
    Adc1_BufReadStatus = adc_dma_bctu_B.Adc;

    /* S-Function (s32k3_adc): '<S2>/Adc1' */
    Adc_EnableGroupNotification(Adc1Group_0);
  }
}

/* Model terminate function */
void adc_dma_bctu_terminate(void)
{
  /* (no terminate code required) */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
