[14-2-2022 08:59:55] Executing Server: "C:\Program Files (x86)\SEGGER\JLink\JLinkGDBServerCL.exe" -nosilent -swoport 2332 -select USB=601002459 -jlinkscriptfile C:\Users\user\Documents\MCUXpressoIDE_11.2.1_4149\workspace_20220208_boot\.mcuxpressoide_packages_support\MIMXRT1062xxxxA_support/Script/evkmimxrt1060_sdram_init.jlinkscript -telnetport 2333 -singlerun -endian little -noir -speed auto   -port 2331    -vd -device MIMXRT1062xxx6A -if SWD -halt -reportuseraction
SEGGER J-Link GDB Server V7.54b Command Line Version

JLinkARM.dll V7.54b (DLL compiled Sep 14 2021 16:07:10)

Command line: -nosilent -swoport 2332 -select USB=601002459 -jlinkscriptfile C:\Users\user\Documents\MCUXpressoIDE_11.2.1_4149\workspace_20220208_boot\.mcuxpressoide_packages_support\MIMXRT1062xxxxA_support/Script/evkmimxrt1060_sdram_init.jlinkscript -telnetport 2333 -singlerun -endian little -noir -speed auto -port 2331 -vd -device MIMXRT1062xxx6A -if SWD -halt -reportuseraction
-----GDB Server start settings-----
GDBInit file:                  none
GDB Server Listening port:     2331
SWO raw output listening port: 2332
Terminal I/O port:             2333
Accept remote connection:      localhost only
Generate logfile:              off
Verify download:               on
Init regs on start:            off
Silent mode:                   off
Single run mode:               on
Target connection timeout:     0 ms
------J-Link related settings------
J-Link Host interface:         USB
J-Link script:                 C:\Users\user\Documents\MCUXpressoIDE_11.2.1_4149\workspace_20220208_boot\.mcuxpressoide_packages_support\MIMXRT1062xxxxA_support/Script/evkmimxrt1060_sdram_init.jlinkscript
J-Link settings file:          none
------Target related settings------
Target device:                 MIMXRT1062xxx6A
Target interface:              SWD
Target interface speed:        auto
Target endian:                 little

Connecting to J-Link...
J-Link is connected.
Device "MIMXRT1062XXX6A" selected.
Firmware: J-Link V11 compiled Nov  2 2021 11:11:52
Hardware: V11.00
S/N: 601002459
Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
Checking target voltage...
Target voltage: 3.27 V
Listening on TCP/IP port 2331
Connecting to target...
ConfigTargetSettings() start
Config JTAG Speed to 4000kHz
ConfigTargetSettings() end
InitTarget() start
InitTarget()
_TargetHalt: CPU halted
InitTarget() end
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
[0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
[1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
[2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[2][1]: E0001000 CID B105E00D PID 000BB002 DWT
[2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[2][3]: E0000000 CID B105E00D PID 000BB001 ITM
[1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[1][2]: E0042000 CID B105900D PID 004BB906 CTI
[0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
[0][2]: E0043000 CID B105F00D PID 001BB101 TSG
Cache: Separate I- and D-cache.

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
SetupTarget() start
Enabling i.MXRT SDRAM
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
SetupTarget() end
ConfigTargetSettings() start
Config JTAG Speed to 4000kHz
ConfigTargetSettings() end
InitTarget() start
InitTarget()
_TargetHalt: CPU halted
InitTarget() end
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
[0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
[1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
[2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
[2][1]: E0001000 CID B105E00D PID 000BB002 DWT
[2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
[2][3]: E0000000 CID B105E00D PID 000BB001 ITM
[1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
[1][2]: E0042000 CID B105900D PID 004BB906 CTI
[0][1]: E0040000 CID B105900D PID 000BB9A9 TPIU-M7
[0][2]: E0043000 CID B105F00D PID 001BB101 TSG
Cache: Separate I- and D-cache.

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
SetupTarget() start
Enabling i.MXRT SDRAM
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
SetupTarget() end
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x0020E362 (Data = 0xF8C0400E)
Read 2 bytes @ address 0x0020E362 (Data = 0x400E)
Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x0020E362 (Data = 0xF8C0400E)
Read 2 bytes @ address 0x0020E362 (Data = 0x400E)
Received monitor command: reset
ResetTarget() start
Core did not halt after reset.
Halting target manually.
ResetTarget() end
AfterResetTarget() start
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
AfterResetTarget() end
Resetting target
Downloading 8192 bytes @ address 0x60000000 - Verified OK
Downloading 16048 bytes @ address 0x60002000 - Verified OK
Downloading 16016 bytes @ address 0x60005EB0 - Verified OK
Downloading 16112 bytes @ address 0x60009D40 - Verified OK
Downloading 16032 bytes @ address 0x6000DC30 - Verified OK
Downloading 16144 bytes @ address 0x60011AD0 - Verified OK
Downloading 15984 bytes @ address 0x600159E0 - Verified OK
Downloading 16032 bytes @ address 0x60019850 - Verified OK
Downloading 16016 bytes @ address 0x6001D6F0 - Verified OK
Downloading 16208 bytes @ address 0x60021580 - Verified OK
Downloading 16176 bytes @ address 0x600254D0 - Verified OK
Downloading 16224 bytes @ address 0x60029400 - Verified OK
Downloading 16208 bytes @ address 0x6002D360 - Verified OK
Downloading 9360 bytes @ address 0x600312B0 - Verified OK
Downloading 6840 bytes @ address 0x60033740 - Verified OK
Downloading 728 bytes @ address 0x600351F8 - Verified OK
J-Link: Flash download: Bank 0 @ 0x60000000: Skipped. Contents already match
Writing register (PC = 0x6000231c)
Read 4 bytes @ address 0x6000231C (Data = 0x4B09B672)
Reading 64 bytes @ address 0x6000C580
Read 2 bytes @ address 0x6000C5AE (Data = 0x2301)
Reading 64 bytes @ address 0x60002300
Read 2 bytes @ address 0x6000231C (Data = 0xB672)
Read 2 bytes @ address 0x6000C5C6 (Data = 0xF009)
Read 2 bytes @ address 0x6000C5AE (Data = 0x2301)
Read 2 bytes @ address 0x6000231C (Data = 0xB672)
Read 2 bytes @ address 0x6000C5C6 (Data = 0xF009)
Reading all registers
Read 4 bytes @ address 0x6000231C (Data = 0x4B09B672)
Read 2 bytes @ address 0x6000C5AE (Data = 0x2301)
Received monitor command: semihosting enable
Semi-hosting enabled (Handle on BKPT)
Received monitor command: exec SetRestartOnClose=1
Executed SetRestartOnClose=1
Received monitor command: reset
ResetTarget() start
Core did not halt after reset.
Halting target manually.
ResetTarget() end
AfterResetTarget() start
FlexRAM configuration is restored
DCDC trim value loaded.
Clock Init Done
SDRAM Init Done
AfterResetTarget() end
Resetting target
Setting breakpoint @ address 0x6000231C, Size = 2, BPHandle = 0x0001
Setting breakpoint @ address 0x6000C5AE, Size = 2, BPHandle = 0x0002
Setting breakpoint @ address 0x6000C5C6, Size = 2, BPHandle = 0x0003
Starting target CPU...