// ******************************************************** // This is for testing the "Match Continuous Mode" // Use a square <30kHz wave as input // timers are not in any logical order, this is just how it was configured when I got it to work // Once this is configured, you just need an input source, and a logic analyzer or scope to see // something happen. There is no software intervention at all. int Flex1_Sync_config(void) { // setup flex clock for i.MXRT1062 // note that the clock setup is device specific CCM_CCGR5 |= CCM_CCGR5_FLEXIO1(CCM_CCGR_OFF); // disable clock CCM_CDCDR &= ~( CCM_CDCDR_FLEXIO1_CLK_PODF( 7 ) ); // clear flex clock bits CCM_CDCDR |= CCM_CDCDR_FLEXIO1_CLK_PODF( 5 ); // set flex clock = 40MHz // clock speed = 480MHz/2/(N+1) CCM_CCGR5 |= CCM_CCGR5_FLEXIO1(CCM_CCGR_ON); // enable clock // if the Flex module gets hung up, reconfiguring will not fix it, you will // need to reset it. Flex module should be disabled during configuration or // else you will likely get "random" output transitions during config. // Reset and disable FLEXIO1 (clock MUST be enabled or this will hang) FLEXIO1_CTRL |= 2; // reset Flex module FLEXIO1_CTRL &= 0xfffffffc; // release reset and leave Flex disabled // route IO pins to FlexIO 1 // input bit stream IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4; // FLEXIO pin4 Teensy pin 2 // Timer 0,1,2 outputs IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 4; // FLEXIO pin5 Teensy pin 3 IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 4; // FLEXIO pin6 Teensy pin 4 IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 4; // FLEXIO pin7 Teensy pin 33 IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 4; // FLEXIO pin8 Teensy pin 5 #define SHIFTER3_IN 4 // Teensy pin 2 match input #define TIMER1_OUT 6 // Teensy pin 4 for debug only #define TIMER2_OUT 8 // Teensy pin 5 for debug only #define TIMER4_OUT 5 // Teensy pin 3 reset for Timer3 #define TIMER7_OUT 7 // Teensy pin 33 for debug only // setup flex timer 1 ***************************************************** // this is here so that we can see something happen if we get a trigger from Shifter3 // produces a 1MHz clock // it is clocked from from the FLEXIO clock // it is enabled by an output from Shifter3 status flag FLEXIO1_TIMCTL1 = FLEXIO_TIMCTL_TRGSEL( 13 ) | // Shifter3 status flag =(3 * 4) + 1 //FLEXIO_TIMCTL_TRGPOL | // trigger active high FLEXIO_TIMCTL_TRGSRC | // internal trigger FLEXIO_TIMCTL_PINCFG( 3 ) | // timer pin output enabled FLEXIO_TIMCTL_PINSEL(TIMER1_OUT) | // timer pin 6 (for debug only) // FLEXIO_TIMCTL_PINPOL | // timer pin active high FLEXIO_TIMCTL_TIMOD( 1 ); // dual counter/baud mode FLEXIO1_TIMCFG1 = FLEXIO_TIMCFG_TIMOUT( 0 ) | // timer output = logic high when enabled, not affcted by reset FLEXIO_TIMCFG_TIMDEC( 0 ) | // decrement on FlexIO clock, shift clock = timer output FLEXIO_TIMCFG_TIMRST( 0 ) | // dont reset timer FLEXIO_TIMCFG_TIMDIS( 2 ) | // disable timer on timer compare FLEXIO_TIMCFG_TIMENA( 6 ) | // enable timer on trigger rising FLEXIO_TIMCFG_TSTOP( 0 ) ; // stop bit disabled // FLEXIO_TIMCFG_TSTART // start bit disabled // TBD // 22 shifts, divide clock by 40 ((n*2-1)<<8) | (baudrate_divider/2-1)) // (22*2-1)<<8 | (40/2-1) // (43)<<8 | (19) // 0x2b00 | 0x13 FLEXIO1_TIMCMP1 = 0x2b13; // setup flex timer 2 ***************************************************** // this is a 5MHz shift clock for shifter 3 // it is clocked from from the FLEXIO clock // it is always enabled FLEXIO1_TIMCTL2 = FLEXIO_TIMCTL_TRGSEL( 0 ) | // trigger not used //FLEXIO_TIMCTL_TRGPOL | // trigger not used FLEXIO_TIMCTL_TRGSRC | // internal trigger FLEXIO_TIMCTL_PINCFG( 3 ) | // timer pin output enabled FLEXIO_TIMCTL_PINSEL(TIMER2_OUT) | // timer pin 8 (for debug only) // FLEXIO_TIMCTL_PINPOL | // timer pin active high FLEXIO_TIMCTL_TIMOD( 3 ); // 16-bit timer mode FLEXIO1_TIMCFG2 = FLEXIO_TIMCFG_TIMOUT( 0 ) | // timer output = logic high when enabled, not affcted by reset FLEXIO_TIMCFG_TIMDEC( 0 ) | // decrement on FlexIO clock, shift clock = timer output FLEXIO_TIMCFG_TIMRST( 0 ) | // dont reset timer FLEXIO_TIMCFG_TIMDIS( 0 ) | // never disable FLEXIO_TIMCFG_TIMENA( 0 ) | // timer is always enabled FLEXIO_TIMCFG_TSTOP( 0 ) ; // stop bit disabled // FLEXIO_TIMCFG_TSTART // start bit disabled // Flex clock = 40MHz, we want 5MHz, so divide by 8 // TIMCMP = divider/2-1 = 8/2-1 = 3 FLEXIO1_TIMCMP2 = 0x0003U; // setup flex timer 3 ***************************************************** // this is the shift counter for Shifter3 // the shift clock is passed thru from Timer2 // it is clocked from from Timer2 // it is always enabled // it is reset by Timer4 FLEXIO1_TIMCTL3 = FLEXIO_TIMCTL_TRGSEL( 11 ) | // trigger on Timer2 out (2 * 4)+3 //FLEXIO_TIMCTL_TRGPOL | // trigger active high FLEXIO_TIMCTL_TRGSRC | // internal trigger FLEXIO_TIMCTL_PINCFG( 0 ) | // timer pin output disabled FLEXIO_TIMCTL_PINSEL(TIMER4_OUT) | // timer pin 5 (used as Reset input) // FLEXIO_TIMCTL_PINPOL | // timer pin active high FLEXIO_TIMCTL_TIMOD( 3 ); // 16-bit timer mode FLEXIO1_TIMCFG3 = FLEXIO_TIMCFG_TIMOUT( 0 ) | // timer output = logic high when enabled, not affcted by reset FLEXIO_TIMCFG_TIMDEC( 3 ) | // decrement on Trig, shift clock = Trig FLEXIO_TIMCFG_TIMRST( 4 ) | // reset timer on pin rising edge FLEXIO_TIMCFG_TIMDIS( 0 ) | // timer never disables FLEXIO_TIMCFG_TIMENA( 0 ) | // timer is always enabled FLEXIO_TIMCFG_TSTOP( 0 ) ; // stop bit disabled // FLEXIO_TIMCFG_TSTART // start bit disabled // 102 shifts (n*2-1) // (102*2-1) // (204) FLEXIO1_TIMCMP3 = 203; // this would normally timeout and stop after 102 shifts, however it will be reset by Timer4 // after 100 shifts, so the timeout never happens // setup flex timer 4 ***************************************************** // this is an an extra timer that produces a reset to Timer3 // it is clocked from from FlexIO // it is always enabled FLEXIO1_TIMCTL4 = FLEXIO_TIMCTL_TRGSEL( 0 ) | // trigger not used //FLEXIO_TIMCTL_TRGPOL | // trigger not used FLEXIO_TIMCTL_TRGSRC | // internal trigger FLEXIO_TIMCTL_PINCFG( 3 ) | // timer pin output enabled FLEXIO_TIMCTL_PINSEL(TIMER4_OUT) | // timer pin 5 (resets Timer3) // FLEXIO_TIMCTL_PINPOL | // timer pin active high FLEXIO_TIMCTL_TIMOD( 3 ); // 16-bit counter mode FLEXIO1_TIMCFG4 = FLEXIO_TIMCFG_TIMOUT( 0 ) | // timer output = logic high when enabled, not affcted by reset FLEXIO_TIMCFG_TIMDEC( 0 ) | // decrement on FlexIO clock, shift clock = timer output FLEXIO_TIMCFG_TIMRST( 0 ) | // dont reset timer FLEXIO_TIMCFG_TIMDIS( 0 ) | // never disable FLEXIO_TIMCFG_TIMENA( 0 ) | // timer is always enabled FLEXIO_TIMCFG_TSTOP( 0 ) ; // stop bit disabled // 50 shifts * 8 flex clocks (n-1) // (400-1) // (399) // 0x018F FLEXIO1_TIMCMP4 = 0x18F; // output toggles after 50 shifts, but reset is on rising edge only, so reset is every 100 shifts // setup flex timer 7 ***************************************************** // for debug only // this basically passes the trigger thru to an IO pin for debug // it is always enabled FLEXIO1_TIMCTL7 = FLEXIO_TIMCTL_TRGSEL( 13 ) | // Shifter3 status flag =(3 * 4) + 1 //FLEXIO_TIMCTL_TRGPOL | // trigger active high FLEXIO_TIMCTL_TRGSRC | // internal trigger FLEXIO_TIMCTL_PINCFG( 3 ) | // timer pin output enabled FLEXIO_TIMCTL_PINSEL(TIMER7_OUT) | // timer pin 7 (for debug only) // FLEXIO_TIMCTL_PINPOL | // timer pin active high FLEXIO_TIMCTL_TIMOD( 3 ); // 16-bit timer mode FLEXIO1_TIMCFG7 = FLEXIO_TIMCFG_TIMOUT( 1 ) | // timer output = logic low when enabled, not affcted by reset FLEXIO_TIMCFG_TIMDEC( 3 ) | // decrement on Trigger input (both edges), Shift clock equals Trigger input. FLEXIO_TIMCFG_TIMRST( 0 ) | // dont reset timer FLEXIO_TIMCFG_TIMDIS( 0 ) | // never disable FLEXIO_TIMCFG_TIMENA( 0 ) | // timer is always enabled FLEXIO_TIMCFG_TSTOP( 0 ) ; // stop bit disabled // FLEXIO_TIMCFG_TSTART // start bit disabled FLEXIO1_TIMCMP7 = 0; // times out on first clock after trigger // setup data shifter 3 ************************************************** // This shifter is configured in Match Continuous Mode // It watches for the sync pattern at the start of the 1553 transmission // and when found, triggers the data capture FLEXIO1_SHIFTCTL3 = FLEXIO_SHIFTCTL_TIMSEL( 3 ) | // clocked from timer 3 FLEXIO_SHIFTCTL_TIMPOL | // shift on neg edge FLEXIO_SHIFTCTL_PINCFG( 0 ) | // pin output disabled FLEXIO_SHIFTCTL_PINSEL(SHIFTER3_IN) | // FLEXIO pin 4 Teensy pin 2 (Input data stream) // FLEXIO_SHIFTCTL_PINPOL | // active high FLEXIO_SHIFTCTL_SMOD( 5 ); // match continuous mode FLEXIO1_SHIFTCFG3 = FLEXIO_SHIFTCFG_PWIDTH( 0 ) | // single bit width // FLEXIO_SHIFTCFG_INSRC | // from pin FLEXIO_SHIFTCFG_SSTOP( 0 ) | // stop bit disabled FLEXIO_SHIFTCFG_SSTART( 0 ); // start bit disabled FLEXIO1_SHIFTBUF3 = 0xff000000U; // pattern triggers on a glitch free rising edge //FLEXIO1_SHIFTBUF3 = 0x00ff0000U; // pattern triggers on a glitch free falling edge // enable FLEXIO3 FLEXIO1_CTRL |= 1; // enable FLEXIO3 module return( 0 ); }