diff --git a/board/board.c b/board/board.c
index a107b4e..487f06a 100644
--- a/board/board.c
+++ b/board/board.c
@@ -384,3 +384,98 @@ void BOARD_ConfigMPU(void) {
   SCB_EnableDCache();
   SCB_EnableICache();
 }
+
+/*
+ * JEDEC reset of external serial flash in three steps:
+ * 1) Disable interrupts and the data cache
+ * 2) Do the JEDEC reset sequence
+ * 3) Issue the NVIC_SystemReset() to do the actual reset
+ *
+ * Note: This function must be executing in RAM.
+ * Note: The NVIC_SystemReset() call may take up to 3s to complete
+ *       depending on compiler and Debug/Release build
+ * Note: Function call only valid for targets running in/from
+ *       flash - not for targets running in debugger and/or in RAM
+ */
+RAMFUNCTION_SECTION_CODE(void software_reset(void)) {
+#define CS (1 << 6)
+#define SCK (1 << 7)
+#define SI (1 << 8)
+#define RESETMASK (CS | SCK | SI)
+#define IGNOREPINS                                                             \
+  ((1 << 9) | (1 << 10) | (1 << 11) | (1 << 1) | (1 << 2) | (1 << 3))
+#define LOW(__mask) GPIO3->DR &= ~(__mask) /* Set pin output to low level.*/
+#define HIGH(__mask) GPIO3->DR |= (__mask) /* Set pin output to high level.*/
+
+  __disable_irq();
+  SCB_DisableDCache();
+
+  /* Configure CS/SCK/SI as outputs and the other flexspi pins as inputs */
+  CLOCK_EnableClock(kCLOCK_Gpio3);
+  GPIO3->IMR &= ~(RESETMASK | IGNOREPINS);
+  GPIO3->GDIR |= (RESETMASK);
+  GPIO3->GDIR &= ~(IGNOREPINS);
+
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_GPIO3_IO06, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_GPIO3_IO07, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_GPIO3_IO08, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_GPIO3_IO09, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_GPIO3_IO10, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_GPIO3_IO11, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO01, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, 0);
+  IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, 0);
+
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_GPIO3_IO06, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_GPIO3_IO07, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_GPIO3_IO08, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_GPIO3_IO09, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_GPIO3_IO10, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_GPIO3_IO11, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_GPIO3_IO01, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, 0x10b0);
+  IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, 0x10b0);
+
+  /* Reset sequence */
+  HIGH(CS);
+  LOW(SCK | SI);
+
+  LOW(CS);
+  HIGH(CS);
+  HIGH(SI);
+
+  LOW(CS);
+  HIGH(CS);
+  LOW(SI);
+
+  LOW(CS);
+  HIGH(CS);
+  HIGH(SI);
+
+  LOW(CS);
+  HIGH(CS);
+
+  /* Delay at least 110us */
+  for (int i = 33000; i >= 0; i--) {
+    __NOP();
+  }
+
+  /* Actual reset. This code is copied from NVIC_SystemReset() in core_cm7.h
+     and must be copied here as MCUXpresso IDE (only for the Debug target)
+     will keep the function in serial flash even if it is 'static inline'
+     and called from a function placed in RAM and since we have resetted
+     the serial flash using it results in a crash and not a reset. Manually
+     copying the code seems to do the trick. */
+  __DSB(); /* Ensure all outstanding memory accesses included
+              buffered write are completed before reset */
+  SCB->AIRCR =
+      (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+  __DSB(); /* Ensure completion of memory access */
+
+  for (;;) /* wait until reset */
+  {
+    __NOP();
+  }
+}
diff --git a/board/board.h b/board/board.h
index 10e7876..bdc0062 100644
--- a/board/board.h
+++ b/board/board.h
@@ -17,7 +17,7 @@
  * Definitions
  ******************************************************************************/
 /*! @brief The board name */
-#define BOARD_NAME "MIMXRT1060-EVK"
+#define BOARD_NAME "EA-IMXRT1062"
 
 /* The UART to use for debug messages. */
 #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
@@ -228,6 +228,7 @@ status_t BOARD_Camera_I2C_ReceiveSCCB(uint8_t deviceAddress,
 void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
 void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
 
+void software_reset(void);
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
diff --git a/board/clock_config.c b/board/clock_config.c
index e4f9d41..97a1451 100644
--- a/board/clock_config.c
+++ b/board/clock_config.c
@@ -71,8 +71,8 @@ outputs:
 - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
-- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
-- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 120 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 120 MHz}
 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
@@ -102,9 +102,9 @@ outputs:
 settings:
 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
-- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '4', locked: true}
 - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
-- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
@@ -123,7 +123,7 @@ settings:
 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
-- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '18', locked: true}
 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
@@ -196,7 +196,7 @@ void BOARD_BootClockRUN(void) {
   CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
   CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
   /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
-  DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+  DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x14);
   /* Waiting for DCDC_STS_DC_OK bit is asserted */
   while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
   }
@@ -258,14 +258,14 @@ void BOARD_BootClockRUN(void) {
   /* Disable Flexspi clock gate. */
   CLOCK_DisableClock(kCLOCK_FlexSpi);
   /* Set FLEXSPI_PODF. */
-  CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+  CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
   /* Set Flexspi clock source. */
   CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
 #endif
   /* Disable Flexspi2 clock gate. */
   CLOCK_DisableClock(kCLOCK_FlexSpi2);
   /* Set FLEXSPI2_PODF. */
-  CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+  CLOCK_SetDiv(kCLOCK_Flexspi2Div, 3);
   /* Set Flexspi2 clock source. */
   CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
   /* Disable CSI clock gate. */
@@ -411,7 +411,7 @@ void BOARD_BootClockRUN(void) {
   /* Init Usb1 PLL. */
   CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
   /* Init Usb1 pfd0. */
-  CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+  CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 18);
   /* Init Usb1 pfd1. */
   CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
   /* Init Usb1 pfd2. */
@@ -477,7 +477,12 @@ void BOARD_BootClockRUN(void) {
   /* Enable Usb2 PLL output. */
   CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
   /* Set preperiph clock source. */
-  CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+  if ((((OCOTP->CFG3) >> 16) & 0x3) == 2) {
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); /* 600MHz, for non-IT */
+  } else {
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 0); /* 528MHz, for IT */
+  }
+
   /* Set periph clock source. */
   CLOCK_SetMux(kCLOCK_PeriphMux, 0);
   /* Set periph clock2 clock source. */
@@ -532,5 +537,5 @@ void BOARD_BootClockRUN(void) {
   /* Set GPT2 High frequency reference clock source. */
   IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
   /* Set SystemCoreClock variable. */
-  SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+  SystemCoreClockUpdate();
 }
diff --git a/board/clock_config.h b/board/clock_config.h
index 6604941..94afd8c 100644
--- a/board/clock_config.h
+++ b/board/clock_config.h
@@ -59,8 +59,8 @@ void BOARD_InitBootClocks(void);
 #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
 #define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 120000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 120000000UL
 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL